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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 1777. Отображено 100.
22-03-2012 дата публикации

Substrate bonding with metal germanium silicon material

Номер: US20120068325A1
Автор: Alex P. Pamatat, Ruben B. Montez
Принадлежит: FREESCALE SEMICONDUCTOR INC

In one embodiment, a semiconductor structure including a first substrate, a semiconductor device on the first substrate, a second substrate, and a conductive bond between the first substrate and the second substrate that surrounds the semiconductor device to seal the semiconductor device between the first substrate and the second substrate. The conductive bond comprises metal, silicon, and germanium. A percentage by atomic weight of silicon in the conductive bond is greater than 5%.

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Номер записи: 1
12-04-2012 дата публикации

Package systems and manufacturing methods thereof

Номер: US20120086126A1
Автор: Chia-Pao SHU, Chun-Wen Cheng, Kuei-Sung CHANG
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A package system includes a first substrate and a second substrate. The second substrate is electrically coupled with the first substrate. The second substrate includes at least one first opening. At least one electrical bonding material is disposed between the first substrate and the second substrate. A first portion of the at least one electrical bonding material is at least partially filled in the at least one first opening.

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Номер записи: 2
12-04-2012 дата публикации

Package systems and manufacturing methods thereof

Номер: US20120086127A1
Автор: Chia-Pao SHU, Chun-Wen Cheng, Hsin-Ting HUANG, Jung-Huei Peng, Kuei-Sung CHANG, Shang-Ying Tsai
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.

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Номер записи: 3
21-06-2012 дата публикации

Semiconductor component, semiconductor wafer component, manufacturing method of semiconductor component, and manufacturing method of joining structure

Номер: US20120153461A1
Автор: Akio Furusawa, Hidetoshi Kitaura, Shigeaki Sakatani, Taichi Nakamura, Takahiro Matsuo
Принадлежит: Panasonic Corp

A semiconductor component of the present invention includes a semiconductor element and a joining layer formed on one surface of the semiconductor element and consisting of a joining material containing Bi as an essential ingredient, and projecting sections are formed on a surface of the joining layer on a side opposite to a surface in contact with the semiconductor element. By joining the semiconductor component to an electrode arranged so as to face the joining layer, the generation of a void can be suppressed.

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Номер записи: 4
12-07-2012 дата публикации

Methods for vacuum assisted underfilling

Номер: US20120178219A1
Автор: Alec J. Babiarz, Horatio Quinones, Thomas L. Ratledge
Принадлежит: Nordson Corp

Methods for applying an underfill with vacuum assistance. The method may include dispensing the underfill onto a substrate proximate to at least one exterior edge of an electronic device attached to the substrate. A space between the electronic device and the substrate is evacuated through at least one gap in the underfill. The method further includes heating the underfill to cause the underfill to flow into the space. Because a vacuum condition is supplied in the open portion of the space before flow is initiated, the incidence of underfill voiding is lowered.

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Номер записи: 5
23-08-2012 дата публикации

Semiconductor device and method for manufacturing semiconductor device

Номер: US20120211764A1
Автор: Keiji Watanabe, Keishiro Okamoto, Nobuhiro Imaizumi, Tadahiro Imada
Принадлежит: Fujitsu Ltd

A semiconductor device includes: a support base material, and a semiconductor element bonded to the support base material with a binder, the binder including: a porous metal material that contacts the support base material and the semiconductor element, and a solder that is filled in at least one part of pores of the porous metal material.

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Номер записи: 6
18-10-2012 дата публикации

Chip package and manufacturing method thereof

Номер: US20120261809A1
Автор: Kuo-Hua LIU, Tsang-Yu Liu, Yen-Shih Ho, Yu-Lin Yen, Yu-Lung Huang
Принадлежит: XinTec Inc

An embodiment of the invention provides a manufacturing method of a chip package including: providing a semiconductor wafer having a plurality of device regions separated by a plurality of scribe lines; bonding a package substrate to the semiconductor wafer wherein a spacer layer is disposed therebetween and defines a plurality of cavities respectively exposing the device regions and the spacer layer has a plurality of through holes neighboring the edge of the semiconductor wafer; filling an adhesive material in the through holes wherein the material of the spacer layer is adhesive and different from the adhesive material; and dicing the semiconductor wafer, the package substrate and the spacer layer along the scribe lines to form a plurality of chip packages separated from each other.

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Номер записи: 7
16-05-2013 дата публикации

Miniaturized Electrical Component Comprising an MEMS and an ASIC and Production Method

Номер: US20130119492A1
Автор: Anton Leidl, Gregor Feiertag, Hans Krueger, Wolfgang Pahl
Принадлежит: EPCOS AG

The invention relates to a miniaturized electrical component comprising an MEMS chip and an ASIC chip. The MEMS chip and the ASIC chip are disposed on top of each other; an internal mounting of MEMS chip and ASIC chip is connected to external electrical terminals of the electrical component by means of vias through the MEMS chip or the ASIC chip.

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Номер записи: 8
15-08-2013 дата публикации

Power Device with Solderable Front Metal

Номер: US20130207120A1
Автор: Chuan Cheah, Michael A. Briere
Принадлежит: International Rectifier Corp USA

Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.

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Номер записи: 9
22-08-2013 дата публикации

Embedded Electrical Component Surface Interconnect

Номер: US20130215583A1
Автор: Michael B. Vincent
Принадлежит: FREESCALE SEMICONDUCTOR INC

An electrical component package is disclosed comprising: an electrical component having an embedded surface, a structure attached to the electrical component opposite the embedded surface, a conductive adhesive directly attached to the embedded surface, where the conductive adhesive is shaped to taper away from the embedded surface, and an encapsulation material covering the conductive adhesive and the electrical component. In various embodiments, the tapered conductive adhesive facilitates the securing of the conductive adhesive to the electrical component by the encapsulation material. Also disclosed are various methods of forming an electrical component package having a single interface conductive interconnection on the embedded surface. The conductive interconnection is configured to maintain an interconnection while under stress forces. Further disclosed in a method of applied a conductive adhesive that enables design flexibility regarding the shape and depth of the conductive interconnection.

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Номер записи: 10
09-01-2014 дата публикации

Submicron connection layer and method for using the same to connect wafers

Номер: US20140008801A1
Автор: Kuan-Neng Chen, Yao-Jen Chang
Принадлежит: Individual

A submicron connection layer and a method for using the same to connect wafers is disclosed. The connection layer comprises a bottom metal layer formed on a connection surface of a wafer, an intermediary diffusion-buffer metal layer formed on the bottom metal layer, and a top metal layer formed on the intermediary diffusion-buffer metal layer. The melting point of the intermediary diffusion-buffer metal layer is higher than the melting points of the top and bottom metal layers. The top and bottom metal layers may form a eutectic phase. During bonding wafers, two top metal layers are joined in a liquid state; next the intermediary diffusion-buffer metal layers are distributed uniformly in the molten top metal layers; then the top and bottom metal layers diffuse to each other to form a low-resistivity eutectic intermetallic compound until the top metal layers are completely exhausted by the bottom metal layers.

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Номер записи: 11
16-01-2014 дата публикации

Semiconductor chips having improved solidity, semiconductor packages including the same and methods of fabricating the same

Номер: US20140015115A1
Автор: Jong Hyun Nam
Принадлежит: SK hynix Inc

Semiconductor chips are provided. The semiconductor chip includes a semiconductor chip body having an arch-shaped groove in a backside thereof and a non-conductive material pattern filling the arch-shaped groove. Related methods are also provided.

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Номер записи: 12
05-01-2017 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20170005024A1
Автор: Shimazaki Koichi
Принадлежит:

Provided is a semiconductor device that includes a passivation film thinner than a wiring layer and has a high resistance to a stress caused during bonding. In the semiconductor device, a wiring layer () is formed in the vicinity of a bonding pad () via a gap (), a passivation film () has a thickness smaller than that of the wiring layer () forming the bonding pad (), and the gap () has a width equal to or smaller than twice the passivation film thickness. 1. A semiconductor device , comprising:a semiconductor substrate;an insulating film formed on a surface of the semiconductor substrate;a bonding pad formed on the insulating film;a top wiring layer formed on the insulating film around the bonding pad via a gap; anda passivation covering the top wiring layer and a portion of the bonding pad, the passivation film having a thickness smaller than a thickness of the bonding pad;the gap having a width equal to or larger than the thickness of the passivation film covering the top wiring layer, and equal to or smaller than twice a side wall thickness of the passivation film covering a side wall of the top wiring layer.2. A semiconductor device according to claim 1 , wherein the top wiring layer is formed around the bonding pad as a rectangular ring.3. A semiconductor device according to claim 2 , wherein the top wiring layer is divided in part.4. A semiconductor device according to claim 2 , wherein the top wiring layer comprises top wiring layers formed around the bonding pad as at least two surrounding members.5. A semiconductor device according to claim 3 , wherein the top wiring layer comprises top wiring layers formed around the bonding pad as at least two surrounding members.6. A semiconductor device according to claim 1 , wherein a vertical thickness of a portion of the passivation film filled into the gap is larger than a vertical thickness of a portion of the passivation film formed on the bonding pad.7. A semiconductor device according to claim 1 , wherein the ...

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Номер записи: 13
03-01-2019 дата публикации

3D Packaging Method for Semiconductor Components

Номер: US20190006301A1
Автор: Fabrice Duval, Fumihiro Inoue
Принадлежит: Interuniversitair Microelektronica Centrum vzw IMEC

The present disclosure relates to a method for bonding semiconductor components. A semiconductor component comprising microbumps on a planar bonding surface is prepared for bonding by applying a photosensitive polymer layer on the bonding surface. The average thickness of the initial polymer layer in between the microbumps is similar to the average height of the microbumps. In a lithography process, the polymer is removed from the upper surface of the microbumps and from areas around the microbumps. The polymer is heated to a temperature at which the polymer flows, resulting in a polymer layer that closely adjoins the microbumps, without exceeding the microbump height. The closely adjoining polymer layer may have a degree of planarity substantially similar to a planarized layer.

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Номер записи: 14
14-01-2021 дата публикации

Die Attach Methods and Semiconductor Devices Manufactured based on Such Methods

Номер: US20210013132A1
Автор: Garbin Giovanni Ragasa, LEE Chen Wen, Mahler Joachim, Reichert Benjamin, Strobel Peter
Принадлежит:

A semiconductor device includes a carrier, a power semiconductor die that includes first and second opposite facing main surfaces, a side surface extending from the first main surface to the second main surface, and first and second electrodes disposed on the first and second main surfaces, respectively, a die attach material arranged between the carrier and the first electrode, wherein the die attach material forms a fillet at the side surface of the power semiconductor die, wherein a fillet height of the fillet is less than about 95% of a height of the power semiconductor die, wherein the height of the power semiconductor die is a length of the side surface, and wherein a maximum extension of the die attach material over edges of a main surface of the power semiconductor die facing the die attach material is less than about 200 micrometers. 1. A semiconductor device , comprising:a carrier;a power semiconductor die that comprises first and second opposite facing main surfaces, a side surface extending from the first main surface to the second main surface, and first and second electrodes disposed on the first and second main surfaces, respectively;a die attach material arranged between the carrier and the first electrode,wherein the die attach material forms a fillet at the side surface of the power semiconductor die,wherein a fillet height of the fillet is less than about 95% of a height of the power semiconductor die,wherein the height of the power semiconductor die is a length of the side surface, andwherein a maximum extension of the die attach material over edges of a main surface of the power semiconductor die facing the die attach material is less than about 200 micrometers.2. The semiconductor device of claim 1 , wherein the height of the power semiconductor die is less than about 400 micrometers.3. The semiconductor device of claim 2 , wherein the height of the power semiconductor die is less than about 150 micrometers.4. The semiconductor device of claim ...

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Номер записи: 15
21-01-2021 дата публикации

INTEGRATION AND BONDING OF MICRO-DEVICES INTO SYSTEM SUBSTRATE

Номер: US20210020593A1
Автор: Chaji Gholamreza, SADEGHIMAKKI Bahareh
Принадлежит: VueReal Inc.

This disclosure is related to integrating optoelectronics microdevices into a system substrate for efficient and durable electrical bonding between two substrates at low temperature. 2D nanostructures and 3D scaffolds may create interlocking structures for improved bonding properties. Addition of nanoparticles into the structure creates high surface area for better conduction. Application of curing agents before or after alignment of micro devices and receiving substrates further assists with formation of strong bonds. 1. A method of electrically bonding a microdevice into a receiver substrate , the method comprising:bonding at least a part of one surface of at least one bonding pad on a receiver substrate to at least a part of another surface of at least an optoelectronic microdevice on a donor substrate; andwherein a gap between the pads and the optoelectronic microdevice is covered with a coated nanowire.2. The method of claim 1 , wherein the nanowire coating comprises of nanoparticles.3. The method of claim 1 , wherein the nanowire coating is done by deposition of metal on the nanowire.4. The method of claim 1 , wherein the nanowire coating is In claim 1 , Ag or Sn.5. The method of claim 1 , wherein the nanowire is a metal claim 1 , a TOC or a carbon nanotube.6. The method of claim 1 , wherein an electrical energy is applied to the nanowire to reduce the resistivity.7. The method of claim 6 , wherein the electrical energy is applied as a pulsed voltage.8. The method of claim 1 , wherein a bonding material enhances the eutectic bonding to form alloys with Ag nano-wires and lower the thermal input required for bonding9. The method of claim 1 , wherein the dc current is 400 mA applied constantly for 80 seconds.10. The method of claim 1 , wherein a resistance is decreased via a deposition of the bonding material onto Ag nano-wires by applying a 25-800 mA DC current. This application is a continuation of U.S. Nonprovsisional application Ser. No. 16/189,844, filed on ...

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Номер записи: 16
21-01-2021 дата публикации

ELECTRICAL CONNECTING STRUCTURE HAVING NANO-TWINS COPPER AND METHOD OF FORMING THE SAME

Номер: US20210020599A1
Автор: CHEN Chih, Juang Jing-Ye, SHIE Kai-Cheng
Принадлежит:

Disclosed herein is a method of forming an electrical connecting structure having nano-twins copper. The method includes the steps of (i) forming a first nano-twins copper layer including a plurality of nano-twins copper grains; (ii) forming a second nano-twins copper layer including a plurality of nano-twins copper grains; and (iii) joining a surface of the first nano-twins copper layer with a surface of the second nano-twins copper layer, such that at least a portion of the first nano-twins copper grains grow into the second nano-twins copper layer, or at least a portion of the second nano-twins copper grains grow into the first nano-twins copper layer. An electrical connecting structure having nano-twins copper is provided as well. 1. A method of forming electrical connecting structure having nano-twins copper , comprising steps of:forming a first nano-twins copper layer comprising a plurality of first nano-twins copper grains;forming a second nano-twins copper layer comprising a plurality of second nano-twins copper grains; andjoining a surface of the first nano-twins copper layer with a surface of the second nano-twins copper layer, such that at least a portion of the first nano-twins copper grains grow into the second nano-twins copper layer, or at least a portion of the second nano-twins copper grains grow into the first nano-twins copper layer.2. The method of claim 1 , wherein a joining interface is formed in the step of joining the surface of the first nano-twins copper layer with the surface of the second nano-twins copper layer claim 1 , at least a portion of the first nano-twins copper grains growing across the joining interface claim 1 , or at least a portion of the second nano-twins copper grains growing across the joining interface.3. The method of claim 1 , wherein the first nano-twins copper grains and the second nano-twins copper grains are substantially columnar claim 1 , and a width of each of the first nano-twins copper grains and the second ...

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Номер записи: 17
10-02-2022 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20220045027A1
Автор: Kitaura Hidetoshi, Ochi Shozo
Принадлежит:

A semiconductor device includes an insulation board, an electrode provided on the insulation board, a bonding layer provided on the electrode and made of a sintered body of metal particles having an average particle size of nano-order, and a semiconductor element bonded to the electrode via the bonding layer. A layer thickness of the bonding layer is greater than or equal to 220 μm and less than or equal to 700 μm. 1. A semiconductor device comprising:an insulation board;an electrode provided on the insulation board;a bonding layer provided on the electrode and made of a sintered body of metal particles having an average particle size of nano-order; anda semiconductor element bonded to the electrode via the bonding layer,wherein a layer thickness of the bonding layer is greater than or equal to 220 μm and less than or equal to 700 μm.2. The semiconductor device of claim 1 ,wherein a side surface of the bonding layer has a stair-like step in cross-sectional view.3. The semiconductor device of claim 1 , a first bonding layer provided on the electrode,', 'a second bonding layer provided on the first bonding layer, and', 'a third bonding layer provided on the second bonding layer, and, 'wherein the bonding layer includes'}a layer thickness of the second bonding layer is larger than a layer thickness of each of the first bonding layer and the third bonding layer.4. The semiconductor device of claim 3 ,wherein the layer thickness of the second bonding layer is greater than or equal to 200 μm and less than or equal to 500 μm.5. The semiconductor device of claim 3 ,wherein the layer thickness of each of the first bonding layer and the third bonding layer is greater than or equal to 10 μm and less than or equal to 100 μm.6. The semiconductor device of claim 3 ,wherein areas of the first bonding layer, the second bonding layer, and the third bonding layer in plane view satisfy the following expression,area of first bonding layer≥area of second bonding layer≥area of third ...

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Номер записи: 18
02-02-2017 дата публикации

Method for Manufacturing Metal Powder

Номер: US20170028477A1
Автор: Nirmalya Kumar Chaki, Poulami Sengupta ROY, Rohan P. Setna, Siuli Sarkar, Sutapa MUKHERJEE
Принадлежит: Alpha Assembly Solutions Inc, Alpha Metals Inc

A method for manufacturing metal powder comprising: providing a basic metal salt solution; contacting the basic metal salt solution with a reducing agent to precipitate metal powder therefrom; and recovering precipitated metal powder from the solvent.

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Номер записи: 19
02-02-2017 дата публикации

Semiconductor Devices and Methods of Forming Thereof

Номер: US20170033066A1
Автор: Alexander Heinrich, Evelyn Napetschnig, Thomas Fischer, Ulrike Fastner
Принадлежит: INFINEON TECHNOLOGIES AG

In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

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Номер записи: 20
01-02-2018 дата публикации

Semiconductor device and method of manufacturing same

Номер: US20180033709A1
Автор: Soshi KURODA, Takanori Aoki, Tatsuya Kobayashi
Принадлежит: Renesas Electronics Corp

To provide a semiconductor device having improved reliability. The semiconductor device has a wiring board, bonding land, semiconductor chip mounted on the wiring board via an adhesive layer and having a pad electrode, bonding wire connecting the pad electrode with the bonding land, and sealing body. The sealing body is, in a circuit formation region, in contact with an organic protection film and, in a scribe region and a region between the pad electrode and the scribe region, in contact with a surface protection film while not in contact with the organic protection film. A first side surface is closer to the circuit formation region side than a second one. The adhesive layer covers entirety of the semiconductor chip back surface and the second side surface of the semiconductor chip. The first side surface is in contact with the sealing body without being covered with the adhesive layer.

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Номер записи: 21
17-02-2022 дата публикации

Display panel, preparation method thereof, and display device

Номер: US20220052022A1
Автор: Quanpeng YU
Принадлежит: Shanghai Tianma Microelectronics Co Ltd

Provided are a display panel, a preparation method thereof, and a display device. The display panel includes a plurality of sub-panels. Each sub-panel includes first substrate, second substrate, bezel adhesive located therebetween, a plurality of bank structures, and a plurality of light-emitting elements. At least one light-emitting element forms a pixel unit. Each bank structure is located between adjacent pixel units. Seaming adhesive is located between adjacent sub-panels. The sub-panels share a same first substrate, and the seaming adhesive is disposed on the same first substrate. The first substrate includes a display region and a non-display region surrounding the display region. The light-emitting elements and the bank structures are located in the display region, and the bezel adhesive is located in the non-display region. In this manner, splicing gaps between adjacent sub-panels can be effectively reduced, and thus the display effect of the display panel can be improved.

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Номер записи: 22
31-01-2019 дата публикации

SEMICONDUCTOR PACKAGE WITH INDIVIDUALLY MOLDED LEADFRAME AND DIE COUPLED AT SOLDER BALLS

Номер: US20190035669A1
Автор: TALLEDO Jefferson
Принадлежит:

According to principles as taught herein, a leadframe array for a semiconductor die is prepared having locations to receive solder balls. Solder balls are then applied to the leadframe array, after which the leadframe array and solder ball combination is placed in a first mold and encased in a first molding compound. After the molding compound is cured, a layer of molding compound is removed to expose the solder balls. After this, a semiconductor die is electrically connected to the exposed solder balls. The combined semiconductor die and leadframe are placed in a second mold, and a second molding compound injected. The second molding compound flows around the semiconductor die and leadframe combination, fully enclosing the electrical connections between the leadframe and the semiconductor die, making the final package a twice-molded configuration. After this, the twice-molded semiconductor package array is cut at the appropriate locations to singulate the packages into individual products. 1. A method for making a semiconductor die package , comprising:forming recesses in a first surface of a leadframe array;placing solder in the recesses of the leadframe array to form solder balls;placing the combined leadframe array and solder balls into a mold;injecting a molding compound into the mold sufficient to fully encapsulate the solder and the first surface of the leadframe array to create a once-molded leadframe array;removing an upper portion of the molding compound and the solder balls sufficient to expose an interior surface area of the solder;attaching a semiconductor die to the exposed solder;placing the combined semiconductor die and once-molded molded leadframe array into a second mold;injecting a second molding compound into the second mold to encapsulate the semiconductor die and the upper surface of the exposed first molding compound; andsingulating individual semiconductor die packages from the twice-molded semiconductor package array.2. The method of claim ...

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Номер записи: 23
08-02-2018 дата публикации

SYSTEMS AND METHODS FOR MEASURING PHYSICAL CHARACTERISTICS OF SEMICONDUCTOR DEVICE ELEMENTS USING STRUCTURED LIGHT

Номер: US20180038806A1
Автор: Colosimo, JR. Thomas J., Rauth David A., Sood Deepak, Tang Shu-Guo, Wang Zhijie
Принадлежит:

A method of determining a physical characteristic of an adhesive material on a semiconductor device element using structured light is provided. The method includes the steps of: (1) applying a structured light pattern to an adhesive material on a semiconductor device element; (2) creating an image of the structured light pattern using a camera; and (3) analyzing the image of the structured light pattern to determine a physical characteristic of the adhesive material. Additional methods and systems for determining physical characteristics of semiconductor devices and elements using structured light are also provided. 1. A method of determining a physical characteristic of an adhesive material on a semiconductor device element using structured light , the method comprising the steps of:(a) applying a structured light pattern to an adhesive material on a semiconductor device element;(b) creating an image of the structured light pattern using a camera; and(c) analyzing the image of the structured light pattern to determine a physical characteristic of the adhesive material.2. The method of wherein the adhesive material is selected from the group consisting of an epoxy material claim 1 , a non-conductive paste material claim 1 , and a curable liquid material.3. The method of wherein the structured light pattern includes at least one of a parallel bar pattern and a grid pattern.4. The method of further comprising a step of dispensing the adhesive material on to the semiconductor device element prior to step (a).5. The method of wherein step (c) includes using the image to determine if the physical characteristic is within a predetermined specification.6. The method of further comprising a step of adjusting an aspect of the step of dispensing the adhesive material for a subsequent semiconductor device element if it is determined that the physical characteristic is not within the predetermined specification.7. The method of wherein the step of adjusting is performed using a ...

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Номер записи: 24
08-02-2018 дата публикации

CHIP CARRIER AND METHOD THEREOF

Номер: US20180040573A1
Автор: POHL Jens, Pueschner Frank
Принадлежит:

A method may include providing a chip carrier having a chip supporting region to support a chip, and a chip contacting region having at least one contact pad, the chip carrier being thinner in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region. A disposing of the chip, having at least one contact protrusion, over the chip carrier, such that the at least one contact protrusion is arranged over the at least one contact pad may be included. In addition, a pressing of the chip against the chip carrier such that the at least one contact protrusion extends at least partially into the chip contacting region and is electrically contacted to the at least one contact pad may be included. 1. A method , comprising: a chip supporting region configured to support a chip, and', 'a chip contacting region having at least one contact pad configured to electrically contact the chip,', 'the chip carrier being thinner in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region;, 'providing a chip carrier, the chip carrier including'}disposing the chip including at least one contact protrusion over the chip carrier, such that the at least one contact protrusion is arranged over the at least one contact pad; andpressing the chip against the chip carrier such that the at least one contact protrusion extends at least partially into the chip contacting region and is electrically contacted to the at least one contact pad.2. The method of claim 1 ,wherein pressing the chip against the chip carrier includes displacing the at least one contact pad by deforming the chip carrier to form a recess for receiving the at least one contact protrusion.3. The method of claim 1 ,wherein pressing the chip against the chip carrier is ...

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Номер записи: 25
07-02-2019 дата публикации

POWER ELECTRONICS ASSEMBLY HAVING AN ADHESION LAYER, AND METHOD FOR PRODUCING SAID ASSEMBLY

Номер: US20190043820A1
Автор: Sagebaum Ulrich
Принадлежит: SEMIKRON Elektronik GmbH & Co. KG

A power electronics method and assembly produced by the method. The assembly has a substrate, having a power semiconductor element, and an adhesion layer disposed therebetween, wherein the substrate has a first surface that faces a power semiconductor element, a power semiconductor element has a third surface that faces the substrate, the adhesion layer has a second surface which, preferably across the full area, contacts the third surface and has a first consistent surface contour having a first roughness, and wherein a fourth surface of the power semiconductor element that is opposite the third surface has a second surface contour having a second roughness, said second surface contour following the first surface contour. 1. A power electronics assembly , comprising:{'b': 1', '3', '2, 'a substrate (), having a power semiconductor element (), and an adhesion layer () disposed therebetween;'}{'b': 1', '120', '160', '3, 'the substrate () has a first surface (, ) that faces the power semiconductor element ();'}{'b': 3', '320', '2, 'the power semiconductor element () has a third surface () that faces the substrate ();'}{'b': 2', '220', '320, 'the adhesion layer () has a second surface () which contacts the third surface () and has a first consistent surface contour having a first roughness; and'}{'b': 340', '3', '320, 'a fourth surface () of the power semiconductor element () that is opposite the third surface () has a second surface contour having a second roughness, said second surface contour following the first surface contour.'}2. The power electronics assembly claim 1 , according to claim 1 , wherein:a value of the second roughness is between 50% and 100%, of a value of the first roughness.3. The power electronics assembly claim 2 , according to claim 2 , wherein:{'b': 3', '3, 'the first roughness is configured so as to vary in one of a consistent and a inconsistent manner from a centre of the power semiconductor element () towards an outside of said power ...

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Номер записи: 26
06-02-2020 дата публикации

SEMICONDUCTOR DEVICE, POWER CONVERSION APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20200043888A1
Автор: Tatsumi Hiroaki
Принадлежит: Mitsubishi Electric Corporation

A bonding material that contains first particles containing a first metal, second particles containing a second metal having a melting point lower than that of the first metal, and filling resin is supplied on one of a semiconductor element or a conductor member, and a gap is formed in a surface of the supplied bonding material. The other of the conductor member or the semiconductor element is mounted on and pressed against the bonding material in which the gap is formed, and the filling resin unevenly distributed on the surface of the bonding material is moved to the gap. 1. A semiconductor device comprising:a semiconductor element;a conductor member; anda bonding portion that bonds the semiconductor element and the conductor member with electrical conduction;the bonding portion containing first particles that contain a first metal, an intermetallic compound that contains the first metal and a second metal having a melting point lower than a melting point of the first metal and couples the first particles to each other, and a filling resin,the bonding portion having, in a cross section parallel to a bonding direction,mixed metal regions in which a coupled structure including the first particles and the intermetallic compound is continuously formed from a bonding surface with the semiconductor element to a bonding surface with the conductor member, anda mixed resin region formed between two of the mixed metal regions that are adjacent to each other, in which a ratio of the filling resin is greater than a ratio of the filling resin in the mixed metal region, and the coupled structure is not in contact with at least one of the semiconductor element or the conductor member.2. The semiconductor device according to claim 1 , wherein the ratio of the filling resin in the mixed resin region is 50% by volume or more.3. The semiconductor device according to claim 1 , wherein the mixed resin regions are disposed to be dispersed over entirety of the bonding portion.4. The ...

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Номер записи: 27
18-02-2021 дата публикации

Semiconductor device

Номер: US20210050444A1
Автор: Eiji Yasuda, Kazuma Yoshida, Ryosuke Okawa, Ryou Kato, Shigetoshi Sota, Toshikazu Imai, Yoshihiro Matsushima
Принадлежит: Nuvoton Technology Corp Japan

A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 μm, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

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Номер записи: 28
16-02-2017 дата публикации

METHOD FOR MANUFACTURING THERMAL INTERFACE SHEET

Номер: US20170047269A1
Автор: NAKAMURA Naoaki
Принадлежит:

A thermal interface sheet includes a peripheral portion, in a surface direction, configured to have a melting point higher than the melting point of a central portion in the surface direction. 1. A method for manufacturing a thermal interface sheet , comprising:preparing a first solder region having a quadratic prism shape and being formed from a first solder;immersing the first solder region into a second solder which is melted so as to form a second solder region having a quadratic prism shape around the first solder region;immersing the first solder region and the second solder region into a third solder which is melted so as to form a third solder region having a quadratic prism shape around the second solder region; andcutting the first solder region, the second solder region and the third solder region,wherein a third melting point of the third solder is larger than a second melting point of the second solder and the second melting point is larger than a first melting point of the first solder.2. The method according to claim 1 , wherein the first solder region claim 1 , the second solder region and the third region are provided concentrically.3. The method according to claim 1 , wherein the first solder region is cooled before being immersed into the second solder claim 1 , and the first solder region and the second solder region are cooled before being immersed into the third solder.4. The method according to claim 1 , wherein the first solder region claim 1 , the second solder region and the third solder region contain one of an In—Ag solder claim 1 , a Sn—Cu solder claim 1 , a Sn—Ag—Cu solder claim 1 , and a Sn—Ag—Cu—Bi solder.5. A method for manufacturing a thermal interface sheet claim 1 , comprising:preparing a first solder region having a quadratic prism shape and being formed from a first solder;winding, onto the first solder region, a second solder which is sheet-shaped so as to form a second solder region having a quadratic prism shape around the ...

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Номер записи: 29
15-02-2018 дата публикации

LIGHT EMITTING DEVICE PACKAGE, BACKLIGHT UNIT, ILLUMINATION APPARATUS, AND METHOD OF MANUFACTURING LIGHT EMITTING DEVICE PACKAGE

Номер: US20180047884A1
Автор: JO Sung-Sik, KIM Bo-Young, LEE Ji-yeon, LIM Jung-a, OH Seung-Hyun, YUN Sung-Yole
Принадлежит: LUMENS CO., LTD.

Disclosed herein are a light emitting device package, a backlight unit, an illumination apparatus, and a method of manufacturing a light emitting device package capable of being used for a display application or an illumination application. The light emitting device package includes: a flip-chip type light emitting device having a first terminal and a second terminal installed therebeneath; a substrate having a first electrode formed at one side of an electrode separating space and a second electrode formed at the other side thereof; a first conductive bonding member installed on the first electrode of the substrate so as to be electrically connected to the first terminal of the light emitting device; a second conductive bonding member installed on the second electrode of the substrate so as to be electrically connected to the second terminal of the light emitting device; a reflection encapsulant molded and installed on the substrate so as to form a reflection cup part reflecting light generated in the light emitting device and filled in the electrode separating space to form an electrode separating part; and a filler filled between the reflection cup part and the first and second conductive bonding members. 118-. (canceled)19. A light emitting device package comprising:a light emitting device including a first terminal and a second terminal;a substrate including a first electrode formed at one side of an electrode separating space and a second electrode formed at the other side of the electrode separating space;a first conductive bonding member installed on the first electrode of the substrate so as to be electrically connected to the first terminal of the light emitting device;a second conductive bonding member installed on the second electrode of the substrate so as to be electrically connected to the second terminal of the light emitting device; anda reflection encapsulant installed on the substrate so as to form a reflection cup part configured to reflect light ...

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Номер записи: 30
03-03-2022 дата публикации

METHOD OF PRODUCING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE

Номер: US20220068788A1
Автор: ALBERTINETTI Andrea, CAGUD Marifi Corregidor
Принадлежит:

A warped semiconductor die is attached onto a substrate such as a leadframe by dispensing a first mass of die attach material onto an area of the substrate followed by dispensing a second mass of die attach material so that the second mass of die attach material provides a raised formation of die attach material. For instance, the second mass may be deposited centrally of the first mass. The semiconductor die is placed onto the first and second mass of die attach material with its concave/convex shape matching the distribution of the die attach material thus effectively countering undesired entrapment of air.

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Номер записи: 31
25-02-2016 дата публикации

Fabricating pillar solder bump

Номер: US20160056116A1
Автор: Hiroyuki Mori, Kazushige Toriyama, Toyohiro Aoki
Принадлежит: International Business Machines Corp

A substrate bonding method is able to reliably bond substrates while avoiding a reduction in yield made worse by finer pitches. The substrate bonding method can include: forming an adhesive resin layer on a surface of a first substrate on which a pad has been formed; forming an opening on the adhesive resin layer above the pad; filling the opening with molten solder to form a pillar-shaped solder bump; and applying heat and pressure to the first substrate and a second substrate while a terminal formed on the second substrate is aligned with the solder bump.

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Номер записи: 32
15-05-2014 дата публикации

Solder fatigue arrest for wafer level package

Номер: US20140131859A1
Автор: Arkadii V. Samoilov, Kaysar M. Rahim, Tiao Zhou, Viren Khandekar, Xiansong Chen, Yi-Sheng Anthony SUN, Yong Li Xu
Принадлежит: Maxim Integrated Products Inc

A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 μm) and fifty micrometers (50 μm) from the lead. In some embodiments, the core covers between at least approximately one-third (⅓) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

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Номер записи: 33
15-05-2014 дата публикации

Method And System For A Semiconductor Device Package With A Die To Interposer Wafer First Bond

Номер: US20140134796A1
Автор: David Jon Hiner, Michael G. Kelly, Ronald Patrick Huemoeller, Won Chul Do
Принадлежит: Amkor Technology Inc

Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. A mold material may be applied to encapsulate the die. The interposer wafer may be thinned to expose through-silicon-vias (TSVs) and metal contacts may be applied to the exposed TSVs. The interposer wafer may be singulated to generate assemblies comprising the semiconductor die and an interposer die. The die may be placed on the interposer wafer utilizing an adhesive film. The interposer wafer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The die may be bonded to the interposer wafer utilizing a mass reflow or a thermal compression process.

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Номер записи: 34
03-03-2016 дата публикации

CONNECTION ARRANGEMENT OF AN ELECTRIC AND/OR ELECTRONIC COMPONENT

Номер: US20160064350A1
Автор: Fix Andreas, Frueh Christiane
Принадлежит:

A connection arrangement includes at least one electric and/or electronic component. The at least one electric and/or electronic component has at least one connection face, which is connected in a bonded manner to a join partner by means of a connection layer. The connection layer can for example be an adhesive, soldered, welded, sintered connection or another known connection that connects joining partners while forming a material connection. Furthermore, a reinforcement layer is arranged adjacent to the connection layer in a bonded manner. The reinforcement layer has a higher modulus of elasticity than the connection layer. A particularly good protective effect is achieved if the reinforcement layer is formed in a frame-like manner by an outer and an inner boundary and, at least with the outer boundary thereof, encloses the connection face of the at least one electric and/or electronic component. 11002003004001010114020. A connection arrangement ( , , , ) of at least one electric and/or electronic component () , wherein the at least one electric and/or electronic component () has a connection face () , which is connected in a bonded manner to the join partner () by a connection layer () , wherein{'b': 30', '20', '30', '20', '30', '36', '35', '36', '11', '10, 'a reinforcement layer (′) is arranged adjacent to the connection layer (), said reinforcement layer (′) having a higher modulus of elasticity than the connection layer (), wherein the reinforcement layer (′) is formed in a frame-like manner by an outer boundary and an inner boundary (, ) and, at least with the outer boundary () thereof, encloses the connection face () of the at least one electric and/or electronic component (), and'}{'b': '30', 'wherein the reinforcement layer (′) comprises at least one intermetallic phase.'}2203030203030. The connection arrangement according to claim 1 , characterized in that the connection layer () comprises at least one metal and the reinforcement layer (′) is formed from ...

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Номер записи: 35
01-03-2018 дата публикации

Semiconductor Device with Plated Lead Frame

Номер: US20180061671A1
Автор: Brockmeier Andre, Fastner Ulrike, von Koblinski Carsten, Zorn Peter
Принадлежит:

A semiconductor device includes an insulating carrier structure comprised of an insulating inorganic material. The carrier structure has a receptacle in which a semiconductor chip is disposed. The semiconductor chip has a first side, a second side and a lateral rim. The carrier structure laterally surrounds the semiconductor chip and the lateral rim. The semiconductor device also includes a metal structure on and in contact with the second side of the semiconductor chip and embedded in the carrier structure. 1. A semiconductor device , comprising:an insulating carrier structure comprised of an insulating inorganic material, the carrier structure comprising a receptacle;a semiconductor chip comprising a first side, a second side and a lateral rim, the semiconductor chip being disposed in the receptacle, wherein the carrier structure laterally surrounds the semiconductor chip and the lateral rim; anda metal structure on and in contact with the second side of the semiconductor chip and embedded in the carrier structure.2. The semiconductor device of claim 1 , wherein the metal structure has a thickness between about 30 μm to about 500 μm.3. The semiconductor device of claim 1 , wherein the insulating carrier structure comprises a carrier substrate and a cover substrate joined with the carrier substrate by an adhesive bond.4. The semiconductor device of claim 3 , wherein the carrier substrate comprises at least one of glass and ceramic.5. The semiconductor device of claim 3 , wherein the cover substrate comprises at least one of glass and ceramic.6. The semiconductor device of claim 1 , wherein the insulating carrier structure comprises a circumferential groove encompassing a peripheral region of the semiconductor chip.7. The semiconductor device of claim 1 , wherein the semiconductor chip comprises a semiconductor material comprising a first doping region formed in the semiconductor material at a first side of the semiconductor material and a second doping region ...

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Номер записи: 36
02-03-2017 дата публикации

Chip carrier, a device and a method

Номер: US20170062358A1
Автор: Frank Pueschner, Jens Pohl
Принадлежит: INFINEON TECHNOLOGIES AG

According to various embodiments, a chip carrier may include: a chip supporting region configured to support a chip; a chip contacting region including at least one contact pad for electrically contacting the chip; wherein the chip carrier is thinned in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region.

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Номер записи: 37
02-03-2017 дата публикации

Anisotropic conductive film structures

Номер: US20170062379A1
Автор: Bo Zhang, Cyrus Y. LIU, Kuo-Hua Sung, Sang Ha Kim
Принадлежит: Apple Inc

Anisotropic conductive film (ACF) structures and manufacturing methods for forming the same are described. The manufacturing methods include preventing clusters of conductive particles from forming between adjacent bonding pads and that are associated with electrical shorting of ACF structures. In some embodiments, the methods involve use of multiple layered ACF materials that include a non-electrically conductive layer that reduces the likelihood of formation of conductive particle clusters between bonding pads. In some embodiment, the methods include the use of ultraviolet sensitive ACF material combined with lithography techniques that eliminate conductive particles from between neighboring bonding pads. In some embodiments, the methods involve the use of insulation spacers that block conductive particles from entering between bonding pads. Any suitable combination of the described methods can be used.

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Номер записи: 38
04-03-2021 дата публикации

Monolithic die with acoustic wave resonators and active circuitry

Номер: US20210067132A1
Автор: Aleksandar Aleksov, Feras Eid, Georgios Dogiamis, Johanna M. Swan, Telesphor Kamgaing
Принадлежит: Intel Corp

Embodiments may relate to a radio frequency (RF) front-end module (FEM). The RF FEM may include an integrated die with an active portion and an acoustic wave resonator (AWR) portion adjacent to the active portion. The RF FEM may further include a lid coupled with the die. The lid may at least partially overlap the AWR portion at a surface of the die. Other embodiments may be described or claimed.

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Номер записи: 39
28-02-2019 дата публикации

ANISOTROPIC CONDUCTIVE FILM AND MANUFACTURING METHOD THEREOF

Номер: US20190067234A1
Автор: AKUTSU Yasushi, SARUYAMA Kenichi
Принадлежит: DEXERIALS CORPORATION

An anisotropic conductive film A includes a conductive particle array layer in which a plurality of conductive particles are arrayed in a prescribed manner and held in an insulating resin layer The anisotropic conductive film A has a direction in which a thickness distribution, around the individual conductive particle, of the insulating resin layer holding the array of the conductive particles is asymmetric with respect to the conductive particle The direction in which the thickness distribution is asymmetric is aligned in the same direction in the plurality of conductive particles. When an electronic component is mounted using this anisotropic conductive film A, short circuits and conductive failure can be reduced. 1. An anisotropic conductive film comprising:a conductive particle array layer in which a plurality of conductive particles are arrayed in a prescribed manner and held in an insulating resin layer, the anisotropic conductive film having a direction in which a thickness distribution, around the individual conductive particle, of the insulating resin layer holding the array of the conductive particles is asymmetric with respect to the conductive particle.2. The anisotropic conductive film according to claim 1 , wherein the direction in which the thickness distribution is asymmetric is aligned in the same direction in the plurality of conductive particles.3. The anisotropic conductive film according to claim 1 , wherein in a cross section of the anisotropic conductive film when the anisotropic conductive film is cut in the direction in which the thickness distribution is asymmetric claim 1 , the direction passing through a center of the conductive particle claim 1 , an area of the insulating resin layer surrounding the conductive particle is configured such that an area on one side of the conductive particle is smaller than an area on the other side.4. The anisotropic conductive film according to claim 3 , wherein in the cross section of the anisotropic ...

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Номер записи: 40
15-03-2018 дата публикации

CHIP MOUNTING STRUCTURE

Номер: US20180076162A1
Автор: Horibe Akihiro, MATSUMOTO Keiji, Okamoto Keishi, Toriyama Kazushige
Принадлежит:

Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate. 1. A method for changing a shape of a substrate to reduce stress exerted on an interlayer insulating layer of a chip , the method comprising:providing the substrate;mounting the chip on the substrate such that a center of the chip corresponds to a center of the substrate and such that sides of the chip are parallel to sides of the substrate;measuring a distance B between a side of the chip and a nearest side of the substrate; andcutting off square portions of the substrate from each corner of the substrate such that a distance between a corner of the chip and a nearest corner of the substrate is less than the distance B.2. The method of claim 1 , wherein each square portion has sides of a length c.4. A method for mounting a chip on a substrate claim 1 , the method comprising:providing a chip having an interlayer insulating layer, the interlayer insulating layer having a low dielectric constant;mounting the chip to a substrate such that there is a distance B between a side of the chip and a nearest side of the substrate;connecting the chip to the substrate using flip-chip bumps; andcutting off right-angle isosceles triangle portions of the substrate from each ...

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Номер записи: 41
31-03-2022 дата публикации

Advanced Device Assembly Structures And Methods

Номер: US20220097166A1
Автор: Uzoh Cyprian Emeka
Принадлежит: INVENSAS CORPORATION

A microelectronic assembly includes a first substrate having a surface and a first conductive element and a second substrate having a surface and a second conductive element. The assembly further includes an electrically conductive alloy mass joined to the first and second conductive elements. First and second materials of the alloy mass each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element to a relatively lower amount toward the second conductive element, and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element to a relatively lower amount toward the first conductive element. 1. A microelectronic assembly , comprising:a first substrate having a first surface and first conductive elements;a second substrate having a second surface and second conductive elements; anda plurality of electrically conductive masses, each mass joined to a respective pair of the first and second conductive elements,wherein each electrically conductive mass includes a first material, a second material, and a third material, the third material selected to increase the melting point of an alloy including the third material and at least one of the first material or the second material,wherein a concentration of the first material varies from a relatively higher amount at a location disposed toward the respective first conductive element to a relatively lower amount toward the respective second conductive element,wherein a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the respective second conductive element to a relatively lower amount toward the respective first conductive element, andwherein the third material has a highest concentration at a location ...

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Номер записи: 42
02-04-2015 дата публикации

SEMICONDUCTOR DEVICE CONNECTED BY ANISOTROPIC CONDUCTIVE FILM

Номер: US20150091192A1
Автор: HWANG Ja Young, JUNG Kwang Jin, KANG Kyoung Ku, KIM Ji Yeon, PARK Kyoung Soo, SHIN Woo Jung, Shin Young Ju
Принадлежит:

A semiconductor device connected by an anisotropic conductive film including a first insulation layer, a conductive layer, and a second insulation layer one above another, wherein the conductive layer has an expansion length of 20% or less in a width direction thereof, and the second insulation layer has an expansion length of 50% or more in a width direction thereof, the expansion length is calculated according to Equation 1, below, after glass substrates are placed on upper and lower sides of the anisotropic conductive film respectively, followed by compression at 110° C. to 200° C. for 3 to 7 seconds under a load of 1 MPa to 7 MPa per unit area of a sample, 1. A semiconductor device connected by an anisotropic conductive film , the anisotropic conductive film comprising:a first insulation layer, a conductive layer, and a second insulation layer sequentially stacked one above another,wherein:the conductive layer has an increased ratio of expansion length of 20% or less in a width direction thereof, andthe second insulation layer has an increased ratio of expansion length of 50% or more in a width direction thereof, {'br': None, 'Increased ratio of expansion length(%)=[(length of layer in width direction after compression−length of layer in width direction before compression)/length of layer in width direction before compression]×100.\u2003\u2003[Equation 1]'}, 'the increased ratio of expansion length is calculated according to Equation 1, below, after glass substrates are placed on upper and lower sides of the anisotropic conductive film respectively, followed by compression at 110° C. to 200° C. for 3 to 7 seconds under a load of 1 MPa to 7 MPa per unit area of a sample,'}2. A semiconductor device connected by an anisotropic conductive film , the anisotropic conductive film comprising:a first insulation layer, a conductive layer, and a second insulation layer sequentially stacked one above another,wherein a ratio of an expansion length of the second insulation ...

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Номер записи: 43
12-03-2020 дата публикации

SHIELDED PACKAGE ASSEMBLIES WITH INTEGRATED CAPACITOR

Номер: US20200083177A1
Автор: JR. Peter, Lamorey Mark C., Patel Janak G., Slota, Stone David B.
Принадлежит:

Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor. 1. A method for electrostatically storing energy in a package assembly including a chip stack and a lid , the method comprising:storing a first charge on a first plate of a capacitor provided by a flange of the lid that is coupled with the chip stack; andstoring a second charge on a second plate of the capacitor provided by a section of a conductive layer located along a sidewall of a first substrate of the package assembly that supports and laterally surrounds the chip stack, wherein the flange of the first plate and the second plate are laterally separated by a gap composed of dielectric material having a permittivity, and the first substrate is a laminated substrate containing a through-hole in which at least a portion of the chip stack and the lid and flange are located.2. The method of claim 1 , wherein the conductive layer is ring-shaped.3. The method of claim 1 , further comprising a solder ball on the conductive layer of the first substrate.4. The method of claim 1 , wherein the lid is cup shaped.5. The method of claim 1 , wherein the dielectric material that provides the gap is air.6. The method of claim 1 , wherein the ...

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Номер записи: 44
05-05-2022 дата публикации

Selective micro device transfer to receiver substrate

Номер: US20220139856A1
Автор: Ehsanollah Fathi, Gholamreza Chaji
Принадлежит: Vuereal Inc

A method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. Micro devices being attached to a donor substrate with a donor force. The donor substrate and receiver substrate are aligned and brought together so that selected micro devices meet corresponding contact pads. A receiver force is generated to hold selected micro devices to the contact pads on the receiver substrate. The donor force is weakened and the substrates are moved apart leaving selected micro devices on the receiver substrate. Several methods of generating the receiver force are disclosed, including adhesive, mechanical and electrostatic techniques.

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Номер записи: 45
05-05-2022 дата публикации

SELECTIVE MICRO DEVICE TRANSFER TO RECEIVER SUBSTRATE

Номер: US20220139857A1
Автор: Chaji Gholamreza, Fathi Ehsanollah
Принадлежит: VueReal Inc.

A method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. Micro devices being attached to a donor substrate with a donor force. The donor substrate and receiver substrate are aligned and brought together so that selected micro devices meet corresponding contact pads. A receiver force is generated to hold selected micro devices to the contact pads on the receiver substrate. The donor force is weakened and the substrates are moved apart leaving selected micro devices on the receiver substrate. Several methods of generating the receiver force are disclosed, including adhesive, mechanical and electrostatic techniques.

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Номер записи: 46
01-04-2021 дата публикации

Thermocompression bonding of electronic components

Номер: US20210098416A1
Автор: Eckardt Bihler, Marc Hauer
Принадлежит: DYCONEX AG

A method for producing an electronic module includes providing a first substrate including at least one first electrical contacting surface, an electronic component including at least one second electrical contacting surface, and a first material layer made of a thermoplastic material including at least one recess extending through the material layer. The first substrate, the electronic component and the first material layer are arranged with the first material layer disposed between the first substrate and the electronic component, and the at least one first electrical contacting surface, the at least one second electrical contacting surface and the at least one recess aligned relative to one another. The first substrate, the electronic component and the material layer are thermocompression bonded. A joint formed between the at least one first electrical contacting surface and the at least one second electrical contacting surface is surrounded or enclosed by the first material layer.

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Номер записи: 47
06-04-2017 дата публикации

FAN-OUT WAFER LEVEL PACKAGE STRUCTURE

Номер: US20170098589A1
Автор: Hsiao Ching-Wen, HUANG Wei-Che, LIN Tzu-Hung, LIU Nai-Wei, PENG I-Hsuan
Принадлежит:

A semiconductor package structure is provided. The structure includes a molding compound having a dicing lane region. A semiconductor die is disposed in the molding compound and surrounded by the dicing lane region. The semiconductor die has a first surface and a second surface opposite thereto, and the first and second surfaces are exposed from the molding compound. The structure further includes a redistribution layer (RDL) structure disposed on the first surface of the semiconductor die and covering the molding compound. The RDL structure includes a photo-sensitive material and has an opening aligned with the dicing lane region. 1. A semiconductor package structure , comprising:a molding compound having a dicing lane region;a semiconductor die disposed in the molding compound and surrounded by the dicing lane region, wherein the semiconductor die has a first surface and a second surface opposite thereto, and the first and second surfaces are exposed from the molding compound; anda redistribution layer (RDL) structure disposed on the first surface of the semiconductor die and covering the molding compound, wherein the RDL structure comprises a photo-sensitive material and has an opening aligned with the dicing lane region.2. The semiconductor package structure as claimed in claim 1 , wherein the opening passes through the RDL structure claim 1 , so that the molding compound corresponding to the dicing lane region is exposed by the opening.3. The semiconductor package structure as claimed in claim 1 , wherein the opening has a bottom within the RDL structure.4. The semiconductor package structure as claimed in claim 1 , wherein the opening has a width in a range of about 1 μm to 100 μm.5. The semiconductor package structure as claimed in claim 1 , further comprising a passive device disposed on and electrically coupled to the RDL structure.6. The semiconductor package structure as claimed in claim 1 , further comprising a plurality of bumps disposed on and ...

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Номер записи: 48
28-03-2019 дата публикации

3DIC Packaging with Hot Spot Thermal Management Features

Номер: US20190096781A1
Автор: Chen Kim Hong, Huang Szu-Po, Hung Wensen, Jeng Shin-Puu, Lee Hsiang-Fan, WU Chi-Hsi
Принадлежит:

A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material. 1. A package comprising: a plurality of first dies; and', 'a second die bonded to the plurality of first dies, wherein a first portion of the second die is disposed directly under the plurality of first dies, and wherein a second portion of the second die extends laterally past sidewalls of the plurality of first dies; and, 'a die stack comprising a conductive line extending continuously from the plurality of conductive connectors to a thermal interface material (TIM) at the top surface of the package substrate; and', 'a solder resist, wherein the solder resist covers a first portion of the conductive line and does not cover a second portion of the conductive line, and wherein the TIM extends through the solder resist to contact the second portion of the conductive line., 'a package substrate, wherein the die stack is bonded to a top surface of the package substrate by a plurality of conductive connectors, and wherein the package substrate comprises2. The package of claim 1 , further comprising a heat dissipation feature adhered to the package substrate by an adhesive claim 1 , wherein the conductive line is thermally connected to the heat dissipation feature through the TIM.3. The package of claim 2 , wherein the heat dissipation feature is adhered to the package substrate by an adhesive having a lower thermal conductivity than the TIM.4. The package of claim 3 , wherein the adhesive encircles the second portion of the conductive line in a top down view.5. The package of claim 1 , wherein the conductive line is a signal line claim 1 ...

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Номер записи: 49
28-03-2019 дата публикации

ANISOTROPIC CONDUCTIVE FILM AND MANUFACTURING METHOD THEREOF

Номер: US20190096844A1
Автор: AKUTSU Yasushi, SARUYAMA Kenichi
Принадлежит: DEXERIALS CORPORATION

An anisotropic conductive film 1A includes a conductive particle array layer 4 in which a plurality of conductive particles 2 are arrayed in a prescribed manner and held in an insulating resin layer The anisotropic conductive film 1A has a direction in which a thick distribution, around the individual conductive particle, of the insulating resin layer 3 holding the array of the conductive particles 2 is asymmetric with respect to the conductive particle 2. The direction in which the thickness distribution is asymmetric is aligned in the same direction in the plurality of conductive particles. When an electronic component is mounted using this anisotropic conductive film 1A, short circuits and conductive failure can be reduced. 1. An anisotropic conductive film comprising:a conductive particle array layer in which a plurality of conductive particles are arrayed in a prescribed manner and held in an insulating resin layer,wherein the anisotropic conductive film has a resin amount distribution, around the individual conductive particle, of the insulating resin layer holding the array of the conductive particles, and the resin amount distribution has a direction in which a resin amount decreases.2. The anisotropic conductive film according to claim 1 , wherein claim 1 , in a film surface direction claim 1 , the resin amount distribution claim 1 , around the individual conductive particle claim 1 , of the insulating resin layer holding the array of the conductive particles has a direction in which a resin amount decreases.3. The anisotropic conductive film according to claim 1 , wherein the direction in which the resin amount is less aligned in the same direction in the plurality of conductive particles.4. The anisotropic conductive film according to claim 1 , wherein in a cross section of the anisotropic conductive film when the anisotropic conductive film is cut in the direction in which the resin amount decreases claim 1 , the direction passing through a center of the ...

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Номер записи: 50
11-04-2019 дата публикации

SEAL RING STRUCTURES AND METHODS OF FORMING SAME

Номер: US20190109125A1
Автор: Lin Yung-Lung, LIU Kuan-Liang, Wang Wen-De, Wu Kuo-Ming
Принадлежит:

Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC. 1. A semiconductor packaging device comprising:a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate;a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure; anda seal ring structure that separates the first interconnect structure from the second interconnect structure and which perimetrically surrounds a gas reservoir between the first IC die and second IC die, wherein the seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.2. The semiconductor packaging device according to claim 1 , wherein the seal ring structure is conductive but is electrically isolated from both the first interconnect structure and the second interconnect structure.3. The semiconductor packaging device according to claim 1 , wherein the first interconnect structure comprises a first interlayer dielectric (ILD) layer claim 1 , first wiring layers claim 1 , and first via ...

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Номер записи: 51
25-08-2022 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20220271000A1
Автор: ZUO Mingxing
Принадлежит:

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a die and a first adhesive layer; a surface of the substrate is provided with an insulation layer; the die is arranged on a surface of the insulation layer via the first adhesive layer; the insulation layer is provided with at least one hole slot; a position of the at least one hole slot corresponds to at least a part of an edge of the first adhesive layer; a second adhesive layer is arranged in the at least one hole slot; at least a part of a surface of the second adhesive layer is connected with the first adhesive layer; and an elasticity modulus of the second adhesive layer is smaller than an elasticity modulus of the first adhesive layer. 1. A semiconductor structure , comprising a substrate , a die and a first adhesive layer , wherein a surface of the substrate is provided with an insulation layer; the die is arranged on a surface of the insulation layer via the first adhesive layer;the insulation layer is provided with at least one hole slot; a position of the at least one hole slot corresponds to at least a part of an edge of the first adhesive layer; a second adhesive layer is arranged in the at least one hole slot; at least a part of a surface of the second adhesive layer is connected with the first adhesive layer; andan elasticity modulus of the second adhesive layer is smaller than an elasticity modulus of the first adhesive layer.2. The semiconductor structure according to claim 1 , wherein the at least one hole slot runs through the insulation layer.3. The semiconductor structure according to claim 1 , wherein one hole slot of the at least one hole slot is of an annular closed structure claim 1 , such that the hole slot of the at least one hole slot corresponds to a whole edge of the first adhesive layer.4. The semiconductor structure according to claim 3 , wherein the first adhesive layer is rectangular; the ...

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Номер записи: 52
16-04-2020 дата публикации

Semiconductor device

Номер: US20200118979A1
Автор: Chi-Hsi Wu, Kuo-Chiang Ting, Shang-Yun Hou, Tu-Hao Yu, Weiming Chris Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes a first electronic component, a second electronic component, a third electronic component, a plurality of first interconnection structures, and a plurality of second interconnection structures. The second electronic component is between the first electronic component and the third electronic component. The first interconnection structures are between and electrically connected to the first electronic component and the second electronic component. Each of the first interconnection structures has a length along a first direction substantially parallel to a surface of the first electronic component and a width along a second direction substantially parallel to the surface and substantially perpendicular to the first direction. The length is larger than the width. The second interconnection structures are between and electrically connected to the second electronic component and the third electronic component.

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Номер записи: 53
27-05-2021 дата публикации

ELECTRONIC SUBSTRATE AND ELECTRONIC APPARATUS

Номер: US20210159202A1
Автор: Maehara Masataka
Принадлежит:

The present technology relates to an electronic substrate that achieves a reduction in the size of a substrate and enables a void risk in an underfill to be reduced, and an electronic apparatus. An electronic substrate in one aspect of the present technology includes: an electronic chip that is placed above a substrate; an electrode that exists between the substrate and the electronic chip and electrically connects the substrate and the electronic chip; an underfill with which a space between the substrate and the electronic chip is filled so that the electrode is sealed and protected; a protection target to be protected from inflow of the underfill, the protection target being formed on the substrate; and an underfill inflow prevention unit that is formed in the substrate so as to surround an entirety or a portion of the protection target. The present technology is applicable to, for example, a solid-state image sensor. 1. An electronic substrate , comprising:an electronic chip above a substrate;an optical layer on a surface of the substrate;an electrode between the substrate and the electronic chip, wherein the electrode electrically connects the substrate and the electronic chip;an underfill in a space between the substrate and the electronic chip to seal the electrode;a protection target to be protected from inflow of the underfill, wherein the protection target is on the substrate;a first inflow prevention unit that prevents the underfill from flowing into the optical layer, wherein the first inflow prevention unit is between a position where the electronic chip is placed and the optical layer; anda second inflow prevention unit that prevents the underfill from flowing into the protection target, wherein the second inflow prevention unit is around the protection target of the substrate.2. The electronic substrate according to claim 1 , wherein each of the first inflow prevention unit and the second inflow prevention unit is a recessed groove.3. The electronic ...

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Номер записи: 54
10-05-2018 дата публикации

Semiconductor device

Номер: US20180130846A1
Автор: Shin Hasegawa
Принадлежит: Canon Inc

Provided is a semiconductor device including: a first substrate having a first primary surface, a second primary surface, and a side surface; a semiconductor element formed on the first primary surface; a first electrode formed on the first primary surface and connected to the semiconductor element on the first primary surface; a second electrode formed on the second primary surface; a through-electrode formed so as to penetrate the first substrate and connecting the first electrode and the second electrode to each other; a second substrate bonded to the first substrate so as to face the first primary surface; and a third electrode formed on the side surface of the first substrate and connected to the second electrode.

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Номер записи: 55
11-05-2017 дата публикации

ASSEMBLY OF AN INTEGRATED CIRCUIT CHIP AND OF A PLATE

Номер: US20170133297A1
Автор: Collin Louis-Michel, Frechette Luc Guy, Lhostis Sandrine
Принадлежит:

An assembly includes an integrated circuit chip and a plate with at least one heat removal channel arranged between the chip and the plate. Metal sidewalls are formed to extend from one surface of the chip to an opposite surface of the plate. The assembly is encapsulated in a body that includes an opening extending to reach the channel. The plate may be one of an interposer, an integrated circuit chip, a support of surface-mount type, or a metal plate. 1. A method of manufacturing a flip-chip assembly of an integrated circuit chip and of a plate between which is arranged at least one channel delimited by metal sidewalls , the method comprising the steps of:a) forming metal walls corresponding to at least part of a height of each of the sidewalls on one of a surface of the integrated circuit chip or a surface of the plate;b) inserting sacrificial resin between the metal walls extending to at least a contour of a smaller one of the plate and the integrated circuit chip;c) mounting the integrated circuit chip and the plate on each other, the sidewalls being formed by the metal walls extending from the integrated circuit chip surface to the plate surface; andd) removing the sacrificial resin.2. The method of claim 1 , wherein the metal walls are formed at the same time as connection elements arranged between opposite surfaces of the integrated circuit chip and of the plate.3. The method of claim 1 , wherein at step c) claim 1 , the sacrificial resin extends along an entire length of said at least one channel and to a height of the sidewalls.4. The method of claim 1 , wherein at step c) claim 1 , the sidewalls extend from the integrated circuit chip surface to the plate surface claim 1 , the sacrificial resin fully obstructing said at least one channel to said contour.5. The method of claim 1 , wherein claim 1 , before step d) claim 1 , interstitial resin is arranged in an entire volume accessible between the integrated circuit chip and the plate.6. The method of claim 1 ...

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Номер записи: 56
07-08-2014 дата публикации

Semiconductor light emitting device and method for manufacturing same

Номер: US20140217438A1
Автор: Akihiro Kojima, Hideto Furuyama, Hideyuki Tomizawa, Miyoko Shimada, Yoshiaki Sugizaki, Yosuke Akimoto
Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor light emitting device includes: a semiconductor layer; a first electrode; a first interconnection layer; a second electrode; a second interconnection layer; a support substrate; a bonding layer; a first terminal; and a second terminal. The support substrate has a third face facing the semiconductor layer, the first interconnection layer, and the second interconnection layer and a fourth face opposite to the third face. The support substrate has a first opening extending from the fourth face to the first interconnection layer and a second opening extending from the fourth face to the second interconnection layer. The bonding layer is provided between the support substrate and each of the semiconductor layer, the first interconnection layer, and the second interconnection layer.

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Номер записи: 57
02-05-2019 дата публикации

Die stack structure and method of fabricating the same and package

Номер: US20190131277A1
Автор: Ching-Jung Yang, Hsien-Wei Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Provided is a die stack structure including a first die and a second die. The first die and the second die are bonded together through a hybrid bonding structure. At least one of a first test pad of the first die or a second test pad of the second die has a protrusion of the at least one of the first test pad or the second test pad, and a bonding insulating layer of the hybrid bonding structure covers and contacts with the protrusion, so that the first test pad and the second test pad are electrically isolated from each other.

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Номер записи: 58
23-04-2020 дата публикации

ELECTRONIC ASSEMBLIES HAVING A MESH BOND MATERIAL AND METHODS OF FORMING THEREOF

Номер: US20200126943A1
Автор: JOSHI Shailesh N., TAKE Naoya
Принадлежит: Toyota Motor Engineering & Manufacturing North America, Inc.

Embodiments of the present disclosure include a method of forming an electronic assembly with a mesh bond layer. The method may include forming a mesh bond material comprising a first surface spaced apart from a second surface by a thickness of the mesh bond material and one or more openings extending from the first surface through the thickness of the mesh bond material to the second surface. The method may further include adjusting at least one of: the thickness of the mesh bond material, a geometry of the one or more openings, or a size of the one or more openings of the mesh bond material, where the adjusting modifies a Young's modulus of the mesh bond material, and bonding the first surface of the mesh bond material to a surface of a semiconductor device. 1. A method of forming an electronic assembly with a mesh bond layer , the method comprising:forming a mesh bond material comprising a first surface spaced apart from a second surface by a thickness of the mesh bond material and one or more openings extending from the first surface through the thickness of the mesh bond material to the second surface;adjusting at least one of: the thickness of the mesh bond material, a geometry of the one or more openings, or a size of the one or more openings of the mesh bond material, wherein the adjusting modifies a Young's modulus of the mesh bond material; andbonding the first surface of the mesh bond material to a surface of a semiconductor device.2. The method of claim 1 , further comprising bonding the second surface of the mesh bond material to a surface of a substrate.3. The method of claim 1 , further comprising coating the mesh bond material with a layer of Sn to facilitate bonding with the semiconductor device.4. The method of claim 1 , wherein adjusting comprises decreasing the thickness of the mesh bond material to decrease the Young's modulus of the mesh bond material.5. The method of claim 1 , wherein adjusting comprises increasing the size of the one or more ...

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Номер записи: 59
23-04-2020 дата публикации

Bonded structures

Номер: US20200126945A1
Автор: Arkalgud R. Sitaram, Javier A. Delacruz, Liang Wang, Rajesh Katkar
Принадлежит: Invensas Bonding Technologies Inc

A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.

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Номер записи: 60
03-06-2021 дата публикации

METHOD AND APPARATUS FOR CREATING A BOND BETWEEN OBJECTS BASED ON FORMATION OF INTER-DIFFUSION LAYERS

Номер: US20210167035A1
Автор: Paknejad Seyed Amir
Принадлежит:

The present disclosure provides a method of creating a bond between a first object and a second object. For example, at least one insert may be provided at a location in a space formed between the first object and the second object. In additional, a filler material may be provided proximal to the location. An inter-diffusion layer may be formed, wherein a first portion of the inter-diffusion layer is formed by diffusion between the filler material and the at least one insert, wherein a second portion of the inter-diffusion layer is formed between the filler material and the first object, wherein a third portion of the inter-diffusion layer is formed between the filler material and the second object, wherein the first portion is coadunate with each of the second portion and third portion. 1. An electronic module comprising:a substrate;at least one chip; a first set of inserts placed inside a space between the substrate and the at least one chip,', "wherein diffusion of the second set of inserts occurs into at least one of the following: the substrate's mating surface, the at least one chip's mating surface and the first set of inserts;", 'a second set of inserts placed inside a space formed by the substrate, the at least one chip and the first set of inserts,'}], 'a plurality of inserts comprisinga gap between the first set of the inserts and the substrate; and 'wherein the diffusion results in formation of at least one of the following: a coadunate inter-diffusion layer along at least one insert of the first set of inserts to the at least one chip and a coadunate inter-diffusion layer along at least one insert of the first set of the inserts to the substrate.', 'a gap between the first set of inserts and the at least one chip,'}21. The electronic module of lain , wherein the at least one insert of the first set of inserts is comprised in at least one of the substrate's mating surface and the chip's mating surface.3. The electronic module of claim 1 , wherein the at ...

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Номер записи: 61
28-05-2015 дата публикации

Semiconductor Chip with Electrically Conducting Layer

Номер: US20150145107A1
Автор: Ng Chee Yang
Принадлежит:

A semiconductor device includes a semiconductor chip having a first main surface, a second main surface opposite to the first main surface, and a side wall surface. An electrical contact area is exposed at the side wall surface of the semiconductor chip. An electrically conducting layer covers at least partially the second main surface and the electrical contact area. 1. A semiconductor device , comprising:a semiconductor chip having a first main surface, a second main surface opposite to the first main surface, and a side wall surface;an electrical contact area exposed at the side wall surface; andan electrically conducting layer covering at least partially the second main surface and the electrical contact area.2. The semiconductor device of claim 1 , further comprising:a chip electrode arranged at the first main surface, wherein the electrical contact area is electrically connected to the chip electrode.3. The semiconductor device of claim 1 , wherein the electrically conducting layer is an electromagnetic interference shielding layer.4. The semiconductor device of claim 1 , wherein the electrically conducting layer is an antenna layer.5. The semiconductor device of claim 1 , wherein the electrically conducting layer directly connects to the electrical contact area.6. The semiconductor device of claim 2 , wherein the chip electrode is a ground electrode.7. The semiconductor device of claim 2 , wherein the electrical contact area is a side face of the chip electrode.8. The semiconductor device of claim 2 , further comprising:a metal block, wherein the electrical contact area is a side face of the metal block; anda chip-internal wiring line connecting the chip electrode to the metal block.9. The semiconductor device of claim 1 , wherein the electrically conducting layer comprises at least one of the group consisting of a metal layer claim 1 , a conducting polymer material claim 1 , a conducting ink claim 1 , a conducting paint claim 1 , a conducting molding ...

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Номер записи: 62
26-05-2016 дата публикации

WAFER LEVEL PACKAGING USING A CATALYTIC ADHESIVE

Номер: US20160148893A1
Автор: BAHL Kenneth S., KARAVAKIS Konstantine
Принадлежит:

Wafer level packaging includes a first layer of a catalytic adhesive on a wafer surface. The catalytic adhesive includes catalytic particles that will reduce electroless copper (Cu) from Cu to Cu. Metal traces are formed in trace channels within the first layer of catalytic adhesive. The trace channels extend below a surface of the first layer of the catalytic material. The trace metals traces are also in contact with integrated circuit pads on the surface of the wafer. 1. A method for wafer level packaging , comprising:{'sup': '++', 'applying a first layer of a catalytic adhesive on a wafer surface, the catalytic adhesive including catalytic particles that will reduce electroless copper (Cu) from Cu to Cu;'}curing the catalytic adhesive;forming trace channels in the first layer of catalytic adhesive, including removing a portion of the catalytic material directly over integrated circuit pads located on the wafer surface; and,performing a metal plating process to form metal traces within the trace channels and over the integrated circuit pads.2. A method as in wherein the metal plating process includes performing electroless copper bath.3. A method as in wherein the trace channels are formed using laser ablation.4. A method as in wherein the trace channels are formed by:applying resist over the first layer of catalytic adhesive;exposing and developing the resist to delineate locations of the trace channels; and,performing plasma etching to form the trace channels.5. A method as in wherein the trace channels are formed by:applying foil over the first layer of catalytic adhesive;applying resist over the foil;exposing and developing the resist to expose portions of the foil that delineate locations of the trace channels;etching the exposed portions of the foil; and,performing plasma etching to form the trace channels.6. A method as in claim 1 , additionally comprising:coating the first layer of catalytic adhesive with non-catalytic material before forming trace ...

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Номер записи: 63
15-09-2022 дата публикации

Microelectronics h-frame device

Номер: US20220289559A1
Автор: Dah-Weih Duan, Elizabeth T. Kunkee, Laura M. Woo, Martin E. RODEN
Принадлежит: Northrop Grumman Systems Corp

A microelectronics H-frame device includes: a stack of two or more substrates wherein the substrate stack comprises a top substrate and a bottom substrate, wherein bonding of the top substrate to the bottom substrate creates a vertical electrical connection between the top substrate and the bottom substrate, wherein the top surface of the top substrate comprises top substrate top metallization, wherein the bottom surface of the bottom substrate comprises bottom substrate bottom metallization; mid-substrate metallization located between the top substrate and the bottom substrate; a micro-machined top cover bonded to a top side of the substrate stack; and a micro-machined bottom cover bonded to a bottom side of the substrate stack.

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Номер записи: 64
02-06-2016 дата публикации

Methods of manufacturing a semiconductor device

Номер: US20160155862A1
Автор: Byung-lyul Park, Joo-Hee Jang, Yeun-Sang Park, Yi-koan Hong
Принадлежит: SAMSUNG ELECTRONICS CO LTD

In a method for fabricating a semiconductor, a first conductive pattern structure partially protruding upwardly from first insulating interlayer is formed in first insulating interlayer. A first bonding insulation layer pattern covering the protruding portion of first conductive pattern structure is formed on first insulating interlayer. A first adhesive pattern containing a polymer is formed on first bonding insulation layer pattern to fill a first recess formed on first bonding insulation layer pattern. A second bonding insulation layer pattern covering the protruding portion of second conductive pattern structure is formed on second insulating interlayer. A second adhesive pattern containing a polymer is formed on second bonding insulation layer pattern to fill a second recess formed on second bonding insulation layer pattern. The first and second adhesive patterns are melted. The first and second substrates are bonded with each other so that the conductive pattern structures contact each other.

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Номер записи: 65
07-05-2020 дата публикации

Method of applying conductive adhesive and manufacturing device using the same

Номер: US20200144077A1
Автор: Min-Hsun Hsieh
Принадлежит: Epistar Corp

An applying method includes the following steps. Firstly, a conductive adhesive including a plurality of conductive particles and an insulating binder is provided. Then, a carrier plate is provided. Then, a patterned adhesive is formed on the carrier plate by the conductive adhesive, wherein the patterned adhesive includes a first transferring portion. Then, a manufacturing device including a needle is provided. Then, the needle of the manufacturing device is moved to contact the first transferring portion. Then, the transferring portion is transferred to a board by the manufacturing device.

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Номер записи: 66
17-06-2021 дата публикации

Processes for adjusting dimensions of dielectric bond line materials and related films, articles and assemblies

Номер: US20210183806A1
Автор: Andrew M. Bayless, Brandon P. Wirz
Принадлежит: Micron Technology Inc

Processes for adjusting dimensions of dielectric bond line materials in stacks of microelectronic components, and related material films, articles and assemblies.

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Номер записи: 67
09-06-2016 дата публикации

Semiconductor Bonding Structure and Process

Номер: US20160163670A1
Автор: Chang Kuei-Sung, Tsai Nien-Tsung, Tsai Yi Heng, Wu Ting-Hau
Принадлежит:

A system and method for bonding semiconductor devices is provided. An embodiment comprises halting the flow of a eutectic bonding material by providing additional material of one of the reactants in a grid pattern, such that, as the eutectic material flows into the additional material, the additional material will change the composition of the flowing eutectic material and solidify the material, thereby stopping the flow. Other embodiments provide for additional layouts to put the additional material into the path of the flowing eutectic material. 1. A semiconductor device comprising:a first substrate;a second substrate; an initiating portion with a first proportion of a first eutectic component and a second eutectic component; and', 'a halting portion surrounding the initiating portion, the halting portion having a second proportion of the first eutectic component and the second eutectic component that is different from the first proportion; and, 'a eutectic bonding material interposed between the first substrate and the second substrate, the eutectic bonding material comprisinga block laterally separated from the eutectic bonding material, wherein the block comprises the first eutectic component;wherein the eutectic bonding material bonds the first substrate and the second substrate.2. The semiconductor device of claim 1 , wherein the initiating portion has a larger proportion of the second eutectic component than the halting portion.3. The semiconductor device of claim 1 , wherein the first substrate comprises a passivation layer.4. The semiconductor device of claim 3 , wherein the first substrate comprises at least one trench formed within the passivation layer.5. The semiconductor device of claim 4 , wherein the at least one trench has a depth of between about 0.5 μm and about 40 μm.6. The semiconductor device of claim 5 , wherein the eutectic bonding material is at least partially located within the at least one trench.7. The semiconductor device of claim 1 , ...

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Номер записи: 68
18-06-2015 дата публикации

Semiconductor component and method for manufacturing semiconductor component

Номер: US20150171054A1
Автор: Kenji Hirohata, Tetsuya Kugimiya, Yuu YAMAYOSE
Принадлежит: Toshiba Corp

According to an embodiment, a semiconductor component includes a circuit board; a semiconductor chip; and a bond part formed by sintering a paste containing metal particles between the circuit board and the semiconductor chip to bond the circuit board and the semiconductor chip. The bond part includes a first area immediately under the semiconductor chip and a second area adjacent to the first area. The second area has a porosity equal to or lower than that of the first area.

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Номер записи: 69
29-09-2022 дата публикации

MULTI-LAYER SHEET FOR MOLD UNDERFILL ENCAPSULATION, METHOD FOR MOLD UNDERFILL ENCAPSULATION, ELECTRONIC COMPONENT MOUNTING SUBSTRATE, AND PRODUCTION METHOD FOR ELECTRONIC COMPONENT

Номер: US20220310546A1
Автор: ASAHARA Masahiro, Kan Katsushi, Mori Daisuke, NOMURA Eiichi
Принадлежит:

[Problem] To provide a multi-layer sheet for mold underfill encapsulation, which exhibits good infiltrability between electrodes. [Solution] In order to solve the aforementioned problem, the present invention provides a multi-layer sheet for mold underfill encapsulation, which is characterized by having provided as an outermost layer thereof an (A) layer that comprises a resin composition having a local maximum loss tangent (tan δ) value of 3 or more at a measurement temperature of 125° C. for a measurement time of 0-100 seconds. 1. A multi-layer sheet for mold underfill encapsulation , the multi-layer sheet comprising the following (A)-layer as an outermost layer:(A)-layer: a layer formed from a resin composition having a local maximum value of tan δ (loss tangent) of 3 or more at a measurement temperature of 125° C. for a measurement time of 0 to 100 seconds.2. The multi-layer sheet according to claim 1 , wherein the (A)-layer contains a filler claim 1 , and the maximum particle size of the filler is 20 μm or less.3. The multi-layer sheet according to claim 1 , wherein the (A)-layer contains a curing accelerator whose median diameter (D50) at a cumulative volume of 50% in the volume particle size distribution is 10 μm or less.4. The multi-layer sheet according to claim 1 , wherein the thickness of the (A)-layer is 10 to 500 μm.5. The multi-layer sheet according to claim 1 , further comprising the following (B)-layer:(B)-layer: a layer formed from a resin composition satisfying the following Formula (1), {'br': None, 'i': 'E′≤', '40000≤α×250000 [Pa/K]\u2003\u2003(1)'}, 'in the following Formula (1), “α” represents the coefficient of thermal expansion α [ppm/K] at 80° C. or lower of a thermoset product obtained after subjecting the resin composition to a thermosetting treatment at 175° C. for one hour; and “E′” represents the storage modulus E′ [GPa] at 25° C. of the thermoset product.'}6. The multi-layer sheet according to claim 5 , wherein the ratio (B/A) of the ...

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Номер записи: 70
22-06-2017 дата публикации

Methods for bonding substrates

Номер: US20170173934A1
Автор: Ashish Bhatnagar, Gangadhar SHEELAVANT, Kadthala Ramaya Narendrnath, Monika Agarwal
Принадлежит: Applied Materials Inc

Methods for fabricating and refurbishing an assembly are disclosed herein. The method begins by applying an adhesive layer onto a first substrate. A second substrate is placed onto the adhesive layer, thereby securing the two substrates together, the adhesive layer bounding at least one side of a channel that extends laterally between the substrates to an exterior of the assembly. And, the substrates and the adhesive layer are subjected to a bonding procedure and allowing outgassing of volatiles from the adhesive layer to escape from between the substrates through the channel, wherein the substrates bonded by the adhesive layer form a component for a semiconductor vacuum processing chamber.

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Номер записи: 71
01-07-2021 дата публикации

Bonded structures

Номер: US20210202428A1
Автор: Arkalgud R. Sitaram, Javier A. Delacruz, Liang Wang, Rajesh Katkar
Принадлежит: Invensas Bonding Technologies Inc

A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.

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Номер записи: 72
21-06-2018 дата публикации

BONDED STRUCTURES

Номер: US20180174995A1
Автор: Delacruz Javier A., Katkar Rajesh, SITARAM Arkalgud R., Wang Liang
Принадлежит:

A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements. 1. A bonded structure comprising:a first element having a first interface feature;a second element having a second interface feature; andan integrated device coupled to or formed with the first element or the second element,the first interface feature directly bonded to the second interface feature to define an interface structure, the interface structure disposed around the integrated device to define an effectively closed profile to connect the first and second elements, the effectively closed profile substantially sealing an interior region of the bonded structure from gases diffusing into the interior region.2. The bonded structure of claim 1 , wherein the first interface feature comprises a first conductive interface feature and the second interface feature comprises a second conductive interface feature.3. (canceled)4. The bonded structure of claim 1 , wherein the effectively closed profile comprises a completely closed shape.5. (canceled)6. The bonded structure of claim 1 , wherein the first element comprises a cap and the second element comprises a carrier claim 1 , the cap bonded to the carrier to define a cavity in which the integrated device is disposed.7. The bonded structure of claim 1 , wherein the first element comprises a first integrated device die and the second element comprises a second integrated device die.8. (canceled)915387385212016. The bonded structure of claim 1 , wherein the first interface feature ...

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Номер записи: 73
02-07-2015 дата публикации

CHIP STACK STRUCTURE USING CONDUCTIVE FILM BRIDGE ADHESIVE TECHNOLOGY

Номер: US20150187735A1
Автор: Liao Chien-Ko, Lin Tzu-Chih
Принадлежит: LINGSEN PRECISION INDUSTRIES, LTD.

A chip stack structure using conductive film bridge adhesive technology comprises a substrate, a first chip, at least one bridge element, a conductive film, and a second chip. The first chip is electrically connected to a first electrode of the substrate. The at least one bridge element has a first bridge surface and a second bridge surface at two ends, and the first bridge surface and the second bridge surface are electrically connected to the first chip and a second electrode of the substrate, respectively. The conductive film is electrically connected to the first bridge surface of the at least one bridge element. The second chip is stacked and electrically connected to the conductive film. Thus, the structure of the present invention not only facilitates the ease of stacking the chips but also increases the effectiveness of the chips heat dissipation and ability of withstanding electrical current. 1. A chip stack structure using conductive film bridge adhesive technology , comprising:a substrate comprising a first electrode and a second electrode;a first chip, electrically connected to the first electrode of the substrate;at least one bridge element having a first bridge surface and a second bridge surface at two ends, the first bridge surface and the second bridge surface being electrically connected to the first chip and the second electrode of the substrate, respectively;a conductive film, electrically connected to the first bridge surface of the at least one bridge element; anda second chip, stacked and electrically connected to the conductive film,wherein the first chip has a first connecting surface and a second connecting surface, the fast connecting surface is disposed on the first electrode of the substrate and the first bridge surface of the at least one bridge element is connected to the second connecting surface.2. (canceled)3. The chip stack structure using conductive film bridge adhesive technology in claim 1 , wherein the substrate further ...

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Номер записи: 74
08-07-2021 дата публикации

Package structure and method of manufacturing the same

Номер: US20210210464A1
Автор: Chi-Yang Yu, Chien-Hsun Lee, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min LIANG
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A package structure and a method of forming the same are provided. The package structure includes a first die and a second die, a first encapsulant, a second encapsulant and a RDL structure. The first die includes a first connector and a first protection layer covering sidewalls of the first connector, and the second die includes a second connector. The first encapsulant is at least disposed laterally between the first die and the second die to encapsulate first sidewalls of the first die and the second die that faces each other. The second encapsulant encapsulates second sidewalls of the first die and the second die. The RDL structure is disposed on and electrically connected to the first die and the second die. The top surfaces of the first protection layer, the first encapsulant, and the second encapsulant are in contact with a bottom surface of the RDL structure.

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Номер записи: 75
30-06-2016 дата публикации

Wafer to Wafer Bonding Process and Structures

Номер: US20160190089A1
Автор: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Bonded structures and method of forming the same are provided. A conductive layer is formed on a first surface of a bonded structure, the bonded structure including a first substrate bonded to a second substrate, the first surface of the bonded structure being an exposed surface of the first substrate. A patterned mask having first openings and second openings is formed on the conductive layer, the first openings and the second openings exposing portions of the conductive layer. First portions of first bonding connectors are formed in the first openings and first portions of second bonding connectors are formed in the second openings. The conductive layer is patterned to form second portions of the first bonding connectors and second portions of the second bonding connectors. The bonded structure is bonded to a third substrate using the first bonding connectors and the second bonding connectors.

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Номер записи: 76
05-07-2018 дата публикации

Package structure and manufacturing method thereof

Номер: US20180190558A1
Автор: Hung-Hsin Hsu, Nan-Chun Lin
Принадлежит: Powertech Technology Inc

A manufacturing method of a package structure includes at least the following steps. A plurality of conductive connectors are formed on a circuit layer. The circuit layer includes a central region and a peripheral region electrically connected to the central region. A chip is disposed on the central region of the circuit layer. The chip includes an active surface at a distance from the circuit layer and a sensing area on the active surface. An encapsulant is formed on the circuit layer to encapsulate the chip and the conductive connectors. A redistribution layer is formed on the encapsulant to electrically connect the chip and the conductive connectors. The redistribution layer partially covers the chip and includes a window corresponding to the sensing area of the chip. A package structure is also provided.

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Номер записи: 77
25-09-2014 дата публикации

Semiconductor device, method for manufacturing the same, and electronic device

Номер: US20140284749A1
Автор: Hiroshi Ozaki, Satoru Wakiyama
Принадлежит: Sony Corp

Disclosed herein is a semiconductor device including: a first semiconductor chip having an electronic circuit section and a first connecting section formed on one surface thereof; a second semiconductor chip having a second connecting section formed on one surface thereof, the second semiconductor chip being mounted on the first semiconductor chip with the first and the second connecting sections connected to each other by a bump; a dam formed to fill a gap between the first and the second semiconductor chips on a part of an outer edge of the second semiconductor chip, the part of the outer edge being on a side of a region of formation of the electronic circuit section; and an underfill resin layer filled into the gap, protrusion of the resin layer from the outer edge of the second semiconductor chip to a side of the electronic circuit section being prevented by the dam.

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Номер записи: 78
11-06-2020 дата публикации

Semiconductor device

Номер: US20200185285A1
Автор: Katsumi Miyawaki, Koichiro Nishizawa, Shinsuke Watanabe, Toshihiko Shiga, Yoshitsugu Yamamoto
Принадлежит: Mitsubishi Electric Corp

A semiconductor device according to the present invention includes: a substrate; a heat generating portion provided on the substrate; a cap substrate provided above the substrate so that a hollow portion is provided between the substrate and the cap substrate; and a reflection film provided above the heat generating portion and reflecting a medium wavelength infrared ray. The reflection film reflects the infrared ray radiated to the cap substrate side through the hollow portion due to the temperature increase of the heat generating portion, so that the temperature increase of the cap substrate side can be suppressed. Because of this function, even if mold resin is provided on the cap substrate, increase of the temperature of the mold resin can be suppressed.

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Номер записи: 79
02-10-2014 дата публикации

Anisotropic conductive film and method of making conductive connection

Номер: US20140290059A1
Автор: Takeaki Kawashima
Принадлежит: Fujifilm Corp

An anisotropic conductive film includes: an insulation region having a planer shape and containing an insulating filler at a first content rate; and a plurality of conductive particle holding regions arranged in the insulation region, the conductive particle holding regions holding conductive particles and containing the insulating filler at a second content rate lower than the first content rate, the conductive particle holding regions being arranged discretely in a planar direction of the insulation region. A method of making conductive connection between a first terminal arranged on a first member and a second terminal arranged on a second member includes: preliminarily tacking the anisotropic conductive film to the first member; holding the first and second members such that the first and second terminals face to each other across the preliminarily tacked anisotropic conductive film; pressing the first and second members to each other; and heating the anisotropic conductive film.

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Номер записи: 80
13-07-2017 дата публикации

Porous underfill enabling rework

Номер: US20170200659A1
Автор: Brian BURG, Gerd Schlottig, Jeffrey Gelorme, Jonas Zuercher, Michael Gaynes, Thomas Brunschwiler
Принадлежит: International Business Machines Corp

The disclosure generally relates to methods for manufacturing a filled gap region or cavity between two surfaces forming a device microchip. In one embodiment, the cavity results from two surfaces, for example, a PCB and a chip or two chips. More specifically, the disclosure relates to a method of manufacture and the resulting apparatus having porous underfill to enable rework of the electrical interconnects of a microchip on a multi-chip module. In one embodiment, the disclosure builds on the thermal underfill concept and achieves high thermal conductivity by the use of alumina fillers. Alternatively, other material such as silica filler particles may be selected to render the underfill a poor thermal conductive. In one embodiment, the disclose is concerned with reworkability of the material.

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Номер записи: 81
13-07-2017 дата публикации

ELECTRONIC COMPONENT

Номер: US20170200693A1
Автор: Fujii Yoshimaro, OGURI Hiroshi, Sakamoto Akira, Taguchi Tomoya
Принадлежит: HAMAMATSU PHOTONICS K.K.

An electronic component includes a base, a laminate of a plurality of conductive metal material layers, and a solder layer made of Au—Sn alloy solder. The laminate is disposed on the base. The solder layer is disposed on the laminate. The laminate includes a surface layer made of Au as the conductive metal material layer constituting an outermost layer. The surface layer includes a solder layer-disposing region in which the solder layer is disposed and a solder layer-empty region in which the solder layer is not disposed. The solder layer-disposing region and the solder layer-empty region are spatially separated from each other. 1. An electronic component comprising:a base;a laminate of a plurality of conductive metal material layers, the laminate being disposed on the base; anda solder layer made of Au—Sn alloy solder, the solder layer being disposed on the laminate, whereinthe laminate includes a surface layer made of Au as the conductive metal material layer constituting an outermost layer,the surface layer includes a solder layer-disposing region in which the solder layer is disposed and a solder layer-empty region in which the solder layer is not disposed, andthe solder layer-disposing region and the solder layer-empty region are spatially separated from each other.2. The electronic component according to claim 1 , whereinthe solder layer-disposing region is located inside the solder layer-empty region to be surrounded by the solder layer-empty region, and the whole circumference of the solder layer-disposing region is spatially separated from the solder layer-empty region.3. The electronic component according to claim 1 , whereinthe solder layer-disposing region and the solder layer-empty region are spatially separated from each other by a slit formed in the surface layer.4. The electronic component according to claim 1 , whereinthe solder layer is disposed on the laminate through a barrier layer comprising Pt. The present invention relates to an electronic ...

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Номер записи: 82
30-07-2015 дата публикации

STRUCTURE AND FORMATION METHOD OF CHIP PACKAGE STRUCTURE

Номер: US20150214192A1
Автор: LIN Tzu-Hung
Принадлежит:

A chip package structure and a method for forming a chip package are provided. The chip package structure includes a chip package over a printed circuit board and multiple conductive bumps between the chip package and the printed circuit board. The chip package structure also includes one or more thermal conductive elements between the chip package and the printed circuit board. The thermal conductive element has a thermal conductivity higher than a thermal conductivity of each of the conductive bumps. 1. A chip package structure , comprising:a chip package over a printed circuit board;a plurality of conductive bumps between the chip package and the printed circuit board; andat least one thermal conductive element between the chip package and the printed circuit board, wherein the thermal conductive element has a thermal conductivity higher than a thermal conductivity of each of the conductive bumps.2. The chip package structure as claimed in claim 1 , wherein the conductive bumps comprise solder bumps claim 1 , solder balls claim 1 , or a combination thereof3. The chip package structure as claimed in claim 1 , wherein the thermal conductive element comprises a metal foil.4. The chip package structure as claimed in claim 1 , wherein the thermal conductive element comprises a copper foil.5. The chip package structure as claimed in claim 1 , further comprising:a first bonding layer between the thermal conductive element and the chip package; anda second bonding layer between the thermal conductive element and the printed circuit board.6. The chip package structure as claimed in claim 5 , wherein the first bonding layer and the second bonding layer are made of a solder material.7. The chip package structure as claimed in claim 5 , wherein the first bonding layer and the second bonding layer are made of different solder materials.8. The chip package structure as claimed in claim 7 , wherein the first bonding layer has a melting point higher than that of the second ...

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Номер записи: 83
19-07-2018 дата публикации

Semiconductor device, mechanical quantity measuring device, and semiconductor device fabricating method

Номер: US20180202883A1
Автор: Atsuo Soma, Daisuke Terada, Hanae Shimokawa, Hiroshi Onuki, Junji Onozuka, Mizuki Shibata, Shosaku Ishihara
Принадлежит: HITACHI AUTOMOTIVE SYSTEMS LTD

A semiconductor device includes a metal body; a bonding layer placed on the metal body; and a semiconductor chip placed on the bonding layer. The bonding layer includes a filler-containing first layer formed between the metal body and the semiconductor chip and a second layer bonded to the first layer and the semiconductor chip. The second layer has a thermal expansion coefficient higher than that of the first layer.

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Номер записи: 84
28-07-2016 дата публикации

Selective micro device transfer to receiver substrate

Номер: US20160219702A1
Автор: Ehsan Fathi, Gholamreza Chaji
Принадлежит: Ehsan Fathi, Gholamreza Chaji

A method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. Micro devices being attached to a donor substrate with a donor force. The donor substrate and receiver substrate are aligned and brought together so that selected micro devices meet corresponding contact pads. A receiver force is generated to hold selected micro devices to the contact pads on the receiver substrate. The donor force is weakened and the substrates are moved apart leaving selected micro devices on the receiver substrate. Several methods of generating the receiver force are disclosed, including adhesive, mechanical and electrostatic techniques.

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Номер записи: 85
05-08-2021 дата публикации

SELECTIVE TRANSFER OF MICRO DEVICES

Номер: US20210243894A1
Автор: Chaji Gholamreza
Принадлежит: VueReal Inc.

What is disclosed is a method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. Micro devices being attached to a donor substrate with a donor force. The donor substrate and receiver substrate are aligned and brought together so that selected micro devices meet corresponding contact pads. A receiver force is generated to hold selected micro devices to the contact pads on the receiver substrate. The donor force is weakened and the substrates are moved apart leaving selected micro devices on the receiver substrate. Several methods of generating the receiver force are disclosed, including adhesive, mechanical and electrostatic techniques. 1. A method of transferring a micro device , the method comprising:positioning a donor substrate comprising the micro device proximal to a receiver substrate, wherein the receiver substrate comprises a force modulator element creating transfer force for transferring the selected micro devices; andreducing the effect of said force generated by the force modulator element on unwanted micro devices.2. The method of claim 1 , wherein selectively reducing the effect of a force generated by the force modulator element comprises generating a reverse polarity of force surrounding the force modulating element.3. A method of transferring micro devices claim 1 , the method comprising:positioning a donor substrate comprising micro devices proximal to a receiver substrate, wherein the receiver substrate comprises a current curable bonding layer; andtransferring the micro devices by applying current to the bonding layer of selected micro devices.4. The method of claim 3 , wherein the current is applied using a circuit in the receiver substrate.5. The method of claim 3 , wherein the circuit in the receiver substrate is shared with a circuit associated the driving or controlling the selected micro devices.6. The method of claim 3 , wherein the bonding layer comprises one or more contact pads and ...

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Номер записи: 86
13-08-2015 дата публикации

Hybrid thermal interface material for ic packages with integrated heat spreader

Номер: US20150228553A1
Автор: Mehdi Saeidi, Sam Ziqun Zhao
Принадлежит: Broadcom Corp

Flip chip packages are described that include two or more thermal interface materials (TIMs). A die is mounted to a substrate by solder bumps. A first TIM is applied to the die, and has a first thermal resistance. A second TIM is applied to the die and/or the substrate, and has a second thermal resistance that is greater than the first thermal resistance. An open end of a heat spreader lid is mounted to the substrate such that the die is positioned in an enclosure formed by the heat spreader lid and substrate. The first TIM and the second TIM are each in contact with an inner surface of the heat spreader lid. A ring-shaped stiffener may surround the die and be connected between the substrate and heat spreader lid by the second TIM.

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Номер записи: 87
04-08-2016 дата публикации

Electrode connection structure and electrode connection method

Номер: US20160225730A1
Автор: Kohei Tatsumi
Принадлежит: WASEDA UNIVERSITY

An electrode connection structure includes: a first electrode of an electrical circuit; and a second electrode of the electrical circuit that is electrically connected to the first electrode. The first and second electrodes are oppositely disposed in direct or indirect contact with each other. A plated lamination is substantially uniformly formed by plating process from a surface of a contact region and opposed surfaces of the first and second electrodes. A void near the surface of the contact region is filled by formation of the plated lamination. Portions of the plated lamination formed from the opposed surfaces of the first and second electrodes in a region other than the contact region are not joined together.

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Номер записи: 88
16-08-2018 дата публикации

RECONSTITUTED INTERPOSER SEMICONDUCTOR PACKAGE

Номер: US20180233440A1
Автор: Hu Kunzhong, Khan Rezaur Rahman, LAW Edward, Zhao Sam Ziqun
Принадлежит: Avago Technologies General IP (Singapore) Pte. Ltd.

A reconstituted semiconductor package and a method of making a reconstituted semiconductor package are described. An array of die-attach substrates is formed onto a carrier. A semiconductor device is mounted onto a first surface of each of the die-attach substrates. An interposer substrate is mounted over each of the semiconductor devices. The interposer substrates are electrically connected to the first surface of the respective die-attach substrates. A molding compound is filled in open spaces within and between the interposer substrates mounted to their respective die-attach substrates to form an array of reconstituted semiconductor packages. Electrical connections are mounted to a second surface of the die-attach substrates. The array of reconstituted semiconductor packages is singulated through the molding compound between each of the die-attach substrates and respective mounted interposer substrates. 1. A reconstituted interposer package comprising:an interposer substrate electrically mounted to a first surface of a reconstituted die-attach substrate and straddling an integrated circuit mounted on the first surface of the reconstituted die-attach substrate;a molding compound filled within open spaces between the interposer substrate and the first surface of the reconstituted die-attach substrate, wherein singulated surfaces of the molding compound reside along edges of the interposer substrate and the reconstituted die-attach substrate; andexternal electrical connections formed in a grid array on a second surface of the reconstituted die-attach substrate.2. The reconstituted interposer package of claim 1 , wherein one or more of the reconstituted interposer packages are assembled into one of a baseband microprocessor claim 1 , a set-top-box microprocessor claim 1 , a server message block microprocessor claim 1 , or an encryption/security microprocessor.3. The reconstituted semiconductor package of claim 1 , wherein the molding compound covers side walls of the ...

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Номер записи: 89
16-08-2018 дата публикации

Semiconductor apparatus and method for preparing the same

Номер: US20180233479A1
Автор: Chin-Lung Chu, Po-Chun Lin
Принадлежит: Nanya Technology Corp

The present disclosure is directed to a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The semiconductor devices have conductive portions with higher coefficient of thermal expansion than their dielectric portions. By forming the depression to provide a space for the volume expansion of the conductive portion with higher coefficient of thermal expansion during the subsequent thermal treating process of the fusion bonding, the semiconductor apparatus formed of semiconductor devices by the fusion bonding technique does not exhibit a lateral protrusion into the interface between the two dielectric portions. As a result, the failure of the electrical function due to the lateral protrusion is effectively eliminated.

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Номер записи: 90
26-08-2021 дата публикации

Lead frame for improving adhesive fillets on semiconductor die corners

Номер: US20210265245A1
Автор: Jefferson Talledo, Maiden Grace Maming, Rennier Rodriguez
Принадлежит: STMicroelectronics Inc Philippines

The present disclosure is directed to a lead frame including a die pad with cavities, and methods for attaching a semiconductor die to the lead frame. The cavities allow for additional adhesive to be formed on the die pad at the corners of the semiconductor die, and prevent the additional adhesive from overflowing on to active areas of the semiconductor die.

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Номер записи: 91
01-08-2019 дата публикации

COOLING BOND LAYER AND POWER ELECTRONICS ASSEMBLIES INCORPORATING THE SAME

Номер: US20190237389A1
Автор: Dede Ercan Mehmet, JOSHI Shailesh N.
Принадлежит:

A cooling bond layer for a power electronics assembly is provided. The cooling bond layer includes a first end, a second end spaced apart from the first end, a metal matrix extending between the first end and the second end, and a plurality of micro-channels extending through the metal matrix from the first end to the second end. The plurality of micro-channels are configured for a cooling fluid to flow through and remove heat from the cooling bond layer. In some embodiments, the plurality of micro-channels are cylindrical shaped micro-channels. In such embodiments, the plurality of micro-channels may have a generally constant average inner diameter along a thickness of the cooling bond layer. In the alternative, the plurality of micro-channels may have a graded average inner diameter along a thickness of the cooling bond layer. In other embodiments, the plurality of micro-channels may have a wire mesh layered structure. 1. A bond layer for a power electronics assembly comprising: a first end and a second end spaced apart from the first end;', 'a metal matrix extending between the first end and the second end; and', 'a plurality of micro-channels extending through the metal matrix from the first end to the second end;, 'a cooling bond layer comprisingwherein the plurality of micro-channels extend from the first end to the second end of the cooling bond layer and comprise one of a constant average inner diameter or a graded average inner diameter as a function of a thickness of the cooling bond layer, and wherein the plurality of micro-channels are configured for a cooling fluid to flow through and remove heat from the cooling bond layer.2. The bond layer of claim 1 , wherein the plurality of micro-channels comprise a plurality of cylindrical shaped micro-channels.3. (canceled)4. (canceled)5. The bond layer of claim 2 , wherein the plurality of cylindrical shaped micro-channels comprise a plurality of tubes extending through the metal matrix.6. The bond layer of ...

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Номер записи: 92
01-09-2016 дата публикации

JOINING SILVER SHEET, METHOD FOR MANUFACTURING SAME, AND METHOD FOR JOINING ELECTRONIC PART

Номер: US20160254243A1
Автор: Endoh Keiichi, KURITA Satoru, Miyoshi Hiromasa
Принадлежит:

A joining silver sheet with high joining strength contains silver particles having a particle diameter of from 1 to 250 nm integrated by sintering, and has a capability of further undergoing sintering on heating and retaining the silver sheet at a temperature range of from Tto T(° C.) satisfying 270 £ T Подробнее

Номер записи: 93
09-09-2021 дата публикации

METHOD OF APPLYING CONDUCTIVE ADHESIVE AND MANUFACTURING DEVICE USING THE SAME

Номер: US20210280436A1
Автор: Hsieh Min-Hsun
Принадлежит:

An applying method includes the following steps. Firstly, a conductive adhesive including a plurality of conductive particles and an insulating binder is provided. Then, a carrier plate is provided. Then, a patterned adhesive is formed on the carrier plate by the conductive adhesive, wherein the patterned adhesive includes a first transferring portion. Then, a manufacturing device including a needle is provided. Then, the needle of the manufacturing device is moved to contact the first transferring portion. Then, the transferring portion is transferred to a board by the manufacturing device. 1. A manufacturing system , comprising:a carrier plate configured to accommodate an adhesive material; anda needle array device arranged on the carrier plate, and comprising a plate and a plurality of needles associated with the plate;wherein the plurality of needles is configured to approach the carrier plate for capturing portions of the adhesive material from the carrier plate, andwherein the adhesive material comprises a plurality of conductive particles and an insulating binder wherein the plurality of conductive particles is dispersed.2. The manufacturing system according to claim 1 , wherein the adhesive material has a patterned shape which includes a plurality of transferring portions separated from each other.3. The manufacturing system according to claim 1 , wherein the adhesive material is provided in a linear arrangement.4. The manufacturing system according to claim 1 , wherein the needle array device comprises a base therein the plurality of needles is fixed claim 1 , and a scraping portion disposed between the base and the plurality of needles and configured to scrap the adhesive material from the plurality of needles.5. The manufacturing system according to claim 4 , wherein the scraping portion is movable along with a direction parallel to the plurality of needles.6. The manufacturing system according to claim 4 , wherein the scraping portion is movable downward ...

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Номер записи: 94
09-09-2021 дата публикации

ANISOTROPIC CONDUCTIVE FILM AND MANUFACTURING METHOD THEREOF

Номер: US20210280548A1
Автор: AKUTSU Yasushi, SARUYAMA Kenichi
Принадлежит: DEXERIALS CORPORATION

An anisotropic conductive film includes a conductive particle array layer in which a plurality of conductive particles are arrayed in a prescribed manner and held in an insulating resin layer. The anisotropic conductive film has a direction in which a thickness distribution, around the individual conductive particle, of the insulating resin layer holding the array of the conductive particles is asymmetric with respect to the conductive particle. The direction in which the thickness distribution is asymmetric is aligned in the same direction in the plurality of conductive particles. When an electronic component is mounted using this anisotropic conductive film, short circuits and conductive failure can be reduced. 1. An anisotropic conductive film for connecting electronic components via an anisotropic conductive connection , the anisotropic conductive film comprising:a conductive particle array layer in which a plurality of conductive particles are arrayed in a prescribed manner and held in an insulating resin layer, whereinthe insulating resin layer comprises a resin that is present around an individual conductive particle,the resin has a decreasing distribution in which a resin amount decreases in area, the area extending at an incline towards the conductive particle in a direction from a first plane at one end of the conductive particle to a second plane at an opposite end of the conductive particle,an amount of the resin present at the first plane is larger than an amount of resin present at the second plane, andthe anisotropic conductive film is formed before connecting the electronic components via the anisotropic conductive connection.2. The anisotropic conductive film according to claim 1 , wherein in a cross section of the anisotropic conductive film when the anisotropic conductive film is cut in a thickness direction thereof passing through a center of the conductive particle claim 1 , along the direction in which a resin amount decreases claim 1 , an area ...

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Номер записи: 95
27-11-2014 дата публикации

Integrated bondline spacers for wafer level packaged circuit devices

Номер: US20140346643A1
Автор: Adam M. Kennedy, Buu Diep, Roland Gooch, Stephen H. Black, Thomas Allan KOCIAN
Принадлежит: Raytheon Co

A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

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Номер записи: 96
01-10-2015 дата публикации

Die interconnect

Номер: US20150279803A1
Автор: Coenraad Cornelis Tak, Hendrik Bouman, Leonardus Antonius Elisabeth van Gemert, Marten Oldsen
Принадлежит: NXP BV

One example embodiment discloses a chip having a chip area, wherein the chip area includes: an overhang area; a rigid coupling area, having a set of rigid coupling points, located on one side of the overhang area; and a flexible coupling area, having a set of flexible coupling points, located on a side of the overhang area opposite to the a rigid coupling area. Another example embodiment discloses a method for fabricating a die interconnect, comprising: fabricating a rigid coupler area, having a set of rigid coupler points, within a chip having a chip area; defining an overhang area within the chip area and abutted to the rigid coupler area; and fabricating a flexible coupler area, having a set of flexible coupler points, within the chip area abutted to a side of the overhang area opposite to the rigid coupler area.

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Номер записи: 97
22-09-2016 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20160276312A1
Автор: Ken Muramatsu, Mika Kiritani, Shinya Shimizu
Принадлежит: Toshiba Corp

A semiconductor device includes a wiring substrate, a first semiconductor chip provided on the wiring substrate, a supporting member provided on the wiring substrate in a region which does not overlap with the first semiconductor chip in a plan view when viewed from a direction perpendicular to the wiring substrate, a resin member provided on the first semiconductor chip, and a second semiconductor chip provided on the supporting member and the resin member. A method for manufacturing a semiconductor device includes providing a first semiconductor chip in a first region on a wiring substrate, providing a supporting member in a second region on the wiring substrate, providing a resin member in at least a portion on the first semiconductor chip, and providing a second semiconductor chip on the supporting member and the resin member.

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Номер записи: 98
01-10-2015 дата публикации

Method of manufacturing light-emitting device, light-emitting device, and projector

Номер: US20150280090A1
Автор: Kunihiko Aoyagi, Shuichi Tanaka
Принадлежит: Seiko Epson Corp

A method of manufacturing a light-emitting device, includes: disposing a first conductive paste on a substrate and sintering the first conductive paste to forma first bonding layer; disposing a second conductive paste on a semiconductor light-emitting element and sintering the second conductive paste to form a second bonding layer; polishing surfaces of the first bonding layer and the second bonding layer; and causing a third conductive paste to intervene between the first bonding layer and the second bonding layer and sintering the third conductive paste to bond the first bonding layer and the second bonding layer together.

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Номер записи: 99
13-08-2020 дата публикации

Thermal management solutions for integrated circuit packages

Номер: US20200260609A1
Автор: Amitesh Saha, Betsegaw K. Gebrehiwot, Je-Young Chang
Принадлежит: Intel Corp

A heat dissipation device may be formed having a planar structure with a first surface and a surface area enhancement structure projecting from or extending into the first surface of the planar structure. In one embodiment, an integrated circuit package may be formed with the heat dissipation device, wherein the heat dissipation device and at least one integrated circuit device are brought into thermal contact with a thermal interface material between the at least one integrated circuit device and the heat dissipation device and wherein the surface area enhancement structure of the heat dissipation device directly contacts the thermal interface material.

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Номер записи: 100