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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 5709. Отображено 100.
26-01-2012 дата публикации

Substrate for semiconductor element, method for manufacturing substrate for semiconductor element, and semiconductor device

Номер: US20120018867A1
Принадлежит: Toppan Printing Co Ltd

Provided is a manufacturing method of a semiconductor element substrate including: a step of forming a first photoresist pattern on a first surface of a metallic plate, to form a semiconductor element mounting part, a semiconductor element electrode connection terminal, a wiring, an outer frame part, and a slit; a step of forming a second photoresist pattern on the second surface of the metallic plate; a step of forming the slit by half etching to connect the metallic chip with a four corners of the outer frame part; a step of forming a plurality of concaved parts on the second surface of the metallic plate; a step of forming a resin layer by injecting a resin to the plurality of concaved parts; and a step of etching the first surface of the metallic plate and forming the semiconductor element electrode connection terminal and the outer frame.

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02-02-2012 дата публикации

Power Semiconductor Module, Method for Producing a Power Semiconductor Module and a Housing Element for a Power Semiconductor Module

Номер: US20120025393A1
Принадлежит: INFINEON TECHNOLOGIES AG

A power semiconductor module includes a housing element into which one or more connecting lugs are inserted. Each connecting lug has a foot region on the topside of which one or more bonding connections can be produced. In order to fix the foot regions, press-on elements are provided, which press against the end of the connecting lug.

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09-02-2012 дата публикации

Gas delivery system for reducing oxidation in wire bonding operations

Номер: US20120031877A1
Принадлежит: Kulicke and Soffa Industries Inc

A wire bonding machine is provided. The wire bonding machine includes a bonding tool and an electrode for forming a free air ball on an end of a wire extending through the bonding tool where the free air ball is formed at a free air ball formation area of the wire bonding machine. The wire bonding machine also includes a bond site area for holding a semiconductor device during a wire bonding operation. The wire bonding machine also includes a gas delivery mechanism configured to provide a cover gas to: (1) the bond site area whereby the cover gas is ejected through at least one aperture of the gas delivery mechanism to the bond site area, and (2) the free air ball formation area.

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09-02-2012 дата публикации

Method for Forming a Patterned Thick Metallization atop a Power Semiconductor Chip

Номер: US20120034775A1
Автор: Il Kwan Lee
Принадлежит: Individual

A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK 1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK 2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK 1 +TK 2 ; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.

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19-04-2012 дата публикации

Composite alloy bonding wire and manufacturing method thereof

Номер: US20120093681A1
Автор: Jun-Der LEE
Принадлежит: Individual

A manufacturing method for a composite alloy bonding wire and products thereof. A primary material of Ag is melted in a vacuum melting furnace, and then a secondary metal material of Pd is added into the vacuum melting furnace and is co-melted with the primary material to obtain an Ag—Pd alloy solution. The obtained Ag—Pd alloy solution is drawn to obtain an Ag—Pd alloy wire. The Ag—Pd alloy wire is then drawn to obtain an Ag—Pd alloy bonding wire with a predetermined diameter.

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07-06-2012 дата публикации

Semiconductor Device

Номер: US20120139130A1
Принадлежит: Renesas Electronics Corp

The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

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14-06-2012 дата публикации

Brace for long wire bond

Номер: US20120145446A1
Принадлежит: FREESCALE SEMICONDUCTOR INC

An electrical connection includes a first wire bonded to adjacent bond pads proximate to an edge of a die and a second wire having one end bonded to a die bond pad distal to the die edge and a second end bonded to a lead finger of a lead frame or a connection pad of a substrate. The second wire crosses and is supported by the first wire. The first wire acts as a brace that prevents the second wire from touching the edge of the die. The first wire also prevents the second wire from excessive lateral movement during encapsulation.

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05-07-2012 дата публикации

Semiconductor device

Номер: US20120168927A1
Автор: Shingo Itoh
Принадлежит: Sumitomo Bakelite Co Ltd

A semiconductor device is configured that two or more semiconductor elements are stacked and mount on a lead frame, the aforementioned lead frame is electrically joined to the semiconductor element with a wire, and the semiconductor element, the wire and an electric junction are encapsulated with a cured product of an epoxy resin composition for encapsulating semiconductor device, and that the epoxy resin composition for encapsulating semiconductor device contains (A) an epoxy resin; (B) a curing agent; and (C) an inorganic filler, and that the (C) inorganic filler contains particles having particle diameter of equal to or smaller than two-thirds of a thinnest filled thickness at a rate of equal to or higher than 99.9% by mass.

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02-08-2012 дата публикации

Semiconductor device and method of manufacturing the semiconductor device

Номер: US20120193791A1
Автор: Ryota Seno
Принадлежит: Nichia Corp

Disclosed are: a semiconductor device that comprises a semiconductor element to which a plurality of wires are bonded, wherein bonding strength of the wires is high and sufficient bonding reliability is achieved; and a method for manufacturing the semiconductor device. Specifically disclosed is a semiconductor device which is characterized by comprising a first wire that has one end bonded onto an electrode and the other end bonded to a second bonding point that is out of the electrode, and a second wire that has one end bonded onto the first wire on the electrode and the other end bonded to a third bonding point that is out of the electrode. The semiconductor device is also characterized in that the bonded portion of the first-mentioned end of the second wire covers at least apart of the upper surface and the lateral surface of the first wire.

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30-08-2012 дата публикации

Semiconductor apparatus, method for manufacturing the same and electric device

Номер: US20120217660A1
Принадлежит: Fujitsu Ltd

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

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04-10-2012 дата публикации

Integrated circuit package including miniature antenna

Номер: US20120249380A1
Принадлежит: Fractus SA

The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna.

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25-10-2012 дата публикации

Semiconductor device

Номер: US20120267682A1
Принадлежит: Renesas Electronics Corp

A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.

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25-10-2012 дата публикации

Light-emitting device, white light-emitting device, illuminator, and image display

Номер: US20120267997A1
Принадлежит: Mitsubishi Chemical Corp

To achieve a light-emitting device emitting light with high brightness, closer to natural light, and less color shift due to a small change in intensity of emitted light, in a light-emitting device including a light source emitting light by driving current and at least one wavelength-converting material absorbing at least part of the light from the light source and emitting light having a different wavelength, the color coordinate x 1 (17.5) and the color coordinate y 1 (17.5) of the light emitted at a driving current density of 17.5 A/cm 2 and the color coordinate x 1 (70) and the color coordinate y 1 (70) of the light emitted at a driving current density of 70 A/cm 2 satisfy the following Expressions (D) and (E): −0.006≦ x 1 (17.5)− x 1 (70)≦0.006  (D), −0.006≦ y 1 (17.5)− y 1 (70)≦0.006  (E).

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15-11-2012 дата публикации

Method for Making Solder-top Enhanced Semiconductor Device of Low Parasitic Packaging Impedance

Номер: US20120289001A1
Принадлежит: Alpha and Omega Semiconductor Ltd

A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

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13-12-2012 дата публикации

Impedence controlled packages with metal sheet or 2-layer rdl

Номер: US20120313228A1
Принадлежит: Tessera LLC

A microelectronic assembly includes an interconnection element, a conductive plane, a microelectronic device, a plurality of traces, and first and second bond elements. The interconnection element includes a dielectric element, a plurality of element contacts, and at least one reference contact thereon. The microelectronic device includes a front surface with device contacts exposed thereat. The conductive plane overlies a portion of the front surface of the microelectronic device. Traces overlying a surface of the conductive plane are insulated therefrom and electrically connected with the element contacts. The traces also have substantial portions spaced a first height above and extending at least generally parallel to the conductive plane, such that a desired impedance is achieved for the traces. First bond element electrically connects the at least one conductive plane with the at least one reference contact. Second bond elements electrically connect device contacts with the traces.

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20-12-2012 дата публикации

Electronic device and manufacturing thereof

Номер: US20120319109A1
Принадлежит: INFINEON TECHNOLOGIES AG

An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.

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10-01-2013 дата публикации

Semiconductor device and method for manufacturing same

Номер: US20130009300A1
Автор: Hiroi Oka, Yuichi Yato
Принадлежит: Renesas Electronics Corp

A dug portion ( 50 ) in which a die-bonding material is filled is provided to a lower surface of a stamping nozzle ( 42 ) used in a step of applying the die-bonding material onto a chip mounting portion of a wiring board. Planar dimensions of the dug portion ( 50 ) are smaller than external dimensions of a chip to be mounted on the chip mounting portion. In addition, a depth of the dug portion ( 50 ) is smaller than a thickness of the chip. When the thickness of the chip is 100 μm or smaller, a problem of crawling up of the die-bonding material to an upper surface of the chip is avoided by applying the die-bonding material onto the chip mounting portion using the stamping nozzle ( 42 ).

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07-03-2013 дата публикации

Electronic component and method for producing same

Номер: US20130058061A1
Принадлежит: Noritake Co Ltd, TDK Corp

This electronic component is provided with an inorganic substrate, a conductor film formed on a surface of the substrate, and bonding wires bonded to a part of said conductor film, and wire bonding sections are formed on at least a part of the electronic component. The part of the conductor film at least forming the aforementioned wire bonding sections contains an Ag-based metal formed of Ag or an alloy having Ag as the main constituent and a metal oxide which coats said Ag-based metal and which has, as a constituent element, any of the elements selected from the group consisting of Al, Zr, Ti, Y, Ca, Mg, and Zn. The coating quantity of the metal oxide is a quantity corresponding to 0.02 to 0.1 parts by mass relative to 100 parts by mass of the aforementioned Ag-based metal.

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14-03-2013 дата публикации

Epoxy resin composition for semiconductor encapsulant and semiconductor device using the same

Номер: US20130062748A1
Автор: Jun-Ichi Tabei
Принадлежит: Sumitomo Bakelite Co Ltd

According to the present invention, an epoxy resin composition for semiconductor encapsulant including (A) an epoxy resin, (B) a curing agent, (C) an inorganic filler, and (D) a compound in which a copolymer of a 1-alkene having 5 to 80 carbon atoms and maleic anhydride is esterified with an alcohol having 5 to 25 carbon atoms in the presence of a compound represented by General Formula (1), wherein R 1 in General Formula (1) is selected from the group consisting of an alkyl group having 1 to 5 carbon atoms, a halogenated alkyl group having 1 to 5 carbon atoms, and an aromatic group having 6 to 10 carbon atoms is provided.

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14-03-2013 дата публикации

Low loop wire bonding

Номер: US20130062765A1
Принадлежит: Carsem M Sdn Bhd

A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads positioned thereon. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires includes a first portion extending upward from one of the second plurality of bond pads substantially along a z-axis and curving outward substantially along x and y axes in a direction towards the first semiconductor die. The bonding wire also includes a second portion coupled to the first portion and extending from the first portion downward to one of the first plurality of bond pads on the upper surface of the first semiconductor die.

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30-05-2013 дата публикации

Structure for High-Speed Signal Integrity in Semiconductor Package with Single-Metal-Layer Substrate

Номер: US20130134579A1
Принадлежит: Texas Instruments Inc

A semiconductor chip ( 101 ) with bond pads ( 110 ) on a substrate ( 103 ) with rows and columns of regularly pitched metal contact pads ( 131 ). A zone comprises a first pair ( 131 a, 131 b ) and a parallel second pair ( 131 c, 131 d ) of contact pads, and a single contact pad ( 131 e ) for ground potential; staggered pairs of stitch pads ( 133 ) connected to respective pairs of adjacent contact pads by parallel and equal-length traces ( 132 a, 132 b , etc.). Parallel and equal-length bonding wires ( 120 a, 120 b , etc.) connect bond pad pairs to stitch pad pairs, forming differential pairs of parallel and equal-length conductor lines. Two differential pairs in parallel and symmetrical position form a transmitter/receiver cell for conducting high-frequency signals.

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06-06-2013 дата публикации

Doped 4n copper wires for bonding in microelectronics devices

Номер: US20130142567A1

A doped 4N copper wire for bonding in microelectronics contains one or more corrosion resistance dopant materials selected from Ag, Ni, Pd, Au, Pt, and Cr. A total concentration of the corrosion resistance dopant materials is between about 10 wt. ppm and about 80 wt. ppm.

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13-06-2013 дата публикации

Semiconductor device

Номер: US20130147064A1
Автор: Tomoaki Uno, Yukihiro Sato
Принадлежит: Renesas Electronics Corp

The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7 D 2 , a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

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04-07-2013 дата публикации

Alloy wire and methods for manufacturing the same

Номер: US20130171470A1
Принадлежит: WIRE Tech CO Ltd

An alloy wire made of a material selected from one of a group consisting of a silver-gold alloy, a silver-palladium alloy and a silver-gold-palladium alloy is provided. The alloy wire is with a polycrystalline structure of a face-centered cubic lattice and includes a plurality of grains. A central part of the alloy wire includes slender grains or equi-axial grains, and the other parts of the alloy wire consist of equi-axial grains. A quantity of the grains having annealing twins was 20 percent or more of the total quantity of the grains of the alloy wire.

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01-08-2013 дата публикации

Processes and structures for IC fabrication

Номер: US20130193561A1
Автор: Jayna Sheats
Принадлежит: Terepac Corp

The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires.

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29-08-2013 дата публикации

Heavy-wire bond arrangement and method for producing same

Номер: US20130220673A1
Автор: Andreas Middendorf
Принадлежит: TECHNISCHE UNIVERSITAET BERLIN

The invention relates to a heavy-wire bond arrangement, having a substrate ( 2 ), a heavy wire ( 1 ) and a high-voltage heavy-wire bond connection, in which an end bond section ( 4 ) of the heavy wire ( 1 ), which extends towards the end ( 7 ) of the heavy wire ( 1 ), is bonded to the substrate ( 2 ), such that in the area of the bond section ( 4 ) a bond contact ( 5 ) between the heavy wire ( 1 ) and the substrate ( 2 ) is formed, the heavy wire ( 1 ) having a tapering section ( 6 ) which adjoins the end of the wire ( 7 ) and in which the wire cross-section tapers towards the end of the wire ( 7 ). The application additionally relates to a method for producing a heavy-wire bond arrangement.

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03-10-2013 дата публикации

Lead frame, semiconductor device, and method for manufacturing lead frame

Номер: US20130256854A1
Принадлежит: Shinko Electric Industries Co Ltd

A lead frame includes a plurality of leads defined by an opening extending in a thickness direction. An insulating resin layer fills the opening to entirely cover side surfaces of each lead and to support the leads. A first surface of each lead is exposed from a first surface of the insulating resin layer.

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10-10-2013 дата публикации

Lead frame with grooved lead finger

Номер: US20130264693A1
Принадлежит: FREESCALE SEMICONDUCTOR INC

A lead finger of a lead frame has a number of channels or grooves in a portion of its top surface that provide a locking mechanism for securing a bond wire to the lead finger. The bond wire may be attached to the lead finger by stitch bonding.

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31-10-2013 дата публикации

Circuit device

Номер: US20130286616A1
Принадлежит: ON SEMICONDUCTOR TRADING LTD

A circuit device having superior voltage resistance is provided. A structure is achieved that omits the resin layer that is normally provided to the top surface of a circuit board. Specifically, a ceramic substrate ( 22 ) is disposed on the top surface of a circuit board ( 12 ) comprising a metal, and a transistor ( 34 ) such as an IGBT is mounted to the top surface of the ceramic substrate ( 22 ). As a result, the transistor ( 34 ) and the circuit board ( 12 ) are insulated from each other by the ceramic substrate ( 22 ). The ceramic substrate ( 22 ), which comprises an inorganic material, has an extremely high voltage resistance compared to the conventionally used insulating layer comprising resin, and so even if a high voltage on the order of 1000V is applied to the transistor ( 34 ), short circuiting between the transistor ( 34 ) and the circuit board ( 12 ) is prevented.

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28-11-2013 дата публикации

Semiconductor power module and method of manufacturing the same

Номер: US20130313574A1
Автор: Toshio Hanada
Принадлежит: ROHM CO LTD

A semiconductor power module according to the present invention includes a base member, a semiconductor power device having a surface and a rear surface with the rear surface bonded to the base member, a metal block, having a surface and a rear surface with the rear surface bonded to the surface of the semiconductor power device, uprighted from the surface of the semiconductor power device in a direction separating from the base member and employed as a wiring member for the semiconductor power device, and an external terminal bonded to the surface of the metal block for supplying power to the semiconductor power device through the metal block.

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12-12-2013 дата публикации

Package-on-package assembly with wire bond vias

Номер: US20130328219A1
Принадлежит: Invensas LLC

A structure includes a substrate having a first region and a second region, the substrate also having a first surface and a second surface. Electrically conductive elements are exposed at the first surface within the second region. Wire bonds have bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. At least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane. A bent portion of the at least one wire bond extends away from the axis within the plane. A dielectric encapsulation layer covers portions of the wire bonds such that unencapsulated portions, including the ends, of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer.

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23-01-2014 дата публикации

Power device and power device module

Номер: US20140021620A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

According to example embodiments of inventive concepts, a power device includes a semiconductor structure having a first surface facing a second surface, an upper electrode, and a lower electrode. The upper electrode may include a first contact layer that is on the first surface of the semiconductor structure, and a first bonding pad layer that is on the first contact layer and is formed of a metal containing nickel (Ni). The lower electrode may include a second contact layer that is under the second surface of the semiconductor structure, and a second bonding pad layer that is under the second contact layer and is formed of a metal containing Ni.

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06-02-2014 дата публикации

Method for fabricating a through wire interconnect (twi) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer

Номер: US20140038406A1
Принадлежит: Micron Technology Inc

A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

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13-02-2014 дата публикации

Power MOSFET Having Selectively Silvered Pads for Clip and Bond Wire Attach

Номер: US20140042624A1
Автор: Nathan Zommer
Принадлежит: IXYS LLC

A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of the islands. A silvered backside of the die is directly bonded to the sintered silver structure of the DBA. The upper surface of the die includes a first aluminum pad (a source pad) and a second aluminum pad (a gate pad). A sintered silver structure is disposed on the first aluminum pad, but there is no sintered silver structure disposed on the second aluminum pad. A high current clip is attached via soft solder to the sintered silver structure on the first aluminum pad (the source pad). A bond wire is ultrasonically welded to the second aluminum pad (gate pad).

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03-04-2014 дата публикации

High density second level interconnection for bumpless build up layer (bbul) packaging technology

Номер: US20140091442A1
Принадлежит: Intel Corp

An apparatus including a die including a device side; and a build-up carrier including a body including a plurality of alternating layers of conductive material and dielectric material disposed on the device side of the die, an ultimate conductive layer patterned into a plurality of pads or lands; and a grid array including a plurality of conductive posts disposed on respective ones of the plurality of pads of the ultimate conductive layer of the body, at least one of the posts coupled to at least one of the contact points of the die through at least a portion of the conductive material of the body. A method including forming a body of a build-up carrier including a die, the body of the build-up carrier including an ultimate conductive layer and forming a grid array including a plurality of conductive posts on the ultimate conductive layer of the body.

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01-01-2015 дата публикации

Power semiconductor module

Номер: US20150001726A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A power semiconductor module includes a first power device on a substrate, a first electrode on an upper surface of the first power device, a first nickel plating layer on the first electrode, and a copper wire connected to the first nickel plating layer.

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04-01-2018 дата публикации

Repackaged integrated circuit assembly method

Номер: US20180005910A1
Автор: Spory Erick Merle
Принадлежит: Global Circuit Innovations Inc.

A method is provided. The method includes one or more of extracting a die from an original packaged integrated circuit, modifying the extracted die, reconditioning the modified extracted die, placing the reconditioned die into a cavity of a hermetic package base, bonding a plurality of bond wires between reconditioned die pads of the reconditioned die to leads of the hermetic package base or downbonds to create an assembled hermetic package base, and sealing a hermetic package lid to the assembled hermetic package base to create a new packaged integrated circuit. Modifying the extracted die includes removing the one or more ball bonds on the one or more die pads. Reconditioning the modified extracted die includes adding a sequence of metallic layers to bare die pads of the modified extracted die. The extracted die is a fully functional semiconductor die with one or more ball bonds on one or more die pads of the extracted die. 1. A method , comprising:extracting a die from an original packaged integrated circuit, wherein the extracted die is a fully functional semiconductor die with one or more ball bonds on one or more die pads of the extracted die;modifying the extracted die, comprising removing the one or more ball bonds on the one or more die pads; 'adding a sequence of metallic layers to bare die pads of the modified extracted die;', 'reconditioning the modified extracted die, comprisingplacing the reconditioned die into a cavity of a hermetic package base;bonding a plurality of bond wires between reconditioned die pads of the reconditioned die to leads of the hermetic package base or downbonds to create an assembled hermetic package base; andsealing a hermetic package lid to the assembled hermetic package base to create a new packaged integrated circuit.2. The method as recited in claim 1 , wherein bare die pads of the modified extracted die comprises all metallic and chemical residue claim 1 , all ball bonds claim 1 , and all bond wires removed from all die ...

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03-01-2019 дата публикации

3D SEMICONDUCTOR DEVICE AND SYSTEM

Номер: US20190006240A1
Принадлежит: MonolithIC 3D Inc.

A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming memory peripheral circuits; a plurality of second transistors underlying the first single crystal layer; a second metal layer overlaying the plurality of second transistors; a first memory cell underlying the memory peripheral circuits; a second memory cell underlying the first memory cell, and a non-volatile NAND memory, where the first memory cell includes at least one of the second transistors, where at least one of the second transistors includes a source, channel and drain, where the source, the channel and the drain have the same dopant type, here the non-volatile NAND memory includes the first memory cell, and where at least one of the second transistors includes a polysilicon channel. 1. A 3D semiconductor device , the device comprising:a first single crystal layer comprising a plurality of first transistors; 'wherein said interconnecting comprises forming memory peripheral circuits;', 'at least one first metal layer interconnecting said plurality of first transistors,'}a plurality of second transistors underlying said first single crystal layer;a second metal layer overlaying said plurality of second transistors;a first memory cell underlying said memory peripheral circuits;a second memory cell underlying said first memory cell;a staircase structure underlying said first single crystal layer; and wherein said first memory cell comprises at least one of said second transistors,', 'wherein said memory peripheral circuits control at least said first memory cell,', 'wherein at least one of said second transistors comprises a source, channel and drain,', 'wherein said source, said channel and said drain have the same dopant type,', 'wherein said non-volatile NAND memory comprises said first memory cell,', 'wherein at ...

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04-01-2018 дата публикации

METHOD OF MANUFACTURING A CIRCUIT DEVICE

Номер: US20180006578A1

In one form, a method of manufacturing a circuit device comprises providing a lead frame comprising a plurality of leads, each comprising an island portion, a bonding portion elevated from the island portion, a slope portion extending obliquely so as to connect the island portion and the bonding portion, and a lead portion extending from the bonding portion. First and second transistors and first and second diodes are mounted upper surfaces of island portions of respective first and second leads, and are connected to the respective leads through wirings that connect the transistors and diodes to the bonding portions of the respective leads. Lower surfaces of the island portions are attached to an upper surface of a circuit board, and the circuit board, the transistors, the diodes, and the lead frame are encapsulated by a resin, so that the lead portions are not covered by the resin. 1. A method of manufacturing a circuit device , comprising:providing a lead frame comprising a plurality of leads, each comprising an island portion, a bonding portion elevated from the island portion, a slope portion extending obliquely so as to connect the island portion and the bonding portion, and a lead portion extending from the bonding portion;mounting a first transistor and a first diode of a first phase on an upper surface of the island portion of a first lead;connecting the first transistor and the first diode of the first phase to a bonding portion of a second lead by a first wiring;mounting a second transistor and a second diode of the first phase on the upper surface of the island portion of a third lead;connecting the second transistor and the second diode of the first phase to a bonding portion of the second lead by a second wiring;attaching lower surfaces of the island portion of each of the plurality of leads to an upper surface of a circuit board; andencapsulating by a resin the circuit board, the first and second transistors, the first and second diodes and the lead ...

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11-01-2018 дата публикации

Electronic Components with Integral Lead Frame and Wires

Номер: US20180012827A1
Принадлежит:

An electronic component includes one or more circuits having electrical connections coupled therewith. The electrical connections include a lead frame as well as electrical wires coupling the circuit or circuits to respective portions of the lead frame. The electrical wires may be formed as one piece with the respective portion of the lead frame without joints therebetween, e.g., by 3D printing. 1. A method of producing a semiconductor package , the method comprising:forming an electrical wire for contacting with a chip contact pad of a semiconductor chip and a lead of a lead frame in a single process, wherein the electrical wire and the lead are formed as a single piece without a joint.2. The method of claim 1 , wherein the electrical wire has a variable cross-section.3. The method of claim 1 , wherein a cross-sectional width of the electrical wire at the chip contact pad is narrower than a cross-sectional width of the electrical wire at other locations along the length of the electrical wire.4. The method of claim 1 , further comprising attaching the electrical wire with the chip contact pad of the semiconductor chip.5. The method of claim 1 , further comprising forming a molding compound around the semiconductor chip claim 1 , wherein the lead extends out of the molding compound.6. The method of claim 1 , further comprising:positioning the semiconductor chip on a carrier;attaching the electrical wire with the chip contact pad of the semiconductor chip; andforming a molding compound around the semiconductor chip, wherein the lead extends out of the molding compound.7. The method of claim 6 , further comprising selecting the carrier out of one of a carrier pad for the semiconductor chip claim 6 , and a carrier tape provided with holes configured for pad wire bonding.8. The method of claim 1 , wherein the single process is a 3D printing process.9. The method of claim 8 , wherein the electrical wire comprises copper claim 8 , aluminum claim 8 , or steel.10. A method ...

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09-01-2020 дата публикации

Cu ALLOY CORE BONDING WIRE WITH Pd COATING FOR SEMICONDUCTOR DEVICE

Номер: US20200013747A1

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof, and the boding wire contains one or more elements of As, Te, Sn, Sb, Bi and Se in a total amount of 0.1 to 100 ppm by mass. The bonding longevity of a ball bonded part can increase in a high-temperature and high-humidity environment, improving the bonding reliability. When the Cu alloy core material further contains one or more of Ni, Zn, Rh, In, Ir, Pt, Ga and Ge in an amount, for each, of 0.011 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 170° C. or more. When an alloy skin layer containing Au and Pd is further formed on a surface of the Pd coating layer, wedge bondability improves.

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19-01-2017 дата публикации

Semiconductor device

Номер: US20170018470A1
Принадлежит: Renesas Electronics Corp

A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.

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03-02-2022 дата публикации

PROCESS FOR ELECTRICALLY CONNECTING CONTACT SURFACES OF ELECTRONIC COMPONENTS

Номер: US20220037284A1
Принадлежит:

A process for electrically connecting contact surfaces of electronic components by capillary wedge bonding a round wire of 8 to 80 μm to the contact surface of a first electronic component, forming a wire loop, and stitch bonding the wire to the contact surface of a second electronic component, wherein the wire comprises a wire core having a silver or silver-based wire core with a double-layered coating comprised of a 1 to 50 nm thick inner layer of nickel or palladium and an adjacent 5 to 200 nm thick outer layer of gold. 1. A process for electrically connecting a contact surface of a first electronic component with a contact surface of a second electronic component comprising the subsequent steps:(1) capillary wedge bonding a wire having a circular cross-section with an average diameter in the range of 8 to 80 μm to the contact surface of the first electronic component,(2) raising the capillary wedge bonded wire to form a wire loop between the capillary wedge bond formed in step (1) and the contact surface of the second electronic component, and(3) stitch bonding the wire to the contact surface of the second electronic component,wherein the capillary wedge bonding of step (1) is carried out with a ceramic capillary having a lower face angle within the range of from zero to 4 degrees,wherein the wire comprises a wire core with a surface, the wire core having a double-layered coating superimposed on its surface,wherein the wire core consists of a material selected from the group consisting of pure silver, doped silver with a silver content of >99.5 wt.-% and silver alloys with a silver content of at least 89 wt.-%, andwherein the double-layered coating comprises a 1 to 50 nm thick inner layer of nickel or palladium and an adjacent 5 to 200 nm thick outer layer of gold.2. The process of claim 1 , (a′) an ultrasonic energy in a range of 50 to 100 mA,', '(b′) a force in a range of 10 to 30 g,', '(c′) a constant velocity in a range of 0.3 to 0.7 μm/s,', '(d′) a contact ...

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18-01-2018 дата публикации

Package-on-Package Structure

Номер: US20180019151A1
Принадлежит:

A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures. 1. A method comprising:forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier;attaching a semiconductor die on a first side of the plurality of interconnect structures;forming an underfill layer between the semiconductor die and the plurality of interconnect structures;mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps;forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer;detaching the carrier from the plurality of interconnect structures; andmounting a plurality of bumps on a second side of the plurality of interconnect structures.2. The method of claim 1 , wherein:the top package comprises a plurality of second bumps, and wherein a second bump of the plurality of second bumps and a corresponding redistribution line of the plurality of interconnect structures form a joint structure between the top package and the plurality of interconnect structures.3. The method of claim 1 , further ...

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22-01-2015 дата публикации

Led with multiple bonding methods on flexible transparent substrate

Номер: US20150021632A1
Принадлежит: Heilux LLC

Inventive aspects disclosed herein include a flexible device. The flexible device includes a flexible transparent substrate and an adhesive adhered to the flexible transparent substrate, covering a portion of the substrate. The device also includes two or more bare LED dies adhered to the adhesive, the two or more LED dies spaced as little as 0.22 inches (5.4 mm), or less, apart. The device additionally includes a pair of conductive traces on or in the substrate and positioned on opposing sides of the bare LED dies; a pair of conductive pads positioned on opposing surfaces of the bare LED die; and an interconnect that interconnects the pads and the traces.

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22-01-2015 дата публикации

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices

Номер: US20150021769A1
Принадлежит: Micron Technology Inc

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a microelectronic device includes attaching a microelectronic die to a support member by forming an attachment feature on at least one of a back side of the microelectronic die and the support member. The attachment feature includes a volume of solder material. The method also includes contacting the attachment feature with the other of the microelectronic die and the support member, and reflowing the solder material to join the back side of the die and the support member via the attachment feature. In several embodiments, the attachment feature is not electrically connected to internal active structures of the die.

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16-01-2020 дата публикации

Interconnect structure for stacked die in a microelectronic device

Номер: US20200020629A1
Принадлежит: Intel IP Corp

A microelectronic package includes at least two semiconductor die, one die stacked over at least partially another. At a least the upper die is oriented with its active surface facing in the direction of a redistribution structure, and one or more wires are coupled to extend from contacts on that active surface into conductive structures in the redistribution structure.

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21-01-2021 дата публикации

INTERCONNECT WIRES INCLUDING RELATIVELY LOW RESISTIVITY CORES

Номер: US20210020502A1
Принадлежит:

A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1. 1. (canceled)2. An integrated circuit structure , comprising:a dielectric material;a trench in the dielectric material, the trench having a bottom and sidewalls;a core material within the trench, the core material comprising copper, and the core material having a bottom surface, sidewall surfaces and a top surface;a jacket on the bottom surface, along the sidewall surfaces and on the top surface of the core material, the jacket comprising cobalt; anda barrier layer between the bottom of the trench and the jacket, the barrier layer comprising tantalum and nitrogen.3. The integrated circuit structure of claim 2 , wherein the barrier layer is further between the jacket and the sidewalls of the trench.4. The integrated circuit structure of claim 2 , wherein the core material further comprises a second metal claim 2 , the second metal different than copper.5. The integrated circuit structure of claim 4 , wherein the core material comprises an alloy of copper and the second metal.6. The integrated circuit structure of claim 2 , wherein the core material has a height and a width claim 2 , the height greater than the width.7. The integrated circuit structure of claim 2 , wherein a portion of the jacket on the bottom surface of the core material has a first thickness claim 2 , and a portion of the jacket on the top surface of the core material has a second thickness claim 2 , the first thickness greater than the second thickness.8. The integrated circuit structure of claim 2 , wherein the core material is in a volume surrounded by the jacket claim 2 , the core material completely filling the volume surrounded by the jacket.9. An ...

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21-01-2021 дата публикации

Method for manufacturing bonding wire and manufacturing apparatus thereof

Номер: US20210020598A1
Автор: Mun-Sub SONG
Принадлежит: Individual

A method for manufacturing a bonding wire includes: putting a surface layer metal of a bonding wire in a crucible having a die cooler provided at the lower part thereof and melting the same; putting a main component metal core of the bonding wire in a core guide located at the upper part of the die cooler of the crucible and heating the core guide to the melting point or below of the metal core; transferring the metal core toward the die cooler so as to allow the molten surface layer metal to be injected to the surface of the metal core; and manufacturing a 50 □m to 350 □m bonding wire from the cast wire precursor by using a drawing die.

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24-04-2014 дата публикации

Embedded chip packages and methods for manufacturing an embedded chip package

Номер: US20140110858A1
Принадлежит: INFINEON TECHNOLOGIES AG

A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.

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25-01-2018 дата публикации

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

Номер: US20180026007A1
Принадлежит: INVENSAS CORPORATION

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer. 1. A structure comprising:a substrate having a first region and a second region, the substrate also having a first surface and a second surface remote from the first surface, wherein the first surface extends in first and second lateral directions to define a first plane;electrically conductive elements exposed at the first surface of the substrate within the second region;wire bonds having bases bonded to respective ones of the conductive elements and free ends remote from the substrate and remote from the bases, at least one of the wire bonds having a shape such that the at least one wire bond defines an axis between the free end and the base thereof coincident with a side surface of the at least one wire bond and such that the at least one wire bond defines a second plane, a bent portion of the at least one wire bond extending away from the axis within the second plane, wherein the entire at least one wire bond is positioned on one side of the axis and a substantially straight portion of the at least one wire bond extends between the free end ...

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29-01-2015 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20150028465A1
Автор: Shingo Itoh
Принадлежит: Sumitomo Bakelite Co Ltd

A semiconductor device includes a semiconductor element that is mounted on a substrate, an electrode pad that contains aluminum as a main component and is provided in the semiconductor element, a copper wire that contains copper as a main component and connects a connection terminal provided on the substrate and the electrode pad, and an encapsulant resin that encapsulates the semiconductor element and the copper wire. When the semiconductor device is heated at 200° C. for 16 hours in the atmosphere, a barrier layer containing any metal selected from palladium and platinum is farmed at a junction between the copper wire and the electrode pad.

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24-01-2019 дата публикации

A 3d semiconductor device and system

Номер: US20190027409A1
Принадлежит: Monolithic 3D Inc

A 3D semiconductor device, the device including: a first crystalline silicon layer including a plurality of first transistors; a first metal layer interconnecting the first transistors, a portion of the first transistors forming a plurality of first logic gates; a first array of memory cells including second transistors; a second metal layer overlying the first and second transistors; a second crystalline silicon layer overlaying the second metal layer and the second crystalline silicon layer including a plurality of third transistors; a third metal layer interconnecting the third transistors, a portion of the third transistors forming a plurality of second logic gates; a second array of memory cells including fourth transistors and overlaying the second crystalline silicon layer; a fourth metal layer overlying the third and fourth transistors, where at least one of the fourth transistors is overlaying at least another one of the fourth transistors such that they are self-aligned, having been processed following the same lithography step, where the second array of memory cells include NAND flash type memory cells.

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24-01-2019 дата публикации

Wire bond wires for interference shielding

Номер: US20190027444A1
Принадлежит: Invensas LLC

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

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24-01-2019 дата публикации

Semiconductor Package and Method of Forming the Same

Номер: US20190027456A1
Автор: An-Jhih Su, Hsien-Wei Chen

A method of forming a semiconductor package includes receiving a carrier, coating the carrier with a bonding layer, forming a first insulator layer over the bonding layer, forming a backside redistribution layer over the first insulator layer, forming a second insulator layer over the backside redistribution layer, patterning the second insulator layer to form a recess that extends through the second insulator layer and to the backside redistribution layer, filling the recess with a solder, and coupling a surface-mount device (SMD) to the solder.

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24-01-2019 дата публикации

Light emitting apparatus

Номер: US20190027667A1
Принадлежит: Nichia Corp

A light emitting apparatus includes a positive lead terminal and a negative lead terminal, each of which includes a first main surface, a second main surface, and an end surface including a first recessed surface area extending from a first point of the first main surface in cross section, and a second recessed surface area extending from a second point of the second main surface in cross section. A distance between a first part of the end surface of the positive lead terminal and a second part of the end surface of the negative lead terminal than a first distance between the first points of the positive lead terminal and the negative lead terminal and a second distance between the second points of the positive lead terminal and the negative lead terminal. The first part and the second part are separated from the first point and the second point.

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10-02-2022 дата публикации

Pre-Plating of Solder Layer on Solderable Elements for Diffusion Soldering

Номер: US20220046792A1
Принадлежит: INFINEON TECHNOLOGIES AG

A pre-soldered circuit carrier includes a carrier having a metal die attach surface, a plated solder region on the metal die attach surface, wherein a maximum thickness of the plated solder region is at most 50 μm, the plated solder region has a lower melting point than the first bond pad, and the plated solder region forms one or more intermetallic phases with the die attach surface at a soldering temperature that is above the melting point of the plated solder region.

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01-02-2018 дата публикации

Ultra-thin embedded semiconductor device package and method of manufacturing thereof

Номер: US20180033762A1
Принадлежит: General Electric Co

A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

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01-02-2018 дата публикации

OPTOELECTRONIC SEMICONDUCTOR COMPONENT

Номер: US20180033931A1
Принадлежит:

An optoelectronic semiconductor device includes a carrier having a carrier top side, at least one optoelectronic semiconductor chip arranged at the carrier top side and having a radiation main side remote from the carrier top side, at least one bonding wire, at least one covering body on the radiation main side, and at least one reflective potting compound surrounding the semiconductor chip in a lateral direction and extending from the carrier top side at least as far as the radiation main side, wherein the bonding wire is completely covered by the reflective potting compound or completely covered by the reflective potting compound and the covering body, the bonding wire is fixed to the semiconductor chip in an electrical connection region on the radiation main side, and the electrical connection region is free of the covering body and covered partly or completely by the reflective potting compound. 1. An optoelectronic semiconductor device comprisinga carrier having a carrier top side,at least one optoelectronic semiconductor chip arranged at the carrier top side and having a radiation main side remote from the carrier top side,at least one bonding wire via which electrical contact is made with the semiconductor chip,at least one covering body on the radiation main side that projects beyond the bonding wire in a direction away from the carrier top side and traverse or perpendicularly to the radiation main side, andat least one reflective potting compound surrounding the semiconductor chip in a lateral direction and extending from the carrier top side at least as far as the radiation main side, whereinthe bonding wire is completely covered by the reflective potting compound or completely covered by the reflective potting compound and the covering body,the bonding wire is fixed to the semiconductor chip in an electrical connection region on the radiation main side, andthe electrical connection region is free of the covering body and covered partly or completely by ...

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31-01-2019 дата публикации

Semiconductor package with supported stacked die

Номер: US20190035705A1
Автор: Guo Mao
Принадлежит: Intel Corp

Semiconductor packages with electromagnetic interference supported stacked die and a method of manufacture therefor is disclosed. The semiconductor packages may house a stack of dies in a system in a package (SiP) implementation, where one or more of the dies may be wire bonded to a semiconductor package substrate. The dies may be stacked in a partially overlapping, and staggered manner, such that portions of some dies may protrude out over an edge of a die that is below it. This dies stacking may define a cavity, and in some cases, wire bonds may be made to the protruding portions of the die. Underfill material may be provided in the cavity and cured to form an underfill support. Wire bonding of the bond pads overlying the cavity formed by the staggered stacking of the dies may be performed after the formation of the underfill support.

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31-01-2019 дата публикации

SEMICONDUCTOR PACKAGE

Номер: US20190035738A1
Принадлежит:

The present disclosure provides a manufacturing method of a semiconductor packaging, including forming a redistribution layer (RDL) on a carrier, defining an active portion and a dummy portion of the RDL, and placing a semiconductor die over the dummy portion of the RDL. The present disclosure also provides a manufacturing method of a package-on-package (PoP) semiconductor structure, including forming a first redistribution layer (RDL) on a polymer-based layer of a carrier, defining an active portion and a dummy portion of the first RDL, placing a semiconductor die over the dummy portion of the first RDL, a back side of the semiconductor die facing the first RDL, forming a second RDL over a front side of the semiconductor die, the front side having at least one contact pad, and attaching a semiconductor package at the back side of the semiconductor die. 1. A semiconductor structure , comprising:a first redistribution layer (RDL) having a plurality of pads;a semiconductor die over the first RDL, at least one contact pad being positioned on a front side of the semiconductor die;a through package via (TPV) electrically connecting the front side and the first RDL; anda semiconductor device over a back side of the semiconductor die, the back side being opposite to the front side.2. The semiconductor structure of claim 1 , wherein the plurality of pads of the first RDL further comprises a dummy portion electrically isolated from any component of the semiconductor structure.3. The semiconductor structure of claim 1 , wherein the plurality of pads of the first RDL further comprises an active portion electrically coupled to the through package via.4. The semiconductor structure of claim 1 , further comprising a conductive plug at the back side of the semiconductor die.5. The semiconductor structure of claim 4 , further comprising a first carrier surrounding the conductive plug.6. The semiconductor structure of claim 4 , further comprising a second carrier between the ...

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04-02-2021 дата публикации

Package-on-package Assembly With Wire Bond Vias

Номер: US20210035948A1
Принадлежит: Invensas LLC

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

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08-02-2018 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20180040521A1
Принадлежит:

A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad. 119-. (canceled)20. A semiconductor device , comprising:a semiconductor chip having a first main surface, a second main surface opposite the first main surface, a side extending in a first direction, and a plurality of bonding pads formed on the first main surface and extending along the side,each of the bonding pads having a first side and a second side opposite the first side, extending in the first direction,wherein the first main surface of the semiconductor chip is covered by a protective film in which a plurality of openings are formed, andwherein a peripheral portion of an upper surface of each of the bonding pads is covered by the protective film and a portion other than the peripheral portion of the upper surface of each of the bonding pads is exposed from a corresponding one of the openings. The disclosure of Japanese Patent Application No. 2009-121857 filed on May 20, 2009 including the specification, drawings and abstract is incorporated herein by reference in its entirety.The present invention relates to a semiconductor device, in particular, to a technique effective to be applied to a semiconductor device with a semiconductor chip, having bonding pads, mounted thereon.Japanese Patent Laid-Open No. 1991-79055 (Patent Document 1), for example, discloses an electrode pad provided with a first portion to bond a wire or a film lead and a second portion that is integrally linked to the first portion, can be ...

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08-02-2018 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20180040552A1
Автор: SHIMANUKI YOSHIHIKO
Принадлежит:

A semiconductor device includes a die pad, a semiconductor chip with a bonding pad being formed, a lead one end of which is located in the vicinity of the semiconductor chip, a coupling wire that connects an electrode and the lead, and a sealing body that seals the semiconductor chip, the coupling wire, a part of the lead, and a part of the die pad. A lower surface of the die pad is exposed from a lower surface of the sealing body, the die pad and the coupling wire are comprised of copper, and a thickness of the semiconductor chip is larger than the sum of a thickness of the die pad and a thickness from an upper surface of the semiconductor chip to an upper surface of the sealing body. 117-. (canceled)18. A semiconductor device comprising: a first upper surface including a chip mounting region and a first bent part, and', 'a first lower surface located on an opposite side from the first upper surface;, 'a die pad that includes a second upper surface,', 'a second lower surface located on an opposite side from the second upper surface, and', 'an electrode formed over the second upper surface;, 'a semiconductor chip that is mounted in the chip mounting region and includesa sealing body that includes a third upper surface and a third lower surface located on an opposite side from the third upper surface, and that seals the semiconductor chip and the first upper surface of the die pad;a lead having a first portion that is located in the sealing body and a second portion that is located outside the sealing body; anda wire that is located in the sealing body and connects the electrode of the semiconductor chip and the first portion of the lead,wherein the first lower surface of the die pad is exposed from the third lower surface of the sealing body,wherein the first bent part is located in the sealing body,wherein the first bent part extends from the chip mounting region in a first direction,wherein the electrode of the semiconductor chip and the first portion of the lead ...

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08-02-2018 дата публикации

INTEGRATED ELECTRONIC DEVICE WITH TRANSCEIVING ANTENNA AND MAGNETIC INTERCONNECTION

Номер: US20180040591A1
Принадлежит: STMICROELECTRONICS S.R.L.

An embodiment of an integrated electronic device having a body, made at least partially of semiconductor material and having a top surface, a bottom surface, and a side surface, and a first antenna, which is integrated in the body and enables magnetic or electromagnetic coupling of the integrated electronic device with a further antenna. The integrated electronic device moreover has a coupling region made of magnetic material, which provides, in use, a communication channel between the first antenna and the further antenna. 1. A test system , comprising:a test chuck having a top surface configured to receive a wafer; a semiconductor body region;', 'an insulating layer disposed adjacent a top surface of the semiconductor body region;', 'a device winding within the insulating layer; and', 'a magnetic region disposed within at least the semiconductor body region and aligned with the device winding; and, 'wherein the wafer includes a plurality of integrated circuit devices, and wherein each integrated circuit device comprisesa layer of magnetic material extending between the top surface of the chuck and a bottom surface of the wafer.2. The test system of claim 1 , wherein said layer of magnetic material is mounted to the top surface of the test chuck and electromagnetically couples at least two of the plurality of integrated circuit devices.3. The test system of claim 1 , wherein said layer of magnetic material is mounted to the bottom surface of the wafer and electromagnetically couples at least two of the plurality of integrated circuit devices.4. The test system of claim 1 , wherein said layer of magnetic material comprises a magnetic material strip that is mounted to the bottom surface of the wafer and electromagnetically couples the magnetic regions of at least two of the plurality of integrated circuit devices.5. The test system of claim 4 , wherein said magnetic material strip comprises a strip of a host material containing magnetic particles.6. The test system ...

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15-02-2018 дата публикации

SYSTEMS AND METHODS FOR SINGLE-MOLECULE NUCLEIC-ACID ASSAY PLATFORMS

Номер: US20180045717A1

Integrated circuits for a single-molecule nucleic-acid assay platform, and methods for making such circuits are disclosed. In one example, a method includes transferring one or more carbon nanotubes to a complementary metal-oxide semiconductor (CMOS) substrate, and forming a pair of post-processed electrodes on the substrate proximate opposing ends of the one or more carbon nanotubes. 1. A method of making an integrated circuit for a single-molecule nucleic-acid assay platform , comprising:transferring one or more carbon nanotubes to a complementary metal-oxide semiconductor (CMOS) substrate; andforming a pair of post-processed electrodes on the substrate proximate opposing ends of the one or more carbon nanotubes.2. The method of claim 1 , wherein transferring the one or more carbon nanotubes comprises spinning the one or more carbon nanotubes from a suspension to the substrate.3. The method of claim 1 , wherein transferring the one or more carbon nanotubes comprises:forming the one or more carbon nanotubes on a transfer substrate;applying a layer of polymer to the transfer substrate to adhere the one or more carbon nanotubes to the transfer substrate; andplacing the layer of polymer with the one or more carbon nanotubes on the CMOS substrate.4. The method of claim 1 , wherein transferring the one or more carbon nanotubes comprises:placing the one or more carbon nanotubes in a suspension proximate a pair of preformed electrodes on the substrate; andapplying a voltage across the pair of preformed electrodes, whereby a force is applied to the one or more carbon nanotubes to urge the carbon nanotubes to be disposed across the pair of preformed electrodes.5. The method of claim 1 , wherein the substrate comprises surface-exposed electrodes claim 1 , and forming the pair of post-processed electrodes comprises depositing titanium on a pair of the surface-exposed electrodes.6. The method of claim 1 , wherein the substrate comprises surface-exposed electrodes claim 1 , and ...

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18-02-2016 дата публикации

Wire bonds for electronics

Номер: US20160049380A1
Принадлежит: Hamilton Sundstrand Corp

A circuit element includes a semiconductor chip and a wire for connecting between the semiconductor chip and an additional circuit element. A plurality of wire bond connections electrically connect the wire and the semiconductor chip. The plurality of wire bond connections can be disposed on a surface of the semiconductor chip and on a surface of the wire.

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08-05-2014 дата публикации

Semiconductor Package Having Multi-Phase Power Inverter with Internal Temperature Sensor

Номер: US20140124890A1
Принадлежит: International Rectifier Corp USA

According to an exemplary implementation, a semiconductor package includes a multi-phase power inverter having power switches and situated on a leadframe of the semiconductor package. The semiconductor package further includes a temperature sensor situated on the leadframe, where the temperature sensor is configured to generate a sensed temperature of the power switches. The semiconductor package also includes a driver circuit configured to drive the power switches of the multi-phase power inverter responsive to the sensed temperature. The temperature sensor can be on a common IC with the driver circuit. Furthermore, the semiconductor package can include an over-temperature protection circuit configured to provide over-temperature protection to the multi-phase power inverter using the sensed temperature.

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15-02-2018 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20180047695A1
Принадлежит: RENESAS ELECTRONICS CORPORATION

In a semiconductor device (SP) according to an embodiment, a solder resist film (first insulating layer, SR) which is in contact with the base material layer, and a resin body (second insulating layer, ) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (CR) of a wiring substrate and a semiconductor chip (). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved. 1. A semiconductor device comprising:a wiring substrate including a base material layer, a terminal formed on a first surface of the base material layer, and an insulating layer formed on the first surface such that the insulating film covers a first portion of the terminal, and such that the insulating film exposes a second portion of the terminal;a semiconductor chip including a front surface, a bonding pad formed on the front surface, and a projecting electrode formed on the bonding pad, and mounted over the wiring substrate such that the front surface faces the first surface of the wiring substrate via the projecting electrode;a solder material located between the second portion of the terminal and the projecting electrode; anda resin body located between the wiring substrate and the semiconductor chip, and sealing a connection part between the projecting electrode and the terminal,wherein the insulating film has an opening in which the second portion of the terminal is exposed,wherein, ...

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15-02-2018 дата публикации

Semiconductor device

Номер: US20180047698A1
Принадлежит: ROHM CO LTD

An inventive semiconductor device includes: a semiconductor chip including an integrated circuit; a plurality of electrode pads provided on the semiconductor chip and connected to the integrated circuit; a rewiring to which the electrode pads are electrically connected together, the rewiring being exposed on an outermost surface of the semiconductor chip and having an exposed surface area greater than the total area of the electrode pads; and a resin package which seals the semiconductor chip.

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08-05-2014 дата публикации

Semiconductor Package Having an Over-Temperature Protection Circuit Utilizing Multiple Temperature Threshold Values

Номер: US20140126256A1
Принадлежит: International Rectifier Corp USA

According to an exemplary implementation, a semiconductor package includes a multi-phase power inverter having power switches and situated on a leadframe of the semiconductor package. The semiconductor package further includes an over-temperature protection circuit configured to reduce current through the power switches based on multiple temperature threshold values of the power switches and a sensed temperature of the power switches. The over-temperature protection circuit can be configured to enter first and second modes based on the multiple temperature threshold values and the sensed temperature, where the second mode reduces current through the power switches to a greater extent than the first mode.

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26-02-2015 дата публикации

Methods to fabricate integrated circuits by assembling components

Номер: US20150053774A1
Автор: Jayna Sheats
Принадлежит: Terepac Corp, TERPAC

The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. The present process can fabricate multiple components separately before assembling them into a complete integrated circuit. In an aspect, the ready-for-assembling components are taken directly from processed wafers without any additional assembling processes, and/or having lateral dimensions less than 1 mm.

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08-05-2014 дата публикации

Semiconductor Packages Utilizing Leadframe Panels with Grooves in Connecting Bars

Номер: US20140127861A1
Принадлежит: International Rectifier Corp USA

According to an exemplary implementation, a method includes utilizing a leadframe panel comprising a plurality of leadframe modules, each of the plurality of leadframe modules having a leadframe pad. The leadframe panel has a plurality of bars each having a plurality of grooves, where the plurality of bars connect the plurality of leadframe modules. The method further includes attaching a device to the leadframe pad. The method also includes molding the leadframe panel while leaving a bottom of the leadframe pad exposed. Furthermore, the method includes sawing through the plurality of grooves of the plurality of bars to singulate the plurality of leadframe modules into separate packaged modules.

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26-02-2015 дата публикации

Semiconductor device

Номер: US20150054146A1
Автор: Shingo Itoh
Принадлежит: Sumitomo Bakelite Co Ltd

A semiconductor device of the present invention includes a semiconductor element having an electrode pad; a substrate over which the semiconductor element is mounted and which has an electrical bonding part; and a bonding wire electrically connecting the electrode pad to the electrical bonding part, wherein a main metal component of the electrode pad is the same as or different from a main metal component of the bonding wire, and when the main metal component of the electrode pad is different from the main metal component of the bonding wire, a rate of interdiffusion of the main metal component of the bonding wire and the main metal component of the electrode pad at a junction of the bonding wire and the electrode pad under a post-curing temperature of an encapsulating resin is lower than that of interdiffusion of gold (Au) and aluminum (Al) at a junction of aluminum (Al) and gold (Au) under the post-curing temperature.

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05-03-2015 дата публикации

Dense-pitch small-pad copper wire bonded double ic chip stack packaging piece and preparation method therefor

Номер: US20150061099A1
Автор: WEI Mu, Xiaowei Guo, Xizhou Li

A dense-pitch small-pad copper wire bonded double IC chip stack package comprises a plastic package body, in which a lead frame carrier and a frame lead inner pin are arranged; the upper surface of the lead frame carrier is fixedly connected with a first IC chip; a second IC chip is stacked on the first IC chip; the upper surface of the first IC chip and the upper surface of the second IC chip are respectively provided with a plurality of pads which are arranged as two lines of pad groups in parallel; the two pad groups are respectively a first pad group and a second pad group; a metal ball is implanted on each pad; each metal ball is connected with a first copper bonding ball; and a third copper bonding wire is formed by looping and arching on a corresponding metal ball between the second IC chip and the first IC chip. The preparation process of the present invention comprises thinning, scribing, loading the chip, performing pressure welding, plastic packaging and post-curing, trimming, electroplating, printing, forming and separating, and packaging. The package and the preparation method of the invention avoid the hidden danger of open circuit of a plastic packaging punching wire caused by the crater on the pad, the short circuit of adjacent welding spots, and the easy damage of a previous wire.

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02-03-2017 дата публикации

Palladium (pd)-coated copper wire for ball bonding

Номер: US20170057020A1
Принадлежит: Tanaka Denshi Kogyo KK

A palladium coated copper wire for ball bonding includes a core formed of pure copper or copper alloy having a purity of 98% by mass or more, and a palladium draw coated layer coated on the core. The copper wire has a diameter of 10 to 25 μm, and the palladium drawn layer contains sulfur, phosphorus, boron or carbon.

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21-02-2019 дата публикации

3D SEMICONDUCTOR DEVICE AND SYSTEM

Номер: US20190057903A1
Принадлежит: MonolithIC 3D Inc.

A 3D semiconductor device, the device including: a first layer including a first single crystal transistor; a second layer including second transistors; a third layer including third transistors; a fourth layer including fourth transistors, where the first layer is overlaid by the second layer, where the second layer is overlaid by the third layer, and where the third layer is overlaid by the fourth layer; where a plurality of the fourth transistors are aligned to the plurality of the first single crystal transistor with less than 40 nm alignment error, where the third transistors are junction-less transistors (JLT), where each of the fourth transistors include a transistor channel, a drain and a source, and where the transistor channel is significantly narrower than the drain or the source. 1. A 3D semiconductor device , the device comprising:a first level comprising a first single crystal transistor;a second level comprising second transistors;a third level comprising third transistors; wherein said first level is underneath said second level,', 'wherein said second level is underneath said third level, and', 'wherein said third level is underneath said fourth level;, 'a fourth level comprising fourth transistors,'} 'wherein said at least first metal layer and second metal layer comprise connections between a plurality of said first single crystal transistor; and', 'at least a first metal layer and a second metal layer,'} wherein said NAND type memory cells comprise a plurality of said third transistors,', 'wherein a plurality of said fourth transistors are aligned to said plurality of said first single crystal transistor with less than 140 nm alignment error,', 'wherein said second metal layer is above said first metal layer,', 'wherein said first metal layer comprises a first current carrying capacity,', 'wherein said second metal layer comprises a second current carrying capacity,', 'wherein said first current carrying capacity is significantly greater than ...

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03-03-2016 дата публикации

Integrating Multi-Output Power Converters Having Vertically Stacked Semiconductor Chips

Номер: US20160064313A1
Принадлежит: Texas Instruments Inc

A electronic multi-output device having a substrate including a pad and pins. A composite first chip has a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface. Patterned second and third terminals are on the opposite chip surface. The common first terminal is attached to the substrate pad. The second terminals are connected by discrete first and second metal clips to respective substrate pins. A composite second chip has a third and a fourth transistor integrated so that the second terminals of the transistors are merged into a common terminal on one chip surface. Patterned first and third terminals are on the opposite chip surface. The second chip is flipped to be vertically attached with its first terminals to the first and second clips, respectively. The third terminals are connected by discrete clips to respective substrate pins. The common second terminal is connected by a common clip to a substrate pin.

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03-03-2016 дата публикации

Integrating Multi-Output Power Converters Having Vertically Stacked Semiconductor Chips

Номер: US20160064352A1
Принадлежит: Texas Instruments Inc

A method for fabricating an electronic multi-output device. A substrate having a pad and pins is provided. A first chip is provided having a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface and the patterned second and third terminals are on the opposite chip surface. The common first terminal is attached to the substrate pad. A driver and control chip is attached to the substrate pad adjacent to the first chip. The second terminals of the first and second transistors are connected by discrete first and second gang clips to respective substrate pins. A second chip is provided having a third and a fourth transistor integrated so that the second terminals of the transistors are merged into a common terminal on one chip surface. Patterned first and third terminals are on the opposite chip surface. The second chip is flipped to attach the first terminals vertically to the first and second gang clips. The third terminals are concurrently attached by discrete gang clips to respective pins. A common clip is attached to the common second terminal and connecting the common clip to a pin.

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01-03-2018 дата публикации

Wire Bond Wires for Interference Shielding

Номер: US20180061774A1
Принадлежит: INVENSAS CORPORATION

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region. 1. An apparatus for a microelectronic package having interference protection , comprising:a substrate having an upper surface and a lower surface opposite the upper surface and having bond pads on the upper surface;a microelectronic device coupled to the upper surface of the substrate;wire bond wires having lower ends coupled to the bond pads, the wire bond wires extending away from the upper surface of the substrate and placed for one or more frequencies associated with the interference;the wire bond wires positioned on at least one side of the microelectronic device to provide a shielding region with respect to the interference;a conductive surface positioned above the wire bond wires for covering the shielding region; andthe wire bond wires having upper ends coupled to the conductive surface.2. The apparatus according to claim 1 , wherein the wire bond wires are place to shield the microelectronic device from the interference.3. The apparatus according to claim 2 , wherein the microelectronic device is an active device.4. The apparatus according to claim 2 ...

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01-03-2018 дата публикации

SEMICONDUCTOR COPPER METALLIZATION STRUCTURE AND RELATED METHODS

Номер: US20180061791A1
Автор: LIN Yusheng

Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip. 1. A semiconductor package comprising:a silicon die comprising a pad, the pad comprising one of aluminum copper (AlCu); aluminum copper silicon (AlCuSi); aluminum copper tungsten (AlCuW); aluminum silicon (AlSi); and any combination thereof;a passivation layer over at least a portion of the silicon die;a layer of one of a polyimide (PI), a polybenzoxazole (PBO), a polymer resin, and any combination thereof coupled to the passivation layer;a first copper layer coupled directly over and to the pad and at least a portion of the layer of one of a polyimide (PI), a polybenzoxazole (PBO), a polymer resin, and any combination thereof, the first copper layer being 1 microns to 20 microns thick; anda second copper layer coupled over the first copper layer, the second copper layer being 5 microns to 40 microns thick;wherein a width of the first copper layer above the pad is wider than a width of the second copper layer above the pad; andwherein the first and second copper layers are configured to one of bond with a heavy copper wire and solder with a copper clip.2. A semiconductor package of claim 1 , wherein the heavy copper wire is more than 5 mil in diameter.3. The ...

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01-03-2018 дата публикации

BONDING DEVICE

Номер: US20180061803A1
Автор: Sugito Akio
Принадлежит:

[Problem] 111-. (canceled)12. A bonding device that includes a plurality of piezoelectric elements to vibrate a capillary ,wherein the capillary is vibrated while inclination of the capillary caused by a leading end of the capillary being pulled with a load at a contact face of the capillary is corrected by performing functional operation of amplitude, phase, frequency, or waveform on a drive voltage waveform to each of the piezoelectric elements.13. (canceled) The present invention relates to a bonding device, and in particular, relates to a bonding device capable of adequately controlling a leading end of a capillary as a bonding tool for bonding a wire.Conventionally, there has been known a wire bonding device that bonds an electrode of a semiconductor chip and a lead for wiring formed on a substrate with a wire.A wire bonding device presses a ball formed at a leading end of a wire to an electrode of a semiconductor chip with ultrasonic vibration to bond the ball thereto and presses the wire to a lead with ultrasonic vibration, so that the electrode on the semiconductor chip and the lead on the substrate are bonded.In a wire bonding device, a bonding head is fixed as being placed on an XY-table movable in two-dimensional directions. A bonding arm that constitutes the bonding head is configured to be rotatable about a support shaft. The bonding arm is provided at a leading end at one side with an ultrasonic horn to which a capillary serving as a bonding tool is attached and is provided at the other side with an ultrasonic transducer serving as an ultrasonic applying unit that applies ultrasonic vibration to the capillary via the ultrasonic horn.Here, the ultrasonic horn of the conventional bonding arm is required to have a length on the basis of λ(acoustic wavelength)/2. Further, when the ultrasonic horn is attached to the bonding head serving as the bonding arm, the ultrasonic horn is fixed to a position at a node of λ/4. Thus, there have been restrictions for ...

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02-03-2017 дата публикации

METHOD FOR MANUFACTURING WIRE BONDING STRUCTURE, WIRE BONDING STRUCTURE, AND ELECTRONIC DEVICE

Номер: US20170062381A1
Автор: IKOMA Kazuya
Принадлежит:

A manufacturing method for a wire bonding structure of the present invention includes a step of preparing a wire made of Cu and a step of joining the wire to a first joining target formed on an electronic device. Before the joining step, the wire has an outer circumferential surface and a withdrawn surface. The withdrawn surface is withdrawn toward a central axis of the wire from the outer circumferential surface. In the joining step, ultrasonic vibration is applied to the wire in a state in which the withdrawn surface is pressed against the first joining target. 1. A manufacturing method for a wire bonding structure , the method comprising:a step of preparing a wire made of Cu: anda step of joining the wire to a first joining target formed on an electronic device;wherein before the joining step, the wire has an outer circumferential surface and a withdrawn surface,the withdrawn surface is withdrawn toward a central axis of the wire from the outer circumferential surface, andin the joining step, ultrasonic vibration is applied to the wire in a state in which the withdrawn surface is pressed against the first joining target.2. The manufacturing method according to claim 1 , wherein the withdrawn surface is flat at a point in time of starting the joining step.3. The manufacturing method according to claims 1 , further comprising a step of forming the withdrawn surface by pressing the wire against a pressing target before the joining step.4. The manufacturing method according to claim 3 , wherein the pressing target is made of a ceramic material or a metal.5. The manufacturing method according to claim 3 , further comprising a step of preparing a wedge for pressing the wire claim 3 ,wherein in the step of forming the withdrawn surface, the wire is pressed against the pressing target by the wedge, andin the step of joining the wire to the first joining target, the wire is pressed against the first joining target by the wedge.6. The manufacturing method according to ...

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04-03-2021 дата публикации

Semiconductor device and semiconductor device manufacturing method

Номер: US20210066146A1
Автор: Makoto Isozaki
Принадлежит: Fuji Electric Co Ltd

A semiconductor device, including a substrate having an insulating plate and a conductive plate formed on the insulating plate, a semiconductor chip formed on the conductive plate, a contact part arranged on the conductive plate with a bonding member therebetween, a rod-shaped external connection terminal having a lower end portion thereof fitted into the contact part, and a lid plate having a front surface and a back surface facing the substrate. An insertion hole pierces the lid plate, forming an entrance and exit respectively on the back and front surfaces of the lid plate. The external connection terminal is inserted in the insertion hole. The semiconductor device has at least one of a guide portion with an inclined surface, fixed to a portion of the external connection terminal located in the insertion hole, or an inclined inner wall of the insertion hole.

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17-03-2022 дата публикации

Straight wirebonding of silicon dies

Номер: US20220084979A1
Принадлежит: Western Digital Technologies Inc

A method including stacking a number of silicon dice such that one or more edges of the dice are in vertical alignment, where the one or more edges include a number of connection pads. The method also includes positioning a connecting wire on a substantially perpendicular axis to the one or more edges. The connecting wire includes a number of solder blocks formed thereon. The solder blocks are spaced at intervals associated with a distance between a first set of aligned connection pads on the dice. The connecting wire is positioned such that the solder blocks are in contact with the first set of aligned connection pads. The method also includes applying heat to cause the solder blocks to reflow and physically and electrically couple the connecting wire to the connection pads.

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28-02-2019 дата публикации

3D SEMICONDUCTOR DEVICE AND SYSTEM

Номер: US20190067109A1
Принадлежит: MonolithIC 3D Inc.

A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors; contact plugs; a first metal layer, where a portion of the contact plugs provide connections from the plurality of first single crystal transistors to the first metal layer, and where connections include forming memory control circuits; a second level including a plurality of second transistors; a third level including a plurality of third transistors, where the second level overlays the first level, the third level overlays the second level; a second metal layer overlaying the third level; and a third metal layer overlaying the second metal layer, where second transistors are aligned to first transistors with less than 40 nm alignment error, where the second level includes first memory cells, where the third level includes second memory cells, and where the memory control circuits are designed to adjust a memory write voltage according to the device specific process parameters. 1. A 3D semiconductor device , the device comprising:a first level comprising a plurality of first single crystal transistors; 'wherein said first single crystal transistors comprise forming memory control circuits;', 'a first metal layer,'}a second level comprising a plurality of second transistors; wherein said second level overlays said first level, and', 'wherein said third level overlays said second level;, 'a third level comprising a plurality of third transistors,'}a second metal layer overlaying said third level; and wherein said plurality of second transistors are aligned to said plurality of first single crystal transistors with less than 140 nm alignment error,', 'wherein said third metal comprises bit lines,', 'wherein said second level comprises a plurality of first memory cells,', 'wherein said third level comprises a plurality of second memory cells,', 'wherein one of said plurality of second transistors is at least partially self-aligned to at least one of ...

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28-02-2019 дата публикации

3D SEMICONDUCTOR DEVICE AND SYSTEM

Номер: US20190067110A1
Принадлежит: MonolithIC 3D Inc.

A 3D semiconductor device including: a first level with first single crystal transistors; contact plugs; a first metal layer, where a portion of the contact plugs provide connections from the first transistors to the first metal, where connections formed logic circuits; a second level with second transistors; a third level with third transistors, where the second level overlays the first level, and where the third level overlays the second level; a second metal layer overlaying the third level, second level includes first memory cells where each of the memory cells include at least one of the second transistors; and vertically oriented conductive plugs, where the second transistors are aligned to the first transistors with less than 100 nm alignment error, where the second transistors are junction-less transistors, where one end of each of the vertically oriented conductive plugs are connected to the second metal layer, where at least one of the vertically oriented conductive plugs is disposed directly on one of the contact plugs. 1. A 3D semiconductor device , the device comprising:a first level comprising a plurality of first single crystal transistors;contact plugs; wherein a portion of said contact plugs provide connections from said plurality of first single crystal transistors to said first metal layer, and', 'wherein connections comprise forming logic circuits;, 'a first metal layer,'}a second level comprising a plurality of second transistors; wherein said second level is above said first level, and', 'wherein said third level is above said second level;, 'a third level comprising a plurality of third transistors,'} wherein said second level comprises memory cells, and', 'wherein each of said memory cells comprises at least one of said plurality of second transistors; and, 'a second metal layer atop said third level;'} wherein said plurality of second transistors are aligned to said plurality of first single crystal transistors with less than 150 nm ...

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08-03-2018 дата публикации

Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units

Номер: US20180068937A1
Принадлежит: STATS ChipPAC Pte. Ltd.

A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die. 1. A semiconductor device , comprising:a substrate including a conductive via formed through the substrate;a modular interconnect unit including a vertical interconnect structure disposed over the substrate;a first semiconductor die disposed over the substrate adjacent to the modular interconnect unit; andan encapsulant deposited around the first semiconductor die and over modular interconnect unit with an opening in the encapsulant extending to the modular interconnect unit.2. The semiconductor device of claim 1 , further including a second semiconductor die disposed over the first semiconductor die with a bump of the second semiconductor die within the opening of the encapsulant to contact the vertical interconnect structure.3. The semiconductor device of claim 1 , further including a first interconnect structure disposed between the substrate and modular interconnect unit.4. The semiconductor device of claim 3 , further including a second interconnect structure disposed between the first interconnect structure and ...

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08-03-2018 дата публикации

SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR

Номер: US20180068972A1
Автор: Yasunaga Shoji
Принадлежит: ROHM CO., LTD.

A semiconductor device includes a semiconductor chip, a lead arranged on a side portion of the semiconductor chip, and a wire, whose one end and another end are bonded to the semiconductor chip and the lead respectively, having a ball portion and a stitch portion wedged in side elevational view on the semiconductor chip and the lead respectively. An angle of approach of the wire to the lead is not less than 50°, and the length of the stitch portion is not less than 33 μm. 1. A semiconductor device , comprising:a semiconductor chip;leads arranged around the semiconductor chip;wires bonded to the semiconductor chip and the leads;an island to which the semiconductor chip is bonded;a chip bonding material interposed between the semiconductor chip and the island to bond the semiconductor chip and the island to each other; anda package covering a part of the island and the leads, whereinin a plan view, the island has a quadrangular shape having four sides that are each skewed relative to respective outer sides of the package,the island includes hanging portions which in the plan view, extend from respective corner portions of the island toward the respective outer sides of the package,in the plan view, each respective lead of the leads has an opposing side opposed to and parallel to a nearest side of the four sides of the island which is nearest to the respective lead out of the four sides of the island, the opposing side located outside an outer perimeter of the semiconductor chip in the plan view, andin the plan view, a first hanging portion of the hanging portions is opposed to and parallel to a first side of the respective lead, a second hanging portion of the hanging portions is opposed to and parallel to a second side of the respective lead, the nearest side of the island is bridged between the first hanging portion and the second hanging portion, and the opposing side of the respective lead is bridged between the first side and the second side.2. The semiconductor ...

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27-02-2020 дата публикации

Power Semiconductor Device and Power Conversion Device

Номер: US20200068735A1
Принадлежит:

A semiconductor module includes a first power semiconductor element having a first surface and a second surface. The semiconductor module also includes a second power semiconductor element having a first surface and a second surface. The semiconductor module also includes first, second, third, and fourth conductor plates, and a connecting part. The connecting part is integrally formed with the second conductor plate, extends toward the third conductor plate, and is connected to the third conductor plate. 1. A semiconductor module comprising:a first power semiconductor element having a first surface and a second surface;a second power semiconductor element having a first surface and a second surface;a first conductor plate disposed on the first surface of the first power semiconductor element;a second conductor plate disposed on the second surface of the first power semiconductor element;a third conductor plate disposed on the first surface of the second power semiconductor element;a fourth conductor plate disposed on the second surface of the second power semiconductor element; anda connecting part which is integrally formed with the second conductor plate, extends toward the third conductor plate, and is connected to the third conductor plate.2. The power semiconductor device according to claim 1 , whereinthe connecting part has a bending portion which is bent toward the third conductor plate from the second conductor plate.3. The power semiconductor device according to claim 2 , whereina thickness of the connecting part is formed smaller than a thickness of the second conductor plate in portion to which the first power semiconductor element is connected.4. The power semiconductor device according to claim 1 , whereinthe first conductor plate, the second conductor plate, the third conductor plate, and the fourth conductor plate are fixed with a sealing resin,the second conductor plate is exposed from a surface of the sealing resin, andthe connecting part is not ...

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07-03-2019 дата публикации

3D SEMICONDUCTOR DEVICE AND SYSTEM

Номер: US20190074222A1
Принадлежит: MonolithIC 3D Inc.

A 3D semiconductor device including: a first level including first single crystal transistors and a first metal layer; a second level including a plurality of second transistors; where the second level includes memory cells including the plurality of second transistors; a third level including a plurality of third transistors, where the second level overlays the first level, and where the third level overlays the second level; a second metal layer overlaying the third level; and vertically oriented conductive plugs, the vertically oriented conductive plugs connect from the second transistors to the first metal layer, where the second transistors are aligned to the first transistors with less than 100 nm alignment error, where the second transistors are junction-less transistors, and where one end of at least one of the vertically oriented conductive plugs functions also as a contact to a portion of each of the plurality of second transistors. 1. A 3D semiconductor device , the device comprising: 'wherein said logic circuits comprise a plurality of first single crystal transistors and a first metal layer;', 'a first level comprising logic circuits,'} 'wherein said second level comprises memory cells comprising said plurality of second transistors;', 'a second level comprising a plurality of second transistors,'} wherein said second level is atop said first level, and', 'wherein said third level is atop said second level;, 'a third level comprising a plurality of third transistors,'}a second metal layer atop said third level; and wherein said vertically oriented conductive plugs connect from said second transistors to said first metal layer,', 'wherein said plurality of second transistors are aligned to said plurality of first single crystal transistors with less than 150 nm alignment error,', 'wherein said plurality of second transistors are junction-less transistors,', 'wherein one end of at least one of said vertically oriented conductive plugs functions also as a ...

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24-03-2022 дата публикации

Semiconductor device

Номер: US20220093544A1
Автор: Yasuki Aihara
Принадлежит: Mitsubishi Electric Corp

Provided here are: an electrically-conductive semiconductor substrate with which a semiconductor circuit is formed; an insulating film deposited on a major surface of the electrically-conductive semi-conductor substrate; and a bonding pad having fixing parts fixed onto the insulating film, side wall parts rising up from the fixing parts, and an electrode part connected to the side wall parts and disposed in parallel to the major surface; wherein the electrode part forms, together with the insulating film, a gap region therebetween, and portions of the electrode part where it is connected to the side wall parts are configured to have at least one of: a positional relationship in which they sandwich therebetween a central portion of the electrode part in its bonding region to be bonded to a bonding wire; and a positional relationship in which they surround the central portion.

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22-03-2018 дата публикации

Semiconductor package

Номер: US20180082954A1

The present disclosure provides a manufacturing method of a semiconductor packaging, including forming a redistribution layer (RDL) on a carrier, defining an active portion and a dummy portion of the RDL, and placing a semiconductor die over the dummy portion of the RDL. The present disclosure also provides a manufacturing method of a package-on-package (PoP) semiconductor structure, including forming a first redistribution layer (RDL) on a polymer-based layer of a carrier, defining an active portion and a dummy portion of the first RDL, placing a semiconductor die over the dummy portion of the first RDL, a back side of the semiconductor die facing the first RDL, forming a second RDL over a front side of the semiconductor die, the front side having at least one contact pad, and attaching a semiconductor package at the back side of the semiconductor die.

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14-03-2019 дата публикации

PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES

Номер: US20190081015A1
Принадлежит:

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a system comprises a semiconductor component including an interposer substrate, a microelectronic die over the interposer substrate, and a connection structure composed of a volume of solder material between the interposer substrate and the microelectronic die. The connection structure can include at least one of (a) a single, unitary structure covering approximately all of the back side of the microelectronic die, and (b) a structure electrically isolated from internal active features of the microelectronic die. In some embodiments, the connection structure can be positioned to provide generally consistent stress distribution within the system. 1. A system , comprising: an interposer substrate including a plurality of first terminals;', 'a microelectronic die having an active side, a back side opposite the active side and facing toward the interposer substrate, integrated circuitry, and a plurality of second terminals at the active side and electrically coupled to the integrated circuitry, and wherein the second terminals at the active side of the microelectronic die are electrically coupled to corresponding first terminals of the interposer substrate with a plurality of wire bonds; and', 'a connection structure composed of a volume of solder material between the interposer substrate and the microelectronic die, wherein the connection structure is attached to both the interposer substrate and the back side of the microelectronic die,', 'wherein the connection structure includes at least one of (a) a single, unitary structure covering approximately all of the back side of the microelectronic die, and (b) a structure electrically isolated from internal active features of the microelectronic die., 'at least one of a processor and a memory device, wherein at least one of the processor and the memory device includes a semiconductor component ...

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19-06-2014 дата публикации

Semiconductor die package and method for making the same

Номер: US20140167238A1
Принадлежит: Fairchild Semiconductor Corp

Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

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31-03-2022 дата публикации

Semiconductor device

Номер: US20220102316A1
Автор: Kenshi Terashima
Принадлежит: Fuji Electric Co Ltd

A semiconductor device includes a semiconductor unit, a printed circuit board and a case, including a bottom portion formed in a plate-like shape and a side wall portion surrounding an outer periphery of the bottom portion of the case. The bottom portion has a main circuit area having an opening, and a control circuit area adjacent to the main circuit area in a plan view. The semiconductor unit is attached in the main circuit area from a rear surface of the bottom portion such that an insulating plate of the semiconductor unit is exposed to inside the case through the opening. The printed circuit board is disposed in the control circuit area on the front surface of the bottom portion via a spacer, having a gap between the printed circuit board and the front surface of the bottom portion.

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12-03-2020 дата публикации

Impedance Controlled Electrical Interconnection Employing Meta-Materials

Номер: US20200083171A1
Автор: Wyland Christopher
Принадлежит:

A method of improving electrical interconnections between two electrical elements is made available by providing a meta-material overlay in conjunction with the electrical interconnection. The meta-material overlay is designed to make the electrical signal propagating via the electrical interconnection to act as though the permittivity and permeability of the dielectric medium within which the electrical interconnection is formed are different than the real component permittivity and permeability of the dielectric medium surrounding the electrical interconnection. In some instances the permittivity and permeability resulting from the meta-material cause the signal to propagate as if the permittivity and permeability have negative values. Accordingly the method provides for electrical interconnections possessing enhanced control and stability of impedance, reduced noise, and reduced loss. Alternative embodiments of the meta-material overlay provide, the enhancements for conventional discrete wire bonds whilst also facilitating single integrated designs compatible with tape implementation. 120.-. (canceled)21. A device comprising: the first set of layers includes a second conductor layer and a third conductor layer, wherein the second conductor layer is disposed between the first surface of the first conductor layer and the third conductor layer;', 'the second set of layers includes a fourth conductor layer and a fifth conductor layer, wherein the fourth conductor layer is disposed between the second surface of the first conductor layer and the fifth conductor layer;', 'the second conductor layer includes a first plurality of electrically independent conductors arranged to span the width of the plurality of layers and the third conductor layer extends continuously along the width of the plurality of layers; and', 'the fourth conductor layer includes a second plurality of electrically independent conductors arranged to span the width of the plurality of layers and the ...

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25-03-2021 дата публикации

FLOATING DIE PACKAGE

Номер: US20210091012A1
Принадлежит:

A floating die package including a cavity formed through sublimation of a sacrificial die encapsulant and sublimation or separation of die attach materials after molding assembly. A pinhole vent in the molding structure is provided as a sublimation path to allow gases to escape, whereby the die or die stack is released from the substrate and suspended in the cavity by the bond wires only. 1. A semiconductor package comprising:a lead frame including a die paddle and a first plurality of conductors and a second plurality of conductors;a first semiconductor die electrically connected to the first plurality of conductors through a first set of bond wires;a second semiconductor die electrically connected to the second plurality of conductors through a second set of bond wires, the second semiconductor die attached to the first semiconductor die;a molding structure covering portions of the lead frame, the first semiconductor die, the second semiconductor die, the first set of bond wires, and the second set of bond wires; anda cavity within the molding structure and covering portions of top surfaces of the first semiconductor die and attached to the second semiconductor die, wherein a portion of the cavity is in between the first semiconductor die and the die paddle, wherein one surface of each of the first plurality of conductors and two surfaces of each of the second plurality of conductors are exposed from the semiconductor package, and wherein the first semiconductor die is suspended by the first set of bond wires to float inside the cavity.2. The semiconductor package of claim 1 , wherein the second set of bond wires is below the first set of bond wires in a cross-sectional view of the semiconductor package.3. The semiconductor package of further comprising a film layer in contact with portions of the molding structure and covering a portion of the cavity.4. The semiconductor package of claim 3 , wherein the film layer includes a screen-printed film.5. The ...

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29-03-2018 дата публикации

SEMICONDUCTOR DEVICE HAVING LOW ON RESISTANCE

Номер: US20180090463A1
Принадлежит:

A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad. 1. A semiconductor device , comprising:a semiconductor chip including a field effect transistor, having a main surface over which a source electrode and a gate electrode of the field effect transistor are formed, and having a second main surface on which a drain electrode of the field effect transistor is formed, the second main surface being opposed to the first main surface;a metal-made support board having a top surface and a bottom surface opposite the top surface, the semiconductor chip being mounted over the top surface such that the drain is fixed to the top surface of the metal-made support board via a conductive adhesive material;a source lead electrically connected with the source electrode of the semiconductor chip via a plurality of source conductors;a gate lead electrically connected with the gate electrode of the semiconductor chip via a gate conductor;a drain lead formed contiguously with the metal-made support board; anda sealing body sealing the semiconductor chip, andwherein, in plan view, the metal-made support board has a first side and a second side opposite the first side,wherein, in plan view, the sealing body having a third side that is extended along the first side of the metal-made support board,wherein, in plan view, ...

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21-03-2019 дата публикации

Multichip modules and methods of fabrication

Номер: US20190088607A1
Принадлежит: Invensas LLC

In a multi-chip module (MCM), a “super” chip (110N) is attached to multiple “plain” chips (110F′ “super” and “plain” chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips (110F). The plain chips overlap the super chip. Further, the plain chips' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties.

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