Erase Stress and Delta Erase Loop Count Methods for Various Fail Modes in Non-Volatile Memory

Techniques are presented for using erase stress and variations in the loop count (number of cycles) for various fail modes in non-volatile memories, including erase disturb and shallow erase. For detection of shallow erase, cells are programmed and then erased, where the variation (delta) in the number of erase loop counts can be used to determine defective blocks. To determine blocks prone to erase disturb, an erase stress is applied to unselected blocks, after which they are programmed: after then erasing one block, the next block can then be read to determine whether it has suffered erase disturb. 1. A method of determining defects in a non-volatile flash memory circuit , comprising:programing memory cells of a first plurality of blocks of an array of the non-volatile flash memory circuit;subsequently performing an erase operation on the first plurality of blocks, wherein the erase operation includes an alternating series of erase pulses and erase verify operations;maintaining, for each the first plurality of blocks, a count of the number erase pulses required for the corresponding block to verify as erased in the erase operation;determining from the counts of a second plurality of blocks from the first plurality of blocks an average erase count; comparing the count for first block to the average erase count; and', 'in response to the count for the first block exceeding the average erase count by a first number of counts, marking the first block as defective., 'performing a first defect determination operation on a first block of the first plurality of blocks, including2. The method of claim 1 , wherein the first defect determination operation further includes:in response to the count for the first block not exceeding the average erase count by a first number of counts, determining whether the count for the first block exceeds the average erase count by a second number of counts, the second number of counts being less than the first number of counts;in response ...

CLAMPED SEMICONDUCTOR WAFERS AND SEMICONDUCTOR DEVICES

Clamped semiconductor wafers and clamped semiconductor devices include reservoirs filled with a flowable metal which hardens to allow the wafers/devices to be shipped or stored. The hardened metal may also be reflowed to a liquid to allow clamping of the semiconductor wafers together and to allow clamping of the semiconductor packages together. The flowable metal may be filled into the reservoirs as a liquid or paste. Thereafter, the flowable metal may be cooled to harden the flowable metal into a clamping member.

SEMICONDUCTOR DEVICE INCLUDING FRACTURED SEMICONDUCTOR DIES

A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces. 1. A semiconductor die , comprising:a substrate;die bond pads in the substrate, the die bond pads configured to transfer electrical signals to and from the semiconductor die; anda memory cell array in the substrate, the memory cell array electrically coupled to the die bond pads, and the memory cell array divided into a plurality of blocks;wherein the semiconductor die is fractured to a size smaller than an original size of the semiconductor die; andwherein the semiconductor die is fractured at a block of the plurality of blocks at an edge of the semiconductor die.2. (canceled)3. The semiconductor die of claim 1 , wherein the memory cell array is fractured upon fracturing the semiconductor die.4. The semiconductor die of claim 3 , wherein the memory cell array comprises a plurality of blocks sequentially arranged along an axis of the semiconductor die claim 3 , the memory cell array fractured in a plane perpendicular to the axis along which the blocks are arranged.5. The semiconductor die of claim 1 , wherein the memory cell array comprises electrical traces electrically coupled to the die bond pads claim 1 , wherein the electrical traces are fractured.6. The semiconductor die of claim 5 , wherein the fractured electrical traces comprise bit lines in a memory cell array.7. The semiconductor die of claim 5 , wherein a pair ...

Three dimensional NAND device with channel contacting conductive source line and method of making thereof

A NAND memory cell region of a NAND device includes a conductive source line that extends substantially parallel to a major surface of a substrate, a first semiconductor channel that extends substantially perpendicular to a major surface of the substrate, and a second semiconductor channel that extends substantially perpendicular to the major surface of the substrate. At least one of a bottom portion and a side portion of the first semiconductor channel contacts the conductive source line and at least one of a bottom portion and a side portion of the second semiconductor channel contacts the conductive source line.

Three dimensional NAND device containing fluorine doped layer and method of making thereof

A method of making a monolithic three dimensional NAND string comprising forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming an at least one front side opening in the stack and forming at least a portion of a memory film in the at least one front side opening. The method also includes forming a semiconductor channel in the at least one front side opening and doping at least one of the memory film and the semiconductor channel with fluorine in-situ during deposition or by annealing in a fluorine containing atmosphere.

Three-dimensional non-volatile memory device having a silicide source line and method of making thereof

A memory device and a method of making a memory device that includes a stack of alternating layers of a first material and a second material different from the first material over a substrate, where the layers of the second material form a plurality of conductive control gate electrodes. A plurality of NAND memory strings extend through the stack, where each NAND memory string includes a semiconductor channel which contains at least a first portion which extends substantially perpendicular to a major surface of the substrate and at least one memory film located between the semiconductor channel and the plurality of conductive control gate electrodes. A source line including a metal silicide material extends through the stack.

Alternating Refractive Index In Charge-Trapping Film In Three-Dimensional Memory

Techniques are provided for fabricating a three-dimensional, charge-trapping memory device with improved long term data retention. A corresponding three-dimensional, charge-trapping memory device is also provided which includes a stack of alternating word line layers and dielectric layers. A charge-trapping layer is deposited in a memory hole. The refractive index of portions of the charge-trapping layer which are adjacent to the word line layers is increased relative to the refractive index of portions of the charge-trapping layer which are adjacent to the dielectric layers. This can be achieved by doping the portions of the charge-trapping layer which are adjacent to the word line layers. In one approach, the charge-trapping layer is SiON and is doped with Si or N. In another approach, the charge-trapping layer is HfO and is doped with Hf. In another approach, the charge-trapping layer is HfSiON and is doped with Hf, Si or N. 1. A memory device , comprising:a stack comprising alternating word line layers and dielectric layers;a memory hole extending vertically in the stack;a channel material extending in the memory hole;an oxide extending in the memory hole around the channel material; anda charge-trapping layer extending in the memory hole around the oxide, the charge-trapping layer comprising portions which are adjacent to the word line layers and portions which are adjacent to the dielectric layers, the portions of the charge-trapping layer which are adjacent to the word line layers have a refractive index which is higher than a refractive index of the portions of the charge-trapping layer which are adjacent to the dielectric layers.2. The memory device of claim 1 , wherein:the portions of the charge-trapping layer which are adjacent to the word line layers comprise silicon-rich silicon oxynitride.3. The memory device of claim 1 , wherein:the portions of the charge-trapping layer which are adjacent to the word line layers comprise nitrogen-rich silicon ...

Three-dimensional memory devices having a shaped epitaxial channel portion

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A dielectric collar structure can be formed prior to formation of an epitaxial channel portion, and can be employed to protect the epitaxial channel portion during replacement of the sacrificial material layers with electrically conductive layers. Exposure of the epitaxial channel portion to an etchant during removal of the sacrificial material layers is avoided through use of the dielectric collar structure. Additionally or alternatively, facets on the top surface of the epitaxial channel portion can be reduced or eliminated by forming the epitaxial channel portion to a height that exceeds a target height, and by recessing a top portion of the epitaxial channel portion. The recess etch can remove protruding portions of the epitaxial channel portion at a greater removal rate than a non-protruding portion.

METHOD OF MAKING A THREE-DIMENSIONAL MEMORY DEVICE HAVING A HETEROSTRUCTURE QUANTUM WELL CHANNEL

A cylindrical confinement electron gas confined within a two-dimensional cylindrical region can be formed in a vertical semiconductor channel extending through a plurality of electrically conductive layers comprising control gate electrodes. A memory film in a memory opening is interposed between the vertical semiconductor channel and the electrically conductive layers. The vertical semiconductor channel includes a wider band gap semiconductor material and a narrow band gap semiconductor material. The cylindrical confinement electron gas is formed at an interface between the wider band gap semiconductor material and the narrow band gap semiconductor material. As a two-dimensional electron gas, the cylindrical confinement electron gas can provide high charge carrier mobility for the vertical semiconductor channel, which can be advantageously employed to provide higher performance for a three-dimensional memory device. 1. A method of forming a monolithic three-dimensional memory device , comprising:forming a stack of alternating layers comprising first material layers and second material layers over a substrate;forming a memory opening through the stack of alternating layers;forming a memory film in the memory opening;forming a first semiconductor material layer having a first band gap over the memory film; andforming a second semiconductor material layer having a second band gap that is narrower than the first band gap over the first semiconductor material layer, wherein a heterostructure quantum well is formed at an interface between the first semiconductor material layer and the second semiconductor material layer.2. The method of claim 1 , wherein:the first semiconductor material layer and the second semiconductor material layer collectively constitute a semiconductor channel;a conduction band of the semiconductor channel has a minimum along a radial direction at, or in proximity to, the interface;a quantum well containing two-dimensional electron gas for ...

Three-dimensional memory device containing etch stop structures and methods of making the same

A method of forming a semiconductor structure includes providing a dopant species selected from carbon, boron, nitrogen or oxygen into an upper portion of a semiconductor region to form a doped etch stop semiconductor material portion over a remaining semiconductor material portion, forming an overlying material portion over the etch stop semiconductor material portion, etching through the overlying material portion by an etch process that removes the overlying material portion selective to a material of the etch stop semiconductor material portion, and depositing at least one fill material over the etch stop semiconductor material portion.

Techniques for Determining Local Interconnect Defects

Techniques are presented for the determination defects in non-volatile arrays, particularly those having a 3D or BiCS type of arrangement where NAND strings run in a vertical direction relative to the substrate. In such an arrangement, the NAND strings are formed along memory holes and connected to global bit lines, and are separated into blocks or sub-blocks by vertical local interconnects, such as for source lines, and connected to a corresponding global line. To determine defective blocks, a reference current is determined based on the amount of current drawn by the local interconnects when a high voltage is applied and all of the blocks are de-selected. The amount of leakage current is determined when a selected block is biased to ground and the high voltage is applied to the interconnects. By comparing the reference current to the leakage current, a determination can be made on whether the selected block has defects related to the local interconnect structure. 1. A method of determining defects in a monolithic three-dimensional semiconductor memory device having an array of memory cells arranged in multiple physical levels above a silicon substrate and including a charge storage medium , the memory cells being formed into a plurality of blocks each having a plurality of NAND strings , wherein the NAND strings are formed above a well structure and run in a vertical direction relative to the substrate and are formed in groups between local interconnect lines that also are formed above the well structure and run in the vertical direction relative to the substrate , and wherein the local interconnect lines are connected along global interconnect lines that run in a horizontal direction relative to the substrate , the method comprising: 'biasing the array by deselecting the blocks and applying a high voltage along the global interconnect lines, and determining the reference current level from an amount of current drawn by the global interconnect lines with the array ...

Method of making a three-dimensional memory device having a heterostructure quantum well channel

A cylindrical confinement electron gas confined within a two-dimensional cylindrical region can be formed in a vertical semiconductor channel extending through a plurality of electrically conductive layers comprising control gate electrodes. A memory film in a memory opening is interposed between the vertical semiconductor channel and the electrically conductive layers. The vertical semiconductor channel includes a wider band gap semiconductor material and a narrow band gap semiconductor material. The cylindrical confinement electron gas is formed at an interface between the wider band gap semiconductor material and the narrow band gap semiconductor material. As a two-dimensional electron gas, the cylindrical confinement electron gas can provide high charge carrier mobility for the vertical semiconductor channel, which can be advantageously employed to provide higher performance for a three-dimensional memory device.

Support pillar structures for leakage reduction in a three-dimensional memory device and methods of making the same

Multiple tier structures including a respective alternating stack of insulating layers and electrically conductive layers is formed over a substrate. A memory opening fill structure extends through the alternating stacks, and includes a vertical semiconductor channel and a memory film. A support pillar structure extends through at least an upper alternating stack, and includes a dummy memory film and a dummy memory film. The support pillar structure may be narrower than the memory opening fill structure at a bottommost layer of the upper alternating stack. Additionally or alternatively, the dummy memory film may be located above a horizontal plane including a topmost surface of a lower alternating stack. Optionally, another support pillar structure including a dielectric material may be provided underneath the support pillar structure in the lower alternating stack. A dielectric material can be provided at levels of the lower alternating stack in a support pillar structure to reduce inter-level ...

Non-volatile memory with efficient testing during erase

When erasing multiple sub-blocks of a block, erase verify is performed for memory cells connected to even word lines to generate even results and for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine that the erase verify process successfully completed. For each NAND string of a first sub-block, a last even result for the NAND string is compared to a last odd result for the NAND string. Despite the determination that the first sub-block successfully completed erase verify, the erasing failed for the first sub-block because the number of NAND strings that have the last even result different than the last odd result is greater than a limit. The system determines that one or more additional sub-blocks also failed erasing based on and in response to determining that the first sub-block failed erasing.

CURRENT BASED Detection and Recording of Memory Hole-Interconnect Spacing Defects

For a non-volatile memory device having a NAND type of architecture, techniques are presented for determining NAND strings that are slow to program, including comparing the amount of current drawn by different sets of memory cells during different write operations. These techniques are particularly applicable to memory devices have a 3D structure, such as of BiCS type, where the slow programming can arise from defects of the spacing between the memory holes, in which the NAND strings are formed, and the local interconnects, such as for connecting common source lines and which run in a vertical direction between groups of NAND strings. The slow to program NAND strings can be recorded and this information can be used when writing data to the NAND strings. Several methods of writing data along a word line that includes such slow to program cells are described. 110-. (canceled)11. In a non-volatile flash memory circuit having an array of memory cells formed according to a NAND type of architecture , a method of determining NAND strings of a block of the array having slow to program memory cells , the memory cells of the NAND strings being formed along word lines and each of the NAND strings of the block connected along a corresponding bit line , the method comprising:performing a first write operation for a first set of memory cells of the block along a first word line corresponding to a first set of a plurality bit lines, but not for a second set of one or more memory cells of the block along the first word line corresponding to a second set of one or more bit lines, where the second set of bit lines is distinct from the first set of bit lines;determining an amount of current through the first set of memory cells during the first write operation;performing a second write operation for the second set of memory cells, but not for the first set of memory cells;determining an amount of current through the second set of memory cells during the second write operation; ...

Method of forming memory cell with high-k charge trapping layer

A non-volatile storage device with memory cells having a high-k charge storage region, as well as methods of fabrication, is disclosed. The charge storage region has three or more layers of dielectric materials. At least one layer is a high-k material. The high-k layer(s) has a higher trap density as compared to Si3N4. High-k dielectrics in the charge storage region enhance capacitive coupling with the memory cell channel, which can improve memory cell current, program speed, and erase speed. The charge storage region has a high-low-high conduction band offset, which may improve data retention. The charge storage region has a low-high-low valence band offset, which may improve erase.

Method of making a vertical NAND device using a sacrificial layer with air gap and sequential etching of multilayer stacks

A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and forming a sacrificial material portion including an encapsulated cavity. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material portion to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening.

Three dimensional NAND device with channel contacting conductive source line and method of making thereof

A NAND memory cell region of a NAND device includes a conductive source line that extends substantially parallel to a major surface of a substrate, a first semiconductor channel that extends substantially perpendicular to a major surface of the substrate, and a second semiconductor channel that extends substantially perpendicular to the major surface of the substrate. At least one of a bottom portion and a side portion of the first semiconductor channel contacts the conductive source line and at least one of a bottom portion and a side portion of the second semiconductor channel contacts the conductive source line.

NAND structure with tier select gate transistors

Systems and methods for improving performance of a non-volatile memory by utilizing one or more tier select gate transistors between different portions of a NAND string are described. A first memory string tier may comprise a first set of memory cell transistors that may be programmed to store a first set of data and a second memory string tier may comprise a second set of memory cell transistors that are arranged above the first set of transistors and that may be programmed to store a second set of data. Between the first set of memory cell transistors and the second set of memory cell transistors may comprise a tier select gate transistor in series with the first set of memory cell transistors and the second set of memory cell transistors. The tier select gate transistor may comprise a programmable transistor or a non-programmable transistor.

Three-dimensional memory device having a heterostructure quantum well channel

A cylindrical confinement electron gas confined within a two-dimensional cylindrical region can be formed in a vertical semiconductor channel extending through a plurality of electrically conductive layers comprising control gate electrodes. A memory film in a memory opening is interposed between the vertical semiconductor channel and the electrically conductive layers. The vertical semiconductor channel includes a wider band gap semiconductor material and a narrow band gap semiconductor material. The cylindrical confinement electron gas is formed at an interface between the wider band gap semiconductor material and the narrow band gap semiconductor material. As a two-dimensional electron gas, the cylindrical confinement electron gas can provide high charge carrier mobility for the vertical semiconductor channel, which can be advantageously employed to provide higher performance for a three-dimensional memory device.

3D memory having crystalline silicon NAND string channel

Disclosed herein are 3D NAND memory devices having vertical NAND strings with a crystalline silicon channel and techniques for fabricating the same. The NAND string channel may be a single crystal of silicon or have a few large grains of polysilicon. The single crystal may have a (100) orientation with respect to a tunnel oxide of the 3D NAND string. When the channel region comprises grains of polysilicon, predominantly all of the silicon channel is part of a grain of polysilicon having the (100) orientation. The (100) orientation may be favorable for high carrier mobility. Techniques using metal induced crystallization (MIC) for forming the NAND strings having a crystalline silicon channel are also disclosed.

Erase stress and delta erase loop count methods for various fail modes in non-volatile memory

Techniques are presented for using erase stress and variations in the loop count (number of cycles) for various fail modes in non-volatile memories, including erase disturb and shallow erase. For detection of shallow erase, cells are programmed and then erased, where the variation (delta) in the number of erase loop counts can be used to determine defective blocks. To determine blocks prone to erase disturb, an erase stress is applied to unselected blocks, after which they are programmed: after then erasing one block, the next block can then be read to determine whether it has suffered erase disturb.

Three-dimensional memory device containing source select gate electrodes with enhanced electrical isolation

A method of manufacturing a three-dimensional memory device includes forming, a bottom dielectric layer, a bottom sacrificial material layer, and an alternating stack of insulating layers and spacer material layers over a semiconductor substrate, forming a memory opening, forming an epitaxial channel portion and a memory stack structure in the memory opening, forming a backside contact trench, forming a first backside recess by selectively removing the bottom sacrificial material layer, forming a semiconductor oxide layer underneath the bottom dielectric layer and around a material of the epitaxial channel portion, forming second backside recesses by selectively removing the spacer material layers, and forming electrically conductive layers in the first and second backside recesses.

HIGH ASPECT RATIO MEMORY HOLE CHANNEL CONTACT FORMATION

A memory device and a method of fabricating a memory device that includes forming a protrusion over a substrate, an etch stop layer over the protrusion, and a stack of alternating material layers over the etch stop layer. The method further includes etching the stack to the etch stop layer to form a memory opening having a first width dimension proximate to the etch stop layer, etching the etch stop layer to provide a void area between the protrusion and a bottom of the memory opening, where the void area has a second width dimension that is larger than the first width dimension, forming a memory film over a sidewall of the memory opening and within the void area over the top surface of the protrusion, etching the memory film to expose the protrusion, and forming a semiconductor channel in the memory opening that is electrically coupled to the protrusion. 1. A method of fabricating a memory device , comprising:forming a protrusion comprising a semiconductor material over a major surface of a semiconductor substrate, the protrusion having a top surface substantially parallel to the major surface of the substrate;forming an etch stop layer over the top surface of the protrusion;forming a stack of alternating layers of a first material and a second material different from the first material over the etch stop layer;etching the stack through a mask to the etch stop layer to form a memory opening having a first width dimension proximate to the etch stop layer;etching the etch stop layer to provide a void area between the top surface of the protrusion and a bottom of the memory opening, the void area having a second width dimension that is larger than the first width dimension;forming at least a portion of a memory film over a sidewall of the memory opening and within the void area over the top surface of the protrusion;etching the memory film to expose the top surface of the protrusion; andforming a semiconductor channel in the memory opening such that the semiconductor ...

MULTILEVEL MEMORY STACK STRUCTURE AND METHODS OF MANUFACTURING THE SAME

A first stack of alternating layers including first electrically conductive layers and first electrically insulating layers is formed with first stepped surfaces and a first dielectric material portion thereupon. Dielectric pillar structures including a dielectric metal oxide can be formed through the first stepped surfaces. Lower memory openings can be formed, and filled with a disposable material or a lower memory opening structure including a lower semiconductor channel and a doped semiconductor region. At least one dielectric material layer and a second stack of alternating layers including second electrically conductive layers and second electrically insulating layers can be sequentially formed. Upper memory openings can be formed through the second stack and the at least one dielectric material layer. A memory film and a semiconductor channel can be formed after removal of the disposable material, or an upper semiconductor channel can be formed on the doped semiconductor region. 1. A monolithic three-dimensional memory device comprising:a lower stack structure comprising a first stack of alternating layers including first electrically insulating layers and first electrically conductive layers and located over a substrate;at least one dielectric material layer overlying the lower stack structure;an upper stack structure comprising a second stack of alternating layers including second electrically insulating layers and second electrically conductive layers and located over the at least one dielectric material layer;a memory opening extending through the second stack, the at least one dielectric material layer, and the first stack;a memory film and at least one semiconductor channel located within the memory opening; andat least one via contact structure vertically extending through the upper stack structure, the at least one dielectric material layer, and a portion of the lower stack structure, and electrically shorted to at least one conductive structure ...

Method of making a three-dimensional memory array with etch stop

A method of making a semiconductor device including forming a sacrificial feature over a substrate, forming a plurality of etch through regions having an etch through material and an etch stop region having an etch stop material over the sacrificial feature, forming a stack of alternating layers of a first material and a second material over the plurality of the etch through regions and the plurality of the etch stop regions, etching the stack to form a plurality of openings through the stack and through the etch through regions to expose the sacrificial feature, such that the etch through material is etched preferentially compared to the first and the second materials of the stack, removing the sacrificial feature through the plurality of openings and etching the stack to form a slit trench up to or only partially through the etch stop region, such that the first and the second materials of the stack are etched preferentially compared to the etch stop material.

NON-VOLATILE MEMORY WITH EFFICIENT TESTING DURING ERASE

When erasing multiple sub-blocks of a block, erase verify is performed for memory cells connected to even word lines to generate even results and for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine that the erase verify process successfully completed. For each NAND string of a first sub-block, a last even result for the NAND string is compared to a last odd result for the NAND string. Despite the determination that the first sub-block successfully completed erase verify, the erasing failed for the first sub-block because the number of NAND strings that have the last even result different than the last odd result is greater than a limit. The system determines that one or more additional sub-blocks also failed erasing based on and in response to determining that the first sub-block failed erasing.

Select transistors with tight threshold voltage in 3D memory

Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope.

SELECT TRANSISTORS WITH TIGHT THRESHOLD VOLTAGE IN 3D MEMORY

Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope. 1. A method of fabricating a 3D memory array , comprising:forming a plurality of alternating layers of insulator material and sacrificial material above a semiconductor substrate;forming an opening through the alternating layers of the insulator material and the sacrificial material to the semiconductor substrate;forming a pillar of crystalline semiconductor in a bottom of the opening in contact with the semiconductor substrate to form a body of a select transistor;removing a layer of the sacrificial material to form a recess that exposes a sidewall of the pillar of crystalline semiconductor;forming crystalline semiconductor on the exposed sidewall of the pillar of crystalline semiconductor;processing the crystalline semiconductor that was formed on the exposed sidewall to form a gate dielectric of the select transistor;forming a conductor in the recess adjacent to the gate dielectric to form a control gate of the select transistor; andforming a memory cell film in the opening above the pillar of crystalline ...

THREE DIMENSIONAL NAND DEVICE WITH SILICON GERMANIUM HETEROSTRUCTURE CHANNEL

A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming an at least one opening in the stack, forming at least a portion of a memory film in the at least one opening and forming a first portion of a semiconductor channel followed by forming a second portion of the semiconductor channel in the at least one opening. The second portion of the semiconductor channel comprises silicon and germanium and contains more germanium than a first portion of the semiconductor channel which is located closer to the memory film than the second portion. 1. A monolithic three dimensional NAND string , comprising:a semiconductor channel, at least one end part of the semiconductor channel extending substantially perpendicular to a major surface of a substrate;a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level, wherein the first control gate electrode is separated from the second control gate electrode by an insulating layer located between the first and second control gates;a blocking dielectric located adjacent the plurality of control gate electrodes;at least one charge storage region located adjacent the blocking dielectric; anda tunnel dielectric located between the at least one charge storage region and the semiconductor channel,wherein a second portion of the semiconductor channel comprises silicon and germanium and contains more germanium than a first portion of the semiconductor channel which is located closer to the tunnel dielectric than the second portion.2. The monolithic three ...

Fluorine-blocking insulating spacer for backside contact structure of three-dimensional memory structures

Electrical shorts caused by diffusion of residual fluorine in metallic layers can be retarded or eliminated by forming fluorine-blocking structures. A stack of alternating layers including electrically insulating layers and electrically conductive layers with a vertically extending trench is provided. In one embodiment, an insulating spacer can be formed by depositing a silicon nitride layer and partially or fully converting the silicon nitride layer into a silicon oxynitride layer, and by performing an anisotropic etch. Alternatively, an insulating spacer can be formed by forming a stack of a silicon nitride layer and a silicon oxide layer, and by performing an anisotropic etch. The silicon nitride layer or the silicon oxynitride layer can retard fluorine diffusion. Yet alternately, sidewalls of the electrically conductive layers can be nitrided to form metallic nitride portions that retard fluorine diffusion.

Semiconductor device including coupled bond pads having differing numbers of pad legs

A semiconductor device including an integrated module formed of a first semiconductor die coupled to a second semiconductor die. Each of the first and second semiconductor dies includes a number of bond pads, which are bonded to each other to form the integrated module. Each bond pad may be divided into a number of discrete pad legs. While the overall footprint of each bond pad on the first and second semiconductor dies may be the same, the bond pads on one of the dies may have a larger number of pad legs.

Three dimensional memory device containing aluminum source contact via structure and method of making thereof

A low-stress contact via structure for a device employing an alternating stack of insulating layers and electrically conductive layers over a substrate can be formed by forming a trench extending to the substrate through the alternating stack. After formation of an insulating spacer and a diffusion barrier layer, a remaining volume of the trench can be filled with a combination of an aluminum portion and a non-metallic material portion to form a contact via structure. The non-metallic material portion can include a semiconductor material portion or a dielectric material portion, and can prevent reflow of the aluminum portion and generation of a cavity in subsequent thermal processes. If a semiconductor material portion is employed, the aluminum portion and the semiconductor material portion can exchange places during a metal induced crystallization anneal process of the semiconductor material.

System and Method for Warpage Detection in a CMOS Bonded Array

A system and method for warpage detection in a CMOS bonded array includes a conductor positioned between bonded contact pads of first and second wafers. The conductor is connected to a continuity check circuit. If the continuity check circuit detects an interruption in conductivity of the conductor, such interruption is indicative of warpage in the first and/or second wafers. In one implementation, the conductor is a serpentine-shaped structure. 1. An integrated circuit comprising:a first wafer comprising a first plurality of contact pads;a second wafer comprising a second plurality of contact pads, wherein at least some of the first plurality of contact pads are bonded to at least some of the second plurality of contact pads forming a plurality of pillars;a conductor positioned in the first and second wafers and between at least some of the plurality of pillars; anda continuity check circuit electrically coupled with the conductor and configured to detect warpage in the first and/or second wafers by detecting an interruption in conductivity of the conductor.2. The integrated circuit of claim 1 , wherein the first wafer comprises a memory array and the second wafer comprises peripheral circuitry for the memory array.3. The integrated circuit of claim 2 , wherein the second wafer comprises a complementary metal-oxide-semiconductor (CMOS) wafer.4. The integrated circuit of claim 1 , wherein the continuity check circuit is in the second wafer.5. The integrated circuit of claim 1 , wherein the conductor runs through the first and second wafers and between at least some of the plurality of pillars in a serpentine shape.6. The integrated circuit of claim 1 , wherein the conductor runs across at least one of a plurality of zones in the first and second wafers.7. The integrated circuit of claim 6 , wherein the integrated circuit comprises at least one additional conductor electrically coupled with the continuity check circuit and running across at least one other zone of ...

METHODS OF FABRICATING A THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE

A method of fabricating a memory device, such as a three-dimensional NAND string, includes forming a trench through a stack of alternating first and second material layers to expose a source region of a semiconductor channel, partially filling the trench with a protective material, removing at least a portion of the alternating second material layers to form recesses between the first material layers, forming a conductive material in the recesses to form control gate electrodes for a memory device, depositing an insulating material over the sidewalls and bottom of the trench, etching through the insulating material and the protective material to expose the semiconductor channel at the trench bottom while leaving the insulating material on the trench sidewalls, and filling the trench with a source line that electrically contacts the source region while the insulating material is between the source line and the control gate electrodes along the trench sidewalls. 1. A method of fabricating a memory device , comprising:forming a trench through a stack of alternating layers of a first material and a second material different from the first material over a substrate, wherein a bottom of the trench exposes a source region in a portion of a semiconductor channel extending substantially parallel to a major surface of the substrate;filling a bottom portion of the trench with a protective material;etching the stack through the trench to remove at least a portion of the alternating layers of the second material and form recesses between the alternating layers of the first material;forming an electrically conductive material in the trench and within the recesses to form control gate electrodes for a memory device;removing the electrically conductive material from the trench;depositing an insulating material over the sidewalls of the trench and over the protective material at the bottom portion of the trench;etching through the insulating material and the protective material to ...

METHOD OF MAKING A VERTICAL NAND DEVICE USING SEQUENTIAL ETCHING OF MULTILAYER STACKS

A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and at least partially filling the lower portion of the memory openings with a sacrificial material. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening. 1. A method of making a vertical NAND device , comprising:forming a lower portion of a memory stack over a substrate;forming a lower portion of memory openings in the lower portion of the memory stack;at least partially filling the lower portion of the memory openings with a sacrificial material;forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material;forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings;removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings extending through the upper and the lower portions of the memory stack; andforming a semiconductor channel in each continuous memory opening.2. The method of claim 1 , wherein the lower and the upper portions of the memory stack comprise alternating insulating and sacrificial layers claim 1 , and wherein the sacrificial material layers are removed and replaced with a ...

Controlled string erase for nonvolatile memory

A methodology and structure for selectively erases a group of strings in a vertical NAND memory array to account for the slow to erase memory cells in the inner strands compared to the outer strands in the group. Erase signals can be applied through both the drain side connections and the source side connections in a first step to erase the outer strings. A second erase signal can be applied to the inner strands to erase the inner strands. The second signal can be applied from just the drain side connections or through both the drain side connections and the source side connections. In another embodiment, the erase signals are applied from both the source side connections and the drain side connections to the inner strings and only from the source side connections to the outer strings.

Metal layer air gap formation

Air gaps are provided to reduce interference and resistance between metal bit lines in non-volatile memory structures. Metal vias can be formed that are electrically coupled with the drain region of an underlying device and extend vertically with respect to the substrate surface to provide contacts for bit lines that are elongated in a column direction above. The metal vias can be separated by a dielectric fill material. Layer stack columns extend in a column direction over the dielectric fill and metal vias. Each layer stack column includes a metal bit line over a nucleation line. Each metal via contacts one of the layer stack columns at its nucleation line. A low temperature dielectric liner extends along sidewalls of the layer stack columns. A non-conformal dielectric overlies the layer stack columns defining a plurality of air gaps between the layer stack columns.

Support pillar structures for leakage reduction in a three-dimensional memory device

Multiple tier structures including a respective alternating stack of insulating layers and electrically conductive layers is formed over a substrate. A memory opening fill structure extends through the alternating stacks, and includes a vertical semiconductor channel and a memory film. A support pillar structure extends through at least an upper alternating stack, and includes a dummy memory film and a dummy memory film. The support pillar structure may be narrower than the memory opening fill structure at a bottommost layer of the upper alternating stack. Additionally or alternatively, the dummy memory film may be located above a horizontal plane including a topmost surface of a lower alternating stack. Optionally, another support pillar structure including a dielectric material may be provided underneath the support pillar structure in the lower alternating stack. A dielectric material can be provided at levels of the lower alternating stack in a support pillar structure to reduce inter-level ...

Three-dimensional memory device having epitaxial germanium-containing vertical channel and method of making thereof

An alternating stack of insulating layers and spacer material layers is formed over a semiconductor substrate. Memory openings are formed through the alternating stack. An optional silicon-containing epitaxial pedestal and a memory film are formed in each memory opening. After forming an opening through a bottom portion of the memory film within each memory opening, a germanium-containing semiconductor layer and a dielectric layer is formed in each memory opening. Employing the memory film and the dielectric layer as a crucible, a liquid phase epitaxy anneal is performed to convert the germanium-containing semiconductor layer into a germanium-containing epitaxial channel layer. A dielectric core and a drain region can be formed over the dielectric layer. The germanium-containing epitaxial channel layer is single crystalline, and can provide a higher charge carrier mobility than a polysilicon channel.

Three-dimensional memory device having enhanced contact between polycrystalline channel and epitaxial pedestal structure and method of making the same

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. An amorphous semiconductor material portion is formed at a bottom region of the memory opening. A memory film is formed in the memory opening. The memory film includes an opening at a bottom portion thereof, and a surface of the amorphous semiconductor material portion is physically exposed at a bottom of the opening in the memory film. An amorphous semiconductor channel material layer is formed on the exposed surface of the amorphous semiconductor material portion and over the memory film. A vertical semiconductor channel is formed by annealing the amorphous semiconductor material portion and the amorphous semiconductor channel material layer. The vertical semiconductor channel and contacts an entire top surface of an underlying semiconductor material portion.

Semiconductor device with copper interconnects separated by air gaps

A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.

STRAIGHT WIREBONDING OF SILICON DIES

A method including stacking a number of silicon dice such that one or more edges of the dice are in vertical alignment, where the one or more edges include a number of connection pads. The method also includes positioning a connecting wire on a substantially perpendicular axis to the one or more edges. The connecting wire includes a number of solder blocks formed thereon. The solder blocks are spaced at intervals associated with a distance between a first set of aligned connection pads on the dice. The connecting wire is positioned such that the solder blocks are in contact with the first set of aligned connection pads. The method also includes applying heat to cause the solder blocks to reflow and physically and electrically couple the connecting wire to the connection pads.

Offset backside contact via structures for a three-dimensional memory device

Die cracking of a three dimensional memory device may be reduced by adding offsets to backside contact via structures. Each backside contact via structure can include laterally extending portions that extend along a first horizontal direction adjoined by adjoining portions that extend along a horizontal direction other than the first horizontal direction. In order to preserve periodicity of memory stack structures extending through an alternating stack of insulating layers and electrically conductive layers, the distance between an outermost row of a string of memory stack structures between a pair of backside contact via structures and a most proximal backside contact via structure can vary from a laterally extending portion to another laterally extending portion within the most proximal backside contact via structure. Source shunt lines that are parallel to bit lines can be formed over a selected subset of offset portions of the backside contact via structures.

Techniques for detection and treating memory hole to local interconnect marginality defects

Techniques are presented for the determination and handling of defects in non-volatile arrays, particularly those having a 3D or BiCS type of arrangement where NAND strings run in a vertical direction relative to the substrate. In such an arrangement, the NAND strings are formed along memory holes and connected to global bit lines, and are separated into blocks or sub-blocks by vertical local interconnects, such as for source lines, and connected to a corresponding global line. To determine defects, an AC stress can be applied between the interconnects and the bit lines/NAND strings, after which a defect determination operation can be performed. This technique can also be implemented at the system level by having the controller instruct the memory to perform it as part of an adaptive defect determination operation.

COPPER INTERCONNECTS SEPARATED BY AIR GAPS AND METHOD OF MAKING THEREOF

A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines. 1. A semiconductor device , comprising:a plurality of copper interconnects, at least a first portion of the plurality of copper interconnects having a meniscus in a top surface; anda plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.2. The semiconductor device of claim 1 , further comprising a conformal liner on sidewalls of at least the first plurality of copper interconnects claim 1 , wherein the liner separates each of at least the first plurality of copper interconnects from two adjacent air gaps.3. The semiconductor device of claim 2 , further comprising a cap located in the meniscus on the top surface of at least the first portion of the plurality of copper interconnects.4. The semiconductor device of claim 3 , wherein the liner and the cap comprise tantalum nitride.5. The semiconductor device of claim 3 , further comprising a non-conformal insulating layer located over at least the first portion of the plurality of copper interconnects claim 3 , such that the non-conformal insulating layer does not completely fill spaces between at least the first portion of the plurality of copper interconnects to leave the plurality of air gaps.6. The semiconductor device of claim 5 , wherein the non-conformal insulating layer comprises a silicon oxide layer located in contact with the cap and an upper portion of the liner of at least the first portion of the plurality of copper interconnects.7. The semiconductor device of claim 1 , wherein the semiconductor device comprises a ...

Select transistors with tight threshold voltage in 3D memory

Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope.

Vertical memory device with bit line air gap

A structure includes a three-dimensional semiconductor device including a plurality of unit device structures located over a substrate. Each of the unit device structures includes a semiconductor channel including at least a portion extending vertically along a direction perpendicular to a top surface of the substrate, and a drain region contacting a top end of the semiconductor channel. The structure also includes a combination of a plurality of contact pillars and a contiguous volume that laterally surrounds the plurality of contact pillars. The plurality of contact pillars is in contact with the drain regions, and the contiguous volume has a dielectric constant less than 3.9.

Copper Interconnects Separated by Air Gaps and Method of Making Thereof

A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.

Three-dimensional memory device having enhanced contact between polycrystalline channel and epitaxial pedestal structure and method of making the same

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. An amorphous semiconductor material portion is formed at a bottom region of the memory opening. A memory film is formed in the memory opening. The memory film includes an opening at a bottom portion thereof, and a surface of the amorphous semiconductor material portion is physically exposed at a bottom of the opening in the memory film. An amorphous semiconductor channel material layer is formed on the exposed surface of the amorphous semiconductor material portion and over the memory film. A vertical semiconductor channel is formed by annealing the amorphous semiconductor material portion and the amorphous semiconductor channel material layer. The vertical semiconductor channel and contacts an entire top surface of an underlying semiconductor material portion.

Three dimensional NAND device with silicon germanium heterostructure channel

A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming an at least one opening in the stack, forming at least a portion of a memory film in the at least one opening and forming a first portion of a semiconductor channel followed by forming a second portion of the semiconductor channel in the at least one opening. The second portion of the semiconductor channel comprises silicon and germanium and contains more germanium than a first portion of the semiconductor channel which is located closer to the memory film than the second portion.

3D Vertical NAND With III-V Channel

Disclosed herein is 3D memory with vertical NAND strings having a III-V compound channel, as well as methods of fabrication. The III-V compound has at least one group III element and at least one group V element. The III-V compound provides for high electron mobility transistor cells. Note that III-V materials may have a much higher electron mobility compared to silicon. Thus, much higher cell current and overall cell performance can be achieved. Also, the memory device may have better read-write efficiency due to much higher carrier mobility and velocity. The tunnel dielectric of the memory cells may have an Al 2 O 3 film in direct contact with the III-V NAND channel. The drain end of the NAND channel may be a metal-III-V alloy in direct contact with a metal region. The body of the source side select transistor could be formed from the III-V compound or from crystalline silicon.

Single-semiconductor-layer channel in a memory opening for a three-dimensional non-volatile memory device

A memory film layer is formed in a memory opening through an alternating stack of first material layers and second material layers. A sacrificial material layer is deposited on the memory film layer. Horizontal portions of the sacrificial material layer and the memory film layer at the bottom of the memory opening is removed by an anisotropic etch to expose a substrate underlying the memory opening, while vertical portions of the sacrificial material layer protect vertical portions of the memory film layer. After removal of the sacrificial material layer selective to the memory film, a doped semiconductor material layer can be formed directly on the exposed material in the memory opening and on the memory film as a single material layer to form a semiconductor channel of a memory device.

THREE DIMENSIONAL NAND STRING MEMORY DEVICES AND METHODS OF FABRICATION THEREOF

A method of making a monolithic three dimensional NAND string includes forming a stack of alternating first and second material layers over a substrate, etching the stack to form a front side opening, partially removing the second material layers through the front side opening to form front side recesses, forming a first blocking dielectric in the front side recesses, forming charge storage regions over the first blocking dielectric in the front side recesses, forming a tunnel dielectric layer and a semiconductor channel over the charge storage regions in the front side opening, etching the stack to form a back side opening, removing the second material layers through the back side opening to form back side recesses using the first blocking dielectric as an etch stop, forming a second blocking dielectric in the back side recesses, and forming control gates over the second blocking dielectric in the back side recesses. 1. A method of making a monolithic three dimensional NAND string , comprising:forming a stack of alternating layers of a first material and a second material different than the first material over a substrate;etching the stack to form a front side opening in the stack;removing a first portion of the second material layers through the front side opening to form front side recesses between the first material layers;forming a first blocking dielectric in the front side recesses through the front side opening;forming charge storage regions over the first blocking dielectric in the front side recesses through the front side opening;forming a tunnel dielectric layer over the charge storage regions in the front side opening;forming a semiconductor channel layer over the tunnel dielectric layer in the front side opening;etching the stack to form a back side opening in the stack;removing by etching at least a second portion of the second material layers through the back side opening to form back side recesses between the first material layers using the first ...

PROCESS FOR FABRICATING NON-VOLATILE STORAGE

Fabricating non-volatile storage includes creating gate stacks with hard masks on top of the gate stacks. The gate stacks include two polysilicon layers and a dielectric layer between the two polysilicon layers. A portion of the hard mask over each gate stack is removed, leaving two separate tapered sections of each of the hard masks positioned above an upper polysilicon layer of the gate stacks. After the removing the portion of the hard masks, fluorine is implanted into the upper polysilicon layer of the gate stacks. Metal is added on the top surface of the upper polysilicon layer of the floating gate stacks. A silicidation process for the metal and the upper polysilicon layer of the gate stacks is preformed and the remaining tapered sections of the hard mask are removed. Other control lines can then be added.

Straight wirebonding of silicon dies

A method including stacking a number of silicon dice such that one or more edges of the dice are in vertical alignment, where the one or more edges include a number of connection pads. The method also includes positioning a connecting wire on a substantially perpendicular axis to the one or more edges. The connecting wire includes a number of solder blocks formed thereon. The solder blocks are spaced at intervals associated with a distance between a first set of aligned connection pads on the dice. The connecting wire is positioned such that the solder blocks are in contact with the first set of aligned connection pads. The method also includes applying heat to cause the solder blocks to reflow and physically and electrically couple the connecting wire to the connection pads.

Amorphous Silicon Layer In Memory Device Which Reduces Neighboring Word Line Interference

Techniques for fabricating a memory device which has reduced neighboring word line interference, and a corresponding memory device. The memory device comprises a stack of alternating conductive and dielectric layers, where the conductive layers form word lines or control gates of memory cells. In one aspect, rounding off of the control gate layers due to inadvertent oxidation during fabrication is avoided. An amorphous silicon layer is deposited along the sidewall of the memory holes, adjacent to the control gate layers. SiNis deposited along the amorphous silicon layer and oxidized in the memory hole to form SiO. The amorphous silicon layer acts as an oxidation barrier for the sacrificial material of the control gate layers. The amorphous silicon layer is subsequently oxidized to also form SiO. The two SiOlayers together form a blocking oxide layer. 1. A method , comprising:forming a stack of alternating dielectric layers and control gate layers, the control gate layers comprising a sacrificial material;forming a memory hole which extends through the stack, the memory hole comprising a sidewall;depositing an amorphous silicon layer along the sidewall, adjacent to the dielectric layers and the control gate layers, from a bottom of the memory hole to a top of the memory hole;depositing a material comprising silicon in the memory hole, adjacent to the amorphous silicon layer, from the bottom of the memory hole to the top of the memory hole;oxidizing the material comprising silicon in the memory hole to provide a material comprising oxidized silicon;forming a slit in the stack;providing an etchant in the slit to remove the sacrificial material, creating voids in the control gate layers which expose portions of the amorphous silicon layer at heights of the control gate layers;oxidizing the exposed portions of the amorphous silicon layer at the heights of the control gate layers and portions of the amorphous silicon layer which are at heights of the dielectric layers to ...

Column erasing in non-volatile memory strings

Strings of non-volatile memory cells include one or more joint regions adjacent to dummy non-volatile memory cells. During erase operations, different voltage levels are used for different dummy word lines coupled to respective dummy non-volatile memory cells. For example, a selection circuit may set a voltage level of a particular dummy word line to a voltage level greater than a different dummy word line. In another example, the selection circuit may determine a voltage level for a given dummy word line based on a distance between a non-volatile memory cell coupled to the given dummy word line and a selection device included in a string of non-volatile memory cells. Electron holes generated using the dummy word lines during erase operations may neutralize undesired trapped charges in a non-volatile memory string, thereby reducing disparity in erase times for different strings in the non-volatile memory circuit.

Reducing Neighboring Word Line In Interference Using Low-K Oxide

Techniques for fabricating a memory device which has reduced neighboring word line interference, and a corresponding memory device. The memory device comprises a stack of alternating conductive and dielectric layers, where the conductive layers form word lines or control gates of memory cells. In one aspect, the memory device is provided with a reduced dielectric constant (k) in locations of a fringing electric field of the control gate. For example, portions of the dielectric layers can be replaced with a low-k material. One approach involves recessing the dielectric layer and providing a low-k material in the recess. Another approach involves doping a portion of the blocking oxide layer to reduce its dielectric constant. Another approach involves removing a portion of the blocking oxide layer. In another aspect, the memory device is provided with an increased dielectric constant adjacent to the control gates. 1. A method , comprising:forming a stack of alternating dielectric layers and control gate layers;forming a memory hole which extends through the alternating dielectric layers and control gate layers, the memory hole comprising a sidewall;providing an etchant in the memory hole to etch back the dielectric layers to form recesses in the dielectric layers adjacent to a recessed dielectric material of the dielectric layers;depositing a low-k material in the memory hole, the low-k material having a dielectric constant which is lower than a dielectric constant of the dielectric layers, and the low-k material conforms to a shape of the sidewall by filling the recesses and covering edges of the control gates layers which face the memory hole;perform slimming to remove excess portions of the low-k material in the memory hole; andafter the slimming, depositing a continuous blocking oxide layer along the sidewall.2. (canceled)3. The method of claim 1 , wherein:the low-k material comprises at least one of an F-doped oxide, a C-doped oxide or an H-doped oxide.4. The ...

Process for fabricating non-volatile storage

Fabricating non-volatile storage includes creating gate stacks with hard masks on top of the gate stacks. The gate stacks include two polysilicon layers and a dielectric layer between the two polysilicon layers. A portion of the hard mask over each gate stack is removed, leaving two separate tapered sections of each of the hard masks positioned above an upper polysilicon layer of the gate stacks. After the removing the portion of the hard masks, fluorine is implanted into the upper polysilicon layer of the gate stacks. Metal is added on the top surface of the upper polysilicon layer of the floating gate stacks. A silicidation process for the metal and the upper polysilicon layer of the gate stacks is preformed and the remaining tapered sections of the hard mask are removed. Other control lines can then be added.

Inter-plane offset in backside contact via structures for a three-dimensional memory device

A three-dimensional memory device includes a plurality of planes, each having a respective alternating stack, strings of memory stack structures which extends through the respective alternating stack, and backside contact via structures vertically extending through the respective alternating stack, extending generally along the first horizontal direction, and laterally separating neighboring pairs of strings of memory stack structures along a second horizontal direction. A first plane includes a first plurality of strings that are laterally spaced apart along the second horizontal direction by a first plurality of backside contact via structures. A second plane laterally shifted from the first plane along the first horizontal direction and including a second plurality of strings that are laterally spaced apart along the second horizontal direction by a second plurality of backside contact via structures which are laterally offset with respect the first plurality of backside contact via ...

STRESS PATTERNS TO DETECT SHORTS IN THREE DIMENSIONAL NON-VOLATILE MEMORY

A non-volatile storage system includes a three dimensional structure comprising vertical columns of memory cells and a managing circuit in communication with the vertical columns The managing circuit applies one or more patterns of stress voltages to the vertical columns, with different voltages applied to each vertical column of pairs of adjacent vertical columns being tested for shorts. The managing circuit tests for a short in the pairs of adjacent vertical columns after applying the one or more patterns of stress voltages. In one embodiment, the test may comprise programming a memory cell in each vertical column with data that matches the pattern of stress voltages, reading from the memory cells and determining whether data read matches data programmed. The applying of the stress voltages and the testing can be performed as part of a test during manufacturing or in the field during user operation. 1. An apparatus , comprising:a plurality of non-volatile memory cells arranged in a three dimensional structure comprising a plurality of vertical columns with each vertical column of the plurality including multiple memory cells; anda managing circuit in communication with the vertical columns, the managing circuit is configured to apply one or more patterns of stress voltages to the plurality of vertical columns of non-volatile memory cells with different voltages applied to each vertical column of pairs of adjacent vertical columns being tested for shorts, the managing circuit is configured to test for a defect in the pairs of adjacent vertical columns after applying the one or more patterns of stress voltages.2. The apparatus of claim 1 , wherein:the managing circuit is configured to apply the one or more patterns of stress voltages by applying different patterns of stress voltages, each pattern of stress voltages is configured to test for different sets of shorts between pairs of adjacent vertical columns; andthe managing circuit is configured to test for a short ...

Prevention of latent block fails in three-dimensional NAND

Technology is disclosed for detecting latent defects in non-volatile storage systems. Prior to writing data, a stress voltage is applied to SGS transistors in a 3D memory structure. After applying the stress voltage, the Vt of the SGS transistors are tested to determine whether they meet a criterion. The criterion may be whether a Vt distribution of the SGS transistors falls within an allowed range. If the criterion is not met, then a sub-block mode may be enabled. In the sub-block mode, data is not written to memory cells in a sub-block that contains SGS transistors whose Vt does not meet the criterion. Hence, the possibility of data loss due to defective SGS transistors is avoided. However, in the sub-block mode, data is written to memory cells in a sub-block that does not contain SGS transistors whose Vt does not meet the criterion. Hence, data capacity is preserved.

Methods for manufacturing ultrathin semiconductor channel three-dimensional memory devices

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack to the substrate. After formation of memory film layers, a sacrificial cover material layer can be employed to protect the tunneling dielectric layer during formation of a bottom opening in the memory film layers. An amorphous semiconductor material layer can be deposited and optionally annealed in an ambient including argon and/or deuterium to form a semiconductor channel layer having a thickness less than 5 nm and surface roughness less than 10% of the thickness. Alternately or additionally, at least one interfacial layer can be employed on either side of the amorphous semiconductor material layer to reduce surface roughness of the semiconductor channel. The ultrathin channel can have enhanced mobility due to quantum confinement effects.

Metal Layer Air Gap Formation

Air gaps are provided to reduce interference and resistance between metal bit lines in non-volatile memory structures. Metal vias can be formed that are electrically coupled with the drain region of an underlying device and extend vertically with respect to the substrate surface to provide contacts for bit lines that are elongated in a column direction above. The metal vias can be separated by a dielectric fill material. Layer stack columns extend in a column direction over the dielectric fill and metal vias. Each layer stack column includes a metal bit line over a nucleation line. Each metal via contacts one of the layer stack columns at its nucleation line. A low temperature dielectric liner extends along sidewalls of the layer stack columns. A non-conformal dielectric overlies the layer stack columns defining a plurality of air gaps between the layer stack columns. 1. A non-volatile memory system , comprising:a plurality of metal vias, each metal via electrically coupled to a drain region of one of a plurality of groups of non-volatile storage elements;a plurality of layer stack columns extending in a column direction over the plurality of metal vias, each layer stack column includes a nucleation line in contact with at least one of the plurality of metal vias, a metal bit line in contact with the strip of nucleation material, and a cap line over the metal bit line, each layer stack column including sidewalls extending in the column direction;a low temperature dielectric liner extending along the sidewalls of the plurality of layer stack columns;a non-conformal cap layer overlying the plurality of layer stack columns; anda plurality of air gaps extending in the column direction between adjacent layer stack columns.2. A non-volatile memory system according to claim 1 , wherein:the metal bit line of each layer stack column is formed of tungsten; andthe nucleation line of each layer stack column is formed of tungsten nitride.3. A non-volatile memory system according ...

Method of forming 3D vertical NAND with III-V channel

Disclosed herein is 3D memory with vertical NAND strings having a III-V compound channel, as well as methods of fabrication. The III-V compound has at least one group III element and at least one group V element. The III-V compound provides for high electron mobility transistor cells. Note that III-V materials may have a much higher electron mobility compared to silicon. Thus, much higher cell current and overall cell performance can be achieved. Also, the memory device may have better read-write efficiency due to much higher carrier mobility and velocity. The tunnel dielectric of the memory cells may have an Al2O3 film in direct contact with the III-V NAND channel. The drain end of the NAND channel may be a metal-III-V alloy in direct contact with a metal region. The body of the source side select transistor could be formed from the III-V compound or from crystalline silicon.

COLUMN ERASING IN NON-VOLATILE MEMORY STRINGS

Strings of non-volatile memory cells include one or more joint regions adjacent to dummy non-volatile memory cells. During erase operations, different voltage levels are used for different dummy word lines coupled to respective dummy non-volatile memory cells. For example, a selection circuit may set a voltage level of a particular dummy word line to a voltage level greater than a different dummy word line. In another example, the selection circuit may determine a voltage level for a given dummy word line based on a distance between a non-volatile memory cell coupled to the given dummy word line and a selection device included in a string of non-volatile memory cells. Electron holes generated using the dummy word lines during erase operations may neutralize undesired trapped charges in a non-volatile memory string, thereby reducing disparity in erase times for different strings in the non-volatile memory circuit. 1. An apparatus , comprising: a plurality of non-volatile memory cells;', 'a joint region positioned between ends of the NAND strings; and', 'a plurality of dummy non-volatile memory cells each adjacent to the joint region; and, 'a plurality of NAND strings each NAND string coupled to a source line and includinga control circuit configured to set a plurality of dummy word lines to different voltage levels as part of executing an erase command, wherein each of the plurality of dummy word lines is coupled to a respective one of the plurality of dummy non-volatile memory cells.2. The apparatus of claim 1 , wherein each NAND string further includes a selection device coupled to the source line and a bit line claim 1 , and wherein the control circuit is further configured to select a voltage level for a particular dummy word line based on a distance from a corresponding dummy non-volatile memory cell coupled to the particular dummy word line to the selection device.3. The apparatus of claim 2 , wherein to select the voltage level for the particular dummy word ...

System and method for warpage detection in a CMOS bonded array

A system and method for warpage detection in a CMOS bonded array includes a conductor positioned between bonded contact pads of first and second wafers. The conductor is connected to a continuity check circuit. If the continuity check circuit detects an interruption in conductivity of the conductor, such interruption is indicative of warpage in the first and/or second wafers. In one implementation, the conductor is a serpentine-shaped structure.

High aspect ratio memory hole channel contact formation

A memory device and a method of fabricating a memory device that includes forming a protrusion over a substrate, an etch stop layer over the protrusion, and a stack of alternating material layers over the etch stop layer. The method further includes etching the stack to the etch stop layer to form a memory opening having a first width dimension proximate to the etch stop layer, etching the etch stop layer to provide a void area between the protrusion and a bottom of the memory opening, where the void area has a second width dimension that is larger than the first width dimension, forming a memory film over a sidewall of the memory opening and within the void area over the top surface of the protrusion, etching the memory film to expose the protrusion, and forming a semiconductor channel in the memory opening that is electrically coupled to the protrusion.

Protective structure to prevent short circuits in a three-dimensional memory device

In a three-dimensional stacked non-volatile memory device, a short circuit is prevented in a select gate layer by providing a protective material such as a diode, capacitor, linear resistor or varistor between select gate lines and a remaining portion of the select gate layer. Charges which are accumulated in the select gate lines due to plasma etching are therefore prevented from discharging through the remaining portion in a short circuit path when the select gate lines are driven. The protective material can comprise a p-n diode, an n-i-n or p-i-p resistor, a thin oxide layer between doped polysilicon layers in a capacitor, or a variable-resistance material such as ZnO2 between oxide layers in a varistor.

Memory cell with high-k charge trapping layer

A non-volatile storage device with memory cells having a high-k charge storage region, as well as methods of fabrication, is disclosed. The charge storage region has three or more layers of dielectric materials. At least one layer is a high-k material. The high-k layer(s) has a higher trap density as compared to Si 3 N 4 . High-k dielectrics in the charge storage region enhance capacitive coupling with the memory cell channel, which can improve memory cell current, program speed, and erase speed. The charge storage region has a high-low-high conduction band offset, which may improve data retention. The charge storage region has a low-high-low valence band offset, which may improve erase.

Three-dimensional memory device containing a silicon nitride ring in an opening in a memory film and method of making the same

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. A memory film including a silicon nitride layer and a tunneling dielectric layer is formed in the memory opening, and an opening is formed through the memory film. A chemical oxide layer is formed on a physically exposed surface of an underlying semiconductor material portion. A silicon nitride ring can be formed by selectively growing a silicon nitride material from an annular silicon nitride layer portion of the silicon nitride layer while suppressing deposition of the silicon nitride material on the tunneling dielectric layer and on the chemical oxide layer. A vertical semiconductor channel can be formed by depositing a continuous semiconductor material layer on the underlying semiconductor material portion and the tunneling dielectric layer and on the silicon nitride ring.

Three-dimensional memory structure with multi-component contact via structure and method of making thereof

A contact via structure can include a ruthenium portion formed by selective deposition of ruthenium on a semiconductor surface at the bottom of a contact trench. The ruthenium-containing portion can reduce contact resistance at the interface with an underlying doped semiconductor region. At least one conductive material portion can be formed in the remaining volume of the contact trench to form a contact via structure. Alternatively or additionally, a contact via structure can include a tensile stress-generating portion and a conductive material portion. In case the contact via structure is formed through an alternating stack of insulating layers and electrically conductive layers that include a compressive stress-generating material, the tensile stress-generating portion can at least partially cancel the compressive stress generated by the electrically conductive layers. The conductive material portion of the contact via structure can include a metallic material or a doped semiconductor ...

3D vertical NAND with III-V channel

Disclosed herein is 3D memory with vertical NAND strings having a III-V compound channel, as well as methods of fabrication. The III-V compound has at least one group III element and at least one group V element. The III-V compound provides for high electron mobility transistor cells. Note that III-V materials may have a much higher electron mobility compared to silicon. Thus, much higher cell current and overall cell performance can be achieved. Also, the memory device may have better read-write efficiency due to much higher carrier mobility and velocity. The tunnel dielectric of the memory cells may have an Al2O3 film in direct contact with the III-V NAND channel. The drain end of the NAND channel may be a metal-III-V alloy in direct contact with a metal region. The body of the source side select transistor could be formed from the III-V compound or from crystalline silicon.

Stress patterns to detect shorts in three dimensional non-volatile memory

A non-volatile storage system includes a three dimensional structure comprising vertical columns of memory cells and a managing circuit in communication with the vertical columns. The managing circuit applies one or more patterns of stress voltages to the vertical columns, with different voltages applied to each vertical column of pairs of adjacent vertical columns being tested for shorts. The managing circuit tests for a short in the pairs of adjacent vertical columns after applying the one or more patterns of stress voltages. In one embodiment, the test may comprise programming a memory cell in each vertical column with data that matches the pattern of stress voltages, reading from the memory cells and determining whether data read matches data programmed. The applying of the stress voltages and the testing can be performed as part of a test during manufacturing or in the field during user operation.

Program disturb improvements in multi-tier memory devices including improved non-data conductive gate implementation

Techniques for reducing program disturb of memory cells which are formed in a NAND string extending in a lower tier and an upper tier of a stack, the lower tier including a first plurality of memory cells and the upper tier including a second plurality of memory cells, wherein each memory cell of the first and second pluralities of memory cells is connected to a respective word line. The NAND string includes a joint region formed of a dielectric material and disposed between the lower tier and the upper tier of the stack; a first non-data memory cell adjacent to and below the joint region; a second non-data memory cell adjacent to and above the joint region; and a conductive gate connected to the first non-data memory cell and the second non-data memory cell.

Multiple liner interconnects for three dimensional memory devices and method of making thereof

An opening is formed through at least one dielectric material layer. A first metallic liner is formed on a bottom surface and sidewalls of the opening by depositing a first metallic material. A metal portion including an elemental metal or an intermetallic alloy of at least two elemental metals is formed on the first metallic liner. A second metallic liner including a second metallic material is formed directly on a top surface of the metal portion. The first metallic material and the second metallic material differ in composition. The first metallic liner and the second metallic liner contact an entirety of all surfaces of the metal portion. The first and second metallic liners can protect the metal portion from a subsequently deposited dielectric material layer, which may be formed as an air-gap dielectric layer after recessing the at least one dielectric material layer.

High aspect ratio memory hole channel contact formation

A method of fabricating a semiconductor device, such as a three-dimensional monolithic NAND memory string, includes etching a select gate electrode over a first gate insulating layer over a substrate to form an opening, forming a second gate insulating layer over the sidewalls of the opening, forming a sacrificial spacer layer over the second gate insulating layer on the sidewalls of the opening, and etching the first gate insulating layer over the bottom surface of the opening to expose the substrate, removing the sacrificial spacer layer to expose the second gate insulating layer over the sidewalls of the opening, and forming a protrusion comprising a semiconductor material within the opening and contacting the substrate, wherein the second gate insulating layer is located between the select gate electrode and first and second side surfaces of the protrusion.

METHODS OF FABRICATING A THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE

A method of fabricating a semiconductor device, such as a three-dimensional NAND memory string, includes forming a first stack of alternating layers of a first material and a second material different from the first material over a substrate, removing a portion of the first stack to form a first trench, filling the trench with a sacrificial material, forming a second stack of alternating layers of the first material and the second material over the first stack and the sacrificial material, removing a portion of the second stack to the sacrificial material to form a second trench, and removing the sacrificial material to form a continuous trench through the first stack and the second stack.

Three dimensional NAND devices with air gap or low-k core

A monolithic three dimensional NAND string device includes a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate in different device levels, a blocking dielectric located in contact with the plurality of control gate electrodes, at least one charge storage region located in contact with the blocking dielectric, and a tunnel dielectric located between the at least one charge storage region and the semiconductor channel. The semiconductor channel is a hollow body surrounding a middle region and at least one of an air gap or a low-k insulating material having a dielectric constant of less than 3.9 is located in the middle region.

Ultrathin semiconductor channel three-dimensional memory devices

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack to the substrate. After formation of memory film layers, a sacrificial cover material layer can be employed to protect the tunneling dielectric layer during formation of a bottom opening in the memory film layers. An amorphous semiconductor material layer can be deposited and optionally annealed in an ambient including argon and/or deuterium to form a semiconductor channel layer having a thickness less than 5 nm and surface roughness less than 10% of the thickness. Alternately or additionally, at least one interfacial layer can be employed on either side of the amorphous semiconductor material layer to reduce surface roughness of the semiconductor channel. The ultrathin channel can have enhanced mobility due to quantum confinement effects.

High stack 3D memory and method of making

A method of making a monolithic three dimensional NAND device includes forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming a mask layer over the stack and patterning the mask layer to form at least on opening in the mask layer to expose a top layer of the stack. The method also includes forming a metal block in the at least one opening in the mask layer, etching the stack by metal induced localized etch using the metal block in the at least one opening in the mask layer to form at least one opening in the stack and forming at least one layer of the NAND device in the at least one opening.

Multilevel memory stack structure employing support pillar structures

A first stack of alternating layers including first electrically insulating layers and first sacrificial material layers is formed with first stepped surfaces. First memory openings can be formed in a device region outside of the first stepped surfaces, and first support openings can be formed through the first stepped surfaces. The first memory openings and the first support openings can be filled with a sacrificial fill material. A second stack of alternating layers including second electrically insulating layers and second sacrificial material layers can be formed over the first stack. Inter-stack memory openings including the first memory openings can be formed in the device region, and inter-stack support openings including the first support openings can be formed in a steppes surface region. Memory stack structures and support pillar structure are simultaneously formed in the inter-stack memory openings and the inter-stack support openings, respectively.

Three dimensional memory device with hybrid source electrode for wafer warpage reduction

The metallic material content of a contact via structure for a three-dimensional memory device can be reduced by employing a vertical stack of a doped semiconductor material portion and a metallic fill material portion. A backside contact via can be filled with an outer metallic layer, a lower conductive material portion, an inner metallic layer, and an upper conductive material portion to form a contact via structure such that one of the lower and upper conductive material portions is a doped semiconductor material portion and the other is a metallic fill material portion. The doped semiconductor material generates less stress than the metallic fill material per volume, and thus, the contact via structure can reduce stress applied to surrounding regions in the three-dimensional memory device.

Method of forming an active area with floating gate negative offset profile in FG NAND memory

A stack can be patterned by a first etch process to form an opening defining sidewall surfaces of a patterned material stack. A masking layer can be non-conformally deposited on sidewalls of an upper portion of the patterned material stack, while not being deposited on sidewalls of a lower portion of the patterned material stack. The sidewalls of a lower portion of the opening can be laterally recessed employing a second etch process, which can include an isotropic etch component. The sidewalls of the upper portion of the opening can protrude inward toward the opening to form an overhang over the sidewalls of the lower portion of the opening. The overhang can be employed to form useful structures such as an negative offset profile in a floating gate device or vertically aligned control gate electrodes for vertical memory devices.

Contact for vertical memory with dopant diffusion stopper and associated fabrication method

A memory device and corresponding fabrication method prevent undesired diffusion of dopants from a silicon cap of a vertical NAND string to a channel film of the NAND string. Initially, a memory hole is provided in a stack of alternating control gate layers and dielectric layers. The memory hole is filled with annular films and a dielectric core filler. The dielectric core filler is etched back from a top of the memory hole to a topmost control gate layer, forming a void. A dopant stopper liner is deposited in the void before depositing n+ doped silicon which forms the silicon cap. The dopant stopper liner can be a conductive material such as metal or polysilicon doped with carbon. A conductive via is then formed above, and aligned with, the top of the silicon cap. A bit line may be formed over the conductive via.

SEMICONDUCTOR DEVICE INCLUDING VERTICAL BOND PADS

The present technology relates to a semiconductor device including semiconductor dies formed with vertical die bond pads on an edge of the dies. During wafer fabrication, vertical bond pad blocks are formed in scribe lines of the wafer and electrically coupled to the die bond pads of the semiconductor dies. The vertical bond pad blocks are cut through during wafer dicing, thereby leaving large, vertically oriented pads exposed on a vertical edge of each semiconductor die.

THREE-DIMENSIONAL MEMORY DEVICES HAVING A SHAPED EPITAXIAL CHANNEL PORTION

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A dielectric collar structure can be formed prior to formation of an epitaxial channel portion, and can be employed to protect the epitaxial channel portion during replacement of the sacrificial material layers with electrically conductive layers. Exposure of the epitaxial channel portion to an etchant during removal of the sacrificial material layers is avoided through use of the dielectric collar structure. Additionally or alternatively, facets on the top surface of the epitaxial channel portion can be reduced or eliminated by forming the epitaxial channel portion to a height that exceeds a target height, and by recessing a top portion of the epitaxial channel portion. The recess etch can remove protruding portions of the epitaxial channel portion at a greater removal rate than a non-protruding portion. 1. A three-dimensional memory device comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;a memory opening extending through the alternating stack;an epitaxial channel portion located at a bottom of the memory opening and contacting a portion of the substrate;a memory stack structure overlying the epitaxial channel portion and located in the memory opening; anda dielectric collar structure laterally surrounding at least the epitaxial channel portion and having a first thickness region having a first thickness and a second thickness region having a second thickness that is greater than the first thickness, the second thickness region being located at a level of one of the electrically conductive layers and contacting an outer sidewall of the epitaxial channel portion.2. The three-dimensional memory device of claim 1 , wherein an outer sidewall of the second thickness region protrudes outward from a vertical plane including an outer sidewall of the first thickness region.3. The three-dimensional memory ...

Different word line programming orders in non-volatile memory for error recovery

An apparatus includes non-volatile memory and a control circuit configured to program the non-volatile memory. The control circuit is configured to change a programming order. In one aspect, the control circuit changes the order in which word lines are programmed from one point in time to another. In one aspect, the control circuit uses one order for programming one set of word lines and a different order for a different set of word lines. The sets of word lines could be in different sub-blocks, memory blocks, or memory dies. Such programming order differences can improve performance of error recovery.

SELECT TRANSISTORS WITH TIGHT THRESHOLD VOLTAGE IN 3D MEMORY

Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope. 1. An apparatus , comprising:a semiconductor substrate having a major surface; a body formed from a solid pillar of semiconductor in contact with the semiconductor substrate;', 'a conductive floating gate that is completely surrounded by insulators in direct contact with the conductive floating gate;', 'a conductive control gate;', 'a first dielectric between the conductive floating gate and the conductive control gate; and', 'a second dielectric between the body and the conductive floating gate; and, 'a select transistor comprisinga string of memory cells that extends vertically with respect to the major surface of the semiconductor substrate, the string having a string channel, wherein the solid pillar of semiconductor of the select transistor is in contact with the string channel.2. The apparatus of claim 1 , wherein the conductive floating gate surrounds the solid pillar of semiconductor.3. The apparatus of claim 1 , wherein the conductive floating gate comprises polysilicon.4. The apparatus of claim 1 , wherein ...

Techniques for detecting broken word lines in non-volatile memories

Techniques for determining broken word lines in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. One set of techniques uses test program operation that alternates a standard staircase waveform with an elongated verify operation. This allows for a more accurate verify of under-programmed broken word lines relative to the standard verify operation. Another set of techniques looks at the ramp rate along the interconnect between the word line decoding circuitry and the main part of the word line. These techniques can also be used for determining defective select gate lines of an array with a NAND type structure.

THREE-DIMENSIONAL MEMORY STRUCTURE WITH MULTI-COMPONENT CONTACT VIA STRUCTURE AND METHOD OF MAKING THEREOF

A contact via structure can include a ruthenium portion formed by selective deposition of ruthenium on a semiconductor surface at the bottom of a contact trench. The ruthenium-containing portion can reduce contact resistance at the interface with an underlying doped semiconductor region. At least one conductive material portion can be formed in the remaining volume of the contact trench to form a contact via structure. Alternatively or additionally, a contact via structure can include a tensile stress-generating portion and a conductive material portion. In case the contact via structure is formed through an alternating stack of insulating layers and electrically conductive layers that include a compressive stress-generating material, the tensile stress-generating portion can at least partially cancel the compressive stress generated by the electrically conductive layers. The conductive material portion of the contact via structure can include a metallic material or a doped semiconductor material. 1. A structure comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;an insulating spacer located at a periphery of a contact trench that extends through the alternating stack; and a ruthenium-containing portion contacting a top surface of a doped semiconductor portion located in or over the substrate; and', 'at least one conductive material portion overlying the ruthenium-containing portion and located within an inner sidewall of the insulating spacer., 'a contact via structure laterally surrounded by the insulating spacer and comprising2. The structure of claim 1 , wherein the at least one conductive material portion comprises:a metallic diffusion barrier layer contacting a top surface of the ruthenium-containing portion and the inner sidewall of the insulating spacer; anda conductive fill material portion surrounded by the metallic diffusion barrier layer.3. The structure of claim 2 , wherein:the metallic ...

NON-VOLATILE MEMORY WITH EFFICIENT TESTING DURING ERASE

A non-volatile memory system erasing groups of connected memory cells separately performs erase verify for memory cells connected to even word lines to generate even results and erase verify for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine if the erase verify process indicates that the erasing has successful completed. In addition, for each group of connected memory cells, a last even result for the group is compared to a last odd result for the group. Even if the erase verify indicated that the erasing has successfully completed, the system may determine that the erasing failed (i.e. due to a defect) if the number of groups of connected memory cells that have the last even result different than the last odd result is greater than a limit.

MEMORY CONTROLLER FOR RESOLVING STRING TO STRING SHORTS

A memory controller includes, in one embodiment, a memory interface and a controller circuit. The memory interface is configured to interface with a memory interface configured to interface with a memory having a plurality of memory blocks. Each memory block has a plurality of strings. The controller circuit is configured to perform a string defect leakage check on one of the memory blocks during a first programming operation of the one memory block, determine whether the one memory block has one or more string to string shorts based on the string defect leakage check, and resolve the string to string shorts in response to determining that the one of the memory blocks has the string to string shorts.

Crystalline layer stack for forming conductive layers in a three-dimensional memory structure

A stack of alternating layers comprising first epitaxial semiconductor layers and second epitaxial semiconductor layers is formed over a single crystalline substrate. The first and second epitaxial semiconductor layers are in epitaxial alignment with a crystal structure of the single crystalline substrate. The first epitaxial semiconductor layers include a first single crystalline semiconductor material, and the second epitaxial semiconductor layers include a second single crystalline semiconductor material that is different from the first single crystalline semiconductor material. A backside contact opening is formed through the stack, and backside cavities are formed by removing the first epitaxial semiconductor layers selective to the second epitaxial semiconductor layers. A stack of alternating layers including insulating layers and electrically conductive layers is formed. Each insulating layer contains a dielectric material portion deposited within a respective backside cavity. Each ...

Three dimensional NAND string memory devices with voids enclosed between control gate electrodes

A method of making a monolithic three dimensional NAND string includes forming a stack of alternating first and second material layers over a substrate, etching the stack to form a front side opening, partially removing the second material layers through the front side opening to form front side recesses, forming a first blocking dielectric in the front side recesses, forming charge storage regions over the first blocking dielectric in the front side recesses, forming a tunnel dielectric layer and a semiconductor channel over the charge storage regions in the front side opening, etching the stack to form a back side opening, removing the second material layers through the back side opening to form back side recesses using the first blocking dielectric as an etch stop, forming a second blocking dielectric in the back side recesses, and forming control gates over the second blocking dielectric in the back side recesses.

Semiconductor device including fractured semiconductor dies

A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.

THREE DIMENSIONAL NAND DEVICE WITH CHANNEL CONTACTING CONDUCTIVE SOURCE LINE AND METHOD OF MAKING THEREOF

A NAND memory cell region of a NAND device includes a conductive source line that extends substantially parallel to a major surface of a substrate, a first semiconductor channel that extends substantially perpendicular to a major surface of the substrate, and a second semiconductor channel that extends substantially perpendicular to the major surface of the substrate. At least one of a bottom portion and a side portion of the first semiconductor channel contacts the conductive source line and at least one of a bottom portion and a side portion of the second semiconductor channel contacts the conductive source line. 2. A method of making a semiconductor device , comprising:forming a conductive source line that extends substantially parallel to a major surface of a substrate;forming a stack of alternating layers of a first material and a second material over the conductive source line;etching the stack to form a plurality of memory openings in the stack to expose the conductive source line, wherein the plurality of memory openings extend substantially perpendicular to the major surface of the substrate;forming a plurality of charge storage regions;forming a tunnel dielectric over the charge storage regions; andforming a plurality of semiconductor channels over the tunnel dielectric in the respective plurality of memory openings in contact with the conductive source line.3. The method of claim 2 , wherein the tunnel dielectric and the plurality of charge storage regions are formed in the plurality of memory openings.5. The method of claim 4 , further comprising:forming an insulating layer over the first semiconductor layer and second semiconductor layer in the plurality of memory opening;recessing a top portion of the semiconductor channel and the insulating layer from an upper part of the plurality of memory openings; andforming a plurality of drain regions of the second conductivity type in the upper part of the plurality of memory openings above the recessed ...

Memory controller for resolving string to string shorts

A memory controller includes, in one embodiment, a memory interface and a controller circuit. The memory interface is configured to interface with a memory interface configured to interface with a memory having a plurality of memory blocks. Each memory block has a plurality of strings. The controller circuit is configured to perform a string defect leakage check on one of the memory blocks during a first programming operation of the one memory block, determine whether the one memory block has one or more string to string shorts based on the string defect leakage check, and resolve the string to string shorts in response to determining that the one of the memory blocks has the string to string shorts.

Three-dimensional memory device with leakage reducing support pillar structures and method of making thereof

Memory openings and support openings can be formed through an alternating stack of insulating layers and sacrificial material layers. A set of dielectric layers and at least one semiconductor material layer can be sequentially deposited in each of the memory openings and the support openings. The at least one semiconductor material layer is removed from inside the support openings, while the at least one semiconductor material layer is not removed from inside the memory openings. Memory stack structures and support pillar structures are formed in the memory openings and the support openings, respectively. The sacrificial material layers are replaced with electrically conductive layers. Removal of the at least one semiconductor material layer from the support pillar structures reduces or eliminates leakage current through the support pillar structures.

Air Isolation In High Density Non-Volatile Memory

Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Air gaps are formed at least partially in isolation regions between active areas of the substrate. The air gaps may further extend above the substrate surface between adjacent layer stack columns. A sacrificial material is formed at least partially in the isolation regions, followed by forming a dielectric liner. The sacrificial material is removed to define air gaps prior to forming the control gate layer and then etching it and the layer stack columns to form individual control gates and columns of non-volatile storage elements. 1. A method performed as part of fabricating non-volatile storage , comprising:forming a plurality of layer stack columns overlying a plurality of active areas of a substrate, each active area having two vertical sidewalls and being separated from an adjacent active area by a plurality of isolation regions in the substrate;partially filling the isolation regions with a first insulating material;forming a sacrificial material over the first insulating material in each isolation region, the sacrificial material extending above a level of a surface of the substrate;forming a dielectric liner vertically along the vertical sidewalls of each layer stack column; andremoving the sacrificial material after forming the dielectric liner to define a plurality of bit line air gaps extending vertically from an upper surface of the first insulating material to at least the level of the surface of the substrate.2. A method according to claim 1 , wherein a plurality of openings separate the plurality of layer stack columns in a row direction claim 1 , each layer stack column includes a strip of charge storage material claim 1 , the method further comprising:filling the plurality of openings with a second insulating material after removing the sacrificial material; andrecessing the second insulating material and the dielectric liner below a level of an upper ...

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING ALUMINUM-SILICON WORD LINES AND METHODS OF MANUFACTURING THE SAME

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The electrically conductive layers include aluminum and silicon and provide low resistance electrically conductive paths as word lines of the three-dimensional memory device. The aluminum-based electrically conductive layers can provide low resistivity, low mechanical stress, and thermal stability for use as high performance word lines. 1. A three-dimensional memory device comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate; andmemory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film, and extends through each of the electrically conductive layers and is laterally surrounded by each of the electrically conductive layers,wherein each of the electrically conductive layers comprises a respective conductive fill material structure including an aluminum-containing portion surrounded on at least three sides by a silicon-containing portion.2. The three-dimensional memory device of claim 1 , wherein at least 85% of all atoms within the aluminum-containing portions comprise aluminum atoms.3. The three-dimensional memory device of claim 1 , wherein at least 95% of all atoms within the silicon-containing portions comprise silicon atoms.4. The three-dimensional memory device of claim 1 , wherein each of electrically conductive layers further comprises a metallic barrier layer embedding the conductive fill material structure.5. The three-dimensional memory device of claim 4 , wherein the metallic barrier ...

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING ALUMINUM-SILICON WORD LINES AND METHODS OF MANUFACTURING THE SAME

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The electrically conductive layers include aluminum and silicon and provide low resistance electrically conductive paths as word lines of the three-dimensional memory device. The aluminum-based electrically conductive layers can provide low resistivity, low mechanical stress, and thermal stability for use as high performance word lines. 1. A three-dimensional memory device comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate; andmemory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film, and extends through each of the electrically conductive layers and is laterally surrounded by each of the electrically conductive layers,wherein each of the electrically conductive layers includes a respective metallic alloy material portion including aluminum and silicon, wherein at least 40% of all atoms within the metallic alloy material portion are aluminum atoms and at least 1% of all atoms within the metallic alloy material portions are silicon atoms.2. The three-dimensional memory device of claim 1 , wherein each of electrically conductive layers comprises a metallic barrier layer embedding a respective metallic alloy material portion and providing spatial separation of the metallic alloy material portion from the insulating layers and from the memory stack structures.3. The three-dimensional memory device of claim 2 , further comprising a backside blocking dielectric layer located between each neighboring ...

Method Of Making A Three-Dimensional Memory Array With Etch Stop

A method of making a semiconductor device including forming a sacrificial feature over a substrate, forming a plurality of etch through regions having an etch through material and an etch stop region having an etch stop material over the sacrificial feature, forming a stack of alternating layers of a first material and a second material over the plurality of the etch through regions and the plurality of the etch stop regions, etching the stack to form a plurality of openings through the stack and through the etch through regions to expose the sacrificial feature, such that the etch through material is etched preferentially compared to the first and the second materials of the stack, removing the sacrificial feature through the plurality of openings and etching the stack to form a slit trench up to or only partially through the etch stop region, such that the first and the second materials of the stack are etched preferentially compared to the etch stop material. 1. A method of making a semiconductor device , comprising:forming a sacrificial feature over a substrate;forming a plurality of etch through regions comprising an etch through material and an etch stop region comprising an etch stop material over the sacrificial feature;forming a stack of alternating layers of a first material and a second material over the plurality of the etch through regions and the plurality of the etch stop regions;etching the stack to form a plurality of openings through the stack and through the etch through regions to expose the sacrificial feature, such that the etch through material is etched preferentially compared to the first and the second materials of the stack;removing the sacrificial feature through the plurality of openings; andetching the stack to form a slit trench up to or only partially through the etch stop region, such that the first and the second materials of the stack are etched preferentially compared to the etch stop material.2. The method of claim 1 , further ...

Bias To Detect And Prevent Short Circuits In Three-Dimensional Memory Device

In a three-dimensional stacked non-volatile memory device, a short circuit in a select gate layer is detected and prevented. A short circuit may occur when charges which are accumulated in select gate lines due to plasma etching, discharge through a remaining portion of the select gate layer in a short circuit path when the select gate lines are driven. To detect a short circuit, during a testing phase, an increasing bias is applied is applied to the remaining portion while a current is measured. An increase in the current above a threshold indicates that the bias has exceed a breakdown voltage of a short circuit path. A value of the bias at this time is recorded as an optimal bias. During subsequent operations involving select gate transistors or memory cells, such as programming, erasing or reading, the optimal bias is applied when the select gate lines are driven to prevent a current flow through the short circuit. 1. A method for controlling a memory device , comprising:applying a voltage to a remaining portion of a select gate layer in a stacked three-dimensional memory structure, the stacked three-dimensional memory structure comprising alternating conductive layers and dielectric layers, the select gate layer is one of the conductive layers and comprises parallel select gate lines, the remaining portion of the select gate layer extends transversely to the parallel select gate lines and is separated from the parallel select gate lines by an end trench at one end the of parallel select gate lines, the parallel select gate lines are separated from one another by side trenches, the end trench is connected to the side trenches, an oxide is provided in the end trench and an oxide is provided in the side trenches;detecting a short circuit path in the oxide in the end trench during the applying the voltage;determining a voltage level for counteracting the short circuit path; andbiasing the remaining portion of the select gate layer during an operation in the stacked ...

THREE-DIMENSIONAL MEMORY DEVICE HAVING ENHANCED CONTACT BETWEEN POLYCRYSTALLINE CHANNEL AND EPITAXIAL PEDESTAL STRUCTURE AND METHOD OF MAKING THE SAME

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. An amorphous semiconductor material portion is formed at a bottom region of the memory opening. A memory film is formed in the memory opening. The memory film includes an opening at a bottom portion thereof, and a surface of the amorphous semiconductor material portion is physically exposed at a bottom of the opening in the memory film. An amorphous semiconductor channel material layer is formed on the exposed surface of the amorphous semiconductor material portion and over the memory film. A vertical semiconductor channel is formed by annealing the amorphous semiconductor material portion and the amorphous semiconductor channel material layer. The vertical semiconductor channel and contacts an entire top surface of an underlying semiconductor material portion. 1. A three-dimensional memory device , comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;memory openings vertically extending through the alternating stack; andmemory opening fill structures located within a respective one of the memory openings, wherein each of the memory opening fill structures comprises:a memory film contacting a sidewall of a respective memory opening and including an annular opening at a bottom portion thereof;a vertical semiconductor channel including a polycrystalline cylindrical portion contacting an inner sidewall of a vertically-extending portion of the memory film, a polycrystalline neck portion extending through the annular opening in the annular bottom portion of the memory film, and a polycrystalline base portion contacting an annular bottom surface of the annular bottom portion of the memory film; andan epitaxial pedestal structure including a single crystalline semiconductor material and contacting the polycrystalline base portion and contacting a sidewall ...

THREE-DIMENSIONAL MEMORY DEVICE HAVING ENHANCED CONTACT BETWEEN POLYCRYSTALLINE CHANNEL AND EPITAXIAL PEDESTAL STRUCTURE AND METHOD OF MAKING THE SAME

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. An amorphous semiconductor material portion is formed at a bottom region of the memory opening. A memory film is formed in the memory opening. The memory film includes an opening at a bottom portion thereof, and a surface of the amorphous semiconductor material portion is physically exposed at a bottom of the opening in the memory film. An amorphous semiconductor channel material layer is formed on the exposed surface of the amorphous semiconductor material portion and over the memory film. A vertical semiconductor channel is formed by annealing the amorphous semiconductor material portion and the amorphous semiconductor channel material layer. The vertical semiconductor channel and contacts an entire top surface of an underlying semiconductor material portion. 1. A three-dimensional memory device , comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;memory openings vertically extending through the alternating stack; andmemory opening fill structures located within a respective one of the memory openings, wherein each of the memory opening fill structures comprises:a memory film contacting a sidewall of a respective memory opening and including an opening at a bottom portion thereof;an epitaxial pedestal structure comprising a single crystalline semiconductor material and including a cylindrical portion located underneath a bottom surface of the memory film and a protrusion portion having a tubular configuration and extending through the opening in the memory film;a vertical semiconductor channel contacting an inner sidewall of the memory film and overlying and contacting the protrusion portion of the epitaxial pedestal structure; anda dielectric core having a cylindrical shape and contacting an inner sidewall of the vertical semiconductor channel ...

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING A VERTICAL SEMICONDUCTOR CHANNEL CONTAINING A CONNECTION STRAP AND METHOD OF MAKING THE SAME

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. A memory film is formed in the memory opening. The memory film includes an opening at a bottom portion. A connection strap is formed by performing a selective semiconductor deposition process that grows a strap semiconductor material from a physically exposed surface of an underlying semiconductor material portion through the opening. A vertical semiconductor channel is formed on an inner sidewall of the memory film by non-selectively depositing a semiconductor channel material. The connection strap provides an electrical connection between the underlying semiconductor material portion and the vertical semiconductor channel through the opening in the memory film. The sacrificial material layers are then replaced with electrically conductive layers. 1. A three-dimensional memory device , comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;memory openings vertically extending through the alternating stack; andmemory opening fill structures located within a respective one of the memory openings, wherein each of the memory opening fill structures comprises:a memory film contacting a sidewall of a respective memory opening and including an opening at a bottom portion thereof;a vertical semiconductor channel contacting an inner sidewall of the memory film and overlying the opening in the memory film;a dielectric core contacting an inner sidewall of the vertical semiconductor channel; anda connection strap comprising a semiconductor material, extending through the opening in the memory film, and contacting a bottom surface of the vertical semiconductor channel and a top surface of a semiconductor material that underlies the respective memory opening,wherein:the connection strap comprises a single crystalline strap semiconductor material;the vertical ...

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING A SILICON NITRIDE RING IN AN OPENING IN A MEMORY FILM AND METHOD OF MAKING THE SAME

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. A memory film including a silicon nitride layer and a tunneling dielectric layer is formed in the memory opening, and an opening is formed through the memory film. A chemical oxide layer is formed on a physically exposed surface of an underlying semiconductor material portion. A silicon nitride ring can be formed by selectively growing a silicon nitride material from an annular silicon nitride layer portion of the silicon nitride layer while suppressing deposition of the silicon nitride material on the tunneling dielectric layer and on the chemical oxide layer. A vertical semiconductor channel can be formed by depositing a continuous semiconductor material layer on the underlying semiconductor material portion and the tunneling dielectric layer and on the silicon nitride ring. 1. A three-dimensional memory device , comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;memory openings vertically extending through the alternating stack; andmemory opening fill structures located within a respective one of the memory openings, wherein each of the memory opening fill structures comprises:a memory film contacting a sidewall of a respective memory opening, comprising a layer stack including at least a tunneling dielectric layer and a silicon nitride layer, and including an opening at a bottom portion thereof;a silicon nitride ring contacting a sidewall of the opening in the memory film; anda vertical semiconductor channel contacting an inner sidewall of a vertically-extending portion of the memory film and extending through the silicon nitride ring and contacting a semiconductor material portion that underlies the memory film and the silicon nitride ring,wherein the silicon nitride ring vertically extends from a top surface of the semiconductor material ...

MULTI-CHARGE REGION MEMORY CELLS FOR A VERTICAL NAND DEVICE

A memory cell can be formed with a pair of charge storage regions. The pair of charge storage regions can be two portions of a charge storage region that are located at the same level and are positioned adjacent to two different control gate electrodes. Alternately, the pair of charge storage regions can be two disjoined structures located on opposite sides of a portion of a semiconductor channel. Yet alternately, the pair of charge storage regions can be two disjoined structures located at the same level, and on two laterally split semiconductor channel. The memory cell can be employed to store two bits of information within the pair of charge storage regions located at the same level within a vertical memory string that employs a single memory opening. 1. A memory device , comprising:a substrate having a major surface;a first plurality of memory cells arranged in a first string extending in a first direction substantially perpendicular to the major surface of the substrate in a plurality of device levels, wherein each of the first plurality of memory cells is positioned in a respective one of the plurality of device levels above the substrate;a first select gate electrode located between the major surface of the substrate and the first plurality of memory cells; anda second select gate electrode located above the first plurality of memory cells; a portion of a first control gate electrode extending in a second direction substantially parallel to the major surface; and', 'a portion of a second control gate electrode extending in the second direction, located at a same level as the respective first control gate electrode, and spaced apart from the respective first control gate electrode in a third direction substantially parallel to the major surface and transverse to the second direction; and, 'wherein each memory cell in the first string further compriseswherein for each memory cell in the first string, the respective first control gate electrode is electrically ...

METHOD OF INTEGRATING SELECT GATE SOURCE AND MEMORY HOLE FOR THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE

A method of fabricating a semiconductor device, such as a three-dimensional NAND memory string, includes forming a carbon etch stop layer having a first width over a major surface of a substrate, forming a stack of alternating material layers over the etch stop layer, etching the stack to the etch stop layer to form a memory opening having a second width at a bottom of the memory opening that is smaller than the width of the etch stop layer, removing the etch stop layer to provide a void area having a larger width than the second width of the memory opening, forming a memory film over a sidewall of the memory opening and in the void area, and forming a semiconductor channel in the memory opening such that the memory film is located between the semiconductor channel and the sidewall of the memory opening. 1. A method of fabricating a memory device , comprising:forming a carbon etch stop layer having a first width dimension over a major surface of a substrate;forming a stack of alternating layers of a first material and a second material different from the first material over the carbon etch stop layer;etching the stack through a mask to the carbon etch stop layer to form a memory opening having a second width dimension at a bottom of the memory opening proximate to the carbon etch stop layer that is smaller than the first width dimension of the carbon etch stop layer;removing the carbon etch stop layer to provide a void area between the bottom of the memory opening and a top surface of a protrusion comprising a semiconductor material, the void area having a larger width dimension than the second width dimension of the memory opening;forming at least a portion of a memory film over a sidewall of the memory opening and in the void area; andforming a semiconductor channel in the memory opening such that the memory film is located between the semiconductor channel and the sidewall of the memory opening.2. The method of claim 1 , further comprising:forming a first gate ...

THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE

A memory device includes a stack of material layers with a plurality of NAND strings extending through the stack, and a trench through the stack with a pair of sidewalls defining a width of the trench that is substantially constant or decreases from the top of the trench to a first depth and increases between a first depth and a second depth that is closer to the bottom of the trench than the first depth and the trench has an insulating material covering at least the trench sidewalls. Further embodiments include a memory device including a stack of material layers and an active memory cell region defined between a pair of trenches, and within the active region the stack comprises alternating layers of a first material and a second material, and outside of the active region the stack comprises alternating layers of the first material and a third material. 1. A memory device , comprising:a stack of alternating layers of a first material and a second material different from the first material over a substrate, wherein the layers of the second material form a plurality of conductive control gate electrodes; a semiconductor channel which contains at least a first portion which extends substantially perpendicular to a major surface of the substrate; and', 'at least one memory film located between the semiconductor channel and the plurality of conductive control gate electrodes; and, 'a plurality of NAND memory strings extending through the stack, wherein each NAND memory string comprisesa trench formed through the stack and having a pair of sidewalls defining a width of the trench, the trench having a depth dimension along a direction between a top of the trench and a bottom of the trench proximate to the substrate, and a width of the trench is substantially constant or decreases from the top of the trench to a first depth and increases between a first depth and a second depth, wherein the second depth is closer to the bottom of the trench than the first depth, the trench ...

SINGLE-SEMICONDUCTOR-LAYER CHANNEL IN A MEMORY OPENING FOR A THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE

A memory film layer is formed in a memory opening through an alternating stack of first material layers and second material layers. A sacrificial material layer is deposited on the memory film layer. Horizontal portions of the sacrificial material layer and the memory film layer at the bottom of the memory opening is removed by an anisotropic etch to expose a substrate underlying the memory opening, while vertical portions of the sacrificial material layer protect vertical portions of the memory film layer. After removal of the sacrificial material layer selective to the memory film, a doped semiconductor material layer can be formed directly on the exposed material in the memory opening and on the memory film as a single material layer to form a semiconductor channel of a memory device. 1. A method of fabricating a memory device , comprising:forming a stack of alternating layers of a first material and a second material different from the first material over a substrate including a semiconductor material;etching a portion of the stack to form a memory opening extending from a top surface of the stack to a top surface of the substrate;forming a memory film layer within the memory opening;forming a sacrificial material layer on the memory film layer;etching horizontal portions of the sacrificial material layer and the memory film layer to physically expose a portion of the top surface of the substrate underneath the memory opening, while leaving a vertical portion of the sacrificial material layer remaining on a vertical portion of the memory film layer;removing the sacrificial material layer selective to a remaining portion of the memory film layer; anddepositing a single semiconductor material layer on a sidewall of the remaining portion of the memory film layer to form at least an upper portion of a semiconductor channel.2. The method of claim 1 , wherein the memory film layer comprises a stack containing claim 1 , from one side to another claim 1 , a blocking ...

HIGH ASPECT RATIO MEMORY HOLE CHANNEL CONTACT FORMATION

A method of fabricating a semiconductor device, such as a three-dimensional monolithic NAND memory string, includes etching a select gate electrode over a first gate insulating layer over a substrate to form an opening, forming a second gate insulating layer over the sidewalls of the opening, forming a sacrificial spacer layer over the second gate insulating layer on the sidewalls of the opening, and etching the first gate insulating layer over the bottom surface of the opening to expose the substrate, removing the sacrificial spacer layer to expose the second gate insulating layer over the sidewalls of the opening, and forming a protrusion comprising a semiconductor material within the opening and contacting the substrate, wherein the second gate insulating layer is located between the select gate electrode and first and second side surfaces of the protrusion. 1. A method of fabricating a memory device , comprising:forming a first gate insulating layer over a major surface of a semiconductor substrate;forming a select gate electrode over the first gate insulating layer;etching the select gate electrode to the first gate insulating layer through a mask to form an opening having sidewalls and a bottom surface, wherein the select gate electrode forms at least a portion of the sidewalls and the first gate insulating layer forms the bottom surface;forming a second gate insulating layer on the sidewalls of the opening;forming a sacrificial spacer layer over the second gate insulating layer on at least the sidewalls of the opening;etching the first gate insulating layer over the bottom surface of the opening to expose the semiconductor substrate while the sacrificial spacer layer protects the second gate insulating layer on the sidewalls of the opening;removing the sacrificial spacer layer to expose the second gate insulating layer over the sidewalls of the opening; andforming a protrusion comprising a semiconductor material within the opening and contacting the ...

High stack 3d memory and method of making

A method of making a monolithic three dimensional NAND device includes forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming a mask layer over the stack and patterning the mask layer to form at least on opening in the mask layer to expose a top layer of the stack. The method also includes forming a metal block in the at least one opening in the mask layer, etching the stack by metal induced localized etch using the metal block in the at least one opening in the mask layer to form at least one opening in the stack and forming at least one layer of the NAND device in the at least one opening.

VERTICAL MEMORY DEVICE WITH BIT LINE AIR GAP

A structure includes a three-dimensional semiconductor device including a plurality of unit device structures located over a substrate. Each of the unit device structures includes a semiconductor channel including at least a portion extending vertically along a direction perpendicular to a top surface of the substrate, and a drain region contacting a top end of the semiconductor channel. The structure also includes a combination of a plurality of contact pillars and a contiguous volume that laterally surrounds the plurality of contact pillars. The plurality of contact pillars is in contact with the drain regions, and the contiguous volume has a dielectric constant less than 3.9. 1. A method of fabricating a structure , comprising: a semiconductor channel having at least a portion extending vertically along a direction perpendicular to a top surface of the substrate; and', 'a drain region contacting a top end of the semiconductor channel; and, 'forming a three-dimensional semiconductor device including a plurality of unit device structures over a substrate, each of the unit device structures includingforming a combination of a plurality of contact pillars and a contiguous volume that laterally surrounds the plurality of contact pillars,wherein each of the plurality of contact pillars is contact with, and is formed above, a top surface of a respective drain region; andthe contiguous volume has a dielectric constant less than 3.9 and is formed above a horizontal plane including the top surfaces of the drain regions.2. The method of claim 1 , wherein the plurality of contact pillars is formed by:forming a sacrificial material layer over the at least one dielectric material layer;forming a plurality of pillar cavities through the sacrificial material layer to expose top surfaces of the drain regions; andforming the plurality of contact pillars by filling the plurality of pillar cavities with a conductive material.3. The method of claim 2 , further comprising:removing the ...

SINGLE-SEMICONDUCTOR-LAYER CHANNEL IN A MEMORY OPENING FOR A THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE

A memory film layer is formed in a memory opening through an alternating stack of first material layers and second material layers. A sacrificial material layer is deposited on the memory film layer. Horizontal portions of the sacrificial material layer and the memory film layer at the bottom of the memory opening is removed by an anisotropic etch to expose a substrate underlying the memory opening, while vertical portions of the sacrificial material layer protect vertical portions of the memory film layer. After removal of the sacrificial material layer selective to the memory film, a doped semiconductor material layer can be formed directly on the exposed material in the memory opening and on the memory film as a single material layer to form a semiconductor channel of a memory device. 1. A three-dimensional memory device , comprising:a substrate having a major surface;an alternating stack of insulating material layers and control gate electrodes located over the substrate, the alternating stack having a memory opening extending through the alternating stack in a direction substantially perpendicular to the major surface;a memory film located at a peripheral region of the memory opening; anda semiconductor channel including an upper portion extending substantially perpendicular to the major surface and contacting an inner sidewall of the memory film and a lower portion contacting a single crystalline semiconductor material portion located within or on the substrate; an outer sidewall of the upper portion of the semiconductor channel is laterally offset with respect to an outer sidewall of the lower portion of the semiconductor channel; and', 'the semiconductor channel does not include a substantially contiguous interface composed of grain boundaries, not contacting the memory film, and vertically extending through the semiconductor channel between a plurality of control gate electrodes., 'wherein2. The three-dimensional memory device of claim 1 , wherein the ...

Three dimensional nand string memory devices and methods of fabrication thereof

Monolithic three-dimensional NAND memory strings and methods of fabricating a monolithic three-dimensional NAND memory string include forming single crystal or large grain polycrystalline semiconductor material charge storage regions by a metal induced crystallization process. In another embodiment, a plurality of front side recesses are formed having a concave-shaped surface and a blocking dielectric and charge storage regions are formed within the front side recesses and over the concave-shaped surface. In another embodiment, layers of oxide material exposed in a front side opening of a material layer stack are surface nitrided and etched to provide convexly-rounded corner portions, and a blocking dielectric is formed over the convexly-rounded corner portions.

THREE-DIMENSIONAL MEMORY STRUCTURE HAVING SELF-ALIGNED DRAIN REGIONS AND METHODS OF MAKING THEREOF

A memory stack structure can be formed through a stack of an alternating plurality of first material layers and second material layers and through an overlying temporary material layer having a different composition than the first and second material layers. The memory stack structure can include a memory film and a semiconductor channel layer. The overlying temporary material layer is removed selective to the stack to form a lateral recess. Portions of the memory film are removed around the lateral recess, and dopants are laterally introduced into an upper portion of the semiconductor channel to form a self-aligned drain region. 1. A method of manufacturing a three-dimensional memory structure , comprising:forming a stack of alternating layers comprising first material layers and second material layers over a substrate;forming a temporary material layer over the stack; wherein the temporary material layer has a different composition than the first material layers and second material layers;forming a memory opening through the temporary material layer and the stack;forming a memory film and a semiconductor channel in the memory opening;forming a first backside recess by removing the temporary material layer and a portion of the memory film that adjoins the temporary material layer, wherein a portion of a sidewall of the semiconductor channel is physically exposed to the first backside recess; andintroducing electrical dopants through the physically exposed portion of the sidewall of the semiconductor channel and into a portion of the semiconductor channel, which is converted into a drain region.2. The method of claim 1 , further comprising:forming a trench through the temporary material layer and the stack; andremoving a material of the temporary material layer selective to materials of the first and second material layers to form second backside recesses.3. The method of claim 2 , further comprising simultaneously filling the first and second backside recesses with ...

THREE-DIMENSIONAL MEMORY STRUCTURE HAVING SELF-ALIGNED DRAIN REGIONS AND METHODS OF MAKING THEREOF

A memory stack structure can be formed through a stack of an alternating plurality of first material layers and second material layers and through an overlying temporary material layer having a different composition than the first and second material layers. The memory stack structure can include a memory film and a semiconductor channel layer. The overlying temporary material layer is removed selective to the stack to form a lateral recess. Portions of the memory film are removed around the lateral recess, and dopants are laterally introduced into an upper portion of the semiconductor channel to form a self-aligned drain region. 1. A monolithic three-dimensional memory structure , comprising:a stack including an alternating plurality of insulator layers and electrically conductive layers located over a substrate;a memory opening extending through the stack;a memory film and a semiconductor channel located within the memory opening, wherein the semiconductor channel includes a vertical portion that extends vertically through a subset of layers within the stack;a drain region having a same horizontal cross-sectional area as the vertical portion of the semiconductor channel, wherein the drain region includes an electrical dopant of a first conductivity type.2. The monolithic three-dimensional memory structure of claim 1 , wherein the drain region includes a same semiconductor material as the vertical portion of the semiconductor channel.3. The monolithic three-dimensional memory structure of claim 1 , further comprising:a first dielectric liner portion in contact with the drain region; anda first conductive electrode embedded in the first dielectric liner portion.4. The monolithic three-dimensional memory structure of claim 3 , further comprising a second dielectric liner portion laterally spaced from the semiconductor channel by the memory film.5. The monolithic three-dimensional memory structure of claim 4 , further comprising a second conductive electrode embedded ...

THREE-DIMENSIONAL MEMORY DEVICE WITH LEAKAGE REDUCING SUPPORT PILLAR STRUCTURES AND METHOD OF MAKING THEREOF

Memory openings and support openings can be formed through an alternating stack of insulating layers and sacrificial material layers. A set of dielectric layers and at least one semiconductor material layer can be sequentially deposited in each of the memory openings and the support openings. The at least one semiconductor material layer is removed from inside the support openings, while the at least one semiconductor material layer is not removed from inside the memory openings. Memory stack structures and support pillar structures are formed in the memory openings and the support openings, respectively. The sacrificial material layers are replaced with electrically conductive layers. Removal of the at least one semiconductor material layer from the support pillar structures reduces or eliminates leakage current through the support pillar structures. 1. A three-dimensional memory device comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film, a vertical semiconductor channel contacting an inner sidewall of the memory film, and a dielectric core contacting an inner sidewall of the vertical semiconductor channel; andsupport pillar structures extending through the alternating stack and laterally spaced from the memory stack structures, wherein each of the support pillar structures comprises a dielectric layer stack and a dielectric fill material portion that contacts an inner sidewall of the dielectric layer stack; wherein:an epitaxial channel portion is disposed between each vertical semiconductor channel and a semiconductor material portion of the substrate; anda tubular dielectric spacer laterally surrounds, and contacts, a respective epitaxial channel portion; and one of: 'a top surface of the epitaxial channel portion extends farther away from the semiconductor material ...

ULTRATHIN SEMICONDUCTOR CHANNEL THREE-DIMENSIONAL MEMORY DEVICES

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack to the substrate. After formation of memory film layers, a sacrificial cover material layer can be employed to protect the tunneling dielectric layer during formation of a bottom opening in the memory film layers. An amorphous semiconductor material layer can be deposited and optionally annealed in an ambient including argon and/or deuterium to form a semiconductor channel layer having a thickness less than 5 nm and surface roughness less than 10% of the thickness. Alternately or additionally, at least one interfacial layer can be employed on either side of the amorphous semiconductor material layer to reduce surface roughness of the semiconductor channel. The ultrathin channel can have enhanced mobility due to quantum confinement effects. 2. The three-dimensional memory device of claim 1 , wherein an atomic concentration of argon in the semiconductor channel is in a range from 1.0×10/cmto 5.0×10/cm.3. The three-dimensional memory device of claim 1 , wherein the semiconductor channel is further doped with deuterium atoms.4. The three-dimensional memory device of claim 3 , wherein an atomic concentration of deuterium atoms in the semiconductor channel is in a range from 1.0×10/cmto 5.0×10/cm.5. The three-dimensional memory device of claim 1 , wherein the semiconductor channel comprises at least one of:(a) the semiconductor channel has a thickness not greater than 5.0 nm and a first sidewall having a surface roughness not greater than 10% of the thickness of the semiconductor channel; or(b) the semiconductor channel has the surface roughness less than 0.5 nm in root mean square thickness.6. The three-dimensional memory device of claim 5 , wherein:a second sidewall of the semiconductor channel has a surface roughness not greater than 10% of the thickness of the semiconductor channel;one of the first sidewall and ...

METHODS FOR MANUFACTURING ULTRATHIN SEMICONDUCTOR CHANNEL THREE-DIMENSIONAL MEMORY DEVICES

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack to the substrate. After formation of memory film layers, a sacrificial cover material layer can be employed to protect the tunneling dielectric layer during formation of a bottom opening in the memory film layers. An amorphous semiconductor material layer can be deposited and optionally annealed in an ambient including argon and/or deuterium to form a semiconductor channel layer having a thickness less than 5 nm and surface roughness less than 10% of the thickness. Alternately or additionally, at least one interfacial layer can be employed on either side of the amorphous semiconductor material layer to reduce surface roughness of the semiconductor channel. The ultrathin channel can have enhanced mobility due to quantum confinement effects. 1. A method of forming a three-dimensional memory device comprising:forming an alternating stack of insulating layers and spacer material layers over a substrate;forming memory openings extending through the alternating stack;forming a memory film and an amorphous semiconductor material layer in the memory openings; andconverting a predominant portion of the amorphous semiconductor material layer into an argon-doped semiconductor material layer.2. The method of claim 1 , wherein the argon-doped semiconductor material layer includes argon at an atomic concentration in a range from 1.0×10/cmto 5.0×10/cm.3. The method of claim 2 , wherein the argon-doped semiconductor material layer is formed by performing an anneal process in an ambient gas composition that includes argon at an atomic concentration greater than 10%.4. The method of claim 3 , wherein the atomic concentration of argon in the ambient gas composition is greater than 50%.5. The method of claim 3 , wherein the ambient gas composition comprises deuterium gas at an atomic concentration greater than 10%.6. The method ...

DEUTERIUM ANNEAL OF SEMICONDUCTOR CHANNELS IN A THREE-DIMENSIONAL MEMORY STRUCTURE

A monolithic three-dimensional memory structure includes a memory stack structure including a memory film and a semiconductor channel. Traps and/or defects within the semiconductor channel and/or at the semiconductor/dielectric material interface and/or inside dielectric materials can be passivated by an anneal in a deuterium-containing gas, which replaces hydrogen atoms within the semiconductor channel or passivate the dangling bonds/traps with deuterium atoms. The anneal may be performed immediately after formation of the semiconductor channel, before or after formation of a dielectric core or a drain region, after replacement of sacrificial material layers with conductive material layers, after dicing of a substrate into semiconductor chips, or at another suitable processing step. 1. A method of manufacturing a three-dimensional memory structure , comprising:forming a stack of alternating layers comprising first material layers and second material layers over a substrate;forming a memory opening through the stack to a top surface of the substrate;forming a memory film and a semiconductor channel material in the memory opening;replacing the first material layers with electrically conductive layers; andannealing the semiconductor channel material and the electrically conductive material layers in an anneal process that reduces a resistivity of a conductive material of the electrically conductive layers while incorporating deuterium atoms into the semiconductor channel material in an environment including a deuterium-containing gas.24.-. (canceled)5. The method of claim 1 , wherein the semiconductor channel material comprises a portion that vertically extends from the top surface of the substrate to a top surface of the stack.6. The method of claim 1 , wherein the memory film comprises a tunneling dielectric claim 1 , and the semiconductor channel material is formed by depositing a conformal semiconductor material layer on a sidewall of the tunneling dielectric.7. ...

THREE DIMENSIONAL NAND DEVICE CONTAINING FLUORINE DOPED LAYER AND METHOD OF MAKING THEREOF

A method of making a monolithic three dimensional NAND string comprising forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming an at least one front side opening in the stack and forming at least a portion of a memory film in the at least one front side opening. The method also includes forming a semiconductor channel in the at least one front side opening and doping at least one of the memory film and the semiconductor channel with fluorine in-situ during deposition or by annealing in a fluorine containing atmosphere. 1. A monolithic three dimensional NAND string , comprising:a semiconductor channel, at least one end part of the semiconductor channel extending substantially perpendicular to a major surface of a substrate;a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level, wherein the first control gate electrode is separated from the second control gate electrode by an insulating layer located between the first and second control gates;a blocking dielectric located adjacent the plurality of control gate electrodes;at least one charge storage region located adjacent the blocking dielectric; anda tunnel dielectric located between the at least one charge storage region and the semiconductor channel,wherein at least one of the semiconductor channel, blocking dielectric or tunnel dielectric is doped with fluorine.2. The monolithic three dimensional NAND string of claim 1 , wherein the semiconductor channel claim 1 , blocking dielectric and tunnel dielectric are each doped with fluorine.3. The monolithic three dimensional NAND string of claim 1 , ...

THREE-DIMENSIONAL MEMORY DEVICES HAVING A SHAPED EPITAXIAL CHANNEL PORTION AND METHOD OF MAKING THEREOF

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A dielectric collar structure can be formed prior to formation of an epitaxial channel portion, and can be employed to protect the epitaxial channel portion during replacement of the sacrificial material layers with electrically conductive layers. Exposure of the epitaxial channel portion to an etchant during removal of the sacrificial material layers is avoided through use of the dielectric collar structure. Additionally or alternatively, facets on the top surface of the epitaxial channel portion can be reduced or eliminated by forming the epitaxial channel portion to a height that exceeds a target height, and by recessing a top portion of the epitaxial channel portion. The recess etch can remove protruding portions of the epitaxial channel portion at a greater removal rate than a non-protruding portion. 19.-. (canceled)10. A method of manufacturing a device , comprising:forming an alternating stack comprising insulating layers and spacer material layers over a substrate;forming a memory opening through the alternating stack;forming an epitaxial channel portion on a semiconductor surface underneath the memory opening;removing an upper portion of the epitaxial channel portion, wherein a remaining portion of the epitaxial channel portion comprises a chamfer; andforming a memory stack structure on the remaining portion of the epitaxial channel portion, wherein:the chamfer is located in a peripheral portion of the epitaxial channel portion;the chamfer has an upper edge that adjoins a periphery of a horizontal top surface located in a center portion of the epitaxial channel portion and a lower edge that adjoins a sidewall of the memory opening;the chamfer comprises an inner periphery and an outer periphery;the inner periphery of the chamfer comprises the upper edge of the chamfer;the outer periphery of the chamfer comprises the lower edge of the chamfer; andremoval of ...

THREE DIMENSIONAL NAND DEVICE HAVING REDUCED WAFER BOWING AND METHOD OF MAKING THEREOF

A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate, and at least one trench extending substantially perpendicular to the major surface of the substrate. The trench is filled with at least a first trench material and a second trench material. The first trench material includes a material under a first magnitude of a first stress type, and the second trench material includes a material under no stress, a second stress type opposite the first stress type, or a second magnitude of the first stress type lower than the first magnitude of the first stress type to offset warpage of the substrate due to the stress imposed by at least one of the first trench material or the plurality of control gate electrodes on the substrate. 1. A monolithic three dimensional NAND memory device , comprising:a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate, wherein the plurality of control gate electrodes comprises at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level;an interlevel insulating layer located between the first control gate electrode and the second control gate electrode;a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to the major surface of the substrate, such that at least one first portion of each of the plurality of semiconductor channels is located in the first device level, and at least one second portion of each of the plurality of semiconductor channels is located in the second device level;at least one memory film located between each of the plurality of control gate electrodes and each respective semiconductor channel of the plurality ...

Contact For Vertical Memory With Dopant Diffusion Stopper And Associated Fabrication Method

A memory device and corresponding fabrication method prevent undesired diffusion of dopants from a silicon cap of a vertical NAND string to a channel film of the NAND string. Initially, a memory hole is provided in a stack of alternating control gate layers and dielectric layers. The memory hole is filled with annular films and a dielectric core filler. The dielectric core filler is etched back from a top of the memory hole to a topmost control gate layer, forming a void. A dopant stopper liner is deposited in the void before depositing n+ doped silicon which forms the silicon cap. The dopant stopper liner can be a conductive material such as metal or polysilicon doped with carbon. A conductive via is then formed above, and aligned with, the top of the silicon cap. A bit line may be formed over the conductive via. 1. A method for fabricating a contact in a memory device , comprising:forming a vertically-extending memory hole in a stack, the stack comprising alternating control gate layers and dielectric layers;providing a channel film in the vertically-extending memory hole, a central void in the vertically-extending memory hole is formed within the channel film;providing a dielectric core filler in the central void;forming a void in the vertically-extending memory hole, the forming the void comprises etching back the dielectric core filler to provide an etched back dielectric core filler;providing a dopant stopper liner in the void, the dopant stopper liner is conductive and extends upward from a top surface of the etched back dielectric core filler to a top of the stack;providing n+ doped silicon in the void, above the dopant stopper liner, the n+ doped silicon conforms to the dopant stopper liner; andproviding a conductive via which extends above the stack, the conductive via has a bottom surface which rests on a top surface of the n+ doped silicon.2. The method of claim 1 , wherein:the dielectric core filler is etched back to a height of a topmost control gate ...

PREVENTION OF LATENT BLOCK FAILS IN THREE-DIMENSIONAL NAND

Technology is disclosed for detecting latent defects in non-volatile storage systems. Prior to writing data, a stress voltage is applied to SGS transistors in a 3D memory structure. After applying the stress voltage, the Vt of the SGS transistors are tested to determine whether they meet a criterion. The criterion may be whether a Vt distribution of the SGS transistors falls within an allowed range. If the criterion is not met, then a sub-block mode may be enabled. In the sub-block mode, data is not written to memory cells in a sub-block that contains SGS transistors whose Vt does not meet the criterion. Hence, the possibility of data loss due to defective SGS transistors is avoided. However, in the sub-block mode, data is written to memory cells in a sub-block that does not contain SGS transistors whose Vt does not meet the criterion. Hence, data capacity is preserved. 1. An apparatus comprising: apply a first voltage to control gates of a group of the regular source side select transistors while applying a second voltage to the substrate, wherein the second voltage is different in magnitude from the first voltage;', 'determine whether threshold voltages of the group of the regular source side select transistors meet a criterion after the first voltage is applied to the control gates and the second voltage is applied to the substrate; and', 'determine that the group of the regular source side select transistors are ineligible to be used to control write operations in the three-dimensional memory structure if the threshold voltages of the group fails to meet the criterion., 'one or more control circuits configured to connect to a three-dimensional memory structure having memory holes, the memory holes comprising regular memory holes having NAND strings, each NAND string having a regular source side select transistor having a body in electrical contact with a substrate below the three-dimensional memory structure, the one or more control circuits configured to2. The ...

Fabricating 3D NAND Memory Having Monolithic Crystalline Silicon Vertical NAND Channel

Disclosed herein are techniques for fabricating 3D NAND memory devices having a mono-crystalline silicon semiconductor vertical NAND channel. Memory holes are formed in horizontal layers of material above a substrate. A vertically-oriented NAND string is formed in each of the memory holes. Forming the vertically-oriented NAND string channel comprises growing monolithic crystalline silicon upwards in the memory hole from the substrate through all of the plurality of horizontal layers of material. Vapor phase epitaxial growth may be used grow the monolithic crystalline silicon upwards from the bottom of the vertically-oriented NAND channel. Alternatively, a nanowire of monolithic crystalline silicon is synthesized in the memory hole from the substrate at the bottom of the vertically-oriented NAND channel upwards to the top of the vertically-oriented NAND channel. 1. A method for fabricating a three-dimensional (3D) non-volatile storage device , the method comprising:forming a plurality of horizontal layers of material above a substrate;forming memory holes that extend vertically through the plurality of horizontal layers of material to the substrate; forming material for the plurality of non-volatile storage elements for the NAND string in the given memory hole leaving a channel hole that extends vertically through the plurality of horizontal layers of material to the substrate, the non-volatile storage elements of the NAND string surround the channel hole; and', 'forming the vertically-oriented NAND string channel in the channel hole comprising growing monolithic crystalline silicon upwards from the substrate through all of the plurality of horizontal layers of material., 'forming a vertically-oriented NAND string in each of the memory holes, each vertically-oriented NAND string comprising a plurality of non-volatile storage elements and a vertically-oriented NAND string channel, forming an individual one of the NAND strings in a given memory hole including2. The ...

Method of making a vertical nand device using sequential etching of multilayer stacks

A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and at least partially filling the lower portion of the memory openings with a sacrificial material. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening.

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING ETCH STOP STRUCTURES AND METHODS OF MAKING THE SAME

A method of forming a semiconductor structure includes providing a dopant species selected from carbon, boron, nitrogen or oxygen into an upper portion of a semiconductor region to form a doped etch stop semiconductor material portion over a remaining semiconductor material portion, forming an overlying material portion over the etch stop semiconductor material portion, etching through the overlying material portion by an etch process that removes the overlying material portion selective to a material of the etch stop semiconductor material portion, and depositing at least one fill material over the etch stop semiconductor material portion. 1. A three-dimensional memory device , comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;a memory opening fill structure extending through the alternating stack and comprising a first pedestal channel portion, a first memory film and a first vertical semiconductor channel;a staircase region including stepped surfaces of the alternating stack; anda support pillar structure extending through a portion of the alternating stack in the staircase region and comprising a second semiconductor pedestal channel portion, a second memory film, and a second vertical semiconductor channel,wherein:the second semiconductor pedestal channel portion comprises a semiconductor etch stop pedestal segment containing a dopant species overlying a semiconductor remaining pedestal segment, andthe etch stop pedestal segment has an etch rate than is at least 5 times less in trimethyl-2 hydroxyethyl ammonium hydroxide (TMY) than the remaining pedestal segment.2. The three-dimensional memory device of claim 1 , wherein:the dopant species comprise carbon, boron, nitrogen or oxygen; andthe remaining pedestal segment is free of the dopant species or includes the dopant species at an atomic concentration that is less than 0.05 times an atomic concentration of the dopant species within the etch stop ...

MULTILEVEL MEMORY STACK STRUCTURE AND METHODS OF MANUFACTURING THE SAME

A first stack of alternating layers including first electrically conductive layers and first electrically insulating layers is formed with first stepped surfaces and a first dielectric material portion thereupon. Dielectric pillar structures including a dielectric metal oxide can be formed through the first stepped surfaces. Lower memory openings can be formed, and filled with a disposable material or a lower memory opening structure including a lower semiconductor channel and a doped semiconductor region. At least one dielectric material layer and a second stack of alternating layers including second electrically conductive layers and second electrically insulating layers can be sequentially formed. Upper memory openings can be formed through the second stack and the at least one dielectric material layer. A memory film and a semiconductor channel can be formed after removal of the disposable material, or an upper semiconductor channel can be formed on the doped semiconductor region. 1. A monolithic three-dimensional memory device comprising:a lower stack structure comprising a first stack of alternating layers including first electrically insulating layers and first electrically conductive layers and located over a substrate;at least one dielectric material layer overlying the lower stack structure;an upper stack structure comprising a second stack of alternating layers including second electrically insulating layers and second electrically conductive layers and located over the at least one dielectric material layer;a memory opening extending through the second stack, the at least one dielectric material layer, and the first stack;a memory film and at least one semiconductor channel located within the memory opening; andat least one via contact structure vertically extending through the upper stack structure, the at least one dielectric material layer, and a portion of the lower stack structure, and electrically shorted to at least one conductive structure ...

Program Disturb Improvements in Multi-Tier Memory Devices Including Improved Non-Data Conductive Gate Implementation

Techniques for reducing program disturb of memory cells which are formed in a NAND string extending in a lower tier and an upper tier of a stack, the lower tier comprising a first plurality of memory cells and the upper tier comprising a second plurality of memory cells, wherein each memory cell of the first and second pluralities of memory cells is connected to a respective word line. The NAND string includes a joint region formed of a dielectric material and disposed between the lower tier and the upper tier of the stack; a first non-data memory cell adjacent to and below the joint region; a second non-data memory cell adjacent to and above the joint region; and a conductive gate connected to the first non-data memory cell and the second non-data memory cell. 1. An apparatus , comprising:a NAND string extending along a lower tier and an upper tier of a stack, the lower tier comprising a first plurality of memory cells and the upper tier comprising a second plurality of memory cells, wherein each memory cell of the first and second pluralities of memory cells is connected to a respective word line;a joint region formed of a dielectric material and disposed between the lower tier and the upper tier of the stack;a first non-data memory cell adjacent to and below the joint region;a second non-data memory cell adjacent to and above the joint region; anda conductive gate extending through the joint region and connecting to a gate of the first non-data memory cell and a gate of the second non-data memory cell.2. The apparatus of claim 1 , wherein the conductive gate forms a joint word line in electrical contact with a gate of the first non-data memory cell and a gate of the second non-data memory cell.3. The apparatus of claim 1 , wherein:the first non-data memory cell is connected to a first dummy word line adjacent to and below the joint region;the second non-data memory cell is connected to a second dummy word line adjacent to and above the joint region; andthe ...

Metal Replacement Process For Low Resistance Source Contacts In 3D NAND

A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to memory holes at a bottom of a stack. The stack includes alternating control gate layers and dielectric layers on a substrate, and memory holes are etched through the stack. The process avoids the need to etch through films at the bottom of the memory hole. Instead, a path is formed from the bottom of the memory hole to the top of the stack. The path includes a horizontal portion using a voided trench in a substrate dielectric, and a passageway etched in the stack. The memory films, a channel material and a dielectric material are deposited throughout the interior surfaces of the void and the memory holes concurrently. The path is filled with metal to form a continuous, low resistance conductive path. 1. A method for fabricating a 3d stacked non-volatile memory device , comprising:forming a memory hole in a stack, the stack comprising alternating control gate layers and dielectric layers on a substrate dielectric;forming a void in the substrate dielectric, a bottom of the memory hole is connected to the void;forming a passageway in the stack between a top of the stack and the void;depositing a plurality of materials in the void and the memory hole, the plurality of materials comprise a programmable material, a channel material and a dielectric material;removing a portion of the dielectric material which is in the void, exposing a portion of the channel material which is in the void;doping the portion of the channel material which is in the void, the doping comprises introducing a dopant to the void via the passageway; anddepositing a metal in the void and the passageway, the metal extends to the bottom of the memory hole.2. The method of claim 1 , wherein:the removing the portion of the dielectric material in the void comprises introducing an etchant into the void via the passageway.3. The method of claim 1 , wherein:the forming the void in the substrate ...

Crystalline layer stack for forming conductive layers in a three-dimensional memory structure

A stack of alternating layers comprising first epitaxial semiconductor layers and second epitaxial semiconductor layers is formed over a single crystalline substrate. The first and second epitaxial semiconductor layers are in epitaxial alignment with a crystal structure of the single crystalline substrate. The first epitaxial semiconductor layers include a first single crystalline semiconductor material, and the second epitaxial semiconductor layers include a second single crystalline semiconductor material that is different from the first single crystalline semiconductor material. A backside contact opening is formed through the stack, and backside cavities are formed by removing the first epitaxial semiconductor layers selective to the second epitaxial semiconductor layers. A stack of alternating layers including insulating layers and electrically conductive layers is formed. Each insulating layer contains a dielectric material portion deposited within a respective backside cavity. Each electrically conductive layer contains a material from a portion of a respective second epitaxial semiconductor layer.

METHOD OF FORMING AN ACTIVE AREA WITH FLOATING GATE NEGATIVE OFFSET PROFILE IN FG NAND MEMORY

A stack can be patterned by a first etch process to form an opening defining sidewall surfaces of a patterned material stack. A masking layer can be non-conformally deposited on sidewalls of an upper portion of the patterned material stack, while not being deposited on sidewalls of a lower portion of the patterned material stack. The sidewalls of a lower portion of the opening can be laterally recessed employing a second etch process, which can include an isotropic etch component. The sidewalls of the upper portion of the opening can protrude inward toward the opening to form an overhang over the sidewalls of the lower portion of the opening. The overhang can be employed to form useful structures such as an negative offset profile in a floating gate device or vertically aligned control gate electrodes for vertical memory devices. 1. A semiconductor device comprising: a semiconductor channel;', 'a tunnel dielectric layer; and', 'a charge storage region electrically separated from the semiconductor channel by the tunnel dielectric layer; and, 'a stack of layers arranged in the following order in a first direction extending transverse to a major surface of a substrate the semiconductor channel has a first sidewall;', 'the charge storage region has a first sidewall; and', 'the first sidewall of the semiconductor channel is overhung by the first sidewall of the charge storage region by a first offset distance in a second direction transverse to the first direction; and', 'the first offset distance is greater than 1 nm., 'wherein2. The semiconductor device of claim 1 , wherein the first offset distance is greater than about 2 nm.3. The semiconductor device of claim 1 , wherein the first offset distance is greater than about 5 nm.4. The semiconductor device of claim 1 , wherein the first offset distance is 10-30 nm.5. The semiconductor device of claim 1 , wherein the semiconductor channel comprises a portion of a semiconductor material pillar etched into the major surface ...

Method Of Forming 3D Vertical NAND With III-V Channel

Disclosed herein is 3D memory with vertical NAND strings having a III-V compound channel, as well as methods of fabrication. The III-V compound has at least one group III element and at least one group V element. The III-V compound provides for high electron mobility transistor cells. Note that III-V materials may have a much higher electron mobility compared to silicon. Thus, much higher cell current and overall cell performance can be achieved. Also, the memory device may have better read-write efficiency due to much higher carrier mobility and velocity. The tunnel dielectric of the memory cells may have an AlOfilm in direct contact with the III-V NAND channel. The drain end of the NAND channel may be a metal-III-V alloy in direct contact with a metal region. The body of the source side select transistor could be formed from the III-V compound or from crystalline silicon. 1. A method for fabricating a three-dimensional (3D) non-volatile storage device , the method comprising:forming a plurality of layers of material above a semiconductor substrate that has a major surface that extends in a horizontal plane; and 'growing a III-V semiconductor upwards in a hole having a major axis that extends in the vertical direction to form a solid core of III-V semiconductor in the hole.', 'forming vertically-oriented NAND strings that extend through the plurality of layers of material, each vertically-oriented NAND string comprising a plurality of non-volatile storage elements and a NAND string channel that extends in a vertical direction with respect to the horizontal plane, wherein forming an individual one of the NAND string channels includes2. The method of claim 1 , wherein the growing a III-V semiconductor upwards in a hole having a major axis that extends in the vertical direction to form a solid core of III-V semiconductor in the hole comprises:growing a nanowire of III-V semiconductor from the semiconductor substrate upwards to fill the entire hole and to form the ...

METHOD OF MAKING A VERTICAL NAND DEVICE USING A SACRIFICIAL LAYER WITH AIR GAP AND SEQUENTIAL ETCHING OF MULTILAYER STACKS

A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and forming a sacrificial material portion including an encapsulated cavity. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material portion to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening. 1. A method of making a vertical NAND device , comprising:forming a lower portion of a memory stack over a substrate;forming a lower portion of memory openings in the lower portion of the memory stack;partially filling each lower portion of the memory openings with a sacrificial material to leave an air gap in each lower portion of the memory openings below the sacrificial material;forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material;forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings;removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings extending through the upper and the lower portions of the memory stack; andforming a semiconductor channel in each continuous memory opening.2. The method of claim 1 , wherein partially filling each lower portion of the memory openings with a sacrificial material to leave an air gap in each lower ...

NAND STRUCTURE WITH TIER SELECT GATE TRANSISTORS

Systems and methods for improving performance of a non-volatile memory by utilizing one or more tier select gate transistors between different portions of a NAND string are described. A first memory string tier may comprise a first set of memory cell transistors that may be programmed to store a first set of data and a second memory string tier may comprise a second set of memory cell transistors that are arranged above the first set of transistors and that may be programmed to store a second set of data. Between the first set of memory cell transistors and the second set of memory cell transistors may comprise a tier select gate transistor in series with the first set of memory cell transistors and the second set of memory cell transistors. The tier select gate transistor may comprise a programmable transistor or a non-programmable transistor. 1. An apparatus , comprising:a first portion of a NAND string connected to a bit line;a second portion of the NAND string connected to a source line; andan isolation transistor configured to electrically disconnect the first portion of the NAND string from the second portion of the NAND string during a memory operation, the isolation transistor comprises a first channel length and the first portion of the NAND string comprises a second transistor with a second channel length different from the first channel length.2. The apparatus of claim 1 , further comprising:a control circuit configured to detect a programmed data state stored within a memory cell transistor of the second portion of the NAND string and cause the isolation transistor to electrically disconnect the first portion of the NAND string from the second portion of the NAND string during the memory operation based on the programmed data state; andthe second channel length is less than the first channel length.3. The apparatus of claim 1 , further comprising:a control circuit configured to detect that a programmed data state stored within memory cell transistors of ...

THREE-DIMENSIONAL INTEGRATION SCHEMES FOR REDUCING FLUORINE-INDUCED ELECTRICAL SHORTS

Dielectric degradation and electrical shorts due to fluorine radical generation from metallic electrically conductive lines in a three-dimensional memory device can be reduced by forming composite electrically conductive layers and/or use of a metal oxide material for an insulating spacer for backside contact trenches. Each composite electrically conductive layer includes a doped semiconductor material portion in proximity to memory stack structures and a metallic material portion in proximity to a backside contact trench. Fluorine generated from the metallic material layers can escape readily through the backside contact trench. The semiconductor material portions can reduce mechanical stress. Alternatively or additionally, a dielectric metal oxide employed as an insulating spacer formed on the sidewalls of the backside contact trench, thereby blocking a diffusion path for fluorine radicals generated from the metallic material of the electrically conductive layers, and preventing electrical shorts between electrically conductive layers and/or a backside contact via structure. 1. A monolithic three-dimensional memory device comprising:a stack of alternating layers comprising insulating layers and electrically conductive layers and located over a substrate;an array of memory openings extending through the stack; anda plurality of memory stack structures located within a respective memory opening, wherein:the electrically conductive layers comprise composite electrically conductive layers; and a doped semiconductor material portion; and', 'a metallic material portion electrically shorted to the doped semiconductor material portion and laterally spaced from a most proximal memory stack structure by at least the doped semiconductor material portion., 'each composite electrically conductive layer comprises2. The monolithic three-dimensional memory device of claim 1 , wherein each composite electrically conductive layer contacts horizontal surfaces of a backside blocking ...

MULTILEVEL MEMORY STACK STRUCTURE EMPLOYING SUPPORT PILLAR STRUCTURES

A first stack of alternating layers including first electrically insulating layers and first sacrificial material layers is formed with first stepped surfaces. First memory openings can be formed in a device region outside of the first stepped surfaces, and first support openings can be formed through the first stepped surfaces. The first memory openings and the first support openings can be filled with a sacrificial fill material. A second stack of alternating layers including second electrically insulating layers and second sacrificial material layers can be formed over the first stack. Inter-stack memory openings including the first memory openings can be formed in the device region, and inter-stack support openings including the first support openings can be formed in a steppes surface region. Memory stack structures and support pillar structure are simultaneously formed in the inter-stack memory openings and the inter-stack support openings, respectively. 1. A monolithic three-dimensional memory device comprising:a lower stack structure comprising a first stack of alternating layers including first electrically insulating layers and first electrically conductive layers and located over a substrate;an upper stack structure comprising a second stack of alternating layers including second electrically insulating layers and second electrically conductive layers and located over the lower stack structure;a plurality of memory stack structures including respective vertical semiconductor channels, wherein a bottommost portion of each vertical semiconductor channel is electrically shorted to a source region located below the lower stack, and an upper portion of each vertical semiconductor channel is electrically shorted to a drain contact via structure overlying the vertical semiconductor channel; andat least one support pillar structure located within a stepped surface region of the lower and upper stack structures, comprising a same set of materials as the plurality ...

THREE DIMENSIONAL MEMORY DEVICE WITH HYBRID SOURCE ELECTRODE FOR WAFER WARPAGE REDUCTION

The metallic material content of a contact via structure for a three-dimensional memory device can be reduced by employing a vertical stack of a doped semiconductor material portion and a metallic fill material portion. A backside contact via can be filled with an outer metallic layer, a lower conductive material portion, an inner metallic layer, and an upper conductive material portion to form a contact via structure such that one of the lower and upper conductive material portions is a doped semiconductor material portion and the other is a metallic fill material portion. The doped semiconductor material generates less stress than the metallic fill material per volume, and thus, the contact via structure can reduce stress applied to surrounding regions in the three-dimensional memory device. 1. A monolithic three-dimensional memory device comprising:a stack of alternating layers comprising insulating layers and electrically conductive layers and located over a substrate;a memory stack structure extending through the stack and including a semiconductor channel;a trench vertically extending through the stack; anda contact via structure located in the trench, electrically connected to an end of the semiconductor channel, and comprising a vertical stack of a lower conductive material portion and an upper conductive material portion, wherein:one of the lower conductive material portion and the upper conductive material portion comprises a doped semiconductor material portion;another of the lower conductive material portion and the upper conductive material portion comprises a metallic fill material portion;the lower conductive material portion and the upper conductive material portion are vertically spaced from each other by a substantially horizontal portion of a inner metallic layer; andfurther comprising an outer metallic layer laterally surrounding the inner metallic layer and contacting an outer sidewall of the inner metallic layer, wherein the outer metallic ...

THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE HAVING A SILICIDE SOURCE LINE AND METHOD OF MAKING THEREOF

A memory device and a method of making a memory device that includes a stack of alternating layers of a first material and a second material different from the first material over a substrate, where the layers of the second material form a plurality of conductive control gate electrodes. A plurality of NAND memory strings extend through the stack, where each NAND memory string includes a semiconductor channel which contains at least a first portion which extends substantially perpendicular to a major surface of the substrate and at least one memory film located between the semiconductor channel and the plurality of conductive control gate electrodes. A source line including a metal silicide material extends through the stack. 1. A method of fabricating a memory device , comprising:forming a trench through a stack of alternating layers of a first material and a second material different from the first material over a substrate, wherein a bottom of the trench exposes a source region in contact with a semiconductor channel having at least a portion extending substantially parallel to a major surface of the substrate;etching the stack through the trench to remove at least a portion of the alternating layers of the second material and form recesses between the alternating layers of the first material;forming an electrically conductive material in the trench and within the recesses to form control gate electrodes for the memory device;removing the electrically conductive material from the trench;forming an insulating material over the sidewalls of the trench;forming a silicon liner over the insulating material;forming a metal layer over the silicon liner;annealing the metal layer to react at least a portion of the metal layer with at least a portion of the silicon liner to form a metal silicide source line, such that the source line is in electrical contact with the source region and the insulating material is positioned between the source line and the control gate ...

THREE-DIMENSIONAL MEMORY DEVICE HAVING EPITAXIAL GERMANIUM-CONTAINING VERTICAL CHANNEL AND METHOD OF MAKING THEREOF

An alternating stack of insulating layers and spacer material layers is formed over a semiconductor substrate. Memory openings are formed through the alternating stack. An optional silicon-containing epitaxial pedestal and a memory film are formed in each memory opening. After forming an opening through a bottom portion of the memory film within each memory opening, a germanium-containing semiconductor layer and a dielectric layer is formed in each memory opening. Employing the memory film and the dielectric layer as a crucible, a liquid phase epitaxy anneal is performed to convert the germanium-containing semiconductor layer into a germanium-containing epitaxial channel layer. A dielectric core and a drain region can be formed over the dielectric layer. The germanium-containing epitaxial channel layer is single crystalline, and can provide a higher charge carrier mobility than a polysilicon channel. 1. A three-dimensional memory device comprising:an alternating stack of insulating layers and electrically conductive layers located over a semiconductor substrate;a memory opening extending through the alternating stack to a top surface of the semiconductor substrate;a germanium-containing epitaxial channel layer in epitaxial alignment with a single crystalline structure of the semiconductor substrate; anda memory film located on the germanium-containing epitaxial channel layer and in the memory opening.2. The three-dimensional memory device of claim 1 , wherein:the memory film comprises a layer stack including a charge storage layer and a tunneling dielectric layer; andthe germanium-containing epitaxial channel layer contacts an inner sidewall of the tunneling dielectric layer.3. The three-dimensional memory device of claim 1 , wherein:the memory film comprises a vertical tubular portion that extends vertically through a predominant subset of layers in the alternating stack, and an annular bottom portion including an opening therein, wherein the germanium-containing ...

THREE DIMENSIONAL NAND DEVICE WITH CHANNEL CONTACTING CONDUCTIVE SOURCE LINE AND METHOD OF MAKING THEREOF

A NAND memory cell region of a NAND device includes a conductive source line that extends substantially parallel to a major surface of a substrate, a first semiconductor channel that extends substantially perpendicular to a major surface of the substrate, and a second semiconductor channel that extends substantially perpendicular to the major surface of the substrate. At least one of a bottom portion and a side portion of the first semiconductor channel contacts the conductive source line and at least one of a bottom portion and a side portion of the second semiconductor channel contacts the conductive source line. 1. A NAND memory cell region of a NAND device , comprising:a conductive source line that extends substantially parallel to a major surface of a substrate;a first semiconductor channel that extends substantially perpendicular to a major surface of the substrate; anda second semiconductor channel that extends substantially perpendicular to the major surface of the substrate;wherein at least one of a bottom portion and a side portion of the first semiconductor channel contacts the conductive source line and at least one of a bottom portion and a side portion of the second semiconductor channel contacts the conductive source line.2. The NAND memory cell region of claim 1 , wherein the bottom portion of the first semiconductor channel contacts the conductive source line.3. The NAND memory cell region of claim 1 , wherein at least one side portion of the first semiconductor channel contacts the conductive source line.4. The NAND memory cell region of claim 1 , wherein the bottom portion and at least one side portion of the first semiconductor channel contacts the conductive source line.5. The NAND memory cell region of claim 1 , wherein only at least one side portion of the first semiconductor channel contacts the conductive source line.6. The NAND memory cell region of claim 1 , wherein the conductive source line comprises a metal claim 1 , a metal alloy claim ...

INTER-PLANE OFFSET IN BACKSIDE CONTACT VIA STRUCTURES FOR A THREE-DIMENSIONAL MEMORY DEVICE

A three-dimensional memory device includes a plurality of planes, each having a respective alternating stack, strings of memory stack structures which extends through the respective alternating stack, and backside contact via structures vertically extending through the respective alternating stack, extending generally along the first horizontal direction, and laterally separating neighboring pairs of strings of memory stack structures along a second horizontal direction. A first plane includes a first plurality of strings that are laterally spaced apart along the second horizontal direction by a first plurality of backside contact via structures. A second plane laterally shifted from the first plane along the first horizontal direction and including a second plurality of strings that are laterally spaced apart along the second horizontal direction by a second plurality of backside contact via structures which are laterally offset with respect the first plurality of backside contact via structures along the second horizontal direction. 2. The three-dimensional memory device of claim 1 , wherein:the first plurality of backside contact via structures are spaced apart by a backside contact via structure pitch;the second plurality of backside contact via structures are spaced apart by the backside contact via structure pitch; anda lateral offset distance between the first plurality of backside contact via structures and the second plurality of backside contact via structures is in a range from 10% to 90% of the backside contact via structure pitch.3. The three-dimensional memory device of claim 1 , wherein each backside contact via structure is laterally spaced from the strings of memory stack structures by a respective insulating spacer.4. The three-dimensional memory device of claim 1 , further comprising bit lines that are resistively connected to respective vertical semiconductor channels in the memory stack structures and laterally extending along the second ...

Offset backside contact via structures for a three-dimensional memory device

Die cracking of a three dimensional memory device may be reduced by adding offsets to backside contact via structures. Each backside contact via structure can include laterally extending portions that extend along a first horizontal direction adjoined by adjoining portions that extend along a horizontal direction other than the first horizontal direction. In order to preserve periodicity of memory stack structures extending through an alternating stack of insulating layers and electrically conductive layers, the distance between an outermost row of a string of memory stack structures between a pair of backside contact via structures and a most proximal backside contact via structure can vary from a laterally extending portion to another laterally extending portion within the most proximal backside contact via structure. Source shunt lines that are parallel to bit lines can be formed over a selected subset of offset portions of the backside contact via structures.

MEMORY CONTROLLER FOR RESOLVING STRING TO STRING SHORTS

A memory controller includes, in one embodiment, a memory interface and a controller circuit. The memory interface is configured to interface with a memory interface configured to interface with a memory having a plurality of memory blocks. Each memory block has a plurality of strings. The controller circuit is configured to perform a string defect leakage check on one of the memory blocks during a first programming operation of the one memory block, determine whether the one memory block has one or more string to string shorts based on the string defect leakage check, and resolve the string to string shorts in response to determining that the one of the memory blocks has the string to string shorts. 1. A memory controller comprising:a memory interface configured to interface with a memory having a plurality of wordlines, each wordline having a plurality of strings; and perform a string defect leakage check on one wordline of the plurality of wordlines during a first programming operation of the one wordline,', 'determine whether the one wordline has one or more string to string shorts based on the string defect leakage check, and', 'resolve the one or more string to string shorts in response to determining that the one wordline has the one or more string to string shorts., 'a controller circuit configured to2. The memory controller of claim 1 , wherein claim 1 , to resolve the one or more string to string shorts claim 1 , the controller circuit is further configured to retire the one wordline from programming operations.3. The memory controller of claim 2 , further comprising a second memory that includes an available memory regions data structure claim 2 ,wherein, to retire the one wordline from the programming operations, the controller circuit is further configured to remove the one wordline from the available memory regions data structure.4. The memory controller of claim 1 , wherein claim 1 , to resolve the one or more string to string shorts claim 1 , the ...

Select transistors with tight threshold voltage in 3d memory

Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope.

A single-semiconductor-layer channel in a memory opening for a three-dimensional non-volatile memory device

A memory film layer is formed in a memory opening through an alternating stack of first material layers and second material layers. A sacrificial material layer is deposited on the memory film layer. Horizontal portions of the sacrificial material layer and the memory film layer at the bottom of the memory opening is removed by an anisotropic etch to expose a substrate underlying the memory opening, while vertical portions of the sacrificial material layer protect vertical portions of the memory film layer. After removal of the sacrificial material layer selective to the memory film, a doped semiconductor material layer can be formed directly on the exposed material in the memory opening and on the memory film as a single material layer to form a semiconductor channel of a memory device.

Method of manufacturing air gap isolation in high-density non-volatile memory

Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Air gaps are formed at least partially in isolation regions between active areas of the substrate. The air gaps may further extend above the substrate surface between adjacent layer stack columns. A sacrificial material is formed at least partially in the isolation regions, followed by forming a dielectric liner. The sacrificial material is removed to define air gaps prior to forming the control gate layer and then etching it and the layer stack columns to form individual control gates and columns of non-volatile storage elements.

Three-dimensional memory device containing aluminum-silicon word lines and methods of manufacturing the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The electrically conductive layers include aluminum and silicon and provide low resistance electrically conductive paths as word lines of the three-dimensional memory device. The aluminum-based electrically conductive layers can provide low resistivity, low mechanical stress, and thermal stability for use as high performance word lines.

Method of forming memory cell with high-k charge trapping layer

A non-volatile storage device with memory cells having a high-k charge storage region, as well as methods of fabrication, is disclosed. The charge storage region has three or more layers of dielectric materials. At least one layer is a high-k material. The high-k layer(s) has a higher trap density as compared to S13N4. High-k dielectrics in the charge storage region enhance capacitive coupling with the memory cell channel, which can improve memory cell current, program speed, and erase speed. The charge storage region has a high-low-high conduction band offset, which may improve data retention. The charge storage region has a low-high-low valence band offset, which may improve erase.

Nand structure with tier select gate transistors

Systems and methods for improving performance of a non-volatile memory by utilizing one or more tier select gate transistors between different portions of a NAND string are described. A first memory string tier may comprise a first set of memory cell transistors that may be programmed to store a first set of data and a second memory string tier may comprise a second set of memory cell transistors that are arranged above the first set of transistors and that may be programmed to store a second set of data. Between the first set of memory cell transistors and the second set of memory cell transistors may comprise a tier select gate transistor in series with the first set of memory cell transistors and the second set of memory cell transistors. The tier select gate transistor may comprise a programmable transistor or a non-programmable transistor.

Three dimensional nand string memory devices and methods of fabrication thereof

Monolithic three-dimensional NAND memory strings and methods of fabricating a monolithic three-dimensional NAND memory string include forming single crystal or large grain polycrystalline semiconductor material charge storage regions by a metal induced crystallization process. In another embodiment, a plurality of front side recesses are formed having a concave-shaped surface and a blocking dielectric and charge storage regions are formed within the front side recesses and over the concave-shaped surface. In another embodiment, layers of oxide material exposed in a front side opening of a material layer stack are surface nitrided and etched to provide convexly-rounded corner portions, and a blocking dielectric is formed over the convexly-rounded corner portions.

Non-volatile memory with efficient testing during erase

A non-volatile memory system erasing groups of connected memory cells separately performs erase verify for memory cells connected to even word lines to generate even results and erase verify for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine if the erase verify process indicates that the erasing has successful completed. In addition, for each group of connected memory cells, a last even result for the group is compared to a last odd result for the group. Even if the erase verify indicated that the erasing has successfully completed, the system may determine that the erasing failed (i.e. due to a defect) if the number of groups of connected memory cells that have the last even result different than the last odd result is greater than a limit.

Three dimensional nand device having reduced wafer bowing and method of making thereof

Three-dimensional memory device having a heterostructure quantum well channel

A cylindrical confinement electron gas confined within a two-dimensional cylindrical region can be formed in a vertical semiconductor channel extending through a plurality of electrically conductive layers comprising control gate electrodes. A memory film in a memory opening is interposed between the vertical semiconductor channel and the electrically conductive layers. The vertical semiconductor channel includes a wider band gap semiconductor material and a narrow band gap semiconductor material. The cylindrical confinement electron gas is formed at an interface between the wider band gap semiconductor material and the narrow band gap semiconductor material. As a two-dimensional electron gas, the cylindrical confinement electron gas can provide high charge carrier mobility for the vertical semiconductor channel, which can be advantageously employed to provide higher performance for a three-dimensional memory device.

Three-dimensional non-volatile memory device and methods of fabrication thereof

A method of fabricating a semiconductor device, such as a three-dimensional NAND memory string, includes forming a first stack of alternating layers of a first material and a second material different from the first material over a substrate, removing a portion of the first stack to form a first trench, filling the trench with a sacrificial material, forming a second stack of alternating layers of the first material and the second material over the first stack and the sacrificial material, removing a portion of the second stack to the sacrificial material to form a second trench, and removing the sacrificial material to form a continuous trench through the first stack and the second stack.