ELECTRONIC DEVICE PACKAGING

DEVICE SEMICONDUCTOR HAS DIODE AND MANUFACTORING PROCESS

SEMICONDUCTOR CHIP HAVING BONDING WINDOW SMALLER THAN WIRE BALL AND METHOD FOR MANUFACTURING THE SAME

PURPOSE: A semiconductor chip having a bonding window smaller than a wire ball and a method for fabricating the same are provided to prevent the erosion of a bonding pad by etching a metal film, therefore the size of a bonding window can be smaller than the diameter of the wire ball. CONSTITUTION: A semiconductor chip comprises a semiconductor substrate formed with predetermine circuits. A surface flattening film is coated on the surface of the semiconductor substrate. A bonding pad(14) consisting of the first metal is formed on the surface flattening film. The bonding pad(14) is electrically connected to the circuits on the semiconductor substrate. A passivation film(16) is coated on the surface flattening film to form a window. The second metal film is provided to form a bonding window of the bonding pad(14). COPYRIGHT 2001 KIPO ...

WIRE BONDING METHOD, WIRE BONDING APPARATUS AND SEMICONDUCTOR DEVICE PRODUCED BY THE SAME

ELECTRONIC DEVICE HAVING A METAL PAD STRUCTURE AND A METHOD FOR FABRICATING THE SAME, CAPABLE OF PREVENTING ELECTRICAL SHORT CIRCUIT BETWEEN BONDING WIRES

PURPOSE: An electronic device having a metal pad structure and a method for fabricating the same are provided to prevent generation of electrical short circuit between bonding wires formed on metal pad structures. CONSTITUTION: A protective insulating layer(120) is formed on an upper surface of a substrate(100). A plurality of metal pad structures(130a) penetrate the protective insulating layer. The metal pad structures are separated from each other. The metal pad structures have upper surfaces which are positioned at a level higher than a level of the protective insulating layer. A plurality of insulating barrier spacers(140) are formed on sidewalls of the metal pad structures. The insulating barrier spacers have top surfaces which are positioned at a level higher than a level of the metal pad structures. © KIPO 2008 ...

Wire bonding structure and method that eliminates special wire bondable finish and reduces bonding pitch on substrates

SEMICONDUCTOR DEVICE AND WIRE BONDING METHOD

A semiconductor device (2) includes: a (65) that is disposed on a field limiting ring (FLR) semiconductor substrate so as to divide the semiconductor substrate into an inner region and an outer region; a first bonding pad (24a to 24d) that is disposed in the inner region and is connected to an external circuit by a wire (14a to 14d) whose one end is connected to the external circuit; and a second bonding pad (26a to 26d) that is disposed in the outer region and on which the other end of the wire is bonded.

Semiconductor device and method for producing a semiconductor device

A semiconductor device exhibits a first metal layer, made of a first metal, with at least one contiguous subsection. At least one second metal layer, made of a second metal, is placed on the contiguous subsection of the first metal layer. The second metal is harder than the first metal. The second metal layer is structured to form at least two layer regions, which are disposed on the contiguous subsection of the first metal layer. The second metal exhibits a boron-containing or phosphorus-containing metal or a boron-containing or phosphorus-containing metal alloy.

Method of improving copper pad adhesion

This invention relates to a new improved method and structure in the fabricating of aluminum metal pads. The formation special aluminum bond pad metal structures are described which improve adhesion between the tantalum nitride pad barrier layer and the underlying copper pad metallurgy by a special interlocking bond pad structure. It is the object of the present invention to provide a process wherein a special grid of interlocking via structures is placed in between the underlying copper pad metal and the top tantalum nitride pad barrier layer providing improved adhesion to the aluminum pad metal stack structure. This unique contact bond pad structure provides for thermal stress relief, improved wire bond adhesion to the aluminum pad, and prevents peeling during wire bond adhesion tests.

Method of wire bonding over active area of a semiconductor circuit

A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Semiconductor device and manufacturing method thereof

A semiconductor device and manufacturing method thereof improving moisture resistance of a FeRAM. After a probe test using a pad, a metal film is formed to cover the pad in an opening of a protective film and a region from the pad to an opening outer periphery of the protective film. On the metal film, a metal bump is formed. The metal film is formed to have a two-layer structure of the first and second metal films. Materials of the lower and upper layers are selected mainly in consideration of adhesion to the protective film and adhesion to the metal bump, respectively. Film formation conditions thereof are set to provide metal films with a desired quality and thickness. Thus, penetration of moisture from the pad or the periphery into a ferroelectric capacitor can be prevented and therefore, occurrence of potential inversion abnormalities due to penetrated moisture can be effectively suppressed.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

Wire bonding method for power semiconductor device

Verfahren zum Herstellen einer Schaltungsanordnung

Die Erfindung betrifft ein Verfahren zur Herstellung einer Schaltungsanordnung (16) mit einem Gehäusedeckel (10h-1, 10j-1) und einem Gehäuseboden (10h-2, 10j-2), wobei der Gehäusedeckelrand und der Randbereich des Gehäusebodens jeweils eine Kontaktfläche (12) bilden. Das Verfahren umfasst folgende Verfahrensschritte: Bereitstellen des Gehäusedeckels (10h-1, 10j-1) und des Gehäusebodens (10h-2, 10j-2); Aufrauen mindestens einer der beiden Kontaktflächen (12); Verbinden des Gehäusedeckels (10h-1, 10j-1) und des Gehäusebodens (10h-2, 10j-2) durch eine direkte Aneinanderfügung; Aufeinanderpressen der Kontaktflächen (12) zur mechanischen Fixierung und/oder elektrischen Kontaktierung des Gehäusedeckels (10h-1, 10j-1) und des Gehäusebodens (10h-2, 10j-2).

Anschlußelektrodenstruktur und Verfahren zu deren Herstellung

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

SEMICONDUCTOR DEVICE

Construction performance of transistors

METHOD OF FORMING A BOND PAD AND STRUCTURE THEREOF

A bond pad (100) is formed by first providing a planarized combination of copper (18) and silicon oxide features (14) in a bond pad region. The silicon oxide features (14) are etched back to provide a plurality recesses (15) in the copper in the bond pad region. A corrosion barrier (22) is formed over the copper and the silicon oxide features in the recesses. Probing of the wafer (10) is done by directly applying the probe to the copper. A wire bond (24) is directly attached to the copper (18). The probe (80) is prevented from penetrating all the way through the copper (18) because the recessed features (15) are present. With the recesses (15) in the copper, the wire bond (24) more readily breaks down and penetrates the corrosion barrier and is also less likely to slip on the bond pad (100). © KIPO & WIPO 2007 ...

Power MOSFET and method of preparing the same

The power MOSFET includes a substrate of the power MOS type FET having a source electrode, a part of which corresponds to a source pad area formed directly thereon. The device also includes a bonding wire for connecting the source electrode to the outside. The bonding wire is melt-bonded on the source pad area by an ultra-sonic vibration having a frequency of about 50 to about 70 kHz.

Bond pad structure

Bond pad structures are presented. Some embodiments of the structure include a conductive conductor-insulator layer overlying a substrate. The conductive conductor-insulator layer includes a composite region having a conductor sub-region and insulator sub-region, which neighbor each other, and a single material region. The insulator is harder than the conductor.

Stacked Semiconductor Component Having Through Wire Interconnect And Method Of Fabrication

A stacked semiconductor component includes a plurality of semiconductor substrates in a stacked array and a continuous wire extending through aligned vias on the semiconductor substrates of the stacked array in electrical contact with contacts on the semiconductor substrates. A method for fabricating the semiconductor component includes the steps of stacking the semiconductor substrates in a stacked array with aligned vias; threading a wire through the aligned vias; and forming a plurality of electrical connections between the wire and the contacts on the semiconductor substrates.

Copper bonding compatible bond pad structure and method

A copper bonding compatible bond pad structure and associated method is disclosed. The device bond pad structure includes a buffering structure formed of regions of interconnect metal and regions of non-conductive passivation material, the buffering structure providing buffering of underlying layers and structures of the device.

Semiconductor device having surface protective films on bond pad

To provide: a technique capable of suppressing a titanium nitride film that is exposed at the side surface of an opening from turning into a titanium oxide film even when water permeates the opening over a pad from outside a semiconductor device and thus improving the reliability of the semiconductor device; and a technique capable of suppressing a crack from occurring in a surface protective film of a pad and improving the reliability of a semiconductor device. An opening is formed so that the diameter of the opening is smaller than the diameter of another opening and the opening is included in the other opening. Due to this, it is possible to cover the side surface of an antireflection film that is exposed at the side surface of the other opening with a surface protective film in which the opening is formed. As a result of this, it is possible to form a pad without exposing the side surface of the antireflection film.

Semiconductor device with an elevated bonding pad

A bonding pad comprises a central film and a peripheral film. The peripheral film is formed around the central film, including a film formed at the same time as the central film, and being continuous with the central film. The level of the central film is made equal to or higher than the level of a protective film on the peripheral film by central film raising means. Therefore, even if the wire moves in a lateral direction when the tip of a wire is pressed against the central film, the tip of the wire does not collide with the protective film. Accordingly, it is possible to avoid the case where cracks are generated in the surface protecting film during wire bonding because of a lateral movement of the wire.

Semiconductor components with through wire interconnects

A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer ...

Dual damascene with bond pads

An improved method of forming a bond pad (222) by performing a dual damascene etch through a layer stack (200) disposed above a substrate (204) using self aligned vias (216). The layer (200) stack includes an underlying conductive layer (208) and an insulating layer (202) disposed above the underlying conductive layer (208). The method includes the following operative steps. At least a via hole (216) is formed in the insulating layer (202) positioned over the underlying device layer (208) and extending to the underlying device layer (208) at the bottom of the via hole. A bond pad trench (218) is then formed that takes the form of the desired bond pad (222). A layer of conductive material (220) is then placed over the insulating layer (202) substantially simultaneously filling the via hole (216) and the bond pad trench (218). The bond pad (222) is then formed by removing the layer of conductive material (220) sufficient to expose the upper surface of the insulating layer (210).

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To provide the technique for suppressing changes in a titanium nitride film which is exposed on a side face of an opening on a pad into a titanium oxide film, even when water infiltrates the opening from the outside of a semiconductor device for improving the reliability of the semiconductor device, and to provide the technique for suppressing cracking in a surface protective film of the pad for improving the reliability of the semiconductor device. SOLUTION: An opening OP2 and an opening OP1 are so formed that the opening OP2 has a diameter which is smaller than that of the opening OP1, and the opening OP2 is included in the opening OP1. Consequently, a side face of an antireflection film AR, exposed on the side face of the opening, can be covered with the surface protective film PAS2 forming the opening. As a result, a pad PD is formed without having to expose the side face of the antireflection film AR. COPYRIGHT: (C)2011,JPO&INPIT ...

SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF

PURPOSE: To inhibit collision of the end of a wire with a protective film disposed on a peripheral film even if the wire is moved laterally in the case of wire bonding by setting the positioning height of a central film at the height of the protective film or higher by central film raising means. CONSTITUTION: A step 11c is generated on a second aluminum film 33 by a first aluminum film 29. The film 33 on the film 19 is called 'a central film 11a'. The film 33 disposed around the film 29 is called 'a peripheral film 11b'. With a resist 41 as a mask the film 11b except the film 11b near a step 11c is removed by etching to form a bonding pad 11. The resist 51 is removed. A plasma silicon nitride film 13 is formed on a plasma silicon oxide film 21 and the pad 11 by a plasma CVD method. With a resist 69 as a mask the film 13 is selectively removed by etching to expose the part of the film 11b and the film 11a. COPYRIGHT: (C)1992,JPO&Japio ...

SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To reduce the phenomenon wherein a bonding pad lifts up and reduce contamination troubles in wire bonding operation. SOLUTION: A bonding pad 394 and a bonding pad opening 62 are formed asymmetrically on the conductive section of a bonding pad. If there is a possibility that the bonding pad may be lifted up from the scribe line side of the bonding pad, the bonding pad opening is formed so as to be laid more in number on the conductive section close to the scribe line. If there is a possibility that the bonding pad may be lifted up from the other sides, a passivation layer is formed so as to overlap the other sides of the conductive section more. The possibility of lifting up is reduced, and contamination troubles are also reduced. COPYRIGHT: (C)1996,JPO ...

SEMICONDUCTOR DEVICE

PURPOSE: By setting the thickness of the bonding pad made of Al-evaporated film to 1.5 to 10μm, the service life of the semiconductor device can be prolonged. COPYRIGHT: (C)1977,JPO&Japio ...

SEMICONDUCTOR DEVICE AND ITS MANUFACTURE

PROBLEM TO BE SOLVED: To provide a semiconductor device which reduces the crush of a spherical part at the tip of a bonding wire and can improve the strength of joint to a bonding pad. SOLUTION: A semi-spherical recessed part 2a which is almost equal to the tip spherical part of a gold wire is formed in a bonding pad 2. The semi- spherical recessed part is formed by the existence of the recessed part formed in a semiconductor substrate. The tip spherical part of the gold wire which is fed out from the capillary of a bonding machine is brought into contact with the recessed part 2a and they are jointed. COPYRIGHT: (C)1999,JPO ...

SEMICONDUCTOR DEVICE

PURPOSE: To obtain a semiconductor device of high reliability (humidity resistance). CONSTITUTION: A bonding pad electrode part 6 of a wiring layer 4 of a DRAM element 2 formed on a silicon semiconductor substrate 1 is covered with a protecting insulating layer 5, excepting an aperture part 7, and covered with an elastic insulating film 10 excepting an aperture part 11. A wire bonding 24 is connected with the bonding pad electrode part 6, so as to cover the aperture part 11 of the elastic insulating film 10. COPYRIGHT: (C)1992,JPO&Japio ...

GOLD WIRE BONDING PROCESS FOR SOLVING OXIDATION OF COPPER WELDING PAD IN SEMICONDUCTOR CHIP

PROBLEM TO BE SOLVED: To provide a new gold wire bonding technique for enabling a remarkable improvement of an entire process efficiency. SOLUTION: An exposed copper welding pad 11 is provided outside a chip 1 already subjected to a semiconductor circuit process. When the copper welding pad 11 for the chip 1 is manufactured or when a copper welding oxide is removed therefrom, a welding pad protection film 12 of anti-oxidation material having a thermally-volatile anti-oxidation material is applied on the pad 11 of the chip 1 to protect the pad 11 from oxidizing and to enable long period storage. Even in such a situation that a process of removing the protective film 12 of the pad is unnecessary, the gold wire bonding process is carried out directly on the pad 11 of the chip 1. Utilizing mechanical energy (ultrasonic vibration or pressure deformation energy) and thermal energy generated when a metal wire 23 is bonded to the pad 11, the protective film 12 of the welding pad is volatilized.

Semiconductor device and method of manufacturing the same

SEMICONDUCTOR DEVICE

SEMICONDUCTOR COMPONENT AND WIRE COMMUNICATION PROCEDURE

TRANSISTOR AND MANUFACTORING PROCESS Of SUCH a DEVICE

SEMICONDUCTOR PACKAGE AND ITS FABRICATING METHOD TO EASILY PERFORM A WIRE BONDING PROCESS AND EFFECTIVELY AVOID SHORT-CIRCUIT

PURPOSE: A semiconductor package is provided to reduce defects caused by short-circuit between interconnections while guaranteeing sufficient coupling force between an interconnection and a wire by using a plurality of bonding plates with uniform sizes even if the pitch of the interconnections is reduced according to miniaturization of a semiconductor package. CONSTITUTION: A plurality of interconnections(120) are disposed on a substrate(100). A plurality of bonding plates(150) are electrically connected to the surface of the plurality of interconnections. At least one semiconductor chip(130) includes a plurality of bonding pads(132), mounted on the substrate. The plurality of bonding pads are electrically connected to the plurality of bonding pads by a plurality of wires(140). The width of the bonding plate can be smaller than the pitch of the interconnection and be greater than the width of the interconnection. The plurality of bonding plates can have the same height. © KIPO 2008 ...

Semiconductor device and method of manufacturing the same

Chip package and method for fabricating the same

A chip package includes a semiconductor substrate, a first metal pad over the semiconductor substrate, and a second metal pad over the semiconductor substrate. In a case, the first metal pad is tape automated bonded thereto, and the second metal pad is solder bonded thereto. In another case, the first metal pad is tape automated bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is solder bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is solder bonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is wirebonded thereto.

Semiconductor device, and method of manufacturing the same

A semiconductor device includes a substrate, a semiconductor element, a ground pad, an insulating coating member, a conductive bonding member, and a conductive cap. The inner peripheral end of a bottom of the conductive cap is disposed at a side close to the inner periphery of the insulating coating member relative to the outer peripheral end of the insulating coating member. The bottom has a shape in which the distance between the main surface and itself decreases continuously from its outer peripheral end toward its inner peripheral end.

FABRICATION OF SEMICONDUCTOR DEVICE

PURPOSE: To bond a metal wire efficiently and positively to an electrode pad by suppressing the impact load of actual load to be exerted on the electrode pad substantially equal to a set load and transmitting ultrasonic vibration energy efficiently. CONSTITUTION: When an electrode pad 12 of a semiconductor element 1 secured to a die pad 21 of a lead frame 2 is bonded through a copper wire 3 fed from a capillary 6 to an inner lead 22, the copper wire 3 is heated at the end thereof to produce a copper ball 31 which is bonded to the electrode pad 12. In such method for fabricating a semiconductor device, load for pressing the copper ball 31 to the bonding face is switched from low load F1 to high load F2 and ultrasonic vibration is exerted on the copper ball 31 simultaneously with application of high load F2. COPYRIGHT: (C)1993,JPO&Japio ...

HALBLEITERANORDNUNG MIT EINER LEITERSCHICHT UNTER DEM KONTAKTFLECK.

HALBLEITERBAUELEMENT UND VERFAHREN ZU SEINER HERSTELLUNG

Bond pad

Bond pad structures are presented. Some embodiments of the structure include a conductive conductor-insulator layer overlying a substrate. The conductive conductor-insulator layer includes a composite region having a conductor sub-region and insulator sub-region, which neighbor each other, and a single material region. The insulator is harder than the conductor.

Ribbon bonding tool and process

An ultrasonic bond is formed using a bond tool foot having a waffle shape of thin protrusions and gaps between the protrusions. The tool is brought in contact with the ribbon to a depth to create depressions in a ribbon approximately 150 μm or less from the underlying bonding surface. The tool is then brought down further into the ribbon to contact the portions of the ribbon between the depressions, such as an additional 25 to 50 μm. The result is lightly bonded regions underneath the groove portions and highly bonded regions underneath the protrusions and around the perimeter of the bond. In another embodiment, an ultrasonic bond is formed along a partial width of a ribbon.

Resin molded semiconductor device

The trend toward higher integration degrees has caused the semiconductor pellets to have large sizes. In the resin molded semiconductor devices, in particular, cracks develop on the pellet due to contraction upon cooling that stems from the difference of coefficient of thermal expansion between the molding resin and the pellet. Cracks develop conspicuously under the ball of the wire that is bonded onto the bonding pad on the pellet. The area that receives the shearing stress increases with the increase in the ball portion, and the cracks develop easily. To decrease the shearing stress and to prevent the crack from developing according to the present invention, the breaking strength of the bonding portion is set to be greater than the bending moment that is received depending upon the shape of the ball. That is, the ratio d/l of the thickness d of the ball portion and the width l of the alloy layer formed by the pad and the wire at the time of bonding is selected to be smaller than 0.2.

METHOD OF PRODUCING SEMICONDUCTOR DEVICE

A method of producing a semiconductor device includes bonding a semiconductor chip to a die pad of a lead frame by means of a silicone resin, to bonding a copper wire and an aluminum electrode of the semiconductor chip in such a manner that intermetallic compound mainly consisting of CuAl 2 is formed in the bonding region. This method suppresses the deterioration of the copper-aluminum alloy layer and these semiconductor devices have a high reliability at a high temperature, as well as uniform quality in the production.

SEMICONDUCTOR DEVICE

Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region.

METHOD OF WIRE BONDING OVER ACTIVE AREA OF A SEMICONDUCTOR CIRCUIT

A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

METHOD OF WIRE BONDING OVER ACTIVE AREA OF A SEMICONDUCTOR CIRCUIT

A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Semiconductor device

A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire that is bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. An area of a part of the bonding surface, the part not overlapping the wire, is small.

Hybrid integrated circuit device

A semiconductor device is provided wherein conductive paths 40 , formed of crystal that grows better along the X-Y axis than along the Z axis, are embedded in an insulating resin 44 , and the back surface of the conductive path 40 is exposed through the insulating resin 44 and sealed. With this arrangement, fractures of the conductive paths 40 embedded in the insulating resin 44 are suppressed.

METHOD OF THERMALLY PRESS-BONDING ALUMINUM WIRE

Patent DE3641688C2

Kondensatorstruktur

Beschrieben ist eine Kondensatorstruktur mit einem Kondensatorbereich, einem Randbereich und ggf. einem Kontaktbereich, worin im Kondensatorbereich eine erste leitfähige Schicht, eine auf die erste leitfähige Schicht aufgebrachte durchgehend erste Isolationsschicht und eine auf der Isolationsschicht 5 durchgehend aufgebrachte zweite leitfähige Schicht vorhanden ist, worin weiterhin im Kondensatorbereich langgestreckte Vertiefungen eingearbeitet sind, welche dadurch gekennzeichnet ist, daß die zweite Isolationsschicht entweder zwischen der ersten elektrisch leitfähigen Schicht und der ersten Isolationsschicht oder zwischen der ersten elektrisch leitfähigen Schicht und der zweiten elektrisch leitfähigen Schicht angeordnet ist.

Semiconductor device, and method for manufacturing same

A semiconductor device (1) is provided with a substrate (2a), a semiconductor element (3), a ground pad (10), an insulation covering member (13), an electroconductive joining member (12), and an electroconductive cap (4). The insulation covering member (13) exposes the outer periphery of the ground pad (10) and covers the inner periphery of the ground pad (10), and is provided such that a step is formed from the ground pad (10) to the substrate (2a). The electroconductive joining member (12) is disposed on the outer periphery of the ground pad (10). The electroconductive cap (4) is joined to the ground pad (10) by the electroconductive joining member (12) so as to cover the semiconductor element (3). The inner-peripheral end of the bottom part (BP) of the electroconductive cap (4) is disposed further toward the inner periphery than is the outer-peripheral end of the insulation covering member (13). The bottom part (BP) is shaped so that there is a continual decrease from the outer-peripheral ...

INTEGRATED CIRCUIT HAVING BOND PAD WITH IMPROVED THERMAL AND MECHANICAL PROPERTIES

BONDING WIRE, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND WIRE BONDING METHOD

BONDING WIRE, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND WIRE BONDING METHOD

A bonding wire for connecting a first pad to a second pad is provided. The bonding wire includes a ball part bonded to the first pad, a neck part formed on the ball part, and a wire part extending from the neck part to the second pad. Less than an entire portion of a top surface of the neck part is covered by the wire part, and the wire part is in contact with the neck part, the ball part, and the first pad.

Semiconductor device and method of manufacturing the same

In the present invention, the bonding pad is formed in a lattice-like shape. Directly underneath the passivation layer, the etching stopper layer is provided. An opening is made through the passivation layer and the etching stopper layer so as to expose the bonding pad. The cavity sections of the lattice-like shape of the bonding pad are filled with the insulating layer. The bonding wire is connected to the lattice-shaped bonding pad. With this structure, the bonding error of the device manufactured by the damascening process can be avoided.

Wire bonding method, wire bonding apparatus and semiconductor device produced by the same

A wire bonding method for joining a metal wire with a bonding pad disposed on a semiconductor element by using a load and supersonic wave vibration, comprising: during interval of time from contact of the metal wire with the bonding pad to application of the supersonic wave vibration, continuously applying a first bonding load and a second bonding load which is lower than the first bonding load; and after application of the supersonic wave vibration, continuously applying a third bonding load of a size of about 50% of the load of the second bonding load and a fourth bonding load which is lower than the first bonding load and higher than the third bonding load. The reliability of the fine wire bonding joint is improved remarkably, whereby a high quality semiconductor device can be produced at a low cost.

SEMICONDUCTOR DEVICE AND WIRE BONDING METHOD

Semiconductor device and method of manufacturing the same

LEAD FRAME, MANUFACTURE THEREOF AND SEMICONDUCTOR IC DEVICE USING THE SAME

PURPOSE: To improve junction strength between a coated wire and an inner lead and improve reliability from the view point of its junction. CONSTITUTION: A plated layer 7 having a rougher surface than in the past is formed on the surface of an inner lead 5b of a lead frame 1, with which a coated wire 8 where the surface of a metal wire 8a is coated with a coating insulating film 8b. Then, when the coated wire 8 is to be joined with the inner lead 5b, the coated insulating film 8b of the coated wire 8 can be broken by the unevenness of the surface of the plated layer 7. COPYRIGHT: (C)1992,JPO&Japio ...

SEMICONDUCTOR DEVICE

PURPOSE: To suppress occurrence of cracks due to a mechanical stress at the time of bonding and to prevent manufacturing yield and reliability of a semiconductor device from decreasing by forming a protective metal layer in an insulating film between two different bonding pads to be adjacently disposed. CONSTITUTION: Two bonding pads 4 adjacently disposed are formed on an insulating film 2 provided on a semiconductor substrate 1, and a protective metal layer 3 is formed on the lower part of the film 2 between the pads 4 and 4. A bonding wire 6 is bonded between the two pads 4 and 4 thereby to electrically connect the two pads 4, 4 by the one wire 6. In this case, since the layer 3 made of aluminum is formed in the film 2 between the pads 4 and 4, it can prevent the film 2, the substrate 1 from cracking due to a mechanical stress at the time of bonding. COPYRIGHT: (C)1991,JPO&Japio ...

SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a narrow-pitch wire bonding technique that can be applied to an LSI having a laminated wiring structure formed of Cu wiring and a low-k material similarly to an LSI having the conventional aluminum wiring by reducing the damages given to bonding pads. SOLUTION: In a semiconductor element in which multilayered laminated wiring is formed of Cu wiring and the low-k insulating film material, all cap wires to the uppermost cap wire are formed of Cu wiring layers. Each bonding pad formed of a Cu layer is constituted in a bonding pad structure in which a high-melting point intermediate metallic layer composed of a Ti (titanium) film or tungsten film, etc., is formed on the Cu layer, and an aluminum alloy layer is formed on the metallic layer. COPYRIGHT: (C)2005,JPO&NCIPI ...

MANUFACTURE OF SEMICONDUCTOR DEVICE

PURPOSE: To prevent the stepwise disconnection and the disconnection of a wire in a semiconductor device by contacting the end of a bonded wire having a spherical part including a diameter larger than the infinitesimal interval between isolated or adjacent metallic wire layers between the wire layers formed on the surface of the semiconductor element. CONSTITUTION: When the first SiO2 layer 2 is formed on the entire surface of a semiconductor substrate 1, a PSG layer 3 and the second SiO2 layer 2' are partly laminated thereon and an aluminum wire layer 4 is formed by evaporation over the stepwise part therebetween, the wire is disconnected at the stepwise part to isolate therebetween at an infinitesimal interval. When the interval is, for example, 10μm, the end of a bonding wire having a spherical part including a diameter of 100μm is thermally bonded solderlessly thereto. When a window for mounting an electrode of an SiO2 layer 14 formed without a stepwise part is wire bonded, it is similarly ...

Leistungs-Halbleitervorrichtung und deren Herstellungsverfahren und Leistungsumwandlungsvorrichtung

Die Aufgabe besteht darin, eine Technologie vorzusehen, die imstande ist, die Zuverlässigkeit einer Leistungs-Halbleitervorrichtung zu erhöhen. Eine Leistungs-Halbleitervorrichtung umfasst. ein Substrat (1), das eine isolierende Schicht (1a) und ein Schaltungsmuster (1b) umfasst, die in dieser Reihenfolge angeordnet sind; ein Leistungs-Halbleiterelement (2), das mit dem Schaltungsmuster (1b) elektrisch verbunden ist; und einen Elektrodenanschluss (3) mit einem abgedünnten Teilbereich (3b), der einen geschweißten Teilbereich (3a) enthält, der mittels eines Faserlasers an das Schaltungsmuster (1b) geschweißt wird. Eine Dicke des Schaltungsmusters (1b) beträgt nicht weniger als 0,2 und nicht mehr als 0,5 mm, und eine Dicke des abgedünnten Teilbereichs (3b) des Elektrodenanschlusses (3) beträgt nicht weniger als das Einfache und nicht mehr als dase Zweifache der Dicke des Schaltungsmusters (1b).

Verfahren zur Herstellung einer Bondverbindung

Verfahren zur Herstellung einer Bondverbindung mit den Schritten: Bereitstellen eines Körpers (1, 1'), der eine mit einer anorganischen, dielektrischen Schutzschicht (13, 13') versehene metallische Oberfläche (12a, 12a') aufweist, wobei die Schutzschicht (13, 13') zumindest einen Oberflächenabschnitt (12b, 12b') der metallischen Oberfläche (12a, 12a') bedeckt, in dem die metallische Oberfläche (12a, 12a') elektrisch leitend mit einem Anschlussleiter (30, 30') verbunden werden soll; Bereitstellen eines Anschlussleiters (30, 30'), der eine Leiterquerschnittsfläche von wenigstens 17671 μm2 aufweist; Zerstören der Schutzschicht (13, 13') zumindest lokal oberhalb des Oberflächenabschnitts (12b, 12b') durch Erzeugen einer Anpresskraft (F), die einen Abschnitt des Anschlussleiters (30, 30') an die Schutzschicht (13, 13') und den Körper (1, 1') oberhalb des Oberflächenabschnitts (12b, 12b') presst; Herstellen einer elektrisch leitenden Bondverbindung zwischen der metallischen Oberfläche (12a, 12a ...

Semiconductor device and manufacturing method thereof

SEMICONDUCTOR DEVICE

Low inductance mesa diodes for very high frequencies - are metallised after an etching to expose the plateau

TRANSISTOR AND MANUFACTORING PROCESS Of SUCH a DEVICE

L'INVENTION CONCERNE UN DISPOSITIF A SEMI-CONDUCTEURS ET UN PROCEDE DE FABRICATION D'UN TEL DISPOSITIF. CE DISPOSITIF COMPORTE UN SUBSTRAT SEMI-CONDUCTEUR 1 COMPORTANT UN PLOT DE LIAISON 28 DISPOSE SUR UNE PELLICULE ISOLANTE 5 ET CONSTITUE PAR DE L'ALUMINIUM MUNI D'UN ADDITIF, UN CONDUCTEUR 4 SITUE AU VOISINAGE DU SUBSTRAT 1 ET RELIE PAR UN FIL DE LIAISON 10AU PLOT DE LIAISON 28, LEDIT FIL ETANT CONSTITUE PAR DE L'ALUMINIUM CONTENANT LE MEME ADDITIF QUE LE PLOT DE LIAISON, UNE PELLICULE D'OXYDE D'AXYDE D'ALUMINIUM 12, 13 SUR LE FIL ET LE PLOT DE LIAISON 10, 28, L'ENSEMBLE ETANT ENROBE DANS UNE RESINE 31. APPLICATION NOTAMMENT AUX CIRCUITS INTEGRES A HAUTE FIABILITE RESISTANT BIEN A L'HUMIDITE. THE INVENTION RELATES TO A SEMICONDUCTOR DEVICE AND TO A PROCESS FOR MANUFACTURING SUCH A DEVICE. THIS DEVICE INCLUDES A SEMICONDUCTOR SUBSTRATE 1 INCLUDING A BONDING PLOT 28 PROVIDED ON AN INSULATING FILM 5 AND CONSISTS OF ALUMINUM MADE WITH AN ADDITIVE, A CONDUCTOR 4 LOCATED NEAR SUBSTRATE 1 AND CONNECTED BY A BONDING WIRE 10 AT THE BONDING PLOT 28, THE WIRE IS CONSTITUTED BY ALUMINUM CONTAINING THE SAME ADDITIVE AS THE BONDING PLOT, A FILM OF ALUMINUM AXIDE OXIDE 12, 13 ON THE WIRE AND THE BONDING PLOT 10, 28 , THE ASSEMBLY BEING COATED IN A RESIN 31. APPLICATION ESPECIALLY TO HIGH RELIABILITY INTEGRATED CIRCUITS WITH WELL RESISTANCE TO HUMIDITY.

METHOD AND SYSTEM FOR FABRICATING SEMICONDUCTOR COMPONENTS WITH THROUGH WIRE INTERCONNECTS

Bond pad

Bond pad structures are presented. Some embodiments of the structure include a conductive conductor-insulator layer overlying a substrate. The conductive conductor-insulator layer includes a composite region having a conductor sub-region and insulator sub-region, which neighbor each other, and a single material region. The insulator is harder than the conductor.

SEMICONDUCTOR DEVICE

A semiconductor device provided with a pad having improved moisture resistance. The semiconductor device is provided with a circuit section including a plurality of semiconductor elements formed on a semiconductor substrate; an insulating stacked layer which covers the circuit section, is formed on the semiconductor substrate and includes a passivation film as a topmost layer with an opening; a ferroelectric capacitor formed in the insulating stacked layer; a wiring structure which is formed in the insulating stacked layer and connected with the semiconductor element and the ferroelectric capacitor; a pad electrode structure which is connected with the wiring structure, formed in the insulating stacked layer and exposed from the opening on the passivation film; a conductive pad protection film which includes a Pd film, covers the pad electrode structure through the opening on the passivation film, and extends on the passivation film; and a stud bump or a bonding wire which is connected ...

SEMICONDUCTOR DEVICE AND WIRE BONDING METHOD

A semiconductor device (2) includes: a FLR (65) that is disposed on a semiconductor substrate so as to divide the semiconductor substrate into an inner region and an outer region; a first bonding pad (24a to 24d) that is disposed in the inner region and is connected to an external circuit by a wire (14a to 14d) whose one end is connected to the external circuit; and a second bonding pad (26a to 26d) that is disposed in the outer region and on which the other end of the wire is bonded.

Semiconductor device with pads of enhanced moisture blocking ability

A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.

Wire bonding apparatus

A wire bonding method for joining a metal wire with a bonding pad disposed on a semiconductor element by using a load and supersonic wave vibration, comprising: during interval of time from contact of the metal wire with the bonding pad to application of the supersonic wave vibration, continuously applying a first bonding load and a second bonding load which is lower than the first bonding load; and after application of the supersonic wave vibration, continuously applying a third bonding load of a size of about 50% of the load of the second bonding load and a fourth bonding load which is lower than the first bonding load and higher than the third bonding load. The reliability of the fine wire bonding joint is improved remarkably, whereby a high quality semiconductor device cna be produced at a low cost.

Method of wire bonding over active area of a semiconductor circuit

A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

SEMICONDUCTOR DEVICE

PURPOSE: To provide an electrode terminal lead which does not electrically become nonconductive due to invasion of moisture by forming double in a conductor layer. CONSTITUTION: A specific part such as a metallic wire 3 connected with P or N-type region formed in a substrate is arranged on an insulating layer 2 of oxide formed on a semiconductor substrate 1 in the vicinity of a electrode terminal lead. The surface protective film 5 on the wire 3 is formed not to contain the partial region 7 of the wire 3, and extends on the surface 5 at the second metallic layer 8 electrically connected to the region 7. To connect a fine metallic wire 6 to the second metallic layer 8, the connecting position of the wire 6 is disposed to include the region 7 of the wire 3. In this manner, the second metallic layer 8 of the part covered with the wire 6 becomes stable, thereby improving the reliability. COPYRIGHT: (C)1982,JPO&Japio ...

WIRE BONDING METHOD, ELECTRONIC APPARATUS, AND METHOD OF MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To provide a wire bonding method that allows a reliable connection by preventing short-circuit or peeling in a joint between a wire and an electronic component. SOLUTION: The wire bonding method has steps of: forming a bump 22 on a first electrode 21 provided on a first electronic component; and bonding the bump 22 and a second electrode 31 provided on a second electronic component by using a wire 11. Each of the bump 22 and the wire 11 is formed of a material containing Au, and the Au purity of the material forming the bump 22 is lower than that of the material forming the wire 11. COPYRIGHT: (C)2010,JPO&INPIT ...

SOLID-STATE IMAGING APPARATUS AND ITS MANUFACTURING METHOD, AND SEMICONDUCTOR APPARATUS AND ITS MANUFACTURING METHOD

PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus preventing occurrence of corrosion in an alloy layer of Au-wire and Al-electrode interface under high temperature and high humidity. SOLUTION: A solid-state imaging apparatus 1 includes a ceramic substrate 10 on which a solid-state imaging element 14 is mounted, and a transparent member 11. A polymerization initiator of a resin adhesive material 20 for bonding the ceramic substrate 10 and the transparent member 11 is onium salt having a halogen-containing aromatic compound as an anion. COPYRIGHT: (C)2008,JPO&INPIT ...

ELECTRIC CHARACTERIZATION Of an INSULATING LAYER RECOVERING a CONDUCTING SUBSTRATE OR SEMICONDUCTOR

DISPOSITIF A SEMI-CONDUCTEURS ET PROCEDE DE FABRICATION D'UN TEL DISPOSITIF

L'INVENTION CONCERNE UN DISPOSITIF A SEMI-CONDUCTEURS ET UN PROCEDE DE FABRICATION D'UN TEL DISPOSITIF. CE DISPOSITIF COMPORTE UN SUBSTRAT SEMI-CONDUCTEUR 1 COMPORTANT UN PLOT DE LIAISON 28 DISPOSE SUR UNE PELLICULE ISOLANTE 5 ET CONSTITUE PAR DE L'ALUMINIUM MUNI D'UN ADDITIF, UN CONDUCTEUR 4 SITUE AU VOISINAGE DU SUBSTRAT 1 ET RELIE PAR UN FIL DE LIAISON 10AU PLOT DE LIAISON 28, LEDIT FIL ETANT CONSTITUE PAR DE L'ALUMINIUM CONTENANT LE MEME ADDITIF QUE LE PLOT DE LIAISON, UNE PELLICULE D'OXYDE D'AXYDE D'ALUMINIUM 12, 13 SUR LE FIL ET LE PLOT DE LIAISON 10, 28, L'ENSEMBLE ETANT ENROBE DANS UNE RESINE 31. APPLICATION NOTAMMENT AUX CIRCUITS INTEGRES A HAUTE FIABILITE RESISTANT BIEN A L'HUMIDITE.

ELECTRIC CHARACTERIZATION Of an INSULATING LAYER RECOVERING a CONDUCTING SUBSTRATE OR SEMICONDUCTOR

L'invention concerne la caractérisation d'une couche isolante (14) dont une première face recouvre une face conductrice ou semiconductrice d'un substrat, la seconde face de la couche isolante (14) étant accessible électriquement, la caractérisation consistant à vérifier la qualité d'isolation électrique présentée par au moins une zone (32) de la couche isolante (14) au moyen d'un test électrique. L'invention met en oeuvre les étapes de : - création d'au moins un défaut majeur dans une zone (31, 33) de la couche isolante (14), ce défaut majeur formant un court-circuit localisé entre la seconde face de la couche isolante et la face conductrice ou semiconductrice du substrat, - application du test électrique à la zone (32) de la couche isolante (14) à tester grâce à un signal électrique fourni entre une électrode (21, 23) mise en contact avec le défaut majeur et une électrode (22) mise en contact avec la zone (32) à tester.

Low inductance mesa diodes for very high frequencies - are metallised after an etching to expose the plateau

Semiconductor device having a bond pad

ELECTRONIC DEVICE PACKAGING

A hermetically coated device (10) includes an integrated semiconductor circuit die (16), a first layer comprising an inorganic material, the first layer (300) enveloping the integrated circuit die (16), a second layer (400), the second layer (400) enveloping the integrated semiconductor circuit die (16). Formation of such device includes steps of providing an integrated semiconductor circuit die (16), applying a first layer (300) comprising an inorganic material, the first layer (300) enveloping integrated semiconductor circuit die (16), and applying a second layer (400), the second layer (400) enveloping the integrated semiconductor circuit die (16). © KIPO & WIPO 2007 ...

Semiconductor device

The object of the present invention is to provide a narrow-pitch wire-bonding technique for the LSI in layered wiring structure in Cu wiring/Low-k material to reduce the damages to the bonding pad and ensure the suitability for the LSI with the conventional Cu wiring. The solution is to form the cover wiring to the top layer all with the Cu wiring layer for the semiconductor device using the Cu wiring/Low-k insulative film material to form the multi-layer wirings; and, in the view of the bonding pad formed with Cu layer, the object of the present invention can be achieved by forming the intermediate metal layer with Titanium (Ti) film and Tungsten (W) film with high melting-point formed on the top, and further forming the bonding pad structure with aluminum alloy layer on the top.

Semiconductor package structure

Semiconductor package structure is provided. A semiconductor package structure includes a chip, a molding material surrounding the chip, a through-via extending from a first surface to a second surface of the molding material, a first re-distribution layer (RDL) wire disposed on the second surface of the molding material and coupled to the through-via, and a second RDL wire disposed on the second surface of the molding material and parallel to the first RDL wire. The second surface is opposite to the first surface. A portion of the second RDL wire across the through-via has a first segment with a first width and a second segment with a second width different from the first width.

SEMICONDUCTOR DEVICE

A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire that is bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. An area of a part of the bonding surface, the part not overlapping the wire, is small. 1. (canceled)2. A semiconductor device comprising:a flame member having a die pad, source leads and a gate lead;a semiconductor chip mounted on the die pad, the semiconductor chip having a first metal boding pad for a source electrode and a second metal bonding pad for a gate electrode and an organic insulating film formed over the first and second metal boding pads, the first and second boding pads and the organic insulating film being formed on a first main surface of the semiconductor chip, the organic insulating film having a first opening exposing a first part of the first metal boding pad, a second opening exposing a second part of the first metal boding pad and a third opening exposing a part of the second metal boding pad;a first wire being bonded to the first part of the first metal boding pad and to the source leads;a second wire being bonded to the second part of the first metal boding pad and to the source leads;a third wire being bonded to the part of the second metal boding pad and to the gate lead; anda resin sealer sealing the semiconductor chip, the first to third wires, a part of the source leads and a part of the gate lead such that the resin sealer is in contact with the organic insulating film;wherein, a total area of the organic insulating film in a plan view is larger than a total area defined by the first to third openings of the organic insulating film in the plan view.3. A semiconductor device according to claim 2 ,wherein each of the first and second ...

Semiconductor device with improved bond pads

A semiconductor device with improved bond pads. The semiconductor device includes bond pads electrically connected to an active circuit in the device and openings formed in the bonding surface of the bond pads. The opening(s) may include recesses extending partially into the bonding surface or channels that extend entirely through the bond pads. Various shapes and configurations of the openings may be used, such as a pattern of channels radiating from the center of the bonding surface, a series of spaced apart rectangular channels arranged parallel to one another, an array of L shaped channels arranged around the center of the bonding surface, or an array of holes.

Ribbon bonding tool and process

An ultrasonic bond is formed using a bond tool foot having a waffle shape of thin protrusions and gaps between the protrusions. The tool is brought in contact with the ribbon to a depth to create depressions in a ribbon approximately 150 m or less from the underlying bonding surface. The tool is then brought down further into the ribbon to contact the portions of the ribbon between the depressions, such as an additional 25 to 50 m. The result is lightly bonded regions underneath the groove portions and highly bonded regions underneath the protrusions and around the perimeter of the bond. In another embodiment, an ultrasonic bond is formed along a partial width of a ribbon.

Wire-bonded semiconductor component with reinforced inner connection metallization

Consistent with an example embodiment, there is a semiconductor component comprising a semiconductor chip made of a doped silicon substrate. The chip is doped into a semiconductor device and structured, and includes an inner connection metallization in a contact window. The inner connection metallization of said semiconductor chip is connected to the respective outer connection metallization by a wire bond connection, wherein the inner connection metallization comprises a reinforcing system having an open grid structure on the doped silicon substrate.

Method for assembling at least one chip using a fabric, and fabric including a chip device

A method for assembling a device on two substantially parallel taut threads. The device includes an electronic chip and two substantially parallel grooves open on opposite sides of the device. The distance separating the grooves corresponds to the distance separating the threads. The device presents a penetrating shape along an axis perpendicular to the plane of the grooves, having a base at the level of the grooves and an apex of smaller size than the distance separating the threads. The method includes the steps consisting in placing the apex of the device between the two threads; in moving the device between the two threads resulting in the threads being separated from one another by the penetrating shape of the device; and in continuing movement of the device until the threads penetrate into the grooves reverting to their initial separation distance.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

WIRE BONDING BETWEEN ISOLATION CAPACITORS FOR MULTICHIP MODULES

A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.

Semiconductor device with pads of enhanced moisture blocking ability

A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.

SEMICONDUCTOR DEVICE

A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire that is bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. An area of a part of the bonding surface, the part not overlapping the wire, is small. 1. A semiconductor device comprising:a semiconductor chip having an insulating film formed on a first main surface, the insulating film having a first opening exposing a first bonding surface and a second opening exposing a second bonding surface;a first wire bonded to the first bonding surface of the semiconductor chip;a second wire bonded to the second bonding surface of the semiconductor chip; anda sealer that seals the semiconductor chip, the first wire, and the second wire so that the sealer is in contact with the first bonding surface and the second bonding surface of the semiconductor chip,wherein each of the first bonding surface and the second bonding surface is made of a metal material,the sealer is made of a resin material, a first connecting portion bonded to the first bonding surface;', 'a second connecting portion bonded to the first bonding surface; and', 'a first loop portion located between the first connecting portion and the second connecting portion in a first direction in a plan view, the first loop portion being separated from the first bonding surface,, 'the first wire includes a third connecting portion bonded to the second bonding surface;', 'a fourth connecting portion bonded to the second bonding surface; and', 'a second loop portion located between the third connecting portion and the fourth connecting portion in a plan view, the second loop portion being separated from the second bonding surface,, 'the second wire includes a fist side extending from the ...

Semiconductor package structure

Semiconductor package structures are provided. A semiconductor package structure includes a chip, a molding material surrounding the chip, a through-via extending from a first surface to a second surface of the molding material, a first re-distribution layer (RDL) wire disposed on the second surface of the molding material and coupled to the through-via, and a second RDL wire disposed on the second surface of the molding material and parallel to the first RDL wire. The second surface is opposite to the first surface. A portion of the second RDL wire across the through-via has a first segment with a first width and a second segment with a second width different from the first width.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME

To improve an integration degree of a semiconductor device. 1. A semiconductor device comprising:a semiconductor substrate;a plurality of wiring layers formed on the semiconductor substrate;a pad electrode formed on an uppermost wiring layer among the plurality of wiring layers;an insulating film having a first opening above the pad electrode;a rewiring electrically connected to the pad electrode and extending over the insulating film;a protective film covering an upper surface of the rewiring, and having a second opening exposing part of the upper surface of the rewiring;an external pad electrode electrically connected to the rewiring through the second opening and extending over the protective film; anda wire connected to the external pad electrode,wherein, when seen in a plan view, part of the external pad electrode is located in a region outside the rewiring.2. The semiconductor device according to claim 1 ,wherein the wire has a ball portion connected to the external pad electrode, andwhen seen in a plan view, part of the ball portion is located in a region outside the rewiring.3. The semiconductor device according to claim 2 , further comprising an adjacent rewiring formed on the insulating film and disposed adjacent to the rewiring claim 2 ,wherein when seen in a plan view, the ball portion overlaps the insulating film located between the rewiring and the adjacent rewiring.4. The semiconductor device according to claim 1 ,wherein the insulating film or the protective film is provided as an organic film.5. The semiconductor device according to claim 4 ,wherein the organic film has a Young's modulus of 6 GPa or less and a thickness of 0.5 μm or more.6. The semiconductor device according to claim 5 ,wherein the organic film is a polyimide resin film.7. The semiconductor device according to claim 1 ,wherein the external pad electrode has a film thickness smaller than that of the rewiring.8. The semiconductor device according to claim 1 ,wherein the external pad ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a substrate, a semiconductor element, a ground pad, an insulating coating member, a conductive bonding member, and a conductive cap. The inner peripheral end of a bottom of the conductive cap is disposed at a side close to the inner periphery of the insulating coating member relative to the outer peripheral end of the insulating coating member. The bottom has a shape in which the distance between the main surface and itself decreases continuously from its outer peripheral end toward its inner peripheral end. 1. A semiconductor device comprising:a substrate having a main surface;a semiconductor element packaged on the main surface;a ground pad provided on the main surface so as to surround the semiconductor element;an insulating coating member provided to expose an outer peripheral side of the ground pad, cover an inner peripheral side of the ground pad, and form a step from over the ground pad to over the substrate;a conductive bonding member disposed at the outer peripheral side of the ground pad; anda conductive cap bonded to the ground pad with the conductive bonding member so as to cover the semiconductor element,an inner peripheral end of a bottom of the conductive cap being disposed at a side close to an inner periphery of the insulating coating member relative to an outer peripheral end of the insulating coating member,the bottom having a shape in which a distance between the main surface and the bottom decreases continuously from an outer peripheral end of the bottom toward the inner peripheral end of the bottom.2. The semiconductor device according to claim 1 , wherein an end at an inner periphery of the bottom having the shape in which the distance between the main surface and the bottom decreases continuously from the outer peripheral end of the bottom toward the inner peripheral end of the bottom is disposed directly above a center of a region at the outer peripheral side of the ground pad exposed from the insulating ...

Wire bonding between isolation capacitors for multichip modules

A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.

SEMICONDUCTOR APPARATUS

A semiconductor apparatus includes: a metal plate; a semiconductor device mounted on the metal plate; an external terminal electrically connected to the semiconductor device or the metal plate; a metal wire wire-bonded to the semiconductor device, the metal plate or the external terminal; and a package covering and resin-sealing the semiconductor device, the metal plate and the metal wire, wherein the metal wire is bonded to a top-layer electrode of the semiconductor device at a first bond and a second bond, and the metal wire includes a low loop that is positioned between the first bond and the second bond, is adjacent to at least one of the first bond and the second bond and is not in contact with the top-layer electrode. 1. A semiconductor apparatus comprising:a metal plate;a semiconductor device mounted on the metal plate;an external terminal electrically connected to the semiconductor device or the metal plate;a metal wire wire-bonded to the semiconductor device, the metal plate or the external terminal; anda package covering and resin-sealing the semiconductor device, the metal plate and the metal wire,wherein the metal wire is bonded to a top-layer electrode of the semiconductor device at a first bond and a second bond, andthe metal wire includes a low loop that is positioned between the first bond and the second bond, is adjacent to at least one of the first bond and the second bond and is not in contact with the top-layer electrode.2. The semiconductor apparatus according to claim 1 , wherein the metal wire is linearly in contact with the top-layer electrode between the low loop adjacent to the first bond and the low loop adjacent to the second bond.3. The semiconductor apparatus according to claim 1 , wherein the metal wire is bonded to multiple points of the top-layer electrode between the low loop adjacent to the first bond and the low loop adjacent to the second bond.4. The semiconductor apparatus according to claim 2 , wherein the metal wire is bonded ...

SEMICONDUCTOR PACKAGE STRUCTURE

Semiconductor package structures are provided. A semiconductor package structure includes a chip, a molding material surrounding the chip, a through-via extending from a first surface to a second surface of the molding material, and a first re-distribution layer (RDL) wire disposed on the second surface of the molding material and electrically separated from the through-via. The second surface is opposite to the first surface. A portion of the first RDL wire across the through-via has a first segment with a first width and a second segment with a second width different from the first width. 1. A semiconductor package structure , comprising:a chip;a molding material surrounding the chip;a through-via extending from a first surface to a second surface of the molding material, wherein the second surface is opposite to the first surface; anda first re-distribution layer (RDL) wire disposed on the second surface of the molding material and electrically separated from the through-via,wherein a portion of the first RDL wire across the through-via has a first segment with a first width and a second segment with a second width different from the first width.2. The semiconductor package structure as claimed in claim 1 , wherein the first width of the first segment of the first RDL wire on a boundary between the through-via and the molding material is greater than the second width of the second segment of the first RDL wire on the through-via.3. The semiconductor package structure as claimed in claim 1 , wherein the first RDL wire has a connecting pattern on a boundary between the through-via and the molding material claim 1 , and a center of the connecting pattern is centered on an edge of the through-via.4. The semiconductor package structure as claimed in claim 3 , wherein the connecting pattern comprises a main portion having a circular shape claim 3 , a regular polygonal shape claim 3 , an ellipse shape or an oval shape.5. The semiconductor package structure as claimed in ...

Method of forming a bond pad and structure thereof

A bond pad is formed by first providing a planarized combination of copper and silicon oxide features in a bond pad region. The silicon oxide features are etched back to provide a plurality recesses in the copper in the bond pad region. A corrosion barrier is formed over the copper and the silicon oxide features in the recesses. Probing of the wafer is done by directly applying the probe to the copper. A wire bond is directly attached to the copper. The presence of the features improves probe performance because the probe is likely to slip. Also the probe is prevented from penetrating all the way through the copper because the recessed features are present. With the recesses in the copper, the wire bond more readily breaks down and penetrates the corrosion barrier and is also less likely to slip on the bond pad.

반도체 장치 및 그 제조 방법

본 발명의 목적은 더머신 프로세스에 의한 디바이스의 본딩 불량을 없애기 위한 것이다. 본딩 패드(21)는 격자 모양으로 형성되어 있다. 패시베이션층(22)의 바로 아래에는 에칭 스토퍼층이 배치되어 있다. 패시베이션층(22) 및 에칭 스토퍼층에는 본딩 패드(21) 상에 개구(23)가 설치되어 있다. 격자 모양의 본딩 패드(21)의 사이에는 절연층(27)이 충전되어 있다. 본딩 와이어는 격자 모양의 본딩 패드(21)에 결합되어 있다.

ワイヤボンデイング方法

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Method of forming a bond pad and structure thereof

본드 패드(100)는 본드 패드 영역에 구리(18) 및 실리콘 옥사이드 피쳐(14)의 평탄화된 결합물을 우선 제공함으로써 형성된다. 실리콘 옥사이드 피쳐(14)는 본드 패드 영역의 구리에 복수의 리세스(15)를 제공하기 위하여 에칭백된다. 부식 배리어(22)는 리세스의 구리 및 실리콘 옥사이드 피쳐상에 형성된다. 웨이퍼(10)의 제공은 구리에 프로브를 직접 제공하기 전에 행해진다. 와이어 본드(24)는 직접적으로 구리(18)에 접착된다. 프로브(80)는 리세스된 피쳐(15)가 존재하기 때문에 구리(18)를 통해 모든 길을 관통하지 않는다. 구리의 리세스(15)로 인해, 와이어 본드(24)는 부식 배리어를 쉽게 분석하고 관통하고 또한 본드 패드(100)상에서 보다 적게 미끄러진다. Bond pads 100 are formed by first providing a planarized combination of copper 18 and silicon oxide features 14 in the bond pad region. Silicon oxide feature 14 is etched back to provide a plurality of recesses 15 in the copper of the bond pad region. Corrosion barrier 22 is formed on the copper and silicon oxide features of the recess. Provision of the wafer 10 is done prior to providing the probe directly to copper. Wire bond 24 is directly bonded to copper 18. The probe 80 does not penetrate all the way through the copper 18 because there is a recessed feature 15. Due to the recesses 15 of copper, the wire bonds 24 easily analyze and penetrate the corrosion barriers and also slide less on the bond pads 100. 배리어, 디파지팅, 본드, 패드, 결합물, 구리 Barrier, Depositioning, Bond, Pads, Bonding, Copper

Method for fabricating semiconductor components with through wire interconnects

A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer scale components, stacked components, or interconnect components for electrically engaging or testing other semiconductor components.

How to connect electronic components

PROBLEM TO BE SOLVED: To prevent a bonding wire from coming out of a bonding tool, when the bonding tool vibrates in a method for connecting a power device to the terminals of a wiring board through wedge bonding, even if the initial pressure applied to the tool is reduced by a method where frictional force between the bonding wire and bonding tool is increased. SOLUTION: After a bonding wire 20 supported by the wedge parts of a bonding tool 10 is pressed against the groove part of a jig 30 with a groove made of a material harder than the wire 20 so as to increase a contact area M1 between the wire 20 and the tool 10, the wire 20 is pressed against a power device 1 and made to vibrate under pressure applied by the tool 10 to connect the wire 20 to the power device 1. Then the wire 20 is layed out to the terminal of a wiring board and connected to the terminal through wedge bonding.

Production of semiconductor device

Electrode structure for semiconductor device

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Method of wire bonding over active area of a semiconductor circuit

A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Patent JPS5131185B2

Semiconductor device

Patent JPS4962081A

Semiconductor device with bonding pad

本发明提供一种具有接合垫的半导体装置。该半导体装置包括：一第一基板，包含一元件区域以及一接合区域，其中该第一基板具有一上表面以及一底部表面；一半导体元件，设置于该元件区域的该第一基板的上表面上；一第一金属间介电层，至少形成于该接合区域的该第一基板的上表面；一最底层的金属图案，设置于该第一金属间介电层之中，其中该最底层的金属图案作为接合垫；以及一开口，穿过该第一基板，且露出该最底层的金属图案。通过本发明，可以获得更佳的CMOS图像传感器的接合垫以及接合导线之间接合品质，例如提升两者的黏合度，借此，可防止接合导线剥落。

Semiconductor package and method for manufacturing the same

A semiconductor package and a method for manufacturing the same are provided to perform a wire bonding process on a fine finger by bonding a wire at an upper surface and a lateral surface of the finger. A substrate has a finger(111). One or more semiconductor chip having a chip pad is laminated on the substrate. A wire(160) is formed to connect electrically the finger and the chip pad to each other. One end of the wire is bonded with the finger at an upper surface of the finger and a lateral surface of the finger. A protrusion(162) is formed at one end of the wire. In a vertical projection of the substrate, a maximum width of an upper surface of the finger is smaller than a width of the protrusion. In the vertical projection of the substrate, the upper surface of the finger is positioned within a lower surface of the finger.

Power semiconductor module

(57)【要約】 【課題】ワイヤとチップとの熱膨張率の相違に基づく熱 応力により、ワイヤが短時間で剥離することを改善す る。 【解決手段】パッド６にリング状の溝を設け、ワイヤ７ の端部のパッド６との接触角を大きくし、応力拡大係数 を小さくし、発生する熱応力を低減しクラックの進展速 度を低減する。

Semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Bonding pad of semiconductor memory device for improving adhesive strength bonding pad and bonding wire and method of manufacturing the same

와이어 본딩 공정 시 와이어와의 본딩 패드의 접착력을 증가시키는 반도체 장치의 패드 및 이를 제조하는 방법이 제공된다. 상기 패드는 패드가 형성될 소정의 위치에 사진 식각 기술을 이용하여 절연막을 패터닝하여 형성되는 콘택 홀 및 상기 콘택 홀 및 상기 절연막 상에 형성되는 도전체를 구비하며, 상기 패드의 표면에 단차가 형성된다. 상기 패드는 상기 콘택 홀과 상기 패드 사이에 소정의 콘택 물질을 더 구비하며, 바람직하게는 상기 단차는 상기 콘택 홀에 의하여 생성된다. Provided are a pad of a semiconductor device and a method of manufacturing the same, which increase adhesion of a bonding pad with a wire in a wire bonding process. The pad includes a contact hole formed by patterning an insulating film using a photolithography technique at a predetermined position where the pad is to be formed, and a conductor formed on the contact hole and the insulating film, wherein a step is formed on the surface of the pad. do. The pad further includes a predetermined contact material between the contact hole and the pad, preferably the step is generated by the contact hole.

Semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Semiconductor device and a method of manufacturing the same

System for fabricating semiconductor components with through wire interconnects

A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer scale components, stacked components, or interconnect components for electrically engaging or testing other semiconductor components.

SEMICONDUCTOR DEVICE WITH DIODE AND MANUFACTURING METHOD

Un dispositif à semiconducteur comprend un circuit électronique (112) formé sur un substrat semiconducteur (13); une borne (121) reliée au circuit électronique; et un élément de connexion en métal (3) connecté à la fois à la borne et à une région d'une surface du substrat qui est à nu en position adjacente à la borne. Avec cette structure, une diode dont l'une des électrodes est constituée par la surface du substrat, est formée entre l'élément de connexion (3) et le substrat, de façon à écouler des surtensions susceptibles d'être appliquées au circuit électronique (112). A semiconductor device includes an electronic circuit (112) formed on a semiconductor substrate (13); a terminal (121) connected to the electronic circuit; and a metal connection element (3) connected both to the terminal and to a region of a surface of the substrate which is exposed in position adjacent to the terminal. With this structure, a diode, one of the electrodes of which is formed by the surface of the substrate, is formed between the connection element (3) and the substrate, so as to pass overvoltages which can be applied to the electronic circuit ( 112).

Semiconductor device

내용 없음. No content.

Semiconductor arrangement with an electrode spot.

Wire-bonded semiconductor component with reinforced inner connection metallization

A semiconductor component comprising a semiconductor chip (2) made of a doped silicon substrate, which chip is doped into a semiconductor device and structured, and comprises an inner connection metallization (7) in a contact window, and said inner connection metallization of said semiconductor chip is connected to the respective outer connection metallization by a wire bond connection (9), characterized in that the inner connection metallization comprises a reinforcing system (8) having an open grid structure on the doped silicon substrate.

Manufacture of bonding pad

Lead of semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Semiconductor chip having a bonding window smaller than a wire ball

A semiconductor chip is provided comprising a semiconductor substrate having determined circuit elements on it, a surface-smoothing layer deposited on the substrate, a bonding pad formed on the smoothing layer and connected electrically to the circuit elements, a passivation layer formed on the surface-smoothing layer, the passivation layer having a window for exposing a part of the bonding pad, and a second metal layer having a same height as the passivation layer and occupying peripheral parts of the window to form a reduced bonding windows for the bonding pad.

Electrically conductive connection of the active parts of an electrical component or an integrated circuit with connection points

Semiconductor device and manufacturing method of semiconductor device

A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.

A wirebond structure and method forming the same

Semiconductor device and manufacturing method thereof

Wire bonding

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Semiconductor device and manufacturing method therefor

Wire-Bonded Semiconductor Component with Reinforced Inner Connection Metallization

A semiconductor component comprising a semiconductor chip ( 2 ) made of a doped silicon substrate, which chip is doped into a semiconductor device and structured, and comprises an inner connection metallization ( 7 ) in a contact window, and said inner connection metallization of said semiconductor chip is connected to the respective outer connection metallization by a wire bond connection ( 9 ), characterized in that the inner connection metallization comprises a reinforcing system ( 8 ) having an open grid structure on the doped silicon substrate.

Roughened bonding pad and bonding wire surfaces for low pressure wire bonding

An intermediate semiconductor structure and method for low-pressure wire bonding that reduces the propensity of dielectric material to mechanical failure due to any wire bonding stresses. Roughened surfaces such as metal pillars or metal dendrites are provided on a bonding pad, bonding wire or both. These roughened surfaces increase reactivity between the bond wire and the bond pad to form strong bonds. This increased activity as a result of the roughened bonding pad and/or wire surfaces reduce the amount of pressure, temperature and energy required for wire bonding, which in turn, avoids damage to the bonding pad as well as the semiconductor substrate.

Integrated circuit device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Wirebond structures

Wire bonding method, electronic apparatus, and method of manufacturing same

A wire bonding method which includes forming a bump on a first electrode provided in a first electronic part and bonding the bump and a second electrode provided in a second electronic part by using a wire, wherein the bump and the wire are formed using materials containing Au, and an Au purity of the material forming the bump is lower than an Au purity of the material forming the wire.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use or the like, in general, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding or the like using a gold wire and the like for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). The invention of the present application provides a semiconductor integrated circuit device (semiconductor device or electron circuit device) which includes a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board or the like (wiring substrate).

Method for assembling at least one chip using a fabric, and fabric including a chip device

A method for assembling a device on two substantially parallel taut threads. The device includes an electronic chip and two substantially parallel grooves open on opposite sides of the device. The distance separating the grooves corresponds to the distance separating the threads. The device presents a penetrating shape along an axis perpendicular to the plane of the grooves, having a base at the level of the grooves and an apex of smaller size than the distance separating the threads. The method includes the steps consisting in placing the apex of the device between the two threads; in moving the device between the two threads resulting in the threads being separated from one another by the penetrating shape of the device; and in continuing movement of the device until the threads penetrate into the grooves reverting to their initial separation distance.

Electrode junction structure of semiconductor device

Semiconductor device and manufacturing method for the same

To improve an integration degree of a semiconductor device. The semiconductor device includes a plurality of wiring layers formed on the semiconductor substrate, a pad electrode formed on an uppermost wiring layer among the plurality of wiring layers, a base insulating film having a pad opening above the pad electrode, and a rewiring electrically connected to the pad electrode and extending over the base insulating film. Further, the semiconductor device includes a protective film covering an upper surface of the rewiring and having an external pad opening exposing part of the upper surface of the rewiring, an external pad electrode electrically connected to the rewiring through the external pad opening and extending over the protective film, and a wire connected to the external pad electrode. Part of the external pad electrode is located in a region outside the rewiring.

Wire bonding system for semiconductor component

The component contains a semiconductor element (1) coupled to a connecting frame (4) by a chip bonding material, and a metal wire (3a) connecting the frame to the semiconductor element. A bonding point between a contact spot (2) on the element a metal wire has a number of island-shaped bonding points, and a strip-shaped coupling point, surrounding the bonding point. Preferably the frame is of Cu as its main component, while the main component of the chip bonding material. The main component of the metal wire is Au, and that of the contact spot is Al.

Electronic device

The electronic device comprises a bond pad structure with a bond pad (14), an underlying metal layer (18) and a passivation layer (20) extending between the metal layer (18) and the bond pad (14), wherein the passivation layer (20) is perforated beneath the bond pad (14). Preferably, the perforations (34) are hexagonal to produce a hexagonal matrix. To reduce or avoid deformation of the matrix during bonding, the hexagons are oriented relative to the bond pad axis, for example at 15 degrees.

Evaluation of semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Method of wire bonding over active area of a semiconductor circuit

A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Semiconductor device and wire bonding method

A semiconductor device (2) includes: a FLR (65) that is disposed on a semiconductor substrate so as to divide the semiconductor substrate into an inner region and an outer region; a first bonding pad (24a to 24d) that is disposed in the inner region and is connected to an external circuit by a wire (14a to 14d) whose one end is connected to the external circuit; and a second bonding pad (26a to 26d) that is disposed in the outer region and on which the other end of the wire is bonded.

Semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Patent JPH0482183B2

Semiconductor device and method for producing semiconductor device

A semiconductor device includes: a substrate having an external electrode formed thereon, the external electrode being capable of being electrically connected to an outside; and a semiconductor element having a surface electrode formed thereon, the surface electrode being made from an electrically conducting paste, the semiconductor element being mounted on the substrate, the external electrode being electrically connected by wire bonding to the surface electrode via a connecting member. This provides (i) a semiconductor device including: a substrate having an external electrode capable of being electrically connected to an outside; and a semiconductor element having a surface electrode made from an electrically conducting paste, the semiconductor device allowing for assured bonding reliability and a simplified means or step of connecting the surface electrode to the external electrode, and (ii) a method for producing the semiconductor device.

Semiconductor device including a power device with first metal layer and second metal layer laterally spaced apart

A semiconductor device exhibits a first metal layer, made of a first metal, with at least one contiguous subsection. At least one second metal layer, made of a second metal, is placed on the contiguous subsection of the first metal layer. The second metal is harder than the first metal. The second metal layer is structured to form at least two layer regions, which are disposed on the contiguous subsection of the first metal layer. The second metal exhibits a boron-containing or phosphorus-containing metal or a boron-containing or phosphorus-containing metal alloy.

Method for assembling at least one chip using a fabric, and fabric including a chip device

The invention relates to a method for assembling a device on two substantially parallel, extended threads (18a, 18b). The device includes an electronic chip and two substantially parallel, open grooves (4a, 4b) on opposite sides of the device. The spacing of the grooves corresponds to the spacing of the threads. The device has a shape penetrating along an axis perpendicular to the plane of the grooves, said shape having a base on the grooves and a top (1) that is smaller than the spacing of the threads. The method includes the steps that involve: placing the top (1) of the device between both threads; moving the device between both threads, thus causing the threads to be spaced apart by the penetrating shape of the device; and continuing the movement of the device until the threads penetrate into the grooves while returning to the initial spacing thereof.

Circuit substrate for mounting a semiconductor element

A circuit substrate for mounting a semiconductor element having an aluminum-copper clad foil laminated on a metallic base plate by interposing an insulating layer, characterized in that the roughness in average of a surface of the aluminum foil included in the aluminum-copper clad foil, which surface is in contact with the insulating layer, is in a range of from 0.5 µm to 50 µm; and the roughness of another surface of the aluminum foil, which surface is opposite to said surface being in contact with the insulating layer, is 10 µm or less.

Semiconductor dicing and assembling method

To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.

Bond pad and process for fabricating the same

A bond pad of a semiconductor device and a process for fabricating the same are provided. On a semiconductor base is formed a plurality of disconnected insulation blocks that are defined by a plurality of channels. The disconnected insulation blocks are arranged in a grid or helix form. A barrier layer is formed over the disconnected insulation blocks and the semiconductor base. A conductive layer is formed over the disconnected insulation blocks to fill the channels, such that a topography of the conductive layer is similar to that of the underlying structure.

Method for fabricating stacked semiconductor components with through wire interconnects

A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer scale components, stacked components, or interconnect components for electrically engaging or testing other semiconductor components.

Semiconductor device and fabrication method thereof

A semiconductor device, in which, in order to prevent both a wiring layer (81) including a bonding pad (6, 80) of aluminum and a bonding wire (10) from corroding, the aluminium material has formed on its surface an aluminum oxide film (90, 12, 13). In the semiconductor device disclosed, a first aluminum oxide film (90, 91) is formed on the surface of an upper aluminum wiring (80, 81) underlying a final passivation film (27), and a second aluminum oxide film (12,13) is formed on both an exposed surface of a bonding pad (80) and the surface of a bonding wire (10). In order to ensure the high quality of the second aluminum oxide film (12, 13), the materials of the bonding pad and the bonding wire are made to have an identical ionization tendency, or all leads are short-circuited when the oxidization for the second oxide film is conducted. In order that electrical connection to the bonding pad may not be broken during the oxidization of the second oxide film, moreover, the bonding pad is made to have a stacked construction of two aluminum layers (6, 80). <IMAGE>

Bonding pad structure and method for making the same

Semiconductor device with pads of enhanced moisture blocking ability

A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.

Method of forming a semiconductor device with a contact pad on a sloped silicon dioxide surface

A technique for expanding an effective area in which a semiconductor structure required for a semiconductor device to function is desired. With the semiconductor device 2 of this invention, a pad 12 to be connected with a conductive wire 14 is sloping with respect to the surface of the semiconductor device 2 around the pad 12 and along a longitudinal direction of the conductive wire 14 . Consequently, the length of the pad 12 , when projecting the pad 12 onto the surface of the semiconductor device 2 , can be shortened. As a result, the area of the pad region 10 can be reduced and the effective area for forming a semiconductor structure can be enlarged.

A Semiconductor device and a method of manufacturing the same

배선의 본딩패드부와 본딩와이어의 볼부와의 접착성을 향상시켜 반도체장치의 신뢰성을 향상시킨다. The adhesion between the bonding pad portion of the wiring and the ball portion of the bonding wire is improved to improve the reliability of the semiconductor device. 반도체 기판상의 TiN막, Al막(M3b) 및 TiN막으로 이루어지는 제3층 배선상에 있어서, Al막(M3b)이 노출한 본딩패드부(BP)상에, 본딩와이어의 볼부(B)를 접착시킬 때, Al막(M3b)과 금볼부(B)와의 접속영역(d)과, Al막(M3b)과 금볼부(B)와의 사이에 형성되는 Al-Au 합금층(50)의 형성영역의 지름(g)과의 관계를, g≥0.8d로 하고, 접촉영역의 지름(d)과 금볼부(B)의 최대 외주 지름(D)과의 관계를 d≥0.8D로 한다. 그 결과, Al막(M3b)(제3층 배선)이 박막이라도, 금볼부(B)와의 접착성을 확보할 수 있고, 또한 쇼트 마진을 확보할 수 있다. On the third layer wiring consisting of the TiN film, the Al film M3b, and the TiN film on the semiconductor substrate, the ball portion B of the bonding wire is adhered to the bonding pad portion BP exposed by the Al film M3b. In the connection region d between the Al film M3b and the gold ball portion B and between the Al-Au alloy layer 50 formed between the Al film M3b and the gold ball portion B. The relationship between the diameter g is g≥0.8d, and the relationship between the diameter d of the contact area and the maximum outer diameter D of the gold ball part B is d≥0.8D. As a result, even if Al film M3b (third layer wiring) is a thin film, adhesiveness with the gold ball part B can be ensured, and a short margin can be ensured. 배선, 본딩와이어, 본딩패드, 반도체장치, 접착성, 신뢰성, 박막 Wiring, Bonding Wire, Bonding Pad, Semiconductor Device, Adhesiveness, Reliability, Thin Film

Integrated circuit package including wire bonds

It has been found that integrated packages having dies with at least 10 bonding pads separated by a pitch of 65 μm or less are susceptible to corrosion upon wire bonding to these pads and subsequent encapsulation in a passivating material. In particular, crevices are potentially formed between the bonding wire and bonding pad that are not passivated and that promote corrosion. Avoidance of crevice formation through, for example, appropriately choosing the bonding pad and wire configuration substantially avoids such corrosion.

Semiconductor device

Bond pad design

A bonding pad for an integrated circuit, where the bonding pad overlies a fragile dielectric layer. A lower metal layer stack overlies the fragile dielectric layer, and a hard dielectric layer overlies the lower metal layer stack. An upper metal layer stack overlies the hard dielectric layer, where the upper metal layer stack forms voids extending into the upper metal layer stack from an exposed upper surface of the upper metal layer stack. The voids define deformable protrusions in the upper surface of the upper metal layer stack, for at least partially absorbing forces applied to the bonding pad during a bonding operation. Electrically conductive vias extend from the lower metal layer stack through the hard dielectric layer to the upper metal layer stack, and electrically connect the lower metal layer stack to the upper metal layer stack.

Method for assembling at least one chip on a fabric, and fabric including a chip device

Semiconductor device and manufacturing method thereof

Semiconductor package and method of manufacturing the same

Provided are a semiconductor package and a method of manufacturing the semiconductor package, and more particularly, a semiconductor package with bonding wires and a method of manufacturing the semiconductor package. The semiconductor package includes a substrate including a finger, at least one semiconductor chip stacked on the substrate, the semiconductor chip including a chip pad, and a wire which electrically connects the finger with the chip pad, wherein one end of the wire bonds with an upper surface and lateral surfaces of the finger.

Patent JPS594853B2

Semiconductor device and manufacturing method thereof

本发明揭示一种半导体器件及其制造方法,包括在焊点(21)上形成格子状,在钝化层(22)的下面配置蚀刻阻挡层,在钝化层(22)和蚀刻阻挡层中、在焊点(21)上设置开口(23),在格子状的焊点(21)之间充满绝缘层(27),将焊接线与格子状的焊点(21)连接。

Semiconductor device including an insulating film and insulating pillars and manufacturing method of the semiconductor device

A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.

Semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Integrated circuit package including wire bonds

It has been found that integrated packages having dies with at least 10 bonding pads separated by a pitch of 65 μm or less are susceptible to corrosion upon wire bonding to these pads and subsequent encapsulation in a passivating material. In particular, crevices are potentially formed between the bonding wire and bonding pad that are not passivated and that promote corrosion. Avoidance of crevice formation through, for example, appropriately choosing the bonding pad and wire configuration substantially avoids such corrosion.

Semiconductor device and manufacturing method thereof

Method for forming metal pad of semiconductor device

본 발명은 패키징 공정에서 금속 패드의 벗겨짐(peel-off) 현상이 일어나는 것을 방지할 수 있는 반도체 소자의 금속 패드 형성방법을 개시하며, 개시된 본 발명의 방법은, 반도체 기판 상에 패드 형상으로 금속막을 형성하는 단계; 상기 금속막 상에 소정 두께로 층간절연막을 증착하는 단계; 상기 층간절연막의 소정 부분을 선택적으로 식각해서, 상기 층간절연막에 수 개의 비아홀을 형성하는 단계; 상기 비아홀 내에 금속막을 매립시켜, 금속 플러그를 형성하는 단계; 및 상기 금속 플러그의 소정 높이가 돌출되도록, 상기 층간절연막의 표면을 소정 두께만큼 식각하는 단계를 포함한다. The present invention discloses a method for forming a metal pad of a semiconductor device, which can prevent a peel-off phenomenon of a metal pad in a packaging process. The disclosed method of the present invention provides a method of forming a metal film in a pad shape on a semiconductor substrate. Forming; Depositing an interlayer insulating film with a predetermined thickness on the metal film; Selectively etching a predetermined portion of the interlayer insulating film to form several via holes in the interlayer insulating film; Embedding a metal film in the via hole to form a metal plug; And etching the surface of the interlayer insulating layer by a predetermined thickness so that a predetermined height of the metal plug protrudes.

Semiconductor bond pad structures and methods of manufacturing thereof

Described is a semiconductor device having improved semiconductor bond pad reliability and methods of manufacturing thereof. The semiconductor device includes a layer formed over an integrated circuit on a semiconductor substrate. The first layer includes a conductive portion and an insulating portion. A second layer is then formed over the first layer and includes a conductive portion corresponding to the first layer's conductive portion and an insulating portion corresponding to the first layer's insulating portion. A bond pad is then formed over the first and second layers such that the bond pad is substantially situated above the conductive portions and the insulating portions of the first and second layers. A bonding ball is then formed on the bond pad substantially above the conduction portion of the first and second layers.

Wire bonding method

<P>PROBLEM TO BE SOLVED: To provide a method for wire bonding using an Al wire suitable for a narrower pitch of wire and smaller bonding surface when correcting the bonding. <P>SOLUTION: A method for correcting a wire bonding comprises the steps of once removing a wire 30 which peels off from either of a first bonding surface 21 or a second bonding surface 11 when wire bonding between the surface 21 and the surface 11 by a wire 30 made up of Al, and wire bonding for the correction again. The correcting wire bonding is conducted so that a bonding surface 31 for the wire in the correction positions to the surfaces 11, 21 from which the wire 30 is removed in overlapping a bonded sign 50 corresponding to the removed wire, and the proportion of a region 31a overlapping the bonded sign 50 out of the bonding surface 31 for the wire in the correction is not more than 75%. <P>COPYRIGHT: (C)2004,JPO&amp;NCIPI

Process for enhanced intermetallic growth in IC interconnections

An apparatus (10) and method is provided for bonding wire (12) to the bond sites (28) of integrated circuits (14). In preferred embodiments a bond end (30) on gold wire (12) is bonded to aluminum bond pad (28). Apparatus (10) includes a high frequency ultrasonic energy source (20) designed to provide ultrasonic energy at frequencies from about 100 kHz to about 125 kHz. The ultrasonic energy is imparted to the bonding interface (32) via transducer (18) and capillary (16). The transducer (18) is modified in length and tool clamp point (40) is sited on transducer (18) so that the high frequency ultrasonic energy is at the antinodal point in its application to interface (32) and thus is optimized. In preferred embodiments of the process, the ultrasonic energy is applied at about 114 kHz. In this fashion, the bond formed between bond end (30) and bond pad (28) is optimized in terms of shear strength, bonding time and processing temperatures. Particularly beneficial results are noticed with respect to aluminum alloy bond pads such as Al, 2% Cu, which have been particularly troublesome in terms of intermetallic formation and bond strength in the prior art. Thus according to the invention, the use of high frequency ultrasonic energy in the aforementioned range, results in superior strength bonds formed with greater processing parameter flexibility.

Semiconductor device and method of manufacturing the same

In the present invention, the bonding pad is formed in a lattice-like shape. Directly underneath the passivation layer, the etching stopper layer is provided. An opening is made through the passivation layer and the etching stopper layer so as to expose the bonding pad. The cavity sections of the lattice-like shape of the bonding pad are filled with the insulating layer. The bonding wire is connected to the lattice-shaped bonding pad. With this structure, the bonding error of the device manufactured by the damascening process can be avoided.