HF-Frontend für ein Automobilradarsystem

Es wird eine Anordnung (1) für ein HF-Frontend eines linsenbasierten 77-GHz Automobilradarsystems beschrieben, aufweisend ein HF-Substrat (3) aufweisend eine Oberseite (3a) und eine Unterseite (3b), und einen Halbleiterchip (2), wobei der Halbleiterchip (2) auf der Oberseite (3a) des HF-Substrats (3) angeordnet ist, und wobei das HF-Substrat (3) ein mechanisch festes Material aufweist. Ferner wird ein Verfahren zur Herstellung einer Anordnung (1) für ein HF-Frontend eines linsenbasierten 77-GHz Automobilradarsystems sowie eine Verwendung einer Anordnung (1) für ein HF-Frontend in einem linsenbasierten 77-GHz Automobilradarsystem beschrieben.

Drucksensorgehäuse und Verfahren zu seiner Herstellung

Ein Drucksensorgehäuse (1) der vorliegenden Erfindung umfasst einen vertieft geformten Gehäusehauptkörper (20), in dessen Inneres ein Drucksensor (10) montiert ist, und einen Deckel (30) aus einem lichtabschirmenden Element, der den Gehäusehauptkörper (20) in einem Zustand abdeckt, in dem über der Membran (11) des Drucksensors (10) ein Innenraum (21) sichergestellt wird. Der Gehäusehauptkörper (20) und der Deckel (30) sind an mehreren Stellen abschnittsweise verklebt. In den anderen Bereichen zwischen dem Gehäusehauptkörper (20) und dem Deckel (30) außer den abschnittsweisen Verklebungen sind Zwischenräume (34) gebildet, die die Außenseite und den Innenraum (21) des Gehäusehauptkörpers (20) verbinden.

A method of manufacturing an integrated circuit package and an integrated circuit package

A method of manufacturing an integrated circuit package

CERAMIC SUBSTRATE FOR HYBRID MICROCIRCUITS AND METHOD OF MAKING THE SAME

SEMICONDUCTOR ARRANGEMENT.

Semiconductor device

CERAMIC SUBSTRATE WITH VIAS FILLED WITH METAL FOR MICRO-HYBRID CIRCUITS AND METHOD OF MANUFACTURE

BLACK BOX HAS VIA THERMICS AND MANUFACTORING PROCESS

Boîtier électronique et procédé de fabrication d'un tel boîtier, dans lesquels au moins un élément de transfert thermique (17) est interposé entre une face avant d'une puce de circuits intégrés (4) et une face arrière d'une plaque de transfert thermique (13) ; et un bloc d'encapsulation (19) présente une partie s'étendant entre la face avant de la puce de circuits intégrés et la face arrière de la plaque de transfert thermique (13) et dans laquelle est noyé ledit élément de transfert thermique (17).

Optical semiconductor device, has IC chip casing enclosing optical sensors

Dispositif semi-conducteur optique comprenant une puce de circuits intégrés présentant dans sa face avant un capteur optique, une plaque support sur une face avant de laquelle est fixée la face arrière de la puce et des moyens de connexion électrique de la puce à la plaque support, comprenant un anneau de protection (7) fixé sur la face avant de la puce (3), autour et à distance du capteur optique (6), et un anneau (13) en une matière d'enrobage entourant la périphérie de la puce et s'étendant entre la face avant de la plaque support (2) et ledit anneau de protection.

CIRCUIT CARRIER

ELECTRONIC COMPONENT

LED PACKAGE MODULE

SEMICONDUCTOR PACKAGE FOR BEING DIRECTLY MOUNTED IN THE SEMICONDUCTOR CHIP AND A METHOD OF FORMATION THEREOF

PURPOSE: It can be connected by an interposer even though the pad of memory device and the logic device or the bump's position is changed. The high speed operation can be implemented by the interposer even though the design change of the memory device and logic device. CONSTITUTION: The semiconductor package comprises a printed circuit board(10); the first semiconductor chip(20) having on the printed circuit board; the chip package having on the first semiconductor chip; the chip package directly contacts with the first semiconductor chip; the second semiconductor chip on interposer. The interposer has the penetrating electrode(110). The first semiconductor chip comprises the first bump pad(24) arranged in the upper side. The first bump(105) contacts with the first bump pad. The printed circuit board comprises the solder ball arranged to the lower surface. © KIPO 2009 ...

SEMICONDUCTOR HOUSING PACKAGE, SEMICONDUCTOR PACKAGE STRUCTURE INCLUDING THE SAME, AND PROCESSOR BASED SYSTEM INCLUDING THE SEMICONDUCTOR PACKAGE STRUCTURE CAPABLE OF IMPLEMENTING HIGH INTEGRATION

PURPOSE: A semiconductor housing package, a semiconductor package structure including the same, and a processor based system including the semiconductor package structure are provided to reduce the manufacturing costs of the processor based system by minimizing the use of a printed circuit board. CONSTITUTION: A housing chip(77) is surrounded with a mold layer(84) and is exposed from the mold layer. Rewiring patterns are extended from the mold layer to the housing chip. The rewiring patterns are electrically connected to the housing chip. A housing terminal is protruded from the rewiring patterns. A circuit board(3) is electrically connected to the housing terminals. COPYRIGHT KIPO 2012 ...

Attaching passive components to a semiconductor package

The present invention involves attaching passive components to a semiconductor package. The present invention provides a method including forming a conductive structure on the surface of a semiconductor die, attaching the semiconductor die to a substrate, forming a molding compound for packaging the semiconductor die, forming an opening on the molding compound to at least partially expose the conductive die, and coupling the passive components to the conductive structure through the opening on the molding compound. The description and claims below are intended to protect other embodiments.

Manufacturing method of package-on-package structure

Semiconductor device and the manufacturing method thereof

The present invention uses the block molding method for fixing the semiconductor chip on the wiring substrate through the adhesive material to eliminate the defect in the manufacturing of semiconductor device caused by flowing out of adhesive material. The present invention is a semiconductor device, which comprises: (a) a wiring substrate, which includes a main surface, an insulative film formed on the main surface, and an electrode exposed from the insulative film and formed on the main surface; (b) a semiconductor chip, fixed on the insulative film of the main surface of the layout substrate through the adhesive; (c) the wiring for connecting the electrode on the main surface of the wiring substrate and the electrode of semiconductor chip and having conductivity; and, (d) the packaging, covering the semiconductor chip, the main surface and electrode of the wiring substrate; (e) forming a trench between the semiconductor chip and the electrode; (f) the packaging and the wiring substrate ...

MICRO BALL FEEDING METHOD

Provided is a feeding method for feeding conductive balls to the insides of through holes of a mask reliably and efficiently so as to match a fine pitch. In the feeding method, a head (300), which can move over the surface of a feeding mask (200) and which is caused to give a directivity to micro balls (340) by a squeezee (310) for rotating around a feed port (320) to be fed with the micro balls (340), is used to feed the micro balls (340) to the insides of a plurality of through holes (210) formed in the feeding mask (200). At this time, the head (300) is moved while being oscillated, to feed the micro balls (340) to the insides of the through holes (210) while improving the probability, on which the micro balls (340) meet the through holes (210) of the feeding mask (200).

Apparatus and method for reducing signal cross talk between wire bonds of semiconductor packages

A semiconductor package for reducing signal cross talk between wire bonds of semiconductor packages by using a tier of input-output power bond pads between two tiers of signal bond pads. The package includes a substrate having a first surface and a second surface and a die attach area on the first surface of the substrate. A first tier of signal contacts is arranged around the periphery of the die attach on the first surface of the substrate. A second tier of signal contacts is arranged around the periphery of the die attach area on the first surface of the substrate. A power contact tier is also arranged around the periphery of the die attach area on the first surface of the substrate. The power contact tier is arranged between the first tier of signal contacts and the second tier of signal contacts to reduce signal noise and cross talk between the signal bond wires of the first tier and the second tier.

Optical or electronic module and method for its production

One or more aspects of the invention relate to an optical or electronic module with at least one optical or electronic component and a plastic package within which the component is embedded. The component has an operative region that facilitates operative connection with surroundings. The plastic package has a first region, which comprises a transparent polymer compound, and a second region, which comprises a non-transparent polymer compound. The first region extends such that it borders the operative region of the component.

SEMICONDUCTOR CHIP HAVING BOND PADS

In one embodiment, a semiconductor chip has one or more peripheral bond pads. The semiconductor chip comprises a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other; a bond pad-wiring pattern formed on at least a part of the peripheral region of the semiconductor substrate; a passivation layer formed on the bond pad-wiring pattern and exposed portions of the semiconductor substrate; a pad-rearrangement pattern disposed over the passivation layer and electrically connected to the bond pad-wiring pattern; and an insulating layer formed over the pad-rearrangement pattern. The insulating layer has an opening therein that exposes a portion of the pad-rearrangement pattern to define a bond pad. The bond pad is disposed over at least a part of the cell region.

High density wire bond pattern for integratd circuit package

An improved integrated circuit package having high density interconnections between die pads and a plurality of coplanar connector tabs on a selected metal layer in the integrated circuit package, wherein the pitch of the connector tabs is a predetermined multiple of the pitch of the die pads.

Coils integrated in IC-package

Method for providing at least one inductance associated with a chip attached to a support, in which the inductances are provided by means of at least a first bondwire having first and second ends. In which method the first end of the first bondwire is bonded to a first pad on the chip by means of an automated process using the chip as a reference for placing the first end of the first bondwire on the first pad when bonding it thereto. The second end of the first bondwire is bonded to a second pad on the support by means of the automated process using the chip as a reference for placing the second end of the first bondwire on the second pad when bonding it thereto.

Substrate for semiconductor package and method of making same

The present invention provides a substrate for a semiconductor and the semiconductor package, wherein with the setup that the conductive fingers around the chip of enclosure structure superposes with the electrical connecting element, the distance between the conductive fingers and the chip will be shortened, so as to effectively shorten the wires from the chip to the conductive fingers and reduce the materials and the processing time, in favor of cutting down the cost of production.

Semiconductor device and radio communication device

A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f and the first number is larger than the second number.

SEMICONDUCTOR MODULE AND IMAGE PICKUP APPARATUS

A semiconductor module including multiple semiconductor devices prevents a signal that flows through a bonding wire connected to one semiconductor device from acting as noise which affects the other semiconductor devices, thereby improving the operation reliability of the semiconductor module. A second semiconductor device layered on a first semiconductor device includes a current output electrode via which large current is output. The current output electrode is electrically connected to a substrate electrode provided to a first wiring layer via a bonding wire. The bonding wire is provided across the side E1 of the second semiconductor device. A bonding wire connected to the first semiconductor device is provided across a side of the first semiconductor device other than the side F1 that corresponds to the side E1 of the second semiconductor device, i.e., across the side F2, F3, or F4 of the first semiconductor device.

Stacked semiconductor structure and fabrication method thereof

A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.

Stacked microfeature devices and associated methods

Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device.

Submounts for Semiconductor Light Emitting Devices and Methods of Forming Packaged Light Emitting Devices Including Dispensed Encapsulants

A submount for mounting an LED chip includes a substrate, a die attach pad configured to receive an LED chip on an upper surface of the substrate, a first meniscus control feature on the substrate surrounding the die attach pad and defining a first encapsulant region of the upper surface of the substrate, and a second meniscus control feature on the substrate surrounding the first encapsulant region and defining a second encapsulant region of the upper surface of the substrate. The first and second meniscus control features may be substantially coplanar with the die attach pad. A packaged LED includes a submount as described above and further includes an LED chip on the die attach pad, a first encapsulant on the substrate within the first encapsulant region, and a second encapsulant on the substrate within the second encapsulant region and covering the first encapsulant. Method embodiments are also disclosed.

Micro universal serial bus memory package and manufacturing method the same

The present invention relates to a micro USB memory package and a method for manufacturing the same. The object of the present invention is to provide a micro USB memory package and a method for manufacturing the same, which can meet the USB standard specification, can have light, thin, short and small configuration, can have various applications, and can simply expand the memory capacity thereof. In order to accomplish the object of the present invention, there is disclosed a micro USB memory package, which comprises a substrate with a plurality of circuit patterns formed on the top surface thereof, at least one of passive elements connected with the circuit patterns of the substrate, at least one of controllers connected with the circuit patterns of the substrate, at least one of flash memories connected with the circuit patterns of the substrate, and an encapsulation part encapsulating the passive elements, the controllers and the flash memories on the substrate, and at least one of ...

Power Semiconductor Package Having Vertically Stacked Driver IC

In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier. 120-. (canceled)21. A semiconductor package comprising:a control carrier having a die side and an opposite input/output (I/O) side;a control FET attached to said die side of said control carrier;a driver integrated circuit (IC) for driving said control FET, said driver IC situated over said control FET and electrically coupled to said control FET by at least one conductive buildup layer.22. The semiconductor package of claim 21 , further comprising:a sync carrier having another die side and another opposite input/output (I/O) side;a sync FET attached to said another die side of said sync carrier.23. The semiconductor package of claim 21 , wherein said driver IC is electrically coupled to said at least one conductive buildup layer formed over said control carrier by bondwire.24. The semiconductor package of claim 21 , wherein said driver IC is flip chip mounted over said at least one conductive buildup layer.25. The semiconductor package of claim 21 , wherein said control FET comprises a silicon FET.26. The semiconductor package of claim 21 , wherein said control FET comprises a III-Nitride FET.27. A semiconductor package comprising:a sync carrier having a die side and an opposite input/output (I/O) side;a sync FET attached to said die side of said sync carrier;a driver integrated circuit (IC) for driving said sync FET, said driver IC situated over said sync FET and electrically ...

Circuit board and packaged chip

A circuit board includes an upper circuit and a lower surface that are opposite to each other, a plurality of heat sink bonding pads, and a plurality of heat sink conductive pads. The heat sink bonding pads are disposed on the upper surface and electrically insulated from one another, and are used to electrically connect to a heat sink. The heat sink conductive pads are disposed on the lower surface, electrically insulated from one another, and electrically connected to the heat sink bonding pads, respectively.

Adhesive Sheet, Semiconductor Device, and Process for Producing Semiconductor Device

An object of the present invention is to provide an adhesive sheet that can fill irregularities due to wiring of a substrate or a wire attached to a semiconductor chip, etc., does not form resin burrs during dicing, and has satisfactory heat resistance and moisture resistance. The present invention relates to an adhesive sheet comprising 100 parts by weight of a resin comprising 15 to 40 wt % of a high molecular weight component containing a crosslinking functional group and having a weight-average molecular weight of 100,000 or greater and a Tg of -50° C. to 50° C., and 60 to 85 wt % of a thermosetting component containing an epoxy resin as a main component, and 40 to 180 parts by weight of a filler, the adhesive sheet having a thickness of 10 to 250 mum.

METHOD FOR PRODUCING AN ELECTRICAL CONNECTION

COMPOSITE SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a composite semiconductor device being at GND (ground) potential where a capacitor is connected to the back of a semiconductor substrate 1 at low cost. SOLUTION: An electrode 9 of a thin capacitor 7 is connected to the back 2 being at GND potential of a p-type semiconductor substrate 1 by a conduction type DAF8 (Die Attach Film) or a conductive adhesive, and electrodes 5, 6 on the surface 3 of the p-type semiconductor substrate 1 and terminals 13, 16 of a thin type inductor 12 are connected by bumps 19, 20 each other to be laminated, thereby the, generation of noise is suppressed, a manufacturing cost can be reduced, and a mounting area can be decreased. COPYRIGHT: (C)2009,JPO&INPIT ...

Multilayer board

Elektronische Verdrahtungsstruktur

Gehäuse für Hochleistungsleuchtdioden - "1-Lagen-System"

Gehäuse zur Aufnahme eines opto-elektronischen Funktionselements (40), aus- einem Basiskörper (10) mit einer Oberseite (10a), die zumindest abschnittsweise einen Montagebereich (14) für wenigstens ein opto-elektronisches Funktionselement (40) definiert, so dass der Basiskörper (10) einen Kühlkörper für wenigstens ein opto-elektronisches Funktionselement (40) bildet, einer Unterseite (10b) und einem Rand (10c); und- wenigstens einem Anschlusskörper (30, 30-1, 30-2) für wenigstens ein opto-elektronisches Funktionselement (40), welcher mit dem Basiskörper (10) verbunden ist, wobei- der Basiskörper (10) wenigstens einen Kanal (11, 11-1, 11-2) aufweist, in welchem der wenigstens eine Anschlusskörper (30, 30-1, 30-2) zumindest abschnittsweise angeordnet ist und welcher zumindest abschnittsweise mit einem Glas (20) zum Verbinden des Basiskörpers (10) mit dem Anschlusskörper (30, 30-1, 30-2) befüllt ist, wobei der wenigstens eine Kanal (11, 11-1, 11-2) in die Oberseite (10a) des Basiskörpers (10 ...

Method of forming substrates

A substrate is formed by moulding a composition comprising a particulate material (e.g. alumina) and a binder to provide a planar mounting area for a heat producing element (2) (e.g. an integrated circuit chip) and a heat sink aperture (9) directly below the mounting area. The binder is then at least partly removed and the substrate sintered. A fluid may be circulated through the heat sink aperture (9) or a heat pipe system may be utilised. Conductive tracks (24) may be provided by moulding grooves in the substrate which are further filled with a conductive ink before firing. The grooves enable connecting wires (3) to cross the tracks (24) without the risk of short circuiting. A method of making a mould of reduced size from a master is described in which the uniform shrinkage of a ceramic when fired is used in a sequence of replicating steps. ...

INTEGRATED SWITCHING CONFIGURATION WITH STACKED LEADER LAYERS FOR CONNECTING CIRCUIT ELEMENTS.

SEMICONDUCTOR DEVICE

COATED BOND WIRES FOR DIE PACKAGES AND METHODS OF MANUFACTURING SAID COATED BOND WIRES

The present invention relates to a bond wire having a metal core (202), a dielectric layer (200, 204), and a ground connectable metallization (206), wherein the bond wire has one or more vapor barrier coatings. Further, the present invention relates to a die package with at least one bond wire according to the invention.

Multilayer wiring board, method for manufacturing such multilayer wiring board, and semiconductor device and electronic device using multilayer wiring board

半导体器件

... 本发明涉及BGA型半导体器件，由于电源或接地布线短，减少了电感，可能实现高速化和高集成化的半导体器件。总之，本发明涉及BGA型半导体器件，把电源或者接地的布线设置在BGA基板中央附近，可能使其实现高速化和高集成化。而且，利用该半导体器件，可使电子电路和电子装置实现高速化和功能复杂化。 ...

Semiconductor device and manufacturing method of semiconductor device

ELECTRONIC DEVICE HAVING AN INTEGRATED LEAD AND METHOD OF MANUFACTURE

Boitier pour le montage en surface d'un composant fonctionnant en hyperfrequences

L'invention concerne un boitier CMS apte au fonctionnement en hautes et tres hautes frequences. Ce boitier comprend une embase isolante 1, en ceramique, sur une face de laquelle sont deposees des metallisations 4, 5 pour le report d'un composant 6 et de ses fils de connexions 7. En vue d'avoir les liaisons electriques les plus courtes possibles, les connexions exterieures sont prises par des trous metallises 2, 3 a travers l'embase 1. Les metallisations des deux faces 4, 5 et 8, 9 sont appairees et en contact avec les trous metallises qui les reunissent deux a deux. Detrompage par dissymetrie des metallisations 8 ou de l'embase 17. Le boitier est ferme par enrobage 10 ou capot 11. Application au montage de circuits hybrides hyperfrequences.

INTEGRATED CIRCUIT PACKAGE SYSTEM FOR SHIELDING ELECTROMAGNETIC INTERFERENCE

... 집적회로 패키지 방법은, 기판을 제공하는 단계와; 상기 기판에 집적회로를 연결하는 단계와; 상기 집적회로 주위에 차폐 부재를 장착하는 단계와; 상기 차폐 부재 바로 위에 전도성 차폐층을 부착하는 단계와; 시스템 상호접속부를 상기 차폐 부재에 연결하는 단계를 포함한다.

ELECTRONIC DEVICE CAPABLE OF PREVENTING THE WARP OF A PACKAGE AND IMPROVING HEAT DISSIPATION PERFORMANCE

PURPOSE: An electronic device is provided to improve heat dissipation performance and to prevent the warp of a package. CONSTITUTION: An electronic device includes a body(2), an electronic device(1), a first heat dissipation layer, a thermal via, and a second electric heat layer. The body is made of a ceramic material. A first insulating layer is arranged on the body. The electronic device is arranged on the first insulating layer which is made of a metal material. The first heat dissipation layer is formed on the center of the lower part of the body. The thermal via is buried inside the body and connects the first insulating layer to the first heat dissipation layer. COPYRIGHT KIPO 2011 ...

Semiconductor structure and method of fabricating the same

The invention discloses a semiconductor structure. The semiconductor structure includes a first signal layer, a second signal layer, a wiring layer and at least one via. The wiring layer is formed between the first signal layer and the second signal layer. A conducting wire is disposed between a first terminal and a second terminal of the wiring layer. At least one via is utilized to conduct the first signal layer and the second signal layer. Wherein at least one via is disposed approached the first terminal and the second terminal.

Carbon nanotube-solder composite structures for interconnects, process of making same, packages containing same, and systems containing same

A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die, an interposer-type structure for a flip-chip, a mounting substrate, or a board. The CNT array is patterned by using a patterned metallic seed layer on the substrate to form the CNT array by chemical vapor deposition. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.

Semiconductor package and method of forming same

Wafer level integration package

Reducing cracking by adjusting opening size in pop packages

A package includes a device die, a molding material molding the device die therein, and a surface dielectric layer at a surface of the package. A corner opening is in the surface dielectric layer. The corner opening is adjacent to a corner of the package. An inner opening is in the surface dielectric layer. The inner opening is farther away from the corner of the package than the corner opening. The corner opening has a first lateral dimension greater than a second lateral dimension of the inner opening.

SEMICONDUCTOR DEVICE

There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip. With respect to an arrangement of the plurality of data system bonding pads of the data processor chip, an arrangement of the data system bonding pads to which the memory chip, coupled by the data system wiring, corresponds is made such that memory chips ...

Integrated circuit package structure with heat dissipating design

An integrated circuit (IC) package structure with heat dissipation design. The IC chip is disposed on a package substrate and a power ring structure surrounds the chip. Due to the relatively large surface area of the power ring structure near the high heat zone of the IC chip, the contact area between the power ring structure and package substrate is enlarged. The power ring structure is connected to the isoelectric conductive layer of a multi-layer circuit board via an electric connection path, thereby enhancing heat dissipation.

Arrangement for energy conditioning

Circuit arrangement embodiments that use relative groupings of energy pathways that include shielding circuit arrangements that can sustain and condition electrically complementary energy confluences.

Light emitting device and method for producing same

There is provided a light emitting device highly resistant to the environment, and having good heat resistance, light resistance and gas barrier property, and a method for producing same. With the light emitting device, a substrate 2 and interconnect patterns 5A, 5B formed on the surface thereof are covered with an acrylic resin primer 10 having better gas barrier property than a silicone resin sealing resin part 3. Light resistance is ensured by the silicone resin sealing resin portion 3 and the gas barrier property can be ensured by the acrylic resin primer 10.

Structure and method for fabrication of a leadless chip carrier

Structure and method for fabrication of a leadless chip carrier have been disclosed. A disclosed embodiment comprises a substrate having a top surface for receiving a semiconductor die. The disclosed embodiment also comprises a printed circuit board attached to a bottom surface of the substrate. The disclosed embodiment further comprises at least one via in the substrate, which provides an electrical connection between a signal bond pad of the semiconductor die and the printed circuit board. The at least one via also electrically connects a substrate bond pad and the printed circuit board. The substrate bond pad is further connected to the signal bond pad of the semiconductor die by a signal bonding wire. The at least one via further provides an electrical connection between the signal bond pad of the semiconductor die and a land that is electrically connected to the printed circuit board.

Semiconductor package having optimized wire bond positioning

Closely-spaced bonding wires may be used in a variety of different packaging applications to achieve improved electrical performance. In one embodiment, two adjacent bonding wires within a wire grouping are closely-spaced if a separation distance D between the two adjacent wires is met for at least 50 percent of the length of the shorter of the two adjacent wires. In one embodiment, the separation distance D is at most two times a diameter of the wire having the larger diameter of the two adjacent wires. In another embodiment, the separation distance D is at most three times a wire-to-wire pitch between the two adjacent wires. Each wire grouping may include two of more closely-spaced wires. Wire groupings of closely-spaced bonding wires may be used to form, for example, power-signal-ground triplets, signal-ground pairs, signal-power pairs, or differential signal pairs or triplets.

Direct via wire bonding and method of assembling the same

A method for electrically connecting an integrated circuit to a via in a substrate is disclosed. The method can include deforming a ball over the via to form a bump and attaching a bond wire to the bump. The method also can include attaching the bond wire to the integrated circuit, such as by forming an end of the bond wire into a second ball and deforming the second ball over the integrated circuit. Alternatively, the method can include forming an end of the bond wire into a ball and deforming the ball over the via. Embodiments of a disclosed integrated circuit and substrate assembly can include, for example, a bump aligned with at least a portion of a via in a substrate and a bond wire attached to the integrated circuit and the bump. Other embodiments can include a via with a top metal cap and an upper plating.

Semiconductor package

A semiconductor package is provided which includes a substrate having a plurality of semiconductor dice mounted thereon. The substrate is divided into segments by grooves formed in the bottom surface of the substrate. Each semiconductor die is electrically connected to the substrate by electrical connections which extend from bond pads on the semiconductor die to corresponding bond pads on the substrate. An encapsulant is formed over each segment and contains grooves which correspond to the grooves of the substrate. Break points are thus formed at the grooves to permit the segments to be easily detached from the substrate to form individual integrated circuits.

IC Package with Integrated Waveguide Launcher

Embodiments described herein include an integrated circuit (IC) device. For example, the IC device can include a substrate configured to be coupled to a printed circuit board (PCB), an IC die attached to the substrate, and a waveguide launcher formed on the substrate. The waveguide launcher is electrically coupled to the IC die through the substrate.

METHOD OF FABRICATING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE

A method of fabricating a semiconductor package includes preparing a panel package including a redistribution substrate, a connection substrate and a plurality of lower semiconductor chips; sawing the panel package to form a plurality of separated strip packages each of which includes the sawed redistribution substrate, at least two of the lower semiconductor chips, and the sawed connection substrate; and providing a plurality of upper semiconductor chips on one of the strip packages to electrically connect the upper semiconductor chips to the sawed connection substrate.

Electronic interconnect structure and method for manufacturing it

Ball grid array package for an integated circuit and method of reducing ground bounce

КОРПУСИРОВАННАЯ ИНТЕГРАЛЬНАЯ СХЕМА, СОДЕРЖАЩАЯ СОЕДИНЕННЫЙ ПРОВОЛОЧНЫМИ ПЕРЕМЫЧКАМИ МНОГОКРИСТАЛЬНЫЙ ПАКЕТ

Варианты настоящего изобретения направлены на создание корпусированной интегральной схемы (IC), содержащей первый кристалл интегральной схемы, по меньшей мере частично встроенный в первый герметизирующий слой, и второй кристалл интегральной схемы, по меньшей мере частично встроенный во второй герметизирующий слой. Первый кристалл может содержать первое множество структур межсоединений на уровне кристалла, расположенных на первой стороне первого герметизирующего слоя. Эта корпусированная IC может также содержать множество электрических маршрутных элементов, по меньшей мере частично встроенных в первый герметизирующий слой и конфигурированных для маршрутизации электрических сигналов между первой стороной и второй стороной первого герметизирующего слоя. Вторая сторона слоя может быть противоположной относительно первой стороны указанного слоя. Второй кристалл может иметь вторую группу из нескольких структур соединений на уровне кристалла, которые могут быть электрически соединены по меньшей ...

Metall-Platte für Lasermarkierung

Package, das Folgendes umfasst:ein erstes Package (100), das Folgendes umfasst:einen Chip (102);eine Formmasse (120), in der der Chip (102) gegossen ist,mehrere Umverteilungsleitungen (116), die über dem Chip (102) und der Formmasse (120) liegen;eine Lasermarkierungs-Platte (128), die mit einer der mehreren Umverteilungsleitungen (116) koplanar ist, wobei die Lasermarkierungs-Platte (128) und die eine der mehreren Umverteilungsleitungen (116) aus einem gleichen leitenden Material ausgebildet sind;eine Polymerschicht (131) über der Lasermarkierungs-Platte (128) und den mehreren Umverteilungsleitungen (116);ein Adhäsionsband (133) über der Polymerschicht (131); undeine Lasermarkierung (132), die das Adhäsionsband (133) und die Polymerschicht (131) durchstößt, wobei die Lasermarkierung (132) sich zu einer oberen Fläche der Lasermarkierungs-Platte (128) erstreckt.

Multilayer wiring board, method for manufacturing such multilayer wiring board, and semiconductor device, and electronic device using multilayer wiring board

INTEGRATED CIRCUIT DEVICE HAVING STACKED CONDUCTIVE LAYERS CONNECTING CIRCUIT ELEMENTS THERETHROUGH

INTEGRATED CIRCUIT DEVICE HAVING STACKED CONDUCTIVE LAYERS CONNECTING CIRCUIT ELEMENTS THERETHROUGH An integrated circuit (IC) device including a stacked layer unit (11) having a plurality of stacked layers (11-1 to 11-6) each having an insulation layer (11-1b) and at least one conductive layer strip (11-1a) formed on a surface of the insulation layer, and at least one chip (3) mounted on the top of the insulation layer and having a plurality of circuit elements. The IC device also includes at least one first conductive member (13) formed in the stacked layer unit, having a low inductance for first signals applied thereto and operatively connecting the first signals to be transferred between the circuit elements; at least one second conductive member (14) formed in the stacked layer unit, having a higher inductance for the first signals than that of the first conductive member and operatively connecting second signals to be transferred between the circuit elements; and, a package (21 to ...

REINFORCED WAFER LEVEL PACKAGE COMPRISING A CORE LAYER FOR REDUCING STRESS IN A SOLDER JOINT AND IMPROVING SOLDER JOINT RELIABILITY

Reducing Cracking by Adjusting Opening Size in Pop Packages

By adjusting the opening in the PoP package to reduce the size of the cracks

Semiconductor device

Semiconductor device

Semiconductor packaging part and method for manufacturing same

CERAMICS SUBSTRATE WITH INTERCONNECTIONS BETWEEN LAYERS FILLED WITH METAL FOR MICROCIRCUITS HYBRID AND MANUFACTORING PROCESS

PACKAGE-ON-PACKAGE SECURE MODULE HAVING BGA MESH CAP

패키지-온-패키지(POP_안전 모듈은 BGA 메시 캡, 제 1 BGA 패키지, 및 제 2 BGA 패키지를 포함한다. 제 1 BGA 패키지는 제 1 집적 회로(예를 들어, 탬퍼 검출 로직을 포함하는 마이크로제어기)를 포함한다. 제 2 BGA 패키지는 제 2 집적 회로(예를 들어, 메모리)를 포함한다. 제 2 BGA 패키지는 제 1 BGA 패키지에 피기백 방식으로 장착되고, BGA 메시 캡은 제 2 BGA 패키지에 피기백 장착된다. BGA 메시 캡의 인쇄 회로 기판 부재는 삽입된 안티-탬퍼 메시를 포함한다. 이 메시는 모듈 내에 보호 방식으로 제 1 집적 회로에 접속된다. 모듈이 사용될 때, 밑에 있는 인쇄 회로 기판 내에 삽입된 메시는 BGA 캡 메시에 결합되어 양쪽 안티-탬퍼 메시들은 탬퍼 검출 로직에 의해 제어된다. The package-on-package (POP_safe module includes a BGA mesh cap, a first BGA package, and a second BGA package. The first BGA package includes a first integrated circuit (e.g., a microprocessor including tamper detection logic The second BGA package is piggyback mounted on the first BGA package, and the BGA mesh cap is mounted on the second BGA (not shown) The printed circuit board member of the BGA mesh cap includes an embedded anti-tamper mesh that is connected to the first integrated circuit in a protected manner within the module. When the module is used, the underlying print The mesh inserted into the circuit board is coupled to the BGA cap mesh so that both anti-tamper meshes are controlled by the tamper detection logic.

Semiconductor apparatus having system-in-package arrangement with improved heat dissipation

The present invention provides a semiconductor apparatus that has a system-in-package form and an effective configuration of heat dissipation. The apparatus of the present invention comprises a substrate providing a first surface, a second surface and a plurality of via-holes filled with metal and connecting the first and second surfaces. A semiconductor device and other electronic components are provided on the first surfaces. The semiconductor device is mounted on a metal sheet that is in contact with a portion of the plurality of via-holes. The semiconductor device, electronic components and the metal sheet are molded with resin. Heat generated by the semiconductor device can be dispersed to the metal sheet, transmitted to via-holes and effectively dissipated to an outside of the apparatus.

Integrated packaged having magnetic components

A packaged device is obtained using an innovative package approach that allows integration of miniature planar magnetics into standard low-cost semiconductor packages (BGA, PDIP, SOIC, etc.) with electronic and electrical components, where those components can be C&W and/or SMD types. The packaged device includes a planar magnetic substrate having first and second dielectric layers, the first dielectric layer having a first winding defined thereon, the second dielectric layer having a second winding defined thereon. A magnetic component is provided in the substrate. A package material provided at least partly around the substrate and the magnetic component to protect the substrate and magnetic component. The magnetic component is an inductor or transformer. The packaged device further includes at least one semiconductor component provided on the first dielectric layer.

Method for direct attachment of an on-chip bypass capacitor in an integrated circuit

Switching noise at integrated circuit VDD and VSS metal traces is reduced by minimizing lead inductance in on-chip bypass capacitors. For each on-chip bypass capacitor, a pair of VDD -carrying and VSS -carrying metal traces is formed, these traces having regions spaced-apart laterally a distance ΔX corresponding to lateral separation of the bypass capacitor connecting pads. For each bypass capacitor, column-shaped openings, spaced-apart distance ΔX, are formed through the passivation and inter-metal oxide layers, as needed. These openings expose and access regions of the pair of spaced-apart metal traces carrying VSS and VDD. These openings, which may be formed after the IC has been fabricated, preferably are formed using focussed ion beam technology ("FIB"). Alternatively, these openings may be formed using masking and etching steps. The column-shaped openings are then made into conductive columnar elements, preferably using FIB deposition of tungsten or platinum. Conductive element pads ...

Electronic modules with integral sensor arrays

An electronic module includes multiple stacked bare IC chips ("a stack") and a sensor assembly that is mechanically coupled to an end surface of the stack. Electrical connection between the sensor assembly and the stack is provided by a metallization layer disposed on a side-surface of the stack. Specifically, wiring of the sensor assembly extends to an edge surface thereof corresponding to the side-surface of the stack where it electrically connects to the side-surface wiring. The IC chips of the stack are similarly electrically connected to the side-surface wiring. Multiple sensors (e.g., CCD arrays) may be electrically and mechanically coupled to multiple surfaces of the stack for providing a, e.g., multi-view imaging module. Multiple electrical and mechanical options exist for the connection of sensors to stacks within electronic modules.

Semiconductor device and circuit board used therein

A semiconductor chip having electrode terminals arranged in an area-array manner is mounted on an upper surface of a first region of a circuit board. Bonding pads are provided on the upper surface of a second, different region of the circuit board, and are connected to electrode terminals on the upper surface of the chip with bonding wires covered with an electro-insulation coating. External connection terminals provided on an opposing surface of the second region of the circuit board in an area-array manner are electrically connected to the bonding pads by conductive vias provided through the circuit board in the thickness direction. An electro-insulation film covers the chip, including the bonding wire/electrode terminal connections, and the upper surface of the second region of the circuit board. An electro-conductive resin encapsulates the coated bonding wires and the electro-insulation film.

Semiconductor package device and method for fabricating the same

Disclosed are a semiconductor package device and a method for fabricating the semiconductor package device. The semiconductor package has a semiconductor chip including a plurality of bonding pads having a microscopic size and aligned at a minute interval, a planar layer formed on the semiconductor chip so as to expose the bonding pads, metal patterns formed on the planar layer and having a size larger than a size of the bonding pads in such a manner that at least some parts of the metal patterns are connected to the bonding pads and a seed metal layer interposed between the planar layer and the metal patterns. When the bonding pads have microscopic size and aligned at a minute interval, a wire-bonding process is carried out by using the metal patterns having the size larger than the size of the bonding pads and covering the bonding pad region, as a connection part to the bonding pads. Thus, the bonding pad region is reduced by 50 to 80% so that the number of chips in the semiconductor ...

Nickel bonding cap over copper metalized bondpads

A method for forming a nickel cap layer over copper metalized bond pad is disclosed in which the phosphorous content of the nickel cap, and particularly the surface of the nickel cap, may be controlled. The phosphorous content of the surface of the nickel cap is suitably determined such that oxidation is inhibited. The resulting nickel cap may be wire-bonded directly, without the deposition of a gold cap layer.

Printed wiring board and method for manufacturing the same

A printed wiring board includes an interlayer resin insulation layer having a penetrating hole for a via conductor, a conductive circuit formed on one surface of the interlayer resin insulation layer, a via conductor formed in the penetrating hole and having a protruding portion protruding from the other surface of the interlayer resin insulation layer, and a surface-treatment coating formed on the surface of the protruding portion of the via conductor. The via conductor is connected to the conductive circuit and has a first conductive layer formed on the side wall of the penetrating hole and a plated layer filling the penetrating hole.

Structure for a radio frequency power amplifier module within a radio frequency power amplifier package

A RF power amplifier module comprises a die with a RF power transistor and the RF power transistor comprises a control terminal, a transistor output terminal and a transistor reference terminal. The RF power amplifier module further comprises a module input terminal, a module output terminal and at least two module reference terminals being electrically coupled to the control terminal, the transistor output terminal and the transistor reference terminal, respectively. The RF power amplifier module further comprises an electrically isolating layer and a heat conducting element. The die is in thermal contact with the heat conducting element via the electrically isolating layer in order to transfer heat during operation of the RF power transistor to the heat conducting element.

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure including a redistribution structure, a die, a plurality of conductive structures, a first insulating encapsulant, a chip stack, and a second insulating encapsulant. The die is disposed on and electrically connected to the redistribution structure. The conductive structures are disposed on and electrically connected to the redistribution structure. The conductive structures surround the die. The first insulating encapsulant encapsulates the die and the conductive structures. The first insulating structure includes a plurality of openings exposing top surfaces of the conductive structures. The chip stack is disposed on the first insulating encapsulant and the die. The chip stack is electrically connected to the conductive structures. The second insulating encapsulant encapsulates the chip stack.

COMPENSATING FOR MEMORY INPUT CAPACITANCE

Methods, systems, and devices for compensating for memory input capacitance. Techniques are described herein to alter the capacitance of an access line coupled with a plurality of memory cells. The capacitance of the access line may be filtered by an inductive region, which could be implemented in one or more individual signal paths. Thus a signal may be transmitted to one or more selected memory cells and the inductive region may alter a capacitance of the access line in response to receiving a reflection of the signal from an unselected memory cell. In some examples, the transmitted signal may be modulated using pulse amplitude modulation (PAM), where the signal may be modulated using a modulation scheme that includes at least three levels to encode more than one bit of information (e.g., PAM4).

CHIP PACKAGE

A chip package includes a first wiring layer, chips, a second wiring layer, dielectric layers, first conductive vias, and second conductive vias. The first wiring layer has contacts near a side of the first wiring layer. The chips are stacked over the first wiring layer. The second wiring layer is stacked over the first wiring layer. The dielectric layers are disposed between the first wiring layer, the chips, and the second wiring layer. The first conductive vias are inside at least one of the dielectric layer for electrically connecting the chip to the second wiring layer. The second conductive vias are inside at least one of the dielectric layers for electrically connecting the second wiring layer to the first wiring layer.

Semiconductor chip package

A structure of a semiconductor chip package is provided. The semiconductor chip package includes: a substrate; a semiconductor chip mounted on a first surface of the substrate; a plurality of electrode pads on a second surface, different from the first surface, of the substrate; and an electrostatic discharge protection pad overlapping a portion of a first electrode pad and a portion of a second electrode pad among the plurality of electrode pads.

MULTI CHIP PACKAGE

The preferred embodiment of the present invention can prevent signal distortions such as stress, or the like, occurring at the time of power delivery due to the difference in the lengths of the metal wires for electrically connecting each of the plurality of semiconductor chips formed on the dual die package substrate.

Chip-Stacked Package Structure

A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, a patterned circuit layer and a second chip. The substrate has a first surface and an opposite second surface. The first chip with a first active area and an opposite first rear surface is electrically connected to first surface of substrate by a flip chip bonding process. The patterned circuit layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned circuit layer has a second active area and a plurality of second pads formed on the second active area, wherein the second bonding pad is electrically connected to the patterned circuit layer.

Semiconductor package structure and method for manufacturing the same

A method for manufacturing a semiconductor package structure includes: (a) disposing at least one semiconductor element on a conductive structure, wherein the conductive structure includes at least one insulation layer and at least one circuit layer; (b) disposing an encapsulant on the conductive structure to cover the semiconductor element; (c) attaching a supporting structure on the conductive structure to surround the semiconductor element; and (d) disposing an upper element on the encapsulant, wherein a coefficient of thermal expansion of the upper element is in a range of variation less than or equal to about ±20% of a coefficient of thermal expansion of the circuit layer, and a bending modulus of the upper element is in a range of variation less than or equal to about ±35% of a bending modulus of the circuit layer.

Manufacturing method of semiconductor device

In the manufacture of a semiconductor device by adopting a block molding method wherein a semiconductor chip is fixed onto a wiring substrate through an adhesive, the occurrence of a defect caused by flowing-out of the adhesive is to be prevented. The semiconductor device according to the present invention comprises a wiring substrate, the wiring substrate having a main surface, an insulating film formed on the main surface, and electrodes formed on the main surface so as to be exposed from the insulating film, a semiconductor chip fixed through an adhesive onto the insulating film formed on the main surface of the wiring substrate, conductive wires for connecting the electrodes on the main surface of the wiring substrate and electrodes on the semiconductor chip with each other, and a seal member, i.e., a package, which covers the semiconductor chip, the main surface of the wiring substrate and the electrodes, wherein a groove is formed between the semiconductor chip and the electrodes and the seal member and the wiring substrate have side faces cut by dicing. A protruding portion of the adhesive (an insulating resin) stays within the groove without getting over the groove and does not reach the electrodes. The groove is formed by removing the insulating film partially in the full depth direction of the film so as to extend through the film.

Schaltungsmodul und Schaltungsvorrichtung, die ein Schaltungsmodul umfasst

Schaltungsmodul, mit: einer plattenartigen Platine (1), die eine Mehrzahl von Verbindungselektroden (6) aufweist, die in peripheren Abschnitten einer ersten Hauptoberfläche der plattenartigen Platine (1) angeordnet sind; und einer rahmenartigen Platine (10), die eine Mehrzahl von Verbindungselektroden (12) aufweist, die auf einer ersten Hauptoberfläche der rahmenartigen Platine (10), die der ersten Hauptoberfläche der plattenartigen Platine (1) zugewandt ist, angeordnet sind, wobei die auf der ersten Hauptoberfläche der rahmenartigen Platine (10) angeordnete Mehrzahl von Verbindungselektroden (12) der in den peripheren Abschnitten der ersten Hauptoberfläche der plattenartigen Platine (1) angeordneten Mehrzahl von Verbindungselektroden (6) entspricht, wobei die Mehrzahl von Verbindungselektroden (6) auf der plattenartigen Platine (1) und die Mehrzahl von Verbindungselektroden (12) auf der rahmenartigen Platine (10) durch leitfähige Verbindungsmaterialien (20) zwischen denselben elektrisch ...

Short power signal path integrated circuit package

Led package and method for manufacturing the same

An LED package includes a substrate, an LED chip, a bounding dam, and a first encapsulation. The substrate includes a first surface and a second surface opposite to the first surface. The LED chip is mounted on the first surface of the substrate. The bounding dam is formed on the first surface of the substrate and surrounds the LED chip. The bounding dam and the substrate cooperatively define a receiving space. The bounding dam is made of thermoset resin. The first encapsulation is formed in the receiving space and encloses the LED chip.

Chip package and fabricating method thereof

A chip package and a fabrication method thereof are provided. The chip package includes a substrate and a chip disposed over the substrate. A solder layer is disposed between the chip and the substrate. A conductive pad is disposed between the solder layer and the substrate, wherein the conductive pad includes a first portion disposed under the solder layer, a second portion disposed away from the first portion and a connective portion disposed between the first portion and the second portion. The connective portion has a width which is narrower than a width of the first portion along a first direction perpendicular to a second direction extending from the first portion to the connective portion.

Semiconductor package device with a heat dissipation structure and the packaging method thereof

The present invention provide a heat dissipation structure on the active surface of the die to increase the performance of the heat conduction in longitude direction of the semiconductor package device, so that the heat dissipating performance can be improved when the semiconductor package device is associated with the exterior heat dissipation mechanism.

Led lighting assembly

A LED lighting assembly includes a substrate defining a body and a central hole surrounded by the body, a conductive mass positioned in the central hole of the substrate, a LED chip defining a bottom attached to the conductive mass, and a shell mounted on the body and forming a room together with the body.

Electronic device and method for producing a device

An electronic device or devices and method for producing a device is disclosed. One embodiment provides an integrated component, a first package body and a contact device. The contact device penetrates the package body.

Impedence controlled packages with metal sheet or 2-layer rdl

A microelectronic assembly includes an interconnection element, a conductive plane, a microelectronic device, a plurality of traces, and first and second bond elements. The interconnection element includes a dielectric element, a plurality of element contacts, and at least one reference contact thereon. The microelectronic device includes a front surface with device contacts exposed thereat. The conductive plane overlies a portion of the front surface of the microelectronic device. Traces overlying a surface of the conductive plane are insulated therefrom and electrically connected with the element contacts. The traces also have substantial portions spaced a first height above and extending at least generally parallel to the conductive plane, such that a desired impedance is achieved for the traces. First bond element electrically connects the at least one conductive plane with the at least one reference contact. Second bond elements electrically connect device contacts with the traces.

Electronic device

An electronic device comprising a laminate comprising pluralities of insulator layers each provided with conductor patterns, and an amplifier-constituting semiconductor device mounted to a mounting electrode formed on an upper surface of the laminate, a first ground electrode being formed on an insulator layer near an upper surface of the laminate; a second ground electrode being formed on an insulator layer near a lower surface of the laminate; the first ground electrode being connected to the mounting electrode through pluralities of via-holes; conductor patterns constituting the first circuit block being disposed in a region below the amplifier-constituting semiconductor device between the first ground electrode and the second ground electrode; and at least part of a conductor pattern for a line connecting the first circuit block to the amplifier-constituting semiconductor device being disposed on an insulator layer sandwiched by the mounting electrode and the first ground electrode.

SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME

A semiconductor device package includes a semiconductor device, a non-semiconductor substrate over the semiconductor device, and a first connection element extending from the semiconductor device to the non-semiconductor substrate and electrically connecting the semiconductor device to the non-semiconductor substrate. 1. A semiconductor device package , comprising:a semiconductor device;a non-semiconductor substrate over the semiconductor device; anda first connection element extending from the semiconductor device to the non-semiconductor substrate and electrically connecting the semiconductor device to the non-semiconductor substrate.2. The semiconductor device package of claim 1 , further comprising a patterned insulation layer between the semiconductor device and the non-semiconductor substrate.3. The semiconductor device package of claim 2 , wherein the non-semiconductor substrate comprises a through hole claim 2 , the first connection element extending from the semiconductor device into the through hole.4. The semiconductor device package of claim 3 , further comprising a second connection element in the through hole of the non-semiconductor substrate and surrounding the first connection element.5. The semiconductor device package of claim 4 , wherein the second connection element at least partially fills the through hole thereby forming a space between the semiconductor device claim 4 , the patterned insulation layer claim 4 , and the non-semiconductor substrate.6. The semiconductor device package of claim 2 , wherein the first connection element comprises solder material.7. The semiconductor device package of claim 1 , wherein the non-semiconductor substrate further comprises a patterned conductive layer on a surface away from the semiconductor device.8. The semiconductor device package of claim 1 , wherein the non-semiconductor substrate is narrower than the semiconductor device claim 1 , the first connection element extending from the semiconductor device ...

METHODS OF MAKING SEMICONDUCTOR DEVICE PACKAGES AND RELATED SEMICONDUCTOR DEVICE PACKAGES

Methods of making semiconductor device packages may involve providing a fan out wafer including semiconductor-device-package locations. Each semiconductor-device-package location may include at least two mutually spaced semiconductor dice and a dielectric material laterally surrounding each of the dice and extending between adjacent semiconductor-device-package locations. Electrically conductive traces may extend over active surfaces of the dice and laterally beyond peripheries of the dice over the dielectric material to locations of electrically conductive vias extending from the electrically conductive traces through the dielectric molding material. Semiconductor dice may be stacked on a side of at least some semiconductor-device-package locations of the fan out wafer opposite the electrically conductive traces. The stacks of semiconductor dice may be electrically connected to electrically conductive vias of the at least some semiconductor-device-package locations. The semiconductor-device-package locations having stacks of semiconductor dice thereon may be singulated from the fan out wafer. 1. A method of fabricating a semiconductor device package , comprising: at least two mutually spaced semiconductor dice and a dielectric material laterally surrounding each of the at least two mutually spaced semiconductor dice and extending between adjacent semiconductor-device-package locations;', 'electrically conductive traces extending over active surfaces of the at least two semiconductor dice and laterally beyond peripheries of the at least two semiconductor dice over the dielectric material to locations of electrically conductive vias extending from the electrically conductive traces through the dielectric molding material;, 'providing a fan out wafer comprising semiconductor-device-package locations, each semiconductor-device-package location comprisingstacking semiconductor dice on a side of at least some semiconductor-device-package locations of the fan out wafer ...

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a microelectronic device includes attaching a microelectronic die to a support member by forming an attachment feature on at least one of a back side of the microelectronic die and the support member. The attachment feature includes a volume of solder material. The method also includes contacting the attachment feature with the other of the microelectronic die and the support member, and reflowing the solder material to join the back side of the die and the support member via the attachment feature. In several embodiments, the attachment feature is not electrically connected to internal active structures of the die.

SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING MULTIPLE SHINGLED STACKS OF SEMICONDUCTOR DIES

A semiconductor device assembly includes a substrate having a plurality of external connections, a first shingled stack of semiconductor dies disposed directly over a first location on the substrate and electrically coupled to a first subset of the plurality of external connections, and a second shingled stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first shingled stack and the second shingled stack. 1. A method of making a memory device , comprising:providing a substrate;stacking a first plurality of semiconductor dies on the substrate in a first shingled stack;stacking a second plurality of semiconductor dies on the substrate in a second shingled stack;wirebonding, subsequent to stacking the first and second shingled stacks, the first and second pluralities of semiconductor dies to the substrate; andproviding an encapsulant to at least partially encapsulate the substrate, the first shingled stack and the second shingled stack.2. The method of claim 1 , wherein the wirebonding is performed in a single operation uninterrupted by any stacking.3. The method of claim 2 , wherein:the first plurality of semiconductor dies is stacked directly over a first location on the substrate, andthe second plurality of semiconductor dies is stacked directly over a second location on the substrate.4. The method of claim 2 , further comprising:stacking a third plurality of semiconductor dies in a third shingled stack;stacking a fourth plurality of semiconductor dies in a fourth shingled stack; andwirebonding, subsequent to stacking the third and fourth shingled stacks, the third and fourth pluralities of semiconductor dies to the substrate.5. The method of claim 4 , wherein wirebonding the first and second pluralities of semiconductor dies to ...

Semiconductor device and method of manufacturing semiconductor device

In one example, a semiconductor structure comprises a redistribution structure comprising a conductive structure, a cavity substrate on a top side of the redistribution structure and having a cavity and a pillar contacting the redistribution structure, an electronic component on the top surface of the redistribution structure and in the cavity, wherein the electronic component is electrically coupled with the conductive structure, and an encapsulant in the cavity and on the top side of the redistribution structure, contacting a lateral side of the electronic component, a lateral side of the cavity, and a lateral side of the pillar. Other examples and related methods are also disclosed herein.

Semiconductor package, semiconductor device using the same and manufacturing method thereof

A semiconductor package includes a substrate, a first electronic component, a first conductive layer, a first pillar layer and a first package body. The first electronic component is disposed on the substrate. The first pillar layer connects the first conductive layer and the substrate. The first package body encapsulates the first conductive layer, the first pillar layer and the first electronic component. The first conductive layer is embedded in the first package body.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

In a semiconductor device (SP) according to an embodiment, a solder resist film (first insulating layer, SR) which is in contact with the base material layer, and a resin body (second insulating layer, ) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (CR) of a wiring substrate and a semiconductor chip (). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved. 1. A semiconductor device comprising:a wiring substrate including a base material layer, a terminal formed on a first surface of the base material layer, and an insulating layer formed on the first surface such that the insulating film covers a first portion of the terminal, and such that the insulating film exposes a second portion of the terminal;a semiconductor chip including a front surface, a bonding pad formed on the front surface, and a projecting electrode formed on the bonding pad, and mounted over the wiring substrate such that the front surface faces the first surface of the wiring substrate via the projecting electrode;a solder material located between the second portion of the terminal and the projecting electrode; anda resin body located between the wiring substrate and the semiconductor chip, and sealing a connection part between the projecting electrode and the terminal,wherein the insulating film has an opening in which the second portion of the terminal is exposed,wherein, ...

UNIVERSAL BGA SUBSTRATE

A universal substrate for assembling ball grid array (BGA) type integrated circuit packages has a non-conducting matrix, an array of conducting vias extending between top and bottom surfaces of the matrix, and one or more instances of each of two or more different types of fiducial pairs on the top surface of the matrix. Each instance of each different fiducial pair indicates a location of a different via sub-array of the substrate for a different BGA package of a particular package size. The same substrate can be used to assemble BGA packages of different size, thereby avoiding having to design a different substrate for each different BGA package size. 1. A substrate for ball grid array (BGA) packages , the substrate comprising:a non-conducting matrix having a top surface and a bottom surface;an array of conducting vias extending between the top and bottom surfaces of the matrix;one or more instances of a first fiducial pair on the top surface of the matrix, wherein each instance of the first fiducial pair indicates a location of a different via sub-array for a different BGA package of a first package size; andone or more instances of a second fiducial pair, different from the first fiducial pair, on the top surface of the matrix, wherein each instance of the second fiducial pair indicates a location of a different via sub-array for a different BGA package of a second package size different from the first package size.2. The substrate of claim 1 , wherein the via sub-array for at least one instance of the first fiducial pair overlaps the via sub-array for at least one instance of the second fiducial pair.3. The substrate of claim 1 , wherein the one or more instances of the first fiducial pair have a uniquely different design from the design of the one or more instances of the second fiducial pair.4. The substrate of claim 1 , wherein the matrix comprises multiple instances of the first fiducial pair that all have the same design.5. The substrate of claim 1 , ...

WAFER-LEVEL PACKAGING USING WIRE BOND WIRES IN PLACE OF A REDISTRIBUTION LAYER

An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material. 1. A microelectronic package , comprising:a microelectronic die having a first surface and a second surface opposite the first surface;a plurality of wire bond wires with proximal ends thereof coupled to the first surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from the first surface of the microelectronic die; anda portion of the plurality of wire bond wires extending outside a perimeter of the microelectronic die into a fan-out (“FO”) region.2. The microelectronic package according to claim 1 , further comprising:a molding material for covering the first surface and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material; andinterconnects coupled to the distal ends of the plurality of wire bond wires.3. The microelectronic package according to claim 2 , further comprising:a substrate;wherein the second surface of the microelectronic die is coupled to a surface of the substrate; andwherein the molding material covers a portion of the surface of the ...

ROD-BASED SUBSTRATE WITH RINGED INTERCONNECT LAYERS

An embodiment includes an apparatus comprising: a rod-shaped substrate including a rod long axis; a first layer, including a first interconnect, substantially surrounding the substrate in a first plane that is orthogonal to the rod long axis; and a second layer, including a second interconnect, substantially surrounding the first layer in the first plane. Other embodiments are described herein. 1. An apparatus comprising:a rod-shaped substrate including a rod long axis;a first layer, including a first interconnect, substantially surrounding the substrate in a first plane that is orthogonal to the rod long axis; anda second layer, including a second interconnect, substantially surrounding the first layer in the first plane.2. The apparatus of claim 1 , wherein:the first layer has a first maximum diameter in the first plane; andthe second layer includes a second maximum diameter, in the first plane, which is greater than the first maximum diameter.3. The apparatus of wherein the first interconnect includes (a)(i) a first copper pad claim 1 , and (a)(ii) a first via with a layer of copper along inner walls of the first via.4. The apparatus of wherein:the first via includes first portion having a first width and a second portion having a second width that is less than the first width; andthe second portion is between the first portion and the substrate.5. The apparatus of wherein:the second interconnect comprising a second via; anda plane that intersects the rod long axis and the first via does not intersect the second via.6. The apparatus of comprising a first package comprising a processor and memory and at least one of the processor or the memory are configured to electronically couple to the first via.7. The apparatus of wherein:the first package comprises first and second interconnect bumps;the first plane intersects the first and second interconnect bumps; andthe first interconnect bump includes a first maximum width and the second interconnect bump includes a ...

PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a system comprises a semiconductor component including an interposer substrate, a microelectronic die over the interposer substrate, and a connection structure composed of a volume of solder material between the interposer substrate and the microelectronic die. The connection structure can include at least one of (a) a single, unitary structure covering approximately all of the back side of the microelectronic die, and (b) a structure electrically isolated from internal active features of the microelectronic die. In some embodiments, the connection structure can be positioned to provide generally consistent stress distribution within the system. 1. A system , comprising: an interposer substrate including a plurality of first terminals;', 'a microelectronic die having an active side, a back side opposite the active side and facing toward the interposer substrate, integrated circuitry, and a plurality of second terminals at the active side and electrically coupled to the integrated circuitry, and wherein the second terminals at the active side of the microelectronic die are electrically coupled to corresponding first terminals of the interposer substrate with a plurality of wire bonds; and', 'a connection structure composed of a volume of solder material between the interposer substrate and the microelectronic die, wherein the connection structure is attached to both the interposer substrate and the back side of the microelectronic die,', 'wherein the connection structure includes at least one of (a) a single, unitary structure covering approximately all of the back side of the microelectronic die, and (b) a structure electrically isolated from internal active features of the microelectronic die., 'at least one of a processor and a memory device, wherein at least one of the processor and the memory device includes a semiconductor component ...

STACKED MICROFEATURE DEVICES AND ASSOCIATED METHODS

Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device. 1. A method for forming a microfeature device package , comprising:positioning a first microfeature device at least proximate to a second microfeature device, the first microfeature device having a first bond pad surface with a first bond pad, the second microfeature device having a second bond pad surface with a second bond pad and an intermediate bond pad electrically connected to the second bond pad, the first bond pad surface facing toward the second bond pad surface;coupling a wirebond between the first bond pad and a package connection site; anddisposing an electrically conductive member between the first bond pad and the intermediate bond pad.2. The method of wherein disposing an electrically conductive member includes disposing a volume of solder between the first bond pad and the intermediate bond pad.3. The method of wherein disposing an electrically conductive member includes disposing at least one of a gold stud bump claim 1 , a copper stud bump claim 1 , and a solder bump.4. The method of claim 1 , further ...

Semiconductor packages including a plurality of upper semiconductor devices on a lower semiconductor device

Semiconductor packages are provided. The semiconductor packages may include an upper package including a plurality of upper semiconductor devices connected to an upper package substrate. The semiconductor packages may also include a lower package including a lower semiconductor device connected to a lower package substrate. The upper and lower packages may be connected to each other.

ELECTRONIC DEVICE PROVIDED WITH AN INTEGRAL CONDUCTIVE WIRE AND METHOD OF MANUFACTURE

An electronic device includes a supporting substrate having a front mounting face and an electrical connection network. An integrated circuit chip is mounted to the mounting face and is electrically connected to the electrical connection network. A primary encapsulation block embeds the integrated circuit chip and extends above and around the integrated circuit chip on the mounting face of the supporting substrate. An opening is provided in the primary encapsulation block to at least partially uncover an electrical contact. An additional wire made from an electrically conductive material has an end that is electrically connected to the electrical contact. An additional encapsulation block above the primary encapsulation block embeds the additional wire. 1. An electronic device , comprising:a supporting substrate having a mounting face and including an electrical connection network,an integrated circuit chip mounted on said mounting face of the supporting substrate and electrically connected to said electrical connection network,an encapsulation block including a primary encapsulation block in which the integrated circuit chip is embedded and which extends above and around the integrated circuit chip on said mounting face of the supporting substrate and an additional encapsulation block above the primary encapsulation block; andat least one additional wire made from an electrically conductive material embedded in said additional encapsulation block, said additional conductive wire being electrically connected to at least one of said integrated circuit chip and said electrical connection network.2. The device according to claim 1 , wherein one end of the additional conductive wire is connected to an electrical contact on said mounting face of said supporting substrate at a distance from the periphery of the integrated circuit chip.3. The device according to claim 1 , wherein one end of the additional conductive wire is connected to at least one electrical contact on a ...

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes a substrate including wiring at a surface thereof, a semiconductor element on a surface of the substrate, a first solder resist on the wiring, a bonding wire connecting the wiring and the semiconductor element, and a second solder resist. The first solder resist has an opening region at which a part of the wiring is non-covered by the first solder resist, and the bonding wire connects the wiring and the semiconductor element in the opening region. The second solder resist at least partially covers the non-covered part of the wiring in the opening region.

SEMICONDUCTOR CHIP PACKAGE HAVING OPTICAL INTERFACE

A semiconductor package including: a chip including a pad; an optical device including a pad; a mold configured to encapsulate the optical device and the chip; a wiring pattern configured to electrically connect the optical device and the chip; and an external connection terminal configured to electrically connect the semiconductor package to the outside. The chip includes at least one of: an amplifier circuit configured to process an electrical signal supplied from the optical device; and a driver circuit configured to supply the electrical signal to the optical device. 1. A semiconductor package comprising:a chip including a pad;an optical device including a pad;a mold configured to encapsulate the optical device and the chip;a wiring pattern configured to electrically connect the optical device and the chip; andan external connection terminal configured to electrically connect the semiconductor package to the outside.2. The semiconductor package of claim 1 , wherein the mold is a transparent mold claim 1 ,wherein the outside of the semiconductor package and the optical device communicate with each other using an optical signal passing through the transparent mold.3. The semiconductor package of claim 1 , wherein an opening into which an optical cable for supplying an optical signal is inserted is formed in the mold.4. The semiconductor package of claim 1 , wherein the chip comprises at least one of:an amplifier circuit configured to process an electrical signal supplied from the optical device; anda driver circuit configured to supply the electrical signal to the optical device.5. The semiconductor package of claim 1 , wherein the semiconductor package comprises a plurality of chips claim 1 ,wherein the plurality of chips comprise at least one of:a chip including an amplifier circuit; anda chip including a driver circuit.6. The semiconductor package of claim 1 , wherein the semiconductor package further comprises a chip configured to perform at least one signal ...

STACKED DIE PACKAGE

Disclosed is a package-on-package (PoP) assembly comprises a two-tiered windowed ball grid array (BGA) and a system on a chip (SoC) package. Window openings in the two tiers of the BGA are of different sizes to allow for wirebond landing pads on the first tier. A DRAM die is mounted to the BGA flipped over (i.e., wirebond pads facing the BGA package.) The DRAM die is wirebonded through the window in the BGA. For multi-channel systems and higher memory capacity, the DRAM die will have low-cost through-silicon vias (TSVs) that connect to stacked DRAM die(s). The stacked DRAM dies may be offset or rotated to align active TSVs with passive TSVs thereby enabling unique connections to certain DRAM dies in the stack. 1. An integrated circuit package , comprising:a first integrated circuit die having a first integrated circuit layout; and,a second integrated circuit die having a second integrated circuit layout, the second integrated circuit layout including a plurality of active through-silicon vias and a plurality of passive through-silicon vias, the first integrated circuit stacked on the second integrated circuit to align a plurality of active through-silicon vias on said first integrated circuit with a corresponding plurality of passive through-silicon vias on said second integrated circuit.2. The integrated circuit package of claim 1 , wherein said first integrated circuit layout and said second integrate circuit layout are the same.3. The integrated circuit package of claim 1 , wherein with respect to the plurality of active through-silicon vias on said first integrated circuit and a corresponding plurality of active through-silicon vias on said second integrated circuit claim 1 , said first integrated circuit layout and said second integrate circuit layout are the same.4. The integrated circuit package of claim 3 , wherein with respect to the passivation openings on both sides of the die claim 3 , the said first integrated circuit layout and said second integrate ...

Manufacturing method of package-on-package structure

A manufacturing method of a POP structure including at least the following steps is provided. A first package structure is formed and a second package structure is formed on the first package structure. The first package structure includes a circuit carrier and a die disposed on the circuit carrier. Forming the first package structure includes providing a conductive interposer on the circuit carrier, encapsulating the conductive interposer by an encapsulant and removing a portion of the encapsulant and the plate of the conductive interposer. The conductive interposer includes a plate, a plurality of conductive pillars and a conductive protrusion respectively extending from the plate to the circuit carrier and the die. The conductive protrusion disposed on the die, and the conductive pillars are electrically connected to the circuit carrier. The second package structure is electrically connected to the first package structure through the conductive interposer.

Semiconductor package and semiconductor device using the same

A semiconductor package includes a substrate, a first electronic component, a first conductive layer, a first pillar layer and a first package body. The first electronic component is disposed on the substrate. The first pillar layer connects the first conductive layer and the substrate. The first package body encapsulates the first conductive layer, the first pillar layer and the first electronic component. The first conductive layer is embedded in the first package body.

Package structure and manufacturing method thereof

A package structure and a manufacturing method thereof are provided. The package structure includes a circuit carrier, a substrate, a die, a plurality of conductive wires and an encapsulant. The substrate is disposed on the circuit carrier and includes a plurality of openings. The die is disposed between the circuit carrier and the substrate. The conductive wires go through the openings of the substrate to electrically connect between the substrate and the circuit carrier. The encapsulant is disposed on the circuit carrier and encapsulates the die, the substrate and the conductive wires.

Chip package structure and manufacturing method thereof

A chip package structure including a substrate, a first chip, a frame, a plurality of first conductive connectors, a first encapsulant, and a package is provided. The first chip is disposed on the substrate. The first chip has an active surface and a back surface opposite to the active surface, and the active surface faces the substrate. The frame is disposed on the back surface of the first chip and the frame has a plurality of openings. The first conductive connectors are disposed on the substrate and the first conductive connectors are disposed in correspondence to the openings. The first encapsulant is disposed between the substrate and the frame and encapsulates the first chip. The package is disposed on the frame and is electrically connected to the substrate via the first conductive connectors.

COATED BOND WIRES FOR DIE PACKAGES AND METHODS OF MANUFACTURING SAID COATED BOND WIRES

A bond wire having a metal core, a dielectric layer, and a ground connectable metallization, wherein the bond wire has one or more vapor barrier coatings. Further, the present invention relates to a die package with at least one bond wire according to the invention. 1. A lead having a metal core , a dielectric layer at least partially surrounding the metal core , the dielectric in turn being at least partially surrounded by a ground connectable metal coating , wherein that the lead further has at least one vapor barrier coating for protecting areas that are not covered by metal.2. (canceled)3. The lead of claim 1 , wherein the metal coating surrounds the dielectric layer only partially.4. The lead of claim 1 , wherein the lead includes additional metal layers and/or additional dielectric layers.5. The lead of claim 1 , wherein the lead has multiple layers of dielectric of varying thickness claim 1 , which are separated by thin metal layers claim 1 , with the outermost layer being connected to ground.6. The lead of claim 1 , wherein a high performance dielectric providing a superior vapor barrier and/or oxygen degradation resistance is thinly deposited over a thick layer of another dielectric material.7. A die package comprisinga die having a plurality of connection pads;a die substrate supporting a plurality of connection elements; andone or more leads according to any of the preceding claims connected between the die and the die substrate.8. The die package of claim 7 , wherein the lead includes a first metal core with a defined core diameter claim 7 , a dielectric layer surrounding the first metal core having a first dielectric thickness claim 7 , an outer metal layer at least partially surrounding the dielectric layer claim 7 , and a vapor barrier overcoat.9. The die package of any of claim 7 , wherein the die is overmolded claim 7 , cured claim 7 , and/or singulated for use.10. A method of manufacturing the die package including a die having a plurality of ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

According to one embodiment, a semiconductor device includes a plurality of stacked semiconductor chips each of which has a first surface having an electrode formed thereon, a plurality of wires each of which has one end portion connected to each of the electrodes of the plurality of semiconductor chips and extends in a stacking direction of the semiconductor chips, a sealing resin that covers the plurality of semiconductor chips, has a second surface having recesses formed therein, and is formed so that the other end portions of the plurality of wires and the recesses overlap each other when viewed from the stacking direction, and a plurality of terminals that is provided so as to fill the recesses, each of which has one end portion connected to the other end portion of each of the plurality of wires and has the other end portion exposed from the sealing resin. 1. A semiconductor device comprising:a plurality of semiconductor chips stacked, each of the semiconductor chips having a first surface on which an electrode is formed;a plurality of wires, each of the wires having one end portion connected to each of the electrodes of the plurality of semiconductor chips and extends in a stacking direction of the semiconductor chips;a sealing resin that covers the plurality of semiconductor chips, has a second surface in which a recess is formed, and is formed so that the recess overlaps other end portion of each of the plurality of wires when viewed in the stacking direction; anda plurality of terminals that is provided to fill the recess, each of the terminals having one end portion connected to the other end portion of each of the plurality of wires, and other end portion exposed from the sealing resin.2. The semiconductor device according to claim 1 , whereinother end portion of each of the plurality of terminals is connected to a redistribution layer provided on the second surface side of the sealing resin.3. The semiconductor device according to claim 1 , further ...

SEMICONDUCTOR CHIP PACKAGE HAVING OPTICAL INTERFACE

A semiconductor package includes a chip having a first surface and a second surface; a mold configured to encapsulate the chip; a vertical conductive channel electrically connected to a pad formed on the second surface of the chip while passing through the mold; a wiring pattern electrically connected to a pad formed on the first surface of the chip and configured to perform electrical connection in the package; an optical device arranged on a surface of the semiconductor package to be electrically connected to the vertical conductive channel; and an external connection terminal configured to electrically connect the semiconductor package to the outside. 132-. (canceled)33. A semiconductor package comprising:a chip including a pad formed on a first surface thereof;a via-substrate including a via;a mold configured to encapsulate the chip and the via-substrate;a vertical conductive channel connected to the via while passing through the mold;an optical device arranged on a surface of the semiconductor package to be electrically connected to the vertical conductive channel;a wiring pattern configured to electrically connect the via and the pad to each other; andan external connection terminal configured to electrically connect the semiconductor package to the outside.34. The semiconductor package of claim 33 , wherein the chip comprises at least one of:an amplifier circuit configured to process an electrical signal supplied from the optical device; anda driver circuit configured to supply the electrical signal to the optical device.35. The semiconductor package of claim 33 , wherein the semiconductor package comprises a plurality of chips claim 33 ,wherein the plurality of chips comprise at least one of:a chip including an amplifier circuit; anda chip including a driver circuit.36. The semiconductor package of claim 33 , further comprising at least one signal processing chip.37. The semiconductor package of claim 33 , wherein the mold is a hardened epoxy mold compound ( ...

Via structures having tapered profiles for embedded interconnect bridge substrates

Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

Semiconductor device assemblies including multiple shingled stacks of semiconductor dies

A semiconductor device assembly includes a substrate having a plurality of external connections, a first shingled stack of semiconductor dies disposed directly over a first location on the substrate and electrically coupled to a first subset of the plurality of external connections, and a second shingled stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first shingled stack and the second shingled stack.

Semiconductor Device and Method of Forming Microelectromechanical Systems (MEMS) Package

A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure. 1. A method of making a semiconductor device , comprising:providing a first semiconductor die;disposing a modular interconnect structure adjacent to the first semiconductor die;depositing a first encapsulant over the first semiconductor die and modular interconnect structure;forming a build-up interconnect structure over the first semiconductor die, modular interconnect structure, and first encapsulant; anddisposing a second semiconductor die including a microelectromechanical system (MEMS) over the first semiconductor die opposite the build-up interconnect structure.2. The method of claim 1 , further including forming a bond wire extending from the second semiconductor die to the modular interconnect structure.3. The method of claim 2 , further including disposing a lid on the modular interconnect structure and extending over the second semiconductor die and bond wire.4. The method of claim 2 , further including depositing a ...

Integrated circuit package system

An integrated circuit package system includes a substrate, a plurality of leads, N semiconductor devices, N first heat sinks, an encapsulating body, a second heat sink and a plurality of heat-dissipating fins protruding upward from the second heat sink, where N is a natural number. The leads are formed on a lower surface of the substrate. Each of the semiconductor devices is attached on an upper surface of the substrate, and includes a plurality of bonding pads which each is electrically connected to the corresponding lead. Each first heat sink is thermally coupled to a first top surface of the corresponding semiconductor device. The encapsulating body is formed to cover the substrate, the N semiconductor devices and the N first heat sinks such that the leads are exposed. The second heat sink is mounted on the encapsulating body, and is thermally coupled to the N first heat sinks.

Package on packages and mobile computing devices having the same

A package on package may include: a first printed circuit board (PCB); a bottom package which includes a first chip die and a second chip die attached to the first PCB; a top package which includes a second PCB and a third chip die attached to the second PCB, and is overlaid over the bottom package; and/or first stack connection solder balls and second stack connection solder balls which are electrically connected between the first PCB and the second PCB, and are formed only around two sides facing each other among sides of the bottom package.

Package structure and manufacturing method thereof

A package structure including a redistribution structure, a die, at least one connecting module, a first insulating encapsulant, a chip stack, and a second insulating encapsulant. The die is disposed on and electrically connected to the redistribution structure. The connecting module is disposed on the redistribution structure. The connecting module has a protection layer and a plurality of conductive bars. The conductive bars are embedded in the protection layer. The protection layer includes a plurality of openings corresponding to the conductive bars. The first insulating encapsulant encapsulates the die and the connecting module. The chip stack is disposed on the first insulating encapsulant and the die. The chip stack is electrically connected to the connecting module. The second insulating encapsulant encapsulates the chip stack.

PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE

A printed circuit board (PCB) includes an insulating layer with an upper surface and a lower surface opposite to the upper surface; a first conductive pattern on the upper surface of the insulating layer; a second conductive pattern on the lower surface of the insulating layer; an aluminum pattern that covers at least a portion of an upper surface of the first conductive pattern; and a first passivation layer that covers at least a portion of sides of the first conductive pattern and that prevents diffusion into the first conductive pattern. 1. A method for manufacturing a printed circuit board (PCB) , comprising the steps of:providing a carrier substrate that includes a carrier layer, a release layer, and an aluminum layer;forming a first conductive layer on the carrier substrate;forming a insulating layer and a second conductive layer on the first conductive layer;forming contact plugs that penetrate into the insulating layer and that electrically connect the first conductive layer and the second conductive layer;separating the carrier layer and the aluminum layer from each other by separating the release layer into two sublayers, wherein a first sublayer remains with the carrier layer and a second sublayer remains with the aluminum layer,removing the separated carrier layer and the first sublayer of the release layer;forming an aluminum pattern, a first conductive pattern, and a second conductive pattern by respectively patterning the aluminum layer the first conductive layer, and the second conductive layer, and removing the second sublayer of the release layer from the aluminum layer,forming a first solder resist layer and a second solder resist layer respectively on an upper surface of the insulating layer and a lower surface of the insulating layer opposite to the upper surface, wherein the first solder resist layer includes at least one opening that exposes a part of the first conductive pattern and a part of the aluminum pattern; andforming a first ...

ATTACHING PASSIVE COMPONENTS TO A SEMICONDUCTOR PACKAGE

Embodiments of the present disclosure provide a method comprising forming an electrically conductive structure on a surface of a semiconductor die, attaching the semiconductor die to a substrate, forming a molding compound to encapsulate the semiconductor die, forming an opening in the molding compound, the opening to at least partially expose the electrically conductive structure, and electrically coupling a passive component to the electrically conductive structure through the opening in the molding compound. Other embodiments may be described and/or claimed. 1. A method comprising:forming (i) a first electrically conductive structure formed on an active surface of the semiconductor die and (ii) a second electrically conductive structure formed on the active surface of the semiconductor die, and wherein the first electrically conductive structure provides (i) a power connection for the semiconductor die, or (ii) a ground connection for the semiconductor die;attaching the semiconductor die to a substrate;forming a single molding compound disposed to substantially encapsulate both the substrate and the semiconductor die, including substantially encapsulating the active surface of the semiconductor die, wherein the molding compound has a channel formed in the molding compound;forming an opening in the molding compound, wherein the channel (i) extends from the active surface of the semiconductor die to the opening on the molding compound and (ii) at least partially includes the second electrically conductive structure formed on the active surface of the semiconductor die;attaching a passive component to the molding compound at least partly over the opening on the exterior surface of the molding compound; andelectrically coupling the passive component to the active surface of the semiconductor die via the second electrically conductive structure through the channel in the molding compound.2. The method of claim 1 , wherein the second electrically conductive structure ...

INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK

Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires. 1. A method of forming an integrated circuit (IC) package comprising:providing a first encapsulation layer having a first die and a plurality of electrical routing features at least partially embedded therein, the first die having a first plurality of die-level interconnect structures that are disposed at a first side of the first encapsulation layer, wherein the electrical routing features electrically couple the first side of the first encapsulation layer with a second side of the first encapsulation layer, and wherein the first side of the first encapsulation layer is disposed opposite the second side of the first encapsulation layer;coupling a second die with a second side of the first encapsulation layer, wherein the second die includes a second plurality of die-level interconnect structures;electrically coupling the second plurality of die-level interconnect structures with at least a subset of the plurality of electrical routing features by bonding wires; andforming a second encapsulation layer over the second die and the wire-bonding configuration to encapsulate at least a ...

Semiconductor packages, methods of fabricating the same, memory cards including the same and electronic systems including the same

A semiconductor package includes a package substrate having a cavity therein and a second internal contact portion, a semiconductor die disposed in the cavity of the package substrate and having a first internal contact portion, a bonding wire connecting the first internal contact portion to the second internal contact portion, and an encapsulation part covering surfaces of the semiconductor die and the package substrate and providing an opening that exposes a first external contact portion of the bonding wire. Related memory cards and related electronic systems are also provided.

Fabrication method of semiconductor package without chip carrier

A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer.

High-performance integrated circuit packaging platform compatible with surface mount assembly

An integrated circuit package includes a transmission line structure, wire bonds, a first post and a second post. The transmission line structure runs from a printed circuit board (PCB) to an integrated circuit (IC) and includes a center transmission line between two ground lines and sealed from exposure to air. The wire bonds connect the transmission line structure to pads on the integrated circuit from where the center transmission line exits the integrated circuit package. The wire bonds are selected to have an impedance matched to impedance of the integrated circuit. The first post supports the center transmission line where the center transmission line enters the integrated circuit package from the printed circuit board. The second post supports the center transmission line where the center transmission line exits the integrated circuit package to connect to the wire bonds.

Semiconductor package

A semiconductor package includes: a redistribution substrate; a frame including first and second vertical connection conductors, and having a through-hole; first and second semiconductor chips; an encapsulant; a second redistribution structure disposed on the encapsulant, a conductive wire electrically connecting the second semiconductor chip and the second vertical connection conductor; and a vertical connection via penetrating a portion of the encapsulant, and electrically connecting the second redistribution structure and the first vertical connection conductor. The first semiconductor chip is connected to the second vertical connection conductor by the first redistribution structure.

Semiconductor package

A metallic ring is located on a multilayer ceramic substrate. An optical semiconductor laser is located on the multilayer ceramic substrate, inside the metallic ring. A metallic cap with a window is joined to the metallic ring. The metallic cap covers the optical semiconductor laser. An external heat sink is joined to an external side surface of the metallic cap. These features make it possible to improve high-frequency characteristics, producibility, and heat dissipation.

SEMICONDUCTOR CHIP PACKAGE HAVING OPTICAL INTERFACE

A semiconductor package including: a chip having a first surface and a second surface; a mold configured to encapsulate the chip; a vertical conductive channel electrically connected to a pad formed on the second surface of the chip while passing through the mold; a wiring pattern electrically connected to a pad formed on the first surface of the chip and configured to perform electrical connection in the package; an optical device arranged on a surface of the semiconductor package to be electrically connected to the vertical conductive channel; and an external connection terminal configured to electrically connect the semiconductor package to the outside. 1. A semiconductor package comprising:a chip having a first surface and a second surface;a mold configured to encapsulate the chip;a vertical conductive channel electrically connected to a pad formed on the second surface of the chip while passing through the mold;a wiring pattern electrically connected to a pad formed on the first surface of the chip and configured to perform electrical connection in the package;an optical device arranged on a surface of the semiconductor package to be electrically connected to the vertical conductive channel; andan external connection terminal configured to electrically connect the semiconductor package to the outside.2. The semiconductor package of claim 1 , wherein the chip comprises at least one of:an amplifier circuit configured to process an electrical signal supplied from the optical device; anda driver circuit configured to supply the electrical signal to the optical device.3. The semiconductor package of claim 1 , wherein the semiconductor package comprises a plurality of chips claim 1 ,wherein the plurality of chips comprise at least one of:a chip including an amplifier circuit; anda chip including a driver circuit.4. The semiconductor package of claim 1 , further comprising at least one signal processing chip.5. The semiconductor package of claim 1 , wherein the mold ...

Semiconductor Device and Method of Forming Microelectromechanical Systems (MEMS) Package

A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure.

Method of manufacturing circuit board and semiconductor package

A method of manufacturing a circuit board may include: preparing a circuit board body including an insulating layer having a first surface and a second surface opposite to the first surface and a first conductive thin film layer disposed on the first surface of the insulating layer and having a convex portion which is disposed on a first surface of the first conductive thin film layer and is embedded in the insulating layer; removing the convex portion to form a cavity corresponding to the convex portion in the insulating layer; and forming one or more first wiring patterns on the first surface of the insulating layer by removing first portions of the first conductive thin film layer. The one or more first wiring patterns correspond to second portions of the first conductive thin film layer not removed.

Semiconductor device assemblies including multiple shingled stacks of semiconductor dies

A semiconductor device assembly includes a substrate having a plurality of external connections, a first shingled stack of semiconductor dies disposed directly over a first location on the substrate and electrically coupled to a first subset of the plurality of external connections, and a second shingled stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first shingled stack and the second shingled stack.

METHODS OF MAKING SEMICONDUCTOR DEVICE PACKAGES AND RELATED SEMICONDUCTOR DEVICE PACKAGES

Methods of fabricating a semiconductor device package may involve providing a fan out wafer including semiconductor-device-package locations at a base level. Laterally offset semiconductor dice may be stacked at least some semiconductor-device-package locations of the fan out wafer to expose bond pads at a lateral periphery of each of the laterally offset semiconductor dice. The laterally offset semiconductor dice may be electrically connected to one another and associated electrically conductive traces of the at least some semiconductor-device-package locations. The semiconductor-device-package locations having stacks of semiconductor dice thereon may be singulated from the fan out wafer. 1. A method of fabricating a semiconductor device package , comprising: at least two mutually spaced semiconductor dice and a dielectric material laterally surrounding each of the at least two mutually spaced semiconductor dice and extending between adjacent semiconductor-device-package locations; and', 'electrically conductive traces extending over active surfaces of the at least two semiconductor dice and laterally beyond peripheries of the at least two semiconductor dice over the dielectric material to locations of electrically conductive vias extending from the electrically conductive traces through the dielectric material;, 'providing a fan out wafer comprising semiconductor-device-package locations at a base level, each semiconductor-device-package location comprisingstacking laterally offset semiconductor dice on at least some semiconductor-device-package locations of the fan out wafer to expose bond pads at a lateral periphery of each of the laterally offset semiconductor dice;electrically connecting the laterally offset semiconductor dice to one another and associated electrically conductive traces of the at least some semiconductor-device-package locations by forming wire bonds extending from a respective bond pad of an overlying semiconductor die of the laterally offset ...

Semiconductor package

A semiconductor package includes a redistribution structure including an insulating layer having an upper surface and a lower surface, a redistribution pad and a redistribution pattern on the lower surface of the insulating layer and electrically connected to each other, and a passivation layer on the lower surface of the insulating layer and having an opening exposing at least a portion of the redistribution pad; a semiconductor chip on the redistribution structure and including a connection pad electrically connected to the redistribution pad; an encapsulant on the redistribution structure and encapsulating the semiconductor chip; and a connection bump and a dummy bump on the passivation layer, wherein the redistribution pattern has a width narrower than a width of the redistribution pad, the connection bump vertically overlaps the redistribution pad, and the dummy bump vertically overlaps the redistribution pattern.

Coated bond wires for die packages and methods of manufacturing said coated bond wires

A method of manufacturing a bond wire having a metal core, a dielectric layer, and a ground connectable metallization, wherein the bond wire has one or more vapor barrier coatings, and manufacturing a die package with at least one bond wire according to the invention.

Stack semiconductor package and manufacturing the same

To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold.

CONDUCTIVE TRACE DESIGN FOR SMART CARD

A lead frame for assembling a smart card is formed with a substrate having first and second opposing major surfaces. A die receiving area is formed in the first major surface of the substrate and surrounded by conductive vias. A conductive coating is formed on the second major surface of the substrate and patterned to form electrical contact pads over the conductive vias. A conductive trace is formed on the first major surface of the substrate. The conductive trace extends between at least two adjacent vias and partially surrounds the at least two adjacent conductive vias, thereby forming a gap in the portion of the trace that surrounds the vias. An electrical connection between an integrated circuit chip and the conductive via extends over the gap. The gap prevents the electrical connection from inadvertently contacting the conductive trace. 1. A lead frame for assembling a smart card , the lead frame comprising:a substrate having first and second opposing major surfaces;a die receiving area formed in the first major surface of the substrate;a plurality of conductive vias that generally surround the die receiving area;a conductive coating formed on the second major surface of the substrate, wherein the conductive coating is patterned to form a plurality of electrical contact pads over the plurality of conductive vias; andat least one conductive trace formed on the first major surface of the substrate, wherein the conductive trace extends between at least two adjacent vias and wherein the conductive traces does not fully surround the at least two adjacent conductive vias;wherein the portions of the conductive traces that partially surround said at least two adjacent conductive vias are configured so that bond wires that extend from an integrated circuit chip to said at least two adjacent conductive traces extend over portions of the conductive vias that are not surrounded by the conductive traces.2. The lead frame of claim 1 , wherein the conductive vias are one of ...

Semiconductor Device and Method of Forming Microelectromechanical Systems (MEMS) Package

A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure. 1. A method of making a semiconductor device , comprising:providing a first semiconductor die;disposing a modular interconnect structure laterally with respect to the first semiconductor die;depositing an encapsulant around the first semiconductor die and modular interconnect structure;forming a conductive layer over the first semiconductor die and modular interconnect structure; anddisposing a second semiconductor die over the first semiconductor die, wherein the first semiconductor die or second semiconductor die includes a microelectromechanical device.2. The method of claim 1 , further including forming an interconnect structure over the modular interconnect structure opposite the conductive layer.3. The method of claim 1 , further including forming a conductive via through the modular interconnect structure.4. The method of claim 1 , wherein an active surface of the first semiconductor die is oriented toward an active ...

PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE

A printed circuit board (PCB) includes an insulating layer with an upper surface and a lower surface opposite to the upper surface; a first conductive pattern on the upper surface of the insulating layer; a second conductive pattern on the lower surface of the insulating layer; an aluminum pattern that covers at least a portion of an upper surface of the first conductive pattern; and a first passivation layer that covers at least a portion of sides of the first conductive pattern and that prevents diffusion into the first conductive pattern. 1. A printed circuit board (PCB) comprising:an insulating layer that includes an upper surface and a lower surface opposite to the upper surface;a first conductive pattern on the upper surface of the insulating layer;a second conductive pattern on the lower surface of the insulating layer;an aluminum pattern that covers at least a portion of an upper surface of the first conductive pattern; anda first passivation layer that covers at least a portion of sides of the first conductive pattern and that prevents diffusion into the first conductive pattern.2. The PCB of claim 1 , wherein the upper surface of the first conductive pattern is higher than the upper surface of the insulating layer.3. The PCB of claim 1 , wherein the first passivation layer comprises a material formed through an organic solderability preservative (OSP) surface treatment.4. The PCB of claim 1 , further comprising a first solder resist layer with an opening on the insulating layer.wherein an upper surface of a portion of the aluminum pattern is exposed by the opening of the first solder resist layer.5. The PCB of claim 4 , further comprising a second solder resist layer on a lower surface of the insulating layer.wherein the second solder resist layer covers sides of the second conductive pattern.6. The PCB of claim 5 , further comprising a second passivation layer that covers at least a portion of a lower surface of the second conductive pattern.7. The PCB of ...

Method for forming chip package structure with adhesive layer

A method for forming a chip package structure is provided. The method includes forming a chip on an adhesive layer. The chip has a front surface and a back surface opposite to the front surface. The back surface is in direct contact with the adhesive layer. A first maximum length of the adhesive layer is less than a second maximum length of the chip. The method includes forming a molding compound layer surrounding the chip and the adhesive layer. A first bottom surface of the adhesive layer is substantially coplanar with a second bottom surface of the molding compound layer. The method includes forming a redistribution structure over the chip and the molding compound layer.

INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK

Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires. 1. A semiconductor package , comprising:a first die having an active side and a backside opposite the active side, the active side having a plurality of die level interconnects thereon;a redistribution layer having a die side and a package level interconnect side, the die side coupled to the active side of the first die, and the package level interconnect side coupled to a plurality of package level interconnects;a first via bar laterally adjacent to and spaced apart from a first edge of the first die, the first via bar coupled to the redistribution layer;a second via bar laterally adjacent to and spaced apart from a second edge of the first die opposite the first edge of the first die, the second via bar coupled to the redistribution layer;a first encapsulation layer laterally surrounding the first die;a second die above the first die, the second die having an active side and a backside opposite the active side, the active side of the second die having a plurality of die level interconnects thereon, the backside of the second die facing the backside of the first die;a third die above ...

ELECTRONIC DEVICE PROVIDED WITH AN INTEGRAL CONDUCTIVE WIRE AND METHOD OF MANUFACTURE

An electronic device includes a supporting substrate having a front mounting face and an electrical connection network. An integrated circuit chip is mounted to the mounting face and is electrically connected to the electrical connection network. A primary encapsulation block embeds the integrated circuit chip and extends above and around the integrated circuit chip on the mounting face of the supporting substrate. An opening is provided in the primary encapsulation block to at least partially uncover an electrical contact. An additional wire made from an electrically conductive material has an end that is electrically connected to the electrical contact. An additional encapsulation block above the primary encapsulation block embeds the additional wire. 1. A method , comprising:producing a hole that extends into a primary encapsulation block which encapsulates a primary electronic device including a supporting substrate and an integrated circuit chip mounted on a front mounting face of the supporting substrate, said hole at least partly uncovering an electrical contact;installing at least one electrically conductive wire above the primary encapsulation block and in a position such that one end of the electrically conductive wire is electrically connected to said electrical contact; andproducing an additional encapsulation block on said primary encapsulation block, the additional encapsulation block embedding the electrically conductive wire.2. The method according to claim 1 , further comprising:producing a pillar made of an electrically conductive material in said hole;wherein installing comprises fixing said one end of the electrically conductive wire to said pillar.3. The method according to claim 2 , wherein the electrical contact is a contact on the front mounting face of the supporting substrate.4. The method according to claim 2 , wherein the electrical contact is a contact on the integrated circuit chip.5. The method according to claim 1 , wherein the ...

INTEGRATED CIRCUIT ASSEMBLY THAT INCLUDES STACKED DICE

An integrated circuit assembly that includes a substrate; a member formed on the substrate; a first die mounted to the substrate within an opening in the member such that there is space between the first die and the member and the member surrounds the first die, and wherein the first die does not extend above an upper surface of the member; an underfill between the first the die and the substrate, wherein the underfill at least partially fills the space between the die and member; and a second die mounted to the first die and the member, wherein the second die is mounted to the member on all sides of the opening. 1. (canceled)2. An integrated circuit assembly , comprising:a substrate;a member on the substrate;a first die mounted to the substrate within an opening in the member such that there is space between the first die and the member;an underfill between the first the die and the substrate, wherein the underfill at least partially fills the space between the die and member; anda second die mounted to the first die and the member, wherein the first die is below an upper surface of the member.3. The integrated circuit assembly of claim 2 , wherein an epoxy partially fills the space between the first die and the member claim 2 , and the epoxy attaches the second die to the first die.4. The integrated circuit assembly of claim 2 , wherein the second die is mounted to the member on all sides of the opening.5. The integrated circuit assembly of claim 2 , wherein the second die is mounted to the first die and the member using an epoxy claim 2 , and wherein the epoxy at least partially fills the space between the die and member.6. The integrated circuit assembly of claim 2 , wherein the first die is thermal compression bonded to the substrate claim 2 , and wherein the second die is flip-chip mounted to the first die.7. The integrated circuit assembly of claim 2 , wherein the first die is a system-on-chip die claim 2 , and wherein the second die is a memory die.8. The ...

PACKAGED SEMICONDUCTOR DEVICE HAVING A SHIELDING AGAINST ELECTROMAGNETIC INTERFERENCE AND MANUFACTURING PROCESS THEREOF

A packaged device has a die of semiconductor material bonded to a support. An electromagnetic shielding structure surrounds the die and is formed by a grid structure of conductive material extending into the support and an electromagnetic shield, coupled together. A packaging mass embeds both the die and the electromagnetic shield. The electromagnetic shield is formed by a plurality of metal ribbon sections overlying the die and embedded in the packaging mass. Each metal ribbon section has a thickness-to-width ratio between approximately 1:2 and approximately 1:50. 1. A device comprising: a base;', 'a first vertical region coupled to the base;', 'a second vertical region coupled to the base; and', 'a ribbon section coupled to the first vertical region at a first end and coupled to the second vertical region at a second end, the ribbon section having a curvature; and, 'an interference shield that includesa semiconductor die enclosed by the interference shield, the semiconductor die between the base and the ribbon section and a portion of the semiconductor die between the first vertical region and the second vertical region.2. The device of wherein the curvature of the ribbon section extends from the first end to the second end.3. The device of wherein the ribbon section includes a first portion including the first end claim 1 , a second portion including the second end claim 1 , and a third portion between the first portion and the second portion claim 1 , the first and second portions having curvature and the third portion being planar.4. The device of wherein the ribbon section has a concave side and a convex side claim 1 , the concave side being closer to the semiconductor die than the convex side.5. The device of wherein the ribbon section includes a first shielding ribbon and a second shielding ribbon.6. The device of wherein the first and second shielding ribbons each are spaced apart from and parallel to each other.7. The device of wherein the base is a copper ...

CHIP PACKAGES AND METHODS FOR FORMING THE SAME

A chip package for optical sensing includes a substrate, and a semiconductor device positioned on the substrate and coupled to the substrate through a first conducting element. Two molding processes are applied, to form a first colloid body on the substrate so as to cover the semiconductor device and, on the first colloid body, to form a second colloid body which covers an optical device. The optical device is electrically connected to the substrate through a second conducting element. The light transmittance of the second colloid body exceeds that of the first colloid body. 1. A method for forming a chip package comprising:providing a substrate having a first surface and a second surface opposite to the first surface, wherein the substrate comprises an interconnection structure passing through the first surface and the second surface;positioning a semiconductor element on the first surface;forming a first conductive element coupled between the interconnection structure and the semiconductor element;forming a first colloid body on the substrate and covering the semiconductor element;forming a through hole in the first colloid body to expose the interconnection structure;filling metal into the through hole to form a metal plug;positioning an optical element on the first colloid body;forming a second conductive element coupled between the optical element and the metal plug;forming a second colloid body on the first colloid body and covering the optical element.2. The method of claim 1 , wherein the semiconductor element comprises micro-electromechanical systems.3. The method of claim 1 , wherein a thickness of the second colloid body is less than that of the first colloid body.4. The method of claim 1 , wherein a coefficient of thermal expansion of the second colloid body exceeds that of the first colloid body.5. The method of claim 1 , wherein a material of the first colloid body is a resin with dark color.6. The method of claim 1 , wherein a material of the second ...

Semiconductor device manufacturing method, semiconductor device, and wire bonding apparatus

A semiconductor device manufacturing method includes: raising and moving a bonding tool, while paying out a wire, in a direction from a second toward a first bonding point to form in the wire a cut portion bent in a vicinity of the second bonding point; lowering and moving a tip of the bonding tool to the cut portion; lowering the bonding tool vertically to thin the cut portion; raising the bonding tool while paying out the wire; and moving the bonding tool in a direction away from the first and second bonding points and along a wire direction connecting the first and second bonding points and then cutting the wire at the cut portion to form a wire tail. This allows the length of the wire tail to be adjusted easily and efficiently to be constant.

SEMICONDUCTOR PACKAGE WITH MULTIPLE MOLDING ROUTING LAYERS AND A METHOD OF MANUFACTURING THE SAME

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package. 18-. (canceled)9. A method of manufacturing semiconductor devices that each includes a plurality of conductive routing layers , comprising:obtaining an etched and plated leadframe that includes a plurality of copper routing circuits and a plurality of package terminals, wherein the plurality of copper routing circuits forms a copper leadframe routing layer; coupling a plurality of interconnections with routing circuits associated with a previous routing layer that is directly beneath a current conductive ink printed routing layer being formed;', 'forming an intermediary insulation layer on top of the previous routing layer, wherein the plurality of interconnections protrudes from a top surface of the intermediary insulation layer that has the natural surface roughness;', 'performing an abrasion procedure to roughen at least the top surface of the intermediary insulation layer such that, after the abrasion procedure, the top surface of the intermediary insulation layer has an unnatural surface roughness that is rougher than the natural surface roughness; and', 'adhering a conductive ink layer on the roughened top surface of the intermediary insulation layer to form a plurality of conductive ink routing circuits that is included in the current conductive ink printed routing layer;, 'forming at least one conductive ink printed routing layer on top of the copper leadframe routing layer, wherein each of the at least one conductive ink printed routing layer is formed bycoupling a plurality of dies with a topmost conductive ink printed routing layer;encapsulating the plurality of dies and ...

Semiconductor package with multiple molding routing layers and a method of manufacturing the same

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.

BONDING STRUCTURE AND METHOD

A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform. 1. A method for bonding components , comprising:providing a nanoparticle preparation using a process in which sintering is absent, nanoparticle preparation consisting essentially of unpassivated nanoparticles derived using a top down nanoparticle synthesis process; andcompacting the nanoparticle preparation, wherein providing the nanoparticle preparation includes providing the nanoparticle preparation as a nanoparticle suspension and further including applying the nanoparticle suspension to a substrate and driving off the solvent from the nanoparticle suspension and wherein compacting the nanoparticles preparation where sintering is absent forms a nanoparticle structure.2. The method of claim 1 , further including mounting a semiconductor chip to the nanoparticle structure.3. The method of claim 2 , wherein applying the nanoparticle suspension to the substrate includes applying the nanoparticle suspension to a printed circuit board.4. The method of claim 2 , wherein applying the nanoparticle suspension to the substrate includes applying the nanoparticle suspension to a leadframe.5. The method of claim 1 , wherein providing the nanoparticle preparation includes suspending nanoparticles in a liquid.6. The method of claim 5 , wherein suspending the nanoparticles in the liquid includes suspending the nanoparticles in an organic solvent.7. The method of claim 5 , wherein suspending the nanoparticles in the liquid includes suspending the nanoparticles in an aqueous solution.8. A method for bonding components claim 5 , comprising:{'b': '500', 'providing a nanoparticle suspension consisting essentially of unpassivated nanoparticles of copper, nickel, or silver suspended in a liquid, wherein the unpassivated nanoparticles ...

STACKED MICROFEATURE DEVICES AND ASSOCIATED METHODS

Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device. 1. A microfeature device package , comprising:a first microfeature device having a first bond pad surface with a first bond pad;a second microfeature device proximate to the first microfeature device, the second microfeature device having a second bond pad surface with a second bond pad and an intermediate bond pad electrically connected to the second bond pad, the second bond pad surface facing toward the first bond pad surface of the first microfeature device;a wirebond between the first bond pad and a package connection site; andan electrically conductive member between the first bond pad and the intermediate bond pad.2. The microfeature device package of wherein the electrically conductive member comprises a volume of solder between the first bond pad and the intermediate bond pad.3. The microfeature device package of wherein the electrically conductive member comprises at least one of a gold stud bump claim 1 , a copper stud bump claim 1 , and a solder bump.4. The microfeature device package of claim 1 , wherein the ...

CHIP PACKAGES AND METHODS FOR FORMING THE SAME

A chip package for optical sensing includes a substrate, and a semiconductor device positioned on the substrate and coupled to the substrate through a first conducting element. Two molding processes are applied, to form a first colloid body on the substrate so as to cover the semiconductor device and, on the first colloid body, to form a second colloid body which covers an optical device. The optical device is electrically connected to the substrate through a second conducting element. The light transmittance of the second colloid body exceeds that of the first colloid body. 1. A chip package comprising:a substrate;a semiconductor element on the substrate, and coupled to the substrate through a first conductive element;a first colloid body on the substrate and covering the semiconductor element;an optical element in direct physical contact with the first colloid body and coupled to the substrate through a second conductive element; anda second colloid body on the first colloid body and covering the optical element, wherein the second colloid body is in direct physical contact with both the first colloid body and the optical element.2. The chip package of claim 1 , further comprising a third conductive element formed in the first colloid body and coupled to the first conductive element and the second conductive element.3. The chip package of claim 2 , wherein the third conductive element is a metal plug.4. The chip package of claim 1 , wherein the substrate comprises a first surface and a second surface opposite to the first surface claim 1 , and the substrate comprises an interconnection structure passing through the first surface and the second surface claim 1 , and coupled to the first conductive element and the second conductive element.5. The chip package of claim 1 , wherein the semiconductor element comprises micro-electromechanical systems.6. The chip package of claim 1 , wherein a thickness of the second colloid body is less than that of the first colloid ...

Semiconductor Device and Method of Forming Microelectromechanical Systems (MEMS) Package

A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure. 1. A method of making a semiconductor device , comprising:providing a first semiconductor die including a microelectromechanical system (MEMS);disposing a modular interconnect structure adjacent to the first semiconductor die;depositing a first encapsulant between the first semiconductor die and modular interconnect structure;forming a build-up interconnect structure over the first semiconductor die, first encapsulant, and modular interconnect structure, wherein the build-up interconnect structure includes an opening over the MEMS; anddisposing a second semiconductor die over the first semiconductor die.2. The method of claim 1 , further including disposing the second semiconductor die over the first semiconductor die with the opening of the build-up interconnect structure between the first semiconductor die and second semiconductor die.3. The method of claim 1 , further including depositing a second encapsulant over the ...

Electronic interconnect structure and method for manufacturing it

A process for manufacturing an electronic interconnect structure, the process including the steps of depositing an adhesion metal layer over a dielectric material surface having at least one exposed aluminum surface; depositing a barrier metal layer over the adhesion metal layer; depositing a first layer of aluminum over the barrier metal layer; depositing an intermediate barrier metal layer over the first layer of aluminum; applying a photoresist layer on top of the intermediate barrier metal layer; exposing and developing the photoresist layer; removing the exposed barrier metal and photoresist layer, leaving a layer of barrier metal over the aluminum layer; converting those portions of the layer of aluminum which are not covered by barrier metal to a porous aluminum oxide by porous anodization; removing the porous aluminum oxide; and removing the exposed barrier metal and adhesion metal layers to leave exposed patterned aluminum, and an electronic interconnect structure manufactured by this method.

Semiconductor device and method of manufacturing semiconductor device

In one example, a semiconductor structure comprises a frontside substrate comprising a conductive structure, a backside substrate comprising a base substrate and a cavity substrate contacting the base substrate, wherein the backside substrate is over a top side of the frontside substrate and has a cavity and an internal interconnect contacting the frontside substrate, and a first electronic component over the top side of the frontside substrate and in the cavity. The first electronic component is coupled with the conductive structure, and an encapsulant is in the cavity and on the top side of the frontside substrate, contacting a lateral side of the first electronic component, a lateral side of the cavity, and a lateral side of the internal interconnect. Other examples and related methods are also disclosed herein.

반도체 패키지

본 발명의 일 실시예는, 절연층, 절연층의 하면 상에 배치되며 서로 전기적으로 연결된 재배선 패드와 재배선 패턴, 및 재배선 패드의 적어도 일부를 노출시키는 개구부를 갖는 패시베이션층을 포함하는 재배선 구조체, 상기 재배선 패드와 전기적으로 연결된 접속 패드를 포함하는 반도체 칩, 상기 반도체 칩을 봉합하는 봉합재 및 상기 패시베이션층 상에 배치되는 연결 범프와 더미 범프를 포함하며, 상기 재배선 패턴은 상기 재배선 패드의 폭 보다 작은 폭을 갖고, 상기 연결 범프는 상기 재배선 패드와 수직적으로 중첩되고, 상기 더미 범프는 상기 재배선 패턴과 수직적으로 중첩되는 반도체 패키지를 제공한다.

使用倒装芯片安装的晶片级封装

一种半导体封装器件以及在封装工艺期间并入了在电子器件周围形成腔的封装方法。在一个实例中，所述器件封装包括：第一衬底，具有形成在其中的第一凹陷；以及第二衬底，具有形成在其中的第二凹陷；以及安装在所述第一凹陷中的电子器件。所述第一和第二衬底被接合到一起，其中所述第一和第二凹陷基本上彼此覆盖，从而形成在所述电子器件周围的腔。

Electronic circuit

반도체 장치 및 그 제조방법

베이스 기판의 주면 펠레트 탑재 영역상에 반도체 펠레트가 탑재되고, 상기 반도체 펠레트의 주면에 배치된 외부단자에 베이스 기판의 이면에 배치된 제1전극 패드가 전기적으로 접속되는 반도체 장치에 있어서, 상기 베이스 기판은 리지드 기판으로 구성하고, 상기 베이스 기판의 제1전극패드를 그의 이면에 배치된 제2전극패턴에 전기적으로 접속하며, 상기 반도체 펠레트를 그의 주면을 밑으로해서 베이스 기판의 주면 펠레트 탑재영역상에 탑재하고, 상기 반도체 펠레트의 외부단자와 베이스 기판의 제2전극패드를 베이스 기판에 형성된 슬리트를 통해서 본딩와이어로 전기적으로 접속한다.

콤포넌트 패키지용 장치 및 방법

콤포넌트 패키지 및 그 형성 방법이 제공된다. 제1 콤포넌트 패키지는 제1 반도체 기판의 대향 면 상에서 제1 반도체 소자에 부착되는 인터포저 쌍을 갖는 제1 반도체 소자를 포함할 수 있다. 각각의 인터포저는 그 내에 형성된 도전 트레이스를 포함하여 각 인터포저의 표면 상에 형성된 도전 특징부로의 전기적 결합을 제공한다. 복수의 스루 비어는 인터포저를 서로 전기적으로 접속할 수 있다. 제1 인터포저는 인쇄 회로 기판 또는 후속의 반도체 소자로의 전기적 접속을 제공할 수 있다. 제2 인터포저는 제2 반도체 소자 및 제2 콤포넌트 패키지로의 전기적 접속을 제공할 수 있다. 제1 및 제2 콤포넌트 패키지는 결합되어 패키지 온 패키지(PoP) 구조물을 형성할 수 있다.

半導体装置およびその製造方法

(57)【要約】 【課題】 半導体装置５０に用いる絶縁基板５４の引出 導体パターン１１を不要にして、半導体装置５０を小型 にすることにある。 【解決手段】 半導体装置５０は、半導体チップ５２を 載置する絶縁基板５４の積層断面５６、半導体チップ５ ２を載置する積層断面５６に配置された導電パッド５８ と半導体チップ５２表面に配置された導電パッド６０と を接続するボンディングワイヤ６２、半導体チップ５２ を載置する積層断面５６から絶縁基板５４を貫通する導 電体６４の終端部６６に配置される外部接続端子６８を 設ける。

新型高密度多层线路芯片正装封装结构及制作方法

本发明涉及一种新型高密度多层线路芯片正装封装结构及其制造方法，所述结构包括一层线路层（10）、芯片（2）和二层线路层（3），所述外引脚（7）处设置有金属球（8），所述二层线路层（3）正面设置有内引脚（11），所述二层线路层（3）和内引脚（11）周围设置有内层油墨层（1），所述二层线路层（3）正面设置有内引脚（11），所述芯片（2）正装于二层线路层（3）正面，所述芯片（2）和金属线（12）外围包封有塑封料（4）。本发明的有益效果是：降低了芯片封装载板的厚度，实现超薄高密度封装；可靠性的等级提高；真正地做到高密度线路的技术能力；可彻底解决传统基板在封装工艺中的翘曲问题。

Wiring board, semiconductor device and manufacturing method thereof

Semiconductor package and method of forming the same

반도체 패키지 및 그 형성방법이 제공된다. 상기 반도체 패키지는 인쇄 회로 기판, 상기 인쇄 회로 기판 상에 실장된 제 1 반도체 칩 및 상기 제 1 반도체 칩 상에 실장된 칩 패키지를 포함하되, 상기 칩 패키지는 상기 제 1 반도체 칩과 직접 접한다. 반도체 패키지, 인터포저, 비메모리 소자, 메모리 소자 A semiconductor package and a method of forming the same are provided. The semiconductor package includes a printed circuit board, a first semiconductor chip mounted on the printed circuit board, and a chip package mounted on the first semiconductor chip, wherein the chip package is in direct contact with the first semiconductor chip. Semiconductor Packages, Interposers, Non-Memory Devices, Memory Devices

Electronic device and carrier substrate for same

본 발명은 전자 장치에 관한 것으로, 이 장치(100)는 집적 회로(10)와, 하부 및 상부 도전층을 갖는 캐리어 기판을 포함하며 전압 공급부, 접지 및 신호 전송 접속부가 제공된다. 하나 이상의 공급 전압을 사용할 수 있게 하기 위해, 집적 회로(10)는 핵심 기능부(110)와 주변 기능부(210)로 세부 분할되고, 캐리어 기판(20)은 대응하는 핵심 영역(31)과 주변 영역(32)으로 세부 분할된다. 핵심 및 주변부 모두의 접지 접속부는 캐리어 기판(20)의 상호 접속부(22)를 통해 상호 결합된다. 이 상호 접속부는 특히 접지판이고, 주변부의 신호 전송을 위한 상호 접속부에 전송 라인 특성을 제공하게 한다. The present invention relates to an electronic device, wherein the device (100) comprises an integrated circuit (10), a carrier substrate having lower and upper conductive layers, and is provided with a voltage supply, ground and signal transmission connections. In order to be able to use one or more supply voltages, the integrated circuit 10 is subdivided into a core function 110 and a peripheral function 210, and the carrier substrate 20 is divided into a corresponding core area 31 and a peripheral. The area 32 is subdivided. Ground connections of both the core and the periphery are coupled to each other via interconnects 22 of the carrier substrate 20. This interconnect is in particular a ground plane and allows to provide transmission line characteristics to the interconnect for signal transmission in the periphery.

Semiconductor device in a resin package housed in a frame having high thermal conductivity

A semiconductor device including a substrate, solder bumps provided on a lower major surface of the substrate, a semiconductor chip provided on an upper major surface of the substrate, a resin package body provided on the upper major surface of the substrate so as to bury the semiconductor chip therein, a thermally conductive frame member having a flange part supporting the substrate at a rim part of the substrate, wherein the thermal conductive frame member has a thermal conductivity substantially larger than that of the resin package body and extending along to and in an intimate contact with side walls of the resin package body.

A method of manufacturing an integrated circuit package and integrated cirucit package

본 발명은 집적 회로 칩과 함께 사용하기 위한 BGA(Ball grid array) 패키지와 같은 집적 회로 패키지를 제공한다. 집적 회로 패키지는, 집적 회로 칩과 보다 낮은 도전성 레벨 간의 접속들이 기판에 형성된 관통 홀들을 감소시키기 위해 형성될 수 있도록, 패키지 내의 보다 낮은 도전성 레벨을 노출하는 공동(cavity)을 구비한 기판을 갖는다. 그 결과, 추가의 신호 라인 상호접속들이 기판 회로 패키지에 포함될 수 있고, 및/또는 집적 회로 칩의 크기가 축소될 수 있다. 이들 각각은 전기적 성능의 향상을 위해 구현될 수 있다. 기판내의 복수의 와이어 본딩 계층들은 와이어 본딩 공정 및 후속 캡슐화 공정을 용이하게 하는 더 큰 와이어 분리를 또한 제공할 수 있다. 집적 회로 패키지, 금속 와이어, 솔더 볼, 볼 그리드 어레이

Package carrier and manufacturing method thereof

本发明公开一种封装载板及其制作方法。形成一连通一基板的一上表面与一下表面的第一开口。配置一具有一顶表面与一底表面的导热元件于第一开口内，其中导热元件通过一绝缘材料而固定于第一开口内。压合一第一绝缘层及一第一金属层于上表面上。压合一第二绝缘层及一第二金属层于下表面上。形成一暴露出部分顶表面的第二开口。形成一暴露出部分底表面的第三开口。形成至少一贯穿第一金属层、第一绝缘层、基板、第二绝缘层以及第二金属层的孔道。形成一第三金属层以覆盖第一金属层、第二金属层以及孔道的内壁。形成一防焊层及一表面保护层于第三金属层上。

Semiconductor device, manufacturing method thereof, and electronic device

Semiconductor device and method of forming wafer level multi-row etched lead package

A semiconductor device has a base carrier having first and second opposing surfaces. The first surface of the base carrier is etched to form a plurality of cavities and multiple rows of base leads between the cavities extending between the first and second surfaces. A second conductive layer is formed over the second surface of the base carrier. A semiconductor die is mounted within a cavity of the base carrier. A first insulating layer is formed over the die and first surface of the base carrier and into the cavities. A first conductive layer is formed over the first insulating layer and first surface of the base carrier. A second insulating layer is formed over the first insulating layer and first conductive layer. A portion of the second surface of the base carrier is removed to expose the first insulating layer and electrically isolate the base leads.

Package structure and manufacturing method thereof

재배선 구조, 다이, 적어도 하나의 접속 모듈, 제 1 절연 밀봉재, 칩 스택, 및 제 2 절연 밀봉재를 포함하는 패키지 구조체. 상기 다이는 재배선 구조 상에 배치되고, 그것에 전기적으로 접속된다. 상기 접속 모듈은 재배선 구조 상에 배치된다. 상기 접속 모듈은 보호층 및 상기 보호층에 내장된 복수의 도전성 바를 포함한다. 상기 제 1 절연 밀봉재는 다이 및 접속 모듈을 밀봉한다. 상기 칩 스택은 제 1 절연 밀봉재 및 다이 상에 배치된다. 상기 칩 스택은 상기 접속 모듈에 전기적으로 접속된다. 상기 제 2 절연 밀봉재는 칩 스택을 밀봉한다.

Bonding method and bonding apparatus

(57)【要約】 【課題】 半導体装置の信頼性を高めるとともにその品 質を一定に保つことができるボンディングを行うことに ある。 【解決手段】 ボンディング方法は、ワイヤ２０が挿通 された第１のツール３０から、外部に送り出されたワイ ヤ２０の先端部２２をボール状に形成し、第１のツール ３０によって、先端部２２を第１の電極１２にボンディ ングし、ワイヤ２０を先端部２２から引き出して、第１ のツール３０によってワイヤ２０の一部２４を第２の電 極１６にボンディングし、第１のツール３０の上方に配 置された第２のツール３２でワイヤ２０を保持して、ワ イヤ２０を、一部２４を第２の電極１６上に残して引き ちぎり、第２のツール３２を、ワイヤ２０を保持したま ま、相対的に第１のツール３０に近づくように移動させ ることによって、第１のツール３０の外部に２０ワイヤ を送り出す。

Device package substrate and manufacturing method of the same

본 발명의 일 실시예에 따르면, 상면에 칩탑재영역을 포함하는 캐비티가 형성된 기판, 상기 캐비티 내에 연장되어 형성된 제1 배선층 및 상기 제1 배선층과 이격되어 형성된 제2 배선층, 상기 칩탑재영역에 위치하여 상기 제1 배선층 및 상기 제2 배선층과 접속되는 칩, 상기 제1 배선층, 제2 배선층 및 상기 칩을 덮도록 형성되며, 상기 제2 배선층의 일부를 노출하는 콘택홀을 갖는 절연층 및 외부 소자와 접속하기 위해 상기 콘택홀에 형성된 범프 패드를 포함하는 디바이스 패키지 기판 및 그의 제조 방법을 제공한다. According to an embodiment of the present invention, a substrate having a cavity including a chip mounting region on an upper surface thereof, a first wiring layer extending in the cavity, a second wiring layer formed to be spaced apart from the first wiring layer, and positioned in the chip mounting region An insulating layer and an external element formed to cover a chip connected to the first wiring layer and the second wiring layer, the first wiring layer, the second wiring layer, and the chip, and having a contact hole exposing a portion of the second wiring layer. A device package substrate comprising a bump pad formed in the contact hole for connecting to the device and a manufacturing method thereof. 본 발명에 따르면, 캐비티에 칩이 수용된 디바이스 패키지 기판을 구현함으로써 기존 장치에 비하여 제조 공정이 단순하면서도 전체적인 시스템 면적을 감소시킬 수 있는 디바이스 패키지 기판 및 그의 제조 방법을 제공할 수 있다. According to the present invention, it is possible to provide a device package substrate and a method of manufacturing the same, by implementing a device package substrate in which a chip is accommodated in a cavity, in which the manufacturing process is simple and the overall system area can be reduced as compared to an existing apparatus. 반도체, 패키지, 칩, 캐비티 Semiconductor, Package, Chip, Cavity

Semiconductor package structure and method of fabricating the same

A camera module and a method for manufacturing the same are provided to couple a substrate having an image sensor chip mechanically to a lens assembly, thereby removing the load of a thermal process and preventing the lens assembly and the image sensor chip from being damaged. A lens assembly having upper connection parts(65) is provided. Lower connection parts(20) having a structure jointed to the upper connection parts(65) are formed on a predetermined area of a substrate while defining a chip area. An image sensor chip is arranged on the bottom surface of the chip area. The lens assembly is attached to the substrate by using the upper and lower connection parts(20,65). The lower connection parts(20) are formed around the chip area as column shape. The upper connection parts(65) are formed corresponding to the column shape as groove shape such that the lower connection parts(20) is inserted into the upper connection parts(65).

The forming method of encapsulating structure

一种封装结构的形成方法，包括：形成具有相对的第一表面和第二表面的基板核心层，基板核心层包括塑封结构和位于塑封结构内的连接键结构；塑封结构内包覆有第一芯片，第一芯片具有功能面，且功能面朝向第一表面设置；连接键结构包括电学连接的第一连接键和第二连接键，第二连接键到第一表面的距离大于第一连接键到第一表面的距离，第二连接键到第一芯片的距离大于第一连接键到第一芯片的距离，第一连接键与所述功能面电学连接；在第二表面固定第二芯片，第二芯片和第一芯片位于连接键结构的同一侧；采用打线工艺形成键合金属线，键合金属线的一端与第二连接键电学连接，键合金属线的另一端与第二芯片电学连接。所述方法提高了封装结构的可靠性。

The manufacturing method of semiconductor packages, semiconductor equipment and semiconductor packages

本发明实施例公开了一种半导体封装、半导体设备及半导体封装的制造方法。其中，该半导体封装包括：基底；第一电子元件，设置在该基底上；第一导电层；第一柱层，连接该第一导电层及该基底；以及第一封装体，封装该第一导电层、该第一柱层及该第一电子元件；其中，该第一导电层嵌入于该第一封装体中。由于将第一导电层嵌入于第一封装体中，因此可以降低半导体封装的厚度。

Electronic component module

본 발명은 적어도 하나의 제 1 다층 회로 보드 모듈(21, 22; 31, 32; 41, 42) 및 냉각 장치(23, 33, 43)를 포함하는 전자 컴포넌트 모듈에 관한 것이고, 상기 냉각 장치(23, 33, 43)는 회로 보드 모듈(21, 22; 31, 32; 41, 42)의 상부 측면과 접촉한다. 냉각 장치(23, 33, 43)는 전자 컴포넌트 모듈(2, 3, 4)의 동작 동안 생성된 폐기 열이 냉각 장치(23, 33, 43)를 사용하여 회로 보드 모듈(21, 22; 31, 32; 41, 42)의 배열에 대해 측면 방향으로 추출되도록 설계된다. The invention relates to an electronic component module comprising at least one first multilayer circuit board module (21, 22; 31, 32; 41, 42) and a cooling device (23, 33, 43) 33, 43 are in contact with the upper side surfaces of the circuit board modules 21, 22 (31, 32; 41, 42). The cooling devices 23, 33 and 43 are arranged so that the waste heat generated during operation of the electronic component modules 2, 3 and 4 is transferred to the circuit board modules 21, 22; 31, 32; 41, 42).

Wafer-level packaging using wire bond wires in place of a redistribution layer

An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.

Electronic component, electronic component stack and method for their production and use of a bead placement machine for carrying out a method for producing an electronic component or component stack

Elektronisches Bauteil (12), umfassend: ein integriertes Bauelement (22), einen Gehäusekörper (24), und mindestens eine Kontaktvorrichtung (26, 27), die seitlich des integrierten Bauelements (22) angeordnet ist, wobei das Bauteil (12) eine Verdrahtungsanordnung (30) umfasst, die das integrierte Bauelement (22), den Gehäusekörper (24) und die Kontaktvorrichtung (26, 27) überlappt, und wobei das integrierte Bauelement (22), der Gehäusekörper (24) und die Kontaktvorrichtung (26, 27) auf derselben Seite der Verdrahtungsanordnung (30) angeordnet sind, wobei die Kontaktvorrichtung (26, 27) den Gehäusekörper (24) durchdringt, und wobei die Kontaktvorrichtung (26, 27) ein Kügelchen oder ein an einer Seite verformtes Kügelchen oder ein an zwei Seiten verformtes Kügelchen ist, dadurch gekennzeichnet, dass die Verdrahtungsanordnung (30) eine Schichtdicke kleiner als 50 Mikrometer oder kleiner als 10 Mikrometer hat. An electronic component (12) comprising: an integrated component (22), a housing body (24), and at least one contact device (26, 27) disposed laterally of said integrated device (22), said component (12) being a wiring assembly (30) overlapping the integrated component (22), the housing body (24) and the contact device (26, 27), and wherein the integrated component (22), the housing body (24) and the contact device (26, 27) are arranged on the same side of the wiring arrangement (30), wherein the contact device (26, 27) penetrates the housing body (24), and wherein the contact device (26, 27) is a bead or a bead deformed on one side or deformed on two sides Is bead, characterized in that the wiring arrangement (30) has a layer thickness of less than 50 microns or less than 10 microns.

Microelectronic devices and microelectronic support devices, and associated assemblies and methods

마이크로 전자 장치, 관련된 조립체, 및 관련된 방법이 여기에 개시된다. 예컨대, 본 발명의 어떤 양태는, 측면 및 이 측면 내의 개구를 가진 마이크로피처 공작물을 포함하는 마이크로 전자 장치에 관한 것이다. 이 장치는 표면을 가진 공작물 콘택을 더 포함할 수 있다. 공작물 콘택의 표면의 적어도 일부는 개구 및, 개구와 표면 사이로 연장하는 통로를 통해 접근하기 쉬울 수 있다. 본 발명의 다른 양태는 마이크로피처 공작물의 공작물 콘택에 접속할 수 있는 지지 콘택을 이송하는 측면을 가진 지지 부재를 포함하는 마이크로 전자 지지 장치에 관한 것이다. 이 장치는 지지 부재에 의해 이송되는 리세스된 지지 콘택 수단을 더 포함한다. 리세스된 지지 콘택 수단은 마이크로피처 공작물의 제 2 공작물 콘택에 접속할 수 있다.