STRUKTUR UND FERTIGUNGSVERFAHREN EINES DREIDIMENSIONALEN SYSTEMS EINER METALL-LEITERPLATTE, DIE VOR DEM HORIZONTALEN BESTÜCKEN GEÄTZT WIRD

Gegenstand ist eine horizontal bestückte, dreidimensionale, vor dem Bestücken geätzte System-Level-Metall-Leiterplatte, charakterisiert durch einen Metallsubstrat-Rahmen (1). Dieser Metallsubstrat-Rahmen (1) weist Basisbereiche (2) und Stifte (3) auf. Die Frontseiten der Basisbereiche (2) werden mit Chips (5) bestückt, die Frontseiten der Chips (5) sind über Metalldrähte (6) mit den Frontseiten der Stifte (3) verbunden. Auf den Front- oder den Rückseiten der Stifte (3) befinden sich Leitungspunkte (7). Die peripheren Bereiche der Basisbereiche (2), die Bereiche zwischen den Basisbereichen (2) und den Stiften (3), die Bereiche zwischen den Stiften (3), über den Basisbereichen (2) und den Stiften (3) und den Außenbereichen der Chips (5), die Metalldrähte (6) und die Leitungspunkte (7) sind mit Formmasse (8) vergossen und die Oberflächen des Rahmens aus Metall-Substrat (1), der Stifte (3) und der Leitungspunkte (7), die aus der Formmasse (8) herausragen, sind mit einer oxidationsbeständigen ...

Stromunterbrecher

Stromunterbrecher (10), mit:einem Halbleitersubstrat (12), in dem ein erstes und/oder zweites Schaltglied (14, 14) angeordnet ist;einer ersten Elektrode (18), die auf einer Oberfläche des Halbleitersubstrats (12) angeordnet ist;einer zweiten Elektrode (16), die auf der Oberfläche des Halbleitersubstrats (12) und getrennt von der ersten Elektrode (18) angeordnet ist;einer resistiven Schicht (22), die auf der Oberfläche des Halbleitersubstrats (12) angeordnet ist und die erste Elektrode (18) und die zweite Elektrode (16) verbindet;einem ersten Anschluss (32), der elektrisch mit der ersten Elektrode (18) verbunden ist, und einem zweiten Anschluss (28), der elektrisch mit der zweiten Elektrode (16) verbunden ist;einem ersten Bonddraht (34), der die erste Elektrode (18) elektrisch mit dem ersten Anschluss (32) verbindet und/oder einem zweiten Bonddraht (30), der die zweite Elektrode (16) elektrisch mit dem zweiten Anschluss (28) verbindet; undeinem Ansteuerschaltkreis (40), der ausgelegt ist ...

High-frequency circuit

In a high-frequency circuit arrangement, passive parts of the circuit are realized in a semiconductor body in which active circuit elements of another semiconductor material are located in recesses in the semiconductor body. When the semi-conductor body is at least in part low-ohmic, a reference plane, for example, the ground plane, can extend very close to the elements of the circuit arrangement. Consequently, due to the shorter connections required, parasitic effects are considerably reduced. When only one active element is mounted and only connections for this element are formed on the semiconductor body, a very suitable support for mounting and measurement is obtained.

APPARATUS FOR MAINTAINING RESERVE BONDING WIRE

Method and system for extending die size and packaged semiconductor devices incorporating the die

Semiconductor device, manufacturing method of semiconductor device, and power source device

SEMICONDUCTOR CHIP PACKAGE

PURPOSE: A semiconductor chip package is provided to improve a reliability and to suppress a crack generation by making a semiconductor chip be supported by a bonding wire without using a lead frame pad or an adhesive. CONSTITUTION: In a semiconductor chip package, a bottom surface of a semiconductor chip(34) is contacted with a lower metal mold(87). A lead of a lead frame(62) is lifted over an upper surface of the semiconductor chip(34), and is connected only by a wire. An upper metal mold(88) is closed with the lower metal mold(87), and a molding resin is injected through an injection hole(86) along an arrow direction. An air contained in a cavity(84) is discharged at an air vent. A dummy tie bar is formed at both sides of the chip in the same direction as the injection hole(86) is set. COPYRIGHT 2000 KIPO ...

상이한 용융 온도를 갖는 인터커넥션들을 가진 패키지

... 상이한 용융 온도를 갖는 인터커넥션들을 가진 패키지가 개시된다. 패키지는 적어도 하나의 전자 칩; 적어도 하나의 전자 칩이 제1 인터커넥션에 의해 제1 열 제거 보디 상에 장착되는 1 열 제거 보디; 적어도 하나의 전자 칩 위에, 제2 인터커넥션에 의해서 장착되는 제2 열 제거 보디; 적어도 하나의 전자 칩과 제2 열 제거 보디 사이에 배치된 적어도 하나의 전기적으로 전도성인 스페이서 보디 및 적어도 하나의 스페이서 보디를 제2 열 제거 보디와 직접 연결하는 제3 인터커넥션을 포함하고, 제1 인터커넥션, 제2 인터커넥션 및 제3 인터커넥션은 각각 다른 용융 온도를 갖는다.

Data setting method of Capillary grounding position for wire bonding device

To contrive the shortening of time upon replacing a capillary, and to contrive the laborsaving of maintenance. In the data setting method of the capillary 16 grounding position set at a proper grounding position upon replacing a capillary for a wire bonding device 10, the capillary grounding positional data after replacing are set based on a difference Z of clearances in the height direction between respective capillaries 16 and a basic member 25 measured before and after replacing the capillaries and the grounding positional data of the capillaries before replacing. The measurement of clearance is carried out by an imaging means for photographing the elevation picture images of the capillary tip end 16c as well as the basic member 25; and a clearance measuring means wherein a distance in the direction of height between the capillary tip end 16c and the reference member 25 is measured by processing the elevation picture images, comprising the capillary tip end 16c and the basic member 25 ...

Thermosetting silicone resin composition and die attach material for optical semiconductor device

A thermosetting silicone resin composition contains the following components (A-1) to (D): (A-1) an alkenyl group-containing linear organopolysiloxane; (A-2) a branched organopolysiloxane shown by (R13SiO1/2)a(R23SiO1/2)b(SiO4/2)c (1) ; (B-1) a branched organohydrogenpolysiloxane shown by (HR22SiO1/2)d(R23SiO1/2)e(SiO4/2)f (2) ; (B-2) a linear organohydrogenpolysiloxane shown by (R23SiO1/2)2(HR2SiO2/2)x(R22SiO2/2)y (3) ; (C) an adhesion aid which is an epoxy group-containing branched organopolysiloxane; and (D) a catalyst containing a combination of a zero-valent platinum complex with a divalent platinum complex and/or a tetravalent platinum complex. This provides a thermosetting silicone resin composition which causes little contamination at a gold pad portion and has excellent adhesiveness to a silver lead frame.

Semiconductor device and method of forming an embedded sop fan-out package

SEMICONDUCTOR PACKAGE

A semiconductor package includes an interconnect substrate, an insulating adhesive, a transient voltage suppressor (TVS) chip, at least one first conductive wire, and at least one second conductive wire. The interconnect substrate includes a bottom layer and a top layer, the bottom layer includes two first conductive blocks and a first insulating block therebetween, the top layer includes two second conductive blocks and a second insulating block therebetween, the second conductive blocks are respectively formed on the first conductive blocks, and the second insulating block is formed on the first insulating block. The insulating adhesive is formed on the second insulating block. The TVS chip is formed on the insulating adhesive without overlapping the second conductive blocks. The first conductive wire and the second conductive wire are respectively electrically connected to the second conductive blocks and electrically connected to the TVS chip.

DIE BACKSIDE STANDOFF STRUCTURES FOR SEMICONDUCTOR DEVICES

Standoff structures that can be used on the die backside of semiconductor devices and methods for making the same are described. The devices contain a silicon substrate with an integrated circuit on the front side of the substrate and a backmetal layer on the backside of the substrate. Standoff structures made of Cu of Ni are formed on the backmetal layer and are embedded in a Sn-containing layer that covers the backmetal layer and the standoff structures. The standoff structures can be isolated from each other so that they are not connected and can also be configured to substantially mirror indentations in the leadframe that is attached to the Sn-containing layer. Other embodiments are described.

Wire bonding apparatus

A wire bonding apparatus includes a frame, an X, Y, table, installed on the frame, including a linear stepping motor with a first stator and a first inductor, a transducer, pivotably installed on the X, Y table, to one end of which a capillary for bonding wire is installed, a first transferring portion installed to the frame to make the other end of the transducer ascend so that the capillary for wire bonding ascends, a second transferring portion installed on the X, Y table in front of the first transferring portion to, thereby, make the other end of the transducer ascend during bonding, and a first location detecting portion installed to the frame and the X, Y table to detect an amount of movement in the X and Y directions so that energy loss according to the driving of a head portion can be reduced.

Lead frame device for delivering electrical power to a semiconductor die

A method and apparatus for delivering electrical power to a semiconductor die is provided in which a metal frame (104) is applied to the top surface of a semiconductor die. The metal frame include two voltages leads (106, 108), each adjacent to each series of bond pads (116) formed on the top surface of the semiconductor die. Each voltage lead includes a longitudinal portion (122) adjacent bond pads (116) in the center of the semiconductor die and corner portions (124) or arm portions (125) adjacent bond pads (116) located in the quadrants (114) of the semiconductor die.

Packaged semiconductor device

A semiconductor device includes: a transistor including a main terminal and a sense terminal; a main output electrode connected to the main terminal via a first wire; a sense output electrode connected to the sense terminal via a second wire; and a package sealing the transistor, the first and second wires, part of the main output electrode and part of the sense output electrode, wherein a wiring inductance from the main terminal to the main output electrode is larger than a wiring inductance from the sense terminal to the sense output electrode.

Lead frame with bendable leads

A lead frame for a packaged integrated circuit (IC) device has a die receiving area and leads that extend outwardly from the die receiving area. The leads have an inner lead area proximate the die receiving area and an outer lead area distant from the die receiving area. Notches are formed in a surface of alternate ones of the leads, in the inner lead area proximate to the outer lead area. The notches facilitate bending of the alternate leads when the leads are subjected to a downward force by a mold tool, such that one set of leads lies in a first plane and another set lies in a second plane spaced from the first plane. The leads in the first plane can be formed into Gull Wing leads and the other set of leads into J-leads.

Method Of Fabricating Low Profile Leaded Semiconductor Package

In a semiconductor package a lead having a bottom surface coplanar with the flat bottom surface of the plastic body extends outward at the bottom of the vertical side surface of the plastic body. The result is a package with a minimal footprint that is suitable for the technique known as “wave soldering” that is used in relatively low-cost printed circuit board assembly factories. Methods of fabricating the package are disclosed, in particular a method of fabricating a package including an exposed die pad. 1. A method of fabricating a semiconductor package including an exposed die pad , the method comprising:providing a metal piece, the metal piece having a thickness;thinning the metal piece at a location where a cantilever segment of a lead is to be formed while leaving the thickness of the metal piece unchanged in a location where the die pad is to be formed;thinning the metal piece at a location where a foot of the lead is to be formed; andsevering the metal piece between the location of the die pad and the location of the cantilever segment of the lead.2. The method of wherein thinning the metal piece at a location where a foot of the lead is to be formed and severing the metal piece between the location of the die pad and the location of the cantilever segment of the lead are performed in a single process step.3. The method of wherein thinning a metal piece at the location where the cantilever segment of a lead is to be formed comprises thinning the metal piece at a location of a gap between the die pad and the cantilever segment of the lead.4. The method of wherein thinning the metal piece at locations where the cantilever segment of the lead and the gap between the die pad and the cantilever segment of the lead are to be formed comprises:depositing a first mask layer on a first side of the metal piece;forming an opening in the first mask layer corresponding to the locations where the cantilever segment of the lead and the gap between the die pad and the ...

INTEGRATED CIRCUIT PACKAGE WITH DIE ATTACH PADDLE HAVING AT LEAST ONE RECESSED PORTION

An integrated circuit package having a die attach paddle, a power die mounted on the die attach paddle and a controller die mounted on the die attach paddle. The die attach paddle has at least one recessed portion at least partially underlying the controller die.

Semiconductor packages and methods of formation thereof

In one embodiment, a semiconductor package includes a vertical semiconductor chip having a first major surface on one side of the vertical semiconductor chip and a second major surface on an opposite side of the vertical semiconductor chip. The first major surface includes a first contact region and the second major surface includes a second contact region. The vertical semiconductor chip is configured to regulate flow of current from the first contact region to the second contact region along a current flow direction. A back side conductor is disposed at the second contact region of the second major surface. The semiconductor package further includes a first encapsulant in which the vertical semiconductor chip and the back side conductor are disposed.

SEMICONDUCTOR DEVICE

Provided is a semiconductor device including a bonding layer made from sintered material and having a configuration capable of avoiding a variation in life span. The semiconductor device includes a conductive plate having a main surface, a semiconductor chip deposited to be opposed to the main surface of the conductive plate, and a bonding layer including porous sintered material and arranged between the conductive plate and the semiconductor chip, wherein a first outer edge of a bonding interface between the bonding layer and the conductive plate is located on the inside of an outer circumference of the semiconductor chip and is located on the inside of a second outer edge of a bonding interface between the bonding layer and the semiconductor chip.

SEMICONDUCTOR DEVICE INCLUDING BONDING COVERS

A semiconductor device includes a die pad, a bond post, a die disposed over the die pad, a wire coupled between the die and the bond post and having a first portion bonded to the die at a first bond area and a second portion bonded to the bond post at a second bond area, a first bonding cover disposed over the first portion, and a second bonding cover disposed over the second portion. A method includes bonding a first portion of a wire to a die at a first bond area, bonding a second portion of the wire to a first bond post of a lead frame at a second bond area, applying a bonding material over the first bond area to form a first bonding cover, and applying the bonding material over the second bond area to form a second bonding cover.

POWER ELECTRONICS MODULE

A power electronics module, having a DBC PCB having power semiconductors arranged thereon, and a multilayered leadframe including at least two separate subframes. No power or control routing takes place on the PCB. A region of the load source subregion is arranged between the PCB and the gate source and kelvin source subregion and is in electrical contact with the power semiconductors, and an adjoining region is located outside the PCB. A region of the drain source subregion is in electrical contact with a drain terminal on the PCB, and an adjoining region is located outside the PCB. The gate source subregion and the kelvin source subregion have a region above the load source subregion at which said subregions are in electrical contact with the power semiconductors and have an adjoining region outside the PCB which is opposite the drain source subregion and has pins bent above the PCB.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To solve the problem that, in a conventional manner, it becomes more difficult to measure thickness in ball press fitting by observing an image of a relatively flat portion at the peripheral part of a ball, because the relatively flat portion at the peripheral part of the ball having been press-fitted is narrower, due to miniaturization of ball through it is important to accurately measure the thickness in ball press fitting for setting a bonding strength to a desired value, in hole bonding. SOLUTION: In a method of manufacturing a semiconductor device, the diameter of an outer periphery at an internal chamfer portion at the capillary tip is stored as data in advance when measuring the thickness in ball press fitting. By referencing the data, the height of a ball portion corresponding to the outer periphery of the internal chamfer portion at the capillary tip is measured. COPYRIGHT: (C)2009,JPO&INPIT ...

WIRE BONDING METHOD

PURPOSE: To effectively exclude a defective product without executing a useless bonding operation by a method wherein, when any one out of an IC chip, a lead frame and a terminal is dislocated, it is detected. CONSTITUTION: An image signal which has been picked up by using a video camera 12 is displayed on a monitor screen 13; it is sent to a computation part 14 and computed. A check part 15 compares data obtained from a plurality of images, and checks whether a lead or a pad has been recognized erroneously or not. A control part 16 moves an X-Y table 19 and generates a control signal used to align a bonding position. A bonding head 18 is actuated by a drive part 17. At this stage, straight lines X1, X2, Y1, Y2 formed by rows of leads 5 are found; distances between four apexes of an IC chip which have been found separately and straight lines are computed and designated as l1, l2, l3, l4. When the chip is dislocated in parallel and a dislocation amount is large, l2 becomes excessively large ...

POSITIONING DEVICE FOR VERTICAL-TYPE LEAD FRAME

PURPOSE: To enable effective correction of deformation of a vertical-type lead frame for positioning the same. CONSTITUTION: When the lead frame 1 is guided by the longitudinal groove of rails 2 and 3 and stopped in front of a heat column 4, a shaking lever 7 is rotated D around a supporting point 10 by a cam mechanism through the intermediary of a connecting lever 30. Therefore, the rib 1c of the frame is put in the mechanism 5a of a pawl 5 and thereby the vertical direction thereof is positioned. At the same time, a V-shaped longitudinal groove 5b is engaged with a longitudinal lead 1a to position the horizontal direction, pressing the frame on the heat column 4. Subsequently, a shaking lever 8 is rotated D around a supporting point 9 by the action of a cam through the intermediary of a lever 31 and a pin 6 presses the point 1d of the frame by the force of a spring 29 to remove the bend and distortion of the frame. After linear bonding of the frame is conducted on the bonding surface ...

SEMICONDUCTOR LASER ELEMENT

PURPOSE: To obtain a stable high-output semiconductor laser element in a horizontal transverse mode by a method wherein the width of an active layer, in which a current is injected, is formed in a width of 100μm or wider and bonding wires are connected on the central line of the width of the active layer in such a way that they are symmetric to the central line. CONSTITUTION: A semiconductor laser chip 101 is mounted on a heat sink 102 of a package in a junction-down manner. The side, which comes into contact with the sink 102, of the chip 101 is a P-type electrode and the side, which is the opposite side to the side coming into contact with the sink 102 and is wire bonded, of the chip 101 is an N-type electrode. The N-type electrode is connected with a lead 104 by Au bonding wires 111 and 112 and the P-type electrode is connected to a package main body via the sink 102 consisting of CuW. The width of an active layer, in which a current is injected, is formed in a width of 150μm in a direction ...

SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor device which is capable of reducing a die in dimensions and optimizing bonding pads in number corresponding to a die of given dimensions, and a manufacturing method thereof. SOLUTION: A semiconductor device 20 is possessed of an active circuit 22 and a bonding pad region 24, where bonding pads 26 are arranged in rows in the bonding pad region 24. A bonding pad set is composed of bonding pads which are each selected out of each row of the pads. The bonding pads 26 are arranged in a specific manner in the bonding pad region 24, where a first wire pitch is given between pads which are adjacent to each other and belong to the same set, a second wire pitch is given between pads which are adjacent to each other and belong to different sets, and the arrangement of the bonding pads 26 are determined. COPYRIGHT: (C)1999,JPO ...

WIRE BONDING INSPECTOR

PURPOSE: To obtain high inspection precision and to reduce the cost of an imager through use of only a lens with one kind of magnification by picking up images in several operations and by inspecting relative positional coordinates of wires obtained by each imaging in a unified absolute coordinate system. CONSTITUTION: When a wire 2 is too long to completely fit into one imaging area with dimensions Lx, Ly, a X-Y table 15 moves by control of a X-Y table controller 16 on the basis of instruction from a main controller 17 to move an imager 14 to a first imaging area 201, thereby picking up image for conversion into image signal. This image signal is subjected to image processing so that positional coordinates 31-33 of each point of the bonding wire 2 are determined. Conversion into coordinate positions 31a-31b in the absolute coordinate system is made on the basis of a semiconductor chip 1 in an image processing inspector 20. Thus, positional coordinates of all bonding wires 2 are unified ...

WIRE BONDING APPARATUS

PURPOSE: To display an optimum sighting mark by storing sighting marks of two kinds or more and by selecting and displaying the optimum sighting mark in accordance with a target pattern in an object displayed as an image on a monitoring device. CONSTITUTION: First sighting marks optimum for alignment of positions of a bonding pad and an inner lead end part are set and stored in an apparatus. In the apparatus, in addition, informations showing the sequence of a teaching operation are also stored, and the teaching operation is conducted while the bonding pad and an inner lead are displayed alternately on a monitor. Therefore the sighting marks are changed alternately and displayed on the basis of the stored informations showing the sequence of the teaching operation. By switching over two sighting marks alternately for display in synchronization with an input operation for specifying positions, in this way, position alignment using an optimum square pattern 2a can be conducted when the position ...

RESIN-SEALED SEMICONDUCTOR DEVICE

PURPOSE: To improve integration density of an integrated circuit by bonding a die pad to an upper surface of a first semiconductor chip, bonding a second semiconductor chip which is smaller than the first semiconductor chip to an upper surface of the die pad, and connecting each electrode of the first and second semiconductor chips to an inner lead. CONSTITUTION: A first semiconductor chip 2a is bonded to a rear of a die pad 1 of a lead frame 5 through low stress epoxy resin 3. An electrode 4 of the semiconductor chip 2a protrudes from a die pad 1. A second semiconductor chip 2b is bonded to the die pad 1 through low stress epoxy resin 3. The semiconductor chip 2b is smaller than the semiconductor chip 2a. An electrode 8 of the semiconductor chip 2b and an inner lead 5a are connected by a TAB tape 7. A lead 10 is connected to the electrode 8 of the semiconductor chip 2 through a gold bump 11. The electrode 4 of the semiconductor chip 2a is mostly connected to the electrode 8 of the semiconductor ...

SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a technique capable of reducing the thickness of a semiconductor device. SOLUTION: The semiconductor device has a configuration made up of a semiconductor element, leads arranged at both sides of the semiconductor element so as to sandwich the element, wires for connecting one of the surfaces of each lead and an electrode of the semiconductor element corresponding thereto, and a resin for sealing the semiconductor element, the wires, and the leads, in which the undersurface of the semiconductor element and the other surface of each lead are arranged substantially in the same plane and exposed from the sealing resin. COPYRIGHT: (C)2004,JPO ...

WIRE BONDING DEVICE

PURPOSE: To prevent a lead frame from being oxidized by separating a press- pressure tool for a lead frame on carrying path under an opening of a feeder cover which is provided at a wire bonding position. CONSTITUTION: A press-pressure tool 13 which presses a lead frame L carried to a wire bonding position is separated from the lead frame L under an opening 4 of a feeder cover 2 so that it is not exposed on the opening 4 of the feeder cover 2. Thus, even if the press-pressure tool 13 is separately driven for the lead frame L, no external air is wound up and a curtain for preventing external air from entering from a gap between the inner surface of the feeder cover 2 and the press-pressure tool 13 can be formed. Thus, a stable and reliable wire bonding is made possible without oxidizing the lead frame L which is easily oxidized by copper, etc. COPYRIGHT: (C)1990,JPO&Japio ...

ПЕЧАТНЫЕ ПЛАТЫ

... 1. Печатная плата, на которой предусматривается выполнение паяного соединения, при этом на поверхности печатной платы имеется покрытие из композиции, включающей один или несколько галогенуглеводородных полимеров, с толщиной от 1 нм до 10 мкм, в которой отсутствует припой, или в основном отсутствует припой между указанной композицией покрытия и токопроводящими дорожками печатной платы. ! 2. Печатная плата по п.1, содержащая покрытие из композиции, включающей один или несколько галогенуглеводородных полимеров толщиной от 10 нм до 100 нм. ! 3. Печатная плата по любому из предшествующих пунктов, в которой полимер является фторуглеводородом. ! 4. Способ защиты печатной платы, включающий создание печатной платы, имеющей поверхность, подверженную воздействию факторов окружающей среды, и не содержащей припоя, или в основном не содержащей припоя на указанной поверхности, подверженной воздействию факторов окружающей среды, и нанесение на указанную поверхность композиции толщиной от 10 нм до 10 мкм ...

Verfahren und Einrichtung zur Messung der Schwingungsamplitude an einem Energietransducer.

Halbleiteranordnung mit Überchipanschlüssen

PROCEDURE AND MECHANISM FOR THE MEASUREMENT OF THE PEAK-TO-PEAK SWING AT A ENERGIETRANSDUCER.

PROCEDURE FOR THE PRODUCTION OF BADGES

Electronic device and use thereof

METHOD FOR CONTINUOUS ASSEMBLY OF PATTERNED STRIPS AND INTEGRATED CIRCUIT MICROMODULE OBTAINED BY SAID METHOD

... 2104374 9215118 PCTABS00130 Le procédé consiste à coller par pression une première bande (11) sur une deuxième bande (10) au travers d'une presse à coller (8, 9), en repérant sur chacune des bandes les pas de motifs et en juxtaposant au moment du collage les repères des pas de motifs de chaque bande par extension d'au moins une bande l'une par rapport à l'autre et par échauffement différent de chacune des bandes en regard pour provoquer un déplacement relatif par dilatation des deux bandes l'une par rapport à l'autre. Application: fabrication de "cartes à puces".

Method of forming a semiconductor die

In one embodiment, semiconductor die having non-rectangular shapes and die having various different shapes are formed and singulated from a semiconductor wafer.

Manufactoring process of micromodules of integrated circuit and corresponding micromodule

PROCEDE DE FABRICATION DE MODULES ELECTRONIQUES POUR CARTES A MICROCIRCUITS ET MODULES OBTENUS SELON CE PROCEDE

L'INVENTION CONCERNE LES CARTES A MICROCIRCUITS, DE TRANS- ACTION OU AUTRES ET ELLE A POUR OBJET UN PROCEDE DE FABRICATION EN SERIE DE MODULES ELECTRONIQUES UTILISABLES DANS CES CARTES AINSI QUE LES MODULES OBTENUS SELON CE PROCEDE. CONFORMEMENT A L'INVENTION, ON FABRIQUE, D'UNE PART, UNE GRILLE METALLIQUE 1 AVEC UNE PLURALITE D'OUVERTURES 2 DANS LESQUELLES PENETRENT DES LANGUETTES 3 RATTACHEES AU CADRE 4 DE CETTE GRILLE ET DESTINEES A FORMER LES PLAGES DE CONTACT DES MODULES, ET, D'AUTRE PART, DES PASTILLES 6 EN MATIERE PLASTIQUE QUI ONT UNE FACE AVANT 6 SENSIBLEMENT PLANE, UNE FACE ARRIERE 6 DU COTE DE LAQUELLE ELLES PRESENTENT UN EVIDEMENT 8 ET, ENTRE CET EVIDEMENT ET LA FACE AVANT, DES FENETRES 9 PREVUES POUR ETRE AMENEES AU DROIT DES LANGUETTES DE LA GRILLE. ENSUITE, ON FIXE UNE PASTILLE PAR SA FACE AVANT SUR LES LANGUETTES DE CHAQUE OUVERTURE, ON COLLE UNE PUCE DE CIRCUIT INTEGRE 12 AU FOND DE L'EVIDEMENT DE CHAQUE PASTILLE DE FACON QUE SA FACE ARRIERE SOIT ORIENTEE VERS LA GRILLE ...

ENCAPSULATION OF ELECTRONIC MODULES AND METHOD OF MANUFACTURE

전력용 반도체 장치 및 그 제조 방법

... 전력용 반도체 소자와, 제어 소자와, 전력용 반도체 소자와, 제어 소자를 각각 유지하고 있는 제 1 및 제 2 리드 프레임과, 전력용 반도체 소자와 제 1 리드 프레임을 접속하는 제 1 금속 배선과, 전력용 반도체 소자와 제어 소자를 접속하는 제 2 금속 배선과, 이들을 덮는 밀봉체를 구비하며, 제 1 리드 프레임은 전력용 반도체 소자를 탑재하고 있는 탑재면을 가지는 다이 패드와, 제 1 금속 배선의 한쪽 단부가 접속된 접속면을 가지는 제 1 이너 리드를 포함하고, 밀봉체의 표면 중 탑재면에 따른 방향으로 교차하는 측면에서, 제 1 및 제 2 리드 프레임이 돌출되지 않은 측면 부분에는, 다른 영역보다 표면 거칠기가 거친 수지 주입구 자국이 형성되어 있고, 수지 주입구 자국은 탑재면에 따른 방향에서 보았을 때에 접속면에 대해 제 1 금속 배선이 위치하는 측과는 반대측에 형성되어 있다.

BONDING APPARATUS USING ENHANCED MEASUREMENT UNIT FOR COMPENSATING BONDING MACHINE UNIT FOR CAPACITANCE COMPONENT AND IMPROVING PRECISION OF MEASUREMENT OF CONNECTION STATE BETWEEN WIRE AND OBJECT DEVICE

PURPOSE: A bonding apparatus is provided to compensate a bonding machine unit for a capacitance component and to enhance the precision of measurement of a connection state between a wire and an object device by using an improved measurement unit. CONSTITUTION: A bonding apparatus includes a stage for holding an object device(4), a bonding machine unit(20) for performing a wire bonding process, and a measurement unit(50) for measuring a connection state between the object device and a wire. The measurement unit is composed of an equivalent capacitance circuit(64) for compensating the bonding machine unit for a capacitance component, an AC(Alternating Current) signal source for supplying an AC signal to the equivalent capacitance circuit and the bonding machine unit, a capacitance comparing circuit for comparing the impedance of the bonding machine unit with that of the equivalent capacitance circuit, and a determination part(80) for determinating the connection state between the wire and ...

STACKED SEMICONDUCTOR PACKAGE APPARATUS CAPABLE OF IMPROVING THE RELIABILITY AND DURABILITY OF A PRODUCT

PURPOSE: A stacked semiconductor package apparatus is provided to improve conductivity and prevent a solder joint defect. CONSTITUTION: A stacked semiconductor package apparatus includes a first semiconductor package(100), a second semiconductor package(200), and a signal connection member(10). The first semiconductor package comprises one or more first semiconductor chips and a first encapsulating material to protect the first semiconductor chip. The second semiconductor package includes one or more second semiconductor chips, a lead connected to the second semiconductor chip and a second encapsulating material. The signal connection member passes through the first encapsulating material of the first semiconductor package and connects the first semiconductor chip with the second semiconductor chip. COPYRIGHT KIPO 2011 ...

Bonding device and method for detecting height of subject

A bonding device (100) having an optical system (20), an imaging element (70) for acquiring an image formed by the optical system (20) as a picture (14), an illumination unit (30) for illuminating an electronic component (13), and a control part (80) for processing the image acquired by the imaging element (70), the control part (80) illuminating the electronic component (13) through a first inclined optical path inclined with respect to the optical axis (24) of a first portion of the optical system (20) facing the electronic component (13) and acquiring a first image, illuminating the electronic component (13) through a second inclined optical path inclined toward the opposite side from the first inclined optical path with respect to the optical axis (24) of the first portion and acquiring a second image of the electronic component (13) as a subject, and calculating an amount of variation from a reference height of the electronic component (13) on the basis of the amount of positional ...

Wafer level chip scale package

A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.

Semiconductor device and wire bonding method

A semiconductor device with improved bondability between a wire and a bump and cutting property of the wire to improve the bonding quality. In the semiconductor device, a wire is stacked on a pad as a second bonding point to form a bump having a sloped wedge and a first bent wire convex portion, and a wire is looped from a lead as a first bonding point to the bump and is pressed to the sloped wedge of the bump with a face portion of a tip end of a capillary to bond the wire to the bump. At the same time, the wire is pressed to the first bent wire convex portion using an inner chamfer of a bonding wire hole in the capillary to form a wire bent portion having a bow-shaped cross section. The wire is pulled up and cut at the wire bent portion.

Device for mounting semiconductor element, lead frame, and substrate for mounting semiconductor element

A device for mounting a semiconductor element includes a metal plate serving as a base, a roughened silver plating layer with acicular projections, formed on at least either of: (a) top faces; and (b) faces that form concavities or through holes between the top faces and bottom faces; of the metal plate, and a reinforcing plating layer covering, as an outermost plating layer, an outer surface of the acicular projections in the roughened silver plating layer. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111>, and <101>. An outer surface of the reinforcing plating layer is shaped to have acicular projections with a surface area ratio of 1.30 or more and 6.00 or less to the corresponding smooth surface, as inheriting the shape of the acicular projections in the roughened silver plating layer.

Printed circuit boards

PRE-SOLDER METHOD AND REWORK METHOD FOR MULTI-ROW QFN CHIP

A pre-solder method for a multi-row quad flat no-lead (QFN) packaged chip (500) is provided. Solder paste is applied on at least one pad of the multi-row QFN packaged chip (500). The multi-row QFN packaged chip (500) is heated, such that the solder paste on the at least one pad of the multi-row QFN packaged chip (500) becomes solid solder (510) before the multi-row QFN packaged chip (500) is mounted on a substrate.

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

A method for manufacturing a thin, small, resin-encapsulated semiconductor device of non-lead type. A flexible tape where terminals are removably attached to a product forming portion of a major face through a first adhesive is prepared. A semiconductor device is removably fixed to the major face of the tape through a second adhesive. The electrodes of the semiconductor device are connected to the terminals through conductive wires. An insulating resin layer is formed in the area including the semiconductor device and wires on the major face of the tape so as to cover the semiconductor device and wires. The tape on the back of the insulating resin layer is pealed to form terminals exposed on the back of the insulating resin layer. The exposed surfaces of the terminals are formed of metal. One or more auxiliary metal layers are formed on the major face and the back of a main metal layer made of copper foil to complete terminals. The auxiliary metal layer on the major face side of the main ...

Package with lead frame with improved lead design for discrete electrical components and manufacturing the same

A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package ...

Semiconductor package bond post configuration

A bond post configuration for wire bonded semiconductors has bond posts grouped in three posts where two are arranged closely to a side of a die about a first axis and a third is arranged in between and further removed from the side about a second axis. In one form, the bond post configuration is a radial configuration. Additionally, conductive traces which extend from the bond posts and away from the die are placed off-center from the the bond posts about the first axis to provide more placement area for the bond posts arranged about the second axis. The bond post configuration may be utilized in any wire bonded semiconductor.

On-line inspection method and system for bonds made to electronic components

On-line inspection of electric characteristics of a semiconductor device can be achieved during a step of bonding a lead wire to a chip surface of the semiconductor device in the process of fabricating an electronic component, by the use of a circuit arrangement formed between a lead wire fed from a bonder and connectors serving as electric terminals when the chip is mounted thereon to be made into an electronic component, and by the application of electric power thereto.

Semiconductor device and a manufacturing method thereof

There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead.

Packaging for lateral high voltage GaN power devices

Packaging methods and structures for lateral high voltage gallium nitride (GaN) devices achieve electrical isolation while also maintaining thermal dissipation. The electrical isolation reduces or eliminates vertical leakage current, improving high voltage performance. The packages may use or be compatible standards such as JEDEC, which reduces packaging cost and facilitates implementation of the packaged devices in conventional circuit design approaches.

Semiconductor device and method of forming base substrate with cavities formed through etch-resistant conductive layer for bump locking

A semiconductor device has a base substrate with first and second etch-resistant conductive layers formed over opposing surfaces of the base substrate. First cavities are etched in the base substrate through an opening in the first conductive layer. The first cavities have a width greater than a width of the opening in the first conductive layer. Second cavities are etched in the base substrate between portions of the first or second conductive layer. A semiconductor die is mounted over the base substrate with bumps disposed over the first conductive layer. The bumps are reflowed to electrically connect to the first conductive layer and cause bump material to flow into the first cavities. An encapsulant is deposited over the die and base substrate. A portion of the base substrate is removed down to the second cavities to form electrically isolated base leads between the first and second conductive layers.

SEMICONDUCTOR PACKAGE WITH INTEGRATED OUTPUT INDUCTOR ON A PRINTED CIRCUIT BOARD

A semiconductor package includes a semiconductor die comprising a control transistor and a sync transistor, an integrated output inductor comprising a winding around a core, and coupled to the semiconductor die. The winding comprises a plurality of conductive clips situated above a printed circuit board (PCB) and connected to a plurality of conductive segments in the PCB. The control transistor and the sync transistor are configured as a half-bridge. The integrated output inductor is coupled to a switched node of the half-bridge. At least one of the plurality of conductive clips includes a partially etched portion and a non-etched portion. The semiconductor die is attached to the integrated output inductor by a die attach material. The semiconductor die and the integrated output inductor are encapsulated in a molding compound.

Semiconductor assembly with component attached on die back side

One or more electronic components can be mounted on the back side of a semiconductor die. The components can be passive components, active components, or combinations thereof. The components can be soldered to signal routes on the back side of the die, the signal routes being attached to the die using a metallization layer or using one or more dielectric layer sections. Placing components on the back side of the die can allow for incorporation of the components without necessarily increasing the form factor of the die's package.

Semiconductor Device and Method of Forming Base Substrate with Recesses for Capturing Bumped Semiconductor Die

A semiconductor device has a base substrate with recesses formed in a first surface of the base substrate. A first conductive layer is formed over the first surface and into the recesses. A second conductive layer is formed over a second surface of the base substrate. A first semiconductor die is mounted to the base substrate with bumps partially disposed within the recesses over the first conductive layer. A second semiconductor die is mounted to the first semiconductor die. Bond wires are formed between the second semiconductor die and the first conductive layer over the first surface of the base substrate. An encapsulant is deposited over the first and second semiconductor die and base substrate. A portion of the base substrate is removed from the second surface between the second conductive layer down to the recesses to form electrically isolated base leads for the bumps and bond wires.

Circuit device and manufacturing method of circuit device

After a trench 54 is formed in a conductive foil 60, the circuit elements are mounted, and the insulating resin is applied on the conductive foil 60 as the support substrate. After being inverted, the conductive foil 60 is polished on the insulating resin 50 as the support substrate for separation into the conductive paths. Accordingly, it is possible to fabricate the circuit device in which the conductive paths 51 and the circuit elements 52 are supported by the insulating resin 50, without the use of the support substrate. And the interconnects L1 to L3 requisite for the circuit are formed, and can be prevented from slipping because of the curved structure 59 and a visor 58.

Semiconductor device and its manufacturing method

In a semiconductor device is provided a semiconductor element 22 encapsulated in a package 26. The connection area 29 used to connect an external structure, such as a heat-dissipating plate 30 or another semiconductor device, is installed in either the die pad 23 used for mounting the semiconductor element or inner leads 24 that are electrically connected to the semiconductor element. The connection area is integrated with the external structure via linking holes 28 that have been formed in the package. By combining a packaged and completed semiconductor device with various types of external structures, it becomes possible to expand or enhance the function of the overall semiconductor device, or to lower its cost.

Double-encapsulated power semiconductor module and method for producing the same

One aspect relates to a power semiconductor module. The module includes a module housing, a substrate, and a semiconductor chip attached to the substrate. The semiconductor chip is disposed in the module housing. A dielectric first encapsulation is disposed in the module housing, in physical contact with both the semiconductor chip and the substrate and has a first modulus of elasticity. A dielectric second encapsulation is disposed in the module housing and has a second modulus of elasticity. The first encapsulation is a polymer and disposed between the substrate and the second encapsulation. The semiconductor chip is disposed between the first encapsulation and the substrate. Further, the first modulus of elasticity is greater than the second modulus of elasticity.

Semiconductor device

An object of the present invention is to provide a semiconductor device suppressing a ringing. A semiconductor device in an embodiment 1 includes an IGBT, an SBD connected to the IGBT in series, a PND connected to the IGBT in series and parallelly connected to the SBD, and an output electrode connected between the IGBT and the SBD and between the IGBT and the PND. An anode electrode of the PND is connected to the output electrode by the wiring via an anode electrode of the SBD.

3D PRINTED SEMICONDUCTOR PACKAGE

In described examples, a method for encapsulating a semiconductor device includes the steps of immersing a layer of the semiconductor device in a liquid encapsulation material, irradiating portions of the liquid encapsulation material to polymerize the liquid encapsulation material, and moving the semiconductor device further from a surface of the liquid encapsulation material proximate to the layer. Immersing the semiconductor device is performed to cover a layer of the device in the liquid encapsulation material. Targeted locations of the liquid encapsulation material covering the layer are irradiated to form solid encapsulation material. The semiconductor device is moved from a surface of the liquid encapsulation material so that a new layer of the semiconductor device and/or of the solid encapsulation material can be covered by the liquid encapsulation material. The irradiating and moving steps are then repeated until a three dimensional structure on the semiconductor device is formed ...

LED leadframe or LED substrate, semiconductor device, and method for manufacturing LED leadframe or LED substrate

An LED leadframe or LED substrate includes a main body portion having a mounting surface for mounting an LED element thereover. A reflection metal layer serving as a reflection layer for reflecting light from the LED element is disposed over the mounting surface of the main body portion. The reflection metal layer comprises an alloy of platinum and silver or an alloy of gold and silver. The reflection metal layer efficiently reflects light emitted from the LED element and suppresses corrosion due to the presence of a gas, thereby capable of maintaining reflection characteristics of light from the LED element.

ELECTRONIC DEVICE PACKAGING WITH GALVANIC ISOLATION

In a general aspect, an electronic device assembly can include a dielectric substrate having a first surface and a second surface opposite the first surface and a leadframe including: a first leadframe portion including a first plurality of signal leads; and a second leadframe portion including a second plurality of signal leads. The substrate can be coupled with a subset of the first plurality of signal leads and a subset of the second plurality of signal leads. Signal leads of the first plurality of signal leads, other than the subset of the first plurality of signal leads, can be spaced from the dielectric substrate. Signal leads of the second plurality of signal leads, other than the subset of the second plurality of signal leads, can be spaced from the dielectric substrate. The assembly can further include one or more semiconductor die that are electrically coupled with the substrate and the leadframe portions.

Semiconductor package with connection lug

A semiconductor package includes a first die pad, a first semiconductor die mounted on the first die pad, an encapsulant body of electrically insulating material that encapsulates first die pad and the first semiconductor die, a plurality of package leads that each protrude out of a first outer face of the encapsulant body, a connection lug that protrudes out of a second outer face of the encapsulant body, the second outer face being opposite from the first outer face. The first semiconductor die includes first and second voltage blocking terminals. The connection lug is electrically connected to one of the first and second voltage blocking terminals of the first semiconductor die. A first one of the package leads is electrically connected to an opposite one of the first and second voltage blocking terminals of the first semiconductor die that the first connection lug is electrically connected to.

SEMICONDUCTOR PACKAGE HAVING AN INTERDIGITATED MOLD ARRANGEMENT

A semiconductor package including a leadframe has a plurality of leads, and a semiconductor die including bond pads attached to the leadframe with the bond pads electrically coupled to the plurality of leads. The semiconductor die includes a substrate having a semiconductor surface including circuitry having nodes coupled to the bond pads. A mold compound encapsulates the semiconductor die. The mold compound is interdigitated having alternating extended mold regions over the plurality of leads and recessed mold regions in between adjacent ones of the plurality of leads.

THERMALLY ENHANCED ELECTRONIC PACKAGES FOR GAN POWER INTEGRATED CIRCUITS

An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base. 1. An electronic device comprising:a die-attach pad, at least one drain terminal, at least one source terminal and at least one gate terminal; anda gallium nitride (GaN) semiconductor substrate including a transistor formed therein, the transistor including a gate, a drain and a source, wherein:the GaN semiconductor substrate is electrically connected to the die-attach pad;the gate is electrically connected to the at least one gate terminal;the drain is electrically connected to the at least one drain terminal; andthe source is electrically connected to the at least one source terminal.2. The electronic device of wherein the die-attach pad is arranged to be coupled to a ground potential.3. The electronic device of wherein the die-attach pad claim 1 , the at least one drain terminal the at least one source terminal and the at least one gate terminal are electrically isolated from each other.4. The electronic device of wherein at least a portion of the GaN semiconductor substrate is covered by an encapsulant.5. The electronic device of wherein the encapsulant covers at least a portion of the die-attach pad claim 4 , the at least one gate terminal claim 4 , the at least one drain terminal and the at least one source ...

Semiconductor Device and Method of Making a Semiconductor Package with Graphene for Die Attach

A semiconductor device has a substrate with a die pad. A conductive material is disposed on the die pad. The conductive material includes a plurality of graphene-coated metal balls in a matrix. A semiconductor die is disposed on the conductive material. The conductive material is sintered using an infrared laser. A bond wire is formed between the semiconductor die and substrate. An encapsulant is deposited over the semiconductor die and bond wire.

SEMICONDUCTOR DEVICE, ITS MANUFACTURE AND SUBSTRATE FOR SEMICONDUCTOR DEVICE

PURPOSE: To enhance reliability and a heat radiating characteristic and at the same time to perform a mounting test after mounted in a semiconductor device having a substrate for mounting a semiconductor element, its manufacturing method and a substrate for a semiconductor device. CONSTITUTION: This semiconductor device is provided with a semiconductor element 21, a substrate 24 for a semiconductor device having an element mounting part 32, solder bumps 22 disposed in the substrate 24 for a semiconductor device and connected to the semiconductor element 21 and at the same time, connected to an external electrode at the time of mounting and sealing resin for sealing the semiconductor element 21. Therefore, this semiconductor device is constituted of a substrate comprising a base part 26 capable of bending the substrate 24 for a semiconductor device and a lead part 28 formed in the base part 26 for interconnecting the semiconductor element 21 and the solder bumps 22 and at the same time a ...

ASSEMBLING OF SEMICONDUCTOR DEVICE

PURPOSE: To satisfactorily connect the end point of lead wire and chip by fixing a semiconductor chip at the lower part of vessel divided into upper and lower sections, allowing the lead wire to run through the specified position at the upper part of vessel and then fixing them and connecting the end point of lead wire to the electrode on the chip. CONSTITUTION: A chip 2 on the bottom plate 1 coupled to the side wall 5 by welding is easily brazed by the automatic furnace assembling with a carbon jig. Meanwhile, the upper cover 6 is made of an insulator to which a lead frame having a lead 4 is previously bonded or fixed by the brazing or molding. A solder plate 9, for example, is placed on the electrode of this chip 2, the upper cover 6 to which the lead 4 is fixed is placed and thereafter the end point of lead 4 is connected to the chip 2 and electrode by the method such as allowing it to run in the automatic furnace. In this case, the lead 4 is short within the vessel and therefore the ...

WIRE BONDER

PROBLEM TO BE SOLVED: To prevent a fine recessed part from being formed owing to the sticking of a cut fragments by increasing the width of the groove of an wedge from both end parts to the intermediate part and decreasing the depth of the groove from both end parts to the intermediate part. SOLUTION: The wedge 8 is so formed that the width of the plane shape of the groove 9 formed in the reverse surface of a long leg piece 8a is increased from both ends 9a and 9b to the intermediate part 9c and the depth of the groove 9 viewed from the side section is decreased from both end parts 9a and 9b to the intermediate part 9c. Both end parts 9a and 9b of the groove are narrow in opening width, but set deep, so a wire which is pressed at the groove intermediate part 9c and extruded to both end parts 9a and 9b decreases in outward pressure, so sufficient gaps can be secured between both end parts of the groove and the pressed wire 7, contact pressure to the wire 7 is small, and the sticking of materials ...

FOREIGN MATTER REMOVING METHOD

PURPOSE: To remove positively foreign matters from an object, by feeding air into a vacuum vessel and exhausting it in a state in which the object from which foreign matters is to be removed is covered by a vacuum vessel. CONSTITUTION: In the case where foreign matters are removed from the interior of a cavity 5 of a package 4 before wire-bonding, a foreign matter removing apparatus E is positioned above the package 4 which is fed intermittently over a feeder 8 after bonding of a pellet 6 is finished. Thereafter, by pushing down the vacuum vessel 1 by a cylinder 9, the under face of the surrounding wall is contacted onto the upper face of the surrounding wall of the package 4 in order to define a space uniting a space 1a in the vacuum vessel 1 and the cavity 5 in the package 4. In this state, high pressure gas is jetted from above into the vacuum vessel 1 through a feeding tube 2, and the vacuum vessel 1 is exhausted through an exhausting tube 3 by a vacuum source. Thus foreign matters ...

SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor device which reduces the burden of a manufacturing process and whose production costs can be reduced by dealing with an increase in a rated current without increasing a wire bonding process. SOLUTION: A semiconductor chip 13 which comprises an IGBT or the like is mounted on the surface of a mounting board 11 via a metal pattern 12-2. The main surface of the semiconductor chip 13 and a metal pattern 12-3 are connected by a bonding wire 14. A collector external output terminal 15-1 and an emitter external output terminal 15-2 are installed on the metal patterns 12-2, 12-3. The terminal 15-1 and the terminal 15-2 are electrically connected by a welding connection to the terminal 15-1 and the terminal 15-2 by a collector lead frame 18-1 and an emitter lead frame 18-2. COPYRIGHT: (C)2002,JPO ...

LEADFRAME POSITIONING JIG

PURPOSE: To position the leadframe with a good reproductivity at a high accuracy by moving perpendicular to the leadframe a main pin with a tapered tip arranged between two auxiliary pins each with a flat, tapered tip separated at a given space. CONSTITUTION: After the leadframe is moved to the given position in the direction A, with the action of cams 22 and 22', locked holders 17 and 17' are released sliding so that the main pin 11 and two auxiliary pins are inserted into the reference hole 14 of the frame. As the space between the pins 25 are equal to the sum of the length of the pitch of the hole 14 and the frame 15, the pins 25 are accurately inserted into the holes of the adjacent frames and thus, the main pin 11 is inserted into the hole 14 of the same frame 15 at a sufficent space. As the tip of the auxiliary pins 25 is tapered, slight deviation in the distance of the hole 14 from the corresponding pins 11 and 25 can be overcomed by the pin 25. Thus, the main pin ensure in substance ...

SEMICONDUCTOR H BRIDGE CIRCUIT

PURPOSE: To connect each terminal at the common potential level of two transistors, and to simplify a lead frame by connecting two transistors having different conductivity types formed by discrete semiconductor chips series through the common lead frame. CONSTITUTION: Two transistors Q1, Q2 and Q3, Q4 having different conductivity types formed discrete semiconductor chips are connected in series respectively while being connected in parallel between one power supply V1 and the other power supply V2 respectively. Inductance load L is bonded between each mutual midpoint in the series connection of the two transistors Q1, Q2 and Q3, Q4, and the inductance load L is supplied with currents based on each state of the drive of the two transistors Q1, Q2 and Q3, Q4. Sections between each series connection end T1, T2 and T2, T3 of the two transistors Q1, Q2 and Q3, Q4 are connected in series through common lead frames 10, 20 respectively. Accordingly, each terminal at the common potential level ...

SEMICONDUCTOR DEVICE AND ITS MANUFACTURE

PROBLEM TO BE SOLVED: To enable connection between a pad and a lead even if a lead interval is made narrow, by raising a wire wherein a wire ball is formed by a specified length from a pad on a semiconductor chip, and joining a tip of the wire to a solder plating part of a lead rear. SOLUTION: In the semiconductor device, a wire 8 connects a pad on a semiconductor chip 1 to a lead 3 provided immediately thereon. The lead 3 is bonded to an upper surface of the semiconductor chip 1 through an adhesive tape 5, and an entire thereof is sealed by mold resin 7 in the state. Thereafter, a solder ball 4 is mounted on the lead 3. The solder plating 6 of the lead 3 is fused and is joined to a tip of the wire 8. A creeping up part of solder is formed and the lead 3 and a pad of the semiconductor chip 1 are connected. As a result, it is possible to arrange and join a lead immediately on a pad of a semiconductor chip, minimize the distance between a lead and a wire and miniaturize a semiconductor device ...

SEMICONDUCTOR DEVICE AND ITS MANUFACTURE

PURPOSE: To provide a semiconductor device which can realize reduction of weight and miniaturization while maintaining necessary strength and is excellent in mass-productivity. CONSTITUTION: A surface on which an electrode of a semiconductor element 5 is formed is oppositely arranged to one side surface, on which an upper surface electrode 3 is formed, of a semiconductor carrier 1 constituted of an insulating board wherein the upper surface electrode 3 and a bottom surface electrode 4 which are electrically connected are installed. An electrode 6 of the semiconductor element 5 is bonded to the upper surface electrode 3 of the semiconductor carrier 1 by using a face down method. In the above semiconductor device, the insulating board of the semiconductor carrier 1 forms a recessed part on the semiconductor element 5 side by curving the periphery of the insulating board to the semiconductor element 5 side, and the semiconductor element 5 is accommodated in the recessed part. COPYRIGHT: (C ...

WIRE BONDING APPARATUS AND BONDING ARM

PURPOSE: To provide a wire bonding apparatus and a bonding arm with good efficiency in transmission of ultrasonic energy to a bonding tool at low cost. CONSTITUTION: A bonding tool (capillary) 4 is tightened by inserting a tightening mean (bolt) 35 into an inserting hole 1f of the bonding tool 4. The inserting hole if has a slit 1g formed across a center of the hole 1f and vertically to an axial direction of the bonding arm, namely vertically to a direction of longitudinal vibration. COPYRIGHT: (C)1996,JPO ...

半導体装置及びその製造方法、電源装置

SEMICONDUCTOR CIRCUIT PACKAGE AND METHOD OF PACKAGING SAME

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To facilitate plating the backside of a stage in semiconductor packages, where semiconductor chips are mounted onto the front of the stage comprising metal thin plates and the semiconductor chips and the stage are sealed with resin mold sections so that the backsides of the stages are exposed outward. SOLUTION: A protrusion 11, which projects from an upper surface 9a of the resin mold section 9 positioned at an upper section of a surface 5a of the stage 5, is formed at an outer-enclosure section O of the resin mold section 9 positioned outside a lamination section S of the resin mold section 9 overlapping with the backside 5b of the stage 5 in its thickness direction. Also, thickness dimensions of the outer-enclosure section O of the resin mold section 9 including the protrusion 11 are set to be larger than those obtained by adding the thickness dimension of the stage 5 and that of the lamination section S of the resin mold section 9. COPYRIGHT: (C)2010,JPO&INPIT ...

電力モジュールパッケージ及びその製造方法

Active energy ray-curable pressure-sensitive adhesive for re-release and dicing die-bonding film

Provided is an active energy ray-curable pressure-sensitive adhesive for re-release, which has a small influence on an environment or a human body, can be easily handled, can largely change its pressure-sensitive adhesiveness before and after irradiation with an active energy ray, and can express high pressure-sensitive adhesiveness before the irradiation with the active energy ray and express high releasability after the irradiation with the active energy ray. The active energy ray-curable pressure-sensitive adhesive for re-release includes an active energy ray-curable polymer (P), in which the polymer (P) includes one of a polymer obtained by causing a carboxyl group-containing polymer (P3) and an oxazoline group-containing monomer (m3) to react with each other, and a polymer obtained by causing an oxazoline group-containing polymer (P4) and a carboxyl group-containing monomer (m2) to react with each other.

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

Integrated circuit packaging system with leveling standoff and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a lead; mounting an integrated circuit adjacent the lead; molding an encapsulation encapsulating the lead and the integrated circuit; and forming a leveling standoff protruded from the same surface of the encapsulation as the lead with the integrated circuit between the lead and the leveling standoff electrically isolated from the lead and the integrated circuit.

Integrated circuit packaging system with lead frame etching and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a pre-plated leadframe having a contact pad and a die paddle pad; forming an isolated contact from the pre-plated leadframe and the contact pad; mounting an integrated circuit die over the die paddle pad; and encapsulating with an encapsulation the integrated circuit die and the isolated contact, the encapsulation having a bottom surface which is planar and exposing in the bottom surface only the contact pad and the die paddle pad.

Saw Type Package without Exposed Pad

In one embodiment, a method for manufacturing a saw type pad is provided. The method includes performing a first molding process to form a first molded layer beneath a pad of a lead frame. A semiconductor device is placed on the pad. A second molding process is performed to form a second molded layer. The first molded layer and the second molded layer form an encapsulation to enclose the semiconductor device and the pad. The lead frame is singulated to form an individualized semiconductor package. The pad is not exposed from a bottom surface of the semiconductor package.

Bonded wire semiconductor device

A bonded wire semiconductor device includes a sub-assembly including a semiconductor die having an active face with a set of internal electrical contact elements and an externally exposed set of electrical contact elements. A set of bond wires make respective electrical connections between the internal electrical contact elements and the externally exposed set of electrical contact elements. A molding compound encapsulates the semiconductor die with the active face embedded in the molding compound. The bond wires have the same length. The bond wires are bonded to the internal electrical contact elements and to the externally exposed electrical contact elements at first and second curved arrays and of bond positions respectively. The first and second curved arrays and of bond positions have corresponding concentric shapes.

Termination Structure for Gallium Nitride Schottky Diode

A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer includes a step recess to further enhance the field spreading effect of the termination structure.

Device housing package and electronic apparatus employing the same

A device housing package includes a base body ( 1 ) including, at its upper surface, a placement portion ( 1 a ) of a semiconductor device ( 9 ); a frame body ( 2 ) disposed on the base body ( 1 ) surrounding the placement portion ( 1 a ), including a notch ( 2 b ) formed by cutting a side wall thereof; an input-output terminal ( 3 ) attached to the notch ( 2 b ), including a wiring conductor layer ( 3 a ) electrically connected to the semiconductor device ( 9 ); and a sealing ring ( 5 ) disposed on an upper portion of the frame body ( 2 ). Moreover, side walls of the frame body ( 2 ) have, when seen in a plan view, an outer corner ( 2 c ) of adjacent side walls having a curved surface, the outer corner ( 2 c ) lying within a region overlapping the sealing ring ( 5 ) as seen in a plan view.

Wafer level chip scale package

A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.

Package-on-package assembly with wire bond vias

A structure includes a substrate having a first region and a second region, the substrate also having a first surface and a second surface. Electrically conductive elements are exposed at the first surface within the second region. Wire bonds have bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. At least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane. A bent portion of the at least one wire bond extends away from the axis within the plane. A dielectric encapsulation layer covers portions of the wire bonds such that unencapsulated portions, including the ends, of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer.

Stacked die power converter

A stacked die power converter package includes a lead frame including a die pad and a plurality of package pins, a first die including a first power transistor switch (first power transistor) attached to the die pad, and a first metal clip attached to one side of the first die. The first metal clip is coupled to at least one package pin. A second die including a second power transistor switch (second power transistor) is attached to another side on the first metal clip. A controller is provided by a controller die attached to a non-conductive layer on the second metal clip on one side of the second die.

Semiconductor device package and semiconductor device

A semiconductor device package is disclosed. The package according to one example includes a base having a main surface made of a metal, a dielectric side wall having a bottom surface facing the main surface, a joining material containing silver (Ag) and joining the main surface of the base and the bottom surface of the side wall to each other, a lead made of a metal joined to an upper surface of the side wall on a side opposite to the bottom surface, and a conductive layer not containing silver (Ag). The conductive layer is provided between the bottom surface and the upper surface of the side wall at a position overlapping the lead when viewed from a normal direction of the main surface. The conductive layer is electrically connected to the joining material, extends along the bottom surface, and is exposed from a lateral surface of the side wall.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a lead frame comprising a first terminal and a second terminal for grounding, a sealing resin which covers the lead frame, an exposed part which is a part of the second terminal and is exposed from the sealing resin and a conductive material which covers the surface of the sealing resin and contacts the second terminal at the exposed part. 1. A semiconductor device comprising:a lead frame comprising a first terminal and a second terminal for grounding;a sealing resin which covers the lead frame;an exposed part which is a part of the second terminal and is exposed from the sealing resin; anda conductive material which covers the surface of the sealing resin and contacts the second terminal at the exposed part.2. The semiconductor device according to claim 1 ,wherein the first terminal and the second terminal are arranged at an end of the semiconductor device,the second terminal is higher than the first terminal at the end, andthe sealing resin comprises a thin wall part at the end, whose height is equal to that of the second terminal at the end.3. The semiconductor device according to claim 2 ,wherein the second terminal comprises:a third terminal which is comprised by the lead frame and has the same height as the first terminal; anda conductive piece which is disposed on the surface of the third terminal.4. The semiconductor device according to claim 2 ,wherein the lead frame comprises a die pad for mounting a semiconductor chip, andthe second terminal is electrically conducted with the die pad.5. The semiconductor device according to claim 2 ,wherein the exposed part and the thin wall part are formed so as to enclose the semiconductor chip, andthe conductive material covers the surfaces of the exposed part and the thin wall part which enclose the semiconductor chip.6. The semiconductor device according to claim 1 ,wherein the second terminal is higher than the first terminal,the second terminal is aligned with the sealing resin in ...

SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE

A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode. 1. A semiconductor component having at least first and second terminals , comprising:a leadframe having first and second opposing sides, a device receiving area, and a first lead integrally formed with the leadframe;an insulated metal substrate having a first surface and a second surface, the second surface coupled to the leadframe;a first semiconductor chip mounted to the insulated metal substrate, the first semiconductor chip having first and second surfaces, a first gate bond pad, a first source bond pad, and a first drain bond pad, the first semiconductor chip configured from a III-N semiconductor material, wherein the second surface of the first semiconductor chip is coupled to the insulated metal substrate; anda second semiconductor chip mounted to the first semiconductor chip and having first and second surfaces, an anode formed from the first surface and a cathode formed from the second surface, wherein the cathode is coupled to the first source bond pad.2. The semiconductor component of claim 1 , further including a second lead that is electrically isolated from the leadframe and wherein the first gate bond pad is electrically coupled to ...

SOLID TOP TERMINAL FOR DISCRETE POWER DEVICES

A solid top terminal for discrete power devices. In one embodiment, an apparatus is formed that includes a first die comprising a transistor, which in turn includes a first electrode such as an emitter. The apparatus also includes a first conductor sintered to an electroplated second conductor such as a solid top terminal. Importantly, the first conductor is electrically coupled to the first electrode. 1. An apparatus comprising:a first die comprising a transistor, the transistor comprising a first electrode; anda first conductor sintered to an electroplated second conductor;wherein the first conductor is electrically coupled to the first electrode.2. The apparatus of wherein the second conductor is electroplated with a conductive material claim 1 , and wherein the first conductor also comprises the conductive material.3. The apparatus of wherein the conductive material comprises silver.4. The apparatus of further comprising:a package;wherein the package fully contains the first die and the first conductor;wherein the package partially contains the electroplated second conductor such that a portion of the electroplated second conductor extends from the package.5. The apparatus of wherein the first conductor was formed on the die before the die was cut from a wafer that comprises a plurality of dies claim 1 , and wherein the first conductor and the electroplated second conductor were sintered together after the die was cut from the wafer.6. The apparatus of wherein the transistor comprises an insulated-gate bipolar transistor (IGBT) claim 1 , and wherein the first electrode comprises a collector of the IGBT.7. The apparatus of wherein the first conductor comprises a first pad that was formed on the die before the die was cut from a wafer comprising a plurality of dies claim 1 , wherein the electroplated second conductor comprises a first element and an integrally connected second element that extends at a non-zero angle from the first element claim 1 , wherein the ...

ISOLATOR INTEGRATED CIRCUITS WITH PACKAGE STRUCTURE CAVITY AND FABRICATION METHODS

In described examples, an integrated circuit includes a leadframe structure, which includes electrical conductors. A first coil structure is electrically connected to a first pair of the electrical conductors of the leadframe structure. The first coil structure is partially formed on a semiconductor die structure. A second coil structure is electrically connected to a second pair of the electrical conductors of the leadframe structure. The second coil structure is partially formed on the semiconductor die structure. A molded package structure encloses portions of the leadframe structure. The molded package structure exposes portions of the first and second pairs of the electrical conductors to allow external connection to the first and second coil structures. The molded package structure includes a cavity to magnetically couple portions of the first and second coil structures. 1. An integrated circuit , comprising:a leadframe structure, including electrical conductors;a first coil structure electrically connected to a first pair of the electrical conductors of the leadframe structure, the first coil structure partially formed on a semiconductor die structure;a second coil structure electrically connected to a second pair of the electrical conductors of the leadframe structure, the second coil structure partially formed on the semiconductor die structure; anda molded package structure enclosing portions of the leadframe structure, the molded package structure exposing portions of the first and second pairs of the electrical conductors to allow external connection to the first and second coil structures, the molded package structure including a cavity to magnetically couple portions of the first and second coil structures.2. The IC of claim 1 , wherein the cavity is sealed.3. The IC of claim 1 , wherein portions of the first and second coil structures extend in the cavity.4. The IC of claim 3 , wherein the molded package structure encloses portions of the first and ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor element circuit, a conductive support and a sealing resin. The conductive support includes a die pad, first terminals spaced in a first direction, second terminals spaced in the first direction and opposite to the first terminals in a second direction perpendicular to the first direction, and a support terminal connected to the die pad. The sealing resin encapsulates portions of the first and second terminals, a portion of the support terminal, the semiconductor element circuit and the die pad. The sealing resin has two first side surfaces spaced apart in the second direction and two second side surfaces spaced apart in the first direction. The first terminals and second terminals are exposed from the first side surfaces, while none of the elements of the conductive support is exposed from the second side surfaces. 132-. (canceled)33. A semiconductor device comprising:a first lead frame formed integral with first two terminals respectively extending from the first lead frame, the first two terminals including respective curved portions curved so that edges of the first two terminals are placed in line with other lead terminals than the first two terminals in a plain view, each of the respective curved portions having two mutually opposing and continuously curved edges each having a center of curvature located on a same side of said each edge in plan view as proceeding along said each edge;a first elongated semiconductor chip mounted on the first lead frame and having a first edge and a second edge in plan view, the first edge being parallel to a longitudinal direction of the first elongated semiconductor chip and greater in length than the second edge, the second edge being perpendicular to the first edge;an isolator chip mounted on the first lead frame;a second lead frame formed with second two terminals respectively extending from the second lead frame, the second two terminals are curved so that edges of the second ...

ISOLATION DEVICE AND METHOD OF TRANSMITTING A SIGNAL ACROSS AN ISOLATION MATERIAL USING WIRE BONDS

An isolation system and isolation device are disclosed. An illustrative isolation device is disclosed to include a transmitter circuit, a detector circuit, a first wire bond, and a second wire bond. The detector circuit is configured to generate a first current in accordance with a first signal. The first wire bond is configured to receive the first current from the transmitter circuit to generate a magnetic flux. The second wire bond is configured to receive the magnetic flux. An induced current in the second wire bond is then detected in the detector circuit. The detector circuit is configured to generate a reproduced first signal, as an output of the detector circuit. 1. A device for transmitting a first signal from a first circuit to a second circuit , comprising:a transmitter circuit configured to generate a first current in accordance with a first signal;a first elongated conducting element configured to generate a magnetic field when the first current flows through the first elongated conducting element;a second elongated conducting element adjacent to the first elongated conducting element so as to receive the magnetic field, wherein the second elongated conducting element is configured to generate an induced current when the magnetic field is received; anda receiver circuit configured to receive the induced current as an input, and configured to generate a reproduced first signal as an output of the receiver circuit.2. The device of claim 1 , further comprising a third elongated conducting element extending substantially in parallel with the first elongated conducting element and the second elongated conducting element claim 1 , and wherein the third elongated conducting element is grounded on one end so as to shield the second elongated conducting element from an electric field generated from the first elongated conducting element.3. The device of claim 2 , further comprising a fourth elongated conducting element that is grounded on one end claim 2 , ...

SEMICONDUCTOR PACKAGE

Disclosed is a semiconductor package including a lead frame with a chip pad and a lead, a semiconductor chip may be disposed on the lead frame, and an encapsulating layer may be disposed on the lead frame. The chip pad may include a center region and an edge region, and the lead may include a first region and a second region between the edge region of the chip pad and the first region of the lead. The encapsulating layer may cover the semiconductor chip and may extend between the chip pad and the lead to cover a bottom surface of the edge region of the chip pad and a bottom surface of the second region of the lead. 1. A semiconductor package , comprising:a lead frame comprising a chip pad and a lead, the chip pad including a center region and an edge region, the lead including a first region and a second region between the edge region of the chip pad and the first region of the lead;a semiconductor chip disposed on the lead frame; andan encapsulating layer disposed on the lead frame,wherein the encapsulating layer covers the semiconductor chip and extends between the chip pad and the lead to cover a bottom surface of the edge region of the chip pad and a bottom surface of the second region of the lead.2. The semiconductor package of claim 1 , wherein the encapsulating layer is provided to expose the center region of the chip pad and the first region of the lead.3. The semiconductor package of claim 1 , further comprising a solder plate provided on a bottom surface of the center region of the chip pad and a bottom surface of the first region of the lead.4. The semiconductor package of claim 3 , wherein the encapsulating layer comprises:a first portion covering the semiconductor chip and filling a space between the chip pad and the lead; anda second portion disposed on the bottom surface of the edge region of the chip pad and the bottom surface of the second region of the lead,wherein the solder plate is thicker than the second portion of the encapsulating layer.5. ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

An aspect of the present disclosure provides a method of manufacturing a semiconductor device. The method includes: preparing a first semiconductor element and a second semiconductor element, each of the first semiconductor element and the second semiconductor element having an element main surface and an element back surface that face opposite sides to each other; die bonding the element back surface of the first semiconductor element to a pad main surface by using a first solder; and die bonding the element back surface of the second semiconductor element to the pad main surface by using a second solder having a melting point lower than a melting point of the first solder, after die bonding the element back surface of the first semiconductor element to the pad main surface by using the first solder. 1. A method of manufacturing a semiconductor device , the method including:preparing a lead frame, the lead frame including a first lead including a pad and a first terminal, the pad including a pad main surface and a pad back surface that face opposite sides to each other in a first direction, and the first terminal extending from the pad along a second direction that is perpendicular to the first direction;preparing a first semiconductor element and a second semiconductor element, each of the first semiconductor element and the second semiconductor element having an element main surface and an element back surface that face opposite sides to each other;die bonding the element back surface of the first semiconductor element to the pad main surface by using a first solder; anddie bonding the element back surface of the second semiconductor element to the pad main surface by using a second solder having a melting point lower than a melting point of the first solder, after die bonding the element back surface of the first semiconductor element to the pad main surface by using the first solder.2. The method of manufacturing a semiconductor device according to claim 1 , ...

Semiconductor power device including wire or ribbon bonds over device active region

A semiconductor power device including a base plate; an input lead; an output lead; a field effect transistor (FET) power die disposed over the base plate, wherein the FET power die includes a set of source fingers, a set of drain fingers, and a set of gate fingers disposed directly over an active region, wherein the gate fingers are configured to receive an input signal from the input lead, and wherein the FET power die is configured to process the input signal to generate an output signal at the drain fingers for routing to the output lead; and electrical conductors (wirebonds or ribbons) bonded to the source and/or drain directly over the active region of the FET power die. The electrical conductors produce additional thermal paths between the active region and the base plate for thermal management of the FET power die.

Power device package structure

A package structure of a power device includes a substrate having a first circuit, a first power device, a second power device, an insulation film having a second circuit, at least one electronic component, and a package. The first power device, the second power device, and the insulation film are disposed on the substrate. The first power device and the second power device are directly electrically connected to each other via the first circuit of the substrate. The electronic component is disposed on the insulation film. The package encapsulates the substrate, the first power device, the second power device, and the electronic component.

Doherty amplifier

A package ( 1 ) includes first and second input terminals ( 2,3 ) which are adjacent to each other, and first and second output terminals ( 4,5 ) which are adjacent to each other. A first input matching circuit ( 6 ), a first delay circuit ( 7 ), a second input matching circuit ( 8 ), a first amplifier ( 9 ), and a first output matching circuit ( 10 ) are sequentially connected between the first input terminal ( 2 ) and the first output terminal ( 4 ) inside the package ( 1 ). A third input matching circuit ( 11 ), a second amplifier ( 12 ), a second output matching circuit ( 13 ), a second delay circuit ( 14 ), and a third output matching circuit ( 15 ) are sequentially connected between the second input terminal ( 3 ) and the second output terminal ( 5 ) inside the package ( 1 ). First to fourth matching circuits ( 16 - 19 ) are respectively connected to the first input terminal ( 2 ), the second input terminal ( 3 ), the first output terminal ( 4 ) and the second output terminal ( 5 ) outside the package ( 1 ).

Multi-path amplifier circuit or system and methods of implementation thereof

Power amplifiers such as multi-path power amplifiers, systems employing such amplifiers, and methods of implementing amplifiers and amplifier systems are disclosed herein. In one example embodiment, a multi-path power amplifier includes a first semiconductor die with an integrated first transistor having a first source-to-drain pitch, and a second semiconductor die with an integrated second transistor having a second source-to-drain pitch, where the second source-to-drain pitch is smaller than the first source-to-drain pitch by at least 30 percent. In another example embodiment, a Doherty amplifier system includes a first semiconductor die with a first physical die area to total gate periphery ratio, and a second semiconductor die with a second physical die area to total gate periphery ratio, where the second physical die area to total gate periphery ratio is smaller than the first physical die area to total gate periphery ratio by at least 30 percent.

THERMAL ENHANCEMENT FOR QUAD FLAT NO LEAD (QFN) PACKAGES

Integrated circuit packages with enhanced thermal characteristics are provided. For example, in embodiments, a QFN (quad flat no lead) package includes a die pad that extends to at least one pinless edge of the QFN package body. A portion of the die pad further extends towards a top surface of the QFN package body. By doing so, a low impedance thermal path from a die included in the QFN package to the top of the QFN package body is formed, which causes heat generated by the die to dissipate from one or more sides and the top of the QFN package, and ultimately to the surrounding environment. Furthermore, the path travelled by the heat in a circuit board coupled to the QFN package is shortened, thereby protecting electrical components coupled thereto. 1. A quad flat no-lead (QFN) package , comprising: a die pad having one or more first surfaces and a second surface opposing the one or more first surfaces of the die pad, a first of the one or more first surfaces of the die pad configured to mount an integrated circuit die, the second surface of the die pad forming a portion of the second surface of the body, and', 'a plurality of pins peripherally positioned along a subset of the perimeter edges of the second surface of the body, at least one of the perimeter edges being pinless; and, 'a body having opposing first and second surfaces and a plurality of perimeter edges, the body comprisingthe die pad extending to at least one pinless perimeter edge of the body.2. The QFN package of claim 1 , wherein a second of the one or more first surfaces of the die pad forms a first portion of the first surface of the body.3. The QFN package of claim 2 , wherein the second of the one or more first surfaces of the die pad is configured to mount a heat sink.4. The QFN package of claim 2 , further comprising:an encapsulating material that encapsulates the integrated circuit die and the first of the one or more surfaces of the die pad, a surface portion of the encapsulating material ...

SEMICONDUCTOR MODULE AND POWER CONVERTER

A semiconductor module includes an insulating substrate including an insulating layer, a first metal pattern formed on an upper surface of the insulating layer, and a second metal pattern formed on a lower surface of the insulating layer, a semiconductor chip that is formed of SiC and is fixed to the first metal pattern with a first metal joining member, and a heat sink that is fixed to the second metal pattern with a second metal joining member, wherein the semiconductor chip has a thickness that is equal to or larger than 0.25 mm and equal to or smaller than 0.35 mm, and the insulating layer has a thickness that is larger than the thickness of the semiconductor chip by a factor of 2.66 inclusive to 5 inclusive. 1. A semiconductor module comprising:an insulating substrate including an insulating layer, a first metal pattern formed on an upper surface of the insulating layer, and a second metal pattern formed on a lower surface of the insulating layer;a semiconductor chip that is formed of SiC and is fixed to the first metal pattern with a first metal joining member; anda heat sink that is fixed to the second metal pattern with a second metal joining member, whereinthe semiconductor chip has a thickness that is equal to or larger than 0.25 mm and equal to or smaller than 0.35 mm,the insulating layer has a thickness that is larger than the thickness of the semiconductor chip by a factor of 2.66 inclusive to 5 inclusive, andno terminals are directly connected to the insulating substrate.2. A semiconductor module comprising:an insulating substrate including an insulating layer, a first metal pattern formed on an upper surface of the insulating layer, and a second metal pattern formed on a lower surface of the insulating layer;a semiconductor chip that is formed of SiC and is fixed to the first metal pattern with a first metal joining member; anda heat sink that is fixed to the second metal pattern with a second metal joining member, whereinthe semiconductor chip has a ...

PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME

The present disclosure provides a package structure, including a semiconductor chip having a magnetic device, wherein the semiconductor chip includes a first surface perpendicular to a thickness direction of the semiconductor chip, a second surface opposite to the first surface, and a third surface connecting the first surface and the second surface, and a first magnetic field shielding at least partially surrounding the third surface. 1. A package structure , comprising:a mounting pad having a mounting surface;a semiconductor chip having a magnetic device, a first surface perpendicular to a thickness direction of the semiconductor chip;', 'a second surface opposite to the first surface, wherein the second surface is attached to the mounting surface of the mounting pad, a total area of the mounting surface is greater than a total area of the second surface; and', 'a third surface connecting the first surface and the second surface; and, 'wherein the semiconductor chip comprisesa first magnetic field shielding at least partially surrounding the third surface, wherein a bottom surface of the first magnetic field shielding is attached to the mounting surface of the mounting pad.2. The package structure of claim 1 , wherein the magnetic device has a magnetic component disposed between an Nmetal layer and an (N+1)metal layer.3. The package structure of claim 1 , wherein a height of the first magnetic field shielding is greater than or equal to a thickness of the magnetic device.4. The package structure of claim 1 , further comprising a bonding surface of the semiconductor chip connected to a lead frame by a bonding wire.5. The package structure of claim 4 , further comprising a second magnetic field shielding over the first surface.6. The package structure of claim 5 , wherein the bonding surface of the semiconductor chip is exposed from the second field shielding.7. The package structure of claim 4 , wherein the first magnetic field shielding is disposed between the ...

Semiconductor device manufacturing method

This invention enhances reliability of an electrical test. A semiconductor device manufacturing method in which a potential (first potential) is supplied by bringing a plurality of first and second test terminals into contact with a plurality of leads, respectively in the step of supplying the potential to the leads (first leads) to carry out the electrical test. The first test terminals come into contact with the leads, individually, and the second test terminals come into contact with the leads in one batch.

SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE

In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure and a second device receiving structure and a contact extension that is common to the first and second device receiving structures. The first device receiving structure includes a device receiving area and the second device receiving structure includes a drain contact area. A III-N based semiconductor chip has a drain bond pad bonded to the drain contact area and a source bond pad bonded to the contact extension and a gate bond pad bonded to an interconnect. A portion of the silicon based semiconductor chip is bonded to the support device receiving area. In accordance with another embodiment, a method for manufacturing the semiconductor component includes coupling a III-N based semiconductor chip to a portion of the support a silicon based semiconductor chip to another portion of the support. 1. A semiconductor component , comprising:a support having a first device receiving structure and a second device receiving structure, the first device receiving structure comprising a device receiving area, the second device receiving structure comprising a drain contact area and a first interconnect, the support further including a contact extension, the contact extension common to the first device receiving structure and the second device receiving structure;a first lead spaced apart from the support;a first semiconductor chip having a first surface and a second surface, wherein a first gate bond pad extends from a first portion of the first surface, a source bond pad extends from a second portion of the first surface, and a drain bond pad extends from a third portion of the first surface, the first gate bond pad of the first semiconductor chip coupled to the first interconnect of the second device receiving structure, the drain bond pad coupled to the drain contact area of the second device receiving structure, and the source bond pad of the first ...

Semiconductor component and method of manufacture

A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode.

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer. 1. A structure comprising:a substrate having a first region and a second region, the substrate also having a first surface and a second surface remote from the first surface, wherein the first surface extends in first and second lateral directions to define a first plane;electrically conductive elements exposed at the first surface of the substrate within the second region;wire bonds having bases bonded to respective ones of the conductive elements and free ends remote from the substrate and remote from the bases, at least one of the wire bonds having a shape such that the at least one wire bond defines an axis between the free end and the base thereof coincident with a side surface of the at least one wire bond and such that the at least one wire bond defines a second plane, a bent portion of the at least one wire bond extending away from the axis within the second plane, wherein the entire at least one wire bond is positioned on one side of the axis and a substantially straight portion of the at least one wire bond extends between the free end ...

Pre-Plating of Solder Layer on Solderable Elements for Diffusion Soldering

A pre-soldered circuit carrier includes a carrier having a metal die attach surface, a plated solder region on the metal die attach surface, wherein a maximum thickness of the plated solder region is at most 50 μm, the plated solder region has a lower melting point than the first bond pad, and the plated solder region forms one or more intermetallic phases with the die attach surface at a soldering temperature that is above the melting point of the plated solder region.

Semiconductor device and a method for manufacturing a semiconductor device

According to various embodiments, a semiconductor device may include: at least one first contact pad on a front side of the semiconductor device; at least one second contact pad on the front side of the semiconductor device; a layer stack disposed at least partially over the at least one first contact pad, wherein the at least one second contact pad is at least partially free of the layer stack; wherein the layer stack includes at least an adhesion layer and a metallization layer; and wherein the metallization layer includes a metal alloy and wherein the adhesion layer is disposed between the metallization layer and the at least one first contact pad for adhering the metal alloy of the metallization layer to the at least one first contact pad.

Double-Encapsulated Power Semiconductor Module and Method for Producing the Same

One aspect relates to a power semiconductor module. The module includes a module housing, a substrate, and a semiconductor chip attached to the substrate. The semiconductor chip is disposed in the module housing. A dielectric first encapsulation is disposed in the module housing, in physical contact with both the semiconductor chip and the substrate and has a first modulus of elasticity. A dielectric second encapsulation is disposed in the module housing and has a second modulus of elasticity. The first encapsulation is a polymer and disposed between the substrate and the second encapsulation. The semiconductor chip is disposed between the first encapsulation and the substrate. Further, the first modulus of elasticity is greater than the second modulus of elasticity, 1. A power semiconductor module , comprising:a module housing;a substrate;a semiconductor chip attached to the substrate and disposed in the module housing;a dielectric first encapsulation disposed in the module housing, in physical contact with both the semiconductor chip and the substrate, and having a first modulus of elasticity;a dielectric second encapsulation disposed in the module housing and having a second modulus of elasticity,wherein the first encapsulation is a polymer and disposed between the substrate and the second encapsulation,wherein the semiconductor chip is disposed between the first encapsulation and the substrate,wherein the first modulus of elasticity is greater than the second modulus of elasticity.2. The power semiconductor module of claim 1 , wherein the first modulus of elasticity is claim 1 , at a temperature of 25° C. claim 1 , more than 0.14 MPa or more than 1 GPa.3. The power semiconductor module of claim 1 , wherein the first encapsulation adjoins the second encapsulation.4. The power semiconductor module of claim 1 , wherein the second modulus of elasticity is claim 1 , ata temperature of 25° C. claim 1 , less than 0.1 MPa.5. The power semiconductor module of claim 1 , ...

SEMICONDUCTOR DEVICE AND ANTENNA DEVICE

A semiconductor device according to the present invention includes: a semiconductor element; a first metal body having a die pad to which the semiconductor element is mounted, the semiconductor element being mounted on a die bond surface of the die pad; a second metal body which has a wire bond pad connected to a signal electrode of the semiconductor element via a wire, and is provided on the same side as the die bond surface such that the second metal body is separated from the first metal body and covered by the first metal body, the second metal body forming a transmission line together with the first metal body; and a molding resin holding the first metal body and the second metal body such that a surface of the first metal body opposite to the die bond surface is exposed. 1. A semiconductor device comprising:a semiconductor element;a first metal body having a die pad portion to which the semiconductor element is mounted, the semiconductor element being mounted on a die bond surface of the die pad portion;a second metal body which has a wire bond pad portion connected to a signal electrode of the semiconductor element via a wire, and is provided on a same side as the die bond surface such that the second metal body is separated from the first metal body and covered by the first metal body, the second metal body forming a transmission line together with the first metal body; anda molding resin holding the first metal body and the second metal body such that a surface of the first metal body opposite to the die bond surface is exposed, whereinthe exposed surface of the first metal body protrudes by a predetermined amount from an outer shape of the molding resin.2. The semiconductor device according to claim 1 , whereinthe molding resin holds the first metal body and the second metal body such that the die bond surface and the wire bond pad portion are exposed.3. The semiconductor device according to claim 1 , whereinthe transmission line is a microstrip line.4. ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a first and second semiconductor chips, a resistive component, and a semiconductor chip including a first circuit coupled to electrodes on both ends of the resistive component. A sealing body has a first long side, a second side, a third short side, and a fourth short side. In a Y-direction, each of the first and second semiconductor chips is disposed at a position closer to the first side than to the second side, while the semiconductor chip is disposed at a position closer to the second side than to the first side. Also, in the Y-direction, the resistive component, the second semiconductor chips, and the first semiconductor chips are arranged in order of increasing distance from the third side toward the fourth side, while the semiconductor chip is disposed at a position closer to the third side than to the fourth side. 1. A semiconductor device , comprising:a plurality of terminals including a first terminal coupled to a first potential, a second terminal coupled to a second potential lower than the first potential, and a third terminal coupled to a ground potential;a plurality of first semiconductor chips each including a first power transistor coupled to the first terminal;a plurality of second semiconductor chips each including a second power transistor coupled to the second terminal;a resistive component including a first electrode electrically coupled to the second power transistor, a second electrode opposite to the first electrode, and a resistive element coupled to the first and second electrodes;a third semiconductor chip including an amplification circuit electrically coupled to the first and second electrodes of the resistive component; anda sealing body including a first long side extending in a first direction in plan view, a second long side opposite to the first long side in plan view, a first short side extending in a second direction crossing the first direction in plan view, and a second short side opposite to the ...

SOLID STATE LIGHT EMITTER PACKAGE, A LAMP, A LUMINAIRE AND A METHOD OF MANUFACTURING A SOLID STATE LIGHT EMITTER PACKAGE

A solid state light emitter package (), a lamp, a luminaire and a method of manufacturing the solid state light emitter package are provided. The solid state light emitter package comprising a solid state light emitter die (), a first and second lead frame (), an electrical insulating material (), a thermal element () and a bridging element (). The first and second lead frame are electrically isolated from each other and provide power to said die. Said die is at least partially provided on the first lead frame. The thermal element is in between the first and second lead frame and is electrically isolated by the electrical insulating material from said lead frames. The thermal element is at least one of a heat absorber or a heat spreader. The bridging element bridges the electrical insulating material and the thermal element and provides an electrical connection between said die and the second lead frame. 1. A solid state light emitter package comprisinga solid state light emitter die,a first lead and a second lead frame being electrically isolated from the first lead frame, said lead frames are for receiving power from an external power source and are arranged to provide received power to the solid state light emitter die, the solid state light emitter die being at least partially provided on the first lead frame,an electrical insulating material,a thermal element being arranged in between the first lead frame and the second lead frame and being electrically isolated by the electrical insulating material from the first lead frame and from the second lead frame and the thermal element being at least one of a heat absorber or a heat spreader, the thermal element not being in direct thermal contact with a solid state light emitter die, anda bridging element bridging the electrical insulating material and the thermal element in between the first lead frame and the second lead frame and the bridging element is for obtaining an electrical connection between the solid ...

Package-on-package Assembly With Wire Bond Vias

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a die pad, a semiconductor chip with a bonding pad being formed, a lead one end of which is located in the vicinity of the semiconductor chip, a coupling wire that connects an electrode and the lead, and a sealing body that seals the semiconductor chip, the coupling wire, a part of the lead, and a part of the die pad. A lower surface of the die pad is exposed from a lower surface of the sealing body, the die pad and the coupling wire are comprised of copper, and a thickness of the semiconductor chip is larger than the sum of a thickness of the die pad and a thickness from an upper surface of the semiconductor chip to an upper surface of the sealing body. 117-. (canceled)18. A semiconductor device comprising: a first upper surface including a chip mounting region and a first bent part, and', 'a first lower surface located on an opposite side from the first upper surface;, 'a die pad that includes a second upper surface,', 'a second lower surface located on an opposite side from the second upper surface, and', 'an electrode formed over the second upper surface;, 'a semiconductor chip that is mounted in the chip mounting region and includesa sealing body that includes a third upper surface and a third lower surface located on an opposite side from the third upper surface, and that seals the semiconductor chip and the first upper surface of the die pad;a lead having a first portion that is located in the sealing body and a second portion that is located outside the sealing body; anda wire that is located in the sealing body and connects the electrode of the semiconductor chip and the first portion of the lead,wherein the first lower surface of the die pad is exposed from the third lower surface of the sealing body,wherein the first bent part is located in the sealing body,wherein the first bent part extends from the chip mounting region in a first direction,wherein the electrode of the semiconductor chip and the first portion of the lead ...

Electronic devices in semiconductor package cavities

In examples, a semiconductor device comprises a semiconductor package including a mold compound covering a semiconductor die. The semiconductor package has a surface and a cavity formed in the surface. The semiconductor device comprises an electronic device positioned within the cavity, the electronic device coupled to the semiconductor die via a conductive terminal extending through the mold compound.

SEMICONDUCTOR DEVICE

A semiconductor device includes: a single die pad made of a metal or metal alloy and having a first surface, a second surface that is an opposite side of the first surface, and a pair of ground leads protruding from an end edge in plan view; a signal lead arranged between the ground leads; a plurality of leads arranged around the die pad in plan view; a semiconductor chip mounted on the second surface; bonding wires connecting a signal pad of the chip and the signal lead and connecting a ground pad of the chip and the ground leads; and a mold resin covering the die pad, the signal lead, the plurality of leads, the chip, and the bonding wires; wherein an interval between the signal lead and each of the ground leads is narrower than an interval between the plurality of leads. 1. A semiconductor device comprising:a single die pad having a first surface, a second surface that is an opposite side of the first surface, and a pair of ground leads protruding from an end edge in plan view, the die pad being made of a metal or a metal alloy;a signal lead that is arranged between the pair of ground leads;a plurality of leads that are arranged around the die pad in plan view;a semiconductor chip that is mounted on the second surface;a plurality of bonding wires connecting a signal pad of the semiconductor chip and the signal lead and connecting a ground pad of the semiconductor chip and the pair of ground leads; anda mold resin covering the die pad, the signal lead, the plurality of leads, the semiconductor chip, and the plurality of bonding wires;wherein an interval between the signal lead and each of the pair of ground leads is narrower than an interval between the plurality of leads.2. The semiconductor device according to claim 1 , wherein an interval between the signal lead and the die pad is narrower than an interval between the plurality of leads and the die pad.3. A semiconductor device according comprising:a single die pad having a first surface and a second surface ...

LEAD FRAME-BASED SEMICONDUCTOR PACKAGE

A semiconductor package includes: a lead frame having a plurality of blocks of uniform size and laterally spaced apart from one another with uniform spacing; a first semiconductor die attached to a first group of the blocks; electrical conductors connecting a plurality of input/output (I/O) terminals of the first semiconductor die to a second group of the blocks, at least some blocks of the second group being laterally spaced outward from the blocks of the first group; and a mold compound encapsulating the first semiconductor die and the electrical conductors. Corresponding methods of producing the semiconductor package are also described. 1. A semiconductor package , comprising:a lead frame comprising a plurality of blocks of uniform size and laterally spaced apart from one another with uniform spacing;a first semiconductor die attached to a first group of the blocks;electrical conductors connecting a plurality of input/output (I/O) terminals of the first semiconductor die to a second group of the blocks, at least some blocks of the second group being laterally spaced outward from the blocks of the first group; anda mold compound encapsulating the first semiconductor die and the electrical conductors.2. The semiconductor package of claim 1 , wherein the uniform size and the uniform spacing are the same.3. The semiconductor package of claim 1 , wherein the uniform spacing defines an internal pitch within the semiconductor package claim 1 , and wherein the semiconductor package has a different pitch than the internal pitch.4. The semiconductor package of claim 1 , wherein the uniform size plus the uniform spacing defines a pitch of the semiconductor package claim 1 , and wherein the pitch is 0.4 mm claim 1 , 0.5 mm claim 1 , 0.65 mm claim 1 , or 1.27 mm.5. The semiconductor package of claim 1 , wherein the first semiconductor die overhangs one or more of the blocks to which the first semiconductor die is attached.6. The semiconductor package of claim 1 , wherein the ...

Semiconductor device

A semiconductor device includes a first semiconductor chip and a second semiconductor chip to which different power-supply voltages are supplied, connection bonding wires connecting the first semiconductor chip and the second semiconductor chip to each other, and a sealing resin provided to fill a gap between a first lead frame on which the first semiconductor chip is mounted and a second lead frame on which the second semiconductor chip is mounted so as to cover the respective circumferences of the first semiconductor chip and the second semiconductor chip. The respective surfaces of the first lead frame and the second lead frame in the regions opposed to each other are covered with an insulating protection film including a material having higher electrical breakdown voltage than a material included in the sealing resin.

SEMICONDUCTOR MODULE

A semiconductor module is provided in which a semiconductor element is mounted and a plurality of outside connecting modules are drawn from a side of a mold resin portion. To ensure sufficient space for a holding tool used in mounting the semiconductor module to a device with a simple structure, holding side portions are provided for at least two opposing corner portions of corner portions between adjacent sides of the mold resin portion. 16-. (canceled)7. A semiconductor module in which a semiconductor element is mounted and a plurality of outside connecting modules are drawn from a side of a mold resin portion , characterized in that ,the mold resin portion of the semiconductor module includes a plurality of corner portions, and a holding side portion is provided for each of at least two opposing corner portions of the corner portions.8. The semiconductor module according to claim 7 , characterized in that the holding side portion is integrally molded with the mold resin portion.9. The semiconductor module according to claim 7 , characterized in that the mold resin portion of the semiconductor module is formed in a box shape or a polygonal shape having sides more than four.10. The semiconductor module according to claim 7 , characterized in that the holding side portions provided for the at least two opposing corners are formed in parallel with or not in parallel with each other.11. The semiconductor module according to claim 9 , characterized in that the holding side portions provided for the at least two opposing corners are formed in parallel with or not in parallel with each other.12. The semiconductor module according to claim 7 , characterized in that the plurality of outside connecting terminals are placed only in a side of the mold resin portion.13. The semiconductor module according to claim 9 , characterized in that the plurality of outside connecting terminals are placed only in a side of the mold resin portion.14. The semiconductor module according to ...

WIRELESS COMMUNICATION LINK USING NEAR FIELD COUPLING

A memory device may include an array of closely spaced memory integrated circuits that communicate wirelessly over at least two frequencies using near field coupling. 1. An apparatus comprising:a substrate having an upper surface, a lower surface parallel to the upper surface, and a plurality of side surfaces perpendicular to and extending between the upper surface and the lower surface; and a first portion of the loop antenna on the upper surface,', 'a second portion of the loop antenna on the lower surface, and', 'a via coupling the first portion of the loop antenna to the second portion of the loop antenna., 'a plurality of loop antennas, each loop antenna of the plurality of loop antennas parallel to a respective side surface of the plurality of side surfaces and transversely oriented to the upper surface and the lower surface, each loop antenna of the plurality of loop antennas comprising2. The apparatus of claim 1 , wherein the upper surface of the substrate comprises an upper loop antenna.3. The apparatus of claim 2 , wherein the lower surface of the substrate comprises a lower loop antenna.4. The apparatus of claim 3 , wherein each loop antenna of the plurality of loop antennas is transversely oriented relative the upper loop antenna and the lower loop antenna.5. The apparatus of claim 3 , wherein each loop antenna of the plurality of loop antennas further comprises a third portion of the loop antenna on the upper surface.6. The apparatus of claim 5 , wherein each loop antenna of the plurality of loop antennas further comprises a second via configured to electrically couple the third portion of the loop antenna to the second portion of the loop antenna.7. The apparatus of claim 6 , wherein the first and third portions comprise conductive strips plated or printed on the upper surface.8. The apparatus of claim 6 , wherein the second portion comprises an internal conductive layer plated or printed on the lower surface.9. The apparatus of claim 3 , further ...

THERMOSETTING SILICONE RESIN COMPOSITION AND DIE ATTACH MATERIAL FOR OPTICAL SEMICONDUCTOR DEVICE

A thermosetting silicone resin composition contains the following components (A-1) to (D): (A-1) an alkenyl group-containing linear organopolysiloxane; (A-2) a branched organopolysiloxane shown by (RSiO)(RSiO)(SiO)(1) ; (B-1) a branched organohydrogenpolysiloxane shown by (HRSiO)(RSiO)(SiO)(2) ; (B-2) a linear organohydrogenpolysiloxane shown by (RSiO)(HRSiO)(RSiO)(3) ; (C) an adhesion aid which is an epoxy group-containing branched organopolysiloxane; and (D) a catalyst containing a combination of a zero-valent platinum complex with a divalent platinum complex and/or a tetravalent platinum complex. This provides a thermosetting silicone resin composition which causes little contamination at a gold pad portion and has excellent adhesiveness to a silver lead frame. 2. The thermosetting silicone resin composition according to claim 1 , wherein the divalent platinum complex in the component (D) is bis(acetylacetonato)platinum(II).3. The thermosetting silicone resin composition according to claim 1 , wherein the tetravalent platinum complex in the component (D) is (trimethyl)methylcyclopentadienylplatinum(IV).4. The thermosetting silicone resin composition according to claim 2 , wherein the tetravalent platinum complex in the component (D) is (trimethyl)methylcyclopentadienylplatinum(IV).5. The thermosetting silicone resin composition according to claim 1 , further comprising a diluent (E) which is a hydrocarbon compound being liquid at 25° C. and having a boiling point in a range of 200° C. or more and less than 350° C. under atmospheric pressure (1013 hPa).7. The thermosetting silicone resin composition according to claim 1 , wherein the component (B-1) has a viscosity of 10 Pa·s or more at 25° C. as measured by a method described in JIS K 7117-1:1999.8. The thermosetting silicone resin composition according to claim 1 , wherein{'sup': 2', '2, 'sub': 2', '1/2', '3', '1/2', '4/2, 'the component (B-1) is a co-hydrolysis condensate of an HRSiOunit source, an RSiOunit ...

SEMICONDUCTOR MODULE AND SEMICONDUCTOR MODULE MANUFACTURING METHOD

A semiconductor module includes a semiconductor element made of a wide-bandgap semiconductor, the semiconductor element having an upper surface with an edge, a buffer member that covers the edge of the upper surface of the semiconductor element, and a sealing resin that seals the semiconductor element and the buffer member. The buffer member has a thickness equal to or larger than 50 μm. 1. A semiconductor module , comprising:a semiconductor element made of a wide-bandgap semiconductor, the semiconductor element having an upper surface with an edge;a buffer member that covers said edge; anda sealing resin that seals the semiconductor element and the buffer member,wherein the buffer member has a thickness equal to or larger than 50 μm.2. The semiconductor module according to claim 1 , whereinthe semiconductor element has a rectangular shape in a plan view of the semiconductor module and having edges at four corners of the upper surface, andthe buffer member covers at least the four corners of the upper surface of the semiconductor element.3. The semiconductor module according to claim 1 , wherein the semiconductor element is made of one of silicon carbide (SiC) claim 1 , gallium nitride (GaN) or diamond.4. The semiconductor module according to claim 1 , wherein the buffer member contains at least one of polyimide claim 1 , polyamide or polyamide-imide as a main component.5. The semiconductor module according to claim 1 , wherein the buffer member has an elasticity coefficient lower than an elasticity coefficient of the sealing resin.6. The semiconductor module according to claim 1 , wherein the buffer member covers an entire circumference at the upper surface including the edge of the semiconductor element.7. The semiconductor module according to claim 1 , wherein the buffer member has an elasticity coefficient in a range of 0.5×10GPa to 3 GPa.8. The semiconductor module according to claim 1 , wherein the sealing resin contains at least one of epoxy claim 1 , ...

DICING DIE ATTACH FILM, AND SEMICONDUCTOR PACKAGE USING THE SAME AND METHOD OF PRODUCING SEMICONDUCTOR PACKAGE

A dicing die attach film, including an adhesive layer and a temporary-adhesive layer, the adhesive layer and the temporary-adhesive layer being laminated, 2. The dicing die attach film according to claim 1 , wherein when the adhesive layer is heated at a temperature elevation rate of 5° C./min from 25° C. claim 1 , an elastic modulus G′ before curing in a range of 25 to 80° C. is 10 kPa or more.3. The dicing die attach film according to claim 1 , wherein when the adhesive layer is heated at a temperature elevation rate of 5° C./min from 25° C. claim 1 , a melt viscosity at 120° C. is in a range of 500 to 10 claim 1 ,000 Pa·s.4. The dicing die attach film according to claim 1 , wherein the temporary-adhesive layer is energy ray-curable.5. A method of producing a semiconductor package claim 1 , comprising the steps of:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'a first step of thermocompression bonding the dicing die attach film according to to a back surface of a semiconductor wafer in which at least one semiconductor circuit is formed on a surface so that the adhesive layer is in contact with the back surface of the semiconductor wafer;'}a second step of dicing the semiconductor wafer and the adhesive layer simultaneously to obtain a semiconductor chip with an adhesive layer, the semiconductor chip with an adhesive layer including the semiconductor chip and the adhesive layer on the temporary-adhesive layer;a third step of removing the temporary-adhesive layer from the adhesive layer and thermocompression bonding the semiconductor chip with an adhesive layer and a wiring board via the adhesive layer; anda fourth step of thermally curing the adhesive layer.6. A semiconductor package wherein a semiconductor chip and a wiring board claim 1 , or semiconductor chips are bonded with a thermally curable component of the adhesive layer of the dicing die attach film according to . This application is a Continuation of PCT International Application No. PCT/JP2020/ ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a plurality of chips, which include a plurality of corresponding functional blocks having the same function among the chips, and only one of the corresponding functional blocks having the same function among the chips enables function, and one or more functional blocks enable function in each of the chips, so that the functional blocks are distributed among the chips. 1. A semiconductor package comprising a plurality of chips , whereinthe plurality of chips include a plurality of corresponding functional blocks having the same function among the chips, andonly one of the corresponding functional blocks having the same function among the chips enables function, and one or more functional blocks enable function in each of the chips so that the functional blocks are distributed among the chips.2. The semiconductor package according to claim 1 , wherein the functional blocks are distributed among the chips while the functional block to enable function is changed.3. The semiconductor package according to claim 2 , wherein the functional block to enable function is changed based on the number of start-up times of the semiconductor package.4. The semiconductor package according to claim 2 , wherein the functional block to enable function is changed in accordance with an operation mode of the semiconductor package.5. The semiconductor package according to claim 1 , wherein the chip further includes a temperature detecting unit corresponding to each of the functional block claim 1 , and a determination unit arranged to determine the functional block to enable function based on a result of detection by the temperature detecting unit.6. The semiconductor package according to claim 1 , comprising two chips claim 1 , whereineach of the chips further includes a malfunction monitoring unit arranged to monitor whether or not the functional block has a malfunction, andwhen one of the malfunction monitoring units detects a malfunction, all functional ...

LIGHT EMITTING DIODE PACKAGE HAVING A SMALL LIGHT EMITTING SURFACE

A light emitting diode package, including: a housing, wherein the housing includes a primary cavity, a primary cavity light emitting surface, and a secondary cavity, wherein the secondary cavity is positioned adjacent to the primary cavity; a lead frame associated with the housing; a light emitting diode light source, wherein the light emitting diode light source is associated with the primary cavity of the housing; an encapsulant filled into the primary cavity, wherein the encapsulant is associated with a light converting element; and wherein the ratio of the surface area of the primary cavity light emitting surface to that of the light emitting diode light source is less than 2.0. 1. A light emitting diode package , comprising:a housing, wherein the housing includes a primary cavity, a primary cavity light emitting surface, and a secondary cavity, wherein the secondary cavity is positioned adjacent to the primary cavity;a lead frame associated with the housing;a light emitting diode light source, wherein the light emitting diode light source is associated with the primary cavity of the housing;an encapsulant filled into the primary cavity, wherein the encapsulant is associated with a light converting element; andwherein the ratio of the surface area of the primary cavity light emitting surface to that of the light emitting diode light source is less than 2.0.2. A light emitting diode package , comprising:a housing, wherein the housing includes a primary cavity, a primary cavity light emitting surface, and a secondary cavity, wherein the secondary cavity is positioned adjacent to the primary cavity;a lead frame associated with the housing;a light emitting diode light source, wherein the light emitting diode light source is associated with the primary cavity of the housing;an encapsulant filled into the primary cavity, wherein the encapsulant is associated with a light converting element; andwherein a wire connection is made between the primary and secondary ...

POWER SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREFOR

A lead frame () includes an inner lead (), an outer lead () connected to the inner lead (), and a power die pad (). A power semiconductor device () is bonded onto the power die pad (). A first metal thin line () electrically connects the inner lead () and the power semiconductor device (). Sealing resin () seals the inner lead (), the power die pad (), the power semiconductor device (), and the first metal thin line (). The sealing resin () includes an insulating section () directly beneath the power die pad (). A thickness of the insulating section () is 1 to 4 times a maximum particle diameter of inorganic particles in the sealing resin (). A first hollow () is provided on an upper surface of the sealing resin () directly above the power die pad () in a region without the first metal thin line () and the power semiconductor device (). 1. A power semiconductor apparatus comprising:a lead frame including an inner lead, an outer lead connected to the inner lead, and a power die pad;a power semiconductor device bonded onto the power die pad;a first metal thin line electrically connecting the inner lead and the power semiconductor device; andsealing resin sealing the inner lead, the power die pad, the power semiconductor device, and the first metal thin line,wherein the sealing resin includes an insulating section directly beneath the power die pad,a thickness of the insulating section is 1 to 4 times a maximum particle diameter of inorganic particles in the sealing resin, anda first hollow is provided on an upper surface of the sealing resin directly above the power die pad in a region without the first metal thin line and the power semiconductor device.2. The power semiconductor apparatus according to claim 1 , comprising:a control semiconductor device controlling the power semiconductor device; anda second metal thin line electrically connecting the power semiconductor device and the control semiconductor device,wherein the lead frame includes a control die pad,the ...

Multi-Die Power Semiconductor Device Packaged On a Lead Frame Unit with Multiple Carrier Pins and a Metal Clip

A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to top electrodes of the first and second MOSFET dies, a first row of carrier pins and a second row of carrier pins disposed in-line with the first and second pins respectively for the control die to mount thereon. 1. A power semiconductor device comprising:a lead frame unit, a control die, a first die and a second die, and a metal clip whereinthe lead frame unit comprises a first die paddle and a second die paddle disposed side by side adjacent but separated from each other, a first pin and a first row of carrier pins adjacent to the first die paddle and a second pin and a second row of carrier pins adjacent to the second die paddle;the first and second die paddles each comprises respectively a first transverse edge and a second transverse edge opposite to the first transverse edge, a first longitudinal edge and a second longitudinal edge opposite to the first longitudinal edge, wherein the first pin comprises a bonding area adjacent to and extending along the first transverse edge of the first die paddle, and the second pin comprising a bonding area adjacent to and extending along the second transverse edge of the second die paddle;both of the first row of carrier pins and the second row of carrier pins are positioned at one side of the second longitudinal edges of the first and second die paddles away from the first longitudinal edges, each carrier pin of the first row of carrier pins is substantially parallel to each other and extends from an extension line of the first pin towards a center line between the first transverse edge of the first die paddle and the second transverse edge of the second die paddle, and each carrier pin of the second row of carrier pins is substantially parallel to each ...

ELECTRONIC DEVICE PACKAGING WITH GALVANIC ISOLATION

In a general aspect, an electronic device assembly can include a dielectric substrate having a first surface and a second surface opposite the first surface and a leadframe including: a first leadframe portion including a first plurality of signal leads; and a second leadframe portion including a second plurality of signal leads. The substrate can be coupled with a subset of the first plurality of signal leads and a subset of the second plurality of signal leads. Signal leads of the first plurality of signal leads, other than the subset of the first plurality of signal leads, can be spaced from the dielectric substrate. Signal leads of the second plurality of signal leads, other than the subset of the second plurality of signal leads, can be spaced from the dielectric substrate. The assembly can further include first and second semiconductor die that are electrically coupled with the substrate and the leadframe portions. 1. An electronic device assembly comprising: a first unidirectional isolation channel defined thereon, the first unidirectional isolation channel having an input terminal and an output terminal; and', 'a second unidirectional isolation channel defined thereon, the second unidirectional isolation channel having an input terminal and an output terminal;, 'a dielectric substrate having a first surface and a second surface opposite the first surface, the dielectric substrate including a first leadframe portion including a first plurality of signal leads, a first corner of the first surface of the dielectric substrate being coupled with a first signal lead of the first plurality of signal leads, and a second corner of the first surface of the dielectric substrate being coupled with a second signal lead of the first plurality of signal leads; and', 'a second leadframe portion including a second plurality of signal leads, a third corner of the first surface of the dielectric substrate being coupled with a first signal lead of the second plurality of signal ...

SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR

A semiconductor device includes a semiconductor chip, a lead arranged on a side portion of the semiconductor chip, and a wire, whose one end and another end are bonded to the semiconductor chip and the lead respectively, having a ball portion and a stitch portion wedged in side elevational view on the semiconductor chip and the lead respectively. An angle of approach of the wire to the lead is not less than 50°, and the length of the stitch portion is not less than 33 μm. 1. A semiconductor device , comprising:a semiconductor chip;leads arranged around the semiconductor chip;wires bonded to the semiconductor chip and the leads;an island to which the semiconductor chip is bonded;a chip bonding material interposed between the semiconductor chip and the island to bond the semiconductor chip and the island to each other; anda package covering a part of the island and the leads, whereinin a plan view, the island has a quadrangular shape having four sides that are each skewed relative to respective outer sides of the package,the island includes hanging portions which in the plan view, extend from respective corner portions of the island toward the respective outer sides of the package,in the plan view, each respective lead of the leads has an opposing side opposed to and parallel to a nearest side of the four sides of the island which is nearest to the respective lead out of the four sides of the island, the opposing side located outside an outer perimeter of the semiconductor chip in the plan view, andin the plan view, a first hanging portion of the hanging portions is opposed to and parallel to a first side of the respective lead, a second hanging portion of the hanging portions is opposed to and parallel to a second side of the respective lead, the nearest side of the island is bridged between the first hanging portion and the second hanging portion, and the opposing side of the respective lead is bridged between the first side and the second side.2. The semiconductor ...

Multi-Chip Package

A package includes a package body with a package top side, package footprint side and package sidewalls extending from the package footprint side to the package top side; power semiconductor chips electrically connected in parallel and each having first and second load terminals and being configured to block a blocking voltage and conduct a chip load current between the load terminals; a lead frame structure configured to electrically and mechanically couple the package to a carrier with the package footprint side facing the carrier, the lead frame structure including first outside terminals extending out of the package body for interfacing with the carrier. Each first load terminal is electrically connected, at least by one package body internal connection member, to at least two of the first outside terminals. A horizontally extending conduction layer at the package top side or footprint side is electrically connected with each second load terminal. 1. A package , comprising:a package body with a package top side, a package footprint side and package sidewalls, the package sidewalls extending from the package footprint side to the package top side;a plurality of power semiconductor chips electrically connected in parallel to each other, each power semiconductor chip having a first load terminal and a second load terminal and being configured to block a blocking voltage applied between the first and second load terminals and to conduct a chip load current between the first and second load terminals; each first outside terminal extends out of the package body for interfacing with the carrier; and', 'each first load terminal of the plurality of power semiconductor chips is electrically connected, at least by one package body internal connection member, to at least two of the plurality of first outside terminals; and, 'a lead frame structure configured to electrically and mechanically couple the package to a carrier with the package footprint side facing the carrier, ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

In one embodiment, a semiconductor device includes a substrate, and a first shield member provided on or in the substrate. The device further includes a semiconductor chip provided on the first shield member, and a first wire electrically connected to the semiconductor chip and the substrate. The device further includes a second wire electrically or magnetically connected to the first shield member, and a second shield member provided above the semiconductor chip, electrically insulated from the first wire, and electrically or magnetically connected to the second wire. 1. A semiconductor device comprising:a substrate;a first shield member provided on or in the substrate;a semiconductor chip provided on the first shield member;a first wire electrically connected to the semiconductor chip and the substrate;a second wire electrically or magnetically connected to the first shield member; anda second shield member provided above the semiconductor chip, electrically insulated from the first wire, and electrically or magnetically connected to the second wire.2. The device of claim 1 , wherein a height of a highest portion of the second wire is higher than a height of a highest portion of the first wire.3. The device of claim 1 , wherein the second wire has a linear shape or a belt-like shape.4. The device of claim 1 , whereinthe semiconductor chip comprises a first lateral face, a second lateral face positioned opposite the first lateral face, a third lateral face positioned between the first lateral face and the second lateral face, and a fourth lateral face positioned opposite the third lateral face,the first wire is electrically connected to the semiconductor chip and the substrate on a side of the first or second lateral face, and the second wire is electrically or magnetically connected to the first shield member on a side of the third or fourth lateral face.5. The device of claim 1 , whereinthe semiconductor chip comprises a first lateral face, a second lateral face ...

Electrical device with terminal notches and method for manufacturing the same

An electric device with terminal notches includes a main body, a plurality of SMT leads and a plurality of plating layers. Each of the SMT leads is extended from the main body and ended up with a lead end surface furnished with a terminal notch, where the terminal notch has a notch peripheral surface. Each of the plating layers covers at least the notch peripheral surface of the corresponding SMT lead. In addition, a method for manufacturing the same electric device with terminal notches is also provided.

POWER SEMICONDUCTOR PACKAGE HAVING INTEGRATED INDUCTOR, RESISTOR AND CAPACITOR

A power semiconductor package comprises a lead frame, a low side field-effect transistor (FET), a high side FET, a capacitor, a resistor, an inductor assembly, a first plurality of bonding wires, and a molding encapsulation. In one example, an entirety of the inductor assembly is disposed at a position higher than an entirety of the low side FET, higher than an entirety of the high side FET, and higher than an entirety of the first plurality of bonding wires. In another example, a bottom surface of the low side FET and a bottom surface of the inductor assembly are co-planar. 1. A power semiconductor package comprising: a first die paddle;', 'a second die paddle;', 'a first end paddle; and', 'a second end paddle, wherein the first end paddle and the second end paddle being disposed higher than the first die paddle and the second die paddle;, 'a lead frame comprising'}a low side field-effect transistor (FET) having a bottom surface drain electrode attached to the first die paddle, the low side FET comprising a source electrode and a gate electrode on a top surface of the low side FET;a high side FET having a bottom surface drain electrode attached to the second die paddle, the high side FET comprising a source electrode and a gate electrode on a top surface of the high side FET;a first plurality of bonding wires connecting the top surface source electrode of the high side FET to the first die paddle;an inductor assembly comprising a first terminal and a second terminal, the first terminal stack on the first end paddle and the second terminal stack on the second end paddle;a first lead connecting to the first end paddle; anda second lead connecting to the second end paddle; anda molding encapsulation enclosing the low side FET, the high side FET, the first plurality of bonding wires, the inductor assembly, a majority portion of the first lead, a majority portion of the second lead, and a majority portion of the lead frame.2. The power semiconductor package of claim 1 , ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Reliability of a semiconductor device is improved. 1. A method of manufacturing a semiconductor device , the method comprising the steps of:(a) preparing a semiconductor chip having a pad electrode made of first copper, on a main surface of the semiconductor chip;(b) preparing a base material having a chip mounting portion and a lead;(c) after the step (b), mounting the semiconductor chip in the chip mounting portion; and(d) after the step (c), coupling the pad electrode and the lead by using a wire which is made of second copper and has a ball portion and a wire portion,wherein the step (d) includes the steps of(d-1) exposing the wire and the pad electrode to a reducing gas atmosphere, forming a first hydroxyl layer on a surface of the ball portion, and forming a second hydroxyl layer on a surface of the pad electrode,(d-2) a first bonding step of joining the ball portion to the pad electrode through the first hydroxyl layer and the second hydroxyl layer, and(d-3) after the first bonding step, joining the ball portion to the pad electrode by performing a heat treatment on the semiconductor chip and the base material.2. The method of manufacturing a semiconductor device according to claim 1 ,wherein the reducing gas atmosphere contains nitrogen and hydrogen.3. The method of manufacturing a semiconductor device according to claim 1 ,wherein the second hydroxyl layer is formed on a surface of an oxidized layer formed on a surface of the pad electrode.4. The method of manufacturing a semiconductor device according to claim 3 ,wherein after the step (d-2), a first bonding layer foamed by first hydrogen bond and first ionic bond is formed between the ball portion and the pad electrode.5. The method of manufacturing a semiconductor device according to claim 4 ,wherein the step (d-2) is performed in 130° C.-250° C.6. The method of manufacturing a semiconductor device according to claim 4 ,wherein the first ionic bond included in the first bonding layer is formed of a first ...

SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR

A semiconductor device includes a semiconductor chip, a lead arranged on a side portion of the semiconductor chip, and a wire, whose one end and another end are bonded to the semiconductor chip and the lead respectively, having a ball portion and a stitch portion wedged in side elevational view on the semiconductor chip and the lead respectively. An angle of approach of the wire to the lead is not less than 50°, and the length of the stitch portion is not less than 33 μm. 1. A semiconductor device , comprising:a semiconductor chip;leads arranged around the semiconductor chip;wires bonded to the semiconductor chip and the leads;an island to which the semiconductor chip is bonded;a chip bonding material interposed between the semiconductor chip and the island to bond the semiconductor chip and the island to each other; anda package covering a part of the island and the leads, whereinin a plan view, the island has a quadrangular shape having four sides that are each skewed relative to respective outer sides of the package,the island includes hanging portions which in the plan view, extend from respective corner portions of the island toward the respective outer sides of the package,in the plan view, each respective lead of the leads has an opposing side opposed to a nearest side of the four sides of the island which is nearest to the respective lead out of the four sides of the island, andin the plan view, a first hanging portion of the hanging portions is opposed to a first side of the respective lead, a second hanging portion of the hanging portions is opposed to a second side of the respective lead, the nearest side of the island is bridged between the first hanging portion and the second hanging portion, and the opposing side of the respective lead is bridged between the first side and the second side.2. The semiconductor device according to claim 1 , wherein in the plan view claim 1 , each of the hanging portions extends toward a respective center of centers of ...

FLOATING DIE PACKAGE

A floating die package including a cavity formed through sublimation of a sacrificial die encapsulant and sublimation or separation of die attach materials after molding assembly. A pinhole vent in the molding structure is provided as a sublimation path to allow gases to escape, whereby the die or die stack is released from the substrate and suspended in the cavity by the bond wires only. 1. A semiconductor package comprising:a lead frame including a die paddle and a first plurality of conductors and a second plurality of conductors;a first semiconductor die electrically connected to the first plurality of conductors through a first set of bond wires;a second semiconductor die electrically connected to the second plurality of conductors through a second set of bond wires, the second semiconductor die attached to the first semiconductor die;a molding structure covering portions of the lead frame, the first semiconductor die, the second semiconductor die, the first set of bond wires, and the second set of bond wires; anda cavity within the molding structure and covering portions of top surfaces of the first semiconductor die and attached to the second semiconductor die, wherein a portion of the cavity is in between the first semiconductor die and the die paddle, wherein one surface of each of the first plurality of conductors and two surfaces of each of the second plurality of conductors are exposed from the semiconductor package, and wherein the first semiconductor die is suspended by the first set of bond wires to float inside the cavity.2. The semiconductor package of claim 1 , wherein the second set of bond wires is below the first set of bond wires in a cross-sectional view of the semiconductor package.3. The semiconductor package of further comprising a film layer in contact with portions of the molding structure and covering a portion of the cavity.4. The semiconductor package of claim 3 , wherein the film layer includes a screen-printed film.5. The ...

MULTI WIRE BONDING WITH CURRENT SENSING METHOD

Implementations of a semiconductor package system may include a first bond wire bonded to a portion of a leadframe and to a pad of a semiconductor die, the first bond wire coupled to one of a power source or a ground; and a second bond wire bonded to the portion of the leadframe and to a control integrated circuit. The portion of the leadframe may form a current sense area and the control integrated circuit may be configured to use the second bond wire and the current sense area to measure a current flowing through the first bond wire during operation.

ALUMINUM ALLOY LEAD FRAME FOR A SEMICONDUCTOR DEVICE AND CORRESPONDING MANUFACTURING PROCESS

Described herein is a semiconductor device provided with: a die of semiconductor material; a lead frame, defining a support plate, which is designed to carry the die, and leads, which are designed to be electrically coupled to the die; and a package, of encapsulating material, which is designed to encapsulate the die and partially coming out of which are the leads. The lead frame has as constituent material an aluminum alloy comprising a percentage of silicon ranging between 1% and 1.5%. 1. A semiconductor device , comprising:a die including semiconductor material;a lead frame having a support plate supporting said die and leads electrically coupled to said die, wherein the lead frame is an aluminum alloy including a percentage of silicon that is between 1% and 1.5%; anda package that includes encapsulating material encapsulating said die, wherein a portion of said leads protrude from the package.2. The device according to claim 1 , comprising at least one electrical bonding wire within said package directly coupled to a first end of at least one of said leads and a second end coupled to a contact pad of said die.3. The device according to claim 1 , wherein:the portions of said leads protrude from said package are configured to be directly coupled with contact pads of another device or board.4. The device according to claim 1 , wherein said die is directly coupled to a surface of the support plate of the lead frame.5. The device according to claim 1 , wherein said die is coupled to a surface of the support plate of the lead frame by an adhesive.6. The device according to claim 1 , wherein said aluminum alloy further includes a percentage of magnesium between 0.25% and 0.6%.7. The device according to claim 1 , wherein said semiconductor device is a power device.8. A process for manufacturing a semiconductor device claim 1 , the comprising:coupling a semiconductor die to a support plate of a lead frame that includes an aluminum alloy, the aluminum alloy including a ...

Molded lead frame device

A molded lead frame device includes a plurality of lead frame units and a molding layer. Each of the lead frame units includes an array of leads. Each of the leads includes a die-connecting portion and a terminal portion that extends downwardly from the die-connecting portion. The molding layer embeds the die-connecting portions of the lead frame units and has spaced apart longitudinal and transverse sections intersecting each other and separating the lead frame units from each other.

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor element and a first connection member. The semiconductor element includes a substrate and an electrode pad. The substrate includes a transistor formation region, in which a transistor is formed and which is shaped to be non-quadrangular. The electrode pad is located on the transistor formation region. The first connection member is connected to the electrode pad at one location. The electrode pad is arranged to cover a center of gravity of the transistor formation region in a plan view of the electrode pad. In the plan view, a connection region in which the first connection member is connected to the electrode pad includes a center of gravity position of the transistor formation region. 2. The semiconductor device according to claim 1 , wherein a center position of the connection region coincides with the center of gravity position of the transistor formation region.4. A semiconductor device comprising:a semiconductor element including a substrate, having a transistor formation region in which a transistor is formed and which is shaped to be non-quadrangular, and an electrode pad on the transistor formation region; andfirst connection members connected to the electrode pad, whereinthe transistor formation region is divided into divided regions having equal areas in accordance with the number of the first connection members,the electrode pad is arranged to cover a center of gravity of each of the divided regions in a plan view, andin the plan view, a connection region in which the first connection members are each connected to the electrode pad includes a center of gravity position of each of the divided regions.5. The semiconductor device according to claim 3 , wherein the divided regions are equally divided to approach a square.6. The semiconductor device according to claim 3 , wherein a center position of the connection region coincides with the center of gravity position of each of the divided regions.7. The ...

SEMICONDUCTOR LIGHT EMITTING DEVICE

A semiconductor light emitting device includes a main lead, a sub lead, a semiconductor light emitting element bonded to the main lead, and a protective element bonded to the sub lead, wherein the semiconductor light emitting element is connected to the main lead and the sub lead via a first wire and a second wire, respectively, wherein the protective element has a main surface electrode and a back surface electrode which is connected to the sub lead via a conductive bonding material, and wherein the main surface electrode of the protective element is connected to the main lead via a third wire, a connecting wiring which connects electrodes of the semiconductor light emitting element, and a connecting member including the second wire. 1. A semiconductor light emitting device comprising:a main lead having a main surface and a first back surface facing a side opposite to the main surface;a sub lead arranged in a first direction with respect to the main lead, and having a main surface facing the same side as the main surface of the main lead and a second back surface facing the side opposite to the main surface of the sub lead;a case configured to support the main lead and the sub lead, and having a case main surface facing the same side as the main surfaces of the main lead and the sub lead, and an opening formed in the case main surface to expose portions of the main lead and the sub lead;a semiconductor light emitting element arranged on the main surface of the main lead, and having an element main surface facing the same side as the main surface of the main lead, an element back surface facing the main surface of the main lead, a first electrode formed on the element main surface, and a main surface connecting portion formed on the element main surface;a first bonding material bonding the semiconductor light emitting element to the main lead;a first wire connecting the first electrode of the semiconductor light emitting element to the sub lead;a protective element ...

PACKAGE WITH LEAD FRAME WITH IMPROVED LEAD DESIGN FOR DISCRETE ELECTRICAL COMPONENTS AND MANUFACTURING THE SAME

A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package. 1. A semiconductor package , comprising: a lead having a surface covered by a first conductive material;', 'an engraved lead having a first engraved region on the first side, the engraved lead having a surface on the second side covered by the first conductive material, the first engraved region including a first recess on the first side; and', 'a die pad having a second engraved region on the first side, the die pad having a surface on the second side covered by the first conductive material, the second engraved region including a second recess on the first side;, 'a lead frame having a first side and a second side, the lead frame includinga discrete electrical component coupled to the first engraved region and the second engraved region;a die coupled to the die pad;an electrical connection coupling the die to the lead of the lead frame; anda molding compound encasing the lead frame, the die, the discrete electrical component, and the electrical connections, the molding ...

MULTI-PHASE POWER CONVERTER WITH COMMON CONNECTIONS

In some examples, a device comprises at least two semiconductor die, wherein each respective semiconductor die of the at least two semiconductor die comprises at least two power transistors, an input node on a first side of the respective semiconductor die, a reference node on the first side of the respective semiconductor die, and a switch node on a second side of the respective semiconductor die. The device further comprises a first conductive element electrically connected to the respective input nodes of the at least two semiconductor die. The device further comprises a second conductive element electrically connected to the respective reference nodes of the at least two semiconductor die. 1. A device comprising: at least two power transistors,', 'an input node on a first side of the respective semiconductor die,', 'a reference node on the first side of the respective semiconductor die, and', 'a switch node on a second side of the respective semiconductor die;, 'at least two semiconductor die, wherein each respective semiconductor die of the at least two semiconductor die comprisesa first conductive element electrically connected to the respective input nodes of the at least two semiconductor die; anda second conductive element electrically connected to the respective reference nodes of the at least two semiconductor die.2. The device of claim 1 , wherein:the first conductive element comprises a wire, an aluminum ribbon, a copper clip, or a copper layer; andthe second conductive element comprises a wire, an aluminum ribbon, a copper clip, or a copper layer.3. The device of claim 1 , further comprising at least two die paddles claim 1 , wherein:each switch node of each respective semiconductor die of the at least two semiconductor die is electrically connected to a respective die paddle of the at least two die paddles;each die paddle of the at least two die paddles is electrically isolated from other die paddles of the at least two die paddles; andeach die paddle ...

SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE

In one aspect of the semiconductor module, the sealing material on the lower side of the die stage is thinner than the sealing material on the upper side of the semiconductor element, a bent portion that forms a step with respect to vertical direction in the first lead is provided in a region sealed by the sealing material in the first lead, the side where the die stage is present of the step is positioned below the side where the die stage is not present of the step due to the step, the side where the die stage is not present of the step in the first lead protrudes from one end side of the sealing material, and a groove is provided on an upper side surface, a lower side surface, or both of them of the bent portion of the first lead. 1. A semiconductor module comprising:a first lead;a second lead;a semiconductor element; anda sealing material configured to seal a part of the first lead, a part of the second lead, and the semiconductor element,wherein the first lead includes a die stage,wherein the semiconductor element is bonded onto an upper side surface of the die stage,wherein the sealing material on a lower side of the die stage is thinner than the sealing material on an upper side of the semiconductor element,wherein the sealing material on a lower side of the die stage is thinner than the sealing material on a lower side of the second lead,wherein a bent portion configured to form a step with respect to vertical direction in the first lead is provided in a region sealed with the sealing material in the first lead,wherein a side on which the die stage is present of the step is positioned below a side on which the die stage is not present of the step due to the step,wherein a side on which the die stage is not present of the step of the first lead protrudes from one end side of the sealing material,wherein the second lead protrudes from a side opposite to the one end side of the sealing material, andwherein a groove is provided on an upper side surface, a lower ...

Method and apparatus for high temperature semiconductor device packages and structures using a low temperature process

A semiconductor device package that incorporates a combination of ceramic, organic, and metallic materials that are coupled using silver is provided. The silver is applied in the form of fine particles under pressure and a low temperature. After application, the silver forms a solid that has a typical melting point of silver, and therefore the finished package can withstand temperatures significantly higher than the manufacturing temperature. Further, since the silver is an interfacial material between the various combined materials, the effect of differing material properties between ceramic, organic, and metallic components, such as coefficient of thermal expansion, is reduced due to low temperature of bonding and the ductility of the silver.

Semiconductor Device Leadframe

For so called film assisted moulding (FAM) device processing techniques there is provided lead frame for a semiconductor device, comprising a base portion and a connection lead, said base portion arranged for mounting a semiconductor die, said connection lead comprising a horizontal portion for external connection and an angled portion for connection to said semiconductor die, wherein the angled portion has a positive angle with respect to the base portion. The connection lead may comprise a recessed portion.

Stacked-Die Bulk Acoustic Wave Oscillator Package

A stacked-die oscillator package includes an oscillator circuit die having inner bond pads, and outer bond pads, and a bulk acoustic wave (BAW) resonator die having a piezoelectric transducer with a first and second BAW bond pad on a same side coupled to a top and bottom electrode layer across a piezoelectric layer. A first metal bump is on the first BAW bond pad and a second metal bump is on the second BAW bond pad flip chip bonded to the inner bond pads of the oscillator circuit die. A polymer material is in a portion of a gap between the BAW and oscillator circuit die. 144-. (canceled)45. A stacked-die oscillator package , comprising:an oscillator circuit die having a first and a second bond pad;a bulk acoustic wave (BAW) resonator die flip chip bonded to the first and second bond pads of the oscillator circuit die; anda polymer material positioned in a portion of a gap between the BAW resonator die and the oscillator circuit die.46. The stacked-die oscillator package of claim 45 , wherein the bulk acoustic wave (BAW) resonator die comprises a piezoelectric transducer.47. The stacked-die oscillator package of claim 46 , further comprising a Bragg mirror above the piezoelectric transducer.48. The stacked-die oscillator package of claim 45 , wherein the first metal bump and the second metal bump comprise a copper post with a different metal cap thereon.49. The stacked-die oscillator package of claim 45 , wherein the polymer material comprises a polyimide.50. The stacked-die oscillator package of claim 45 , further comprising a low elastic modulus material positioned over the BAW resonator die for encapsulating the BAW resonator die.51. The stacked-die oscillator package of claim 50 , wherein the low elastic modulus material comprises silicone rubber.52. The stacked-die oscillator package of claim 45 , wherein the polymer material comprises a low elastic modulus material.53. The stacked-die oscillator package of claim 52 , wherein the polymer material also provides ...

Beamforming Integrated Circuit with RF Grounded Material Ring

A beamforming integrated circuit system for use in a phased array has a microchip with RF circuitry, and a plurality of (on chip) interfaces electrically connected with the RF circuitry. The plurality of interfaces includes a signal interface, a first ground interface, and a second ground interface. The signal interface is configured to communicate an RF signal, and both the first and second ground interfaces are adjacent to the signal interface. The system also has a material ring circumscribing the plurality of interfaces, and at least one RF ground path coupled with the material ring. 1. A beamforming integrated circuit system for use in a phased array , the integrated circuit system comprising:a microchip having RF circuitry;a plurality of interfaces electrically connected with the RF circuitry, the plurality of interfaces including a signal interface, a first ground interface, and a second ground interface, the signal interface configured to communicate an RF signal, the first ground interface being adjacent to the signal interface, the second ground interface also being adjacent to the signal interface;a material ring circumscribing the plurality of interfaces; andat least one RF ground paths coupled with the material ring.2. The beamforming integrated circuit system as defined by wherein the RF circuitry operates at between about 5 GHz and 300 GHz.3. The beamforming integrated circuit system as defined by wherein the plurality of interfaces are configured to be flip-chip mounted on a substrate.4. The beamforming integrated circuit system as defined by further comprising a printed circuit board claim 1 , the microchip being flip-chip mounted to the printed circuit board.5. The beamforming integrated circuit system as defined by wherein the at least one RF ground path comprises a plurality of RF ground paths coupled about the material ring.6. The beamforming integrated circuit system as defined by wherein the integrated circuit is configured to operate on an RF ...

SEMICONDUCTOR LIGHT EMITTING APPARATUS, STEM PART

A semiconductor light emitting apparatus includes: a stem part having a stem base, a lead terminal, and a metal member having a closed shape, the stem base having an inner portion having a first face, a second face and an opening extending in a first direction from the first face to the second face, and an outer portion surrounding the inner portion, the inner and outer portions being arranged along a reference plane intersecting the first direction, the lead terminal being supported in the opening, and the metal member being disposed on the outer portion so as to surround the inner portion and having a first portion supported by a top face of the outer portion, and a second portion extending outward with reference to an edge of the outer portion; a semiconductor optical element disposed on the inner portion; and a cap disposed on the metal member. 1. A semiconductor light emitting apparatus including:a stem part having a stem base, a lead terminal, and a metal member, the stem base having an inner portion and an outer portion, the inner portion having a first face, a second face and an opening, the opening extending in a first direction from the first face to the second face, the outer portion surrounding the inner portion, the lead terminal being supported in the opening, and the metal member having a closed shape and being disposed on the outer portion so as to surround the inner portion;a semiconductor optical element disposed on the inner portion; anda cap disposed on the metal member,the inner portion and the outer portion being arranged along a reference plane intersecting the first direction, andthe metal member having a first portion supported by a top face of the outer portion, and a second portion extending outward with reference to an edge of the outer portion.2. The semiconductor light emitting apparatus according to claim 1 , wherein the cap has an end claim 1 , and the end of the cap is welded to the metal member to form a weld zone claim 1 , and the ...

SEMICONDUCTOR DEVICE, MEMORY DEVICE, ELECTRONIC DEVICE, OR METHOD FOR DRIVING THE SEMICONDUCTOR DEVICE

A semiconductor device with an improved arithmetic processing speed and a decreased circuit size, and its driving method are provided. In the semiconductor device, a first terminal of a first transistor and a gate of a second transistor are electrically connected to a first terminal of a capacitor, and a control circuit is electrically connected to a second terminal of the capacitor. The control circuit supplies a first potential to the second terminal of the capacitor, in other words, adds a value corresponding to the first potential to the value of first data previously retained in the gate of the second transistor in order to obtain second data. In the second transistor, the second data, specifically, a third potential commensurate with the potential of the gate will be output from a second terminal when a second potential is supplied to a first terminal. 1. A driving method of a semiconductor device , a first transistor;', 'a second transistor;', 'a capacitor; and', 'a control circuit,, 'the semiconductor device comprisingwherein a first terminal of the first transistor is electrically connected to a first terminal of the capacitor,wherein a gate of the second transistor is electrically connected to the first terminal of the capacitor,wherein the control circuit is electrically connected to a second terminal of the capacitor,wherein first data of m bits is retained in the gate of the second transistor,wherein m is an integer of 1 or more,wherein the first data has a value of i,{'sup': 'm', 'wherein i is an integer of 0 to 2−2, and'}{'sup': 'm', 'wherein j is an integer of 1 to 2−1−i,'} supplying a first potential from the control circuit to the second terminal of the capacitor in order to add a value of j that corresponds to the first potential to the value of the first data, so that data retained in the gate of the second transistor is changed from the first data to second data; and', 'supplying a second potential to a first terminal of the second transistor in ...

OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-ON-PACKAGE STRUCTURES

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads. 2. The structure of wherein the first land side pad is electrically coupled to the first POP side pad by direct contact with a via interconnect structure.3. The structure of wherein the center to center spacing between the first land side pad and the second land side pad does not overlap the spacing between the first POP side pad and the second POP side pad.4. The structure of wherein the center to center spacing between the first land side pad and the second land side pad overlaps the spacing between the first POP side pad and the second POP side pad.5. The structure of wherein the first and second land side pads are part of an array of land side pads that are all configures at a first pitch claim 1 , and wherein the first and second POP side pads are part of an array of POP side pads that are all configured at a second pitch claim 1 , wherein the first pitch is larger than the second pitch.6. The structure of wherein the first and second land side pads are part of an array of land side pads that are all configures at a first pitch claim 1 , and wherein the first and second POP side pads are part of an array of POP side pads that are all configured at a second pitch claim 1 , wherein the first pitch is larger than the second pitch.7. The structure of wherein the memory device is electrically coupled to the POP substrate by one of a wire bond connection or a ...

RECESSED LEAD LEADFRAME PACKAGES

Leadframes for semiconductor packages. Implementations may include a plurality of leads extending inwardly into an opening surrounded by the plurality of leads where the plurality of leads except for at least one are configured to mechanically couple at a surface of a semiconductor chip. The at least one of the plurality of leads that is not configured to mechanically coupled at the surface of the semiconductor chip be configured to electrically couple with the semiconductor chip 1. A chip-on-lead package comprising:a leadframe coupled to a semiconductor chip, the leadframe comprising a plurality of leads extending inwardly into an opening surrounded by the plurality of leads;wherein at least one of the plurality of leads comprises a thinned portion adjacent to the semiconductor chip and is an at least one thinned lead;wherein the at least one thinned lead electrically couples with a high voltage connector of the semiconductor chip; andwherein the plurality of leads, except for the at least one thinned lead, mechanically couple to the semiconductor chip through a die bonding material.2. The package of claim 1 , wherein the at least one thinned lead is configured to carry up to 200 volts.3. The package of claim 1 , wherein the thinned portion of the at least one thinned lead is one of half etched and fully etched4. The package of claim 1 , wherein the plurality of leads is configured to couple with an electronic circuit board at a surface of each of the plurality of leads opposite the surface of the semiconductor chip.5. The package of claim 1 , wherein the at least one thinned lead does not extend inwardly into the opening as far as the other leads of the plurality of leads.6. The package of claim 1 , wherein the plurality of leads is configured to mechanically support the semiconductor chip through coupling at the surface of the semiconductor chip through a die bonding material.7. The package of claim 1 , wherein a perimeter of the surface of each of the plurality ...

Low Profile Leaded Semiconductor Package

In a semiconductor package a lead having a bottom surface coplanar with the flat bottom surface of the plastic body extends outward at the bottom of the vertical side surface of the plastic body. The result is a package with a minimal footprint that is suitable for the technique known as “wave soldering” that is used in relatively low-cost printed circuit board assembly factories. Methods of fabricating the package are disclosed. 1. A method of fabricating a semiconductor package comprising:thinning a metal piece at locations where a die pad and a cantilever segment of a lead are to be formed;thinning the metal piece at a location where a foot of the lead is to be formed; andsevering the metal piece between the location of the die pad and the location of the cantilever segment of the lead.2. The method of wherein thinning the metal piece at a location where a foot of the lead is to be formed and severing the metal piece between the location of the die pad and the location of the cantilever segment of the lead are performed in a single process step.3. The method of wherein thinning a metal piece at locations where a die pad and a cantilever segment of a lead are to be formed comprises thinning the metal piece at a location of a gap between the die pad and the cantilever segment of the lead.4. The method of wherein thinning the metal piece at locations where the die pad claim 3 , the cantilever segment of the lead claim 3 , and the gap between the die pad and the cantilever segment of the lead are to be formed comprises depositing a first mask layer on a first side of the metal piece claim 3 , forming an opening in the first mask layer corresponding to the locations where the die pad claim 3 , the cantilever segment of the lead claim 3 , and the gap between the die pad and the cantilever segment of the lead are to be formed claim 3 , and partially etching the metal piece through the first opening in the first mask layer.5. The method of wherein thinning the metal ...

Bond Wire Connection

An integrated circuit package is provided. The integrated circuit package comprises: a die; a lead; and a bond wire comprising a first end coupled to the die and a second end coupled to the lead via bond. The bond wire further comprises: a first portion between a first bend in the bond wire and the bond and forming a first angle with respect to the lead; and a second portion forming a second angle with respect to the lead. The first bend is immediately between the first and second portions and is configured to reduce the angle of the bond wire with respect to the lead from the second angle to the first angle. 1. An integrated circuit package comprising:a die;a lead; anda bond wire comprising a first end coupled to the die and a second end coupled to the lead via a bond; a first portion between a first bend in the bond wire and the bond and forming a first angle with respect to the lead;', 'a second portion forming a second angle with respect to the lead;, 'the bond wire further comprisingwherein the first bend is immediately between the first and second portions and is configured to reduce the angle of the bond wire with respect to the lead from the second angle to the first angle.2. The integrated circuit of wherein the first angle is equal to or less than 10°.3. The integrated circuit of wherein the bond wire further comprises a third portion coupled between the second portion and the die.4. The integrated circuit of wherein the two or more portions of the bond wire are integral.5. The integrated circuit of wherein the first bend is formed by bending the bond wire in a direction opposite to the direction in which the lead lies relative to the bond wire.6. The integrated circuit of where the bond wire comprises at least one further bend between the first end of the bond wire and the first bend claim 1 , the further bend configured to form at least part of a loop between the first end and the first bend.7. The integrated circuit of wherein the bond is one of a wedge ...

Connection member with bulk body and electrically and thermally conductive coating

A connection member for connecting an electronic chip, wherein the connection member comprises a bulk body, and a coating at least partially coating the bulk body and comprising a material having higher electric and higher thermal conductivity than the bulk body, wherein a ratio between a thickness of the coating and a thickness of the bulk body is at least 0.0016 at at least a part of the connection member. 1. A connection member for connecting an electronic chip , wherein the connection member comprises:a bulk body;a coating at least partially coating the bulk body and comprising a material having higher electric conductivity and higher thermal conductivity than the bulk body;wherein a ratio between a thickness of the coating and a thickness of the bulk body is at least 0.0016 at at least a part of the connection member;wherein the coating comprises or consists of at least one of the group consisting of copper, a copper alloy, zinc, and zinc alloy.2. The connection member according to claim 1 , wherein at least a portion of the coating has a thickness in a range between 4 μm and 100 μm.3. The connection member according to claim 1 , wherein the coating has a thickness of at least 7 μm.4. The connection member according to claim 1 , configured as a leadframe.5. The connection member according to claim 1 , configured as a clip.6. The connection member according to claim 1 , wherein a thickness of the bulk body is in a range between 100 μm and 2500 μm.7. The connection member according to claim 1 , wherein the bulk body comprises or consists of iron.8. The connection member according to claim 7 , wherein the bulk body comprises or consists of one of an iron alloy claim 7 , a steel alloy claim 7 , and steel.9. (canceled)10. The connection member according to claim 1 , comprising at least one further coating on at least part of the coating claim 1 , wherein the further coating and the coating are made of different materials.11109. The connection member according to ...

Galvanic Signal Path Isolation in an Encapsulated Package Using a Photonic Structure

An encapsulated package is provided that includes a pair integrated circuit (IC) die. A radio frequency (RF) circuit on one of the IC die is operable to transmit an RF signal having a selected frequency. An RF circuit on the other IC die is operable to receive the RF signal Encapsulation material encapsulates the IC die. A photonic waveguide couples between the RF transmitter and RF receiver to form galvanic path isolation between the two IC die. The photonic waveguide is formed by a photonic structure within the encapsulation material. 1. An encapsulated package comprising:a first integrated circuit (IC) die having an electromagnetic transmitter circuit to emit an electromagnetic signal having a frequency;a second IC die having an electromagnetic receiver circuit to receive the electromagnetic signal having the frequency;an encapsulation material encapsulating the first IC die together with the second IC die, the first IC die being spaced apart from the second IC die by a distance, and the encapsulation material including a photonic waveguide formed by a photonic structure to couple an output of the electromagnetic transmitter circuit to an input of the electromagnetic receiver circuit; anda leadframe having a first die attach pad separated from a second die attach pad;a portion of the photonic structure being located between the first IC die and the first die attach pad.2. The encapsulated package of claim 1 , wherein the photonic structure is a photonic bandgap (PBG) structure.3. The encapsulated package of claim 2 , wherein the PBG structure has a bandgap that includes the frequency.4. The encapsulated package of claim 1 , wherein the photonic structure is a photonic resonant structure having a pass band that includes the frequency.5. The encapsulated package of claim 1 , wherein the frequency is an optical frequency.6. The encapsulated package of claim 1 , wherein the frequency is a radio frequency.7. The encapsulate package of claim 1 , wherein the first IC ...

Package with interconnections having different melting temperatures

A package comprising at least one electronic chip, a first heat removal body on which the at least one electronic chip is mounted by a first interconnection, a second heat removal body mounted on or above the at least one electronic chip by a second interconnection, and an encapsulant encapsulating at least part of the at least one electronic chip, part of the first heat removal body and part of the second heat removal body, wherein the first interconnection is configured to have another melting temperature than the second interconnection. 2. The package according to claim 1 , comprising an encapsulant encapsulating at least part of the at least one electronic chip claim 1 , part of the first heat removal body and part of the second heat removal body.3. The package according to claim 1 , wherein the first interconnection comprises one of the group consisting of a solder structure and a sinter structure.4. The package according to claim 1 , wherein the second interconnection comprises one of the group consisting of a solder structure and a sinter structure.5. The package according to claim 1 , comprising at least one electrically conductive spacer body claim 1 , in particular at least one electrically conductive and thermally conductive spacer body claim 1 , between the at least one electronic chip and the second heat removal body.6. The package according to claim 5 , wherein the second interconnection directly connects the at least one electronic chip with the at least one spacer body.7. The package according to claim 1 ,wherein at least the first interconnection comprises Pb-based solder material or SnSb-based solder material.8. The package according to claim 5 , comprising a third interconnection which directly connects the at least one spacer body with the second heat removal body.9. The package according to claim 8 , wherein the third interconnection comprises one of the group consisting of a welding structure claim 8 , a solder structure and a sinter structure. ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

An insulating film is formed such that the insulating film covers a source electrode and a gate electrode, and an opening portion exposing a portion of the source electrode and an opening portion exposing a portion of the gate electrode are formed in the insulating film. A plated layer is formed over the source electrode exposed in the opening portion, and a plated layer is formed over the gate electrode exposed in the opening portion. A source pad is formed of the portion of the source electrode exposed in the opening portion, and the plated layer, and a gate pad is formed of the portion of the gate electrode exposed in the opening portion, and the plated layer. An area of the opening portion for the gate pad is smaller than an area of the opening portion for the source pad, and a thickness of the plated layer over the gate electrode is greater than a thickness of the plated layer over the source electrode. 1. A semiconductor device comprising:a semiconductor substrate;an interlayer insulating film formed over a main surface of the semiconductor substrate;a first conductive film pattern for a first pad formed over the interlayer insulating film and a second conductive film pattern for a second pad formed over the interlayer insulating film;an insulating film formed over the interlayer insulating film such that the insulating film covers the first and the second conductive film patterns;a first opening portion for the first pad, the first opening portion being formed in the insulating film and exposing a portion of the first conductive film pattern;a second opening portion for the second pad, the second opening portion being formed in the insulating film and exposing a portion of the second conductive film pattern;a first plated layer formed over the portion of the first conductive film pattern exposed in the first opening portion; anda second plated layer formed over the portion of the second conductive film pattern exposed in the second opening portion,wherein the ...

ELECTRONICS MODULE AND METHOD FOR PRODUCING IT

Electronic module () including 11. An electronic module () , comprising{'b': '20', 'an encapsulation () and'}{'b': 10', '20', '25', '15', '30', '30', '10, 'a carrier substrate () at least partially embedded in the encapsulation () and having a component side (), which has a first metallization layer () and on which at least one first electronic component () is arranged, wherein the first electronic component () is enclosed by the encapsulation and the carrier substrate () is a metal-ceramic substrate,'}{'b': 35', '31', '30', '20, 'wherein at least one second metallization layer () for at least one second electronic component (), in particular for controlling the first electronic component (), is provided on an outside (A) of the encapsulation (),'}{'b': 20', '5', '30', '31, 'wherein the encapsulation () has at least one through hole plating () for an electrical connection of the first electronic component () and the second electronic component ().'}2135. The electronic module () according to claim 1 , wherein the second metallization layer () is structured and/or wherein a distance between the first metallization layer and the second metallization layer measured perpendicular to a main extension plane is less than 5 mm.311112161112. The electronic module () according to claim 1 , wherein the carrier substrate comprises a primary layer () claim 1 , a secondary layer () and a metallic intermediate layer () arranged between the primary layer () and the secondary layer ().415163031511. The electronic module () according to claim 3 , wherein a further through hole plating (′) is provided for electrically connecting the intermediate layer () to the first and/or second electronic component ( claim 3 ,) claim 3 , wherein the further through hole plating (′) extends at least through the primary layer ().5114202510201455. The electronic module () according to claim 1 , wherein a contacting plane () claim 1 , arranged between the outside (A) of the encapsulation () and the ...

TEMPORARY PROTECTIVE FILM, REEL BODY, PACKAGING BODY, PACKAGE BODY, TEMPORARY PROTECTIVE BODY, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

A temporary protective film including a support film and an adhesive layer provided on one surface or both surfaces of the support film. The support film is a polyimide film. The thickness of the adhesive layer is less than 8 μm. 1. A temporary protective film comprising:a support film; andan adhesive layer provided on one surface or both surfaces of the support film,wherein the support film is a polyimide film, anda thickness of the adhesive layer is less than 8 μm.2. The temporary protective film according to claim 1 , wherein the thickness of the adhesive layer is less than 5 μm.3. The temporary protective film according to claim 1 , wherein the adhesive layer comprises at least one organic polymer selected from an aromatic polyamide claim 1 , an aromatic polyester claim 1 , an aromatic polyimide claim 1 , an aromatic polyamideimide claim 1 , an aromatic polyether claim 1 , an aromatic polyetheramideimide claim 1 , an aromatic polyetherimide claim 1 , an aromatic polyesterimide claim 1 , and an aromatic polyetherimide.5. The temporary protective film according to claim 1 , wherein when the adhesive layer is heated for 10 minutes at 120° C. and then heated for 20 minutes at 240° C. claim 1 , a proportion of weight reduction caused by heating for 20 minutes at 240° C. is less than 0.5% with respect to the weight of the adhesive layer before heating for 20 minutes at 240° C.6. The temporary protective film according to claim 1 , wherein the adhesive layer is configured to have a 90-degree peel strength claim 1 , between the adhesive layer and a lead frame as well as a sealing layer claim 1 , of 600 N/m or less at 180° C. when the temporary protective film is attached to a lead frame having a die pad and an inner lead such that the adhesive layer comes into contact with the lead frame claim 1 , a semiconductor element is mounted on a surface of the die pad claim 1 , the surface being on the opposite side of the temporary protective film claim 1 , subsequently the ...

SEMICONDUCTOR PACKAGE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package substrate and a method of manufacturing the same are provided. The semiconductor package substrate includes: a base layer including a conductive material, having a first surface and a second surface opposite the first surface, and having a first groove or first trench in the first surface and a second groove or second trench in the second surface; a first resin buried in the first groove or first trench in the first surface of the base layer; and a groove in at least one corner of the first surface of the base layer and having a depth based on the first surface is 1/2 or more of a thickness of the base layer. 1. A semiconductor package substrate comprising:a base layer including a conductive material, having a first surface and a second surface opposite the first surface, and having a first groove or first trench in the first surface and a second groove or second trench in the second surface;a first resin buried in the first groove or first trench in the first surface of the base layer; anda groove structure in at least one corner of the first surface of the base layer and having a depth based on the first surface of the base layer is ½ or more of a thickness of the base layer.2. The semiconductor package substrate of claim 1 , wherein a depth of the groove structure is 100 μm or more.3. The semiconductor package substrate of claim 1 , wherein a thickness of the base layer corresponding to the groove structure is 35 μm or more.4. The semiconductor package substrate of claim 1 , wherein a width of the base layer with respect to the first surface corresponding to the groove structure is 30 μm or more greater than a width of the groove structure with respect to the second surface of the base layer.5. The semiconductor package substrate of claim 1 , further comprising:a coating layer disposed on a surface of the base layer except for the first resin.6. The semiconductor package substrate of claim 1 , wherein at least a portion of the first resin ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes a first insulating resin member sealing a mounting surface of a lead frame, and a second insulating resin member sealing a heat dissipating surface. The second insulating resin member contains a filler having a maximum diameter of 0.02 mm to 0.075 mm. The second insulating resin member includes a thin molded portion formed in contact with the heat dissipating surface of the lead frame. The thin molded portion has a thickness 1.1 times to 2 times the maximum diameter of the filler. The semiconductor device includes, at an interface between the first insulating resin member and the second insulating resin member, a mixture layer in which these resins are mixed with each other. 1. A semiconductor device including:a lead frame on which a semiconductor element is mounted;a first insulating resin member sealing a mounting surface, of the lead frame, on which the semiconductor element is mounted; anda second insulating resin member sealing a heat dissipating surface, of the lead frame, opposite to the mounting surface, whereinthe second insulating resin member contains a filler having a maximum diameter of 0.02 mm to 0.075 mm, andthe second insulating resin member includes a thin molded portion formed in contact with the heat dissipating surface of the lead frame, the thin molded portion having a thickness 1.1 times to 2 times the maximum diameter of the filler,the semiconductor device includes, at an interface between the first insulating resin member and the second insulating resin member, a mixture layer in which these resins are mixed with each other.2. The semiconductor device according to claim 1 , wherein a lead frame space filled portion which is a portion of the second insulating resin member is formed in at least a portion of a space between two separated regions of the lead frame.3. The semiconductor device according to claim 2 , including depressions and projections at a side surface of the lead frame on which the lead frame ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a first semiconductor chip including a first plurality of wiring layers, and a first coil, a first bonding pad, and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers, and a second semiconductor chip including a second plurality of wiring layers, a second coil, a second bonding pad, and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers. The first semiconductor chip and the second semiconductor chip face each other via an insulation sheet. The first coil and the second coil are magnetically coupled with each other. 1. A semiconductor device , comprising: a first plurality of wiring layers; and', 'a first coil, a first bonding pad, and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers; and, 'a first semiconductor chip comprising a second plurality of wiring layers;', 'a second coil, a second bonding pad, and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers,, 'a second semiconductor chip comprisingwherein the first semiconductor chip and the second semiconductor chip face each other via an insulation sheet, andwherein the first coil and the second coil are magnetically coupled with each other.2. The semiconductor device according to claim 1 , wherein the first semiconductor chip further comprises:a first region in which the first coil and the first dummy wires are disposed; anda second region in which the first bonding pad is disposed, a third region in which the second coil and the second dummy wires are disposed; and', 'a fourth region in which the second bonding pad is disposed,, 'wherein the second semiconductor chip further compriseswherein the first region is overlapped with the third region in a plan view, andwherein the second region is not overlapped with the fourth region in the plan view.3. The semiconductor device according to claim 1 , wherein the first dummy ...

Semiconductor device and method of manufacturing a semiconductor device

Various embodiments provide a semiconductor device, wherein the semiconductor device comprises a semiconductor device chip formed at a substrate, wherein the semiconductor device chip comprises an active region formed in a center of the substrate and a boundary region free of active components of the semiconductor device chip; and a detection wiring arranged in the boundary region of the substrate and at least partially surrounding the active region, wherein the detection wiring and the semiconductor device chip are electrically isolated from each other; and wherein the detection wiring and the substrate are electrically connected with each other via a connection having a high electrical resistance. 1. A semiconductor device , the semiconductor device comprising:a semiconductor device chip formed at a substrate, wherein the semiconductor device chip comprises an active region formed at a center of the substrate and a boundary region free of active components of the semiconductor device chip; anda detection wiring arranged in the boundary region of the substrate and at least partially surrounding the active region;wherein the detection wiring and the semiconductor device chip are electrically isolated from each other; andwherein the detection wiring and the substrate are electrically connected with each other via a connection path having a high electrical resistance.2. The semiconductor device according to claim 1 , wherein the detection wiring surrounds the active region formed in the center region of the substrate.3. The semiconductor device according to claim 1 , wherein the detection wiring comprises a material selected out of the group consisting of:metal; andsemiconductor material.4. The semiconductor device according to claim 1 , wherein the detection wiring is formed so that a leakage current flowing through the detection wiring is small compared to a diode leakage current at operation temperature of the semiconductor device.5. The semiconductor device ...

Semiconductor manufacturing apparatus and method of manufacturing semiconductor device using the same, and semiconductor device

A mold die includes a resin injection gate through which fluid resin serving as mold resin is injected toward a cavity, a resin reservoir to store the fluid resin flowing through the cavity, and a resin reservoir gate. The resin reservoir is provided on the side opposite to the side on which the resin injection gate is arranged with the cavity interposed. The resin reservoir gate communicatively connects the cavity and the resin reservoir. The opening cross-sectional area of the resin reservoir gate is smaller than the opening cross-sectional area of the resin injection gate.

SYSTEM IN PACKAGE

The present application describes a system in package which features no printed circuit board inside an encapsulation structure and comprises: a copper holder with a silicon layer at a top face; a plurality of dies mounted on the silicon layer and electrically connected to a plurality of data pins of the copper holder; a passive element mounted on the silicon layer and electrically connected to the dies wherein the dies are electrically connected to the ground pin of the copper holder; a molding compound encasing the dies and the passive element on the top face of the copper holder. 1. A system in package featuring no printed circuit board inside an encapsulation structure and comprises: a copper holder with a plurality of data pins and at least a ground pin; a silicon layer on a top face of the copper holder; a plurality of dies mounted on the silicon layer and electrically connected to the data pins of the copper holder; at least a passive element mounted on the silicon layer and electrically connected to the dies wherein the dies are electrically connected to the ground pin of the copper holder; a molding compound encasing the dies and the passive element on the top face of the copper holder.2. The system in package as claimed in wherein the dies are electrically connected to the data pins of the copper holder through a plurality of first metal wires.3. The system in package as claimed in wherein the passive element is electrically connected to the dies through a plurality of second metal wires.4. The system in package as claimed in wherein the dies are electrically connected to the ground pin of the copper holder through a plurality of third metal wires.5. The system in package as claimed in wherein the passive element is electrically connected to the ground pin of the copper holder through at least a fourth metal wire.6. The system in package as claimed in wherein the passive element is electrically connected to the data pins of the copper holder through at ...

THINNING SYSTEM IN PACKAGE

The present application discloses a thinning system in package featuring an encapsulation structure in which no printed circuit board exists and comprising: a plurality of dies mounted on a top face of a copper holder and electrically connected to the plurality of data pins on the copper holder; a passive element mounted on the top face and electrically connected to the dies wherein the dies are electrically connected to the ground pin of the copper holder and both the dies and the passive element are fixed on the top face of the copper holder through a layer of insulation adhesives; a molding compound encasing the dies and the passive element on the top face of the copper holder. 1. A thinning system in package featuring an encapsulation structure in which no printed circuit board exist and comprising: a copper holder with a plurality of data pins and at least a ground pin; a plurality of dies mounted on the top face of the copper holder and electrically connected to the data pins of the copper holder; at least a passive element mounted on the top face of the copper holder and electrically connected to the dies wherein both the dies and the passive element are fixed on the top face of the copper holder through a layer of insulation adhesives and the dies are electrically connected to the ground pin of the copper holder; a molding compound encasing the dies and the passive element on the top face of the copper holder.2. The thinning system in package as claimed in wherein the dies are electrically connected to the data pins of the copper holder through a plurality of first metal wires.3. The thinning system in package as claimed in wherein the passive element is electrically connected to the dies through a plurality of second metal wires.4. The thinning system in package as claimed in wherein the dies are electrically connected to the data pins of the copper holder through a layer of conductive adhesives.5. The thinning system in package as claimed in wherein the ...

LOW-PROFILE STACKED-DIE MEMS RESONATOR SYSTEM

A low-profile packaging structure for a microelectromechanical-system (MEMS) resonator system includes an electrical lead having internal and external electrical contact surfaces at respective first and second heights within a cross-sectional profile of the packaging structure and a die-mounting surface at an intermediate height between the first and second heights. A resonator-control chip is mounted to the die-mounting surface of the electrical lead such that at least a portion of the resonator-control chip is disposed between the first and second heights and wire-bonded to the internal electrical contact surface of the electrical lead. A MEMS resonator chip is mounted to the resonator-control chip in a stacked die configuration and the MEMS resonator chip, resonator-control chip and internal electrical contact and die-mounting surfaces of the electrical lead are enclosed within a package enclosure that exposes the external electrical contact surface of the electrical lead at an external surface of the packaging structure. 1. A microelectromechanical-system (MEMS) resonator system packaging structure having a low cross-sectional profile , the packaging structure comprising:a lead frame including an electrical lead having internal and external electrical contact surfaces at respective first and second heights within the cross-sectional profile of the packaging structure, and a die-mounting surface at a third height between the first and second heights;a resonator-control chip mounted to the die-mounting surface of the electrical lead and wire-bonded to the internal electrical contact surface of the electrical lead;a MEMS resonator chip mounted to the resonator-control chip in a stacked die configuration and electrically coupled to the resonator-control chip; anda package enclosure that encloses the MEMS resonator chip, resonator-control chip and internal electrical contact and die-mounting surfaces of the electrical lead, and that exposes the external contact ...

STRUCTURE OF BATTERY PROTECTION CIRCUIT MODULE PACKAGE COUPLED WITH HOLDER, AND BATTERY PACK HAVING SAME

A battery pack includes a structure of a battery protection circuit module package coupled with a holder, the structure including a basic package including a lead frame consisting of leads spaced apart from each other, and protection circuit elements provided on the lead frame, and an encapsulant and a holder simultaneously produced by disposing the basic package in a first injection mold and injecting a melt of resin into the first injection mold to perform an insert injection molding process, a battery core pack coupled with the structure, and an upper case for casing an upper part of the battery core pack to embed the structure therein. The encapsulant encapsulates the protection circuit elements to expose parts of the lead frame. The encapsulant and the basic package configure the battery protection circuit module package. The holder is coupled to the battery protection circuit module package due to the molding process. 1. A structure of a battery protection circuit module package coupled with a holder , the structure comprising:a basic package comprising a lead frame consisting of a plurality of leads spaced apart from each other, and protection circuit elements provided on the lead frame; andan encapsulant and a holder simultaneously produced by disposing the basic package in a first injection mold and injecting a melt of resin into the first injection mold to perform an insert injection molding process,wherein the encapsulant encapsulates the protection circuit elements to expose part of the lead frame,wherein the encapsulant and the basic package configure the battery protection circuit module package, andwherein the holder is coupled to the battery protection circuit module package by the insert injection molding process.2. A structure of a battery protection circuit module package coupled with a holder , wherein the battery protection circuit module package comprises a lead frame consisting of a plurality of leads spaced apart from each other , protection ...

SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE

A semiconductor device has a configuration in which a high-side module portion and a low-side module portion overlap each other. The semiconductor device further includes a control-side frame extending across the high-side module portion and the low-side module portion, and having a high-side integrated circuit and a low-side integrated circuit placed thereon. The high-side integrated circuit of the high-side module portion and the low-side integrated circuit of the low-side module portion are placed on one main surface of the control-side frame. At a boundary between the high-side module portion and the low-side module portion, the control-side frame is bent such that the high-side semiconductor chip and the low-side semiconductor chip face each other. 1. A semiconductor device comprising a high-side module portion and a low-side module portion arranged to overlap each other in a plan view ,the high-side module portion including a high-side semiconductor chip, a high-side integrated circuit, and a high-side lead frame having the high-side semiconductor chip placed thereon,the low-side module portion including a low-side semiconductor chip, a low-side integrated circuit, and a low-side lead frame having the low-side semiconductor chip placed thereon,the semiconductor device further comprising a control-side frame extending across the high-side module portion and the low-side module portion, and having the high-side integrated circuit and the low-side integrated circuit placed thereon,the high-side integrated circuit and the low-side integrated circuit being placed on one main surface of the control-side frame,at a boundary between the high-side module portion and the low-side module portion, the control-side frame being bent such that the high-side semiconductor chip and the low-side semiconductor chip face each other.2. The semiconductor device according to claim 1 , whereina protruding portion extending in a thickness direction of the low-side lead frame and being ...

Semiconductor device

A semiconductor device, includes: a semiconductor element having element main surface and element back surface spaced apart from each other in thickness direction and including a plurality of main surface electrodes arranged on the element main surface; a die pad having a die pad main surface where the semiconductor element is mounted; a plurality of leads including at least one first lead arranged on one side in first direction orthogonal to the thickness direction with respect to the die pad, and arranged around the die pad when viewed in the thickness direction; a plurality of connecting members including a first connecting member bonded to the at least one first lead, and configured to electrically connect the main surface electrodes and the leads; and a resin member configured to seal the semiconductor element, a part of the die pad, parts of the leads, and the connecting members

SEMICONDUCTOR DEVICE

According to one embodiment, a semiconductor device includes: a semiconductor chip; a mold resin provided over the semiconductor chip, and having at least a recess along its bottom surface; and a first terminal provided along a first upper surface of the recess and electrically connected to the semiconductor chip. 1. A semiconductor device comprising:a semiconductor chip;a mold resin provided over the semiconductor chip, and having at least a recess along its bottom surface; anda first terminal provided along a first upper surface of the recess and electrically connected to the semiconductor chip.2. The semiconductor device according to claim 1 , further comprising:a second terminal having a second upper surface; anda sintered material, provided on the second upper surface, including (i) a first portion connected to the first terminal, and (ii) a second portion protruding away from the recess.3. The semiconductor device according to claim 2 , wherein the second portion is thicker than the first portion.4. The semiconductor device according to claim 2 , wherein the sintered material comprises one of Ag (silver) claim 2 , Cu (copper) or Ni (nickel).5. The semiconductor device according to claim 2 , wherein the sintered material has at least one void.6. The semiconductor device according to claim 5 , wherein a proportion of the voids in the sintered material is not more than 20%.7. The semiconductor device according to claim 2 , wherein the second terminal includesa base material portion comprising Cu (copper), anda first film provided on a surface of the base material portion, the first film containing a solderable metal.8. The semiconductor device according to claim 2 , wherein the second terminal includesa base material portion comprising Cu (copper), anda second film provided on a surface of the base material portion, the second film containing N (nitrogen).9. The semiconductor device according to claim 1 , wherein the first terminal is electrically connected to a ...

SEMICONDUCTOR DEVICE

A semiconductor device includes: a first lead; a first semiconductor element mounted on the first lead; and a sealing resin that covers the first semiconductor element, wherein the first lead includes: a first die pad having a first main surface and a first back surface facing opposite sides to each other in a thickness direction; a second die pad arranged side by side with the first die pad in a first direction orthogonal to the thickness direction, and located on a side of the first main surface with respect to the first die pad in the thickness direction; and a connecting portion connected to the first die pad and the second die pad, and wherein the first back surface is exposed from the sealing resin. 1. A semiconductor device comprising:a first lead;a first semiconductor element mounted on the first lead; anda sealing resin that covers the first semiconductor element, a first die pad having a first main surface and a first back surface facing opposite sides to each other in a thickness direction;', 'a second die pad arranged side by side with the first die pad in a first direction orthogonal to the thickness direction, and located on a side of the first main surface with respect to the first die pad in the thickness direction; and', 'a connecting portion connected to the first die pad and the second die pad, and wherein the first back surface is exposed from the sealing resin., 'wherein the first lead includes2. The semiconductor device of claim 1 , wherein the first semiconductor element is mounted on the first main surface.3. The semiconductor device of claim 2 , wherein the second die pad has a second main surface facing the same side as the first main surface in the thickness direction claim 2 , and a second back surface facing the same side as the first back surface in the thickness direction.4. The semiconductor device of claim 3 , further comprising a first connecting member connected to the first semiconductor element and the second main surface.5. The ...