Semiconductor package having a stacked structure

A semiconductor package includes a substrate, a first semiconductor chip stacked on the substrate and a second semiconductor chip stacked on the first semiconductor chip. In the semiconductor package, the second semiconductor chip is rotated to be stacked on the first semiconductor chip. The semiconductor package is used in an electronic system.

Package-On-Package (PoP) Structure Including Stud Bulbs

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. 1. A device comprising:a first pad on a first surface of a first substrate;a second pad on a second surface of a second substrate;a metallic element interposed between the first pad and the second pad, the metallic element electrically coupled to the first pad, the metallic element comprising a base portion and an elongated portion extending from the base portion toward the second pad;a solder connector in contact with the elongated portion and electrically coupled to the second pad; andan inter-metallic compound (IMC) between the elongated portion and the solder connector.2. The device of claim 1 , further comprising a protection layer extending over the base portion and the elongated portion.3. The device of claim 1 , further comprising a die attached to the first substrate adjacent the metallic element.4. The device of claim 3 , wherein a height of the metallic element from the first substrate is greater than a height of the die from the first substrate.5. The device of claim 1 , wherein the metallic element comprises a copper wire.6. The device of claim 1 , wherein the base portion and the elongated portion comprises a single continuous element.7. A device comprising:a first substrate having a first pad;a second substrate having a second pad;a first connector interposed between the first pad and the second pad, the first connector having a first wide portion and a second elongated portion, the first wide portion being ...

Package-On-Package (PoP) Structure Including Stud Bulbs

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. 1. A device comprising:a first pad on a first surface of a first package;a second pad on a second surface of a second package;a metallic element interposed between the first pad and the second pad, the metallic element comprising a base portion and an elongated portion, the base portion being coupled to the first pad, the elongated portion extending from the base portion toward the second pad, wherein a width of the base portion is greater than a width of the elongated portion;a solder connector in contact with the elongated portion and electrically coupled to the second pad; andan inter-metallic compound (IMC) between the elongated portion and the solder connector.2. The device of claim 1 , wherein the first package comprises a first substrate and a first integrated circuit die attached to the first substrate claim 1 , wherein the second package comprises a second substrate and a second integrated circuit die attached to the second substrate.3. The device of claim 2 , wherein the metallic element is laterally adjacent the first integrated circuit die with the first integrated circuit die and the metallic element being interposed between the first substrate and the second substrate.4. The device of claim 3 , wherein the metallic element extends closer to the second substrate than the first integrated circuit die.5. The device of claim 1 , wherein a height of the metallic element is between about 20 micrometers and about 200 ...

Integrated Circuit Assembly and Method of Making

An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface. A first active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the first active layer and formed on the second surface of the insulating layer. A substrate having a first surface and a second surface, with a second active layer formed in the first surface, is provided such that the first active layer is coupled to the second surface of the substrate.

Semiconductor Package Having Spin Stacked Structure

기판과 기판에 적층되는 제 1 반도체 칩 및 제 1 반도체 칩에 적층되는 제 2 반도체 칩을 갖는 반도체 패키지들을 제공한다. 여기서, 제 2 반도체 칩은 회전되어 제 1 반도체 칩 상에 적층되는 반도체 패키지를 제공한다. 나아가, 그러한 반도체 패키지들을 구비하는 각종 전자 시스템들을 제공한다.

Semiconductor device and manufacturing method thereof

Electronic device having metallurgies containing copper-semiconductor compounds

본 발명의 실리콘 및 게르마늄 함유 재료는 전자 장치에서 도체의 표면에 사용된다. 본 발명에 의하면, 이들 표면에 땜납이 용제없이 접합될 수 있고 와이어가 와이어 접합될 수 있다. 이들 재료는 집적 회로 칩을 패키징하기 위한 리드프레임용 표면 피막으로 사용된다. 이들 재료는 도체 표면상으로 전사(傳寫)되거나, 무전해 또는 전기분해 증착될 수 있다. The silicon and germanium containing materials of the present invention are used on the surface of conductors in electronic devices. According to the present invention, solder can be bonded to these surfaces without solvent and wires can be wire bonded. These materials are used as surface coatings for leadframes for packaging integrated circuit chips. These materials may be transferred onto the conductor surface, or may be electrolessly or electrolytically deposited.

Metal base circuit board and its production process

A metal base circuit board is provided. The circuit board includes circuits provided on a metal plate via an insulating layer. A dent portion is provided on one side of the metal plate in such a state that the circumferential portion thereof is not opened, and insulating layers made of the same material are provided both on the space of the dent portion and on the metal plate on which the dent portion is present. The maximum depth of the dent portion may range from 10% to 50% of the thickness of the metal plate. The size of the dent portion as viewed from the vertical direction may be at least 50% of the area of the metal plate, and in a shape of the dent portion as viewed from the vertical direction, the corner may have a curvature radius of at least 2.5mm.

Semiconductor device and manufacturing method of semiconductor device

A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.

Metal-base circuit board and its manufacturing method

Metal-base circuit board and its manufacturing method

혼성 집적 회로의 고주파 동작시에 발생하는 반도체의 오동작시를 대폭 저감시켜, 열 방산성이 우수한 금속 베이스 회로 기판을 제공한다. 금속판 상에 절연층 (A, B) 을 개재시켜 형성된 회로와, 상기 회로 상에 실장되는 출력용 반도체와, 상기 출력용 반도체를 제어하고, 상기 회로 상에 형성되는 제어용 반도체로 이루어지는 혼성 집적 회로에 사용되는 금속 베이스 회로 기판으로서, 상기 제어용 반도체를 탑재하는 회로 부분 (패드 부분) 의 하부에 저정전 용량 부분을 매설하고 있는 것을 특징으로 하는 금속 베이스 회로 기판으로서, 바람직하게는 저정전 용량 부분이, 무기질 충전재를 함유하여 이루어진 수지로 이루어지며, 또한 유전율이 2～9 인 것을 특징으로 하는 상기의 금속 베이스 회로 기판. A metal base circuit board excellent in heat dissipation is provided by significantly reducing malfunction of a semiconductor generated during high frequency operation of a hybrid integrated circuit. Used in a hybrid integrated circuit comprising a circuit formed on the metal plate via insulating layers A and B, an output semiconductor mounted on the circuit, and a control semiconductor formed on the circuit by controlling the output semiconductor. A metal base circuit board, wherein a low capacitance portion is embedded below a circuit portion (pad portion) on which the control semiconductor is mounted. Preferably, the low capacitance portion is an inorganic filler. Said metal base circuit board | substrate, Comprising: It consists of resin which contains and the dielectric constant is 2-9.

Chip package and method of forming the same

本发明涉及芯片封装及形成芯片封装的方法。实施例提供了一种形成芯片封装的方法。方法可以包括：在载体上附着至少一个芯片，该芯片包括与载体相对的芯片表面上的多个芯片焊盘；在载体和芯片的芯片焊盘上沉积第一粘合层，第一粘合层包括锡或铟；在第一粘合层上沉积第二粘合层，第二粘合层包括硅烷有机材料；以及在第二粘合层和芯片上沉积层压层或密封层。

Semiconductor device

A semiconductor device includes a carrier, a chip including a first face having a contact area, where the chip is attached to the carrier such that the contact area faces away from the carrier, a copper connector configured for attachment to the contact area, and a solder material configured to couple the copper connector to the contact area.

Process for applying a material containing Si or Ge to a surface of Cu or Ni

Package-on-package (PoP) structure and method

本发明涉及堆叠封装(PoP)的结构和形成PoP结构的方法。根据一个实施例，结构包括第一衬底、螺柱球、管芯、第二衬底和电连接件。螺柱球与第一衬底的第一表面相接合。管芯附接至第一衬底的第一表面。电连接件与第二衬底连接，以及对应的电连接件与对应的螺柱球相连。

Semiconductor device including an insulating film and insulating pillars and manufacturing method of the semiconductor device

A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.

Electronic devices having metallurgies containing copper-semiconductor compounds

Silicon and germanium containing materials are used as a surface of conductors in electronic devices. Solder can be fluxlessly bonded and wires can be wire bonded to these surfaces. These materials are used as a surface coating for lead frames for packaging integrated circuit chips. These materials can be decal transferred onto conductor surfaces or electrolessly or electrolytically disposed thereon.

Method for manufacturing electronic devices

An embodiment for manufacturing electronic devices is proposed. The embodiment includes the following phases: a) forming a plurality of chips in a semiconductor material wafer including a main surface; each chip includes respective integrated electronic components and respective contact pads facing the main surface; said contact pads are electrically coupled to the integrated electronic components; b) attaching at least one conductive ribbon to at least one contact pad of each chip; c) covering the main surface of the semiconductor material wafer and the at least one conductive ribbon with a layer of plastic material; d) lapping an exposed surface of the layer of plastic material to remove a portion of the plastic material layer at least to uncover portions of the at least one conductive ribbon, and e) sectioning the semiconductor material wafer to separate the chips.

Semiconductor Device and Method of Providing Common Voltage Bus and Wire Bondable Redistribution

A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer.

Nitride semiconductor device

本发明的氮化物半导体装置具备：在氮化物半导体层之上形成的第1电极布线层以及第2电极布线层、在第1电极布线层以及第2电极布线层之上形成且具有第1开口部的第1绝缘膜、在第1绝缘膜之上形成且经由第1开口部而与第1电极布线层以及第2电极布线层分别连接的第1布线层(17a)以及第2布线层(17b)、在第1布线层以及第2布线层之上形成且具有第2开口部的第2绝缘膜(18)、和在第2绝缘膜之上形成且经由第2开口部而与第1布线层以及第2布线层分别连接的第1焊盘层(22a)以及第2焊盘层(22b)。

Semiconductor device

Ein Halbleiterbauelement enthält einen Träger, einen Chip, der eine erste Fläche mit einem Kontaktbereich enthält, wobei der Chip derart an dem Träger angebracht ist, dass der Kontaktbereich von dem Träger wegweist, ein Kupferverbindungsstück, das zum Anbringen an dem Kontaktbereich konfiguriert ist, und ein Lötmaterial, das konfiguriert ist, das Kupferverbindungsstück an den Kontaktbereich zu koppeln. A semiconductor device includes a carrier, a chip including a first surface having a contact region, the chip being attached to the carrier such that the contact region faces away from the carrier, a copper connector configured for attachment to the contact region, and Solder material configured to couple the copper connector to the contact area.

Partially patterned lead frames and methods of making and using the same in semiconductor packaging

A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is performed with a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation.

Multichip-Halbleitergehäuse und deren Zusammenbau

Halbleitergehäuse, umfassend:ein Substrat (10), das einen ersten (11) und einen zweiten (13) und einen dritten (12) Die-Attach-Pad umfasst, die getrennt voneinander angeordnet sind, wobei das dritte Die-Attach-Pad (12) ein inneres Die-Attach-Pad ist, das zwischen dem ersten Die-Attach-Pad (11) und dem zweiten Die-Attach-Pad (13) angeordnet ist;ein erstes Mikroplättchen (30) über dem ersten Die-Attach-Pad (11) angeordnet, wobei das erste Mikroplättchen (30) über einem ersten Teil des ersten Die-Attach-Pads (11) und über einem ersten Teil des dritten Die-Attach-Pads (12) angeordnet ist;ein zweites Mikroplättchen (30) über dem zweiten Die-Attach-Pad (13) angeordnet, wobei das zweite Mikroplättchen (30) über einem zweiten Teil des dritten Die-Attach-Pads (12) und über einem ersten Teil des zweiten Die-Attach-Pads (13) angeordnet ist;ein drittes Mikroplättchen (50) zwischen dem ersten (30) und dem zweiten (30) Mikroplättchen angeordnet, einen ersten Teil des dritten Mikroplättchens (50) über einem ersten Teil des ersten Mikroplättchens (30) angeordnet, einen zweiten Teil des dritten Mikroplättchens (50) über einem ersten Teil des zweiten Mikroplättchens (30) angeordnet, und einen dritten Teil des dritten Mikroplättchens (50) über einem ersten Bereich zwischen dem ersten Mikroplättchen (30) und dem zweiten Mikroplättchen (30) angeordnet.

Nitride semiconductor device

A nitride semiconductor device includes first electrode interconnect layers and second electrode interconnect layers formed over a nitride semiconductor layer, a first insulating film formed on the first and second electrode interconnect layers and including first openings, first interconnect layers and second interconnect layers formed on the first insulating film and respectively connected to the first electrode interconnect layers and the second electrode interconnection layers through the first openings, a second insulating film formed on the first and second interconnect layers and including second openings, and a first pad layer and a second pad layer formed on the second insulating film and respectively connected to the first interconnect layers and the second interconnect layers through the second openings.

窒化物半導体装置

窒化物半導体装置は、窒化物半導体層の上に形成された第１の電極配線層及び第２の電極配線層と、第１の電極配線層及び第２の電極配線層の上に形成され、第１の開口部を有する第１の絶縁膜と、第１の絶縁膜の上に形成され、第１の開口部を介して第１の電極配線層及び第２の電極配線層と各々接続する第１の配線層(17a)及び第２の配線層(17b)と、第１の配線層及び第２の配線層の上に形成され、第２の開口部を有する第２の絶縁膜(18)と、第２の絶縁膜の上に形成され、第２の開口部を介して第１の配線層及び第２の配線層と各々接続する第１のパッド層(22a)及び第２のパッド層(22b)とを備えている。

氮化物半导体装置

本发明的氮化物半导体装置具备：在氮化物半导体层之上形成的第1电极布线层以及第2电极布线层、在第1电极布线层以及第2电极布线层之上形成且具有第1开口部的第1绝缘膜、在第1绝缘膜之上形成且经由第1开口部而与第1电极布线层以及第2电极布线层分别连接的第1布线层(17a)以及第2布线层(17b)、在第1布线层以及第2布线层之上形成且具有第2开口部的第2绝缘膜(18)、和在第2绝缘膜之上形成且经由第2开口部而与第1布线层以及第2布线层分别连接的第1焊盘层(22a)以及第2焊盘层(22b)。

Verfahren zum aufbringen eines si oder ge enthaltenden materials auf eine oberfläche aus cu oder ni

공통 전압 버스 및 와이어 본더블 리디스트리뷰션을제공하는 반도체 장치 및 방법

반도체 웨이퍼가 다수 반도체 다이를 포함한다. 그 웨이퍼는 그것의 표면에 형성된 접촉 패드를 갖는다. 패시베이션 층이 웨이퍼상에 형성된다. 응력 버퍼 층이 패시베이션 층상에 형성된다. 그 응력 버퍼 층은 접촉 패드를 노출시키도록 패턴화된다. 금속 층이 응력 버퍼 층상에 융착된다. 그 금속 층은 접촉 패드와 전기적 접촉을 위한 공통 전압 버스이다. 부착 층, 배리어 층 및 시드 층이 접촉 패드와 전기적 접촉관계로 웨이퍼 상에 형성된다. 그 금속 층은 시드 층에 장착된다. 솔더 범프 또는 다른 상호 접속 구조체가 금속 층상에 형성된다. 제 2패시베이션 층이 금속 층상에 형성된다. 다른 실시예에서, 와이어본더블 층이 금속 층과 금속 층에 연결된 와이어본드 상에 융착된다.

Arrangement for electrically connecting semiconductor circuit arrangements to an external contact device and method for producing the same

An electrical connection arrangement between a semiconductor circuit arrangement and an external contact device, and to a method for producing the connection arrangement is disclosed. In one embodiment, a metallic layer is deposited onto at least one contact terminal and/or the contacts and the wire, the metallic layer protecting the contact terminal or the electrical connection against ambient influences and ensuring a high reliability.

Solderability improvement method for leaded semiconductor package

A microelectronic device package (100) that includes a microelectronic device (106) encapsulated within a packaging material (102). The microelectronic device package also includes a lead (104) attached to a portion of the microelectronic device extending through the packaging material. The lead has a break portion and a non-break portion on a tip of the lead.

Solderability improvement method for leaded semiconductor package

Solderability improvement method for leaded semiconductor package

A microelectronic device package (100) that includes a microelectronic device (106) encapsulated within a packaging material (102). The microelectronic device package also includes a lead (104) attached to a portion of the microelectronic device extending through the packaging material. The lead has a break portion and a non-break portion on a tip of the lead.

Partially patterned lead frames and methods of making and using the same in semiconductor packaging

A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is performed with a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation.

芯片封装和用于制作芯片封装的方法

芯片封装和用于制作芯片封装的方法。提供一种芯片封装，所述芯片封装包括：包括至少一个腔体的载体；至少部分地设置在至少一个腔体内的芯片；设置在芯片的至少一个侧壁上的至少一个中间层；其中至少一个中间层被配置为将来自芯片的热量热传导到载体。

Stackable package by using internal stacking modules

A semiconductor package comprises a substrate, a first semiconductor die mounted to the substrate, and a first double side mold (DSM) internal stackable module (ISM) bonded directly to the first semiconductor die through a first adhesive. The first DSM ISM includes a first molding compound, and a second semiconductor die disposed in the first molding compound. The semiconductor package further comprises a first electrical connection coupled between the first semiconductor die and the substrate, and a second electrical connection coupled between the first DSM ISM and the substrate.

Package on-package (PoP) structure including stud bulbs

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Package on-Package (PoP) structure including stud bulbs and method

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Integrated circuit assembly and method of making

A first wafer is provided that includes an insulating layer, a first active layer, and a handle layer. The insulating layer has a first surface and a second surface. The first active layer contacts the first surface of the insulating layer. The handle layer contacts the second surface of the insulating layer. A second wafer is provided that includes a substrate and a second active layer. The substrate has a first surface and a second surface. The second active layer contacts the first surface of the substrate. The second wafer is bonded to the first wafer by physically connecting the first active layer to the second surface of the substrate. The handle layer is removed. A metal bond pad is formed on the second surface of the insulating layer. The metal bond pad is electrically connected to the first active layer.