Stitch bump stacking design for overall package size reduction for multiple stack

A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.

Brace for long wire bond

An electrical connection includes a first wire bonded to adjacent bond pads proximate to an edge of a die and a second wire having one end bonded to a die bond pad distal to the die edge and a second end bonded to a lead finger of a lead frame or a connection pad of a substrate. The second wire crosses and is supported by the first wire. The first wire acts as a brace that prevents the second wire from touching the edge of the die. The first wire also prevents the second wire from excessive lateral movement during encapsulation.

Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices

A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.

Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereof

A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the first die through a die interconnect positioned between the first die and the second die; connecting a first lead adjacent the first die pad to the first die; connecting a second lead to the second die, the second lead opposing the first lead and adjacent the second die; and providing a molding material around the first die, the second die, the die interconnect, the first lead and the second lead, with a portion of the first lead exposed.

Light emitting device

A light emitting device comprises two or more light emitting elements, two or more lead frames electrically connected to the light emitting elements, and a case formed as a slender flat box shape and having an accommodating recession for accommodating the light emitting elements and the lead frame, wherein the lead frames are buried in the case and provided side by side in a longitudinal direction of the case, and the surfaces of the lead frames are arranged coplanar, the light emitting elements are mounted on the lead frames, and the plurality of lead frames and the case are arranged in a nearly linear symmetric configuration with respect to a central line that bisects the light emitting device in the longitudinal direction, so that no uneven heat distribution takes place.

Light emitting device and method for manufacturing the same

A light emitting device 10 includes a light emitting element 11 , a package 13 in which the light emitting element 11 is accommodated, and a sealing member 14 configured to seal the light emitting element 11 . The package 13 includes a base 13 B configured to hold the light emitting element 11 and a frame part 13 A vertically standing on the base 13 B so as to surround the light emitting element 11 . The sealing member 14 is embedded in a region surrounded by the frame part 13 A. The frame part 13 A includes a protruding wall 15 upwardly protruding from an upper end surface 132 a of the frame part 13 A and provided so as to surround the light emitting element 11.

Wire bonding method in circuit device

A wire bonding method in a circuit device mounted on a lead frame, the wire bonding method including: counting a stop time if an operation of a capillary stops; removing a contaminated free air ball (FAB) formed on an end of the capillary if the stop time exceeds a reference time; forming a new FAB; and restarting a wire bonding process.

Package-on-package assembly with wire bond vias

A structure includes a substrate having a first region and a second region, the substrate also having a first surface and a second surface. Electrically conductive elements are exposed at the first surface within the second region. Wire bonds have bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. At least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane. A bent portion of the at least one wire bond extends away from the axis within the plane. A dielectric encapsulation layer covers portions of the wire bonds such that unencapsulated portions, including the ends, of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer.

Method for fabricating a through wire interconnect (twi) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer

A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

SEMICONDUCTOR DEVICE WITH ACTIVE SHIELDING OF LEADS

A semiconductor device has a multi-wire lead and a die having a multi-site bond pad. A shielding wire and a guarded wire both extend from the multi-wire lead to the multi-site bond pad. The shielding wire (or wires) provide active shielding to the guarded wire by simultaneously transmitting the same signal as the guarded wire between the multi-wire lead the multi-site bond pad. 1. A semiconductor device , comprising:a die having a multi-site bond pad;a multi-wire lead;at least one shielding wire extending from the multi-wire lead to the multi-site bond pad; anda guarded wire extending from the multi-wire lead to the multi-site bond pad.2. The semiconductor device of claim 1 , wherein the multi-wire lead is “T” shaped.3. The semiconductor device of claim 2 , wherein the at least one shielding wire comprises two shielding wires extending from the multi-wire lead to the multi-site bond pad.4. The semiconductor device of claim 3 , wherein the two shielding wires extend between the multi-wire lead and the multi-site bond pad on opposite sides of the guarded wire.5. The semiconductor device of claim 1 , wherein the multi-site bond pad has at least one shielding-wire bond-pad site and a guarded-wire bond-pad site.6. The semiconductor device of claim 5 , wherein the multi-site bond pad has two shielding-wire bond-pad sites each located on opposite sides of the guarded-wire bond-pad site.7. The semiconductor device of claim 5 , wherein the at least one shielding-wire bond-pad site and the guarded-wire bond-pad site are physically connected to one another without having impedance therebetween.8. The semiconductor device of claim 1 , wherein the semiconductor device is a low-profile quad flat package.9. A method of actively shielding a guarded wire on a semiconductor device claim 1 , the method comprising:transmitting a first signal along the guarded wire, which extends between a multi-wire lead and a multi-site bond pad of a die; andsimultaneously transmitting the first ...

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer. 1. A structure comprising:a substrate having a first region and a second region, the substrate also having a first surface and a second surface remote from the first surface, wherein the first surface extends in first and second lateral directions to define a first plane;electrically conductive elements exposed at the first surface of the substrate within the second region;wire bonds having bases bonded to respective ones of the conductive elements and free ends remote from the substrate and remote from the bases, at least one of the wire bonds having a shape such that the at least one wire bond defines an axis between the free end and the base thereof coincident with a side surface of the at least one wire bond and such that the at least one wire bond defines a second plane, a bent portion of the at least one wire bond extending away from the axis within the second plane, wherein the entire at least one wire bond is positioned on one side of the axis and a substantially straight portion of the at least one wire bond extends between the free end ...

WIREBOND INTERCONNECT STRUCTURES FOR STACKED DIE PACKAGES

Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a second die disposed on a first die, a first plurality of interconnect structures disposed on a top surface of the first die, and a second plurality of interconnect structures disposed on a top surface of the second die. Top surfaces of the first plurality of interconnect structures are coplanar with top surfaces of the plurality of the second interconnect structures. At least one of the interconnect structures of the first or the second plurality of interconnect structures comprises a sigmoid shape. 1. A microelectronic package structure comprising:a first die;a second die disposed on the first die;a first plurality of interconnect structures disposed on a first surface opposite a second surface of the first die; anda second plurality of interconnect structures disposed on a first surface of the second die, wherein top surfaces of the first plurality of interconnect structures are coplanar with top surfaces of the plurality of the second interconnect structures, and wherein at least one of the first plurality of interconnect structures or one of the second plurality of interconnect structures comprises a sigmoid shape.2. The microelectronic package structure of wherein the first and the second plurality of interconnect structures comprise wire bonded interconnect structures.3. The microelectronic package structure of wherein a length of the first die is greater than a length of the second die.4. The microelectronic package structure of wherein a third die is disposed on the first surface of the second die.5. The microelectronic package structure of wherein a third plurality of interconnect structures is disposed on a top surface of the third die.6. The microelectronic package structure of wherein a top surface of the third plurality of interconnect structures is coplanar with the top surfaces of the first and the second ...

Package-on-package Assembly With Wire Bond Vias

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor module includes: a semiconductor device having a front-side electrode; a bonding wire having a bonding portion bonded to the front-side electrode; a first sealing member; and a second sealing member. The first sealing member seals a portion where the front-side electrode and the bonding wire are bonded to each other. The second sealing member covers the first sealing member. The first sealing member is higher than the second sealing member in elastic modulus. 1: A semiconductor module comprising:a semiconductor device having a front-side electrode;a bonding wire having a bonding portion bonded to the front-side electrode;a first sealing member filling a space between the bonding wire and the front-side electrode at a periphery of the bonding portion and having a first elastic modulus; anda second sealing member covering the first sealing member, being in contact with the front-side electrode, and having a second elastic modulus,the first elastic modulus being higher than the second elastic modulus,the front-side electrode having a recess around the bonding portion,the recess being formed away from the bonding portion,the recess being filled with the first sealing member.2: The semiconductor module according to claim 1 , wherein claim 1 , in a plan view claim 1 , the recess is formed so as to surround the bonding portion.3: The semiconductor module according to claim 2 , wherein the recess is continuously formed.4: The semiconductor module according to claim 1 , whereinthe recess has an opening, a side face, and a bottom, andin a plan view, the bottom or at least a part of the side face is located farther from the bonding portion than the opening is from the bonding portion.5: The semiconductor module according to claim 1 , wherein the first sealing member is higher than the second sealing member in electric conductivity.6: The semiconductor module according to claim 1 , wherein the first sealing member is lower than the second sealing member in ...

Semiconductor package having overhang portion

A semiconductor package may include a substrate, and a structural body disposed over the substrate. The semiconductor package may include a semiconductor chip stacked over the structural body, and having an overhang portion projecting over a side surface of the structural body and overhanging out over the side surface of the structural body. The semiconductor package may include one or more bonding pads disposed on the overhang portion, and one or more wires electrically coupling the bonding pads to the substrate. The semiconductor package may include a wire fixing film attached onto the structural body, and overhanging out over the side surface of the structural body to fix the one or more wires.

LIGHT EMITTING DIODE PACKAGE HAVING A SMALL LIGHT EMITTING SURFACE

A light emitting diode package, including: a housing, wherein the housing includes a primary cavity, a primary cavity light emitting surface, and a secondary cavity, wherein the secondary cavity is positioned adjacent to the primary cavity; a lead frame associated with the housing; a light emitting diode light source, wherein the light emitting diode light source is associated with the primary cavity of the housing; an encapsulant filled into the primary cavity, wherein the encapsulant is associated with a light converting element; and wherein the ratio of the surface area of the primary cavity light emitting surface to that of the light emitting diode light source is less than 2.0. 1. A light emitting diode package , comprising:a housing, wherein the housing includes a primary cavity, a primary cavity light emitting surface, and a secondary cavity, wherein the secondary cavity is positioned adjacent to the primary cavity;a lead frame associated with the housing;a light emitting diode light source, wherein the light emitting diode light source is associated with the primary cavity of the housing;an encapsulant filled into the primary cavity, wherein the encapsulant is associated with a light converting element; andwherein the ratio of the surface area of the primary cavity light emitting surface to that of the light emitting diode light source is less than 2.0.2. A light emitting diode package , comprising:a housing, wherein the housing includes a primary cavity, a primary cavity light emitting surface, and a secondary cavity, wherein the secondary cavity is positioned adjacent to the primary cavity;a lead frame associated with the housing;a light emitting diode light source, wherein the light emitting diode light source is associated with the primary cavity of the housing;an encapsulant filled into the primary cavity, wherein the encapsulant is associated with a light converting element; andwherein a wire connection is made between the primary and secondary ...

Straight wirebonding of silicon dies

A method including stacking a number of silicon dice such that one or more edges of the dice are in vertical alignment, where the one or more edges include a number of connection pads. The method also includes positioning a connecting wire on a substantially perpendicular axis to the one or more edges. The connecting wire includes a number of solder blocks formed thereon. The solder blocks are spaced at intervals associated with a distance between a first set of aligned connection pads on the dice. The connecting wire is positioned such that the solder blocks are in contact with the first set of aligned connection pads. The method also includes applying heat to cause the solder blocks to reflow and physically and electrically couple the connecting wire to the connection pads.

PRINTED CIRCUIT BOARD STRUCTURE HAVING PADS AND CONDUCTIVE WIRE

The disclosure provides a printed circuit board structure. The printed circuit board structure includes a printed circuit board, a semiconductor chip, a first pad, a second pad, a conductive wire, and a third pad. The semiconductor chip is disposed on the printed circuit board. The first pad is disposed on the semiconductor chip. The second pad is disposed on the printed circuit board. The conductive wire electrically connects the first pad and the second pad. The third pad is disposed between the first pad and the second pad. The conductive wire has a portion located on the third pad. 1. A printed circuit board structure , comprising:a printed circuit board;a semiconductor chip disposed on the printed circuit board;a first pad disposed on the semiconductor chip;a second pad disposed on the printed circuit board;a conductive wire electrically connecting the first pad and the second pad; anda third pad disposed between the first pad and the second pad, wherein the conductive wire has a portion located on the third pad, and wherein the third pad is electrically isolated from the semiconductor chip.2. The printed circuit board structure of claim 1 , wherein a distance between the first pad and the third pad is substantially equal to a distance between the second pad and the third pad in a horizontal direction.3. The printed circuit board structure of claim 1 , wherein the third pad is disposed on the semiconductor chip.4. The printed circuit board structure of claim 1 , wherein the second pad is electrically connected to the printed circuit board.5. The printed circuit board structure of claim 1 , wherein the first pad is electrically connected to the semiconductor chip.6. The printed circuit board structure of claim 1 , wherein the third pad is electrically isolated from the conductive wire.7. (canceled)8. The printed circuit board structure of claim 1 , wherein a top surface of the third pad is substantially coplanar with a top surface of the first pad.9. The printed ...

Semiconductor packages and methods of manufacturing the same

A semiconductor package comprises a board including a board pad, a plurality of semiconductor chips mounted on the board, the semiconductor chips including chip pads. Bumps are disposed on the chip pads, respectively, and a wire is disposed between the chip pads and the bumps. The wire electrically connects the chip pads of the plurality of semiconductor chips and the board pad to each other.

SEMICONDUCTOR DEVICE HAVING CONDUCTIVE WIRE WITH INCREASED ATTACHMENT ANGLE AND METHOD

A semiconductor device includes a shielding wire formed across a semiconductor die and an auxiliary wire supporting the shielding wire, thereby reducing the size of a package while shielding the electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted on the substrate, a shielding wire spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary wire supporting the shielding wire under the shielding wire and formed to be perpendicular to the shielding wire. In another embodiment, a bump structure is used to support the shielding wire. In a further embodiment, an auxiliary wire includes a bump structure portion and wire portion and both the bump structure portion and the wire portion are used to support the shielding wire. 1. A method of manufacturing a semiconductor device , comprising:providing a substrate;mounting a semiconductor component to the substrate;attaching an auxiliary structure to the substrate along only one side of the semiconductor component; and the first shielding wire is spaced apart from a major surface of the semiconductor component and extends across the major surface of the semiconductor component;', 'the first shielding wire physically contacts the auxiliary structure at a location other than either of the opposing ends; and', 'the auxiliary structure contacts the first shielding wire at a point laterally displaced from a maximum elevation of the first shielding wire., 'attaching opposing ends of a first shielding wire to the substrate, wherein2. The method according to claim 1 , further comprising: providing the substrate comprises providing the substrate including a first bonding pad at the one side of the semiconductor component and a second bonding pad at an opposite side of the semiconductor component;', ' ...

METHOD FOR FORMING AN ELECTRICAL CONNECTION BETWEEN AN ELECTRONIC CHIP AND A CARRIER SUBSTRATE AND ELECTRONIC DEVICE

An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire. 19-. (canceled)10. An electronic device , comprising:a carrier substrate;an electronic chip mounted on the carrier substrate;at least one electrical connection wire connecting an electrical connection pad of the carrier substrate and an electrical connection pad of the electronic chip;a dielectric layer made of a dielectric material on top of a zone of the electronic chip and of the carrier substrate, including the electrical connection wire and the electrical connection pads, such that the dielectric layer forms a local dielectric coating which at least partially surrounds the electrical connection wire and at least partially covers the electrical connection pads; anda local conductive shield made of an electrically conductive material at least partially covering the local dielectric coating.11. The electronic device according to claim 10 , wherein the local dielectric coating completely surrounds the electrical connection wire and completely covers the electrical connection pads and wherein the local conductive shield completely covers the local dielectric coating.12. The device according to claim 10 , further comprising at least one additional electrical connection wire connecting an additional electrical connection pad of the carrier substrate and an additional electrical connection pad of the electronic chip claim 10 , the local conductive shield making contact with at least one of ...

METHOD FOR FORMING AN ELECTRICAL CONNECTION BETWEEN AN ELECTRONIC CHIP AND A CARRIER SUBSTRATE AND ELECTRONIC DEVICE

An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire. 1. A method , comprising the following steps:placing an electrical connection wire between an exposed electrical connection pad of an electronic chip and an exposed electrical connection pad of a carrier substrate to which the electronic chip is mounted and forming electrical junctions between the ends of the electrical connection wire and the pads, the electrical connection wire being equipped with an insulating sheath made of a dielectric material which surrounds the electrical connection wire except at exposed ends of the electrical connection wire;producing a local dielectric coating made of a dielectric material, which at least partially covers at least one of the electrical connection pads, the electrical junction and exposed end of the electrical connection wire adjacent thereto and at least partially surrounds an end portion of the insulating sheath adjacent to the electrical junction; andproducing a conductive shield made of an electrically conductive material which at least partially covers said dielectric coating and at least partially surrounds the insulating sheath.2. The method according to claim 1 , wherein producing the local dielectric coating comprises distributing a determined amount of the dielectric material in the liquid state and hardening said dielectric material.3. The method according to claim 2 , wherein distributing comprises using a controlled tool to ...

ELECTRICALLY CONDUCTIVE BOND BETWEEN AT LEAST TWO ELECTRICAL COMPONENTS AT A CARRIER MOUNTED WITH ELECTRONIC AND/OR ELECTRICAL DEVICES, SAID BOND BEING FORMED BY A BOND WIRE

The invention relates to the electrically conductive bond between at least two electrical components and/or devices at a carrier mounted with electronic and/or electrical devices, said bond being formed by a bond wire. The bond wire is bonded in a force fitting, shape matching manner and/or with material continuity to the electrical components and/or devices and is shaped in an arcuate manner between the electrical components and/or devices at a spacing from the surface of the carrier and from electronic and/or electrical devices arranged there. The respective bond wire is bent a multiple of times with changing directions between the electrical components and/or devices such that tips or regions of individual arcs are arranged at different spacings from the surface of the carrier. At least one element formed from or by an electrically conductive material can, however, also be arranged between the surface of the carrier and the arcuate bond wire and the electrically conductive material is arranged at a spacing from the respective bond wire. 12611262676. An electrically conductive bond between at least two electrical components () and/or devices () at a carrier mounted with electronic and/or electrical devices , said electrically conductive bond being formed with a bond wire () , wherein the bond wire () is bonded with a force fit , shape matching and/or material continuity to the electrical components () and/or devices () and is shaped in arcuate form between the electrical components () and/or devices () at a spacing from the surface of the carrier () and electronic and/or electrical devices () arranged there , characterized in that{'b': 1', '2', '6', '1', '1', '1', '2', '7, 'the respective bond wire () is bent a multiple of times with changing directions between the electrical components () and/or devices () such that tips (.) or regions (.) of individual arcs are arranged at different spacings from the surface of the carrier ();'}{'b': 4', '7', '1', '1, 'and/or in ...

SEMICONDUCTOR PACKAGES AND MANUFACTURING METHODS FOR THE SAME

A semiconductor package and a fabrication method of the semiconductor package are disclosed. First and second redistribution layer patterns are formed on a semiconductor substrate including a chip region and a scribe lane region to provide a bonding pad portion and an edge pad portion, respectively. A polymer pattern is formed to reveal the bonding pad portion and a portion of the edge pad portion. A dicing line is set on the scribe lane region. A stealth dicing process is performed along the dicing line to separate a semiconductor chip including the bonding pad portion from the semiconductor substrate. The semiconductor chip is disposed on a package substrate. A bonding wire is formed to connect the bonding pad portion to the package substrate. The bonding wire is supported by an edge of the polymer pattern to be spaced apart from the revealed portion of the edge pad portion. 1. A method of fabricating a semiconductor package , the method comprising:preparing a semiconductor substrate including a chip region in which first pads are disposed and a scribe lane region in which second pads are disposed, wherein the scribe lane region surrounds the chip region;forming a dielectric layer on the semiconductor substrate so as to reveal the first and second pads;forming first redistribution layer patterns connected to the first pads and second redistribution layer patterns connected to the second pads on the dielectric layer, wherein the first redistribution layer patterns extend to provide bonding pads and the second redistribution layer patterns extend to provide edge pad portions located on the scribe lane region;forming a polymer pattern covering the first and second redistribution layer patterns, wherein the polymer pattern is formed so as to reveal the bonding pad portions and a boundary region including a portion of the dielectric layer on the scribe lane region and portions of the edge pad portions;setting a dicing line extending to surround the chip region in the ...

Compact wirebonding in stacked-chip system in package, and methods of making same

A bond-wire system including a wire bond that is deflected above a dielectric ridge at a die edge. The deflected wire bond allows for both a lowered Z-profile and a reduced X-Y footprint. The bond-wire system may include a stacked-die configuration where a stacked die is wire bonded and the stacked-die bond wire is deflected above a dielectric ridge at the stacked die edge.

FAN-OUT SEMICONDUCTOR PACKAGE

A fan-out semiconductor package includes: a core member having a first through-hole and including first and second wiring layer disposed on different levels; a first semiconductor chip disposed in the first through-hole; a second semiconductor chip disposed on the first semiconductor chip in the first through-hole so that a second inactive surface faces a first inactive surface; conductive wires disposed on the core member and a second active surface and electrically connecting second connection pads and the second wiring layer to each other; an encapsulant covering at least portions of the core member, the first semiconductor chip, the second semiconductor chip, and the conductive wires and filling at least portions of the first through-hole; and a connection member disposed on the core member and a first active surface and electrically connecting first connection pads and the first wiring layer to each other. 1. A fan-out semiconductor package comprising:a core member having a first through-hole and including first and second wiring layer disposed on different levels;a first semiconductor chip having a first active surface having first connection pads disposed thereon and a first inactive surface opposing the first active surface and disposed in the first through-hole;a second semiconductor chip having a second active surface having second connection pads disposed thereon and a second inactive surface opposing the second active surface and disposed on the first semiconductor chip in the first through-hole so that the second inactive surface faces the first inactive surface;conductive wires disposed on the core member and the second active surface and electrically connecting the second connection pads and the second wiring layer to each other;an encapsulant covering at least portions of the core member, the first semiconductor chip, the second semiconductor chip, and the conductive wires and filling at least portions of the first through-hole; anda connection ...

Electrode connection structure and electrode connection method

An electrode connection structure includes: a first electrode of an electrical circuit; and a second electrode of the electrical circuit that is electrically connected to the first electrode. The first and second electrodes are oppositely disposed in direct or indirect contact with each other. A plated lamination is substantially uniformly formed by plating process from a surface of a contact region and opposed surfaces of the first and second electrodes. A void near the surface of the contact region is filled by formation of the plated lamination. Portions of the plated lamination formed from the opposed surfaces of the first and second electrodes in a region other than the contact region are not joined together.

SEMICONDUCTOR DEVICE

A semiconductor device includes two or more semiconductor elements, a lead with island portions on which the semiconductor elements are mounted, a heat dissipation member for dissipating heat from the island portions, a bonding layer bonding the island portions and the heat dissipation member, and a sealing resin covering the semiconductor elements, the island portions and a part of the heat dissipation member. The bonding layer includes mutually spaced individual regions provided for the island portions, respectively. 120-. (canceled)21. A semiconductor device comprising:a semiconductor element;a lead on which the semiconductor element is mounted; anda wire electrically connected to the semiconductor element,wherein the wire includes a first bonding portion, a second bonding portion and a reinforcing bonding portion, the second bonding portion gradually reducing in thickness from a boundary provided by a stepped portion, the reinforcing bonding portion overlapping with at least a part of the second bonding portion and exposing the stepped portion.22. The semiconductor device according to claim 21 , wherein the reinforcing bonding portion includes a disk portion held in contact with the second bonding portion.23. The semiconductor device according to claim 22 , wherein the reinforcing bonding portion includes a columnar portion that is formed on the disk portion claim 22 , smaller in diameter than the disk portion and concentric with the disk portion.24. The semiconductor device according to claim 23 , wherein the reinforcing bonding portion includes a peak portion formed on the columnar portion.25. The semiconductor device according to claim 21 , further comprising a circular trace that is formed by a pressed capillary and located close to the second bonding portion.26. The semiconductor device according to claim 25 , wherein a part of the circular trace is exposed from the reinforcing bonding portion.27. The semiconductor device according to claim 26 , wherein the ...

METHOD FOR FORMING AN ELECTRICAL CONNECTION BETWEEN AN ELECTRONIC CHIP AND A CARRIER SUBSTRATE AND ELECTRONIC DEVICE

An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire. 1. A method , comprising the following steps:placing an electrical connection wire between an exposed electrical connection pad of an electronic chip and an exposed electrical connection pad of a carrier substrate to which the electronic chip is mounted and forming electrical junctions between the ends of the electrical connection wire and the pads;producing a dielectric coating made of a dielectric material, which completely covers the electrical connection wire and completely covers the electrical junctions and further at least partially covers each of the electrical connection pads; andproducing a conductive shield made of an electrically conductive material which at least partially covers said dielectric coating at said electrical connection pads and completely covers said dielectric coating at said electrical junctions and further completely surrounds said dielectric coating at said electrical connection wire.2. The method according to claim 1 , wherein producing the dielectric coating comprises distributing a determined amount of the dielectric material in the liquid state and hardening said dielectric material.3. The method according to claim 2 , wherein distributing comprises using a controlled tool to dispense the dielectric material in the liquid state.4. The method according to claim 3 , wherein the controlled tool is a dispensing syringe.5. The method according to claim 1 , ...

SENSOR PACKAGE AND MANUFACTURING METHOD THEREOF

A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise an interconnection structure, for example a bond wire, at least a portion of which extends into a dielectric layer utilized to mount a plate, and/or that comprise an interconnection structure that extends upward from the semiconductor die at a location that is laterally offset from the plate. 120-. (canceled)21. A sensor device comprising:a substrate having a top substrate side, a bottom substrate side, and lateral substrate sides between the top and bottom substrate sides, the substrate comprising a conductive layer on the top substrate side;a semiconductor die having a top die side, a bottom die side coupled to the top substrate side, and lateral die sides between the top and bottom die sides, the semiconductor die comprising a sensing area on the top die side and a conductive pad on the top die side;a conductive interconnection structure electrically connecting the conductive pad of the semiconductor die to the conductive layer of the substrate;a dielectric layer (DL) having a top DL side, a bottom DL side coupled to the top die side, and lateral DL sides between the top and bottom DL sides; anda plate positioned over the sensing area of the semiconductor die, the plate having a top plate side, a bottom plate side coupled to the top DL side, and lateral plate sides between the top and bottom plate sides, wherein the center of the plate is laterally offset from the center of the sensing area of the semiconductor die.22. The sensor device of claim 21 , wherein the dielectric layer comprises an adhesive layer that adheres the bottom plate side to the top die side.23. The sensor device of claim 21 , wherein the dielectric layer is transparent.24. The sensor device of claim 21 , wherein the dielectric layer completely covers the ...

FINGERPRINT SENSOR AND MANUFACTURING METHOD THEREOF

A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise an interconnection structure, for example a bond wire, at least a portion of which extends into a dielectric layer utilized to mount a plate, and/or that comprise an interconnection structure that extends upward from the semiconductor die at a location that is laterally offset from the plate. 1. A fingerprint sensor device comprising:a substrate having a top substrate side, a bottom substrate side, and lateral substrate sides between the top and bottom substrate sides, the substrate comprising a conductive layer on the top substrate side;a semiconductor die having a top die side, a bottom die side, and lateral die sides between the top and bottom die sides, the semiconductor die comprising a bond pad on the top die side;a conductive interconnection structure electrically connecting the bond pad and the conductive pattern;a dielectric layer (DL) having a top DL side, a bottom DL side coupled to the top die side, and lateral DL sides between the top and bottom DL sides; andan encapsulating material covering the top substrate side, the lateral die sides, and the conductive interconnection structure.220-. (canceled) The present application makes reference to, claims priority to, and claims the benefit of Korean Patent Application No. 10-2015-0079157, filed on Jun. 4, 2015, in the Korean Intellectual Property Office and titled “PACKAGE OF FINGERPRINT SENSOR,” the contents of which are hereby incorporated herein by reference in their entirety.Present semiconductor packages and methods for forming sensor devices (e.g., fingerprint sensor devices) are inadequate, for example resulting in inadequate sensing accuracy and/or device reliability, manufacturability issues, devices that are thicker than necessary, devices that are difficult and/or ...

Signal block and double-faced cooling power module using the same

A signal block and a double-faced cooling power module that uses the signal block is provided. The signal block includes a plurality of signal clips that are formed in a ribbon shape to connect a first signal pad formed on a semiconductor chip and a second signal pad formed on a signal lead frame. An insulator fixes the position of the plurality of signal clips while spacing the signal clips apart from each other.

BOND WIRE SUPPORT SYSTEMS AND METHODS

A system includes a substrate; a bond pad; a wire spanning above the substrate, having a first end bonded to the bond pad and a second end extending from the bond pad to terminate in a second end thereof; and a support structure disposed on the substrate, the support structure comprising at least a side wall and extending from the substrate to terminate in an end portion spaced from the substrate to support the wire. 1. A system comprising:a substrate;a bond pad;a wire, spanning above the substrate, having a first end bonded to the bond pad and a second end extending from the bond pad to terminate in a second end thereof; anda support structure disposed on the substrate, the support structure comprising at least a side wall and extending from the substrate to terminate in an end portion spaced from the substrate to support the wire.2. The system of claim 1 , wherein the substrate comprises at least one of an integrated circuit microchip claim 1 , a leadframe claim 1 , and a lead finger.3. The system of claim 2 , wherein the substrate comprises a monolithic structure claim 2 , and wherein the leadframe comprises the lead finger.4. The system of claim 1 , further comprising a second substrate claim 1 , wherein the first substrate comprises a leadframe claim 1 , wherein the second substrate comprises an integrated circuit microchip supported by the leadframe claim 1 , wherein the bond pad is disposed on the integrated circuit microchip claim 1 , and wherein the support structure is disposed proximate to the bond pad.5. The system of claim 4 , further comprising a third substrate claim 4 , wherein the third substrate comprises a lead finger supported by the leadframe claim 4 , and wherein the second end of the bond wire is bonded to the lead finger.6. The system of claim 4 , further comprising a third substrate claim 4 , wherein the third substrate comprises a second integrated circuit microchip supported by the leadframe claim 4 , and wherein the second end of the bond ...

Semiconductor device

A semiconductor device includes a semiconductor element, a substrate, a lead, and a sealing resin member. The semiconductor element has a first electrode and a second electrode located on opposite sides in the thickness direction. The substrate has an insulating base and a conductive plate. The base has first and second surfaces located on opposite sides in the thickness direction. The conductive plate is bonded to the first surface of the base and electrically connected to the second electrode of the semiconductor element. The lead has an island electrically connected to the first electrode. The sealing resin member covers at least the semiconductor element.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

A semiconductor device includes: a board; a semiconductor chip that is not joined to the board; a wire whose one end is coupled with the semiconductor chip and whose other end is coupled with the board; and a first cover member that covers a first wire coupling portion in which the wire is coupled with the semiconductor chip. 1. A semiconductor device comprising:a board;a semiconductor chip that is not joined to the board;a wire whose one end is coupled with the semiconductor chip and whose other end is coupled with the board; anda first cover member that covers a first wire coupling portion in which the wire is coupled with the semiconductor chip.2. The semiconductor device according to claim 1 , further comprising:a second cover member that covers a second wire coupling portion in which the wire is coupled with the board.3. The semiconductor device according to claim 2 ,wherein the first cover member and the second cover member are configured with a resin material.4. The semiconductor device according to claim 1 , further comprising:a lid body that houses the semiconductor chip and the wire in an internal portion of the lid body.5. The semiconductor device according to claim 4 , further comprising:a low-elasticity member that has a lower elastic modulus than the lid body and surrounds an outer periphery of the semiconductor chip,wherein the wire is embedded in an internal portion of the low-elasticity member.6. The semiconductor device according to claim 4 , further comprising:a low-elasticity member that covers an internal wall of the lid body and has a lower elastic modulus than the lid body.7. The semiconductor device according to claim 1 ,wherein the board has a recess in a surface, andthe semiconductor chip is arranged in a space that is formed by the recess.8. The semiconductor device according to claim 1 , further comprising:an electrically releasable adhesive member that is provided between the semiconductor chip and the board and is released by being ...

SEMICONDUCTOR DEVICE

A semiconductor device includes two or more semiconductor elements, a lead with island portions on which the semiconductor elements are mounted, a heat dissipation member for dissipating heat from the island portions, a bonding layer bonding the island portions and the heat dissipation member, and a sealing resin covering the semiconductor elements, the island portions and a part of the heat dissipation member. The bonding layer includes mutually spaced individual regions provided for the island portions, respectively. 120-. (canceled)21. A semiconductor device comprising:a first island:a first semiconductor element, a second semiconductor element, a third semiconductor element, a fourth semiconductor element, a fifth semiconductor element and a sixth semiconductor element mounted on the first island and spaced apart from each other in plan view, the second semiconductor element overlapping with the first semiconductor element as viewed in a first direction, the third semiconductor element overlapping with the first semiconductor element as viewed in a second direction perpendicular to the first direction, the fourth semiconductor element overlapping with the third semiconductor element as viewed in the first direction, the fifth semiconductor element overlapping with the third semiconductor element as viewed in the second direction, the sixth semiconductor element overlapping with the fifth semiconductor element as viewed in the first direction;a second island spaced apart from the first island;a first control IC mounted on the second island for driving the first semiconductor element, the third semiconductor element and the fifth semiconductor element;a first terminal, a second terminal and a third terminal spaced from each other and spaced from the first island and the second island in plan view;a first wire connecting the first semiconductor element to the second semiconductor element;a second wire connecting the first wire to the first terminal;a third wire ...

Radiofrequency transmission/reception device

A radiofrequency transmission/reception device includes a first and a second conductive wire element, a first far-field transmission/reception chip and a second near-field transmission/reception chip. The first and the second wire element combine with the characteristic impedance of the second transmission/reception chip in order to form a coupling device associated with the first transmission/reception chip at the operating frequency of the first chip. The first and the second wire element combine with the characteristic impedance of the first transmission/reception chip in order to form a coupling device associated with the second transmission/reception chip at the operating frequency of the second chip.

SEMICONDUCTOR DEVICE

A semiconductor device includes two or more semiconductor elements, a lead with island portions on which the semiconductor elements are mounted, a heat dissipation member for dissipating heat from the island portions, a bonding layer bonding the island portions and the heat dissipation member, and a sealing resin covering the semiconductor elements, the island portions and a part of the heat dissipation member. The bonding layer includes mutually spaced individual regions provided for the island portions, respectively. 120-. (canceled)21. A semiconductor device , comprising:a first island part,a first semiconductor chip mounted on the first island part,a second island part,a second semiconductor chip mounted on the second island part,a third island part,a third semiconductor chip mounted on the third island part,a fourth island part,a fourth semiconductor chip mounted on the forth island part,a fifth semiconductor chip mounted on the forth island part,a sixth semiconductor chip mounted on the forth island part,a fifth island part,a first driving semiconductor chip mounted on the fifth island part and connected to each of the first to third semiconductor chips,a sixth island part,a second driving semiconductor chip mounted on the sixth island part and connected to each of the fourth to sixth semiconductor chips,a first lead terminal connected to the first semiconductor chip by a first wire,a second lead terminal connected to the second semiconductor chip by a second wire,a third lead terminal connected to the third semiconductor chip by a third wire,a fourth lead terminal connected to the fourth semiconductor chip by a fourth wire,a fifth lead terminal connected to the fifth semiconductor chip by a fifth wire,a sixth lead terminal connected to the sixth semiconductor chip by a sixth wire, anda seventh lead terminal extending from the fourth island part,wherein the first to sixth semiconductor chips are arranged in a first direction in a row,the first lead terminal is ...

Method for inserting a wire into a groove of a semiconductor chip, and piece of equipment for implementing such a method

A method for inserting a wire into a longitudinal groove of a semiconductor chip for the assembly thereof, the groove containing a pad made of a bonding material having a set melting point, the method comprises: in a positioning step, placing a longitudinal section of the wire along the groove, in forced abutment against the pad; and, in an insertion step, exposing a zone containing at least one portion of the pad to a processing temperature higher than the melting point of the bonding material and for a sufficient time to make the pad at least partially melt, and causing the wire to be inserted into the groove. The present disclosure also relates to a piece of equipment allowing the insertion method to be implemented.

Electrode connection method and electrode connection structure

Provided is an electrode connection method and the like which make it possible to connect tightly without leaving a gap, by connecting by plating while electrodes in an electrical circuit contact one another in a dot or linear pattern. Contact is made directly or indirectly in at least part of the interval between a plurality of electrically connected electrodes in an electrical circuit, and the interval between electrodes is plated and connected while a plating fluid flows around the periphery of the contact section. In addition, the contact section maintains a linear or dot pattern. Furthermore, nickel or a nickel alloy or copper or a copper alloy is used as the material for performing the plating, while the material for the surface of the electrodes to be connected is nickel or a nickel alloy, copper or a copper alloy, gold or a gold alloy, silver or a silver alloy, or palladium or a palladium alloy.

SEMICONDUCTOR PACKAGES AND MANUFACTURING METHODS FOR THE SAME

A semiconductor package and a fabrication method of the semiconductor package are disclosed. First and second redistribution layer patterns are formed on a semiconductor substrate including a chip region and a scribe lane region to provide a bonding pad portion and an edge pad portion, respectively. A polymer pattern is formed to reveal the bonding pad portion and a portion of the edge pad portion. A dicing line is set on the scribe lane region. A stealth dicing process is performed along the dicing line to separate a semiconductor chip including the bonding pad portion from the semiconductor substrate. The semiconductor chip is disposed on a package substrate. A bonding wire is formed to connect the bonding pad portion to the package substrate. The bonding wire is supported by an edge of the polymer pattern to be spaced apart from the revealed portion of the edge pad portion. 1. A semiconductor package comprising:a semiconductor chip including an edge pad portion and a bonding pad portion, wherein an edge of edge pad portion is aligned with an edge of the semiconductor chip;a package substrate on which the semiconductor chip is disposed, wherein the package substrate includes a bond finger; anda bonding wire connecting the bonding pad portion to the bond finger, a semiconductor substrate; and', 'a polymer pattern formed on the semiconductor substrate to reveal edge portions of the semiconductor chip, a portion of the edge pad portion adjacent to an edge of the semiconductor chip, and the bonding pad portion, and, 'wherein the semiconductor chip includeswherein a portion of the bonding wire is physically supported by an edge of the polymer pattern such that the bonding wire is spaced apart from the edge pad portion, andwherein the edge of the polymer pattern is in direct contact with the revealed portions of the edge pad portions.2. The semiconductor package of claim 1 , wherein the semiconductor substrate includes:a first pad disposed in a chip region; anda second ...

半導体装置のワイヤ−ボンデイング方法

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

지지 테이프를 이용한 초박형 반도체 패키지 소자

본 발명에 따른 반도체 패키지 소자는 다이 패드 대신에 필름형 접착 지지 테이프를 사용하며, 반도체 칩과, 이 칩의 전극 패드와 전기적으로 연결되고, 활성면과 높이가 동일한 상부면을 갖는 내부 리드를 포함하는 리드 프레임과, 칩의 전극 패드와 내부 리드를 전기적으로 연결하는 복수의 본딩 와이어와, 반도체 칩, 지지 테이프, 본딩 와이어를 보호하는 성형 몸체를 포함한다. 내열성 지지 테이프는 내부 리드의 상부면과 반도체 칩의 활성면에 부착되어 내부 리드와 반도체 칩을 지지하는데, 지지 테이프는 본딩 와이어가 접속되는 칩의 전극 패드와 내부 리드의 본딩부를 개방하는 전극 패드 개방 영역과 본딩부 개방 영역을 포함하며, 성형 몸체는 칩의 밑면과 일치하며, 칩의 밑면은 성형 몸체로부터 노출되어 있고, 지지 테이프의 전극 패드 개방 영역은 각각의 전극 패드에 대해 개별적으로 형성될 수도 있고, 복수의 전극 패드 열 전체에 대해 일체형으로 형성될 수도 있다. 지지 테이프는 반도체 칩의 활성면을 부분적으로 노출시켜 상기 노출된 부분이 성형 몸체와 직접 접촉되도록 하는 활성면 개방 영역을 포함할 수도 있다. 내부 리드는 칩의 모든 옆면 둘레에 배치되어 있고, 지지 테이프는 칩의 전극 패드와 제1 복수의 본딩 와이어와 전기적으로 연결되는 제1 본딩부와 내부 리드와 제2 복수의 본딩되는 제2 본딩부 및 제1 본딩부와 제2 본딩부를 전기적으로 연결하는 배선 패턴을 포함한다.

Light-emitting device

실시예는 발광소자패키지에 관한 것이다. 실시예에 따른 발광소자패키지는 제1 리드프레임 상에 위치하고, 상면에 전극패드를 구비하는 발광소자, 상기 제1 리드프레임과 이격되어 위치하는 제2 리드프레임과 상기 전극패드를 전기적으로 연결하는 제1 와이어 및 상기 제2 리드프레임 상에서, 상기 제1 와이어와 상기 제2 리드프레임이 접하는 제1 접점과 이격되어 위치하는 제1 접합볼 을 포함하고, 상기 제1 접합볼은 상기 제1 와이어와 상기 제2 리드프레임 사이에 위치하여, 상기 제1 와이어와 상기 제2 리드프레임을 전기적으로 연결할 수 있다. 실시예에 따른 발광소자패키지는 와이어 본딩시 접합볼을 사용함으로써 와이어를 고정하여 리드프레임의 와이어 접합부가 끊어지는 것을 방지하고, 접합볼을 통하여 와이어가 리드프레임에 전기적으로 연결될 수 있어 와이어 본딩에 관한 신뢰성을 개선시키는 효과를 가진다. An embodiment relates to a light emitting device package. A light emitting device package according to an exemplary embodiment of the present invention includes a light emitting element located on a first lead frame and having an electrode pad on an upper surface thereof, a second lead frame spaced apart from the first lead frame, And a first bonding ball located on a first lead frame and spaced apart from a first contact where the first wire and the second lead frame are in contact with each other on the first lead frame and the first bonding ball, The first lead frame and the second lead frame, and electrically connect the first wire and the second lead frame. In the light emitting device package according to the embodiment, when the wire bonding is used, the wire bonding is prevented by fixing the wire by bonding the wire, and the wire can be electrically connected to the lead frame through the bonding ball, And has an effect of improving the reliability.

semiconductor package and method for manufacturing the same

본 발명은 반도체 패키지에 관한 것이다. 본 발명에 따른 반도체 패키지는 제1 패키지 기판과 제2 패키지 기판을 전기적으로 연결시키는 본딩 와이어 및 상기 제1 패키지 기판과 상기 제2 패키지 기판을 접착시키며, 일부가 상기 본딩 와이어를 덮도록 형성된 절연막을 포함한다. The present invention relates to a semiconductor package. A semiconductor package according to the present invention includes a bonding wire for electrically connecting a first package substrate and a second package substrate, and an insulating film formed to cover the first package substrate and the second package substrate, . 반도체, 패키지, 본딩 와이어, 접착막, Semiconductor, package, bonding wire, adhesive film,

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Wafer level chip size package and method for fabricating the same

본 발명 웨이퍼 레벨 칩 사이즈 패키지는, 반도체 기판과 연결된 칩 패드 및 외부 칩 패드를 구비하되, 칩 패드는 보호막에 의해 표면에 노출되고, 외부 칩 패드 상기 보호막 위에서 노출된 구조를 갖는 웨이퍼 레벨 칩 사이즈 패키지에 관한 것으로서, 칩 패드 및 외부 칩 패드 위에 형성된 스터드 범프와, 스터드 범프를 상호 연결하는 와이어와, 외부 칩 패드 위에서 스터드 범프와 일정 간격 이격되도록 형성된 단자 스터드 범프와, 단자 스터드 범프 표면 위에 형성된 솔더 볼, 및 솔더 볼이 노출되도록 스터드 범프, 와이어 및 단자 스터드 범프를 덮는 몰딩재를 구비한다. The wafer level chip size package of the present invention includes a chip pad connected to a semiconductor substrate and an external chip pad, wherein the chip pad is exposed on the surface by a protective film, and the external chip pad has a structure exposed on the protective film. The present invention relates to a stud bump formed on a chip pad and an external chip pad, a wire interconnecting the stud bump, a terminal stud bump formed to be spaced apart from the stud bump on the outer chip pad by a predetermined distance, and a solder ball formed on the terminal stud bump surface. And a molding material covering the stud bumps, the wires and the terminal stud bumps to expose the solder balls.

Light emitting device and lighing system

PURPOSE: A light emitting device and a lighting system including the same are provided to improve a manufacturing process by supporting a metal layer with an insulation film instead of a package body. CONSTITUTION: A first metal layer(11), a second metal layer(13) and a third metal layer are separated. A first insulation film(21) is formed around the first, second, and third metal layers. A second insulation layer is formed in boundaries between the first and third metal layers and between the second and third metal layers. A light emitting chip is arranged on the third metal layer and is electrically connected to the first metal layer and the second metal layer. A first guide member is formed around the upper side of the first insulation film. A second guide member is formed on the upper side of the second insulation film. A resin layer surrounds the light emitting chip.

Package body

一种封装体，包括引线框架和芯片，其中，所述引线框架包括基岛和引脚，所述芯片设置于所述引线框架的所述基岛上。所述芯片具有至少一个焊盘，所述焊盘通过一第一连接线与所述引脚电性连接；所述第一连接线与所述引脚之间具有两个接触点，或者，所述第一连接线与所述引脚的接触点处还设置一第二连接线，所述第二连接线的两端均与所述引脚接触。

Semiconductor package, manufacturing method thereof, card comprising same and system comprising same

와이어들 사이의 단선을 방지하여 신뢰성을 높일 수 있는 반도체 패키지 및 그 제조 방법을 제공하고, 이러한 반도체 패키지를 포함하는 카드 및 시스템을 제공한다. 반도체 패키지에 있어서, 패키지 기판이 제공되고, 하나 이상의 반도체 칩은 상기 패키지 기판 상에 적층된다. 하나 이상의 와이어는 상기 하나 이상의 반도체 칩 및 상기 패키지 기판을 전기적으로 연결한다. 복수의 절연성 비드들은 상기 하나 이상의 와이어를 한바퀴 감싸고 상기 하나 이상의 와이어를 따라서 서로 이격 배치된다. Provided are a semiconductor package and a method of manufacturing the same, which can increase the reliability by preventing disconnection between wires, and provide a card and a system including the semiconductor package. In a semiconductor package, a package substrate is provided, and one or more semiconductor chips are stacked on the package substrate. One or more wires electrically connect the one or more semiconductor chips and the package substrate. The plurality of insulating beads wrap one or more wires one by one and are spaced apart from each other along the one or more wires.

Method for fabricating semiconductor components with through wire interconnects

A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer scale components, stacked components, or interconnect components for electrically engaging or testing other semiconductor components.

Semiconductor components having through wire interconnects (TWI)

A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire. A system for fabricating the semiconductor component includes a bonding capillary configured to place the wire in the via, and to form a bonded connection between the wire and the substrate contact.

Semiconductor components having encapsulated through wire interconnects (TWI)

A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) attached to the substrate contact. The through wire interconnect provides a multi level interconnect having contacts on opposing first and second sides of the semiconductor substrate. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via having a bonded connection with the substrate contact, a first contact on the wire proximate to the first side, and a second contact on the wire proximate to the second side. The through wire interconnect (TWI) also includes a polymer layer which partially encapsulates the through wire interconnect (TWI) while leaving the first contact exposed. The semiconductor component can be used to fabricate stacked systems, module systems and test systems. A method for fabricating the semiconductor component can include a film assisted molding process for forming the polymer layer.

Semiconductor device and manufacturing method thereof

Lead frame for semiconductor package

본 고안은 반도체 패키지용 리드 프레임에 관한 것으로, 인너 리드의 내측단부의 상,하면과 인너 리드들 사이를 포함하여 소정의 폭을 가지며 인너 리드의 상면보다 높게 돌출되는 절연체에 완전히 매립하여 연결 고정함으로써 각 인너 리드(1)의 평탄도를 유지하고, 외력에 의하여 인접한 인너 리드(1)가 변형되면서 접촉되는 현상을 근본적으로 방지하여 쇼트 현상을 방지하며, 와이어 본딩을 위한 캐필러리의 접촉으로 인너 리드(1)가 좌우로 뒤틀리는 현상을 방지할 뿐만 아니라 반도체 칩(3)과 인너 리드(1)를 연결하는 2차 본드 공정 시 인너 리드(1)의 상면보다 높게 돌출되어 있는 절연체(11)에 의하여 와이어(4)가 하측으로 처지는 현상을 방지함으로써 보다 안정적인 2차 본드를 수행할 수 있도록 한 것이다. The present invention relates to a lead frame for a semiconductor package, and includes a space between the upper and lower ends of the inner lead and the inner leads, and is completely embedded in and fixed to an insulator protruding higher than the upper surface of the inner lead. Maintain the flatness of each inner lead 1, prevent the shorting phenomenon by fundamentally preventing the adjacent inner lead 1 from being deformed by external force, and by the contact of the capillary for wire bonding, the inner lead The insulator 11 protrudes higher than the upper surface of the inner lead 1 during the secondary bonding process for connecting the semiconductor chip 3 and the inner lead 1 as well as preventing the distortion of the right and left sides. By preventing the wire 4 from sagging downward, more stable secondary bonding can be performed.

Light emitting device and lighing system

실시 예에 따른 발광 소자는, 서로 이격된 복수의 금속층, 상기 복수의 금속층의 상면 둘레에 형성된 제1절연 필름, 상기 복수의 금속층 중 어느 한 금속층 위에 배치되며 다른 금속층과 전기적으로 연결된 발광 칩 및 상기 발광 칩을 둘러싸는 수지층을 포함하며, 상기 수지층은 볼록한 반구형상일 수 있다.

Semiconductor device and its manufacture

(57)【要約】 【課題】高さの異るワイヤループを有する半導体装置に おいて、これらのワイヤループ間のワイヤショートを防 止する。 【解決手段】ＩＣチップ３とリードフレーム４は、ＩＣ チップ上の内側にあるボンディングパッドほど高いボン ディングワイヤループ２によって接続されており、高さ の異るボンディングループ２間に絶縁物１を介在させて いる。

Package-on-package assembly with wire bond vias

A microelectronic package can include wire bonds having bases bonded to respective conductive elements on a substrate and ends opposite the bases. A dielectric encapsulation layer extending from the substrate covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds which are uncovered by the encapsulation layer. Unencapsulated portions can be disposed at positions in a pattern having a minimum pitch which is greater than a first minimum pitch between bases of adjacent wire bonds.

Manufacturing method of sensor device and sensor device

A method for manufacturing a sensor device is provided. The method prevents corrosion of metal electrodes of a sensor due to outside air with high humidity and preventing the occurrence of warpage of the sensor due to resin sealing of the sensor, thereby reducing the influence on sensor characteristics, and provides the sensor device. The method includes arranging a sensor on a substrate, the sensor having a fixed part, a movable part positioned inside the fixed part, a flexible part connecting the fixed part and the movable part, and a plurality of metal electrodes, electrically connecting the plurality of metal electrodes of the sensor and a plurality of terminals of the substrate with bonding wires, and covering portions of the plurality of metal electrodes of the sensor connected to the bonding wires with a resin so that a part of the bonding wires between the plurality of metal electrodes and the plurality of terminals is exposed.

Plastic electronic component package

一种用于图像传感器的塑料封装体，该封装体包括塑料框体，所述塑料框体围绕引线框架成型并且限定腔体，图像传感器布置于所述腔体中。提供了有保持在塑料盖子框架中的透明玻璃盖的盖子组件，所述盖子框架可与封装体的塑料框体焊接或以其它方式接合，以包封安装在腔体中的图像传感器。在引线框架的表面上形成界面层，界面层由形成在引线框架表面上的氧化亚铜基层和形成在氧化亚铜层上的氧化铜层构成。氧化铜外层有针状结构，可在封装体形成中为与在此处成型的塑料材料的粘结提供互锁机制。

Lead frame and semiconductor device using the lead frame and method of manufacturing the same

提供了用于安装半导体芯片的半导体芯片安装区，通过以相同间隔在半导体芯片安装区的整个周边上配置内引线的末端，可使内引线末端更接近于半导体芯片安装区。沿半导体芯片安装区的整个周边配置内引线的末端，使对应于半导体芯片安装区的角部的内引线的末端处的引线间距比在其他内引线末端的引线间距宽。

Semiconductor device and method for manufacturing thereof

기판 상에 제 1 반도체 칩 및 제 2 반도체 칩을 적층하고, 제 1 본딩 와이어 및 제 2 본딩 와이어에 의해 기판에 각각의 반도체 칩상에 형성한 전극 단자를 전기적으로 접속시킨 반도체 장치로서, 제 2 본딩 와이어와 제 1 반도체 칩 사이에 절연층을 형성시킨 반도체 장치이다. A semiconductor device in which a first semiconductor chip and a second semiconductor chip are laminated on a substrate, and the electrode terminals formed on the respective semiconductor chips are electrically connected to the substrate by the first bonding wire and the second bonding wire. A semiconductor device in which an insulating layer is formed between a wire and a first semiconductor chip.

Electrode connection method and electrode connection structure

Lead frame for semiconductor package

Insulator seal type semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Semiconductor device

Wire bonding method of electric element

개시된 와이어 본딩 방법은, 리드 프레임 상에 탑재된 회로소자의 와이어 본딩 방법으로서, 캐필러리의 가동이 정지된 경우 정지 시간을 카운트하고, 이 정지 시간이 기준 시간을 초과하는 경우에 캐필러리의 단부에 형성된 오염된 프리에어볼을 제거한 후에 와이어 본딩 공정을 재시작한다. The disclosed wire bonding method is a wire bonding method of a circuit element mounted on a lead frame. When the capillary stops moving, the stop time is counted. When the stop time exceeds the reference time, After removing the contaminated pre-air ball formed, the wire bonding process is restarted.

Semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Light-emitting device

실시예는 발광소자패키지에 관한 것이다. 실시예에 따른 발광소자패키지는 제1 리드프레임 상에 위치하고, 상면에 전극패드를 구비하는 발광소자, 상기 제1 리드프레임과 이격되어 위치하는 제2 리드프레임과 상기 전극패드를 전기적으로 연결하는 제1 와이어 및 상기 제2 리드프레임 상에서, 상기 제1 와이어와 상기 제2 리드프레임이 접하는 제1 접점과 이격되어 위치하는 제1 접합볼 을 포함하고, 상기 제1 접합볼은 상기 제1 와이어와 상기 제2 리드프레임 사이에 위치하여, 상기 제1 와이어와 상기 제2 리드프레임을 전기적으로 연결할 수 있다. 실시예에 따른 발광소자패키지는 와이어 본딩시 접합볼을 사용함으로써 와이어를 고정하여 리드프레임의 와이어 접합부가 끊어지는 것을 방지하고, 접합볼을 통하여 와이어가 리드프레임에 전기적으로 연결될 수 있어 와이어 본딩에 관한 신뢰성을 개선시키는 효과를 가진다.

Semiconductor device

Circuit structure

本发明提供一种线路结构，包括接垫组件、连接垫组件以及连接组件。接垫组件包括彼此分离的第一接垫、第二接垫以及第三接垫。连接垫组件位于接垫组件的一侧且包括第一连接垫。连接组件包括第一打线、第二打线以及多个连接件。第一打线连接第一连接垫与第一接垫。第二打线连接第一连接垫与第三接垫。连接件连接于第一接垫、第二接垫及第三接垫之间。本发明的线路结构可提高打线效率及接线点排布密度，且可减少打线的用量。

Moisture-resistant electronic device package and methods of assembly

Various embodiments for moisture-resistant image sensor packaging structures and methods of assembly are disclosed. Image sensor packages of the present invention include an interposer, a housing structure formed on the interposer for surrounding an image sensor chip, and a transparent cover. The housing structure may cover substantially all of the interposer chip surface. In another embodiment, the housing structure also covers substantially all of the interposer edge surfaces. The housing structure may also cover substantially all of the interposer attachment surface. An image sensor chip is electrically connected to the interposer with sealed wire bond connections or with sealed flip-chip connections. The housing structure may include runners that enable simultaneous sealing of the interior of the image sensor package and of the transparent cover.

Semiconductor device

Semiconductor device and manufacturing method thereof

본 발명에 따른 반도체 장치는 반도체 소자 (1) 위에 제공된 복수의 전극 패드, 본딩선 (W) 을 거쳐 전극 패드와 결합된 리드 (L) 및, 복수의 전극 패드간의 공통 신호를 처리하는 전극 패드의 전기적 연속성을 성취하는 반도체 소자 (1) 위에 제공된 공통선 (2a 및 2b) 을 포함한다. 적어도 공통선 (2a 및 2b) 의 표면은 절연 소자, 즉 2차 절연 접착 테이프로 덮인다. 이로써, 본딩선의 루프가 낮아질 수 있으므로, 더 얇은 패키지가 성취된다. The semiconductor device according to the present invention comprises a plurality of electrode pads provided on the semiconductor element 1, leads L bonded to the electrode pads via a bonding line W, and electrode pads for processing common signals between the plurality of electrode pads. Common lines 2a and 2b provided over the semiconductor element 1 to achieve electrical continuity. At least the surfaces of the common lines 2a and 2b are covered with insulating elements, i.e. secondary insulating adhesive tape. In this way, the loop of the bonding line can be lowered, so that a thinner package is achieved.

Method for reducing or eliminating semiconductor device wire sweep and a device produced by the method

本发明提供一种多层线键合半导体器件的封装方法。该方法包括只穿过每层的多个导体中的至少两个导体的一部分施加绝缘材料，其中所述多个导体提供多层线键合半导体器件中的元件之间的互连。该方法还包括封装导体和元件，由此封装半导体器件。

System for fabricating semiconductor components with through wire interconnects

A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer scale components, stacked components, or interconnect components for electrically engaging or testing other semiconductor components.

METHOD OF INSERTING A WIRE INTO A GROOVE OF A SEMICONDUCTOR CHIP, AND EQUIPMENT FOR IMPLEMENTING SUCH A METHOD

L'invention porte sur un procédé d'insertion d'un fil (7a, 7b) dans une rainure longitudinale d'une puce de semi-conducteur (1) en vue de leur assemblage, la rainure contenant un plot (6a, 6b) constitué d'un matériau de liaison présentant une température de fusion déterminée, le procédé comprenant : - dans une étape de mise en place, disposer une section longitudinale du fil (7a, 7b) le long de la rainure, en butée forcée contre le plot (6a, 6b) ; - dans une étape d'insertion, exposer une zone contenant au moins une partie du plot (6a, 6b) à une température de traitement supérieure à la température de fusion du matériau de liaison et pendant une durée suffisante pour faire fondre au moins en partie le plot (6a, 6b), et provoquer l'insertion du fil (7a, 7b) dans la rainure. L'invention porte également sur un équipement permettant de mettre en œuvre le procédé d'insertion. The invention relates to a method for inserting a wire (7a, 7b) into a longitudinal groove of a semiconductor chip (1) for their assembly, the groove containing a pad (6a, 6b) consisting of a bonding material having a determined melting temperature, the method comprising: - in a positioning step, arranging a longitudinal section of the wire (7a, 7b) along the groove, in forced abutment against the stud (6a, 6b); - in an insertion step, exposing an area containing at least part of the pad (6a, 6b) to a treatment temperature above the melting temperature of the bonding material and for a time sufficient to melt at least in part the pad (6a, 6b), and cause the insertion of the wire (7a, 7b) in the groove. The invention also relates to equipment for carrying out the insertion method.

Electronic component built-in substrate and method for manufacturing electronic component built-in substrate

Patent FR2185915B1

1427588 Component assemblies COMMISSARIAT A L'ENERGIE ATOMIQUE 14 May 1973 [25 May 1972] 22893/73 Heading H1R In a method of interconnecting microcomponents which avoids the use of multilayer printed circuit boards, conducting studs 62, Fig. 1, are deposited on a substrate 60; a single length of insulated wire 64 is stuck to the substrate, the wire being bared and welded to studs 62 where required; then excess wire is removed, leaving a number of interconnection circuits between sets of studs 62 to which microcomponent terminals are connected. Fig. 6 depicts a substrate 30 of polyimide with a layer 32 of thermo-adhesive material on one surface thereof. Wire 36 having a thermo-adhesive coating is paid out by a feed head 34 having a heating coil 40 thereon for activating the adhesive. In modifications, a plurality of rectangular insulation frames 2, Fig. 5, are attached to the substrate each having grooves 4 in its upper surface. Bared wire portions 22 are secured in the grooves by copper studs 24 which are built up by electrodeposition. The studs may protrude finger-like into the space within the frame, to be connected flip-chip-wise to a micro-component therein (Figs. 4, 8, not shown); alternatively the studs may end flush with the inner periphery of the frame, connection to a micro-component therein being by way of beam leads (Fig. 7, not shown). The substrate may be mounted on a further, more rigid, support to strengthen the assembly; the further support may also act as a heat dissipator. Reference has been directed by the Comptroller to Specification 1,352,557.

Memory module assembly using partially defective chips

A method of fabricating a memory module according to one embodiment, a clock booster is mounted on a multi-layer circuit bard (101). The clock booster may be any apparatus that receives a clock input, and output one or more clock signals capable of driving a multiplicity of logic parts without clock distortion. In a preferred embodiment, a phase-locked loop circuit may be used as a clock booster. The test and patching (102) allows a fully-functional memory part adds, it is desirable to only connect the clock signal to those memory parts that are utilized. This may be accomplished using any number of switching mechanisms to connect or disconnect a clock signal to a memory part. In a preferred embodiment, a clock patching network may be used to selectively connect or disconnect outputs of a clock booster to the memory parts (103).

METHOD FOR ASSEMBLING AT LEAST ONE CHIP WITH A WIRED ELEMENT, ELECTRONIC CHIP WITH DEFORMABLE BONDING ELEMENT, METHOD FOR MANUFACTURING A PLURALITY OF CHIPS, AND ASSEMBLY OF AT LEAST ONE CHIP WITH A WIRED ELEMENT

METHOD FOR ASSEMBLING AT LEAST ONE CHIP WITH A WIRED ELEMENT, ELECTRONIC CHIP WITH DEFORMABLE BONDING ELEMENT, METHOD FOR MANUFACTURING A PLURALITY OF CHIPS, AND ASSEMBLY OF AT LEAST ONE CHIP WITH A WIRED ELEMENT

Le procédé d'assemblage d'un élément filaire avec une puce électronique comporte dans une première étape la disposition de l'élément filaire dans une rainure de la puce délimitée par un premier élément (8) et un deuxième élément (8'), reliés par un élément de liaison (6) comprenant un matériau plastiquement déformable, puis dans une deuxième étape le serrage des premier et deuxième éléments (8, 8') pour déformer l'élément de liaison (6) jusqu'à la fixation de l'élément filaire dans la rainure. The method of assembling a wire element with an electronic chip comprises in a first step the arrangement of the wire element in a groove of the chip delimited by a first element (8) and a second element (8 '), connected by a connecting element (6) comprising a plastically deformable material, then in a second step the clamping of the first and second elements (8, 8 ') to deform the connecting element (6) until the attachment of the wire element in the groove.

FUNCTIONAL CHIP ADAPTED TO BE ASSEMBLED WITH WIRED ELEMENTS, AND METHOD FOR MANUFACTURING SUCH A CHIP

L’invention concerne une puce fonctionnelle (100) dont au moins deux plots de connexion électrique (11a,11b) sont destinés à être reliés à des éléments filaires (40a,40b). Ladite puce comprend : - un support (10) comprenant un composant microélectronique électriquement relié aux deux plots de connexion électrique disposés sur une face avant dudit support (10),- un capot (20) comportant une première portion (21) assemblée à la face avant du support (10), ladite première portion (21) formant une entretoise entre les deux plots de connexion électrique ; le capot (20) comportant en outre une deuxième portion (22) à distance de la face avant du support (10) et s’étendant en vis-à-vis de chaque plot de connexion électrique uniquement partiellement, de manière à autoriser un accès auxdits plots, selon un axe (z) normal à la face avant du support (10). L’invention concerne également un procédé de fabrication d’une telle puce fonctionnelle. Figure à publier avec l’abrégé : F igure 2

METHOD OF MUTUAL CONNECTING OF ELECTRONIC MICRO COMPONENTS AND CONNECTING SUBSTRATES AND HYBRID CIRCUITS MANUFACTURED BY SUCH A PROCESS

Multi-layer tab tape having distinct signal, power and ground planes, semiconductor device assembly employing same, apparatus for and method of assembling same

Separate and distinct conductive layers for power and ground are insulated from one another and a patterned signal conductive layer to form a flexible substrate for mounting a semiconductor die in a semiconductor device assembly. TAB technology is utilized to produce an assembly that has superior electrical characteristics because power and ground is conducted on separate low impedance conductive layers. The power and ground leads connecting the semiconductor die and external circuits are selected from the signal trace layer, cut bent downward and attached by bonding to the respective power or ground layer. A tool is disclosed for cutting the selected leads. A method of attaching solder balls to a TBGA film using solder flux and photoimageable solder resist definition is also disclosed.

Semiconductor device and method for manufacturing the same

本发明的半导体装置具备形成于基板(1、12)的表面的衬垫(3)、将衬垫(3)与外部的电路连接的接合线(5)以及树脂层(6)，所述树脂层(6)至少将衬垫(3)与接合线(5)的连接部覆盖并且使基板中的衬垫(3)的外侧的部分的至少一部分露出。

SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND POWER CONVERSION DEVICE

【課題】パワー半導体装置において、樹脂によるワイヤ接合部の被覆を、高い信頼性で、かつ容易に実現できるようにする。【解決手段】ワイヤ（１３）が接続される表面電極（３１）を形成した半導体チップ（１２）と、ワイヤ（１３）と表面電極（３１）との接合部を被覆する第１の樹脂膜（４０）と、該表面電極の形成面の周縁部を被覆し、第１の樹脂膜に接するとともに第１の樹脂膜よりも膜厚の厚い第２の樹脂膜（３４）と、半導体チップ、第１の樹脂膜および第２の樹脂膜を覆うゲル状封止材（３６）とを設けた。 In a power semiconductor device, coating of a wire bonding portion with a resin can be easily realized with high reliability. A semiconductor chip (12) on which a surface electrode (31) to which a wire (13) is connected is formed, and a first resin film (1) covering a joint portion between the wire (13) and the surface electrode (31). 40), a second resin film (34) that covers the peripheral edge of the surface electrode formation surface, is in contact with the first resin film and is thicker than the first resin film, and the semiconductor chip, The gel sealing material (36) which covers 1 resin film and 2nd resin film was provided.

Flip chip double die package

A flip chip double die package is provided to minimize the malfunction due to noises by forming power/ground pads on a center portion and an edge portion of a chip. A board(20) includes a circuit pattern with bond fingers(21a,21b,21c) at an upper surface and ball lands(22) at a lower surface. A first semiconductor chip(24) is attached on the board by using a face-down type method. A plurality of first bonding pads(25) are formed at first center and edge portions of the first semiconductor chip. A first bump(26) is interposed between the first bonding pads of the first semiconductor chip and the bond fingers of the board to connect electrically physically the first semiconductor chip and the board. A pattern tape(29) with bump pads is attached on the first semiconductor chip. A second semiconductor chip(32) is attached to the pattern tape by using the face-down type manner. The second semiconductor chip includes second bonding pads at second center and edge portions. A second bump(34) is interposed between the second bonding pads of the second semiconductor chip and bump pads of the pattern tape to connect electrically physically the second semiconductor chip with the pattern tape. A bonding wire(35) is used for connecting electrically the bump pads of the pattern tape with the bond fingers of the board. Solder balls(38) are attached to the ball lands of the substrate.

Light emitting device package

本发明公开了一种发光器件封装，其包括：封装体，包括布置在所述封装体的表面上的至少一个电极垫；发光器件，布置在所述封装体上，所述发光器件经由引线而被电连接至所述电极垫；以及通孔电极，穿过所述封装体，其中，所述引线在所述发光器件和所述电极垫的至少一个上形成针脚，所述发光器件封装还包括布置在所述针脚上的焊球，且通孔电极在垂直方向上不与针脚和焊球重叠。

Stacked chip packaging structure

A stacked chip packaging structure ( 10 ) includes a substrate ( 20 ), a first chip ( 40 ), a second chip ( 70 ), and a cover ( 80 ). The first chip is mounted on the substrate and is electrically connected with the substrate via a first plurality of wires ( 50 a ). The second chip is mounted above the first chip and above the wires connected with the first chip and is electrically connected with the substrate via a second plurality of wires ( 50 b ). The cover is mounted above the second chip and the wires connected with the second chip. The mounting of the second chip and the cover in such a manner is facilitated through the use of an adhesive/glue ( 60 a, 60 b ) that is able to function both as an adherent and as a spacer.

Semiconductor device

본 발명은, 본딩 패드에서 발생하는 응력에 대한 강도를 향상시키는 것이 가능한 반도체장치를 제공하는 것을 목적으로 한다. 본 발명에 따른 반도체장치에 있어서는, 반도체칩 위에 본딩 패드(1)가 여러 개 설치된다. 각각의 본딩 패드(1)에 있어서는, 최상층의 배선층을 사용하여 형성된 제1메탈(11) 아래에, 라인 형상의 제2메탈(12)이 여러 개 설치된다. 그리고, 상기 목적을 달성하기 위하여, 본딩 패드(1)는, 제2메탈(12)의 길이 방향으로 나란히 설치된다. 즉, 제2메탈(2)의 길이 방향(L1)과, 본딩 패드(1)의 배열 방향(L2)이 같은 방향이 되도록, 본딩 패드(1)를 나란히 배치한다. 본딩 패드, 응력, 반도체칩, 메탈, 길이 방향, 배열 방향

Thermal-stress-resistant semiconductor sensor

A semiconductor sensor is provided with a good temperature characteristic, the sensor being capable of preventing a pressure or acceleration detection characteristic from being affected by a change of the surrounding temperature. A semiconductor chip is provided approximately in the center of a die pad of a lead frame and detects a displacement amount corresponding to a pressure or an acceleration. The displacement amount is converted into an electric signal and output. A resin mold is formed so as to cover the semiconductor chip. A thermal-stress-relieving buffer ring is provided on the die pad so as to surround an external circumference of the semiconductor sensor chip thereby preventing stress caused by thermal expansion/contraction of the resin mold from being directly applied to the semiconductor chip from the side.

Method for low loop wire bonding

A method is provided for low loop wire bonding. The method includes forming a first bond between a first bonding ball disposed at an end of a first wire and a bond pad of a die coupled to a leadframe having one or more leads. The method also includes forming a second bond between a portion of the wire and a lead of the leadframe. The length of wire between the first and second bonds forms a loop in the wire having a first loop height. The method further includes disposing a second bonding ball on top of the first bonding ball, a portion of the loop being compressed between the first and second bonding balls. The compressed loop has a second loop height less than the first loop height. The method also includes forming a third bond between the second bonding ball, the wire, and the first bonding ball.

Semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Semiconductor device and manufacturing method for the same

A semiconductor device and a manufacturing method of the same are provided to reduce a size thereof and to enhance performance thereof by increasing density of wires. A first electrode(21) is arranged on a surface of a substrate(10). A second electrode(22) is installed on a surface of a first semiconductor element(11A). The first semiconductor element is supported by the substrate. A first wire(41) is connected through a first bump to at least one electrode which is installed on one of the substrate and the first semiconductor element. A second wire(42) is connected through a second bump(32) to a connecting target part of the first wire. The first wire and the second wire are bonded with the first bump and the second bump, respectively by using a stitch bonding method.

Semiconductor device

본 발명은 반도체 다이를 가로질러서 형성된 쉴딩 와이어와 상기 쉴딩 와이어를 지지하는 보조 와이어를 구비하여, 반도체 다이에서 발생되는 전자파를 차폐하는 동시에 패키지의 크기를 줄일 수 있는 반도체 디바이스에 관한 것이다. 일례로, 적어도 하나의 회로 소자가 안착된 회로 기판; 상기 회로 소자와 이격되어 상기 회로 기판에 안착된 반도체 다이; 상기 반도체 다이와 이격되며, 상기 반도체 다이를 가로질러서 형성된 쉴딩 와이어; 및 상기 쉴딩 와이어의 하부에서 상기 쉴딩 와이어를 지지하며, 상기 쉴딩 와이어와 수직한 방향으로 형성된 보조 와이어를 포함하는 것을 특징으로 하는 반도체 디바이스를 개시한다. The present invention relates to a semiconductor device having a shielding wire formed across a semiconductor die and an auxiliary wire for supporting the shielding wire so as to shield the electromagnetic wave generated in the semiconductor die and reduce the size of the package. For example, a circuit board on which at least one circuit element is mounted; A semiconductor die spaced apart from the circuit element and seated on the circuit board; A shielding wire spaced apart from the semiconductor die and formed across the semiconductor die; And an auxiliary wire supporting the shielding wire at a lower portion of the shielding wire and formed in a direction perpendicular to the shielding wire.

Semiconductor device and method for manufacturing same

제1반도체 칩(21)은 칩 탑재 부재(11) 위에 배열 설치되고, 제1반도체 칩(21)의 전극 패드(21e)에 접속되는 본딩 와이어(36)는, 제1절연성 접착제(31)에 피복되어 고정되어 있다. 제2반도체 칩(22)은, 제1절연성 접착제(31)를 통하여 제1반도체 칩(21) 위에 적층 배치되는 것을 특징으로 하는 반도체 장치. 이것에 의해, 칩을 적층 실장할 때에, 기판 바로 위 칩의 본딩 와이어가 단선이나 단락되는 불량을 방지할 수 있다. The first semiconductor chip 21 is arranged on the chip mounting member 11, and the bonding wire 36 connected to the electrode pad 21e of the first semiconductor chip 21 is attached to the first insulating adhesive 31. It is covered and fixed. The second semiconductor chip (22) is laminated on the first semiconductor chip (21) via a first insulating adhesive (31). As a result, when the chips are stacked and mounted, a defect in which the bonding wires of the chips immediately above the substrate are disconnected or shorted can be prevented. 반도체 칩, 본딩 와이어, 리드 프레임, 절연성 접착제, 전극 패드 Semiconductor chip, bonding wire, lead frame, insulating adhesive, electrode pad

Semiconductor integrated circuit

Structure and method of wire bonding

(57)【要約】 【目的】 半導体装置において、フレーム側に第１ボ ンディング、半導体チップ側に第２ボンディングを採用 したワイヤボンディング構造に関し生産性、信頼性の高 いワイヤボンディング構造及びワイヤボンディング方法 を提供する。 【構成】 半導体チップ上のボンディングパッドにワ イヤの先端に形成した溶融ボールを圧着したのち、ひき ちぎりによってワイヤパンプを形成し、当該パンプを第 ２ボンディング部、フレーム上の電極を第１ボンディン グ部としてワイヤボンディングしたワイヤボンディング 構造。

SEMICONDUCTOR DEVICE HAVING A METALLIC PATTERN.

Un dispositif à semiconducteurs pour un amplificateur de sortie de forte puissance comporte un substrat (4) ayant une épaisseur réduite, et une électrode faisant fonction de radiateur thermique, formée sur la surface arrière du substrat. Le dispositif comprend un motif métallisé (13) qui est formé au moyen d'une couche de revêtement de métal entourant la périphérie de l'élément, la surface latérale de l'élément et l'électrode faisant fonction de radiateur thermique, sauf au voisinage de parties d'entrée/sortie de haute fréquence (8, 9). Cette structure permet d'empêcher un endommagement du dispositif sous l'effet de petites fissures et d'un ébrèchement se produisant au moment de l'opération de fixation de puce. De plus, on peut éviter que la matière de brasage tendre qui monte sur la surface de l'élément ne soit connectée à la pellicule de métal. A semiconductor device for a high power output amplifier comprises a substrate (4) having a reduced thickness, and an electrode acting as a heat sink, formed on the rear surface of the substrate. The device comprises a metallized pattern (13) which is formed by means of a metal coating layer surrounding the periphery of the element, the lateral surface of the element and the electrode acting as a heat radiator, except in the vicinity high frequency input / output parts (8, 9). This structure makes it possible to prevent damage to the device under the effect of small cracks and chipping occurring at the time of the chip fixing operation. In addition, it is possible to prevent the soft soldering material which rises on the surface of the element from being connected to the metal film.