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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 1153. Отображено 100.
26-09-2013 дата публикации

Magnet Assisted Alignment Method for Wafer Bonding and Wafer Level Chip Scale Packaging

Номер: US20130252375A1
Автор: Ge Yi, Shaoping Li, YunJun Tang, Zongrong Liu
Принадлежит: Individual

A high-precision alignment method with high throughput is proposed, which can be used for wafer-to-wafer, chip-to-wafer or chip-to-chip bonding. The scheme implements pairing patterned magnets predetermined designed and made using wafer level process on two components (wafer or chip). The magnetization in patterned magnet can be set at predetermined configuration before bonding starts. When, the two components are bought to close proximity after a coarse alignment, the magnetic force will bring the magnet pairs together and aligned the patterned magnet on one component with its mirrored or complimentary patterned magnets on the other component to minimize the overall the magnetic energy of the pairing magnet. A few patterned magnet structures and materials, with their unique merits are proposed as examples for magnet pair for the self-alignment purpose. This method enables solid contact at the bonding interface via patterned magnets under the magnetic force, which avoid the wafer drafting due to the formation of the liquid phases.

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Номер записи: 1
03-10-2013 дата публикации

Bonded processed semiconductor structures and carriers

Номер: US20130256907A1
Автор: Ionut Radu, Mariam Sadaka
Принадлежит: Soitec SA

Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.

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Номер записи: 2
07-01-2021 дата публикации

Semiconductor Device and Method of Manufacturing

Номер: US20210005561A1
Автор: Chen Ming-Fa, Hu Chih-Chia, Jan Sen-Bor, Yeh Sung-Feng, Yuan Ching-Pin
Принадлежит:

A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads. 1. A semiconductor device , comprising: a first passivation layer disposed over a first substrate; and', 'first bond pads disposed in the first passivation layer; and, 'a first die, comprising a second passivation layer, the second passivation layer being bonded to the first passivation layer; and', 'second bond pads disposed in the second passivation layer, each of the second bond pads being bonded to one of the first bond pads, the second bond pads comprising inner bond pads and outer bond pads, the outer bond pads having a greater diameter than the inner bond pads., 'a second die, comprising2. The semiconductor device of further comprising third bond pads disposed in the second passivation layer claim 1 , wherein the third bond pads are closer than the outer bond pads to an outer edge of the second passivation layer claim 1 , and wherein the third bond pads have a greater diameter than the outer bond pads.3. The semiconductor device of claim 1 , wherein:a center of one of the first bond pads is located a first distance from a center of the first passivation layer, the one of the first bond pads having a first diameter;a center of one of the second bond pads is located a second distance from a center of the second passivation layer, the one of the second bond pads being bonded to the one of the first bond pads, the one of the second bond pads having a second diameter; andthe second distance being ...

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Номер записи: 3
02-01-2020 дата публикации

Semiconductor Device Package and Method

Номер: US20200006164A1
Автор: Chen-Hua Yu, Ching-Pin Yuan, Hsien-Wei Chen, Hui-Wen Liu, Ming-Fa Chen, Sung-Feng Yeh
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.

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Номер записи: 4
02-01-2020 дата публикации

Semiconductor Interconnect Structure and Method

Номер: US20200006266A1
Автор: Chen Hsien-Wei, Chen Jie
Принадлежит:

A semiconductor device includes a first interconnect structure over first substrate, a first bonding layer over the first interconnect structure, multiple first bonding pads disposed in a first region of the first bonding layer, the first bonding pads having a first pitch, and multiple second bonding pads disposed in a second region of the first bonding layer, the second region extending between a first edge of the first bonding layer and the first region, the second bonding pads having the first pitch, the multiple second bonding pads including multiple pairs of adjacent second bonding pads, wherein the second bonding pads of each respective pair are connected by a first metal line. 1. A semiconductor device comprising:a first interconnect structure over first substrate;a first bonding layer over the first interconnect structure;a plurality of first bonding pads disposed in a first region of the first bonding layer, the first bonding pads having a first pitch; anda plurality of second bonding pads disposed in a second region of the first bonding layer, the second region extending between a first edge of the first bonding layer and the first region, the second bonding pads having the first pitch, the plurality of second bonding pads comprising a plurality of pairs of adjacent second bonding pads, wherein the second bonding pads of each respective pair are connected by a first metal line.2. The semiconductor device of claim 1 , wherein the first metal lines are disposed in the same layer as the second bonding pads.3. The semiconductor device of claim 1 , wherein the first metal lines are disposed in the interconnect structure and connected to the second bonding pads of each respective pair by vias disposed in the bonding layer.4. The semiconductor device of claim 1 , comprising:a second bonding layer over a second substrate; anda plurality of third bonding pads disposed in the second bonding layer, comprising a plurality of pairs of adjacent third bonding pads, ...

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Номер записи: 5
02-01-2020 дата публикации

Methods and devices for fabricating and assembling printable semiconductor elements

Номер: US20200006540A1
Автор: Dahl-Young Khang, Etienne Menard, John A. Rogers, Keon Jae Lee, Matthew Meitl, Ralph G. Nuzzo, Yugang Sun, Zhengtao Zhu
Принадлежит: University of Illinois

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

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Номер записи: 6
11-01-2018 дата публикации

Chip-On-Wafer Package and Method of Forming Same

Номер: US20180012862A1
Автор: Chen Ming-Fa, Yeh Sung-Feng, Yu Chen-Hua
Принадлежит:

A method includes bonding a die to a substrate, where the substrate has a first redistribution structure, the die has a second redistribution structure, and the first redistribution structure is bonded to the second redistribution structure. A first isolation material is formed over the substrate and around the die. A first conductive via is formed, extending from a first surface of the substrate, where the first surface is opposite the second redistribution structure, the first conductive via contacting a first conductive element in the second redistribution structure. Forming the first conductive via includes patterning an opening in the substrate, extending the opening to expose the first conductive element, where extending the opening includes using a portion of a second conductive element in the first redistribution structure as an etch mask, and filling the opening with a conductive material. 1. A method comprising:bonding a die to a substrate, the substrate having a first redistribution structure disposed at a first surface of the substrate, the die having a second redistribution structure, the first redistribution structure being bonded to the second redistribution structure;forming a first isolation material over the substrate and around the die;patterning an opening in a second surface of the substrate, the second surface being opposite the substrate from the first surface;extending the opening to expose a first conductive element in the second redistribution structure, wherein extending the opening comprises using a second conductive element in the first redistribution structure as an etch mask; andfilling the opening with a conductive material, the conductive material contacting the first conductive element.2. The method of claim 1 , further comprising:after extending the opening, forming an isolation layer in the opening; andetching the isolation layer to form sidewall spacers on sidewalls of the opening.3. The method of claim 2 , wherein the sidewall ...

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Номер записи: 7
14-01-2021 дата публикации

METHOD OF TRANSFERRING MICRO DEVICE

Номер: US20210013172A1
Автор: CHEN Li-Yi
Принадлежит:

A method of transferring a micro device is provided. The method includes: aligning a transfer plate with the micro device thereon with a receiving substrate having a contact pad thereon such that the micro device is above or in contact with the contact pad; moving a combination of the transfer plate with the micro device thereon and the receiving substrate into a confined space with a relative humidity greater than or equal to about 85% so as to condense some water between the micro device and the contact pad; and attaching the micro device to the contact pad. 1. A method of transferring a micro device , comprising:aligning a transfer plate with the micro device thereon with a receiving substrate having a contact pad thereon such that the micro device is above or in contact with the contact pad;moving a combination of the transfer plate with the micro device thereon and the receiving substrate into a confined space with a relative humidity greater than or equal to about 85% so as to condense some water between the micro device and the contact pad; andattaching the micro device to the contact pad.2. The method of claim 1 , wherein attaching the micro device to the contact pad comprises:moving the combination out of the confined space to an environment with a relative humidity smaller than about 80% such that the water is evaporated and the micro device is stuck to and in contact with the contact pad.3. The method of claim 2 , wherein attaching the micro device to the contact pad further comprises:applying an external pressure to press the micro device and the contact pad during evaporating the water.4. The method of claim 1 , wherein attaching the micro device to the contact pad comprises:increasing a temperature within the confined space such that the water is evaporated and the micro device is stuck to and in contact with the contact pad.5. The method of claim 4 , wherein the temperature within the confined space is increased to a temperature point such that the ...

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Номер записи: 8
17-01-2019 дата публикации

INPUT/OUTPUT CELL WIRE CONNECTOR

Номер: US20190019747A1
Автор: Mehetre Shrikrishna Nana, PAWASKAR Pritesh, Smooha Yehuda
Принадлежит:

An input/output (I/O) circuit includes at least one I/O cell having a first size, and a high current circuit coupled to the at least one I/O cell. The high current circuit has a second size that is smaller than the first size. A connection bus is coupled to the high current circuit. The connection bus has the second size and is positioned in substantially a same location within the I/O circuit as the high current circuit. A bump or a bond pad is coupled to the connection bus. 1. An input/output (I/O) circuit , comprising:at least one I/O cell having a first size;a high current circuit coupled to the at least one I/O cell, the high current circuit having a second size that is smaller than the first size;a connection bus coupled to the high current circuit, the connection bus having the second size and positioned in substantially a same location within the I/O circuit as the high current circuit; anda bump or bond pad coupled to the connection bus.2. The I/O circuit of claim 1 , wherein the second size is chosen to accommodate connection of a high current area.3. The I/O circuit of claim 1 , wherein the connection bus couples the bump or bond pad to lower level lines.4. The I/O circuit of claim 1 , wherein the connection bus comprises vias between upper and lower level lines.5. The I/O circuit of claim 1 , wherein the high current circuit is an electrostatic discharge (ESD) protection circuit.6. A solid state drive including the input/output circuit of .7. A hard disc drive including the input/output circuit of .8. An input/output (I/O) circuit claim 1 , comprising:at least one power bus having a first size;at least one ground bus having the first size;an electrostatic discharge (ESD) protection circuit coupled to the at least one power bus or the at least one ground bus, the ESD protection circuit having a second size that is smaller than the first size;a connection bus coupled to the ESD protection circuit, the connection bus having the second size and positioned in ...

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Номер записи: 9
16-01-2020 дата публикации

METHOD FOR SELF-ASSEMBLING MICROELECTRONIC COMPONENTS

Номер: US20200020665A1
Автор: Di Cioccio Lea
Принадлежит: Commissariat A L'Energie Atomique Et Aux Energies Alternatives

A method for self-assembling microelectronic components includes providing a self-aligning substrate having protrusions, each having a thickness greater than 1 μm and an upper face and flanks, the upper face and the flanks being hydrophobic. The method also includes providing dies, each die having a first face and a second hydrophilic face, and providing a self-assembling substrate. Finally, the method includes obtaining, by capillary effect, the self-alignment of each die through the first face thereof on a protrusion of the self-aligning substrate, then obtaining the assembly of the dies through the second hydrophilic face thereof on the self-assembling substrate by direct adhesion. Such a method has application in the industrial production of 3D integrated circuits. 1. A method for self-assembling microelectronic components comprising:providing a self-aligning substrate comprising a plurality of protrusions each having a thickness greater than 1 μm and each having an upper face and flanks, the upper face and the flanks being hydrophobic,providing a plurality of dies, each die having a first face and a second hydrophilic face,providing a self-assembling substrate,obtaining, by capillary effect, a self-alignment of each die, through the first face thereof, on one single protrusion of the self-aligning substrate, thenobtaining an assembly of the plurality of dies on the self-assembling substrate, by direct adhesion on the self-assembling substrate of the second hydrophilic face of each die.2. The method according to claim 1 , wherein the self-assembling substrate has a plurality of hydrophilic receiving zones and wherein obtaining the assembly of the plurality of dies on the self-assembling substrate comprises at least an alignment of the self-aligning substrate and of the self-assembling substrate claim 1 , such that each die is located opposite a hydrophilic receiving zone of the self-assembling substrate and is transferred by direct adhesion on the hydrophilic ...

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Номер записи: 10
10-02-2022 дата публикации

BONDING APPARATUS AND BONDING METHOD

Номер: US20220045030A1
Автор: MOON Gil Yong
Принадлежит: SEMES CO., LTD.

A bonding apparatus includes a stage on which a substrate is seated, a gantry installed above the stage, a bonding unit configured to bond a chip to the substrate while moving along the gantry, and a control part moving the bonding unit to align the bonding unit with a bonding position on the substrate, controlling the bonding unit to allow the bonding unit to bond the chip at the bonding position, determining a movement distance of the bonding unit based on a weighted sum of a number of continuous operations and an idle time of the bonding unit. 1. A bonding apparatus comprising:a stage on which a substrate is seated;a gantry installed above the stage;a bonding unit configured to bond a chip to the substrate while moving along the gantry; anda control part configured to move the bonding unit to align the bonding unit with a bonding position on the substrate, the control part being configured to control the bonding unit to allow the bonding unit to bond the chip at the bonding position,wherein the control part is configured to determine a movement distance of the bonding unit based on a weighted sum of a number of continuous operations and an idle time of the bonding unit.2. The bonding apparatus of claim 1 ,wherein the control part determines the movement distance of the bonding unit using a linear regression equation in which an offset value is added to the weighted sum of the number of continuous operations of the bonding unit and the idle time of the bonding unit.3. The bonding apparatus of claim 2 ,wherein the control part corrects a first weight applied to the number of continuous operations and corrects a second weight applied to the idle time based on a result of a bonding inspection on the chip on the substrate.4. The bonding apparatus of claim 3 ,wherein the control part corrects the first weight and the second weight when a range of change in bonding error according to a result of a post-bonding inspection is within a reference range.5. The bonding ...

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Номер записи: 11
24-01-2019 дата публикации

SUBSTRATE BONDING APPARATUS AND SUBSTRATE BONDING METHOD

Номер: US20190027462A1
Автор: FUKUDA MINORU, Sugaya Isao
Принадлежит: NIKON CORPORATION

A substrate bonding apparatus that brings a part of a surface of a first substrate and a part of a surface of a second substrate into contact in a state where a temperature difference is generated therebetween, to form contact regions at the parts, and then enlarges the contact regions to bond the first substrate and the second substrate, wherein enlargement of the contact regions starts before positional misalignment between the first substrate and the second substrate exceeds a threshold, and the threshold is set such that positional misalignment after the first substrate and the second substrate are bonded does not exceed a tolerated value. 1. A substrate bonding apparatus that brings a part of a surface of a first substrate and a part of a surface of a second substrate into contact in a state where a temperature difference is generated therebetween , to form contact regions at the parts , and then enlarges the contact regions to bond the first substrate and the second substrate , whereinenlargement of the contact regions starts before positional misalignment between the first substrate and the second substrate exceeds a threshold, andthe threshold is set such that positional misalignment after the first substrate and the second substrate are bonded does not exceed a tolerated value.2. The substrate bonding apparatus according to claim 1 , wherein enlargement of the contact regions starts before a temperature difference between non-contact regions of the respective surfaces of the first substrate and the second substrate that are yet to contact becomes a temperature difference out of a predetermined range.3. The substrate bonding apparatus according to claim 1 , wherein enlargement of the contact regions starts after the first substrate and the second substrate are coupled to each other at a predetermined coupling force in the contact regions formed at the parts.4. The substrate bonding apparatus according to claim 3 , comprising:a judging unit that judges ...

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Номер записи: 12
23-01-2020 дата публикации

HYBRID BONDING WITH THROUGH SUBSTRATE VIA (TSV)

Номер: US20200027868A1
Автор: Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor device structure is provided. The semiconductor device structure includes a first polymer layer formed between a first substrate and a second substrate, and a first conductive layer formed over the first polymer. The semiconductor device includes a first through substrate via (TSV) formed over the first conductive layer, and the conductive layer is in direct contact with the first TSV and the first polymer. 1. A semiconductor device structure , comprising:a first polymer layer formed between a first substrate and a second substrate;a first conductive layer formed over the first polymer; anda first through substrate via (TSV) formed over the first conductive layer, wherein the conductive layer is in direct contact with the first TSV and the first polymer.2. The semiconductor device structure as claimed in claim 1 , further comprising:an interconnect structure formed over the first substrate, wherein the interconnect structure is in direct contact with the first TSV.3. The semiconductor device structure as claimed in claim 1 , further comprising:a first transistor formed in the first substrate; anda first contact plug formed below the first transistor, wherein a bottom surface of the first contact plug is level with a bottom surface of the first TSV.4. The semiconductor device structure as claimed in claim 3 , wherein a sidewall of the first contact plug is aligned with a sidewall of the first conductive layer.5. The semiconductor device structure as claimed in claim 1 , further comprising:a second TSV formed in the second substrate, wherein a first width of the first TSV is smaller than a second width of the second TSV.6. The semiconductor device structure as claimed in claim 5 , further comprising:a second polymer layer formed between the first substrate and the second substrate; anda second conductive layer formed below the second polymer layer, wherein the second conductive layer is in direct contact with the second polymer layer and the second TSV ...

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Номер записи: 13
30-01-2020 дата публикации

POST CMP PROCESSING FOR HYBRID BONDING

Номер: US20200035641A1
Автор: FOUNTAIN, Gao Guilian, JR. Gaius Gillman, MANDALAPU Chandrasekhar
Принадлежит:

Devices and techniques include process steps for forming openings through stacked and bonded structures. The openings are formed by pre-etching through one or more layers of prepared dies after planarization of the bonding layer (by chemical-mechanical polishing (CMP) or the like) and prior to bonding. For instance, the openings are etched through one or more layers of dies to be bonded prior to bonding the dies to form an assembly. 1. A microelectronic assembly , comprising:a first substrate having a bonding surface, the bonding surface of the first substrate having a planarized topography;a first plurality of electrically conductive features at the bonding surface of the first substrate;a second substrate having a bonding surface, the bonding surface of the second substrate having a planarized topography and bonded to the bonding surface of the first substrate;a second plurality of electrically conductive features at the bonding surface of the second substrate and bonded to the first plurality of electrically conductive features; andone or more electrically conductive contact pads disposed within an insulating layer of the second substrate and below the bonding surface of the second substrate, the one or more electrically conductive contact pads disposed in an area different from the first plurality of electrically conductive features and the second plurality of electrically conductive features.2. The microelectronic assembly of claim 1 , further comprising one or more secondary openings in the insulating layer of the second substrate aligned to the one or more electrically conductive contact pads claim 1 , the one or more secondary openings extending from the bonding surface of the second substrate to the one or more electrically conductive contact pads claim 1 , providing access to the one or more electrically conductive contact pads.3. The microelectronic assembly of claim 2 , further comprising one or more primary openings in an insulating layer of the first ...

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Номер записи: 14
04-02-2021 дата публикации

METHOD FOR MANUFACTURING AN ELECTRONIC CIRCUIT COMPONENT AND ELECTRONIC CIRCUIT COMPONENT

Номер: US20210035943A1
Автор: RAMM Peter
Принадлежит:

A method for manufacturing an electronic circuit component includes: providing a first electronic component with one or several electrically conductive first contacts and with one or several insulating first supporting elements; providing a second electronic component with one or several electrically conductive second contacts and with one or several insulating second supporting elements; configuring a connecting structure with an interposer substrate, with electrically conductive third contacts, with one or several electrically conductive fourth contacts, with one or several insulating third supporting elements, with one or several electrically conductive fifth contacts, and with one or several insulating fourth supporting elements; connecting the first electronic component and the second electronic component to the connecting structure, wherein the first contacts are electrically connected to the fourth contacts, wherein the first supporting elements are mechanically connected to the third supporting elements, wherein the second contacts are electrically connected to the fifth contacts, and wherein the second supporting elements are mechanically connected to the fourth supporting elements, so that the first electronic component, the second electronic component, and the connecting structure are connected electrically and mechanically; removing a part of the interposer substrate so that the third contacts are exposed. 1. Method for manufacturing an electronic circuit component , comprising:providing a first electronic component, wherein one or several first electronic component structures are configured on a first semiconductor substrate, wherein a first rewiring device is configured on a side of the first electronic component structures facing away from the first semiconductor substrate, and wherein one or several electrically conductive first contacts that are electrically connected to the first rewiring device, and one or several insulating first supporting ...

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Номер записи: 15
04-02-2021 дата публикации

LIGHT EMITTING ELEMENT AND DISPLAY DEVICE INCLUDING THE SAME AND METHOD FOR MANUFACTURING DISPLAY DEVICE

Номер: US20210035962A1
Автор: DOH Hyunmi, HA Jaekook, JUNG Yunku, KIM Jaehoon, KIM Sungwoon, KO Yunhyuk, LEE Changhee, Nam Minki, Park Jae Hong, PARK Junwoo, PARK Myoungjin
Принадлежит:

Provided is a light emitting element according to embodiments which includes a body including a semiconductor layer and an active layer, and a ligand including a head portion bonded to a surface of the body, an end portion spaced apart from the body, and having a positive or a negative charge, and a chain portion connecting the head portion and the end portion. 1. A light emitting element comprising:a body comprising a semiconductor layer and an active layer; and a head portion bonded to a surface of the body;', 'an end portion spaced apart from the body, and having a positive or a negative charge; and', 'a chain portion connecting the head portion and the end portion., 'a ligand comprising2. The light emitting element of claim 1 , wherein the semiconductor layer comprises a first semiconductor layer claim 1 , and a second semiconductor layer spaced apart from the first semiconductor with the active layer therebetween.3. The light emitting element of claim 2 , wherein the body further comprises:a first contact electrode adjacent to the first semiconductor layer; anda second contact electrode adjacent to the second semiconductor layer.4. The light emitting element of claim 1 , wherein the body further comprises an insulating film covering a side surface of the semiconductor layer and the active layer claim 1 , and comprising a metal oxide.5. The light emitting element of claim 4 , wherein the ligand is bonded to the insulating film.6. The light emitting element of claim 1 , wherein the ligand comprises a first ligand comprising a first end portion having a positive charge claim 1 , and a second ligand comprising a second end portion having a negative charge.7. The light emitting element of claim 6 , wherein the body comprises:a first side surface to which the first ligand is bonded; anda second side surface facing the first side surface, and to which the second ligand is bonded.8. The light emitting element of claim 1 , wherein the head portion comprises at least one ...

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Номер записи: 16
11-02-2016 дата публикации

Semiconductor Device and Method of Forming Double-Sided Fan-Out Wafer Level Package

Номер: US20160043047A1
Автор: Caparas Jose A., Choi Won Kyoung, Goh Sze Ping, Marimuthu Pandi C., Shim Il Kwon
Принадлежит: STATS CHIPPAC, LTD.

A semiconductor device comprises a first semiconductor package including a conductive layer. A substrate including an interconnect structure is disposed over the conductive layer. The interconnect structure of the substrate with the conductive layer of the first semiconductor package are self-aligned. A plurality of openings is formed in the substrate. An adhesive is disposed between the substrate and the first semiconductor package and in the openings of the substrate. A redistribution layer (RDL) is formed over the first semiconductor package opposite the substrate. A pitch of the substrate is different from a pitch of the RDL. The adhesive extends to the interconnect structure of the substrate. A second semiconductor package is disposed over the substrate and the first semiconductor package. 1. A method of making a semiconductor device , comprising:providing a semiconductor package including a conductive layer;providing a substrate including an interconnect structure;disposing the substrate over the semiconductor package;bonding the interconnect structure of the substrate with the conductive layer of the semiconductor package; anddisposing an adhesive through an opening in the substrate and between the substrate and the semiconductor package after bonding the interconnect structure of the substrate with the conductive layer of the semiconductor package.2. The method of claim 1 , further including forming a plurality of openings in the substrate.3. The method of claim 1 , further including forming a redistribution layer (RDL) over the semiconductor package opposite the substrate.4. The method of claim 3 , wherein a pitch of the substrate is greater than a pitch of the RDL.5. The method of claim 3 , wherein a pitch of the substrate is less than a pitch of the RDL.6. The method of claim 1 , wherein the adhesive extends to the interconnect structure of the substrate.7. A method of making a semiconductor device claim 1 , comprising:providing a semiconductor package; ...

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Номер записи: 17
11-02-2016 дата публикации

SEMICONDUCTOR COOLING STRUCTURE AND METHOD IN A MIXED BONDING PROCESS

Номер: US20160043058A1
Автор: CHEN Jun, CHENG Weihua, Mei Shaoning, Zhu Jifeng
Принадлежит:

The invention provides a semiconductor cooling structure and method in a mixed bonding process, and comprises: providing two wafers which require to be treated by a mixed bonding process, each of the wafers being provided with several metallic device structure layers therein; a heat dissipation layer is set in at least one of the wafer, the heat dissipation layer is arranged in the free area above at least one of the metallic device structure layers, and the heat dissipation layer connects to the adjacent metallic device structure layer which is adjacent to and below the heat dissipation layer; wherein material of each of the heat dissipation layers is good conductors of heat. The invention can make heat generated during bonding process transfer and distribute evenly. 1. A semiconductor cooling method in a mixed bonding process , comprising:providing two wafers which require to be treated by a mixed bonding process, each of the wafers being provided with several metallic device structure layers therein;a heat dissipation is arranged in at least one of the wafers, said heat dissipation layer is arranged in the free area above at least one of the metallic device structure layers, and the heat dissipation layer connects to the adjacent metallic device structure layer which is adjacent to and below the heat dissipation layer;wherein, material of each of said heat dissipation layers is good conductors of heat.2. The semiconductor cooling method in a mixed bonding process as claimed in claim 1 , wherein the material of said heat dissipation layers is metal.3. The semiconductor cooling method in a mixed bonding process as claimed in claim 1 , wherein said heat dissipation layer claim 1 , through several holes claim 1 , connects to the adjacent metallic device structure layer which is adjacent to and below the heat dissipation layer.4. The semiconductor cooling method in a mixed bonding process as claimed in claim 3 , wherein said several holes uniformly distribute in a ...

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Номер записи: 18
07-02-2019 дата публикации

SUBSTRATE BONDING APPARATUS AND SUBSTRATE BONDING METHOD

Номер: US20190043826A1
Автор: FUKUDA MINORU, MITSUISHI Hajime, Sugaya Isao
Принадлежит: NIKON CORPORATION

A substrate bonding apparatus that brings a part of a surface of a first substrate and a part of a surface of a second substrate into contact to form contact regions at the parts, and then enlarges the contact regions to bond the first substrate and the second substrate includes: a temperature adjusting unit that adjusts a temperature of at least one of the first substrate and the second substrate such that positional misalignment between the first substrate and the second substrate does not exceed a threshold at least in a course of enlargement of the contact regions. 1. A substrate bonding apparatus that brings a part of a surface of a first substrate and a part of a surface of a second substrate into contact to form contact regions at the parts , and then enlarges the contact regions to bond the first substrate and the second substrate , the substrate bonding apparatus comprising:a temperature adjusting unit that adjusts a temperature of at least one of the first substrate and the second substrate such that positional misalignment between the first substrate and the second substrate does not exceed a threshold at least in a course of enlargement of the contact regions.2. The substrate bonding apparatus according to claim 1 , wherein the temperature adjusting unit adjusts a temperature of at least one of non-contact regions of the first substrate and the second substrate such that positional misalignment which is equal to or larger than the threshold does not occur between the non-contact regions claim 1 , the non-contact regions being regions in which the surface of the first substrate and the surface of the second substrate are not in contact yet.3. The substrate bonding apparatus according to claim 2 , wherein the temperature adjusting unit keeps a temperature difference between the non-contact regions within a predetermined range until the non-contact regions come into contact.4. The substrate bonding apparatus according to claim 1 , wherein the temperature ...

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Номер записи: 19
18-02-2021 дата публикации

BONDING SYSTEM AND BONDING METHOD

Номер: US20210050243A1
Автор: Otsuka Yoshitaka
Принадлежит:

A bonding system includes a first holder and a second holder arranged to be spaced apart from each other in a vertical direction; a position adjuster configured to move the first holder and the second holder relatively to perform a position adjustment in a horizontal direction between a first substrate held by the first holder and a second substrate held by the second holder; a pressing unit configured to press the first substrate and the second substrate against each other; a measuring unit configured to measure a position deviation between an alignment mark on the first substrate and an alignment mark on the second substrate, the first substrate and the second substrate being bonded by the pressing unit; and a position adjustment controller configured to control the position adjustment in the horizontal direction in a currently-performed bonding processing based on the position deviation generated in a previously-performed bonding processing. 1. A bonding system , comprising:a first holder and a second holder arranged to be spaced apart from each other in a vertical direction, the first holder having, on a surface thereof facing the second holder, an attraction surface configured to attract and hold a first substrate, and the second holder having, on a surface thereof facing the first holder, an attraction surface configured to attract and hold a second substrate;a position adjuster configured to move the first holder and the second holder relatively to perform a position adjustment in a horizontal direction between the first substrate held by the first holder and the second substrate held by the second holder;a pressing unit configured to press the first substrate held by the first holder and the second substrate held by the second holder against each other;a measuring unit configured to measure a position deviation between an alignment mark formed on the first substrate and an alignment mark formed on the second substrate, the first substrate and the second ...

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Номер записи: 20
16-02-2017 дата публикации

Apparatus And Method For Verification Of Bonding Alignment

Номер: US20170047260A1
Автор: Chao Lan-Lin, Huang Xin-Hua, Liu Ping-Yin
Принадлежит:

Presented herein is a device comprising a common node disposed in a first wafer a test node disposed in a first wafer and having a plurality of test pads exposed at a first surface of the first wafer. The test node also has test node lines connected to the test pads and that are separated by a first spacing and extend to a second surface of the first wafer. A comb is disposed in a second wafer and has a plurality of comb lines having a second spacing different from the first spacing. Each of the comb lines has a first surface exposed at a first side of the second wafer. The comb lines provide an indication of an alignment of the first wafer and second wafer by a number or arrangement of connections made by the plurality of comb lines between the test node lines and the common node. 1. A device comprising:a common node disposed in a first wafer;a test node disposed in the first wafer and having a plurality of test pads exposed at a first surface of the first wafer, the test node further having a plurality of test node lines separated by a first spacing and exposed at a second surface of the first wafer and each connected to a respective one of the plurality of test pads; anda comb disposed in a second wafer and having a plurality of comb lines having a second spacing different from the first spacing, each of the comb lines having a first surface exposed at a first side of the second wafer.2. The device of claim 1 , wherein the common node includes a common node pad exposed at the first surface of the first wafer and further includes a plurality of common node lines exposed at the second surface of the first wafer claim 1 , the common node lines being separated by the first spacing.3. The device of claim 1 , wherein respective test node lines of the plurality of test node lines comprises substantially straight conductive line segments extending from the first surface of the first wafer to the second surface of the first wafer.4. The device of claim 1 , wherein at ...

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Номер записи: 21
14-02-2019 дата публикации

Hybrid Bonding Systems and Methods for Semiconductor Wafers

Номер: US20190051628A1
Автор: Chao Lan-Lin, Huang Xin-Hua, LIN SHIH-WEI, Liu Ping-Yin, Tsai Chia-Shiung
Принадлежит:

Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together. 1. A method comprising:depositing a first protection layer on a first bonding surface of a first semiconductor wafer;removing the first protection layer from the first bonding surface of the first semiconductor wafer to expose the first bonding surface of the first semiconductor wafer;applying a plasma process to the first bonding surface of the first semiconductor wafer;performing a cleaning process on the first bonding surface of the first semiconductor wafer;coupling the first semiconductor wafer to a second semiconductor wafer; andannealing the first semiconductor wafer and the second semiconductor wafer to bond the first bonding surface of the first semiconductor wafer to a second bonding surface of the second semiconductor wafer, wherein bonding the first bonding surface of the first semiconductor wafer to the second bonding surface of the second semiconductor wafer comprises:forming a first bond between a first insulating layer of the first bonding surface and a second insulating layer of the second bonding surface; andforming a second bond between a first conductive pad of the first bonding ...

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Номер записи: 22
22-02-2018 дата публикации

Semiconductor Packages and Methods of Forming the Same

Номер: US20180053730A1
Автор: Chen-Hua Yu, Chih-Hang Tung, Tung-Liang Shao
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Semiconductor packages and methods of forming the same are disclosed. Embodiments include forming a first recess in a first substrate, wherein a first area of an opening of the first recess is larger than a second area of a bottom of the first recess. The embodiments also include forming a first device, wherein a third area of a top end of the first device is larger than a fourth area of a bottom end of the first device. The embodiments also include placing the first device into the first recess, wherein the bottom end of the first device faces the bottom of the first recess, and bonding a sidewall of the first device to a sidewall of the first recess.

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Номер записи: 23
25-02-2021 дата публикации

SUBSTRATE BONDING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE BY USING THE SAME

Номер: US20210057373A1
Автор: Han Ilyoung, KIM HOECHUL, Kim Taeyeong
Принадлежит:

A substrate bonding method and apparatus are described. The substrate bonding apparatus is used to bond a first substrate to a second substrate. The bonding apparatus includes a first bonding chuck configured to hold the first substrate on a first surface of the first bonding chuck; a second bonding chuck configured to hold the second substrate on a second surface of the second bonding chuck, the second surface facing the first surface of the first bonding chuck; a seal arranged between the first bonding chuck and the second bonding chuck and adjacent to at least one edge of the first substrate and at least one edge of the second substrate; and a process gas supply device configured to supply a process gas to a bonding space surrounded by the seal. 1. A substrate bonding apparatus for bonding a first substrate to a second substrate , a first bonding chuck configured to hold the first substrate on a first surface of the first bonding chuck;', 'a second bonding chuck configured to hold the second substrate on a second surface of the second bonding chuck, the second surface facing the first surface of the first bonding chuck;', 'a seal arranged between the first bonding chuck and the second bonding chuck and adjacent to at least one edge of the first substrate and at least one edge of the second substrate, and configured to enclose a bonding space; and', 'a process gas supply device configured to supply a process gas to the bonding space enclosed by the seal., 'the substrate bonding apparatus comprising2. The substrate bonding apparatus of claim 1 , whereina first portion of the seal is detachably coupled to the first bonding chuck, anda second portion of the seal is coupled to the second bonding chuck, the second portion of the seal being opposite the first portion of the seal.3. The substrate bonding apparatus of claim 2 , whereinthe first bonding chuck comprises a vacuum groove, andthe substrate bonding apparatus further comprises a vacuum pump configured to provide ...

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Номер записи: 24
20-02-2020 дата публикации

CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

Номер: US20200058614A1
Автор: CHANG Geng-Ming, Shao Tung-Liang, Tung Chih-Hang, Yang Su-Chun, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A method for forming a chip package structure is provided. The method includes partially removing a first redistribution layer to form an alignment trench in the first redistribution layer. The alignment trench surrounds a bonding portion of the first redistribution layer. The method includes forming a liquid layer over the bonding portion. The method includes disposing a chip structure over the liquid layer, wherein a first width of the bonding portion is substantially equal to a second width of the chip structure. The method includes evaporating the liquid layer. The chip structure is in direct contact with the bonding portion after the liquid layer is evaporated. 1. A method for forming a chip package structure , comprising:partially removing a first redistribution layer to form an alignment trench in the first redistribution layer, wherein the alignment trench surrounds a first bonding portion of the first redistribution layer;forming a liquid layer over the first bonding portion;disposing a chip structure over the liquid layer, wherein a first width of the first bonding portion is substantially equal to a second width of the chip structure; andevaporating the liquid layer, wherein the chip structure is bonded to the first bonding portion after the liquid layer is evaporated.2. The method for forming the chip structure package structure as claimed in claim 1 , wherein the liquid layer is made of water.3. The method for forming the chip package structure as claimed in claim 1 , further comprising:before partially removing the first redistribution layer to form the alignment trench in the first redistribution layer, forming the first redistribution layer over a substrate.4. The method for forming the chip package structure as claimed in claim 1 , wherein a first length of the first bonding portion is substantially equal to a second length of the chip structure.5. The method for forming the chip package structure as claimed in claim 1 , wherein the chip structure ...

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Номер записи: 25
02-03-2017 дата публикации

CONDUCTIVE BARRIER DIRECT HYBRID BONDING

Номер: US20170062366A1
Автор: ENQUIST Paul M.
Принадлежит: Ziptronix, Inc.

A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region. 1. A method of forming a direct hybrid bond surface , comprising:forming a first plurality of metallic contact structures in an upper surface of a first substrate, where a top surface of said structures is below said upper surface;forming a first layer of conductive barrier material over said upper surface and said plurality of metallic contact structures; andremoving said first layer of conductive barrier material from said upper surface.2. The method according to claim 1 , comprising:removing said first layer conductive barrier material to leave said conductive barrier material on said plurality of metal contact structures, a top surface of said conductive barrier material on said plurality of metal contact structures being below said upper surface of said substrate by less than 20 nm.3. The method according to claim 1 , comprising:removing said first layer of conductive barrier material to leave said conductive barrier material on said plurality of metal contact structures, a top surface of said conductive barrier material on said plurality of metal contact structures being below said upper surface of said substrate in a ...

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Номер записи: 26
04-03-2021 дата публикации

PACKAGE AND MANUFACTURING METHOD THEREOF

Номер: US20210066248A1
Автор: Chen Ming-Fa, Hong Jian-Wei, Yeh Sung-Feng
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), a second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs. 1. A package , comprising:a first die;a second die stacked on the first die;a first encapsulant laterally encapsulating the first die;first through insulating vias (TIV) aside the first die, wherein the first TIVs penetrate through the first encapsulant and are electrically floating;a second encapsulant laterally encapsulating the second die; andsecond TIVs aside the second die, wherein the second TIVs penetrate through the second encapsulant and are electrically floating, and the second TIVs are substantially aligned with the first TIVs.2. The package of claim 1 , further comprising:a first bonding layer over the first die, the first encapsulant, and the first TIVs, wherein the first bonding layer comprises first bonding pads and connecting pads, and the first TIVs are connected to the connecting pads; anda second bonding layer sandwiched between the first bonding layer and the second die, wherein the second bonding layer comprises second bonding pads, and the first bonding pads are hybrid bonded to the second bonding pads.3. The package of claim 1 , further comprising:a carrier substrate over the second die and the second encapsulant.4. The package of claim 1 , wherein the first die comprises:a first semiconductor substrate;first through semiconductor vias (TSV) penetrating through the first semiconductor substrate;a first interconnection structure ...

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Номер записи: 27
08-03-2018 дата публикации

Conductive Pad Structure for Hybrid Bonding and Methods of Forming Same

Номер: US20180068965A1
Автор: Chen Sheng-Chau, Chou Cheng-Hsien, Chou Shih Pei, Chu Yen-Chang, HUANG Chih-Hui, Tu Yeur-Luen
Принадлежит:

A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the device die is patterned to extend the opening further into the device die. After patterning, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material. 1. A device comprising:a first substrate;a first redistribution structure over the first substrate;a first dielectric layer over the first redistribution structure; and a first portion extending through the first dielectric layer, the first portion having a first width; and', 'a second portion extending through the first redistribution structure, the second portion having a second width, the second width being different from the first width., 'a first conductive pad extending through the first dielectric layer and the first redistribution structure, a bottommost surface of the first conductive pad being below a bottommost surface of the first redistribution structure, wherein the first conductive pad comprises2. The device of claim 1 , wherein the second width is less than the first width.3. The device of claim 1 , further comprising:a second substrate;a second redistribution structure interposed between the second substrate and the first dielectric layer;a second dielectric layer interposed between the second redistribution structure and the first dielectric layer, the second dielectric layer being in physical contact with first dielectric layer; anda second conductive pad extending through the second dielectric layer and the second redistribution structure, the second conductive pad being in physical contact with the first conductive pad.4. The device of claim 3 , wherein a topmost surface of the second conductive pad is above a topmost surface of the second redistribution structure.5. The device of claim 3 , wherein the second conductive pad comprises:a third portion extending through the second ...

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Номер записи: 28
08-03-2018 дата публикации

METHOD FOR BONDING AND INTERCONNECTING INTEGRATED CIRCUIT DEVICES

Номер: US20180068984A1
Автор: Beyne Eric, De Vos Joeri, Van Huylenbroeck Stefaan
Принадлежит:

A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple IC devices are provided with metal contact structures. At least the upper substrate is provided prior to bonding with a cavity in its bonding surface. A TSV (Through Semiconductor Via) is produced through the bonded wafer assembly and an aggregate opening is formed including the TSV opening and the cavity. After the formation of an isolation liner on at least part of the sidewalls of the aggregate opening (that is, at least on the part where the liner isolates the aggregate opening from semiconductor material), a TSV interconnection plug is produced in the aggregate opening. 1. A method for bonding and interconnecting a first IC device arranged on a first substrate to a second IC device arranged on a second substrate , wherein each IC device comprises a dielectric bonding layer at its outer surface , and wherein each IC device further comprises one or more metal contact structures , wherein the method comprises the steps of:producing at least one cavity in the outer surface of the first IC device, the cavity traversing at least the dielectric bonding layer of the first IC device;aligning the first substrate with respect to the second substrate, and forming a substrate assembly by direct bonding between the bonding layers, so that in the substrate assembly the cavity formed in the first IC device overlaps a contact structure of the second IC device;after bonding, optionally thinning the first substrate;producing a Through Substrate Via (TSV) opening in the first substrate, the TSV opening overlapping the cavity;forming an aggregate opening comprising the TSV opening and the cavity, thereby exposing at least part of the contact structure of the second IC device;after the formation of an isolation liner on at least part of the sidewalls of ...

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Номер записи: 29
11-03-2021 дата публикации

BONDING ALIGNMENT MARKS AT BONDING INTERFACE

Номер: US20210072653A1
Автор: Hu Shun, Hu Si Ping, Wang Jia Wen, YAN Meng
Принадлежит:

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first device layer is formed on a first substrate. A first bonding layer including a first bonding contact and a first bonding alignment mark is formed above the first device layer. A second device layer is formed on a second substrate. A second bonding layer including a second bonding contact and a second bonding alignment mark is formed above the second device layer. The first bonding alignment mark is aligned with the second bonding alignment mark, such that the first bonding contact is aligned with the second bonding contact. The first substrate and the second substrate are bonded in a face-to-face manner, so that the first bonding contact is in contact with the second bonding contact at a bonding interface, and the first bonding alignment mark is in contact with the second bonding alignment mark at the bonding interface. 1. A method for forming a semiconductor device , comprising:forming a first device layer on a first substrate;forming a first bonding layer comprising a first bonding contact and a first bonding alignment mark above the first device layer;forming a second device layer on a second substrate;forming a second bonding layer comprising a second bonding contact and a second bonding alignment mark above the second device layer;aligning the first bonding alignment mark with the second bonding alignment mark, such that the first bonding contact is aligned with the second bonding contact; andbonding the first substrate and the second substrate in a face-to-face manner, so that the first bonding contact is in contact with the second bonding contact at a bonding interface, and the first bonding alignment mark is in contact with the second bonding alignment mark at the bonding interface.2. The method of claim 1 , wherein a dimension of each of the first and second bonding alignment marks is ...

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Номер записи: 30
05-03-2020 дата публикации

BOND ENHANCEMENT IN MICROELECTRONICS BY TRAPPING CONTAMINANTS AND ARRESTING CRACKS DURING DIRECT-BONDING PROCESSES

Номер: US20200075533A1
Автор: Delacruz Javier A., FOUNTAIN, Gao Guilian, Huang Shaowu, JR. Gaius Gillman, Katkar Rajesh, Uzoh Cyprian Emeka, Wang Liang
Принадлежит:

Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process. 1. A method , comprising:planarizing a bonding surface of a die or a wafer to a flatness sufficient for direct bonding or for direct hybrid bonding at a bonding interface; andproviding a recess in the bonding surface before, during, or after the planarizing step, the recess configured to arrest propagation of cracking, chipping, or delamination in the bonding surface, in a bonding layer, or in a completed bond of the bonding surface.2. The method of claim 1 , further comprising joining the bonding surface with another bonding surface in a direct-bonding process or a direct hybrid bonding process.3. The method of claim 2 , further comprising providing the recess in the bonding surface at or near the location of a stress point or a stress area to arrest the cracking or chipping.4. The method of claim 1 , further comprising vertically aligning a first recess in a first bonding surface with a ...

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Номер записи: 31
18-03-2021 дата публикации

Flat metal features for microelectronics applications

Номер: US20210082754A1
Автор: Cyprian Emeka Uzoh
Принадлежит: Invensas LLC

Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.

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Номер записи: 32
18-03-2021 дата публикации

SEMICONDUCTOR STORAGE DEVICE

Номер: US20210082896A1
Автор: HARASHIMA Hiromitsu, KAMEDA Yasushi
Принадлежит:

A semiconductor storage device includes first and second chips. The first chip includes memory cells provided on a first substrate in a memory cell region, a plurality of first pads provided on a first surface of the first substrate and disposed in an edge region of the first chip that surrounds the memory cell region, and a first conductive layer provided on the first substrate and electrically connected to the first pads. The second chip includes a first circuit provided on a second substrate in a circuit region, a plurality of second pads provided on the second substrate and disposed in an edge region of the second chip that surrounds the circuit region, and a second conductive layer provided on the second substrate and electrically connected to the second pads. The first pads of the first chip and the second pads of the second chip are bonded facing each other. 1. A semiconductor storage device comprising: a plurality of memory cells provided on a first substrate in a memory cell region,', 'a plurality of first pads provided on a first surface of the first substrate and disposed in an edge region of the first chip that surrounds the memory cell region, and', 'a first conductive layer provided on the first substrate and electrically connected to the first pads; and, 'a first chip including'} a first circuit provided on a second substrate in a circuit region,', 'a plurality of second pads provided on the second substrate and disposed in an edge region of the second chip that surrounds the circuit region, and', 'a second conductive layer provided on the second substrate and electrically connected to the second pads,, 'a second chip including'}wherein the first pads of the first chip and the second pads of the second chip are bonded facing each other.2. The semiconductor storage device according to claim 1 , wherein the first pads claim 1 , the first conductive layer claim 1 , the second pads claim 1 , and the second conductive layer are electrically insulated from ...

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Номер записи: 33
31-03-2016 дата публикации

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

Номер: US20160093601A1
Автор: DING JINGXIU, HE ZUOPENG
Принадлежит:

Semiconductor structure and fabrication methods are provided. The semiconductor structure includes a first wafer having a first metal layer therein and having a first material layer thereon, and a second wafer having a second metal layer therein and having a second material layer thereon. An alignment process and a bonding process are preformed between the first wafer and the second wafer, such that the first material layer and the second material layer are aligned and in contact with one another to provide a first alignment accuracy between the first metal layer and second metal layer. A heating process is performed on the first material layer and the second material layer to melt the first material layer and the second material layer to provide a second alignment accuracy between the first metal layer and second metal layer. The second alignment accuracy is greater than the first alignment accuracy. 1. A method for forming a semiconductor structure , comprising:providing a first wafer and a second wafer, wherein a first metal layer is formed in the first wafer and has a top surface exposed, and a second metal layer is formed in the second wafer and has a top surface exposed;forming a first material layer on the first wafer, wherein the first material layer and the first metal layer are on a same side of the first wafer;forming a second material layer on the second wafer, wherein the second material layer and the second metal layer are on a same side of second wafer;performing an alignment process and a bonding process between the first wafer and the second wafer, such that the first material layer and the second material layer are aligned and in contact with one another to provide a first alignment accuracy between the first metal layer and second metal layer; andafter the bonding process, performing a heating process on the first material layer and the second material layer, such that the first material layer and the second material layer are melted into one ...

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Номер записи: 34
05-05-2022 дата публикации

STACKED SEMICONDUCTOR DEVICE

Номер: US20220139445A1
Автор: Ware Frederick A.
Принадлежит:

A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies.

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Номер записи: 35
05-05-2022 дата публикации

Semiconductor structure and method for forming the same

Номер: US20220139771A1
Автор: Jen-Yuan Chang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor structure includes a first die, a second die over the first die, and a positioning member disposed within a bonding dielectric and configured to align the second die with the first die. A method for forming a semiconductor structure includes receiving a first die having a first bonding layer; forming a recess on the first bonding layer; forming a positioning member on a second die; bonding the second die over the first die using the first bonding layer; and disposing the positioning member into the recess.

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Номер записи: 36
05-05-2022 дата публикации

Semiconductor wafer and method for fabricating the same

Номер: US20220139841A1
Автор: Han Byul JANG, Jung-A Lee, Yeon Sook Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor wafer includes a wafer body including an active layer having a first crystal orientation and having first and second surfaces opposing each other, and a support layer having a second crystal orientation different from the first crystal orientation and having third and fourth surfaces opposing each other, a bevel portion that extends along an outer periphery of the wafer body to connect the first surface to the fourth surface, and a notch portion formed at a predetermined depth in a direction from the outer periphery of the wafer body toward a center portion of the wafer body. The bevel portion includes a first beveled surface connected to the first surface and a second beveled surface connected to the fourth surface. The first beveled surface has a width in a radial direction of the wafer body that is 300 μm or less.

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Номер записи: 37
05-04-2018 дата публикации

Substrate attachment for attaching a substrate thereto

Номер: US20180096962A1
Автор: Andreas Fehkührer
Принадлежит: EV Group E Thallner GmbH

A method for bonding a first substrate with a second substrate, characterized in that the first substrate and/or the second substrate is/are thinned before the bonding.

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Номер записи: 38
28-03-2019 дата публикации

Method for aligning chip components relative to substrate by using liquid

Номер: US20190096697A1
Автор: Kangwook Lee, Mitsumasa Koyanagi, Satohiko Hoshino, Shinya KIKUTA, Takafumi Fukushima
Принадлежит: Tohoku University NUC, Tokyo Electron Ltd

A liquid is supplied to a substrate and a chip component is arranged on the liquid. The substrate includes a first surface in which a rectangular mounting region is formed. The chip component includes a second surface having a rectangular shape which substantially coincides with the shape of the mounting region, and has an area substantially equal to that of the mounting region. The mounting region includes first and second regions. Wettability of the first region with respect to the liquid is higher than that of the second region with respect to the liquid. The first region is provided symmetrically with respect to a first central line passing through the middle of a pair of long sides and a second central line passing through the middle of a pair of short sides in the mounting region, and includes rectangular partial regions. The liquid is supplied to the first region.

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Номер записи: 39
12-04-2018 дата публикации

Chip package and method for forming the same

Номер: US20180102321A1
Автор: Chia-Ming Cheng, Hsin-Yen Lin, Po-Han Lee, Yen-Shih Ho
Принадлежит: XinTec Inc

A chip package including a substrate having an upper surface, a lower surface, and a sidewall surface that is at the edge of the substrate is provided. The substrate includes a sensor device therein and adjacent to the upper surface thereof. The chip package further includes light-shielding layer disposed over the sidewall surface of the substrate and extends along the edge of the substrate to surround the sensor device. The chip package further includes a cover plate disposed over the upper surface of the substrate and a spacer layer disposed between the substrate and the cover plate. A method of forming the chip package is also provided.

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Номер записи: 40
02-06-2022 дата публикации

BONDING ALIGNMENT MARKS AT BONDING INTERFACE

Номер: US20220173038A1
Автор: Hu Shun, Hu Si Ping, Wang Jia Wen, YAN Meng
Принадлежит:

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a bonded structure includes a first bonding layer including a first bonding contact and a first bonding alignment mark, a second bonding layer including a second bonding contact and a second bonding alignment mark, and a bonding interface between the first bonding layer and the second bonding layer. The first bonding alignment mark is aligned with the second bonding alignment mark at the bonding interface, such that the first bonding contact is aligned with the second bonding contact at the bonding interface. The first bonding alignment mark includes a plurality of first repetitive patterns. The second bonding alignment mark includes a plurality of second repetitive patterns different from the plurality of first repetitive patterns. 1. A bonded structure , comprising:a first bonding layer comprising a first bonding contact and a first bonding alignment mark;a second bonding layer comprising a second bonding contact and a second bonding alignment mark; anda bonding interface between the first bonding layer and the second bonding layer,wherein the first bonding alignment mark is aligned with the second bonding alignment mark at the bonding interface, such that the first bonding contact is aligned with the second bonding contact at the bonding interface;the first bonding alignment mark comprises a plurality of first repetitive patterns; andthe second bonding alignment mark comprises a plurality of second repetitive patterns different from the plurality of first repetitive patterns.2. The bonded structure of claim 1 , wherein the plurality of first repetitive patterns are repetitive strips and the plurality of second repetitive patterns are repetitive squares.3. The semiconductor device of claim 2 , wherein the repetitive strips of the plurality of first repetitive patterns and the repetitive squares of the plurality of second repetitive patterns are at least ...

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Номер записи: 41
30-04-2015 дата публикации

DEVICE INCLUDING SEMICONDUCTOR CHIPS AND METHOD FOR PRODUCING SUCH DEVICE

Номер: US20150115475A1
Автор: Palm Petteri, Scharf Thorsten
Принадлежит: INFINEON TECHNOLOGIES AG

A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip. 1. A device , comprising:a first semiconductor chip comprising a first face, wherein a first contact pad is arranged over the first face of the first semiconductor chip; anda second semiconductor chip comprising a first face, wherein a first contact pad is arranged over the first face of the second semiconductor chip,wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction,wherein the first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.2. The device of claim 1 , wherein the first face of the first semiconductor chip and a second face of the second semiconductor chip claim 1 , opposite to the first face of the second semiconductor chip claim 1 , are arranged on different heights.3. The device of claim 1 , wherein at least one of the first semiconductor chip and the second semiconductor chip comprises a power semiconductor.4. The device of claim 1 , wherein the first semiconductor chip comprises a second contact pad arranged over a second face of the first semiconductor chip opposite to the first face of the first semiconductor chip.5. The device of claim ...

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Номер записи: 42
02-04-2020 дата публикации

Method and apparatus to control transfer parameters during transfer of semiconductor devices

Номер: US20200105551A1
Автор: Andrew Huska, Cody Peterson, Justin Wendt
Принадлежит: Rohinni LLC

An apparatus includes a transfer mechanism to transfer an electrically-actuatable element directly from a wafer tape to a transfer location on a circuit trace on a product substrate. The transfer mechanism includes one or more transfer wires. Two or more stabilizers disposed on either side of the one or more transfer wires. A needle actuator is connected to the one or more transfer wires and the two or more stabilizers to move the one or more transfer wires and the two or more stabilizers to a die transfer position.

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Номер записи: 43
09-04-2020 дата публикации

Semiconductor device and method of forming a semiconductor device

Номер: US20200111750A1
Автор: Jia Yi WONG, Marius Aurel Bodea, Stefan Beyer
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device and method is disclosed. The semiconductor device may include a semiconductor substrate including an active area, a metal layer structure over the active area, wherein the metal layer structure is configured to form an electrical contact, the metal layer structure including a solder area, a buffer area, and a barrier area between the solder area and the buffer area, wherein, in the barrier area, the metal layer structure is further away from the active area than in the solder area and in the buffer area, and wherein each of the solder area and the buffer area is in direct contact with the active area or with a wiring layer structure arranged between the active area and the metal layer structure.

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Номер записи: 44
09-04-2020 дата публикации

Semiconductor package

Номер: US20200111763A1
Автор: Ji-Hoon Kim, Ji-Seok HONG
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor package includes: a lower semiconductor chip including a first semiconductor substrate, which includes a first semiconductor device on an active surface thereof and a protrusion defined by a recess region on an inactive surface thereof opposite to the active surface, a plurality of external connecting pads on a bottom surface of the first semiconductor substrate, and a plurality of through-electrodes electrically connected to the plurality of external connecting pads; and at least one upper semiconductor chip stacked on the protrusion of the lower semiconductor chip and electrically connected to the plurality of through-electrodes, the at least one upper semiconductor chip including a second semiconductor substrate which includes a second semiconductor device on an active surface thereof.

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Номер записи: 45
14-05-2015 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20150130085A1
Автор: HINO Yasunari
Принадлежит: Mitsubishi Electric Corporation

A manufacturing method of a semiconductor device according to the present invention includes the steps of (a) preparing an insulating or conductive substrate; (b) arranging a bonding material having sinterability in at least one bonding region of a principal surface of the substrate (i.e., insulating substrate); and (c) sintering the bonding material while a bonding surface to be subjected to bonding of at least one semiconductor element is brought into pressurized contact with the bonding material, and bonding the substrate (i.e., insulating substrate) and the semiconductor element together through the bonding material. The bonding region in the step (b) is inwardly positioned from the bonding surface (i.e., region) of the semiconductor element in plan view, and the bonding material is not protruded outwardly from the bonding surface of the semiconductor element in plan view even after the step (c). 1. A manufacturing method of a semiconductor device , comprising the steps of:(a) preparing an insulating or conductive substrate;(b) arranging a bonding material having sinterability in at least one bonding region of a principal surface of said substrate; and(c) sintering said bonding material while a bonding surface to be subjected to bonding of at least one semiconductor element is brought into pressurized contact with said bonding material, and bonding said substrate and said semiconductor element together through said bonding material,wherein said bonding region in said step (b) is inwardly positioned from the bonding surface of said semiconductor element in plan view, andsaid bonding material is not protruded outwardly from the bonding surface of said semiconductor element in plan view even after said step (c).2. The manufacturing method of a semiconductor device according to claim 1 ,wherein, after said step (c), said bonding material is a conductive metal having any of Ag, Cu, Pd, and Au as a main component.3. The manufacturing method of a semiconductor device ...

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Номер записи: 46
03-05-2018 дата публикации

DISPLAY APPARATUS AND METHOD FOR BINDING THE SAME

Номер: US20180122758A1
Автор: CHEN Liqiang, Zhou Huiji
Принадлежит:

Embodiments of the present application provide a display apparatus and a method for binding the same. The apparatus includes: a flexible display panel; and a chip on film bound on a binding region of the flexible display panel. The chip on film has at least two rows of output pads and the flexible display panel has at least two rows of input pads. Virtual elongation lines of all of the output pads intersect at a same intersection point in a first datum line perpendicular to the first direction. The output pads are electrically connected to the input pads and the output pads and the input pads have the virtual elongation lines at a same angle with respect to a common datum line, the common datum line being composed of the first datum line and the second datum line coinciding with each other. 1. A display apparatus , comprising:a flexible display panel; anda chip on film bound on a binding region of the flexible display panel;wherein the chip on film has at least two rows of output pads separated from each other, the at least two rows of output pads being arranged along a first direction, and virtual elongation lines of all of the output pads intersect at a same intersection point in a first datum line perpendicular to the first direction, and wherein in a same row of output pads, the farther a distance between the virtual elongation line of the output pad and the first datum line is, the larger an angle between said virtual elongation line and the first datum line becomes;wherein the flexible display panel has at least two rows of input pads separated from each other, the at least two rows of input pads being arranged along the first direction, and the input pads are in one to one correspondence with the output pads, and wherein virtual elongation lines of all of the input pads intersect at a same intersection point in a second datum line perpendicular to the first direction, and wherein in a same row of input pads, the farther a distance between the virtual ...

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Номер записи: 47
25-08-2022 дата публикации

MANUFACTURING METHOD OF PACKAGE

Номер: US20220271012A1
Автор: Chen Ming-Fa, Hong Jian-Wei, Yeh Sung-Feng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A manufacturing method of a package includes at least the following steps. Contact vias are embedded in a semiconductor carrier. The contact vias are electrically grounded. A first die and a first encapsulant are provided over the semiconductor carrier. The first encapsulant encapsulates the first die. First through insulating vias (TIV) are formed aside the first die. The first TIVs are electrically grounded through the contact vias. The first die, the first encapsulant, and the first TIVs are grinded. A second die is stacked over the first die. 1. A manufacturing method of a package , comprisingembedding contact vias in a semiconductor carrier, wherein the contact vias are electrically grounded;providing a first die and a first encapsulant over the semiconductor carrier, wherein the first encapsulant encapsulates the first die;forming first through insulating vias (TIV) aside the first die, wherein the first TIVs are electrically grounded through the contact vias;grinding the first die, the first encapsulant, and the first TIVs; andstacking a second die over the first die.2. The method of claim 1 , further comprising:forming an alignment layer over the semiconductor carrier, wherein the alignment layer comprises alignment marks.3. The method of claim 2 , wherein the alignment marks are formed between and electrically connected to the contact vias and the first TIVs.4. The method of claim 2 , further comprising:forming a dielectric layer between the alignment layer and the first encapsulant, wherein the first TIVs penetrate through the dielectric layer.5. The method of claim 1 , further comprising:forming a first bonding layer over the first die, the first encapsulant, and the first TIVs; andforming a second bonding layer over the second die, wherein the first bonding layer is hybrid bonded to the second bonding layer.6. The method of claim 5 , further comprising:encapsulating the second die and the second bonding layer by a second encapsulant; andforming a carrier ...

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Номер записи: 48
16-04-2020 дата публикации

Method of aligning wafers, method of bonding wafers using the same, and apparatus for performing the same

Номер: US20200118964A1
Автор: Hyun-Mog Park
Принадлежит: SAMSUNG ELECTRONICS CO LTD

In a method of aligning wafers, a second wafer having at least one second alignment key may be arranged over a first wafer having at least one first alignment key. At least one alignment hole may be formed by passing through the second wafer to expose the second alignment key and the first alignment key. The first wafer and the second wafer may be aligned with each other using the first alignment key and the second alignment key exposed through the alignment hole. Thus, the first alignment key and the second alignment key exposed through the alignment hole may be positioned at a same vertical line to accurately align the first wafer with the second wafer.

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Номер записи: 49
01-09-2022 дата публикации

Semiconductor Device and Method of Manufacturing

Номер: US20220278063A1
Автор: Chen Ming-Fa, Hu Chih-Chia, Jan Sen-Bor, Yeh Sung-Feng, Yuan Ching-Pin
Принадлежит:

A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads. 1. A method of forming a semiconductor device , the method comprising:forming a first dielectric layer over a first substrate;patterning the first dielectric layer to form first openings in the first dielectric layer, the first dielectric layer having a centermost point on a top surface; anddepositing metal in the first openings to form first bond pads, the first bond pads comprising a first inner bond pad and a first outer bond pad, the first inner bond pad having a first diameter, the first outer bond pad having a second diameter, the second diameter being greater than the first diameter.2. The method of further comprising thinning the first substrate claim 1 , wherein the thinning the first substrate increases a distance between the first inner bond pad the first outer bond pad.3. The method of claim 1 , wherein the first bond pads further comprise a first outermost bond pad claim 1 , wherein the first outermost bond pad has a third diameter being greater than the second diameter.4. The method of further comprising: forming a second dielectric layer over a second substrate;', 'patterning the second dielectric layer to form second openings in the second dielectric layer; and', 'depositing metal in the second openings to form second bond pads, the second bond pads comprising a second inner bond pad and a second outer bond pad, the second outer bond pad having a fourth diameter, the second diameter ...

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Номер записи: 50
08-09-2022 дата публикации

ELECTRICAL OVERLAY MEASUREMENT METHODS AND STRUCTURES FOR WAFER-TO-WAFER BONDING

Номер: US20220285233A1
Автор: Li Liang, LI Minna, QIN Jenny
Принадлежит:

Alignment of a first wafer bonded to a second wafer can be determined using electrical wafer alignment methods. A wafer stack can be formed by overlaying a second wafer over a first wafer such that second metal bonding pads of the second wafer contact first metal bonding pads of the first wafer. A leakage current or a capacitance measurement step is performed between first alignment diagnostic structures in the first wafer and second alignment diagnostic structures in the second wafer for multiple mating pairs of first semiconductor dies in the first wafer and second semiconductor dies in the second wafer to determine the alignment. 1. A method of bonding a first wafer and a second wafer , comprising:providing a first wafer including a first two-dimensional array of first semiconductor dies, wherein each of the first semiconductor dies comprises a respective set of first metal bonding pads and a respective set of first alignment diagnostic structures located at a same level as the first metal bonding pads;providing a second wafer including a second two-dimensional array of second semiconductor dies, wherein each of the second semiconductor dies comprises a respective set of second metal bonding pads and a respective set of second alignment diagnostic structures located at a same level as the second metal bonding pads;forming a wafer stack by overlaying the second wafer over the first wafer such that the second metal bonding pads contact the first metal bonding pads and the first alignment diagnostic structures and the second alignment diagnostic structures are offset from each other;measuring at least one of a leakage current or a capacitance between the first alignment diagnostic structures and the second alignment diagnostic structures for multiple mating pairs of the first semiconductor dies and the second semiconductor dies; andbonding the second wafer to the first wafer.2. The method of claim 1 , wherein the step of bonding the second wafer to the first wafer ...

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Номер записи: 51
08-09-2022 дата публикации

Electrical overlay measurement methods and structures for wafer-to-wafer bonding

Номер: US20220285234A1
Автор: Akihiro Tobioka, Hajime Yamamoto, Hiroshi Sasaki, Ikue Yokomizo, Katsuya Kato, Kazuto Watanabe, Koichi Ito, Liang Li, Michiaki Sano, Ryo Hiramatsu, Takashi Yamaha
Принадлежит: Western Digital Technologies Inc

A method includes providing a first wafer including a respective set of first metal bonding pads and at least one first alignment diagnostic structure, providing a second wafer including a respective set of second metal bonding pads and a respective set of second alignment diagnostic structures, overlaying the first wafer and the second wafer, measuring at least one of a current, voltage or contact resistance between the first alignment diagnostic structures and the second alignment diagnostic structures to determine an overlay offset, and bonding the second wafer to the first wafer.

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Номер записи: 52
24-05-2018 дата публикации

METHOD OF SEMICONDUCTOR WAFER BONDING AND SYSTEM THEREOF

Номер: US20180144999A1
Автор: Huang Xin-Hua, LU KUAN-LIANG, Tu Yeur-Luen
Принадлежит:

A method of semiconductor wafer bonding and system thereof are proposed. A first alignment mark of a first semiconductor wafer is aligned with a second alignment mark of a second semiconductor wafer. A partial attachment is performed between the first semiconductor wafer and the second semiconductor wafer. A scanning is performed along a direction substantially parallel to a surface of the first semiconductor wafer. It is determined if a bonding defect of the partially attached first semiconductor wafer and the second semiconductor wafer exists. 1. A method of semiconductor wafer bonding , the method comprising:aligning a first alignment mark of a first semiconductor wafer with a second alignment mark of a second semiconductor wafer;performing a partial attachment between the first semiconductor wafer and the second semiconductor wafer;performing a scanning along a direction substantially parallel to a surface of the first semiconductor wafer; anddetermining if a bonding defect of the partially attached first semiconductor wafer and the second semiconductor wafer exists.2. The method of claim 1 , further comprising detaching the first semiconductor wafer from the second semiconductor wafer in response to the determination that a bonding defect exists.3. The method of claim 2 , wherein detaching the first semiconductor wafer from the second semiconductor wafer comprises causing the first semiconductor wafer to separate from the second semiconductor wafer with a gaseous flow.4. The method of claim 2 , wherein the bonding defect includes a bonding void between the first semiconductor wafer and the second semiconductor wafer.5. The method of claim 4 , further comprising claim 4 , in response to the determination that a bonding void exists:unloading the first semiconductor wafer and the second semiconductor wafer; andperforming a pre-bonding treatment for the first semiconductor wafer and the second semiconductor wafer.6. The method of claim 1 , wherein the defect ...

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Номер записи: 53
04-06-2015 дата публикации

SEMICONDUCTOR MANUFACTURING APPARATUSES AND METHODS THEREOF

Номер: US20150155210A1
Автор: CHOI Byeong Kap, KAJINAMI MASATO, KIM Hui-Jae, Kim Sang-Yoon, LEE Byung Joon, PARK Byeong-Kuk, Seok Seung Dae, SHIN Jae Bong, YUKIMORI YOSHIAKI
Принадлежит:

A semiconductor manufacturing apparatus may include: a pickup unit configured to pick up a chip in a first region of the semiconductor manufacturing apparatus; a bonding head configured to receive the picked-up chip and configured to move from the first region to a top of a circuit board in a second region of the semiconductor manufacturing apparatus; and/or an optical unit configured to detect a bonding position on the circuit board while moving from the first region to the second region. A semiconductor manufacturing apparatus may include: a bonding head including a heater for heating a chip and bonding the chip onto a circuit board; and/or a cooling block, adjacent to the heater, through which cooling liquid flows. The cooling liquid may be removed from the cooling block while the heater generates heat. The cooling liquid may be supplied to the cooling block while the heater is cooled. 1. A semiconductor manufacturing apparatus , comprising:a pickup unit configured to pick up a chip in a first region of the semiconductor manufacturing apparatus;a bonding head configured to receive the picked-up chip and configured to move from the first region to a top of a circuit board in a second region of the semiconductor manufacturing apparatus; andan optical unit configured to detect a bonding position on the circuit board while moving from the first region to the second region.2. The semiconductor manufacturing apparatus of claim 1 , wherein the optical unit is on an upper portion of the circuit board while the bonding head moves from the first region to the second region.3. The semiconductor manufacturing apparatus of claim 1 , wherein the bonding head bonds the chip at the detected bonding position after the bonding head reaches the second region.4. The semiconductor manufacturing apparatus of claim 1 , further comprising:a gantry frame having a hollow therein;wherein the bonding head is configured to move in the hollow, andwherein the bonding head is configured to move ...

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Номер записи: 54
15-09-2022 дата публикации

Notched wafer and bonding support structure to improve wafer stacking

Номер: US20220293556A1
Автор: Cheng-Hsien Chou, Cheng-Yuan Tsai, Sheng-Chan Li, Sheng-Chau Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method comprises forming a plurality of semiconductor devices over a central region of a semiconductor wafer. The semiconductor wafer comprises a peripheral region laterally surrounding the central region and a circumferential edge disposed within the peripheral region. The semiconductor wafer comprises a notch disposed along the circumferential edge. Forming a stack of inter-level dielectric (ILD) layers over the semiconductor devices and laterally within the central region. Forming a bonding support structure over the peripheral region such that the bonding support structure comprises a bonding structure notch disposed along a circumferential edge of the bonding support structure. Forming the bonding support structure includes disposing the semiconductor wafer over a lower plasma exclusion zone (PEZ) ring that comprises a PEZ ring notch disposed along a circumferential edge of the lower PEZ ring.

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Номер записи: 55
16-05-2019 дата публикации

CLIP FOR SEMICONDUCTOR PACKAGE

Номер: US20190148263A1
Автор: TAN Ariel Sotomayor
Принадлежит: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Implementations of a clip may include a die attach portion including at least one protrusion extending from the die attach portion and a lead frame alignment portion including at least one alignment feature. The at least one alignment feature may be configured to couple into at least one hole in a lead frame thereby aligning the clip with the lead frame. The at least one protrusion may be configured to couple into at least one recess in the die. 1. A clip comprising:a die attach portion comprising at least one protrusion extending from the die attach portion; anda lead frame alignment portion comprising at least one alignment feature;wherein the at least one protrusion is configured to couple into at least one recess in the die.2. The clip of claim 1 , wherein the die attach portion comprises four protrusions extending from the die attach portion.3. The clip of claim 1 , wherein the lead frame alignment portion comprises two alignment features.4. The clip of claim 1 , wherein a section of the lead frame alignment portion extends in a first direction substantially perpendicular away from the die attach portion claim 1 , in a second direction substantially parallel away from the die attach portion claim 1 , and in a third direction parallel to the first direction.5. The clip of claim 1 , wherein the alignment feature does not cross a plane formed by the die attach portion.6. The clip of claim 1 , further comprising a plurality of bond features configured to ensure a minimum bonding compound thickness.7. A clip comprising:a die attach portion configured to directly couple within a recess comprised in a die; anda lead frame alignment portion configured to directly couple to a lead frame;wherein the lead frame alignment portion is configured to fixedly couple the clip to the lead frame in a desired physical arrangement; andwherein the die attach portion is configured to fixedly couple the clip to the die in a desired physical arrangement.8. The package of claim 7 , ...

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Номер записи: 56
16-05-2019 дата публикации

METHOD FOR BONDING WAFERS AND BONDING TOOL

Номер: US20190148333A1
Автор: Chen Chien-Chih, Chen Tzu-Shin, CHENG Mu-Han, HUNG Chung-I, YANG TSUNG-YI, YEH Su-Yu
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A method is provided and includes the following steps. A first wafer is coupled to a first support of a bonding tool and a second wafer is coupled to a second support of the bonding tool. The second wafer is bonded to the first wafer with the first wafer coupled to the first support. Whether a bubble is between the bonded first and second wafers in the bonding tool is detected. 1. A method comprising:coupling a first wafer to a first support of a bonding tool and coupling a second wafer to a second support of the bonding tool;bonding the second wafer to the first wafer with the first wafer coupled to the first support; anddetecting whether a bubble is between the bonded first and second wafers in the bonding tool, wherein detecting whether a bubble is between the bonded first and second wafers is in a same chamber of the bonding tool as bonding the second wafer to the first wafer.2. The method of claim 1 , wherein the detecting comprises performing an optical detection.3. The method of claim 1 , wherein the detecting is performed by Fourier transform infrared microscopy (FTIR) claim 1 , xray reflection (XRR) claim 1 , nuclear reaction analysis (NRA) claim 1 , or combinations thereof.4. The method of claim 1 , further comprising:cleaning a chamber of the bonding tool accommodating the first and second supports when the bubble is detected between the bonded first and second wafers.5. The method of claim 4 , wherein loading of a third wafer is deferred until the cleaning completes.6. The method of claim 1 , wherein the detecting comprises capturing an image of the bonded first and second wafers by an infrared camera.7. The method of claim 1 , wherein the bonding comprises:releasing the second wafer from the second support such that the second wafer is bonded to the first wafer, wherein the detecting is performed after the releasing.8. The method of claim 1 , wherein the detecting is performed with the bonded first and second wafers coupled to the first support.9. The ...

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Номер записи: 57
22-09-2022 дата публикации

System and Method for Bonding Semiconductor Devices

Номер: US20220302078A1
Автор: Chang Kai-Tai, Lee Tung Ying
Принадлежит:

A method includes determining a first offset between a first alignment mark on a first side of a first wafer and a second alignment mark on a second side of the first wafer; aligning the first alignment mark of the first wafer to a third alignment mark on a first side of a second wafer, which includes detecting a location of the second alignment mark of the first wafer; determining a location of the first alignment mark of the first wafer based on the first offset and the location of the second alignment mark of the first wafer; and, based on the determined location of the first alignment mark, repositioning the first wafer to align the first alignment mark to the third alignment mark; and bonding the first side of the first wafer to the first side of the second wafer to form a bonded structure. 1. A method , comprising:determining a first offset between a first alignment mark on a first side of a first wafer and a second alignment mark on a second side of the first wafer; detecting a location of the second alignment mark of the first wafer;', 'determining a location of the first alignment mark of the first wafer based on the first offset and the location of the second alignment mark of the first wafer; and', 'based on the determined location of the first alignment mark, repositioning the first wafer to align the first alignment mark to the third alignment mark; and, 'aligning the first alignment mark of the first wafer to a third alignment mark on a first side of a second wafer, comprisingbonding the first side of the first wafer to the first side of the second wafer to form a bonded structure.2. The method of further comprising determining a second offset between the third alignment mark on the first side of the second wafer and a fourth alignment mark on a second side of the second wafer.3. The method of claim 2 , wherein repositioning the first wafer to align the first alignment mark to the third alignment mark comprises:detecting a location of the fourth ...

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Номер записи: 58
23-05-2019 дата публикации

HYBRID BONDED STRUCTURE

Номер: US20190157333A1
Автор: TSAI Bo-Tsung
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A hybrid bonded structure including a first integrated circuit component and a second integrated circuit component is provided. The first integrated circuit component includes a first dielectric layer, first conductors and isolation structures. The first conductors and the isolation structures are embedded in the first dielectric layer. The isolation structures are electrically insulated from the first conductors and surround the first conductors. The second integrated circuit component includes a second dielectric layer and second conductors. The second conductors are embedded in the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer and the first conductors are bonded to the second conductors. 1. A method of fabricating a hybrid bonded structure , comprising:providing a first integrated circuit component comprising a first semiconductor substrate having a plurality of first semiconductor devices therein, a first interconnection structure disposed on the first semiconductor substrate, a first dielectric layer covering the first interconnection structure and at least one first conductor group, the at least one first conductor group comprising a plurality of first conductors electrically connected to one another through the first interconnection structure;providing a second integrated circuit component comprising a second semiconductor substrate having a plurality of second semiconductor devices therein, a second interconnection structure disposed on the second semiconductor substrate, a second dielectric layer covering the second interconnection structure and at least one second conductor group, the at least one second conductor group comprising a plurality of second conductors electrically connected to one another through the second interconnection structure; andperforming a hybrid bonding process to bond the first integrated circuit component and the second integrated component such that the first dielectric layer is ...

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Номер записи: 59
24-06-2021 дата публикации

3D SEMICONDUCTOR DEVICE AND STRUCTURE

Номер: US20210193626A1
Автор: OR-BACH Zvi
Принадлежит: MonolithIC 3D Inc.

A 3D semiconductor device, the device including: a first die including first transistors and a first interconnect; a second die including second transistors and a second interconnect; and a third die including third transistors and a third interconnect, where the first die is overlaid by the second die, where the first die is overlaid by the third die, where the first die has a first die area and the second die has a second die area, where the first die area is at least 20% larger than the second die area, where the second die is pretested, where the second die is bonded to the first die, where the bonded includes metal to metal bonding, where the first die includes at least two first alignment marks positioned close to a first die edge of the first die, and where the third die is bonded to the first die. 1. A 3D semiconductor device , the device comprising:a first die comprising first transistors and a first interconnect;a second die comprising second transistors and a second interconnect; and wherein said first die is overlaid by said second die,', 'wherein said first die is overlaid by said third die,', 'wherein said first die has a first die area and said second die has a second die area,', 'wherein said first die area is at least 20% larger than said second die area,', 'wherein said second die is pretested,', 'wherein said second die is bonded to said first die,', 'wherein said bonded comprises metal to metal bonding,', 'wherein said first die comprises at least two first alignment marks positioned close to a first die edge of said first die, and', 'wherein said third die is bonded to said first die., 'a third die comprising third transistors and a third interconnect,'}2. The 3D semiconductor device according to claim 1 ,wherein said second die is aligned to said first die with less than 800 nm alignment error.3. The 3D semiconductor device according to claim 1 ,wherein said bonded comprises hybrid bonding.4. The 3D semiconductor device according to claim 1 , ...

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Номер записи: 60
30-05-2019 дата публикации

Semiconductor Device and Method of Manufacturing

Номер: US20190164919A1
Автор: Chen Ming-Fa, Hu Chih-Chia, Jan Sen-Bor, Yeh Sung-Feng, Yuan Ching-Pin
Принадлежит:

A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads. 1. A semiconductor device , comprising: a first passivation layer disposed on a first substrate; and', 'first bond pads disposed in the first passivation layer; and, 'a first die, comprising a second passivation layer, the second passivation layer being bonded to the first passivation layer; and', 'second bond pads disposed in the second passivation layer, each of the second bond pads being bonded to one of the first bond pads, the second bond pads comprising inner bond pads and outer bond pads, the outer bond pads having a greater diameter than the inner bond pads., 'a second die, comprising2. The semiconductor device of further comprising third bond pads disposed in the second passivation layer claim 1 , wherein the third bond pads are closer than the outer bond pads to an outer edge of the second passivation layer claim 1 , and wherein the third bond pads have a greater diameter than the outer bond pads.3. The semiconductor device of claim 1 , wherein:a center of one of the first bond pads is located a first distance from a center of the first passivation layer, the one of the first bond pads having a first diameter;a center of one of the second bond pads is located a second distance from a center of the second passivation layer, the one of the second bond pads being bonded to the one of the first bond pads, the one of the second bond pads having a second diameter; andthe second distance being ...

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Номер записи: 61
29-09-2022 дата публикации

Semiconductor device with redistribution structure and method for fabricating the same

Номер: US20220310545A1
Автор: Shing-Yih Shih
Принадлежит: Nanya Technology Corp

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure including a first substrate, and a first circuit layer positioned on the first substrate, a first redistribution structure positioned on the first circuit layer, and a second semiconductor structure including a second circuit layer positioned on the first redistribution structure, and a second substrate positioned on the second circuit layer. A layout of the first circuit layer and a layout of the second circuit layer are substantially the same and the first redistribution structure is electrically coupled to the first semiconductor structure and the second semiconductor structure.

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Номер записи: 62
29-09-2022 дата публикации

Bonding to Alignment marks with Dummy Alignment Marks

Номер: US20220310554A1
Автор: Chen Hsien-Wei, Chen Ming-Fa, CHEN Ying-Ju
Принадлежит:

A method includes placing a first package component. The first package component includes a first alignment mark and a first dummy alignment mark. A second package component is aligned to the first package component. The second package component includes a second alignment mark and a second dummy alignment mark. The aligning is performed using the first alignment mark for positioning the first package component, and using the second alignment mark for position the second package component. The second package component is bonded to the first package component to form a package, with the first alignment mark being bonded to the second dummy alignment mark. 1. A method comprising: a first alignment mark; and', 'a first dummy alignment mark;, 'placing a first package component, wherein the first package component comprises a second alignment mark; and', 'a second dummy alignment mark, wherein the aligning is performed using the first alignment mark for positioning the first package component, and using the second alignment mark for position the second package component; and, 'aligning a second package component to the first package component, wherein the second package component comprisesbonding the second package component to the first package component to form a package, wherein after the bonding, the first alignment mark is bonded to the second dummy alignment mark.2. The method of claim 1 , wherein the first alignment mark comprises a first plurality of discrete features claim 1 , the second dummy alignment mark comprises a second plurality of discrete features claim 1 , and wherein the first plurality of discrete features are bonded to the second plurality of discrete features with a one-to-one correspondence.3. The method of claim 1 , wherein after the bonding claim 1 , the second alignment mark is bonded to the first dummy alignment mark.4. The method of claim 1 , wherein the first alignment mark comprises a first plurality of discrete features claim 1 , the ...

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Номер записи: 63
29-09-2022 дата публикации

SEMICONDUCTOR DEVICE WITH THROUGH SEMICONDUCTOR VIA AND METHOD FOR FABRICATING THE SAME

Номер: US20220310580A1
Автор: CHIU Hsih-Yang
Принадлежит:

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure, a second semiconductor structure, a through semiconductor via, and an insulation layer. The first semiconductor structure includes a first circuit layer and a first main bonding layer in the first circuit layer and substantially coplanar with a front face of the first circuit layer. The second semiconductor structure includes a second circuit layer on the first circuit layer and a second main bonding layer in the second circuit layer, and topologically aligned with and contacted to the first main bonding layer. The through semiconductor via is along the second semiconductor structure and the first and second main bonding layer, and extending to the first circuit layer. The insulation layer is positioned on a sidewall of the through semiconductor via. 1. A semiconductor device , comprising:a first semiconductor structure comprising a first circuit layer positioned on a first substrate, and a first main bonding layer positioned in the first circuit layer and substantially coplanar with a front face of the first circuit layer;a second semiconductor structure comprising a second circuit layer positioned on the first circuit layer, a second substrate positioned on the second circuit layer, and a second main bonding layer positioned in the second circuit layer, and topologically aligned with and contacted to the first main bonding layer;a through semiconductor via positioned along the second semiconductor structure and the first main bonding layer, extending to the first circuit layer, and physically and electrically coupled to a corresponding conductive line in the first circuit layer; andan insulation layer positioned between the second semiconductor structure and the through semiconductor via, between the first main bonding layer and the through semiconductor via, and between the first circuit ...

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Номер записи: 64
30-07-2015 дата публикации

ASSEMBLY BONDING

Номер: US20150212340A1
Автор: Etzkorn James
Принадлежит:

A contact lens having a thin silicon chip integrated therein is provided along with methods for assembling the silicon chip within the contact lens. In an aspect, a method includes creating a plurality of lens contact pads on a lens substrate and creating a plurality of chip contact pads on a chip. The method further involves applying assembly bonding material to the each of the plurality of lens contact pads or chip contact pads, aligning the plurality of lens contact pads with the plurality of chip contact pads, bonding the chip to the lens substrate via the assembly bonding material using flip chip bonding, and forming a contact lens with the lens substrate. 125-. (canceled)26. A method for manufacturing a device having an integrated circuit , comprising:creating a plurality of chip contact pads on a chip by forming a grid of metal lines on a surface of the chip, wherein the chip contact pads correspond to intersection points of the metal lines in the grid;applying assembly bonding material to each of a plurality of substrate contact pads formed on a substrate; andbonding the plurality of chip contact pads to the plurality of substrate contact pads via the assembly bonding material to bond the chip to the substrate.27. The method of claim 26 , wherein forming the grid of metal lines comprises forming the grid of metal lines using photolithography.28. The method of claim 26 , further comprising sealing the chip on the substrate.29. The method of claim 26 , wherein the chip has a thickness of about 100 microns or less and a length of about 1.0 millimeter or less.30. The method of claim 26 , wherein the assembly bonding material includes an isotropic conductive material.31. The method of claim 26 , wherein the substrate comprises a polymer material.32. The method of claim 26 , wherein the bonding is performed employing a flip-chip bonder.33. A device having an integrated circuit disposed thereon or therein formed by a process comprising:creating a plurality of chip ...

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Номер записи: 65
26-07-2018 дата публикации

STACKED SEMICONDUCTOR DEVICE

Номер: US20180211701A1
Автор: Ware Frederick A.
Принадлежит:

A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies. 1. (canceled)2. A semiconductor device , comprising:an end die formed with an end contact, the end die configured to be disposed at one end of a vertical die stack;a first die formed with a first contact, the first die stacked vertically with the end die such that the first contact is disposed in vertical alignment with the end contact, the first die including first input/output (I/O) circuitry selectively coupled to the first contact;a second die formed with a second contact, the second die stacked vertically with the end die and the first die such that the second contact is disposed in vertical alignment with the first contact and the end contact, the second die including second I/O circuitry selectively coupled to the second contact;a through-silicon via path formed to electrically couple the end contact to the first contact and the second contact; andwherein solely one of the first I/O circuitry or the second I/O circuitry is connected to the corresponding first contact or second contact to form a point-to-point signal path with the end contact.3. The semiconductor device according to claim 2 , wherein the end contact claim 2 , the first contact claim 2 , and the second ...

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Номер записи: 66
02-08-2018 дата публикации

METHOD FOR DIRECT BONDING WITH SELF-ALIGNMENT USING ULTRASOUND

Номер: US20180218997A1
Автор: Baillin Xavier, Cheramy Séverine, Fournel Frank, Leduc Patrick, Sanchez Loïc
Принадлежит: Commissariat A L'Energie Atomique Et Aux Energies Alternatives

A method for direct bonding an electronic chip onto a substrate or another electronic chip, the method including: carrying out a hydrophilic treatment of a portion of, a surface of the electronic chip and of a portion of a surface of the substrate or of the other electronic chip; depositing an aqueous fluid on the portion of the surface of the substrate or of the second electronic chip; depositing the portion of the surface of the electronic chip on the aqueous fluid; drying the aqueous fluid until the portion of the surface of the electronic chip is rigidly connected to the portion of the surface of the substrate or of the other electronic chip: and during at least part of the drying of the aqueous fluid, emitting ultrasound into the aqueous fluid through the substrate or the other electronic chip. 111-. (canceled)12: A method for directly bonding at least one first electronic chip to a substrate or to at least one second electronic chip , comprising:making, on each of a face of the first electronic chip and a first face of the substrate or of the second electronic chip, at least one first and one second part having a contact angle difference towards a first fluid which is higher than about 70° with respect to each other, such that the first parts have contact angles towards the first fluid lower than those of the second parts and have shapes and dimensions substantially similar with respect to each other, and such that, on each of the face of the first electronic chip and the first face of the substrate or of the second electronic chip, the first part is delimited by the second part;depositing the first fluid onto the first part of the first face of the substrate or of the second electronic chip;depositing the first part of the face of the first electronic chip onto the first fluid;removing the first fluid until a securement of the first part of the face of the first electronic chip with the first part of the first face of the substrate or of the second electronic ...

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Номер записи: 67
09-08-2018 дата публикации

CONDUCTIVE BARRIER DIRECT HYBRID BONDING

Номер: US20180226371A1
Автор: ENQUIST Paul M.
Принадлежит:

A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region. 1. A structure , comprising: a dielectric layer,', 'conductive contact structures, and', 'a first conductive barrier material layer formed directly on an upper surface of each of said conductive contact structures,, 'a direct hybrid bond surface comprisingwherein an upper surface of said conductive barrier layer is recessed about one to ten nm below an upper surface of said dielectric layer.2. The structure according to claim 1 , comprising a top surface of said conductive contact structures being below said upper surface by about 5-40 nm.3. The structure according to claim 1 , comprising a second layer of conductive barrier material on a bottom and sides of said metal contact structures.4. The structure according to claim 1 , wherein said first and second layers of conductive barrier material completely surrounding said conductive contact structures.5. A bonded structure claim 1 , comprising: a dielectric layer,', 'conductive contact structures, and', 'a first conductive barrier material layer formed directly on an upper surface of each of said conductive contact structures, wherein, 'first and second direct hybrid bond ...

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Номер записи: 68
09-08-2018 дата публикации

METHOD OF MANUFACTURING SUBSTRATE STRUCTURE

Номер: US20180226390A1
Автор: KANG Pil Kyu, KIM Seok Ho, KIM Tae Yeong, LEE Ho Jin, Moon Kwang Jin
Принадлежит:

A method of manufacturing a substrate structure includes providing a first substrate including a first device region on a first surface, providing a second substrate including a second device region on a second surface, such that a width of the first device region is greater than a width of the second device region, and bonding the first substrate and the second substrate, such that the first and second device regions are facing each other and are electrically connected to each other. 1. A method of manufacturing a substrate structure , the method comprising:providing a first substrate including a first surface and a second surface, facing each other, and a first device region formed on the first surface;providing a second substrate including a third surface and a fourth surface, facing each other, and a second device region formed on the third surface;bonding the first substrate and the second substrate to electrically connect the first device region and the second device region; andreducing a thickness of the second substrate, after bonding the first and second substrates,wherein a width of the first device region is greater than a width of the second device region in a state where the first substrate is bonded with the second substrate whose thickness is reduced.2. The method as claimed in claim 1 , wherein bonding the first substrate and the second substrate includes directly bonding the first substrate and the second substrate.3. The method as claimed in claim 2 , wherein directly bonding the first substrate and the second substrate includes:disposing the first substrate and the second substrate such that the first surface of the first substrate faces the third surface of the second substrate; andbonding the first device region and the second device region.4. The method as claimed in claim 2 , wherein directly bonding the first substrate and the second substrate includes:disposing the first substrate and the second substrate such that the second surface of the ...

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Номер записи: 69
09-07-2020 дата публикации

SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS

Номер: US20200219924A1
Автор: Hayashi Toshihiko
Принадлежит:

Disclosed herein is a solid-state imaging device including: a laminated semiconductor chip configured to be obtained by bonding two or more semiconductor chip sections to each other and be obtained by bonding at least a first semiconductor chip section in which a pixel array and a multilayer wiring layer are formed and a second semiconductor chip section in which a logic circuit and a multilayer wiring layer are formed to each other in such a manner that the multilayer wiring layers are opposed to each other and are electrically connected to each other; and a light blocking layer configured to be formed by an electrically-conductive film of the same layer as a layer of a connected interconnect of one or both of the first and second semiconductor chip sections near bonding between the first and second semiconductor chip sections. The solid-state imaging device is a back-illuminated solid-state imaging device. 1. A solid-state imaging device comprising:a first semiconductor substrate including a plurality of pixels and a first multilayer wiring layer, the first multilayer wiring layer including a first connecting interconnect and a first plurality of electrically-conductive components disposed in a same layer as the first connecting interconnect; anda second semiconductor substrate including a logic circuit and a second multilayer wiring layer, the second multilayer wiring layer including a second connecting interconnect and a second plurality of electrically-conductive components disposed in a same layer as the second connecting interconnect, whereinthe first semiconductor substrate and the second semiconductor substrate are bonded such that the first multilayer wiring layer and the second multilayer wiring layer face each other at a bonding surface between the first semiconductor substrate and the second semiconductor substrate,the first plurality of electrically-conductive components are strip-shaped, extend in a first direction, have a first width in a second ...

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Номер записи: 70
19-08-2021 дата публикации

SEMICONDUCTOR STRUCTURE

Номер: US20210257340A1
Автор: Chen Hsien-Wei, Chen Jie, Chen Ming-Fa, Yang Ching-Jung
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor structure includes: a first die, comprising a first interconnect structure and a first active pad electrically connected to the first interconnect structure; a first bonding dielectric layer over the first die; a first active bonding via in the first bonding dielectric layer, electrically connected to the first interconnect structure; and a plurality of first dummy bonding vias in the first bonding dielectric layer, wherein the first dummy bonding vias laterally surround the first active bonding via and are electrically floating. 1. A semiconductor structure , comprising:a first die, comprising a first interconnect structure and a first active pad electrically connected to the first interconnect structure;a first bonding dielectric layer over the first die;a first active bonding via in the first bonding dielectric layer, electrically connected to the first interconnect structure; anda plurality of first dummy bonding vias in the first bonding dielectric layer, wherein the first dummy bonding vias laterally surround the first active bonding via and are electrically floating.2. The semiconductor structure according to claim 1 , wherein the first active bonding via is electrically connected to the first active pad.3. The semiconductor structure according to claim 1 , wherein the first active bonding via is electrically isolated from the first active pad.4. The semiconductor structure according to claim 1 , wherein at least one of the the first dummy bonding vias is disposed between the first active bonding via and the first active pad.5. The semiconductor structure according to claim 1 , wherein a width of the first active bonding via is larger than a width of the first dummy bonding vias.6. The semiconductor structure according to claim 1 , wherein a first surface of the first active bonding via is substantially coplanar with first surfaces of the first dummy bonding vias claim 1 , and a second surface opposite to the first surface of the first active ...

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Номер записи: 71
16-08-2018 дата публикации

DEVICE INCLUDING SEMICONDUCTOR CHIPS AND METHOD FOR PRODUCING SUCH DEVICE

Номер: US20180233469A1
Автор: Palm Petteri, Scharf Thorsten
Принадлежит: INFINEON TECHNOLOGIES AG

A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip. 1. A device , comprising:a first semiconductor chip comprising a first face, wherein a first contact pad is arranged over the first face of the first semiconductor chip;a second semiconductor chip comprising a first face, wherein a first contact pad is arranged over the first face of the second semiconductor chip; anda third semiconductor chip comprising a first face, wherein a first contact pad is arranged over the first face of the third semiconductor chip,wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction, and where the first face of the third semiconductor chip faces in the first direction or the second direction,wherein the first semiconductor chip is located laterally outside of an outline of the second semiconductor chip and the third semiconductor chip.2. The device of claim 1 , wherein the first face of the first semiconductor chip and a second face of the second semiconductor chip claim 1 , opposite to the first face of the second semiconductor chip claim 1 , are arranged on different heights relative to a major surface of the device.3. The device of claim 1 , wherein at least one of ...

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Номер записи: 72
16-07-2020 дата публикации

METHOD FOR ALIGNMENT, PROCESS TOOL AND METHOD FOR WAFER-LEVEL ALIGNMENT

Номер: US20200227298A1
Автор: Lin Yeong-Jyh, Liu Ping-Yin, Tu Yeur-Luen, Wang Ching-Hung
Принадлежит:

Various embodiments of the present application are directed towards a method for workpiece-level alignment with low alignment error and high throughput. In some embodiments, the method comprises aligning a first alignment mark on a first workpiece to a field of view (FOV) of an imaging device based on feedback from the imaging device, and further aligning a second alignment mark on a second workpiece to the first alignment mark based on feedback from the imaging device. The second workpiece is outside the FOV during the aligning of the first alignment mark. The aligning of the second alignment mark is performed without moving the first alignment mark out of the FOV. Further, the imaging device views the second alignment mark, and further views the first alignment mark through the second workpiece, during the aligning of the second alignment mark. The imaging device may, for example, perform imaging with reflected infrared radiation. 1. A method for alignment comprising:aligning a first alignment mark on a first workpiece to a field of view (FOV) of an imaging device based on feedback from the imaging device and while a second workpiece is outside the FOV, wherein the aligning of the first alignment mark is performed without moving the imaging device laterally towards the first alignment mark; andaligning a second alignment mark on the second workpiece to the first alignment mark based on feedback from the imaging device and without moving the first alignment mark out of alignment with the FOV, wherein the aligning of the second alignment mark comprises imaging the first alignment mark through the second workpiece using the imaging device.2. The method according to claim 1 , wherein the imaging device is fixed during the aligning of the first alignment mark.3. The method according to claim 1 , wherein the FOV is stationary during the aligning of the first alignment mark.4. The method according to claim 1 , wherein the aligning of the first alignment mark comprises ...

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Номер записи: 73
25-08-2016 дата публикации

Chip-on-wafer package and method of forming same

Номер: US20160247779A1
Автор: Chen-Hua Yu, Ming-Fa Chen, Sung-Feng Yeh
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A package according to an embodiment includes a first device package and a fan-out RDL disposed over the first device package. The fan-out RDL extends past edges of the first device package. The first device package comprises a first die having a first redistribution layer (RDL) disposed on a first substrate, a second die having a second RDL disposed on a second substrate, an isolation material over the first die and extending along sidewalls of the second die, and a conductive via. The first RDL is bonded to the second RDL, and the first die and the second die comprise different lateral dimensions. At least a portion of the conductive via extends from a top surface of the isolation material to contact a first conductive element in the first RDL.

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Номер записи: 74
10-09-2015 дата публикации

DIE-TO-DIE BONDING AND ASSOCIATED PACKAGE CONFIGURATIONS

Номер: US20150255411A1
Автор: Alur Amruthavalli P., Karhade Omkar G., Mahajan Ravindranath V., Mallik Debendra
Принадлежит:

Embodiments of the present disclosure are directed towards die-to-die bonding and associated integrated circuit (IC) package configurations. In one embodiment, a package assembly includes a package substrate having a solder resist layer disposed on a first side and a second side disposed opposite to the first side, a first die mounted on the first side and having an active side that is electrically coupled with the package substrate by one or more first die-level interconnects and a second die bonded with the active side of the first die using one or more second die-level interconnects, wherein at least a portion of the second die is disposed in a cavity that extends into the solder resist layer. Other embodiments may be described and/or claimed. 1. A package assembly comprising:a package substrate having a solder resist layer disposed on a first side and a second side disposed opposite to the first side;a first die mounted on the first side and having an active side that is electrically coupled with the package substrate by one or more first die-level interconnects; anda second die bonded with the active side of the first die using one or more second die-level interconnects, wherein at least a portion of the second die is disposed in a cavity that extends into the solder resist layer.2. The package assembly of claim 1 , wherein:the cavity extends into a laminate layer of the package substrate that is disposed beneath the solder resist layer; andat least a portion of the second die is disposed in a portion of the cavity that extends into the laminate layer.3. The package assembly of claim 1 , further comprising:a third die mounted on the first side of the package substrate and having an active side that is electrically coupled with the package substrate by one or more third die-level interconnects, wherein the second die is bonded with the active side of the third die by one or more fourth die-level interconnects.4. The package assembly of claim 3 , wherein the ...

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Номер записи: 75
10-09-2015 дата публикации

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, AND POSITIONING JIG

Номер: US20150255444A1
Автор: SATO Kenichiro
Принадлежит: FUJI ELECTRIC CO., LTD.

A semiconductor device has a plurality of small-sized semiconductor chips disposed between an insulated circuit board having a conductive pattern and a terminal. The semiconductor device exhibits a high accuracy in positioning the semiconductor chips. The semiconductor device includes an insulated circuit board having a conductive pattern, a first semiconductor chip with a rectangular shape connected to the conductive pattern through a first joining material, a second semiconductor chip with a rectangular shape, disposed on the conductive pattern separated from the first semiconductor chip and connected to the conductive pattern through a second joining material, and a terminal disposed above the first semiconductor chip and the second semiconductor chip, connected to the first semiconductor chip through a third joining material, and connected to the second semiconductor chip through a fourth joining material. The terminal has a through-hole above a place between the first semiconductor chip and the second semiconductor chip. 1. A semiconductor device comprising:an insulated circuit board having a conductive pattern;a first semiconductor chip with a rectangular shape connected through a first joining material to the conductive pattern;a second semiconductor chip with a rectangular shape disposed on the conductive pattern separated from the first semiconductor chip and connected through a second joining material to the conductive pattern;a terminal disposed above the first semiconductor chip and the second semiconductor chip, connected to the first semiconductor chip through a third joining material, and connected to the second semiconductor chip through a fourth joining material, the terminal having a through-hole above a place between the first semiconductor chip and the second semiconductor chip.2. The semiconductor device according to claim 1 , wherein a gap between a side of the first semiconductor chip and a side of the second semiconductor chip claim 1 , the ...

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Номер записи: 76
01-08-2019 дата публикации

CONDUCTIVE BARRIER DIRECT HYBRID BONDING

Номер: US20190237419A1
Автор: ENQUIST Paul M.
Принадлежит:

A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region. 1. (canceled)2. A bonded structure , comprising: a first dielectric layer, and', 'a first conductive contact structure;, 'a first element comprising a second dielectric layer, and', 'a second conductive contact structure; and, 'a second element directly bonded to the first element, the second element comprisinga conductive barrier material layer having a first portion disposed between the first and second conductive contact structures, the first portion of the conductive barrier material layer in direct contact with at least one of an upper surface of the first conductive contact structure and an upper surface of the second conductive contact structure.3. The structure according to claim 2 , wherein the first dielectric layer and the second dielectric layer are directly bonded without an intervening adhesive.4. The structure according to claim 2 , wherein the second element further comprises a third conductive contact structure spaced laterally from the second conductive contact structure by the second dielectric layer.5. The structure according to claim 4 , wherein the conductive barrier material layer further has a second ...

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Номер записи: 77
23-07-2020 дата публикации

THREE-DIMENSIONAL INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME

Номер: US20200235063A1
Автор: CHEN Chun-Hung, Lin Ming-Tse
Принадлежит: UNITED MICROELECTRONICS CORP.

Provided are a three-dimensional integrated circuit (3DIC) and a method of manufacturing the same. The 3DIC includes a first wafer, a second wafer, and a hybrid bonding structure. The second wafer is bonded to the first wafer by the hybrid bonding structure. The hybrid bonding structure includes a blocking layer between a hybrid bonding dielectric layer and a hybrid bonding metal layer. 1. A three-dimensional integrated circuit (3DIC) , comprising:a first wafer; anda second wafer, bonded to the first wafer by a hybrid bonding structure, wherein the hybrid bonding structure comprises a blocking layer disposed between a hybrid bonding dielectric layer and a hybrid bonding metal layer.2. The 3DIC of claim 1 , wherein a material of the blocking layer is from the hybrid bonding dielectric layer and the hybrid bonding metal layer claim 1 , and the blocking layer is in direct contact with the hybrid bonding dielectric layer and the hybrid bonding metal layer.3. The 3DIC of claim 1 , wherein the blocking layer comprises manganese oxide (MnO) claim 1 , manganese silicate (MnSiO) claim 1 , manganese oxynitride (MnON) claim 1 , cobalt oxide (CoO) claim 1 , or a combination thereof.4. The 3DIC of claim 1 , wherein a thickness of the blocking layer is between 0.5 nm and 1.0 nm.5. The 3DIC of claim 1 , wherein the hybrid bonding structure comprises:a first portion, comprising a first bonding metal layer and a second bonding metal layer bonding to each other;a second portion, comprising a first bonding dielectric layer and a second bonding dielectric layer bonding to each other; anda third portion, comprising the first bonding metal layer and the second bonding dielectric layer bonding to each other, the first bonding dielectric layer and the second bonding metal layer bonding to each other, and the blocking layer disposed between the first bonding metal layer and the second bonding dielectric layer and disposed between the first bonding dielectric layer and the second bonding ...

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Номер записи: 78
09-09-2021 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20210280561A1
Автор: Watanabe Takashi
Принадлежит: Kioxia Corporation

A semiconductor device according to the present embodiment includes a first chip and a second chip. A first pad is disposed so as to be exposed from a first region on a first surface. A first mark is provided by a first pattern and is disposed so as to be exposed from a second region. The second chip includes a second substrate, a second wire, a second pad, and a second mark. The second wire is disposed on the second substrate. The second pad is disposed so as to be exposed from a third region on a second surface, and is electrically connected to the second wire and the first pad. The second mark is provided by a second pattern corresponding to the first pattern, is disposed so as to be exposed from a fourth region, and has a thinner thickness than the second pad. 1. A semiconductor device comprising:a first chip; anda second chip having a second surface on which the second chip is bonded to the first chip, the second surface being opposed to a first surface of the first chip, wherein a first substrate,', 'a first wire that is disposed on the first substrate,', 'a first pad that is disposed so as to be exposed from a first region on the first surface and that is electrically connected to the first wire, and, 'the first chip includes'}a first mark that is provided by a first pattern and that is disposed so as to be exposed from a second region which is different from the first region, and a second substrate,', 'a second wire that is disposed on the second substrate,', 'a second pad that is disposed so as to be exposed from a third region on the second surface and that is electrically connected to the second wire and the first pad, and', 'a second mark that is provided by a second pattern corresponding to the first pattern, that is disposed so as to be exposed from a fourth region which is different from the third region, and that has a thinner thickness than the second pad., 'the second chip includes'}2. The semiconductor device according to claim 1 , whereina width ...

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Номер записи: 79
30-08-2018 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20180247913A1
Автор: CHIU Ying-Ta, CHIU Yong-Da, HUANG Shang-Kun, SONG Jenn-Ming
Принадлежит:

The present disclosure relates to a method for manufacturing a semiconductor device. The method includes providing a first electronic component including a first metal contact and a second electronic component including a second metal contact, changing a lattice of the first metal contact, and bonding the first metal contact to the second metal contact under a predetermined pressure and a predetermined temperature. 1. A method for manufacturing a semiconductor device , comprising:providing a first electronic component including a first metal contact and a second electronic component including a second metal contact;irradiating an electromagnetic radiation on the first metal contact to change a lattice of the first metal contact; andbonding the first metal contact to the second metal contact under a pressure and a temperature.2. (canceled)3. The method of claim 1 , wherein a wavelength of the electromagnetic radiation is in a range from about 200 nanometers (nm) to about 3000 nm.4. The method of claim 3 , wherein the wavelength of the electromagnetic radiation is in a range from about 700 nm to about 1100 nm.5. The method of claim 3 , wherein the wavelength of the electromagnetic radiation is in a range from about 200 nm to about 400 nm.6. The method of claim 1 , wherein the first metal contact is irradiated by the electromagnetic radiation for less than about 15 seconds.7. The method of claim 6 , wherein the first metal contact is irradiated by the electromagnetic radiation for a time period in a range from about 5 seconds to about 10 seconds.8. The method of claim 1 , wherein the electromagnetic radiation is incident on a surface of the first metal contact to be contacted by the second metal contact.9. The method of claim 1 , further comprising changing a lattice of the second metal contact.10. The method of claim 9 , further comprising claim 9 , prior to bonding the first metal contact to the second metal contact:de-oxidizing the first metal contact and the second ...

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Номер записи: 80
06-09-2018 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Номер: US20180254267A1
Автор: SATO Kenichiro
Принадлежит: FUJI ELECTRIC CO., LTD.

A method of manufacturing a semiconductor device that includes an insulated circuit board having a conductive pattern, a first semiconductor chip with a rectangular shape connected through a first joining material to the conductive pattern, a second semiconductor chip with a rectangular shape disposed on the conductive pattern separated from the first semiconductor chip and connected through a second joining material to the conductive pattern, a terminal disposed above the semiconductor chips, respectively connected to the first and second semiconductor chips through third and fourth joining materials, the terminal having a through-hole above a place between the first and second semiconductor chips, the method including a positioning step in which the first and second semiconductor chips are respectively positioned at at least three positioning places, and at least one of the positioning places is positioned with a positioning member inserted into the through-hole. 1. A method of manufacturing a semiconductor device that comprises: an insulated circuit board having a conductive pattern; a first semiconductor chip with a rectangular shape connected through a first joining material to the conductive pattern; a second semiconductor chip with a rectangular shape disposed on the conductive pattern separated from the first semiconductor chip and connected through a second joining material to the conductive pattern; a terminal disposed above the first semiconductor chip and the second semiconductor chip , connected to the first semiconductor chip through a third joining material , and connected to the second semiconductor chip through a fourth joining material; the terminal having a through-hole above a place between the first semiconductor chip and the second semiconductor chip ,the method comprising a positioning step in whichthe first semiconductor chip is positioned at at least three positioning places,the second semiconductor chip is positioned at at least three ...

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Номер записи: 81
24-09-2015 дата публикации

Novel 3D Integration Method using SOI Substrates and Structures Produced Thereby

Номер: US20150270172A1
Автор: Purushotaman Sampath D., Yu Roy R.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer. 16-. (canceled)7. A method of fabricating an enhanced 3D device stack comprising the steps of:fabricating silicon on insulator (SOI) circuits on a first SOI wafer with a buried oxide (BOX) layer;providing a first set of middle of the line (MOL) interconnects for said SOI circuits;patterning and etching a set of vias and alignment marks that extend from the top surface of said first set of MOL interconnects to the bottom surface of said BOX layer;filling and planarizing said vias and said alignment marks with metal;completing a first set of BEOL interconnects to connect said SOI circuits;providing a first set of bonding pad level atop said first set of BEOL interconnects;fabricating a second device wafer with a set of circuits, second set of MOL interconnects, a second set of BEOL interconnects and a second set of bonding pads;flipping said first SOI wafer, positioning it atop said second device wafer such that said first and said second set of bonding pads are aligned to each other;bonding said first SOI wafer and said second device wafer together by applying elevated temperature and pressure to bond said first and second set of bonding pads;removing the silicon substrate from said first SOI wafer by a grinding, polishing and etching or combinations thereof and stopping on said BOX layer and exposing said metal filled vias and alignment marks;fabricating a third set of interconnects atop the BOX layer using said alignment marks as reference and connecting ...

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Номер записи: 82
24-09-2015 дата публикации

SEMICONDUCTOR DEVICE, IMAGING DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Номер: US20150270304A1
Автор: Saito Haruhisa
Принадлежит: OLYMPUS CORPORATION

A semiconductor device manufacturing method includes a wafer stack manufacturing process and a dicing process. The wafer stack manufacturing process includes: a first wafer manufacturing process of manufacturing a resin film covering circuits and heated to a temperature higher than a glass transition point of the resin film, manufacturing first holes extending from a surface of the resin film to wirings of the circuits, and providing electrodes electrically connected to the wirings in the first holes to form a first wafer; a second wafer manufacturing process of manufacturing a resin film covering circuits and heated to a temperature lower than a glass transition point of the resin film, manufacturing second holes extending from a surface of the resin film to wirings of the circuits, and providing the electrodes electrically connected to the wirings in the second holes to form a second wafer; and a wafer bonding process. 1. A semiconductor device manufacturing method comprising:a wafer stack manufacturing process of manufacturing a wafer stack in which a plurality of wafers comprising circuits and electrodes electrically connected to the circuits are stacked; anda dicing process of dicing the wafer stack,wherein the wafer stack manufacturing process comprises:a first wafer manufacturing process of manufacturing a resin film covering the plurality of circuits and heated to a temperature higher than a glass transition point of the resin film, manufacturing first holes extending from a surface of the resin film to wirings of the circuits, and providing the electrodes electrically connected to the wirings in the first holes to form a first wafer;a second wafer manufacturing process of manufacturing a resin film covering the plurality of circuits and heated to a temperature lower than a glass transition point of the resin film, manufacturing second holes extending from a surface of the resin film to wirings of the circuits, and providing the electrodes electrically ...

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Номер записи: 83
15-08-2019 дата публикации

Method for transferring micro device

Номер: US20190252221A1
Автор: Fang-Chi Chien, Li-Yi Chen, Shyh-Feng Chen
Принадлежит: Mikro Mesa Technology Co Ltd

A method for transferring a micro device includes: preparing a carrier substrate with the micro device thereon in which an adhesive layer is present between and in contact with the carrier substrate and the micro device; picking up the micro-device from the carrier substrate by a transfer head comprising a force-adjustable glue layer thereon; forming a liquid layer on a receiving substrate; reducing the grip force of the force-adjustable glue layer of the transfer head to be smaller than a force attaching the micro device to the receiving substrate; placing the micro device over the receiving substrate such that the micro device is in contact with the liquid layer and is gripped by a capillary force; and moving the transfer head away from the receiving substrate such that the micro device is detached from the transfer head and is stuck to the receiving substrate.

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Номер записи: 84
15-08-2019 дата публикации

FACE-TO-FACE THREE-DIMENSIONAL INTEGRATED CIRCUIT OF SIMPLIFIED STRUCTURE

Номер: US20190252353A1
Автор: LATTARD Didier, Thuries Sébastien
Принадлежит: Commissariat A L'Energie Atomique Et Aux Energies Alternatives

An integrated circuit including a first chip including a stack of a substrate, of an active layer and of interconnect layers; a second chip including a stack of a substrate, of an active layer and of interconnect layers; an interconnect network for interconnecting the first and second chips. The interconnect layer of the highest metallization level of the first chip includes a power distribution network; the interconnect layer of the highest metallization level of the second chip is without a power distribution network. 1. An integrated circuit comprising:a first chip including a stack of a substrate, of an active layer and of interconnect layers;a second chip including a stack of a substrate, of an active layer and of interconnect layers, the interconnect layers of the first and second chips facing one another;an interconnect network for interconnecting the first and second chips, which is connected to an interconnect layer of the highest metallization level of the first chip and to an interconnect layer of the highest metallization level of the second chip respectively, the interconnect network forming a hybrid connection layer between the first and second chips,wherein:the interconnect layer of the highest metallization level of the first chip includes a power distribution network;the interconnect layer of the highest metallization level of the second chip is without a power distribution network.2. The integrated circuit according to claim 1 , wherein the etch pitch of the highest metallization level of the first chip is at least twice that of the highest metallization level of the second chip.3. The integrated circuit according to claim 1 , wherein the major portion of the area of the first chip is occupied by logic gates claim 1 , and wherein the major portion of the area of the second chip is occupied by memory cells.4. The integrated circuit according to claim 1 , wherein the etch pitch of the interconnect network is at least eight times higher than the etch ...

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Номер записи: 85
28-10-2021 дата публикации

CHIP PACKAGE STRUCTURE WITH REDISTRIBUTION LAYER HAVING BONDING PORTION

Номер: US20210335750A1
Автор: CHANG Geng-Ming, Shao Tung-Liang, Tung Chih-Hang, Yang Su-Chun, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A chip package structure is provided. The chip package structure includes a first redistribution layer having a bonding portion. The bonding portion includes a dielectric layer. The chip package structure includes a chip structure bonded to the bonding portion. A first width of the dielectric layer of the bonding portion is substantially equal to a second width of the chip structure. The chip package structure includes a protective layer over the first redistribution layer and surrounding the chip structure. A portion of the protective layer extends into the first redistribution layer and surrounds the bonding portion. 1. A chip package structure , comprising:a first redistribution layer having a bonding portion, wherein the bonding portion comprises a dielectric layer;a chip structure bonded to the bonding portion, wherein a first width of the dielectric layer of the bonding portion is substantially equal to a second width of the chip structure; anda protective layer over the first redistribution layer and surrounding the chip structure, wherein a portion of the protective layer extends into the first redistribution layer and surrounds the bonding portion.2. The chip package structure as claimed in claim 1 , wherein a first length of the dielectric layer of the bonding portion is substantially equal to a second length of the chip structure.3. The chip package structure as claimed in claim 1 , wherein the chip structure comprises:a substrate; anda second redistribution layer between the substrate and the bonding portion, wherein the second redistribution layer is in direct contact with the bonding portion, and the second redistribution layer has the second width.4. The chip package structure as claimed in claim 3 , wherein the bonding portion comprises a first conductive pad claim 3 , the second redistribution layer of the chip structure comprises a second conductive pad claim 3 , and the second conductive pad is over the first conductive pad.5. The chip package ...

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Номер записи: 86
28-10-2021 дата публикации

METHOD OF TRANSFERRING A PLURALITY OF MICRO LIGHT EMITTING DIODES TO A TARGET SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY APPARATUS THEREOF

Номер: US20210335752A1
Автор: Huang Guan, Huo Yijie, LIU Fang
Принадлежит: BOE Technology Group Co., Ltd.

The present application discloses a method for transferring a plurality of micro light emitting diodes (micro LEDs) to a target substrate. The method includes providing a first substrate having an array of the plurality of micro LEDs; providing a target substrate having a bonding layer having a plurality of bonding contacts; applying the plurality of bonding contacts with an electrical potential; aligning the plurality of micro LEDs with the plurality of bonding contacts having the electrical potential; and transferring the plurality of micro LEDs in the first substrate onto the target substrate. 1. A method for transferring a plurality of micro light emitting diodes (micro LEDs) to a target substrate , comprising:providing a first substrate having an array of the plurality of micro LEDs;providing a target substrate having a bonding layer comprising a plurality of bonding contacts;applying the plurality of bonding contacts with an electrical potential;aligning the plurality of micro LEDs with the plurality of bonding contacts having the electrical potential; andtransferring the plurality of micro LEDs in the first substrate onto the target substrate.2. The method of claim 1 , wherein each of the plurality of micro LEDs comprises a micro p-n diode and a metallization block on the micro p-n diode; andaligning the plurality of micro LEDs with the plurality of bonding contacts comprises aligning the metallization block with one of the plurality of bonding contacts applied with the electrical potential, the metallization block is placed between the micro p-n diode and one of the plurality of bonding contacts.3. The method of claim 2 , wherein aligning the plurality of micro LEDs with the plurality of bonding contacts comprises:placing the first substrate and the target substrate so that the first substrate and the target substrate face each other; andmoving the first substrate and the target substrate toward each other.4. The method of claim 3 , wherein applying the ...

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Номер записи: 87
04-11-2021 дата публикации

METHODS AND DEVICES FOR FABRICATING AND ASSEMBLING PRINTABLE SEMICONDUCTOR ELEMENTS

Номер: US20210343862A1
Автор: KHANG Dahl-Young, LEE Keon Jae, MEITL Matthew, Menard Etienne, NUZZO Ralph G., ROGERS John A., SUN Yugang, ZHU Zhengtao
Принадлежит: The Board of Trustees of the University of Illinois

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

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Номер записи: 88
08-10-2015 дата публикации

Hybrid Bonding Systems and Methods for Semiconductor Wafers

Номер: US20150287694A1
Автор: Chao Lan-Lin, Huang Xin-Hua, LIN SHIH-WEI, Liu Ping-Yin, Tsai Chia-Shiung
Принадлежит:

Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together. 1. A method comprising:forming a first protection layer over a first semiconductor wafer;forming a second protection layer over a second semiconductor wafer;placing the first semiconductor wafer and the second semiconductor wafer into a chamber;removing the first protection layer and the second protection layer while the first semiconductor wafer and the second semiconductor wafer are in the chamber;coupling a top surface of the second semiconductor wafer to a top surface of the first semiconductor wafer while the first semiconductor wafer and the second semiconductor wafer are in the chamber; andhybrid bonding the first semiconductor wafer to the second semiconductor wafer while the first semiconductor wafer and the second semiconductor wafer are in the chamber.2. The method of claim 1 , further comprising after removing the first protection layer and the second protection layer claim 1 , activating the top surfaces of the first semiconductor wafer and the second semiconductor wafer while the first semiconductor wafer and the second semiconductor wafer are in the chamber.3. The method of claim 1 , ...

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Номер записи: 89
25-11-2021 дата публикации

NANOSCALE-ALIGNED THREE-DIMENSIONAL STACKED INTEGRATED CIRCUIT

Номер: US20210366771A1
Автор: Abed Ovadia, Ajay Paras, KULKARNI Jaydeep, McDermott Mark, Sayal Aseem, Singhal Shrawan, Sreenivasan Sidlgata V.
Принадлежит:

A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs). 1. A method for fabricating a three-dimensional (3D) system on a chip (SoC) , the method comprising:assembling a Layer-(k) two-dimensional (2D)-die array onto a Layer-(k−1) 2D-die array of a Layer-(k−1) wafer, wherein said Layer-(k−1) wafer is populated with 2D-dies, wherein said k is a positive integer number greater than 1, wherein said 2D-die array comprises a single 2D-die, a single island of 2D-die that forms a contiguous group of 2D die or multiple islands of 2D die; anddeploying a fluid allowing lubricated relative motion between said Layer-(k) 2D-die array and said Layer-(k−1) 2D-die array, wherein said fluid allows precision overlay of said Layer-(k) and Layer-(k−1) 2D-die arrays.2. The method as recited in claim 1 , wherein said assembly is performed to achieve one of the following: sub-100 nm overlay claim 1 , sub-50 nm overlay claim 1 , sub-30 nm overlay claim 1 , sub-20 nm overlay claim 1 , sub-10 nm overlay and sub-5 nm overlay between each 2D-die of a Layer-(k) wafer and the corresponding 2D-die of said Layer-(k−1) wafer.3. The method as recited in claim 1 , wherein said fluid comprises one of the following: a gas claim 1 , a liquid and a combination thereof claim 1 , wherein said combination comprises disparate gas and liquid portions or portions of a homogenously mixed gas and liquid.4 ...

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Номер записи: 90
27-08-2020 дата публикации

MANUFACTURING METHOD AND MANUFACTURING APPARATUS FOR STACKED SUBSTRATE, AND PROGRAM

Номер: US20200273836A1
Автор: FUKUDA MINORU, KAMASHITA Atsushi, MITSUISHI Hajime, Sugaya Isao
Принадлежит: NIKON CORPORATION

A manufacturing method for manufacturing a stacked substrate by bonding two substrates includes: acquiring information about crystal structures of a plurality of substrates; and determining a combination of two substrates to be bonded to each other, based on the information about the crystal structures. In the manufacturing method described above, the information about the crystal structures may include at least one of plane orientations of bonding surfaces and crystal orientations in a direction in parallel with the bonding surfaces. In the manufacturing methods described above, the determining may include determining a combination of the two substrates with a misalignment amount after bonding being equal to or smaller than a predetermined threshold. 1. A manufacturing method for manufacturing a stacked substrate by bonding two substrates , the method comprising:acquiring information about crystal structures of a plurality of substrates; anddetermining a combination of two substrates to be bonded to each other, based on the information about the crystal structures.2. The manufacturing method according to claim 1 , wherein the information about the crystal structures includes at least one of plane orientations of bonding surfaces of the substrates and crystal orientations in a direction in parallel with the bonding surfaces.3. The manufacturing method according to claim 1 , wherein the determining includes determining a combination of the two substrates with a misalignment amount after bonding being equal to or smaller than a predetermined threshold.4. The manufacturing method according to claim 1 , wherein the determining includes determining a combination of the two substrates with bonding surfaces having plane orientations being a predetermined combination.5. The manufacturing method according to claim 1 , further comprising storing the information about the crystal structures and information about rigidity distributions on bonding surfaces of each of the two ...

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Номер записи: 91
04-10-2018 дата публикации

Sacrificial Alignment Ring And Self-Soldering Vias For Wafer Bonding

Номер: US20180286836A1
Автор: Bomy Chen, Justin Hiroki Sato, Walter Lundy
Принадлежит: Silicon Storage Technology Inc

A method of bonding a first substrate to a second substrate, wherein the first substrate includes first electrical contacts on a top surface of the first substrate, and wherein the second substrate includes second electrical contacts on a bottom surface of the second substrate. The method includes forming a block of polyimide on the top surface of the first substrate, wherein the block of polyimide has a rounded upper corner, and vertically moving the top surface of the first substrate and the bottom surface of the second substrate toward each other until the first electrical contacts abut the second electrical contacts, wherein during the moving, the second substrate makes contact with the rounded upper corner of the polyimide causing the first and second substrates to move laterally relative to each other.

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Номер записи: 92
10-09-2020 дата публикации

Method and device for manufacturing stacked substrate

Номер: US20200286851A1
Автор: Hajime MITSUISHI, Isao Sugaya
Принадлежит: Nikon Corp

A manufacturing method is provided, which includes processing at least one of a plurality of substrates; stacking the plurality of substrates to manufacture a stacked substrate; and correcting, in the processing, a part of an amount of positional misalignment that is generated among a plurality of substrates in the stacking and correcting, in the stacking, at least a part of the remainder of the amount of positional misalignment.

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Номер записи: 93
18-10-2018 дата публикации

EMISSIVE LED DISPLAY DEVICE MANUFACTURING METHOD

Номер: US20180301433A1
Автор: Berthier Jean, Cheramy Séverine, Di Cioccio Lea, ROBIN Ivan-Christophe
Принадлежит: Commissariat A L'Energie Atomique Et Aux Energies Alternatives

A method of manufacturing an emissive LED display device, including the steps of forming a plurality of chips, each including at least one LED and, on a connection surface, a plurality of hydrophilic electric connection areas and a hydrophobic area; forming a transfer substrate including, for each chip, a plurality of hydrophilic electric connection areas and a hydrophobic area; arranging a drop of a liquid on each electric connection area of the transfer substrate and/or of each chip; and affixing the chips to the transfer substrate by direct bonding, using the capillary restoring force of the drops to align the electric connection areas of the chips with the electric connection areas of the transfer substrate. 1. A method of manufacturing an emissive LED display device , comprising the steps of:a) forming a plurality of chips, each comprising at least one LED and, on a connection surface of the chip, a plurality of hydrophilic electric connection areas and a hydrophobic area, each electric connection area of the chip being surrounded and separated from the other electric connection areas of the chip by the hydrophobic area;b) forming a transfer substrate comprising, for each chip, on a connection surface of the transfer substrate, a plurality of hydrophilic electric connection areas intended to be respectively connected to the electric connection areas of the chip, and a hydrophobic area, each electric connection area of the transfer substrate being surrounded and separated from the other electric connection areas of the transfer substrate by the hydrophobic area;c) arranging a drop of a liquid on each electric connection area of the transfer substrate and/or on each electric connection area of each chip; andd) affixing the chips to the transfer substrate by direct bonding to electrically connect the electronic connection areas of each chip to the corresponding electric connection areas of the transfer substrate, using the capillary restoring force of the drops to ...

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Номер записи: 94
26-09-2019 дата публикации

SEMICONDUCTOR DEVICE AND IMAGING DEVICE

Номер: US20190296073A1
Автор: KOIKE Kaoru, KOTOO Kengo
Принадлежит: SONY CORPORATION

To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer. A width of the first metal layer and the second metal layer is a width based on a joining strength between the first insulating layer and the second insulating layer and a joining strength between the first metal layer and the second metal layer in an area from an end portion of the first semiconductor chip to the first pad. 19-. (canceled)10. A light detecting device , comprising:a first substrate including a plurality of pixels in a pixel array and a first wiring layer, wherein the first wiring layer includes a first pad and a first guard ring;a second substrate including a signal processing region and a second wiring layer,wherein the plurality of pixels outputs a plurality of pixel signals to the signal processing region,wherein the second wiring layer includes a second pad and a second guard ring,wherein the first pad is joined to the second pad,wherein the first pad and the second pad are electrically connected to each other,wherein the first pad is electrically connected to the first substrate,wherein the second pad is electrically connected to the second substrate,wherein the first guard ring and the second guard ring are disposed ...

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Номер записи: 95
17-09-2020 дата публикации

HYBRID BONDED STRUCTURE

Номер: US20200295070A1
Автор: TSAI Bo-Tsung
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A hybrid bonded structure including a first integrated circuit component and a second integrated circuit component is provided. The first integrated circuit component includes a first dielectric layer, first conductors and isolation structures. The first conductors and the isolation structures are embedded in the first dielectric layer. The isolation structures are electrically insulated from the first conductors and surround the first conductors. The second integrated circuit component includes a second dielectric layer and second conductors. The second conductors are embedded in the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer and the first conductors are bonded to the second conductors.

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Номер записи: 96
26-10-2017 дата публикации

METHODS AND DEVICES FOR FABRICATING AND ASSEMBLING PRINTABLE SEMICONDUCTOR ELEMENTS

Номер: US20170309733A1
Автор: KHANG Dahl-Young, LEE Keon Jae, MEITL Matthew, Menard Etienne, NUZZO Ralph G., ROGERS John A., SUN Yugang, ZHU Zhengtao
Принадлежит:

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations. 1. A wafer of printable elements , the wafer comprising:a substrate; each printable element is disposed on the substrate,', 'each printable element is at least partially undercut from the substrate, and', 'the printable elements are mechanically connected to the substrate only by alignment maintaining elements., 'a plurality of printable elements native to the substrate, wherein'}2. The wafer of claim 1 , wherein each of the alignment maintaining elements has a length that is less than one half claim 1 , one third claim 1 , one quarter claim 1 , or one eighth of the length of the printable element in at least one dimension having a direction parallel to the surface of the substrate on which the plurality of printable elements is disposed.3. The wafer of claim 1 , wherein each of the alignment maintaining elements is laterally connected to the substrate.4. The wafer of claim 3 , wherein each of the alignment maintaining elements is between the substrate and a corresponding printable element in a direction horizontal to a surface of the substrate on which the plurality of printable elements is disposed.5. The wafer of claim 1 , wherein each of the alignment maintaining elements is vertically connected to the substrate.6. The wafer of claim 5 , wherein each of the alignment maintaining elements is between the substrate and a corresponding printable element in a direction orthogonal to a surface of the substrate on which the ...

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Номер записи: 97
26-10-2017 дата публикации

METHODS OF FORMING A MICROELECTRONIC DEVICE STRUCTURE, AND RELATED MICROELECTRONIC DEVICE STRUCTURES AND MICROELECTRONIC DEVICES

Номер: US20170311451A1
Автор: Hahn Mark
Принадлежит:

A method of forming a microelectronic device structure comprises coiling a portion of a wire up and around at least one sidewall of a structure protruding from a substrate. At least one interface between an upper region of the structure and an upper region of the coiled portion of the wire is welded to form a fused region between the structure and the wire. 1. A method of forming a microelectronic device structure , comprising: a proximal region adjacent an interface between the structure and the surface of the another structure; and', 'a distal region opposing the proximal region; and, 'coiling a portion of a wire up and around at least one sidewall of a structure protruding from a surface of another structure, the structure comprisingwelding at least one interface between an upper region of the structure and an upper region of the coiled portion of the wire to form a fused region integral and continuous with the distal region of the structure and a terminal end of the wire.2. The method of claim 1 , wherein coiling a portion of a wire up and around at least one sidewall of a structure comprises coiling the portion of the wire substantially completely around a lateral periphery of the structure at least one time.3. The method of claim 1 , wherein coiling a portion of a wire up and around at least one sidewall of a structure comprises coiling each of a sheathed region of the wire and an unsheathed region of the wire up and around the at least one sidewall of the structure.4. The method of claim 3 , wherein coiling each of a sheathed region of the wire and an unsheathed region of the wire up and around the at least one sidewall of the structure comprises:wrapping the sheathed region of the wire up and around a periphery of the structure at least one time; andwrapping the unsheathed region of the wire up and around the periphery of the structure at least one time.5. The method of claim 1 , wherein coiling a portion of a wire up and around at least one sidewall of a ...

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Номер записи: 98
24-09-2020 дата публикации

PROCESS FOR MANUFACTURING AN LED-BASED EMISSIVE DISPLAY DEVICE

Номер: US20200303359A1
Автор: CAPLET Stéphane, Cyrille Marie-Claire, Delaet Bertrand, Giroud Sophie, ROBIN Ivan-Christophe
Принадлежит: Commissariat a I'Energie Atomique et aux Energies Alternatives

A method of manufacturing an electronic device, including: a) forming a plurality of chips, each including a plurality of connection areas and at least one first pad; b) forming a transfer substrate including, for each chip, a plurality of connection areas and at least one second pad, one of the first and second pads being a permanent magnet and the other one of the first and second pads being either a permanent magnet or made of a ferromagnetic material; and c) affixing the chips to the transfer substrate to connect the connection areas of the chips to the connection areas of the transfer substrate, by using the magnetic force between the pads to align the connection areas of the chips with the corresponding connection areas of the transfer substrate. 1. A method of manufacturing an electronic device , comprising the steps of: a plurality of electric connection areas arranged on a connection surface of the chip, and', 'at least one first pad arranged in the vicinity of the chip connection surface;, 'a) forming a plurality of chips, each comprising a plurality of electric connection areas arranged on a connection surface of the transfer substrate, and', 'at least one second pad arranged in the vicinity of the connection surface of the transfer substrate, one of the first and second pads being a permanent magnet and the other of the first and second pads being either a permanent magnet or made of a ferromagnetic material; and, 'b) forming a transfer substrate comprising, for each chipc) affixing the chips to the transfer substrate by direct bonding to electrically connect the electric connection areas of each chip to the corresponding electric connection areas of the transfer substrate, by using the magnetic force between the first and second pads to align the electric connection areas of the chips with the corresponding electric connection areas of the transfer substrate.2. The method of claim 1 , wherein claim 1 , in each chip claim 1 , the first pad emerges on the ...

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Номер записи: 99
01-11-2018 дата публикации

NOVEL 3D INTEGRATION METHOD USING SOI SUBSTRATES AND STRUCTURES PRODUCED THEREBY

Номер: US20180315655A1
Автор: Purushothaman Sampath, YU Roy RONGUING
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer. 123-. (canceled)24. A product made by the process of fabricating an enhanced 3D device stack comprising the steps of:fabricating silicon on insulator (SOI) circuits on a first SOI wafer having a silicon substrate with a buried oxide (BOX) layer, said buried oxide (BOX) layer having a bottom surface;providing a first set of middle of the line (MOL) interconnects for said SOI circuits said first set of middle of the line (MOL) interconnects having a top surface;patterning and etching a set of vias and alignment marks that extend from the top surface of said first set of MOL interconnects to the bottom surface of said BOX layer, said vias having exposed ends;filling and planarizing said vias and said alignment marks with metal;completing a first set of BEOL interconnects to connect said SOI circuits;providing a first set of bonding pads level atop said first set of BEOL interconnects;fabricating a second device wafer with a second set of circuits comprising a second set of MOL interconnects, a second set of BEOL interconnects and a second set of bonding pads;flipping said first SOI wafer, positioning it atop said second device wafer such that said first and said second set of bonding pads are aligned to each other;bonding said first SOI wafer and said second device wafer together by applying elevated temperature and pressure to bond said first and second set of bonding pads;removing the silicon substrate from said first SOI wafer by a grinding, polishing and ...

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Номер записи: 100