Package structure and manufacturing method thereof

A package structure includes a redistribution layer having a first surface, a second surface disposed opposite to the first surface, and at least one sidewall connected to the first surface and the second surface, at least one bonding electrode disposed on the first surface of the redistribution layer, and a mounting layer disposed on the second surface of the redistribution layer. The mounting layer includes a plurality of conductive pads that are spaced apart from each other. At least one of the conductive pads is exposed by the sidewall of the redistribution layer.

Diffusion barrier collar for interconnects

Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

Diffusion barrier collar for interconnects

Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

Diffusion barrier collar for interconnects

Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

반도체 패키지

반도체 패키지를 제공한다. 이 반도체 패키지는 일 면에 제1 절연층이 배치되며 상기 제1 절연층을 관통하는 제1 전극 패드들 및 제1 더미 패드들을 갖는 제1 구조물 - 상기 제1 전극 패드들은 20㎛ 이하의 피치(pitch)를 가지며, 상기 제1 더미 패드들은 상기 제1 전극 패드들의 둘레에 배치됨-; 및 상기 일 면에 접합되는 타 면을 가지며, 상기 타 면에 상기 제1 절연층과 접합되는 제2 절연층이 배치되며, 상기 제2 절연층을 관통하는 제2 전극 패드들 및 제2 더미 패드들을 갖는 제2 구조물 - 상기 제2 전극 패드들을 상기 제1 전극 패드들에 각각 접합되며, 상기 제2 더미 패드들은 상기 제1 더미 패드들에 각각 접합됨-을 포함한다. 상기 반도체 칩은 상기 일 면에서 상기 제1 절연층에 대한 상기 제1 더미 패드들의 단위 면적당 표면적의 비율(ratio)은 상기 제1 구조물의 측면으로 갈수록 점점 감소하며, 상기 타 면에서 상기 제2 절연층에 대한 상기 제2 더미 패드들의 단위 면적당 표면적의 비율은 상기 제2 구조물의 측면으로 갈수록 점점 감소한다.

Integrated circuit package and method

디바이스 패키지는 계면에서 제2 다이에 직접 본딩된 제1 다이를 포함하며, 계면은 전도체 대 전도체 접합을 포함한다. 디바이스 패키지는 제1 다이 및 제2 다이를 둘러싸는 봉지재, 및 봉지재를 관통해 연장되는 복수의 관통 비아를 더 포함한다. 복수의 관통 비아는 제1 다이 및 제2 다이에 인접하게 배치된다. 디바이스 패키지는 봉지재를 관통해 연장되는 복수의 열 비아(thermal vias), 그리고 제1 다이, 제2 다이 및 복수의 관통 비아에 전기적으로 접속된 재분배 구조물을 더 포함한다. 복수의 열 비아는 제2 다이의 표면 상에 그리고 제1 다이에 인접하게 배치된다. The device package includes a first die bonded directly to a second die at an interface, the interface including a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die, and a plurality of through vias extending through the encapsulant. A plurality of through vias are disposed adjacent to the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die and the plurality of through vias. A plurality of column vias are disposed on the surface of the second die and adjacent to the first die.

Semiconductor modules, display devices, and methods for manufacturing semiconductor modules

Direct bonding methods and structures

接合方法可包括活化第一元件之第一接合層以直接接合到第二元件之第二接合層。接合方法可包括，在活化之後，在第一元件之經活化之第一接合層上提供保護層。

Semiconductor module, display device, and method of manufacturing semiconductor module.

樹脂（１６）は、青色ＬＥＤ（１５）の側面および裏面を被覆し、かつ青色ＬＥＤ（１５）を水平に保持する。電極（１４）は、配線基板（１１）の表面と青色ＬＥＤ（１５）の裏面との間に設けられ、樹脂（１６）を貫通し、かつ配線基板（１１）と青色ＬＥＤ（１５）とを電気的に接続する。青色ＬＥＤ（１５）の光出射面（表面）（１５１）が樹脂（１６）から露出してなり、光出射面（表面）（１５１）と樹脂（１６）の表面（１６１）とを同一の平面に配置してなる。 The resin (16) covers the side surface and the back surface of the blue LED (15) and holds the blue LED (15) horizontally. The electrode (14) is provided between the front surface of the wiring board (11) and the back surface of the blue LED (15), penetrates the resin (16), and connects the wiring board (11) and the blue LED (15). Connect electrically. The light emitting surface (surface) (151) of the blue LED (15) is exposed from the resin (16), and the light emitting surface (surface) (151) and the surface (161) of the resin (16) are on the same plane. It will be arranged in.

Integrated circuit package and method for fabricating the same

一種元件封裝，包括第一晶粒，所述第一晶粒在界面處直接接合至第二晶粒，其中所述界面包括導體對導體接合。所述元件封裝更包括包圍所述第一晶粒及所述第二晶粒的包封體及延伸穿過所述包封體的多個穿孔。所述多個穿孔鄰近所述第一晶粒及所述第二晶粒配置。所述元件封裝更包括延伸穿過所述包封體的多個熱通孔及電連接至所述第一晶粒、所述第二晶粒以及所述多個穿孔的重佈線結構。所述多個熱通孔配置於所述第二晶粒的表面上且鄰近所述第一晶粒。

Electronic device and method of manufacturing electronic device

An electronic device includes a substrate, an electronic component, a first interposing layer and a second interposing layer. The substrate is non-planar and the substrate includes a first substrate pad and a second substrate pad. The electronic component includes a first component pad and a second component pad corresponding to the first substrate pad and the second substrate pad respectively. When the first component pad contacts the first substrate pad, a height difference exists between the second component pad and the second substrate pad. The first interposing layer connects between the first component pad and the first substrate pad. The second interposing layer connects between the second component pad and the second substrate pad. A thickness difference between the first interposing layer and the second interposing layer is 0.5 to 1 time the height difference.

Display apparatus and method of manufacturing the same

本申请涉及显示设备和制造显示设备的方法。显示设备包括：衬底，包括显示区域和焊盘区域；多个焊盘电极，在衬底上设置在焊盘区域中；电路板，设置成在衬底上与焊盘区域的至少一部分重叠；以及各向异性导电层，设置在衬底和电路板之间的焊盘区域中。电路板包括基础衬底和设置在基础衬底的下表面上的多个凸起电极。各向异性导电层包括粘合层和布置在粘合层中的多个导电颗粒。导电颗粒中的每一个包括芯、以使得芯的至少一部分暴露的方式设置在芯上的第一导电膜、以及完全覆盖芯和第一导电膜的第二导电膜。

Wafer-class encapsulation and its manufacturing method

适用本发明的晶片级封装，能够包括：基板，包括焊板以及第一保护堤，在一侧面配置有多个电路图案部；印刷电路基板，配置有多个连接板、第二保护堤以及导通孔；以及连接部，与配置在上述印刷电路基板上的上述多个连接板中的一部分以及上述第二保护堤连接。通过适用本发明的晶片级封装及其制造方法，能够提升设计自由度并提升晶片级封装的可靠性。此外，通过本发明，能够在布线设计过程中省略桥接工程并借此简化制造工程并实现元件大小的小型化。

Diffusion barrier collar for interconnects

접합된 기판들의 절연 또는 유전체 재료 안으로의 전도성 재료 확산을 감소 또는 방지하는 데 기술들 및 디바이스들의 대표적인 구현예들이 사용된다. 오정렬된 전도성 구조물들은, 특히 직접 접합 기술을 이용하는 동안 중첩으로 인해 기판들의 유전체 부분과 직접 접촉하게 될 수 있다. 확산을 억제할 수 있는 배리어 계면이 일반적으로 전도성 재료와 유전체 사이에 중첩부에서 배치된다.

Inter-component material in microelectronic assemblies having direct bonding

Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, and related structures and techniques. In some embodiments, a microelectronic assembly may include an interposer; a first microelectronic component having a first surface coupled to the interposer by a first direct bonding region and an opposing second surface; a second microelectronic component having a first surface coupled to the interposer by a second direct bonding region and an opposing second surface; a liner material on the surface of the interposer and around the first and second microelectronic components; an inorganic fill material on the liner material and between the first and second microelectronic components; and a third microelectronic component coupled to the second surfaces of the first and second microelectronic components. In some embodiments, the liner material, the inorganic fill material, and a material of the third microelectronic component may include a thermally conductive material.

Semiconductor device with heat dissipation unit and method for fabricating the same

The present application discloses a semiconductor device with a heat dissipation unit and a method for fabricating the semiconductor device. The semiconductor device includes a die stack, an intervening bonding layer positioned on the die stack, and a carrier structure including a carrier substrate positioned on the intervening bonding layer, and through semiconductor vias positioned in the carrier substrate and on the intervening bonding layer for thermally conducting heat.

Integrated circuit package and method

A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

Integrated Circuit Package and Method

A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

Semiconductor packages and methods of forming the same

A semiconductor package includes a first semiconductor die, a second semiconductor die and a plurality of bumps. The first semiconductor die has a front side and a backside opposite to each other. The second semiconductor die is disposed at the backside of the first semiconductor die and electrically connected to first semiconductor die. The plurality of bumps is disposed at the front side of the first semiconductor die and physically connects first die pads of the first semiconductor die. A total width of the first semiconductor die may be less than a total width of the second semiconductor die.

Semiconductor device with a semiconductor chip bonded between a first, plate-shaped electrode with a groove and a second electrode

A semiconductor device (200) includes: a semiconductor chip (1a) including a first main electrode (D) on one surface thereof and a second main electrode (S) and a gate electrode on the other surface thereof; a first electrode (1g) connected to the first main electrode (D) of the semiconductor chip (1a) via a first bonding material (1p); and a second electrode (1d) connected to the second main electrode (S) of the semiconductor chip (1a) via a second bonding material (1q). The first electrode (1g) is a plate-shaped electrode and has a groove (T) in a region overlapping with the semiconductor chip (1a). The groove (T) penetrates in a thickness direction of the first electrode (1g) and reaches an end portion of the first electrode (1g) when viewed in a plan view. In this manner, a highly reliable semiconductor device (200) is provided, in which stress generated in the semiconductor chip (1a) is reduced and an increase in thermal resistance is suppressed. An end portion of the second electrode (1d) may be located so as to project, in the plan view, inside the semiconductor chip (1a), wherein the end portion of the first electrode (1g) is located so as to project, in the plan view, outside the end portion of the semiconductor chip (1a) or inside the semiconductor chip (1a). The groove (T) may have a width larger than a thickness of the first bonding material (1p), mitigating groove (T) filling with the first bonding material (1p). The groove (T) may be provided at a position overlapping with the second electrode (1d). The groove (T) may include a branched groove (T2), provided so as to communicate with the groove (T) and branched from the groove (T). The first bonding material (1p) and the second bonding material (1q) may be solders, such as a high-lead solder, a eutectic solder, a lead-free solder or a solder containing Sn as a main component, may be sintered materials using Cu or Ag or may be conductive adhesive materials in which a metal filler such as Ag, Cu or Ni is ...

Image sensor device

Methods of forming a back side image sensor device, as well as back side image sensor devices formed, are disclosed. In one such a method, an image sensor wafer having a first dielectric layer with a first surface is obtained. A reconstituted wafer having a processor die and a second dielectric layer with a second surface is obtained. The reconstituted wafer and the image sensor wafer are bonded to one another including coupling the first surface of the first dielectric layer and the second surface of the second dielectric layer. In another method, such formation is for a processor die bonded to an image sensor wafer. In yet another method, such formation is for a processor die bonded to an image sensor die.

열 통로를 갖는 반도체 패키지

반도체 패키지는 신호 배선 및 상기 신호 배선과 이격된 열 전달 배선을 갖는 배선 구조체를 포함한다. 상기 배선 구조체 상에 액티브 칩(Active Chip)이 배치된다. 상기 배선 구조체 및 상기 액티브 칩 사이에 신호 단자가 배치된다. 상기 배선 구조체 및 상기 액티브 칩 사이에 배치되고 상기 열 전달 배선에 접속된 제1 열 전달 단자가 제공된다. 상기 배선 구조체 상에 패시브 칩(Passive Chip)이 배치된다. 상기 배선 구조체 및 상기 패시브 칩 사이에 배치되고 상기 열 전달 배선에 접속된 제2 열 전달 단자가 제공된다. 상기 패시브 칩 상에 히트 스프레더(Heat Spreader)가 배치된다.

Method of manufacturing semiconductor structure

A method of manufacturing a semiconductor structure includes following operations. A substrate is provided. A first die is disposed over the substrate. A second die is provided. The second die includes a via extended within the second die. The second die is disposed over the substrate. A molding is formed around the first die and second die. An interconnect structure is formed. The interconnect structure includes a dielectric layer and a conductive member. The dielectric layer is disposed over the molding, the first die and the second die. The conductive member is surrounded by the dielectric layer. The via is formed by removing a portion of the second die to form a recess extended within the second die and disposing a conductive material into the recess.

半導體裝置

本發明之課題在於提供一種減少半導體元件中產生之應力、抑制熱阻力增加且可靠性高之半導體裝置。 本發明之半導體裝置具有：半導體晶片，其於一面具有第1主電極，於另一面具有第2主電極及閘極電極；第1電極，其經由第1接合材連接於半導體晶片之一面；及第2電極，其經由第2接合材連接於半導體晶片之另一面；且第1電極為板狀之電極，於與半導體晶片重合之區域具有溝槽；溝槽具有於第1電極之厚度方向貫通之構成，且為俯視觀察時到達第1電極之端部之形狀。

Shield structures in microelectronic assemblies having direct bonding

Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component, having a first surface and an opposing second surface including a first direct bonding region at the 5 second surface with first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component, having a first surface and an opposing second surface, including a second direct bonding region at the first surface with second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the second microelectronic component is coupled to the first microelectronic component by 10 the first and second direct bonding regions; and a shield structure in the first direct bonding dielectric material at least partially surrounding the one or more of the first metal contacts.

Diffusion barrier collar for interconnects

Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

상호연결부를 위한 확산 배리어 칼라

접합된 기판들의 절연 또는 유전체 재료 안으로의 전도성 재료 확산을 감소 또는 방지하는 데 기술들 및 디바이스들의 대표적인 구현예들이 사용된다. 오정렬된 전도성 구조물들은, 특히 직접 접합 기술을 이용하는 동안 중첩으로 인해 기판들의 유전체 부분과 직접 접촉하게 될 수 있다. 확산을 억제할 수 있는 배리어 계면이 일반적으로 전도성 재료와 유전체 사이에 중첩부에서 배치된다.

Direct bonding methods and structures

A bonding method can include activating a first bonding layer of a first element for direct bonding to a second bonding layer of a second element. The bonding method can include, after the activating, providing a protective layer over the activated first bonding layer of the first element.

반도체 패키지 및 이를 형성하는 방법

반도체 패키지는 제1 반도체 다이, 제2 반도체 다이 및 복수의 범프를 포함한다. 제1 반도체 다이는 서로 반대쪽에 있는 전면 및 후면을 갖는다. 제2 반도체 다이는 제1 반도체 다이의 후면에 배치되고 제1 반도체 다이에 전기적으로 접속된다. 복수의 범프는 제1 반도체 다이의 전면에 배치되고 제1 반도체 다이의 제1 다이 패드를 물리적으로 접속한다. 제1 반도체 다이의 총 폭은 제2 반도체 다이의 총 폭보다 작을 수 있다.

Integrated circuit package and method

A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

半导体装置

提供一种半导体装置，降低在半导体元件中发生的应力，并且抑制热电阻的增加，可靠性高。半导体装置具有：半导体芯片，在一方的面具有第1主电极，在另一方的面具有第2主电极以及栅电极；第1电极，经由第1接合材料而与半导体芯片的一方的面连接；以及第2电极，经由第2接合材料而与半导体芯片的另一方的面连接，其中，第1电极是板状的电极，在与半导体芯片重叠的区域中具有槽，槽具有在第1电极的厚度方向上贯通的结构，并且是在俯视观察时到达至第1电极的端部的形状。

具有散熱單元的半導體元件及其製備方法

本揭露提供一種具有散熱單元的半導體元件及該半導體元件的製備方法。該半導體元件具有一晶粒堆疊；一中介接合層，設置在該晶粒堆疊上；以及一載體結構。該載體結構包括一載體基底以及多個半導體貫穿通孔，該載體基底設置在該中介接合層上，該等半導體貫穿通孔設置在該載體基底中以及在該中介接合層上，以進行導熱。

Method for fabricating semiconductor device with heat dissipation features

The present application provides a method for fabricating a semiconductor device. The method includes providing a carrier substrate, forming through semiconductor vias in the carrier substrate for thermally conducting heat, forming a bonding layer on the carrier substrate, providing a first die structure including through semiconductor vias, forming an intervening bonding layer on the first die structure, bonding the first die structure onto the bonding layer through the intervening bonding layer, and bonding a second die structure onto the first die structure. The carrier substrate, the through semiconductor vias, and the bonding layer together configure a carrier structure. The second die structure and the first die structure are electrically coupled by the through semiconductor vias.

半导体元件及其制备方法

本公开提供一种具有散热单元的半导体元件及该半导体元件的制备方法。该半导体元件具有一晶粒堆叠；一中介接合层，设置在该晶粒堆叠上；以及一载体结构。该载体结构包括一载体基底以及多个半导体贯穿通孔，该载体基底设置在该中介接合层上，所述半导体贯穿通孔设置在该载体基底中以及在该中介接合层上，以进行导热。

具有散熱單元的半導體元件及其製備方法

本揭露提供一種具有散熱單元的半導體元件及該半導體元件的製備方法。該半導體元件具有一晶粒堆疊；一中介接合層，設置在該晶粒堆疊上；以及一載體結構。該載體結構包括一載體基底以及多個半導體貫穿通孔，該載體基底設置在該中介接合層上，該等半導體貫穿通孔設置在該載體基底中以及在該中介接合層上，以進行導熱。

Semiconductor device with heat dissipation unit and method for fabricating the same

The present application discloses a semiconductor device with a heat dissipation unit and a method for fabricating the semiconductor device. The semiconductor device includes a die stack, an intervening bonding layer positioned on the die stack, and a carrier structure including a carrier substrate positioned on the intervening bonding layer, and through semiconductor vias positioned in the carrier substrate and on the intervening bonding layer for thermally conducting heat.

用于互连的扩散阻挡衬层

技术和装置的代表性实施方式用于减少或防止导电材料扩散到结合衬底的绝缘材料或电介质材料中。由于重叠，错位的导电结构可以直接接触衬底的电介质部分，尤其是在采用直接结合技术的情况下。通常在重叠处将可以抑制扩散的阻挡界面设置在导电材料和电介质之间。

Semiconductor package and a package-on-package including the same

A semiconductor package including: a first wiring structure; a semiconductor chip disposed on the first wiring structure; a second wiring structure disposed on the semiconductor chip and including a cavity; and a filling member between the first wiring structure and the second wiring structure and in the cavity, wherein an uppermost end of the filling member and an uppermost end of the second wiring structure are located at the same level.

Semiconductor packages and methods of forming the same

A semiconductor package includes a first semiconductor die, a second semiconductor die and a plurality of bumps. The first semiconductor die has a front side and a backside opposite to each other. The second semiconductor die is disposed at the backside of the first semiconductor die and electrically connected to first semiconductor die. The plurality of bumps is disposed at the front side of the first semiconductor die and physically connects first die pads of the first semiconductor die. A total width of the first semiconductor die may be less than a total width of the second semiconductor die.

Substrate with electronic component embedded therein

A substrate with an electronic component embedded therein includes: a core structure having a cavity; a metal layer disposed on a bottom surface of the cavity of the core structure; and an electronic component disposed on the metal layer in the cavity of the core structure. The substrate with the electronic component embedded therein has an excellent heat dissipation effect.

Semiconductor package including thermal exhaust pathway

A semiconductor package includes; a wiring structure including signal wiring and heat transfer wiring, an active chip on the wiring structure, a signal terminal disposed between the wiring structure and the active chip, a first heat transferring terminal disposed between the wiring structure and the active chip and connected to the heat transfer wiring, a passive chip on the wiring structure, a second heat transferring terminal disposed between the wiring structure and the passive chip and connected to the heat transfer wiring, and a heat spreader on the passive chip.

用于互连的扩散阻挡衬层

本公开涉及一种用于互连的扩散阻挡衬层。技术和装置的代表性实施方式用于减少或防止导电材料扩散到结合衬底的绝缘材料或电介质材料中。由于重叠，错位的导电结构可以直接接触衬底的电介质部分，尤其是在采用直接结合技术的情况下。通常在重叠处将可以抑制扩散的阻挡界面设置在导电材料和电介质之间。

半导体封装和包括该半导体封装的层叠封装

本公开公开了一种半导体封装，包括：第一布线结构；半导体芯片，被设置在第一布线结构上；第二布线结构，被设置在半导体芯片上并且包括腔体；以及填充构件，在第一布线结构和第二布线结构之间并且在腔体中，其中填充构件的最上端和第二布线结构的最上端位于相同的高度水平处。

확산 베리어 및 그 형성 방법

다른 소자에 결합하여 결합 구조체를 형성하도록 구성된 소자가 개시된다. 이러한 소자는, 유전체 결합층의 표면으로부터 유전체 결합층의 두께를 적어도 부분적으로 관통하여 연장되는 캐비티를 가진 유전체 결합층을 포함할 수 있다. 이러한 소자는 캐비티 내에 적어도 부분적으로 배치된 도전성 피쳐를 더 포함할 수 있다. 도전성 피쳐는 접촉면을 가진다. 이러한 소자는 도전성 피쳐와 유전체 결합층의 일부 사이의 확산 베리어층을 포함할 수 있다. 베리어층은 베리어 금속을 포함한다. 확산 베리어층의 베리어 금속은 도전성 피쳐의 산화 경향보다 큰 산화 경향을 가진다.

Halbleiter-Package und Verfahren zum Bilden derselben

Ein Halbleiter-Package schließt einen ersten Halbleiter-Die, einen zweiten Halbleiter-Die und eine Vielzahl von Höckern ein. Der erste Halbleiter-Die weist eine Vorderseite und eine Rückseite gegenüber voneinander auf. Der zweite Halbleiter-Die wird an der Rückseite des ersten Halbleiter-Dies angeordnet und elektrisch mit dem ersten Halbleiter-Die verbunden. Die Vielzahl von Höckern wird an der Vorderseite des ersten Halbleiter-Dies vorgesehen und verbindet erste Die-Pads des ersten Halbleiter-Dies physisch. Eine Gesamtbreite des ersten Halbleiter-Dies kann geringer als eine Gesamtbreite des zweiten Halbleiter-Dies sein.

扩散势垒及其形成方法

公开了一种被配置为结合至另一元件以限定结合结构的元件。所述元件可以包括介电结合层，具有从所述介电结合层的表面至少部分地延伸穿过所述介电结合层的厚度的腔。所述元件还可以包括被至少部分地设置在所述腔中的导电特征。所述导电特征具有接触表面。所述元件可以包括介于所述介电结合层的一部分与所述导电特征之间的扩散势垒层。所述势垒层包括势垒金属。所述扩散势垒层的所述势垒金属具有比所述导电特征的氧化倾向大的氧化倾向。

Image sensor device

Methods of forming a back side image sensor device, as well as back side image sensor devices formed, are disclosed. In one such a method, an image sensor wafer having a first dielectric layer with a first surface is obtained. A reconstituted wafer having a processor die and a second dielectric layer with a second surface is obtained. The reconstituted wafer and the image sensor wafer are bonded to one another including coupling the first surface of the first dielectric layer and the second surface of the second dielectric layer. In another method, such formation is for a processor die bonded to an image sensor wafer. In yet another method, such formation is for a processor die bonded to an image sensor die.

功率半导体模块

本发明的功率半导体模块具备：金属底板；绝缘基板，配设于上述金属底板上，并具有电极；半导体元件，配设于上述绝缘基板上；壳体，以包围上述绝缘基板及上述半导体元件的方式配设于上述金属底板；以及灌封密封剂，被填充于由上述金属底板和上述壳体包围的空间内而密封上述绝缘基板及上述半导体元件，上述灌封密封剂具备硅胶和导电性赋予剂，该导电性赋予剂被添加到上述凝胶，并含有硅原子和离子基团。

Semiconductor packages with stacked dies and methods of forming the same

A semiconductor package includes a first semiconductor die, a second semiconductor die and a plurality of bumps. The first semiconductor die has a front side and a backside opposite to each other. The second semiconductor die is disposed at the backside of the first semiconductor die and electrically connected to first semiconductor die. The plurality of bumps is disposed at the front side of the first semiconductor die and physically connects first die pads of the first semiconductor die. A total width of the first semiconductor die may be less than a total width of the second semiconductor die.

Diffusion barriers and method of forming same

An element that is configured to bond to another element to define a bonded structure is disclosed. The element can include a dielectric bonding layer having a cavity that extends at least partially through a thickness of the dielectric bonding layer from a surface of the dielectric bonding layer. The element can also include a conductive feature that is at least partially disposed in the cavity. The conductive feature has a contact surface. The element can include a diffusion barrier layer between the conductive feature and a portion of the dielectric bonding layer. The barrier layer includes a barrier metal. The barrier metal of the diffusion barrier layer has an oxidation propensity that is greater than an oxidation propensity of the conductive feature.

功率半导体模块

本发明的功率半导体模块具备：金属底板；绝缘基板，配设于上述金属底板上，并具有电极；半导体元件，配设于上述绝缘基板上；壳体，以包围上述绝缘基板及上述半导体元件的方式配设于上述金属底板；以及灌封密封剂，被填充于由上述金属底板和上述壳体包围的空间内而密封上述绝缘基板及上述半导体元件，上述灌封密封剂具备硅胶和导电性赋予剂，该导电性赋予剂被添加到上述凝胶，并含有硅原子和离子基团。

Image sensor device

Methods of forming a back side image sensor device, as well as back side image sensor devices formed, are disclosed. In one such a method, an image sensor wafer having a first dielectric layer with a first surface is obtained. A reconstituted wafer having a processor die and a second dielectric layer with a second surface is obtained. The reconstituted wafer and the image sensor wafer are bonded to one another including coupling the first surface of the first dielectric layer and the second surface of the second dielectric layer. In another method, such formation is for a processor die bonded to an image sensor wafer. In yet another method, such formation is for a processor die bonded to an image sensor die.

Shield structures in microelectronic assemblies having direct bonding

Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component, having a first surface and an opposing second surface including a first direct bonding region at the second surface with first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component, having a first surface and an opposing second surface, including a second direct bonding region at the first surface with second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the second microelectronic component is coupled to the first microelectronic component by the first and second direct bonding regions; and a shield structure in the first direct bonding dielectric material at least partially surrounding the one or more of the first metal contacts.

用于互连的扩散阻挡衬层

本公开涉及一种用于互连的扩散阻挡衬层。技术和装置的代表性实施方式用于减少或防止导电材料扩散到结合衬底的绝缘材料或电介质材料中。由于重叠，错位的导电结构可以直接接触衬底的电介质部分，尤其是在采用直接结合技术的情况下。通常在重叠处将可以抑制扩散的阻挡界面设置在导电材料和电介质之间。

Chip-to-chip stacking by use of nickel tin metallization stacks and diffusion soldering

A method for fabricating a semiconductor device comprises comprisingproviding a substrate layer stack comprising a substrate with a metallic upper surface, a first Ni containing layer disposed on the substrate, and a first Sn layer on the first Ni containing layer (110);depositing a first semiconductor layer stack on the first Sn layer, the first semiconductor layer stack comprising a first NiP layer, a first semiconductor die disposed on the first NiP layer, and a second NiP layer disposed on the first semiconductor die (120);depositing a second semiconductor layer stack on the first semiconductor layer stack, the second semiconductor layer stack comprisinga second Sn layer, a second Ni containing layer disposed on the second Sn layer, and a second semiconductor die disposed on the second Ni containing layer (130); andperforming a diffusion soldering process for connecting the first semiconductor layer stack to the substrate and the second semiconductor layer stack to the first semiconductor layer stack (140).

直接键合方法和结构

一种键合方法可以包括使第一元件的第一键合层活化以用于到第二元件的第二键合层的直接键合。该键合方法可以包括：在活化之后，在第一元件的经活化的第一键合层之上提供保护层。

具有直接接合的微电子组件中的屏蔽结构

本文公开了微电子组件以及相关的设备和方法。在一些实施例中，微电子组件可以包括第一微电子部件，具有第一表面和相反的第二表面，所述第一微电子部件包括在第二表面处的第一直接接合区域，所述第一直接接合区域具有第一金属触点和在第一金属触点中的相邻第一金属触点之间的第一电介质材料；第二微电子部件，具有第一表面和相反的第二表面，所述第二微电子部件包括在第一表面处的第二直接接合区域，所述第二直接接合区域具有第二金属触点和在所述第二金属触点中的相邻第二金属触点之间的第二电介质材料，其中，所述第二微电子部件通过所述第一直接接合区域和所述第二直接接合区域耦接到所述第一微电子部件；以及在第一直接接合电介质材料中的屏蔽结构，至少部分地围绕所述第一金属触点中的一个或多个第一金属触点。

Chip-to-chip stacking by use of nickel tin metallization stacks and diffusion soldering

A method for fabricating a semiconductor device includes: providing a substrate layer stack including a substrate with a metallic upper surface, a first Ni containing layer disposed on the substrate, and a first Sn layer on the first Ni containing layer; depositing a first semiconductor layer stack on the first Sn layer and that includes a first NiP layer, a first semiconductor die disposed on the first NiP layer, and a second NiP layer disposed on the first semiconductor die; depositing a second semiconductor layer stack on the first semiconductor layer stack and that includes a second Sn layer, a second Ni containing layer disposed on the second Sn layer, and a second semiconductor die disposed on the second Ni containing layer; and performing a diffusion soldering process for connecting the first semiconductor layer stack to the substrate and the second semiconductor layer stack to the first semiconductor layer stack.

半导体装置

提供一种半导体装置，降低在半导体元件中发生的应力，并且抑制热电阻的增加，可靠性高。半导体装置具有：半导体芯片，在一方的面具有第1主电极，在另一方的面具有第2主电极以及栅电极；第1电极，经由第1接合材料而与半导体芯片的一方的面连接；以及第2电极，经由第2接合材料而与半导体芯片的另一方的面连接，其中，第1电极是板状的电极，在与半导体芯片重叠的区域中具有槽，槽具有在第1电极的厚度方向上贯通的结构，并且是在俯视观察时到达至第1电极的端部的形状。

显示设备及制造其的方法

本申请涉及显示设备和制造显示设备的方法。显示设备包括：衬底，包括显示区域和焊盘区域；多个焊盘电极，在衬底上设置在焊盘区域中；电路板，设置成在衬底上与焊盘区域的至少一部分重叠；以及各向异性导电层，设置在衬底和电路板之间的焊盘区域中。电路板包括基础衬底和设置在基础衬底的下表面上的多个凸起电极。各向异性导电层包括粘合层和布置在粘合层中的多个导电颗粒。导电颗粒中的每一个包括芯、以使得芯的至少一部分暴露的方式设置在芯上的第一导电膜、以及完全覆盖芯和第一导电膜的第二导电膜。

用于互连的扩散阻挡衬层

本公开涉及用于互连的扩散阻挡衬层。技术和装置的代表性实施方式用于减少或防止导电材料扩散到结合衬底的绝缘材料或电介质材料中。由于重叠，错位的导电结构可以直接接触衬底的电介质部分，尤其是在采用直接结合技术的情况下。通常在重叠处将可以抑制扩散的阻挡界面设置在导电材料和电介质之间。

半导体元件及其制备方法

本公开提供一种具有散热单元的半导体元件及该半导体元件的制备方法。该半导体元件具有一晶粒堆叠；一中介接合层，设置在该晶粒堆叠上；以及一载体结构。该载体结构包括一载体基底以及多个半导体贯穿通孔，该载体基底设置在该中介接合层上，所述半导体贯穿通孔设置在该载体基底中以及在该中介接合层上，以进行导热。

通过使用镍锡金属化堆叠体和扩散焊接实现的芯片到芯片堆叠

本文公开了通过使用镍锡金属化堆叠体和扩散焊接实现的芯片到芯片堆叠。一种用于制造半导体装置的方法包括：提供衬底层堆叠体，其包括具有金属上表面的衬底、设置在衬底上的第一含Ni层、以及第一含Ni层上的第一Sn层(110)；在第一Sn层上沉积第一半导体层堆叠体，其包括：第一NiP层、设置在第一NiP层上的第一半导体管芯、以及设置在第一半导体管芯上的第二NiP层(120)；在第一半导体层堆叠体上沉积第二半导体层堆叠体，其包括：第二Sn层、设置在第二Sn层上的第二含Ni层、以及设置在第二含Ni层上的第二半导体管芯(130)；以及执行用于将第一半导体层堆叠体连接到衬底并且将第二半导体层堆叠体连接到第一半导体层堆叠体的扩散焊接工艺(140)。

具有直接接合的微电子组件中的部件间材料

本文公开了包括通过直接接合耦合在一起的微电子部件的微电子组件以及相关的结构和技术。在一些实施例中，微电子组件可以包括中介层；第一微电子部件，具有通过第一直接接合区域耦合到中介层的第一表面和相对的第二表面；第二微电子部件，具有通过第二直接接合区域耦合到中介层的第一表面和相对的第二表面；衬垫材料，在中介层的表面上且在第一微电子部件和第二微电子部件周围；无机填充材料，在衬垫材料上且在第一微电子部件与第二微电子部件之间；以及第三微电子部件，耦合到第一微电子部件和第二微电子部件的第二表面。在一些实施例中，衬垫材料、无机填充材料和第三微电子部件的材料可以包括导热材料。

半导体封装件及其形成方法

一种半导体封装件，包括第一半导体管芯、第二半导体管芯、和多个凸块。第一半导体管芯具有彼此相对的正面和背面。第二半导体管芯设置在第一半导体管芯的背面，并且电连接至第一半导体管芯。多个凸块设置在第一半导体管芯的正面，并且物理接触第一半导体管芯的第一管芯焊盘。第一半导体管芯的总宽度小于第二半导体管芯的总宽度。本申请的实施例还提供了半导体封装件的形成方法。

具有直接键合界面的微电子组件的单体化

本文公开了与具有直接键合界面的微电子组件的单体化相关的结构和技术。例如，在一些实施例中，微电子组件可以包括：表面，其中，导电触点在所述表面处；在所述表面的周边处的沟槽；以及在沟槽中的毛刺。

半导体封装件

一种半导体封装件包括：第一结构，其具有设置在一个表面上的第一绝缘层以及穿透第一绝缘层的第一电极焊盘和第一虚设焊盘；第二结构，其具有设置在另一表面上的第二绝缘层以及第二电极焊盘和第二虚设焊盘，第二绝缘层使所述另一表面键合到所述一个表面和第一绝缘层，第二电极焊盘和第二虚设焊盘穿透第二绝缘层，第二电极焊盘分别键合到第一电极焊盘，并且第二虚设焊盘分别键合到第一虚设焊盘。在半导体芯片中，在所述一个表面上第一虚设焊盘与第一绝缘层的每单位面积的表面积之比和在所述另一表面上第二虚设焊盘与第二绝缘层的每单位面积的表面积之比朝向第一结构和第二结构的侧表面逐渐减小。

其中嵌入有电子组件的基板

本公开提供一种其中嵌入有电子组件的基板，所述其中嵌入有电子组件的基板包括：芯结构，具有腔；金属层，设置在所述芯结构的所述腔的底表面上；以及电子组件，设置在所述芯结构的所述腔中的所述金属层上。所述其中嵌入有电子组件的基板具有优异的散热效果。

半导体封装和包括该半导体封装的层叠封装

本公开公开了一种半导体封装，包括：第一布线结构；半导体芯片，被设置在第一布线结构上；第二布线结构，被设置在半导体芯片上并且包括腔体；以及填充构件，在第一布线结构和第二布线结构之间并且在腔体中，其中填充构件的最上端和第二布线结构的最上端位于相同的高度水平处。

半导体封装件和制造半导体封装件的方法

一种半导体器件封装件包括在界面处直接接合至第二管芯的第一管芯，其中该界面包括导体与导体键。该半导体器件封装件还包括围绕该第一管芯和该第二管芯的密封剂以及延伸穿过该密封剂的多个贯通孔。该多个贯通孔邻近该第一管芯和该第二管芯设置。该半导体器件封装件还包括延伸穿过该密封剂的多个热通孔以及电连接至该第一管芯、该第二管芯、和该多个贯通孔的再分布结构。该多个热通孔在该第二管芯的表面上并与第一管芯相邻地设置。根据本申请的实施例，还提供了制造半导体封装件的方法。

Singulation of microelectronic components with direct bonding interfaces

Disclosed herein are structures and techniques related to singulation of microelectronic components with direct bonding interfaces. For example, in some embodiments, a microelectronic component may include: a surface, wherein conductive contacts are at the surface; a trench at a perimeter of the surface; and a burr in the trench.

用于互连的扩散阻挡衬层

技术和装置的代表性实施方式用于减少或防止导电材料扩散到结合衬底的绝缘材料或电介质材料中。由于重叠，错位的导电结构可以直接接触衬底的电介质部分，尤其是在采用直接结合技术的情况下。通常在重叠处将可以抑制扩散的阻挡界面设置在导电材料和电介质之间。

拡散バリヤ及び拡散バリヤの形成方法

素子が開示され、この素子は、別の素子に結合するよう構成されている。素子は、誘電体ボンディング層を有するのがよく、誘電体ボンディング層は、誘電体ボンディング層の表面から誘電体ボンディング層の厚みを少なくとも部分的に貫通して延びるキャビティを有する。素子は、キャビティ内に少なくとも部分的に設けられた特徴部をさらに有するのがよい。素子は、導電特徴部と誘電体ボンディング層の一部分との間に拡散バリヤ層を有するのがよい。バリヤ層は、バリヤ金属を含む。拡散バリヤ層のバリヤ金属は、導電特徴部の酸化傾向よりも高い酸化傾向を有する。

Direct bonding methods and structures

半导体模块、显示装置及半导体模块的制造方法

树脂(16)覆盖蓝色LED(15)的侧面及背面，且将蓝色LED(15)保持为水平。电极(14)设于配线基板(11)的表面与蓝色LED(15)的背面之间，贯穿树脂(16)，且将配线基板(11)与蓝色LED(15)电连接。蓝色LED(15)的光出射面(表面)(151)自树脂(16)露出，将光出射面(表面)(151)与树脂(16)的表面(161)配置于同一平面。

功率半导体模块

本发明的功率半导体模块具备：金属底板；绝缘基板，配设于上述金属底板上，并具有电极；半导体元件，配设于上述绝缘基板上；壳体，以包围上述绝缘基板及上述半导体元件的方式配设于上述金属底板；以及灌封密封剂，被填充于由上述金属底板和上述壳体包围的空间内而密封上述绝缘基板及上述半导体元件，上述灌封密封剂具备硅胶和导电性赋予剂，该导电性赋予剂被添加到上述凝胶，并含有硅原子和离子基团。

半导体结构及其制作方法

本发明实施例涉及半导体结构及其制作方法。根据本发明的一些实施例，一种半导体结构包含：衬底；第一裸片，其安置在所述衬底之上；第二裸片，其安置在所述衬底之上；模制物，其安置在所述衬底之上且环绕所述第一裸片及所述第二裸片；互连结构，其包含介电层及导电部件，其中所述介电层安置在所述第一裸片、所述第二裸片及所述模制物之上，且所述导电部件由所述介电层环绕；及通路，其延伸于所述第二裸片内且延伸于所述介电层与所述衬底之间。

Semiconductor device and method of forming wire bondable fan-out EWLB package

A semiconductor device has a first semiconductor die and a first encapsulant deposited over the first semiconductor die. An interconnect structure is formed over the first semiconductor die and first encapsulant. A modular interconnect structure including a conductive via is disposed adjacent to the first semiconductor die. The first encapsulant is deposited over the modular interconnect structure. An opening is formed in the first encapsulant extending to the modular interconnect structure or to the interconnect structure. A second semiconductor die is disposed over the first semiconductor die. A bond wire is formed over the second semiconductor die and extends into the opening in the first encapsulant. A cap is formed over an active region of the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and bond wire. Alternatively, a lid is formed over the second semiconductor die and bond wire.