A process for bonding substrates

Die vorliegende Erfindung betrifft ein Verfahren zum Bonden eines ersten Substrats (4) mit einem zweiten Substrat (4'), dadurch gekennzeichnet, dass das erste Substrat ( 4) und/oder das zweite Substrat (4') vor dem Bonden gedünnt ist/wird.

Semiconductor package and method of manufacturing semiconductor package

Light emitting device

A light emitting device includes a carrier, at least one epitaxial structure, at least one buffer pad and at least one bonding pad. The epitaxial structure is disposed on the carrier. The buffer pad is disposed between the carrier and the epitaxial structure, wherein the epitaxial structure is temporarily bonded to the carrier by the buffer pad. The bonding pad is disposed on the epitaxial structure, wherein the epitaxial structure is electrically connected to a receiving substrate by the bonding pad.

Substrate, method of fabricating the same, and application the same

Provided is a substrate, including a substrate material, two conductive structures, and at least one diode. The two conductive structures extend from a first surface of the substrate material to a second surface of the substrate material via two through holes penetrating through the substrate material. The at least one diode is embedded in the substrate material at a sidewall of one of the through holes.

METHOD FOR FABRICATING A MICRO-WELL OF A BIOSENSOR

A bio-sensing semiconductor structure is provided. A transistor includes a channel region and a gate underlying the channel region. A first dielectric layer overlies the transistor. A first opening extends through the first dielectric layer to expose the channel region. A bio-sensing layer lines the first opening and covers an upper surface of the channel region. A second dielectric layer lines the first opening over the bio-sensing layer. A second opening within the first opening extends to the bio-sensing layer, through a region of the second dielectric layer overlying the channel region. A method for manufacturing the bio-sensing semiconductor structure is also provided.

Bond pads for low temperature hybrid bonding

Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip.

SOLDER BALL, MANUFACTURING METHOD THEREOF, AND ELECTRONIC COMPONENT USING SAME

In the present specification, disclosed are a solder ball used in a semiconductor package, a manufacturing method thereof, and an electronic component including the same. More particularly, disclosed is a solder ball which can be applied to all technical fields based on the bonding of the solder ball, and particularly, can be used in a semiconductor package using the solder ball as a connection base in an electronic industry field. The solder ball maintains a shape of a core including metal with a low melting point even in a reflow and has stable bonding reliability with a substrate. COPYRIGHT KIPO 2017 (AA) Second metal layer (BB) First metal layer ...

METHOD OF MANUFACTURING ELEMENT CHIP, METHOD OF MANUFACTURING ELECTRONIC COMPONENT-MOUNTED STRUCTURE, AND ELECTRONIC COMPONENT-MOUNTED STRUCTURE

In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate which has a plurality of element regions and of which an element surface is covered by insulating film, the substrate is divided into element chips by exposing the substrate to a first plasma, element chips having first surface, second surface, and side surface are held spaced from each other on carrier, insulating film is in a state of being exposed, recessed portions are formed by retreating insulating film by exposing element chips to second plasma for ashing, and then recessed portions are covered by protection films by third plasma for formation of the protection film, thereby suppressing creep-up of the conductive material to side surface in the mounting step.

ROOM TEMPERATURE METAL DIRECT BONDING

COPPER STRUCTURES WITH INTERMETALLIC COATING FOR INTEGRATED CIRCUIT CHIPS

An integrated circuit (IC) chip includes a copper structure with an intermetallic coating on the surface. The IC chip includes a substrate with an integrated circuit. A metal pad electrically connects to the integrated circuit. The copper structure electrically connects to the metal pad. A solder bump is disposed on the copper structure. The surface of the copper structure has a coating of intermetallic. The copper structure can be a redistribution layer and a copper pillar that is disposed on the redistribution layer.

INTEGRIERTE SCHALTUNG, CHIPGEHÄUSE UND VERFAHREN ZUR HERSTELLUNG EINER INTEGRIERTEN SCHALTUNG

Bereitgestellt ist eine integrierte Schaltung, die Folgendes aufweist: einen Träger, der zumindest ein elektronisches Bauteil und zumindest eine Kontaktfläche, die auf einer ersten Seite des Trägers angeordnet ist, aufweist, wobei das zumindest eine elektronische Bauteil mit der zumindest einen Kontaktfläche elektrisch verbunden ist; eine anorganische Materialschicht, die mittels Waferbonden mit der ersten Seite des Trägers verbunden ist, wobei der Träger einen ersten Wärmeausdehnungskoeffizienten aufweist, und wobei die anorganische Materialschicht einen zweiten Wärmeausdehnungskoeffizienten aufweist, wobei der zweite Wärmeausdehnungskoeffizient einen Unterschied von weniger als 100% zum ersten Wärmeausdehnungskoeffizienten aufweist; und zumindest eine Durchkontaktierung, die durch die anorganische Materialschicht ausgebildet ist, wobei die zumindest eine Durchkontaktierung mit der zumindest einen Kontaktfläche in Kontakt ist. An integrated circuit is provided which has the following: a carrier which has at least one electronic component and at least one contact surface which is arranged on a first side of the carrier, the at least one electronic component being electrically connected to the at least one contact surface; an inorganic material layer bonded to the first side of the carrier by wafer bonding, the carrier having a first coefficient of thermal expansion, and the inorganic material layer having a second coefficient of thermal expansion, the second coefficient of thermal expansion being less than 100% different from the first coefficient of thermal expansion; and at least one via formed through the inorganic material layer, the at least one via being in contact with the at least one contact area.

3D Compute circuit with high density z-axis interconnects

Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In this arrangement, several circuit blocks defined on each die (1) overlap with other circuit blocks defined on one or more other dies, and (2) electrically connect to these other circuit blocks through connections that cross one or more bonding layers that bond one or more pairs of dies. In some embodiments, the overlapping, connected circuit block pairs include pairs of computation blocks and pairs of computation and memory blocks. The connections that cross bonding layers to electrically connect circuit blocks on different dies are referred to below as z-axis wiring or connections. This is because these connections traverse completely or mostly in the z-axis of the 3D circuit, with the x-y axes of the 3D circuit defining the planar surface of the IC die substrate or interconnect layers. These connections are also referred to as vertical connections to differentiate them from the horizontal planar connections along the interconnect layers of the IC dies.

Method for bonding substrates

A method for bonding a first substrate with a second substrate, characterized in that the first substrate and/or the second substrate is/are thinned before the bonding.

Semiconductor manufacturing method and associated semiconductor manufacturing system

Method of manufacturing semiconductor package structure

A method of manufacturing a semiconductor package structure includes the following steps. A die is bonded to a wafer. A dielectric material layer is formed on the wafer and the die. The dielectric material layer covers a top surface and sidewalls of the die. At least one planarization process is performed to remove a portion of the dielectric material layer and a portion of the die, such that the top surface of the die is exposed and a dielectric layer aside the die is formed. The dielectric layer surrounds and covers the sidewalls of the die.

Method for manufacturing chip cards and chip card obtained by said method

The invention relates to a chip card manufacturing method. According to this method, there are produced on the one hand, a module including a substrate supporting contacts on one face, and bonding pads on the other, on the other hand, an antenna on a support. The ends of the antenna are linked to lands of connection lands receiving a drop of soldering material on a connection portion. In order to make the soldered electrical connection between the module and the antenna reliable, the bonding pads extend over a zone covering a surface area less than that of the connection portions. The invention relates also to a chip card whose module includes bonding pads extending over a zone covering a surface area less than that of the connection portions.

Semiconductor package and method of fabricating a semiconductor package

In an embodiment, a semiconductor package includes a package footprint having a plurality of solderable contact pads, a semiconductor device having a first power electrode and a control electrode on a first surface and a second power electrode on a second surface, a redistribution substrate having an insulating board, wherein the first power electrode and the control electrode are mounted on a first major surface of the insulating board and the solderable contact pads of the package footprint are arranged on a second major surface of the insulating board, and a contact clip having a web portion and one or more peripheral rim portions. The web portion is mounted on and electrically coupled to the second power electrode and the peripheral rim portion is mounted on the first major surface of the insulating board.

METHOD AND DEVICE FOR TRANSFERRING COMPONENTS

Method of manufacturing element chip, method of manufacturing electronic component-mounted structure, and electronic component-mounted structure

To provide a method of manufacturing an element chip in which creep-up of a conductive material can be suppressed in a mounting step. In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate which has a plurality of element regions and of which an element surface is covered by an insulating film, the substrate is divided into the element chips by exposing the substrate to a first plasma, the element chips having a first surface, a second surface, and a side surface are held spaced from each other on a carrier, and the side surface and the insulating film are in a state of being exposed.

Integrated circuit chip with copper structure and related manufacturing method

Semiconductor device, metal member, and method of manufacturing semiconductor device

ROOM TEMPERATURE METAL DIRECT BONDING

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

In a method for manufacturing a semiconductor device according to the present invention, as shown in FIG. 2(A), a case (2) including a first terminal (1) is placed on a working table (3) with an opening (30) formed at the bottom of the case (2). Subsequently, as shown in FIG. 2(B), a plurality of packages (6,6,6) including second terminals (4) are placed on the working table (3) through the opening (30) of the case (2), forming a clearance (31) between the first terminal (1) and the second terminal (4). As shown in FIG. 2(C), a bonding material (7) is disposed in the clearance (31) so as to electrically connect the first terminal (1) and the second terminal (4). Thus, the exposed surfaces of the packages (6,6,6) in the opening (30) of the case (2) are aligned at the same height, thereby reducing variations in thermal resistance among the packages (6,6,6).

Strombegrenzungsvorrichtung

Strombegrenzungsvorrichtung umfassend eine elektrisch leitfähige Schicht mit einem im Wesentlichen konstanten Widerstand, dadurch gekennzeichnet, dass die Strombegrenzungsvorrichtung ferner umfasst: – ein n-dotiertes Halbleitergebiet mit flächiger Grundform, welches mit der elektrisch leitfähigen Schicht elektrisch verbunden ist, und mindestens ein von p-dotiertes Halbleitergebiet aufweist, – mindestens eine elektrische Leitung zur Kontaktierung des mindestens einen p-dotierten Halbleitergebiets mit einer Stromzuführung der elektrisch leitfähigen Schicht, die von der elektrisch leitfähigen Schicht und dem n-dotierten Halbleitergebiet elektrisch isoliert ist.

INTEGRATED CIRCUIT, A CHIP PACKAGE AND A METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT

An integrated circuit is provided, the integrated circuit including: a carrier including at least one electronic component and at least one contact area disposed on a first side of the carrier, wherein the at least one electronic component is electrically connected to the at least one contact area; an inorganic material layer wafer bonded to the first side of the carrier, wherein the carrier has a first coefficient of thermal expansion, and wherein the inorganic material layer has a second coefficient of thermal expansion, wherein the second coefficient of thermal expansion has a difference of less than 100% compared with the first coefficient of thermal expansion; and at least one contact via formed through the inorganic material layer, wherein the at least one contact via contacts the at least one contact area.

SEMICONDUCTOR LASER STRUCTURE

A semiconductor laser structure is provided. The semiconductor laser comprises a central thermal shunt, a ring shaped silicon waveguide, a contiguous thermal shunt, an adhesive layer and a laser element. The central thermal shunt is located on a SOI substrate which has a buried oxide layer surrounding the central thermal shunt. The ring shaped silicon waveguide is located on the buried oxide layer and surrounds the central thermal shunt. The ring shaped silicon waveguide includes a P-N junction of a p-type material portion, an n-type material portion and a depletion region there between. The contiguous thermal shunt covers a portion of the buried oxide layer and surrounds the ring shaped silicon waveguide. The adhesive layer covers the ring shaped silicon waveguide and the buried oxide layer. The laser element covers the central thermal shunt, the adhesive layer and the contiguous thermal shunt.

Magnet assisted alignment method for wafer bonding and wafer level chip scale packaging

A high-precision alignment method with high throughput is proposed, which can be used for wafer-to-wafer, chip-to-wafer or chip-to-chip bonding. The scheme implements pairing patterned magnets predetermined designed and made using wafer level process on two components (wafer or chip). The magnetization in patterned magnet can be set at predetermined configuration before bonding starts. When, the two components are bought to close proximity after a coarse alignment, the magnetic force will bring the magnet pairs together and aligned the patterned magnet on one component with its mirrored or complimentary patterned magnets on the other component to minimize the overall the magnetic energy of the pairing magnet. A few patterned magnet structures and materials, with their unique merits are proposed as examples for magnet pair for the self-alignment purpose. This method enables solid contact at the bonding interface via patterned magnets under the magnetic force, which avoid the wafer drafting ...

The base plate, its manufacturing method and its application

Semiconductor device and method of manufacturing the same

A semiconductor device includes first and second semiconductor members and a first barrier film. The first semiconductor member includes a first insulating film, and a first wiring film in the first insulating film, the surface of which is exposed in the first insulating film. The second semiconductor member includes a second insulating film, and a second wiring film in the second insulating film, the surface of which is exposed in the second insulating film. The first barrier film forms a barrier to diffusion of the material of the first wiring film into the second insulating film and is formed of a compound of metal element of the first wiring film and an element of the second insulating film in a region where the first wiring film and the second insulating film are in contact with each other at the junction interface of the first and second semiconductor members.

ROOM TEMPERATURE METAL DIRECT BONDING

Semiconductor device and method for manufacturing a semiconductor device

A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

3D INTEGRATION STRUCTURE AND METHOD USING BONDED METAL PLANES

3D 집적회로들을 만드는 방법 및 3D 집적회로 구조가 개시된다. 이와 같은 본 발명은 제2 반도체 구조에 결합된 제1 반도체 구조를 포함한다. 각각의 반도체 구조는 반도체 웨이퍼, 상기 반도체 웨이퍼 상의 FEOL 배선(front end of the line(FEOL) wiring), 상기 FEOL 배선 상의 BEOL 배선(back end of the line(BEOL) wiring), 상기 BEOL 배선 상의 절연체층 및 상기 절연체층 상의 금속층을 포함한다. 상기 반도체 구조들 각각의 금속층들이 서로 마주보도록, 상기 제1 반도체 구조는 상기 제2 반도체 구조와 정렬(align)된다. 상기 반도체 구조들 각각의 금속층들은 금속 대 금속 결합(metal to metal bond)에 의해 접촉되어 서로 연결된다. 상기 결합된 금속층들은 전기적으로 절연된 층을 형성한다. A method of making 3D integrated circuits and a 3D integrated circuit structure are disclosed. This invention includes a first semiconductor structure coupled to a second semiconductor structure. Each semiconductor structure includes a semiconductor wafer, a front end of the line (FEOL) wiring on the semiconductor wafer, a back end of the line (BEOL) wiring on the FEOL wiring, and an insulator layer on the BEOL wiring. And a metal layer on the insulator layer. The first semiconductor structure is aligned with the second semiconductor structure such that the metal layers of each of the semiconductor structures face each other. The metal layers of each of the semiconductor structures are contacted and connected to each other by a metal to metal bond. The combined metal layers form an electrically insulated layer.

ROOM TEMPERATURE METAL DIRECT BONDING

A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed. 1. (canceled)2. A method of bonding substrates , comprising:providing a first substrate having a first non-metallic region proximate to a first plurality of metallic pads;providing a second substrate having a second non-metallic region proximate to a second plurality of metallic pads;directly contacting the first non-metallic region with the second non-metallic region, wherein a first pad of the first plurality of metallic pads is spaced from a second pad of the second plurality of metallic pads by a gap after directly contacting the first non-metallic region with the second non-metallic region;non-adhesively bonding the first non-metallic region to the second non-metallic region; andafter directly contacting the first non-metallic region with the second non-metallic region, forming a contact between the first pad and the second pad.3. The method of claim 2 , wherein forming the contact comprises heating the first and second substrates in a range of about 100-250° C.4. The method of claim 2 , wherein directly contacting and non-adhesively bonding is conducted at room temperature.5. The method of claim 2 , wherein forming the contact comprises heating the first pad and the second pad to cause at least portions ...

Semiconductor apparatus and method for preparing the same

The present disclosure is directed to a method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The method includes the steps of forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.

Interconnect chips

A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

Semiconductor Package with Low Parasitic Connection to Passive Device

A semiconductor assembly includes a semiconductor package that includes first and second transistor dies embedded within a package body, the first and second transistor dies being arranged laterally side by side within the package body such that a first load terminal of the first transistor die faces an upper surface of the package body and such that a second load terminal of the second transistor die faces the upper surface of the package body, and a discrete capacitor mounted on the semiconductor package such that a first terminal of the discrete capacitor is directly over and electrically connected to the first load terminal of the first semiconductor die and such that a second terminal of the discrete capacitor is directly over and electrically connected with the second load terminal of the second semiconductor die.

ZWISCHENVERBINDUNGS-CHIPS

Ein Verfahren umfasst das Bonden eines ersten Vorrichtungs-Dies und eines zweiten Vorrichtungs-Dies mit einem Zwischenverbindungs-Die. Der Zwischenverbindungs-Die umfasst einen ersten Abschnitt, der über dem ersten Vorrichtungs-Die liegt und an diesen gebondet ist, und einen zweiten Abschnitt, der über dem zweiten Vorrichtungs-Die liegt und an diesen gebondet ist. Der Zwischenverbindungs-Die verbindet den ersten Vorrichtungs-Die elektrisch mit dem zweiten Vorrichtungs-Die. Das Verfahren umfasst ferner das Verkapseln des Zwischenverbindungs-Dies in ein Verkapselungsmaterial und das Ausbilden einer Mehrzahl von Umverteilungsleitungen über dem Zwischenverbindungs-Die.

Semiconductor-on-insulator with back side strain topology

Embodiments of the present invention provide for the enhancement of transistors in a semiconductor structure using a strain layer. The structure comprises a patterned layer consisting of an excavated region and a pattern region, a strain layer located in the excavated region and on the pattern region, an active layer located above the strain layer, a field effect transistor formed in the active layer, and a handle layer located above the active layer. The field effect transistor comprises a source, a drain, and a channel. The channel lies completely within a lateral extent of the pattern region. The source and the drain each lie only partially within the lateral extent of the pattern region. The strain layer alters a carrier mobility of the channel. In some embodiments, the strain layer is introduced to the back side of a semiconductor-on-insulator structure.

Semiconductor manufacturing method and associated semiconductor manufacturing system

A semiconductor manufacturing method is disclosed. The method includes: providing a first wafer and a second wafer, wherein the first wafer and the second wafer are bonded together; submerging the bonded first and second wafers in an ultrasonic transmitting medium; producing ultrasonic waves; and directing the ultrasonic waves to the bonded first and second wafers through the ultrasonic transmitting medium for a predetermined time period. An associated semiconductor manufacturing system for at least weakening a bonding strength of bonded wafers is also disclosed.

Used in the wafer bonding the sacrificial aligned welding hole

Interconnect chips

A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

TRANSISTOR FORMATION USING COLD WELDING

A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device.

Display device and method for fabricating the same

A display device comprises a substrate, a pixel electrode on the substrate, a light emitting element on the pixel electrode, and a common electrode layer on the light emitting element, and configured to receive a common voltage, wherein the light emitting element configured to emit a first light according to a driving current having a first current density, is configured to emit a second light according to a driving current having a second current density, and is configured to emit a third light according to a driving current having a third current density.

For the production of biological sensor micro pitfall method

ROOM TEMPERATURE METAL DIRECT BONDING

SEMICONDUCTOR APPARATUS AND METHOD FOR PREPARING THE SAME

The present disclosure is directed to a method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The method includes the steps of forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.

Method for bonding substrates

This invention relates to a method for bonding a first substrate (4) with a second substrate (4'), characterized in that the first substrate (4) and/or the second substrate (4') is/are thinned before the bonding.

METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE STRUCTURE

A method of manufacturing a semiconductor package structure includes: bonding a die to a wafer; forming a dielectric material layer on the wafer to cover a top surface and sidewalls of the die; performing a removal process to remove a portion of the dielectric material layer, so as to at least expose a portion of the top surface of the die, wherein the dielectric material layer comprises a protruding part over the top surface of the die after performing the removal process; and performing a planarization process to planarize top surfaces of the die and the dielectric material layer, and thereby forming a dielectric layer laterally aside the die. 1. A method of manufacturing a semiconductor package structure , comprising:bonding a die to a wafer;forming a dielectric material layer on the wafer to cover a top surface and sidewalls of the die;performing a removal process to remove a portion of the dielectric material layer, so as to at least expose a portion of the top surface of the die, wherein the dielectric material layer comprises a protruding part over the top surface of the die after performing the removal process; andperforming a planarization process to planarize top surfaces of the die and the dielectric material layer, and thereby forming a dielectric layer laterally aside the die.2. The method of claim 1 , wherein the protruding part covers top corners of the die.3. The method of claim 1 , wherein after performing the removal process claim 1 , the top surface of the die is completely exposed claim 1 , and the protruding part is adjacent to top corners of the die.4. The method of claim 1 , whereinthe dielectric material comprises a body part laterally aside the die and a protrusion on the body part and the die; andthe protrusion covers the top surface of the die and a portion of the body part.5. The method of claim 4 , wherein the performing the removal process comprises:forming a mask to cover a top surface of the body part and a sidewall of the protrusion; ...

Room temperature metal direct bonding

A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.

Semiconductor structure and method for manufacturing the same

A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate including a front surface and a back surface; a backside metallization layer formed over the semiconductor substrate, the backside metallization layer being closer to the back surface than to the front surface of the semiconductor substrate, at least a portion of the backside metallization layer forming an inductor structure; and an electrically non-conductive material formed in the semiconductor substrate, the electrically non-conductive material at least partially overlapping the inductor structure from a top view, and the electrically non-conductive material including a top surface, a bottom surface, and sidewalls, the top surface being adjacent to the back surface of the semiconductor substrate. A method for manufacturing a semiconductor structure is also disclosed.

Room temperature metal direct bonding

A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.

Sacrificial alignment ring and self-soldering vias for wafer bonding

A method of bonding a first substrate to a second substrate, wherein the first substrate includes first electrical contacts on a top surface of the first substrate, and wherein the second substrate includes second electrical contacts on a bottom surface of the second substrate. The method includes forming a block of polyimide on the top surface of the first substrate, wherein the block of polyimide has a rounded upper corner, and vertically moving the top surface of the first substrate and the bottom surface of the second substrate toward each other until the first electrical contacts abut the second electrical contacts, wherein during the moving, the second substrate makes contact with the rounded upper corner of the polyimide causing the first and second substrates to move laterally relative to each other.

Room temperature metal direct bonding

A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.

Sacrificial alignment ring and self-soldering vias for wafer bonding

一種將一第一基材接合至一第二基材之方法，其中該第一基材包括在該第一基材之一頂部表面上之第一電氣接觸件，且其中該第二基材包括在該第二基材之一底部表面上之第二電氣接觸件。該方法包括在該第一基材之該頂部表面上形成聚醯亞胺之一塊體，其中聚醯亞胺之該塊體具有一圓化上隅角，且將該第一基材之該頂部表面及該第二基材之該底部表面朝向彼此垂直移動，直到該等第一電氣接觸件毗連該等第二電氣接觸件，其中該第二基材在該移動期間與該聚醯亞胺之該圓化上隅角接觸，造成該第一基材及該第二基材相對於彼此橫向移動。

3D INTEGRATION STRUCTURE AND METHOD USING BONDED METAL PLANES

PURPOSE: A 3D integration structure and method using bonded metal planes are provided to connect metal layers through metal to metal. CONSTITUTION: A second semiconductor structure(20) comprises a semiconductor wafer having devices(23), a BEOL wiring(24), an insulating layer(26), oxide, and a metal layer(28). The second semiconductor structure is similar to that of the first semiconductor structure(10). The first and second semiconductor structure have different functions while a metal layer having holes. COPYRIGHT KIPO 2011 ...

BOND PADS FOR LOW TEMPERATURE HYBRID BONDING

Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip. 116-. (canceled)17. A method of manufacturing , comprising: fabricating first conductor pads in a first glass layer of a first semiconductor chip; planarizing the first glass layer by chemical mechanical polishing; planarizing the first glass layer and the first conductor pads by machining , the first conductor pads being configured to bumplessly connect to corresponding plural conductor pads of a second semiconductor chip to make up a plurality of interconnects that connect the first semiconductor chip to the second semiconductor chip; and treating the first glass layer to render it hydrophillic to facilitate bonding to a second glass layer of the second semiconductor chip.18. The method of claim 17 , comprising mounting the second semiconductor chip on the first semiconductor chip and electrically connecting the first semiconductor chip to the second semiconductor chip with the plurality of conductor pads of the first semiconductor chip.19. The method of claim 18 , wherein the electrically connecting the first semiconductor chip to the second semiconductor chip with the plurality of interconnects comprises annealing to bond the first glass layer to the second glass layer and cause the first conductor pads and the second conductor pads to plastically deform and bond together.20. A method of ...

ROOM TEMPERATURE METAL DIRECT BONDING

A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate including a front surface and a back surface; a backside metallization layer formed over the semiconductor substrate, the backside metallization layer being closer to the back surface than to the front surface of the semiconductor substrate, at least a portion of the backside metallization layer forming an inductor structure; and an electrically non-conductive material formed in the semiconductor substrate, the electrically non-conductive material at least partially overlapping the inductor structure from a top view, and the electrically non-conductive material including a top surface, a bottom surface, and sidewalls, the top surface being adjacent to the back surface of the semiconductor substrate. A method for manufacturing a semiconductor structure is also disclosed.

Halbleiterbauelement und Verfahren zum Fertigen eines Halbleiterbauelements

Ein Bauelement beinhaltet einen ersten Halbleiterchip, der eine erste Fläche beinhaltet, wobei eine erste Kontaktstelle über der ersten Fläche angeordnet ist. Das Bauelement beinhaltet weiter einen zweiten Halbleiterchip, der eine erste Fläche beinhaltet, wobei eine erste Kontaktstelle über der ersten Fläche angeordnet ist, wobei der erste Halbleiterchip und der zweite Halbleiterchip so angeordnet sind, dass die erste Fläche des ersten Halbleiterchips in eine erste Richtung zeigt und die erste Fläche des zweiten Halbleiterchips in eine zur ersten Richtung entgegengesetzte zweite Richtung zeigt. Der erste Halbleiterchip befindet sich seitlich außerhalb von einer Außenlinie des zweiten Halbleiterchips. A device includes a first semiconductor chip that includes a first surface, wherein a first contact location is disposed over the first surface. The device further includes a second semiconductor chip including a first surface, wherein a first pad is disposed over the first surface, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first surface of the first semiconductor chip faces in a first direction shows the first surface of the second semiconductor chip in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

A separation circuit components stacked connection realizing method and circuit

Method of manufacturing semiconductor package structure

A method of manufacturing a semiconductor package structure includes the following steps. A die is bonded to a wafer. A dielectric material layer is formed on the wafer and the die. The dielectric material layer covers a top surface and sidewalls of the die. At least one planarization process is performed to remove a portion of the dielectric material layer and a portion of the die, such that the top surface of the die is exposed and a dielectric layer aside the die is formed. The dielectric layer surrounds and covers the sidewalls of the die.

METHOD FOR BONDING SUBSTRATES

Verfahren zum Bonden von Substraten

Semiconductor-on-insulator with back side heat dissipation

本发明实施例实现了从绝缘体上半导体(SOI)结构去除过剩载流子。在一个实施例中，公开了一种制造集成电路的方法。在一个步骤中，在绝缘体上半导体晶圆的有源层中形成有源器件。在另一个步骤中，从沉积在所述SOI晶圆的背侧上的基板层区域基板材料。在另一个步骤中，从所述绝缘体上半导体晶圆的背侧去除绝缘材料以形成挖掉的绝缘区域。导电层沉积在所述挖掉的绝缘区域上。沉积导电层使所述导电层与所述挖掉的绝缘区域的第一部分中的有源器件的体区物理接触。随后导电层将所述体区耦接至一个接触，所述接触处于所述挖掉的绝缘区域的第二隔开的部分中。

SPANNUNGSKOMPENSATION FÜR WAFER-AN-WAFER-BONDEN

Ausführungsformen hierin beschreiben Techniken für gebondete Wafer, die einen ersten Wafer, der mit einem zweiten Wafer gebondet ist, und eine Spannungskompensationsschicht in Kontakt mit dem ersten Wafer oder dem zweiten Wafer beinhalten. Der erste Wafer weist ein erstes Spannungsniveau an einer ersten Stelle und ein zweites Spannungsniveau, das von dem ersten Spannungsniveau verschieden ist, an einer zweiten Stelle auf. Die Spannungskompensationsschicht beinhaltet ein erstes Material an einer ersten Stelle der Spannungskompensationsschicht, das ein drittes Spannungsniveau an der ersten Stelle des ersten Wafers beinhaltet, ein zweites Material, das von dem ersten Material verschieden ist, an einer zweiten Stelle der Spannungskompensationsschicht, das ein Spannungsniveau, das von dem dritten Spannungsniveau verschieden ist, an der zweiten Stelle des ersten Wafers induziert. Andere Ausführungsformen können beschrieben und/oder beansprucht werden.

Sacrificial alignment ring and self-soldering vias for wafer bonding

一種將一第一基材接合至一第二基材之方法，其中該第一基材包括在該第一基材之一頂部表面上之第一電氣接觸件，且其中該第二基材包括在該第二基材之一底部表面上之第二電氣接觸件。該方法包括在該第一基材之該頂部表面上形成聚醯亞胺之一塊體，其中聚醯亞胺之該塊體具有一圓化上隅角，且將該第一基材之該頂部表面及該第二基材之該底部表面朝向彼此垂直移動，直到該等第一電氣接觸件毗連該等第二電氣接觸件，其中該第二基材在該移動期間與該聚醯亞胺之該圓化上隅角接觸，造成該第一基材及該第二基材相對於彼此橫向移動。

Optical coupling module

An optical coupling module includes a silicon photonic substrate, and an optical waveguide module. The silicon photonic substrate has a first surface and a first grating on the first surface for diffracting the light which passes through the grating. The optical waveguide module is disposed on the silicon photonic substrate, wherein the optical waveguide module includes an optical waveguide having an end disposed in corresponding to the first grating of the silicon photonic substrate. Otherwise, the optical waveguide module has a reflective surface coupled to the end of the optical waveguide and adapted to reflect the light emerging from or incident into the grating to form an optical path between the silicon photonic substrate and the optical waveguide for transmitting the light.

Method of manufacturing semiconductor package structure

Methods of manufacturing a semiconductor package structure are provided. A method includes: bonding dies and dummy dies to a wafer; forming a dielectric material layer on the wafer to cover the dies and the dummy dies; performing a first planarization process to remove a first portion of the dielectric material layer over top surfaces of the dies and the dummy dies; and performing a second planarization process to remove portions of the dies, portions of the dummy dies and a second portion of the dielectric material layer, and a dielectric layer is formed laterally aside the dies and the dummy dies; wherein after the second planarization process is performed, a total thickness variation of the dies is less than a total thickness variation of the dummy dies.

Serializer-deserializer die for high speed signal interconnect

In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed.

Semiconductor-on-insulator with back side support layer

SOLDER BALL, MANUFACTURING METHOD THEREOF, AND ELECTRONIC COMPONENT USING SAME

In the present specification, disclosed are a solder ball used in a semiconductor package, a manufacturing method thereof, and an electronic component including the same. More particularly, disclosed is a solder ball which can be applied to all technical fields based on the bonding of the solder ball, and particularly, can be used in a semiconductor package using the solder ball as a connection base in an electronic industry field. The solder ball maintains a shape of a core including metal with a low melting point even in a reflow and has stable bonding reliability with a substrate. COPYRIGHT KIPO 2017 (AA) Second metal layer (BB) First metal layer ...

Verfahren zur Herstellung eines Halbleiterbauelementes, Halbleiterbauelement und Träger

Die Erfindung betrifft ein Verfahren zur Herstellung eines Halbleiterbauelementes (1) mit folgenden Schritten: Bereitstellen eines Wachstumssubstrates (2) mit einer ersten Seite (21) und einer gegenüberliegenden zweiten Seite (22); Herstellen von zumindest einem elektronischen Bauelement (3) durch Abscheiden und/oder Strukturieren von zumindest einer Schicht (35) auf der ersten Seite (21) des Wachstumssubstrates (2), wobei diese Schicht zumindest einen Verbindungshalbleiter enthält oder daraus besteht; Verbinden der der ersten Seite (21) des Wachstumssubstrates (2) gegenüberliegenden ersten Seite (31) des elektronischen Bauelementes (3) mit einem Träger (4); Entfernen des Wachstumssubstrates (2), wobei der Träger (4) zumindest eine Durchführung (44) und/oder zumindest eine Leiterbahn (45) aufweist, welche mit zumindest einem Anschlusskontakt (36) des elektronischen Bauelementes (3) verbunden ist. Weiterhin betrifft die Erfindung ein so hergestelltes Halbleiterbauelement und einen Träger ...

Verfahren zum Bonden von Substraten

Verfahren zum Bonden eines ersten Substrats (4) mit einem zweiten Substrat (4'), wobei das erste Substrat (4) und/oder das zweite Substrat (4') vor dem Bonden gedünnt ist/wird, wobei Substratfixierungen jeweils eine Substratfixierfläche (9) zur Fixierung jeweils eines Substrats (4, 4') und jeweils eine die Substratfixierfläche (9) umgebende Trägerfixierfläche (8) oder Trägerfixierbereich zur gegenseitigen Fixierung der Substratfixierungen aufweisen, wobei die Trägerfixierfläche (8) oder der Trägerfixierbereich magnetisiert oder magnetisierbar ist.

METHOD OF MANUFACTURING ELEMENT CHIP, ELECTRONIC COMPONENT-MOUNTED STRUCTURE and METHOD OF MANUFACTURING ELECTRONIC COMPONENT-MOUNTED STRUCTURE

Room temperature metal direct bonding

A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.

Element accumulation-type connection realization method for separation circuit and circuit

本发明一种分离电路的元器件堆积式连接实现方法及电路，其方法设置针对电路中用于串联和/或并联的至少两个电路元器件，其中，依照电路的连接结构，将元器件的对应引脚直接焊接，使元器件依照电路需要的连接方式形成组合模块，省却电路板和连接导线。本发明分离电路的元器件堆积式连接实现方法及电路，由于采用了模块化的元器件，以及在元器件上设置的方便焊接的焊接盘，从而无需PCB电路板的存在，而仅仅依靠元器件之间的焊接拼接即可形成电路单元，从而形成节约电路板空间的电路，并且其设计实现方式可以在三维空间内进行，比现有技术的PCB限制在电路板平面内的电路具有更宽的设计空间，而且可以缩短从设计到制作电路的时间。

METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE STRUCTURE

Methods of manufacturing a semiconductor package structure are provided. A method includes: bonding dies and dummy dies to a wafer; forming a dielectric material layer on the wafer to cover the dies and the dummy dies; performing a first planarization process to remove a first portion of the dielectric material layer over top surfaces of the dies and the dummy dies; and performing a second planarization process to remove portions of the dies, portions of the dummy dies and a second portion of the dielectric material layer, and a dielectric layer is formed laterally aside the dies and the dummy dies; wherein after the second planarization process is performed, a total thickness variation of the dies is less than a total thickness variation of the dummy dies. 1. A method of manufacturing a semiconductor package structure , comprising:bonding dies and dummy dies to a wafer;forming a dielectric material layer on the wafer to cover the dies and the dummy dies;performing a first planarization process to remove a first portion of the dielectric material layer over top surfaces of the dies and the dummy dies; andperforming a second planarization process to remove portions of the dies, portions of the dummy dies and a second portion of the dielectric material layer, and a dielectric layer is formed laterally aside the dies and the dummy dies;wherein after the second planarization process is performed, a total thickness variation of the dies is less than a total thickness variation of the dummy dies.2. The method of claim 1 , wherein during the second planarization process claim 1 , a removal amount of the dummy dies is larger than a removal amount of the dies in a direction perpendicular to a top surface of the wafer.3. The method of claim 1 , wherein the dummy dies are disposed on periphery of the dies and laterally surrounding the dies.4. The method of claim 1 , wherein after the second planarization process is performed claim 1 , one of the dummy dies has an inner ...

背面放熱を伴う絶縁体上半導体

Halbleitervorrichtung, Metallelement und Verfahren zum Herstellen einer Halbleitervorrichtung

Ein Flansch 2 an einem offenen Ende 10a eines rohrförmigen Kontaktelements 10 wird mit einer Leiterplatte 22 eines isolierenden Substrats 21 verlötet. Ein externer Elektrodenanschluss 25 wird in einen Hauptkörperrohrteil 1 des rohrförmigen Kontaktelements 10 eingepasst. Das rohrförmige Kontaktelement 10 umfasst einen Vorsprung 5, der von einer Innenwand 10c des Hauptkörperrohrteils 1 nach innen absteht. Der Vorsprung 5 ist entlang des gesamten Umfangs der Innenwand 10c in Richtung auf das eine offene Ende 10a angeordnet. Der Vorsprung 5 weist eine Dickenverformung des Vorsprungs 5 durch eine Belastung auf, die auf ihn ausgeübt wird, wenn der externe Elektrodenanschluss 25 in den Hauptkörperrohrteil 1 eingepresst wird. Der Vorsprung 5 ist auf einer Höhe angeordnet, die ein Lot, das an der Innenwand 10c des Hauptkörperrohrteils 1 aufsteigt, blockieren kann, um zwischen dem Vorsprung 5 und einem unteren Ende des bis in eine vorbestimmte Tiefe des Hauptkörperrohrteils 1 eingeführten externen ...

후면 방열 기능을 갖는 반도체-온-절연체

본 발명의 실시형태들은 반도체-온-절연체(SOI) 구조체들로부터의 열의 방산을 제공한다. 일실시형태에 있어서, 집적 회로의 제조 방법이 개시된다. 제 1 단계에 있어서, 능동 회로가 SOI 웨이퍼의 활성층에 형성된다. 제 2 단계에 있어서, 기판 재료가 SOI 웨이퍼의 후면상에 배치되는 기판층으로부터 제거된다. 제 3 단계에 있어서, 절연체 재료가 익스커베이티드 절연체 영역을 형성하기 위해 SOI 웨이퍼의 후면으로부터 제거된다. 제 4 단계에 있어서, 방열층이 상기 익스커베이티드 절연체 영역상에 증착된다. 방열층은 열전도성이고 전기 절연성이다. Embodiments of the present invention provide for the dissipation of heat from semiconductor-on-insulator (SOI) structures. In one embodiment, a method of manufacturing an integrated circuit is disclosed. In the first step, an active circuit is formed in the active layer of the SOI wafer. In the second step, the substrate material is removed from the substrate layer disposed on the back side of the SOI wafer. In a third step, an insulator material is removed from the backside of the SOI wafer to form an insulated insulator region. In a fourth step, a heat dissipation layer is deposited on the exposed insulator region. The heat-radiating layer is thermally conductive and electrically insulating.

Method for bonding substrates

本發明係關於一種用於接合一第一基板(4)與一第二基板(4’)之方法，其特徵為該第一基板(4)及/或該第二基板(4’)在該接合之前經薄化。

SEMICONDUCTOR APPARATUS AND METHOD FOR PREPARING THE SAME

Method of Fabricating a Semiconductor Device with a Strain Inducing Material

Embodiments of the present invention provide for the dissipation of heat from semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a thermal dissipation layer is deposited on said excavated insulator region. The thermal dissipation layer is thermally conductive and electrically insulating.

Löten eines Leiters an eine Aluminiumschicht

Eine Anordnung aus einem Leiter und einer Aluminiumschicht, die zusammengelötet sind, umfasst ein Substrat und die Aluminiumschicht, die über dem Substrat angeordnet ist. Das Aluminium bildet ein erstes Bondmaterial. Eine intermetallische Zusammensetzungsschicht ist über der Aluminiumschicht angeordnet. Eine Lotschicht ist über der intermetallischen Zusammensetzungsschicht angeordnet, wobei das Lot eine niedrigschmelzende Majoritätskomponente umfasst. Der Leiter ist über der Lotschicht angeordnet, wobei der Leiter eine Lötoberfläche aufweist, die ein zweites Bondmetall umfasst. Die intermetallische Zusammensetzung umfasst Aluminium und das zweite Bondmetall und ist überwiegend frei von der niedrigschmelzenden Majoritätskomponente.

기질을 접합시키기 위한 방법

... 본 발명은 제1 기질(4)을 제2 기질(4')과 접합시키기 위한 방법에 관련되고, 상기 제1 기질(4) 및/또는 제2 기질(4')이 접합되기 전에 씨닝(thinned)가공되는 것을 특징으로 한다.

METHOD FOR BONDING SUBSTRATES

A method for bonding a first substrate with a second substrate, characterized in that the first substrate and/or the second substrate is/are thinned before the bonding.

SEMICONDUCTOR MODULE

A semiconductor module includes: a circuit board; a semiconductor chip having a first electrode pad on a first surface, bonded to the circuit board at a second surface that is opposite to the first surface, and having side surfaces intersecting the first surface and the second surface; an external terminal electrically connected to the first electrode pad; and an insulating member configured to fix the external terminal, wherein by the insulating member contacting the side surfaces of the semiconductor chip at a plurality of locations, parallel movement and rotational movement of the semiconductor chip relative to the insulating member in a plane parallel, to the first surface are restricted, and wherein the external terminal penetrates the insulating member.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes first and second semiconductor members and a first barrier film. The first semiconductor member includes a first insulating film, and a first wiring film in the first insulating film, the surface of which is exposed in the first insulating film. The second semiconductor member includes a second insulating film, and a second wiring film in the second insulating film, the surface of which is exposed in the second insulating film. The first barrier film forms a barrier to diffusion of the material of the first wiring film into the second insulating film and is formed of a compound of metal element of the first wiring film and an element of the second insulating film in a region where the first wiring film and the second insulating film are in contact with each other at the junction interface of the first and second semiconductor members. 1. A semiconductor device comprising:a first semiconductor member that includes a first insulating film, and a first wiring film in the first insulating film, the surface of which is exposed in the first insulating film;a second semiconductor member that includes a second insulating film, and a second wiring film in the second insulating film, the surface of which is exposed in the second insulating film, the first and second semiconductor devices joined together; anda first barrier film which forms a barrier to diffusion of the material of the first wiring film into the second insulating film, the first barrier film formed of a compound of a metal element of the first wiring film and an element of the second insulating film in a region where the first wiring film and the second insulating film are in contact with each other at the junction interface of the first semiconductor member and the second semiconductor member.2. The semiconductor device according to claim 1 , whereinthe metal element is added to the first wiring film during manufacturing of the first semiconductor member.3. The semiconductor ...

SEMICONDUCTOR-ON-INSULATOR WITH BACKSIDE HEAT DISSIPATION

Light emitting module and irradiating system using the same

一種發光模組，包括一投射光源以及一標記光源。投射光源發出一波長介於100~400nm或波長大於700nm的光線。標記光源發出一波長介於400~780nm的光線。投射光源所發出的光線，在一第一平面上投射出一第一投射範圍，標記光源之光軸在第一平面上係位於第一投射範圍內。

Substrate, method of fabricating the same, and application the same

Wafer Level UGA (UBM Grid Array) & PGA (Pad Grid Array) for Low Cost Package

A method to fabricate a land grid array wafer level chip scale package is described. A plurality of silicon dies are provided on a wafer. Openings are etched through a dielectric layer to metal pads on the silicon dies. At least one redistribution layer is formed over the dielectric layer and contacting at least one metal pad. A second dielectric layer is deposited on the at least one redistribution layer. An opening is etched through the second dielectric layer to the at least one redistribution layer and a landing pad is formed on the redistribution layer in the opening. The landing pad may be a portion of the redistribution layer exposed by the opening. Alternatively, the landing pad may be an under bump metal (UBM) layer deposited on the exposed redistribution layer and patterned. The landing pad is covered with an oxidation preventing layer.

Method of manufacturing semiconductor device and semiconductor device

A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove.

Semiconductor device and method of manufacturing the same

A semiconductor device includes first and second semiconductor members and a first barrier film. The first semiconductor member includes a first insulating film, and a first wiring film in the first insulating film, the surface of which is exposed in the first insulating film. The second semiconductor member includes a second insulating film, and a second wiring film in the second insulating film, the surface of which is exposed in the second insulating film. The first barrier film forms a barrier to diffusion of the material of the first wiring film into the second insulating film and is formed of a compound of metal element of the first wiring film and an element of the second insulating film in a region where the first wiring film and the second insulating film are in contact with each other at the junction interface of the first and second semiconductor members.

Interconnect Chips

A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

Semiconductor-on-insulator with back side heat dissipation,method of dissipating heat from the same,and method of fabricating intergrated circuit having the same

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove.

Method for fabricating a micro-well of a biosensor

Method for fabricating a micro-well of a biosensor

A bio-sensing semiconductor structure is provided. A transistor includes a channel region and a gate underlying the channel region. A first dielectric layer overlies the transistor. A first opening extends through the first dielectric layer to expose the channel region. A bio-sensing layer lines the first opening and covers an upper surface of the channel region. A second dielectric layer lines the first opening over the bio-sensing layer. A second opening within the first opening extends to the bio-sensing layer, through a region of the second dielectric layer overlying the channel region. A method for manufacturing the bio-sensing semiconductor structure is also provided.

Magnet Assisted Alignment Method for Wafer Bonding and Wafer Level Chip Scale Packaging

A high-precision alignment method with high throughput is proposed, which can be used for wafer-to-wafer, chip-to-wafer or chip-to-chip bonding. The scheme implements pairing patterned magnets predetermined designed and made using wafer level process on two components (wafer or chip). The magnetization in patterned magnet can be set at predetermined configuration before bonding starts. When, the two components are bought to close proximity after a coarse alignment, the magnetic force will bring the magnet pairs together and aligned the patterned magnet on one component with its mirrored or complimentary patterned magnets on the other component to minimize the overall the magnetic energy of the pairing magnet. A few patterned magnet structures and materials, with their unique merits are proposed as examples for magnet pair for the self-alignment purpose. This method enables solid contact at the bonding interface via patterned magnets under the magnetic force, which avoid the wafer drafting due to the formation of the liquid phases.

BOND PADS FOR LOW TEMPERATURE HYBRID BONDING

Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip. 1. An apparatus , comprising:a first semiconductor chip having a first glass layer and plural first groups of plural conductor pads in the first glass layer, each of the plural first groups of conductor pads including a main conductor pad and one or more dummy pads adjacent the main conductor pad and being configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality of interconnects that connect the first semiconductor chip to the second semiconductor chip; andthe first glass layer being configured to bond to a second glass layer of the second semiconductor chip.2. The apparatus of claim 1 , wherein each of the first groups comprises a main conductor pad and plural dummy pads circumferentially arranged around the main conductor pad.3. The apparatus of claim 1 , comprising the second semiconductor chip mounted on the first semiconductor chip and electrically connected thereto by the plurality of interconnects.4. An apparatus claim 1 , comprising:a first semiconductor chip having a first glass layer and plural first conductor pads in the first glass layer, each of the plural first conductor pads including a base layer and a bonding layer on the base layer, the base layer having a greater ...

ELECTRONIC MODULE

An electronic module includes a substrate that includes a first main surface and a second main surface, at least one first electronic component that includes electrodes on a mounting surface thereof on the substrate and that includes a hollow portion, at least one second electronic component that includes electrodes on a mounting surface thereof on the substrate and that includes no hollow portion, and a sealing resin. The at least one first electronic component is mounted on the first main surface of the substrate and sealed with the sealing resin. The at least one second electronic component is mounted on the second main surface of the substrate and is not sealed with the sealing resin. 1. An electronic module comprising:a substrate that includes a first main surface and a second main surface;at least one first electronic component that includes electrodes provided on a mounting surface thereof on the substrate and that includes a hollow portion;at least one second electronic component that includes electrodes provided on a mounting surface thereof on the substrate and that includes no hollow portion; anda sealing resin; whereinthe at least one first electronic component is mounted on the first main surface of the substrate and sealed with the sealing resin; andthe at least one second electronic component has a narrowest pitch between the electrodes that are provided on the mounting surface and is mounted on the second main surface of the substrate, and at least a portion of the at least one second electronic component that is joined to the substrate is not sealed with the sealing resin.2. The electronic module according to claim 1 , wherein the sealing resin includes a filler.3. The electronic module according to claim 1 , wherein an outer electrode that is defined by a metal piece is mounted on the second main surface of the substrate.4. The electronic module according to claim 1 , wherein the at least one first electronic component is an elastic wave device.5. ...

Display device and method of manufacturing the display device

A display device including a display area and a non-display area further includes a base layer including a first surface and a second surface opposite to the first surface, the base layer having, in the non-display area, an opening portion penetrating the first surface and the second surface; a pad unit including a terminal on the first surface, the pad unit extending from the first surface to the opening portion; a connection line connected to the terminal on the first surface, the connection line extending from the non-display area to the display area; an insulating layer covering the terminal and the connection line; a thin-film transistor including a semiconductor layer on the insulating layer, the thin-film transistor being connected to the connection line; and a display element connected to the thin-film transistor, the display element being in the display area.

SERIALIZER-DESERIALIZER DIE FOR HIGH SPEED SIGNAL INTERCONNECT

In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed. 1. A semiconductor package comprising:a first die;a second die; anda first serializer/deserializer (SerDes) die physically coupled with the first die and communicatively coupled with the second die, wherein the first SerDes die is to serialize signals transmitted from the first die to the second die, and the first SerDes die is to deserialize signals received from the second die.2. The semiconductor package of claim 1 , wherein the die is a monolithic die or a composite die.3. The semiconductor package of claim 1 , further comprising a second SerDes die physically coupled with the second die and communicatively coupled with the first SerDes die claim 1 , wherein the second SerDes die is to serialize signals transmitted from the second die to the first die claim 1 , and the second SerDes die is to deserialize signals received from the first die.4. The semiconductor package of claim 1 , wherein the first SerDes die has first pads at a first pitch at a side of the SerDes die coupled with the first die claim 1 , and the first SerDes die has second pads at a second pitch at a side of the SerDes die communicatively coupled with the second die.5. The semiconductor package of claim 4 , wherein the first pitch is larger than the second pitch.6. The semiconductor package of claim 1 , wherein the second die is an interposer.7. The semiconductor package of claim 1 , wherein the second die is a dual-sided interconnect die that includes an active component.8. A method of forming a die with a serializer/deserializer (SerDes) die attached thereto claim 1 , the method comprising: ...

Photonic package and method of manufacture

A package includes silicon waveguides on a first side of an oxide layer; photonic devices on the first side of the oxide layer, wherein the photonic devices are coupled to the silicon waveguides; redistribution structures over the first side of the oxide layer, wherein the redistribution structures are electrically connected to the photonic devices; a hybrid interconnect structure on a second side of the oxide layer, wherein the hybrid interconnect structure includes a stack of silicon nitride waveguides that are separated by dielectric layers; and through vias extending through the hybrid interconnect structure and the oxide layer, wherein the through vias make physical and electrical connection to the redistribution structures.

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

Semiconductor structure and fabrication methods are provided. The semiconductor structure includes a first wafer having a first metal layer therein and having a first material layer thereon, and a second wafer having a second metal layer therein and having a second material layer thereon. An alignment process and a bonding process are preformed between the first wafer and the second wafer, such that the first material layer and the second material layer are aligned and in contact with one another to provide a first alignment accuracy between the first metal layer and second metal layer. A heating process is performed on the first material layer and the second material layer to melt the first material layer and the second material layer to provide a second alignment accuracy between the first metal layer and second metal layer. The second alignment accuracy is greater than the first alignment accuracy. 1. A method for forming a semiconductor structure , comprising:providing a first wafer and a second wafer, wherein a first metal layer is formed in the first wafer and has a top surface exposed, and a second metal layer is formed in the second wafer and has a top surface exposed;forming a first material layer on the first wafer, wherein the first material layer and the first metal layer are on a same side of the first wafer;forming a second material layer on the second wafer, wherein the second material layer and the second metal layer are on a same side of second wafer;performing an alignment process and a bonding process between the first wafer and the second wafer, such that the first material layer and the second material layer are aligned and in contact with one another to provide a first alignment accuracy between the first metal layer and second metal layer; andafter the bonding process, performing a heating process on the first material layer and the second material layer, such that the first material layer and the second material layer are melted into one ...

Substrate attachment for attaching a substrate thereto

A method for bonding a first substrate with a second substrate, characterized in that the first substrate and/or the second substrate is/are thinned before the bonding.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip. 1. A method , comprising:providing an electrically conductive foil attached on a carrier;exposing at least one portion of the carrier by removing at least one portion of the electrically conductive foil;attaching a first semiconductor chip to a non-removed portion of the electrically conductive foil, wherein the first semiconductor chip comprises a first contact pad arranged over a first face of the first semiconductor chip and a second contact pad arranged over a second face of the first semiconductor chip, wherein the second contact pad is at least one of electrically or thermally coupled to the electrically conductive foil and wherein the first contact pad is electrically coupled to the electrically conductive foil; andforming a first electrically conductive layer over the first semiconductor chip.2. The method of claim 1 , comprising:embedding the first semiconductor chip at least partly in a non-conductive layer between the carrier and the first electrically conductive layer.3. The method of claim 1 , wherein the attaching the first semiconductor chip to the electrically conductive foil comprises one of the following connection techniques:soldering,diffusion soldering,diffusion bonding,conductive adhesive bonding,ultrasonic bonding, andthermal compression.4. The method of claim 1 ,wherein removing the at least one ...

ROOM TEMPERATURE METAL DIRECT BONDING

A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed. 1. A bonded structure comprising:a first plurality of metallic pads disposed on a first substrate;a first non-metallic region located on a first surface of said first substrate proximate to the first plurality of metallic pads;a second plurality of metallic pads disposed on a second substrate; anda second non-metallic region located on a second surface of the second substrate proximate to the second plurality of metallic pads,wherein a portion of each metallic pad of the first plurality of metallic pads directly contacts a corresponding metallic pad of the second plurality of metallic pads to form a metallic contact, andwherein the first non-metallic region contacts and is directly bonded to the second non-metallic region along an interface, the interface between the first non-metallic region and the second non-metallic region extending substantially to the metallic contact.2. The bonded structure of claim 1 , wherein each metallic pad comprises a reflowable material.3. The bonded structure of claim 1 , wherein the first non-metallic region comprises silicon oxide. This application is a continuation of application Ser. No. 14/959,204 filed Dec. 4, 2015, which is a continuation of application Ser. No. 14/474,476 ...

METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE STRUCTURE

A method of manufacturing a semiconductor package structure includes the following steps. A die is bonded to a wafer. A dielectric material layer is formed on the wafer and the die. The dielectric material layer covers a top surface and sidewalls of the die. At least one planarization process is performed to remove a portion of the dielectric material layer and a portion of the die, such that the top surface of the die is exposed and a dielectric layer aside the die is formed. The dielectric layer surrounds and covers the sidewalls of the die. 1. A method of manufacturing a semiconductor package structure , comprising:bonding a die to a wafer;forming a dielectric material layer on the wafer and the die, wherein the dielectric material layer covers a top surface and sidewalls of the die; andperforming at least one planarization process to remove a portion of the dielectric material layer and a portion of the die, such that the top surface of the die is exposed and a dielectric layer aside the die is formed,wherein the dielectric layer surrounds and covers the sidewalls of the die.2. The method of claim 1 , wherein the die and the wafer are configured as face to face.3. The method of claim 1 , wherein the die and the wafer are bonded by a hybrid bonding claim 1 , a fusion bonding claim 1 , a combination thereof or connected by a plurality of connectors.4. The method of claim 1 , wherein the dielectric material layer is formed of a molding compound claim 1 , a molding underfill claim 1 , a resin claim 1 , or a combination thereof by a molding process claim 1 , a molding underfilling (MUF) process claim 1 , or a combination thereof.5. The method of claim 1 , wherein the dielectric material layer is formed of an inorganic material claim 1 , an organic material claim 1 , or a combination thereof by a deposition process.6. The method of claim 1 , whereinthe at least one planarization process comprises a first planarization process and a second planarization process;the ...

Semiconductor Package and Method of Fabricating a Semiconductor Package

In an embodiment, a semiconductor package includes a package footprint having a plurality of solderable contact pads, a semiconductor device having a first power electrode and a control electrode on a first surface and a second power electrode on a second surface, a redistribution substrate having an insulating board, wherein the first power electrode and the control electrode are mounted on a first major surface of the insulating board and the solderable contact pads of the package footprint are arranged on a second major surface of the insulating board, and a contact clip having a web portion and one or more peripheral rim portions. The web portion is mounted on and electrically coupled to the second power electrode and the peripheral rim portion is mounted on the first major surface of the insulating board. 1. A semiconductor package , comprising:a package footprint comprising a plurality of solderable contact pads;a semiconductor device comprising a first power electrode and a control electrode on a first surface and a second power electrode on a second surface opposite the first surface;a redistribution substrate comprising an insulating board having a first major surface and a second major surface, wherein the first power electrode and the control electrode of the semiconductor device are mounted on the first major surface of the insulating board and the solderable contact pads of the package footprint are arranged on the second major surface of the insulating board; anda contact clip comprising a web portion and one or more peripheral rim portions, wherein the web portion is mounted on and electrically coupled to the second power electrode of the semiconductor device and the peripheral rim portion is mounted on the first major surface of the insulating board.2. The semiconductor package of claim 1 , wherein the contact clip comprises two peripheral rim portions extending from opposing sides of the web portion.3. The semiconductor package of claim 1 , wherein ...

Method for Manufacturing Chip Cards and Chip Card Obtained by Said Method

The invention relates to a chip card manufacturing method. According to this method, there are produced on the one hand, a module including a substrate supporting contacts on one face, and bonding pads on the other, on the other hand, an antenna on a support. The ends of the antenna are linked to lands of connection lands receiving a drop of soldering material on a connection portion. In order to make the soldered electrical connection between the module and the antenna reliable, the bonding pads extend over a zone covering a surface area less than that of the connection portions. The invention relates also to a chip card whose module includes bonding pads extending over a zone covering a surface area less than that of the connection portions. 1. A method for manufacturing a chip card , comprising:the production of a chip card module comprising a substrate having a first and a second main faces, with contacts on the first face of the substrate and bonding pads on the second face of the substrate, this module being also provided with an electronic chip connected to at least some contacts and to at least two conductive tracks dedicated to an antenna connection,the production of an antenna comprising two ends,the lamination of the antenna between layers of plastic material, andthe placement of the module in a cavity formed in at least some of the layers of plastic material,the connection, using a soldering material deposited on a portion of connection of each of the ends of the antenna with a bonding pads of the module, and heated up, once the module is in place in the cavity,characterized by the fact that bonding pads are each produced on a zone covering a surface area less than that of a connection portion covered with soldering material.2. The method as claimed in claim 1 , in which at least one of the bonding pads is produced comprising at least one bar extending longitudinally in a direction (L) over a length of between 1 and 7 mm.3. The method as claimed in claim ...

SOLDER-CONTAINING SEMICONDUCTOR DEVICE, MOUNTED SOLDER-CONTAINING SEMICONDUCTOR DEVICE, PRODUCING METHOD AND MOUNTING METHOD OF SOLDER-CONTAINING SEMICONDUCTOR DEVICE

A solder-containing semiconductor device includes a semiconductor device. The semiconductor device includes a substrate, at least one group III nitride semiconductor layer disposed on the substrate, a Schottky electrode disposed on the group III nitride semiconductor layer, and a pad electrode disposed on the Schottky electrode. The pad electrode has a multi-layer structure including at least a Pt layer. The solder-containing semiconductor device further includes a solder having a melting point of 200 to 230° C. and being disposed on the pad electrode of the semiconductor device. Thereby, the solder-containing semiconductor device including the Schottky electrode, the pad electrode disposed on the Schottky electrode and the solder disposed on the pad electrode can be mounted to offer a mounted solder-containing semiconductor device without degrading the semiconductor device properties. 1. A solder-containing semiconductor device comprising a semiconductor device , a substrate;', 'at least one group III nitride semiconductor layer disposed on said substrate;', 'a Schottky electrode disposed on said group III nitride semiconductor layer; and', 'a pad electrode disposed on said Schottky electrode,', 'said pad electrode having a multi-layer structure including at least a Pt layer,, 'the semiconductor device includingthe solder-containing semiconductor device further comprising a solder having a melting point of 200 to 230° C. and being disposed on said pad electrode of said semiconductor device.2. The solder-containing semiconductor device according to claim 1 , whereinsaid solder-containing semiconductor device further includes a dielectric layer having an opening and being disposed on said group III nitride semiconductor layer, andsaid Schottky electrode is disposed on a portion of said group III nitride semiconductor layer that is positioned within said opening of said dielectric layer.3. The solder-containing semiconductor device according to claim 1 , whereinsaid ...

METHOD OF MANUFACTURING ELEMENT CHIP, METHOD OF MANUFACTURING ELECTRONIC COMPONENT-MOUNTED STRUCTURE, AND ELECTRONIC COMPONENT-MOUNTED STRUCTURE

To provide a method of manufacturing an element chip in which creep-up of a conductive material can be suppressed in a mounting step. In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate which has a plurality of element regions and of which an element surface is covered by an insulating film, the substrate is divided into the element chips by exposing the substrate to a first plasma, the element chips having a first surface, a second surface, and a side surface are held spaced from each other on a carrier, and the side surface and the insulating film are in a state of being exposed. 1. A method of manufacturing an element chip , in which a plurality of element chips are manufactured by dividing a substrate , which includes a first surface having a plurality of element regions defined by dividing regions and of which at least a part is covered with an insulating film , and a second surface on a side opposite to the first surface , at the dividing regions , the method comprising:a preparing step of preparing the substrate in which a first surface side is supported on a carrier and an etching-resistant layer is formed so as to cover regions of the second surface opposite to the element regions and to expose regions of the second surface opposite to the dividing regions; anda plasma processing step of performing plasma processing on the substrate that is supported on the carrier after the preparing step,wherein the plasma processing step includesa dividing step of dividing the substrate into the element chips by etching the substrate of regions which are not covered by the etching-resistant layer in a depth direction of the substrate up to the first surface by exposing the second surface to first plasma and causing each of the element chips including the first surface, the second surface, and a side surface connecting the first surface and the second surface to be ...

Semiconductor apparatus and method for preparing the same

The present disclosure is directed to a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The semiconductor devices have conductive portions with higher coefficient of thermal expansion than their dielectric portions. By forming the depression to provide a space for the volume expansion of the conductive portion with higher coefficient of thermal expansion during the subsequent thermal treating process of the fusion bonding, the semiconductor apparatus formed of semiconductor devices by the fusion bonding technique does not exhibit a lateral protrusion into the interface between the two dielectric portions. As a result, the failure of the electrical function due to the lateral protrusion is effectively eliminated.

Method of manufacturing semiconductor device and semiconductor device

A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove.

Sacrificial Alignment Ring And Self-Soldering Vias For Wafer Bonding

A method of bonding a first substrate to a second substrate, wherein the first substrate includes first electrical contacts on a top surface of the first substrate, and wherein the second substrate includes second electrical contacts on a bottom surface of the second substrate. The method includes forming a block of polyimide on the top surface of the first substrate, wherein the block of polyimide has a rounded upper corner, and vertically moving the top surface of the first substrate and the bottom surface of the second substrate toward each other until the first electrical contacts abut the second electrical contacts, wherein during the moving, the second substrate makes contact with the rounded upper corner of the polyimide causing the first and second substrates to move laterally relative to each other.

SEMICONDUCTOR DEVICE, METAL MEMBER, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A flange on first open end of a tubular contact member is soldered to a conductive plate of an insulating substrate. An external electrode terminal is fitted into a main body tube portion of the tubular contact member. The tubular contact member includes a protrusion that protrudes inwardly from an inner wall of the main body tube portion. The protrusion is disposed along the entire perimeter of inner wall toward the first open end. The protrusion has a thickness deformation of the protrusion by a load applied thereto when the external electrode terminal is pressed into the main body tube portion. The protrusion is disposed at a height that can block solder that climbs the inner wall of the main body tube portion, to form a gap between the protrusion and a lower end of the external electrode terminal inserted to a predetermined depth of the main body tube portion. 1. A metal member comprising:a tube portion having a hollow tube shape and first and second open ends; anda first protrusion on an inner wall of the tube portion closer to the first open end than the second open end, the first protrusion including at least two opposing sides that protrude inwardly in a direction orthogonal to a central axis of the tube portion and define a hole between the at least two opposing sides.2. The metal member according to claim 1 , whereinthe first protrusion is disposed along an entire perimeter of the inner wall.3. The metal member according to and further comprisinga flange at the first open end, the flange protruding outwardly in a direction orthogonal to the central axis.4. The metal member according to claim 1 , whereina thickness of the first protrusion is at least 0.1 mm and not more than 1.6 mm.5. The metal member according to claim 1 , whereinthe metal member has an inner diameter d and a ratio of a width w of the first protrusion to the inner diameter d satisfies 0.2≦2×w/d≦0.8.6. The metal member according to claim 1 , whereinthe first protrusion is positioned such ...

Multi-chip package with offset 3d structure

Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package that includes an interposer that has a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by a dielectric layer on the metallization stack, and plural semiconductor chips positioned over and at least partially laterally overlapping the first semiconductor chip.

Copper structures with intermetallic coating for integrated circuit chips

An integrated circuit (IC) chip includes a copper structure with an intermetallic coating on the surface. The IC chip includes a substrate with an integrated circuit. A metal pad electrically connects to the integrated circuit. The copper structure electrically connects to the metal pad. A solder bump is disposed on the copper structure. The surface of the copper structure has a coating of intermetallic. The copper structure can be a redistribution layer and a copper pillar that is disposed on the redistribution layer.

Multi-chip package with offset 3d structure

Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package that includes an interposer that has a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by a dielectric layer on the metallization stack, and plural semiconductor chips positioned over and at least partially laterally overlapping the first semiconductor chip.

Method and device for transferring components

本发明涉及一种用于将构件从发送器基底传递到接收器基底上的方法，所述方法至少具有以下步骤，尤其是带有以下顺序：i)在所述发送器基底上提供和/或产生所述构件，ii)将所述发送器基底的构件传递到转移基底上，iii)将所述构件从所述转移基底传递到所述接收器基底上，其中，所述构件能够借助结合器件和/或去结合器件选择性地传递。

Bonding apparatus, bonding system and bonding method

복수의 칩으로 분할되는 제 1 기판을, 상기 제 1 기판이 접착된 테이프 및 상기 테이프의 외주가 장착된 링 프레임을 개재하여 유지하는 제 1 유지부와, 상기 제 1 기판을 기준으로서 상기 테이프와는 반대측에 배치되는 제 2 기판을, 상기 제 1 기판과 간격을 두고 유지하는 제 2 유지부와, 상기 테이프를 개재하여 상기 칩을 1 개씩 누르고, 상기 칩을 1 개씩 상기 제 2 기판에 눌러, 접합하는 누름부를 가지는, 접합 장치를 제공한다.

Semiconductor-on-insulator with backside heat dissipation

【課題】絶縁体上半導体（ＳＯＩ）構造から熱を放散する方法を提供する。【解決手段】集積回路を製造する方法であって、第１のステップでは、アクティブ回路が、ＳＯＩウエハのアクティブ層１０３内に形成される。第２のステップでは、基板材料が、ＳＯＩウエハの背面上に配置された基板層から除去される。第３のステップでは、絶縁材料１０２が、ＳＯＩウエハの背面から除去されて掘られた絶縁体領域を形成する。第４のステップでは、放熱層２００が、前記掘られた絶縁層上に堆積される。放熱層は、熱的に伝導性があり、かつ電気的に絶縁する。【選択図】図３

3d integration structure and method using bonded metal planes

A method of making 3D integrated circuits and a 3D integrated circuit structure. There is a first semiconductor structure joined to a second semiconductor structure. Each semiconductor structure includes a semiconductor wafer, a front end of the line (FEOL) wiring on the semiconductor wafer, a back end of the line (BEOL) wiring on the FEOL wiring, an insulator layer on the BEOL wiring and a metallic layer on the insulator layer. The first semiconductor structure is aligned with the second semiconductor structure such that the metallic layers of each of the semiconductor structures face each other. The metallic layers of each of the semiconductor structures are in contact with and bonded to each other by a metal to metal bond wherein the bonded metallic layers form an electrically isolated layer.

MICROELECTRONIC ARRANGEMENT AND METHOD OF MANUFACTURING THE SAME

Ausführungsbeispiele schaffen ein Verfahren zur Herstellung einer mikroelektronischen Anordnung. Das Verfahren umfasst einen Schritt des Bereitstellens eines Chip-Folien-Moduls mit einem Halbleiterchip und einem Foliensubstrat, auf dem der Halbleiterchip angeordnet ist, wobei das Chip-Folien-Modul zumindest ein von dem Halbleiterchip beabstandetes Kopplungselement aufweist, das mit zumindest einem Anschluss des Halbleiterchips elektrisch gekoppelt ist. Ferner umfasst das Verfahren einen Schritt des Einbettens des Chip-Folien-Moduls in eine Leiterplatte, wobei bei dem Einbetten des Chip-Folien-Moduls in die Leiterplatte das zumindest eine Kopplungselement des Chip-Folien-Moduls vertikal [z.B. in vertikaler Richtung [z.B. in Bezug auf die Leiterplatte]] [z.B. senkrecht zu einer Oberfläche der Leiterplatte] mit zumindest einem Kopplungsgegenelement der Leiterplatte gekoppelt wird. Exemplary embodiments create a method for producing a microelectronic arrangement. The method comprises a step of providing a chip-foil module with a semiconductor chip and a foil substrate on which the semiconductor chip is arranged, the chip-foil module having at least one coupling element spaced from the semiconductor chip, which is connected to at least one connection of the semiconductor chip is electrically coupled. The method further comprises a step of embedding the chip-foil module in a circuit board, wherein when the chip-foil module is embedded in the circuit board, the at least one coupling element of the chip-foil module is vertical [e.g. in the vertical direction [e.g. in relation to the printed circuit board]] [e.g. perpendicular to a surface of the circuit board] is coupled to at least one counter-coupling element of the circuit board.

ELECTRONIC POWER DEVICE WITH VERTICAL 3D SWITCH CELL

Dispositif électronique de puissance (100) comportant : - au moins un premier composant électronique de puissance (108) disposé au niveau d'une première face principale d'un premier substrat (106) ; - au moins un élément de contact électrique (114) disposé sur le premier composant électronique de puissance tel que le premier composant électronique de puissance soit disposé entre l'élément de contact électrique et le premier substrat et soit relié électriquement à une première face principale de l'élément de contact électrique ; dans lequel le premier substrat, le premier composant électronique de puissance et l'élément de contact électrique forment ensemble un empilement tel qu'une première face latérale d'au moins l'élément de contact électrique, sensiblement perpendiculaire à la première face principale de l'élément de contact électrique, soit disposée contre au moins une métallisation (104) d'un support (102) formant au moins un contact électrique du premier composant électronique de puissance. Power electronic device (100) comprising: - at least one first power electronic component (108) arranged at a first main face of a first substrate (106); - at least one electrical contact element (114) disposed on the first electronic power component such that the first electronic power component is disposed between the electrical contact element and the first substrate and is electrically connected to a first main face of the electrical contact element; in which the first substrate, the first electronic power component and the electrical contact element together form a stack such that a first side face of at least the electrical contact element, substantially perpendicular to the first main face of the electrical contact element, is placed against at least one metallization (104) of a support (102) forming at least one electrical contact of the first electronic power component.

ELECTRONIC POWER DEVICE WITH VERTICAL 3D SWITCH CELL

Dispositif électronique de puissance (100) comportant : - au moins un premier composant électronique de puissance (108) disposé au niveau d'une première face principale d'un premier substrat (106) ; - au moins un élément de contact électrique (114) disposé sur le premier composant électronique de puissance tel que le premier composant électronique de puissance soit disposé entre l'élément de contact électrique et le premier substrat et soit relié électriquement à une première face principale de l'élément de contact électrique ; dans lequel le premier substrat, le premier composant électronique de puissance et l'élément de contact électrique forment ensemble un empilement tel qu'une première face latérale d'au moins l'élément de contact électrique, sensiblement perpendiculaire à la première face principale de l'élément de contact électrique, soit disposée contre au moins une métallisation (104) d'un support (102) formant au moins un contact électrique du premier composant électronique de puissance. An electronic power device (100) comprising: - at least one first electronic power component (108) disposed at a first major face of a first substrate (106); at least one electrical contact element (114) disposed on the first electronic power component such as the first electronic power component is disposed between the electrical contact element and the first substrate and is electrically connected to a first main face of the electrical contact element; wherein the first substrate, the first electronic power component and the electrical contact element together form a stack such as a first side face of at least the electrical contact element, substantially perpendicular to the first major face of the electrical contact element is arranged against at least one metallization (104) of a support (102) forming at least one electrical contact of the first electronic power component.

Method for producing bonded object and semiconductor device and copper bonding paste

本発明の一態様は、第一の部材、接合用銅ペースト、及び第二の部材がこの順に積層されている積層体を用意する工程と、接合用銅ペーストを、０．１～１ＭＰａの圧力を受けた状態で焼結する工程と、を備え、接合用銅ペーストは、金属粒子及び分散媒を含有し、金属粒子の含有量が、接合用銅ペーストの全質量を基準として、５０質量％以上であり、金属粒子が、前記金属粒子の全質量を基準として、９５質量％以上のサブマイクロ銅粒子を含有する、接合体の製造方法を提供する。

Display device and Method of manufacturing of the display device

본 발명의 일 실시예는, 표시영역 및 비표시영역을 포함하는 표시 장치에 있어서, 제1면 및 상기 제1면과 반대되는 제2면을 포함하며, 상기 비표시영역에서 상기 제1면 및 상기 제2면을 관통하는 개구부를 구비한 베이스층; 상기 제1면에 배치되며 상기 제1면으로부터 상기 개구부로 연장된 단자를 포함하는 패드부; 상기 제1면 상에서 상기 단자와 연결되며, 상기 비표시영역에서 상기 표시영역으로 연장된 연결배선; 상기 단자 및 상기 연결배선을 덮는 절연층; 상기 절연층 상에 배치된 반도체층을 포함하며, 상기 연결배선과 연결된 적어도 하나의 박막트랜지스터; 및 상기 적어도 하나의 박막트랜지스터와 연결되며, 상기 표시영역에 배치된 표시요소;를 포함하는, 표시 장치를 개시한다.

Transistor formation using cold welding

A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device.

Three-dimensional heterogeneous module welding method

本发明公开了一种三维异构模组焊接方法，具体包括如下步骤：101)射频模组制作步骤、102)底座模组制作步骤、103)键合形成功能模组步骤、104)替换键合步骤；本发明提供快速更换损坏模组芯片的一种三维异构模组焊接方法。

Bonded body, method for manufacturing semiconductor device, and copper paste for bonding

本发明的一形态提供一种接合体的制造方法，包括：准备依次层叠有第一构件、接合用铜糊及第二构件的层叠体的步骤；以及将接合用铜糊在受到0.1MPa～1MPa的压力的状态下予以烧结的步骤，其中，接合用铜糊含有金属粒子及分散介质，金属粒子的含量以接合用铜糊的总质量为基准，为50质量％以上，金属粒子含有以所述金属粒子的总质量为基准，为95质量％以上的次微米铜粒子。

Manufacturing method of semiconductor device and semiconductor device

本發明之實施形態提供一種能夠一面抑制半導體晶圓損傷、一面在將複數個半導體晶圓積層後一起進行單片化之半導體裝置之製造方法及半導體裝置。 本實施形態之半導體裝置之製造方法係將第1半導體基板與第2半導體基板積層，該第1半導體基板具有包含半導體元件之第1面及位於該第1面之相反側之第2面，該第2半導體基板具有包含半導體元件之第3面及位於該第3面之相反側之第4面。自第1半導體基板之第2面進行蝕刻，形成自該第2面到達至第1面之第1接觸孔，並且於第1半導體基板之第2面中之第1區域形成第1槽。形成被覆第1槽之第1遮罩材。將第1遮罩材用作遮罩而於第1接觸孔內形成第1金屬電極。去除第1遮罩材之後，將第1半導體基板之第1區域切斷。

Bonding device, bonding system, and bonding method

A bonding device, having: a first holding part for holding a first substrate to be split into a plurality of chips, the first holding part holding the first substrate via a tape to which the first substrate is joined and a ring frame on which the outer periphery of the tape is fitted; a second holding part for holding a second substrate disposed on the opposite side of the first substrate from the tape, the second holding part holding the second substrate at a distance from the first substrate; and a pressing part for pushing the chips one by one through the tape, pressing the chips one by one against the second substrate, and bonding the chips.

Bonding apparatus and semiconductor package fabrication equipment including the same

A bonding apparatus includes a body part; a vacuum hole disposed in the body part; a first protruding part protruding in a first direction from a first surface of the body part; a second protruding part protruding from the first surface of the body part in the first direction and spaced farther apart from a center of the first surface of the body part than the first protruding part in a second direction intersecting with the first direction; and a trench defined by the first surface of the body part and second surfaces of the first protruding part, the second surfaces protruding in the first direction from the first surface of the body part, and the trench being connected to the vacuum hole, wherein the second protruding part protrudes farther from the first surface of the body part in the first direction than the first protruding part.

Microelectronic assembly and method for preparation of same

Ausführungsbeispiele schaffen ein Verfahren zur Herstellung einer mikroelektronischen Anordnung. Das Verfahren umfasst einen Schritt des Bereitstellens eines Chip-Folien-Moduls (120) mit einem Halbleiterchip (122) und einem Foliensubstrat (124), auf dem der Halbleiterchip angeordnet ist, wobei das Chip-Folien-Modul zumindest ein von dem Halbleiterchip beabstandetes Kopplungselement (126) aufweist, das mit zumindest einem Anschluss des Halbleiterchips elektrisch gekoppelt ist. Ferner umfasst das Verfahren einen Schritt des Einbettens des Chip-Folien-Moduls in eine Leiterplatte (142), wobei bei dem Einbetten des Chip-Folien-Moduls in die Leiterplatte das zumindest eine Kopplungselement (126) des Chip-Folien-Moduls vertikal [z.B. in vertikaler Richtung [z.B. in Bezug auf die Leiterplatte]] [z.B. senkrecht zu einer Oberfläche der Leiterplatte] mit zumindest einem Kopplungsgegenelement (144) der Leiterplatte gekoppelt wird. Exemplary embodiments create a method for producing a microelectronic arrangement. The method comprises a step of providing a chip-film module (120) with a semiconductor chip (122) and a film substrate (124) on which the semiconductor chip is arranged, the chip-film module having at least one coupling element spaced from the semiconductor chip (126) which is electrically coupled to at least one connection of the semiconductor chip. The method further comprises a step of embedding the chip-foil module in a circuit board (142), wherein during the embedding of the chip-foil module in the circuit board the at least one coupling element (126) of the chip-foil module is vertical [e.g. in the vertical direction [e.g. in relation to the printed circuit board]] [e.g. perpendicular to a surface of the circuit board] is coupled to at least one counter-coupling element (144) of the circuit board.

Semiconductor-on-insulator with backside heat dissipation

本发明实施例实现了对绝缘体上半导体(SOI)结构的散热。在一个实施例中，公开了一种制造集成电路的方法。在第一步骤中，在绝缘体上半导体晶圆的有源层中形成有源电路。在第二步骤中，从布置在所述绝缘体上半导体晶圆背侧的基板层去除基板材料。在第三步骤中，从所述绝缘体上半导体绝缘的所述背侧去除绝缘材料以形成挖掉的绝缘区域。在第四步骤中，在所述挖掉的绝缘区域中沉积散热层。所述散热层是导热的并且是电绝缘的。

Semiconductor device, metal member, and method of manufacturing semiconductor device

A flange on first open end of a tubular contact member is soldered to a conductive plate of an insulating substrate. An external electrode terminal is fitted into a main body tube portion of the tubular contact member. The tubular contact member includes a protrusion that protrudes inwardly from an inner wall of the main body tube portion. The protrusion is disposed along the entire perimeter of inner wall toward the first open end. The protrusion has a thickness deformation of the protrusion by a load applied thereto when the external electrode terminal is pressed into the main body tube portion. The protrusion is disposed at a height that can block solder that climbs the inner wall of the main body tube portion, to form a gap between the protrusion and a lower end of the external electrode terminal inserted to a predetermined depth of the main body tube portion.

Method for bonding substrates

본 발명은 제1 기질(4)을 제2 기질(4')과 접합시키기 위한 방법에 관련되고, 상기 제1 기질(4) 및/또는 제2 기질(4')이 접합되기 전에 씨닝(thinned)가공되는 것을 특징으로 한다.

Multi-chip package with offset 3d structure

Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package (115) that includes an interposer (125) that has a first side and a second and opposite side and a metallization stack (145) on the first side, a first semiconductor chip (25) on the metallization stack and at least partially encased by a dielectric layer (165) on the metallization stack, and plural semiconductor chips (40, 45) positioned over and at least partially laterally overlapping the first semiconductor chip.

Memory device

A memory device includes a lower structure and a plurality of upper structures stacked on the lower structure. The lower structure includes a peripheral circuit, and an upper bonding pad disposed on a top surface of the lower structure. Each of the plurality of upper structures includes a bit line, a through via, and a lower bonding pad disposed on a bottom surface of the upper structures and connected to the through via. Each of upper structures, other than an uppermost upper structure, further includes an upper bonding pad disposed on a top surface thereof and connected to the through via. The bit line includes a gap separating a first portion of the bit line from a second portion thereof in the horizontal direction, and the through via overlaps the gap of the bit line in a plan view.

Semiconductor devices and methods of manufacture

A semiconductor device and method of manufacture are provided wherein semiconductor devices are attached over a semiconductor substrate. An opening is formed within metallization layers over the semiconductor substrate and the semiconductor substrate, and an encapsulant is placed to fill the opening. Once the encapsulant is placed, the semiconductor substrate is singulated to separate the devices. By recessing the material of the metallization layers and forming the opening, delamination damage may be reduced or eliminated.

A SEMICONDUCTOR DEVICE PACKAGE WITH SIDE PANELS CONNECTED TO CONTACT PADS OF A SEMICONDUCTOR AND A METHOD FOR ITS MANUFACTURE

Halbleiterbauelementpaket (100), umfassend:- eine gedruckte Leiterplatte (10) mit einem ersten zentralen Bereich, einem zweiten lateralen Bereich und einem dritten lateralen Bereich;- einen Halbleiterdie (20) mit einer ersten Hauptfläche und einer zweiten Hauptfläche gegenüber der ersten Hauptfläche, einem ersten Kontaktpad (20A), das auf der ersten Hauptfläche angeordnet ist, und einem zweiten Kontaktpad (20B), das auf der zweiten Hauptfläche angeordnet ist, wobei der Halbleiter'die (20) in dem ersten zentralen Bereich der Leiterplatte (10) angeordnet ist;- eine erste metallische Seitenwand (30) des Halbleiterbauelementpakets, die in dem zweiten lateralen Bereich der Leiterplatte (10) angeordnet ist;- eine zweite metallische Seitenwand (40) des Halbleiterbauelementpakets, die in dem dritten lateralen Bereich der Leiterplatte (10) angeordnet ist;- einen ersten metallischen Durchgangssteg (50), der zwischen dem ersten Kontaktpad (20A) des Halbleiterdies (20) und der ersten metallischen Seitenwand (30) verbunden ist und- einen zweiten metallischen Durchgangssteg (60), der zwischen dem zweiten Kontaktpad (20B) des Halbleiterdies (20) und der zweiten metallischen Seitenwand (40) verbunden ist; wobei mindestens eine von der ersten metallischen Seitenwand (30) und der zweiten metallischen Seitenwand (40) elektrisch mit einem von dem ersten Kontaktpad (20A) oder dem zweiten Kontaktpad (20B) des Halbleiterdies (20) verbunden ist,gekennzeichnet durcheine Laminatschicht (70), die auf der gedruckten Leiterplatte angeordnet ist, wobeidie erste metallische Seitenwand (30), die zweite metallische Seitenwand (40), der erste metallische Durchgangssteg (50) und der zweite metallische Durchgangssteg (60) innerhalb von Bereichen der Laminatschicht (70) angeordnet sind. A semiconductor device package (100) comprising:- a printed circuit board (10) having a first central area, a second lateral area and a third lateral area;- a semiconductor die (20) having a first major surface and ...

Method for manufacturing semiconductor element and semiconductor element body

A method of manufacturing a semiconductor element according to the present disclosure includes an element forming step (S1) of forming, on an underlying substrate (11), a semiconductor element (15) connected to the underlying substrate (11) via a connecting portion (13b) and including an upper surface (15a) inclined with respect to a growth surface of the underlying substrate (11), a preparing step (S2) of preparing a support substrate (16) including an opposing surface (16c) facing the underlying substrate (11), a bonding step (S3) of pressing the upper surface (15a) of the semiconductor element (15) against the opposing surface (16c) of the support substrate (16) and heating the upper surface (15a) to bond the upper surface (15a) of the semiconductor element (15) to the support substrate (16), and a peeling step (S4) of peeling the semiconductor element (15) from the underlying substrate (11).

Semiconductor on insulator with backside heat dissipation

Memory device

一种存储器装置包括下部结构和堆叠在下部结构上的多个上部结构。下部结构包括外围电路和设置在下部结构的顶表面上的上接合焊盘。多个上部结构中的每一个包括位线、穿通件和设置在上部结构的底表面上并连接至穿通件的下接合焊盘。除了最上面的上部结构之外，每个上部结构还包括设置在其顶表面上并连接至穿通件的上接合焊盘。位线包括在水平方向上将位线的第一部分与该位线的第二部分分离的间隙，并且在平面图中，穿通件与位线的间隙重叠。

Display device and method for manufacturing the same

提供了一种显示装置和一种用于制造该显示装置的方法，所述显示装置包括：像素电极，设置在基底上；发光元件，设置在像素电极上；连接电极，设置在发光元件的侧表面上；以及共电极，设置在发光元件上。发光元件包括：第一子发光元件；第二子发光元件，设置在第一子发光元件上；以及第三子发光元件，设置在第二子发光元件上。连接电极设置在第一子发光元件、第二子发光元件和第三子发光元件的至少一个侧表面上。

Method of bonding thin film substrates

Manufacturing method of semiconductor device

Semiconductor devices and methods of manufacture

반도체 디바이스 및 제조 방법이 제공되며, 반도체 디바이스는 반도체 기판 위에 부착된다. 반도체 기판 및 반도체 기판 위의 금속 배선 층 내에 개구가 형성되고, 개구를 충진하기 위해 봉지재가 배치된다. 봉지재가 배치되면 반도체 기판이 싱귤레이션되어 디바이스를 분리한다. 금속 배선 층의 재료를 리세싱하고 개구를 형성함으로써 박리 손상이 감소되거나 제거될 수 있다. A semiconductor device and manufacturing method are provided, wherein the semiconductor device is attached onto a semiconductor substrate. An opening is formed in a semiconductor substrate and a metal wiring layer over the semiconductor substrate, and an encapsulant is disposed to fill the opening. When the encapsulant is disposed, the semiconductor substrate is singulated to isolate the device. Peel damage can be reduced or eliminated by recessing the material of the metal wiring layer and forming the opening.

Semiconductor device and manufacturing method of semiconductor device

A semiconductor device includes a first integrated circuit and a second integrated circuit. The first integrated circuit includes a semiconductor substrate and a dielectric layer disposed on a top surface of the semiconductor substrate. The second integrated circuit is disposed on the dielectric layer of the first integrated circuit and includes a dummy opening extending through the second integrated circuit and having a metal layer covering the inner walls of the dummy opening and in contact with the dielectric layer, wherein the metal layer is electrically grounded or electrically floating.

Semiconductor-on-insulator with back side heat dissipation

本發明之實施例是為了散逸來自絕緣體上半導體(SOI)結構之熱而預備。在一實施例，揭露一種製造積體電路之方法。在第一步驟中，在SOI晶圓之一主動層中形成主動電路。在第二步驟中，自設置在該SOI晶圓之一背側上的一基板層去除基板材料。在第三步驟中，自該SOI晶圓之該背側去除絕緣體材料以形成一挖空的絕緣體區域。在第四步驟中，將一散熱層沉積在該挖空的絕緣體區域上。該散熱層為導熱的且電氣絕緣的。

INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING THE SAME

Ein Verfahren zum Bilden eines integrierten Schaltungs-Packages umfasst das Anbringen eines ersten Dies an einem Interposer. Der Interposer weist einen ersten Die-Verbinder und einen zweiten Die-Verbinder am Interposer und eine erste dielektrische Schicht, welche mindestens eine Seitenwand des ersten Die-Verbinders und mindestens eine Seitenwand des zweiten Die-Verbinders bedeckt, auf. Der erste Die ist an den ersten Die-Verbinder und die erste dielektrische Schicht gekoppelt, und der zweite Die-Verbinder ist durch den ersten Die freigelegt. Das Verfahren umfasst ferner das Vertiefen der ersten dielektrischen Schicht zum Freilegen mindestens einer Seitenwand des zweiten Die-Verbinders und das Anbringen eines zweiten Dies am Interposer, wobei der zweite Die an den zweiten Die-Verbinder gekoppelt ist.

Semiconductor circuit and method for manufacturing semiconductor circuit

本发明涉及一种半导体电路和半导体电路的制备方法，通过电性连接线组折弯设置在第一基板和第二基板之间，且第二基板的第一板面靠近第一基板，第二基板的第二板面从密封本体露出，实现在半导体电路的外部集成MCU芯片，通过将对散热要求不高的IC控制线路设置在第二基板的第一板面，将MCU芯片案子在第二基板的第二板面，因此MCU芯片与IC控制电路之间只隔着一个第二基板的厚度，极大的缩短了信号的传输距离。从而实现控制信号的“零距离”传输，缩小玻纤板面积；同时在同一半导体电路实现强、弱电分离，提高了整个半导体电路的抗干扰能力，使电控小型化，布线更灵活，且成本低，进一步的缩小了产品体积，另外，方便MCU芯片的更换拆卸。

Patent JPWO2021039405A1

Semiconductor Devices and Methods of Manufacture

A semiconductor device and method of manufacture are provided wherein semiconductor devices are attached over a semiconductor substrate. An opening is formed within metallization layers over the semiconductor substrate and the semiconductor substrate, and an encapsulant is placed to fill the opening. Once the encapsulant is placed, the semiconductor substrate is singulated to separate the devices. By recessing the material of the metallization layers and forming the opening, delamination damage may be reduced or eliminated.

Semiconductor-on-insulator with backside heat dissipation

Embodiments of the present invention provide for the dissipation of heat from semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a thermal dissipation layer is deposited on said excavated insulator region. The thermal dissipation layer is thermally conductive and electrically insulating.

塑封模块、塑封方法及电子设备

本申请公开了一种塑封模块、塑封方法及电子设备。该塑封模块包括基板，所述基板的表面设置阻焊层，焊料被放置在所述阻焊层形成的四周封闭的区域内，芯片与所述基板之间通过所述焊料实现固定，所述基板和固定在所述基板上的所述芯片被塑封，形成所述塑封模块。还公开了相应的塑封方法和电子设备。采用本申请的方案，阻焊层提供阻焊作用的同时，既能使阻焊层与基板实现高可靠性结合，又能使阻焊层与塑封模块的塑封料实现高可靠性结合。

Dummy pattern structure for reducing dishing

A device includes a substrate, at least one first dielectric layer on the substrate and including a first dielectric constant, at least one second dielectric layer on the at least one first dielectric layer and including a second dielectric constant greater than the first dielectric constant, and a dummy pattern including a first conductive pattern having a first pattern density in the at least one first dielectric layer and a second conductive pattern in the at least one second dielectric layer and comprising a second pattern density. The first pattern density is equal to or greater than the second pattern density.

Integrated circuit package module including a bonding system

An integrated circuit package module includes an integrated circuit package device including a contact element, and a bonding system formed on the integrated circuit package device. The bonding system includes a bonding system substrate and a bonding element formed in the bonding system substrate and conductively coupled to the contact element of the integrated circuit package device. The bonding element includes (a) a conduction component conductively connected to the contact element, the conduction component formed from a first metal having a first melting point, and (b) a bonding component formed from a second metal having a second melting point lower than the first melting point of the first metal.

接合体及び半導体装置の製造方法、並びに接合用銅ペースト

【課題】高圧での接合が不要でありながら、接合強度に優れた接合体を得ることができる、接合体の製造方法及び半導体装置の製造方法を提供すること。【解決手段】接合体１００の製造方法は、第一の部材２、接合用銅ペースト１及び第二の部材３がこの順に積層されている積層体４を用意する工程と、接合用銅ペーストを、０．１～１ＭＰａの圧力を受けた状態で焼結し、接合用銅ペーストの焼結体５を得る工程と、を備え、接合用銅ペーストは、金属粒子及び分散媒を含有し、金属粒子の含有量が、接合用銅ペーストの全質量を基準として、５０質量％以上であり、金属粒子が、前記金属粒子の全質量を基準として、９５質量％以上のサブマイクロ銅粒子を含有する。【選択図】図１

接合体及半导体装置的制造方法

本发明涉及一种接合体及半导体装置的制造方法以及接合用铜糊。本发明的一形态提供一种接合体的制造方法，包括：准备依次层叠有第一构件、接合用铜糊及第二构件的层叠体的步骤；以及将接合用铜糊在受到0.1MPa～1MPa的压力的状态下予以烧结的步骤，其中，接合用铜糊含有金属粒子及分散介质，金属粒子的含量以接合用铜糊的总质量为基准，为50质量％以上，金属粒子含有以所述金属粒子的总质量为基准，为95质量％以上的次微米铜粒子。

半導体装置及びその製造方法

半导体器件及其制造方法

提供了半导体器件及其制造方法，其中，在半导体衬底上方附接半导体器件。在半导体衬底上方的金属化层和半导体衬底内形成开口，并且放置密封剂以填充开口。一旦放置密封剂，则分割半导体衬底以分隔器件。通过使金属化层的材料凹进并且形成开口，可以减少或消除分层损坏。

Soldering a conductor to an aluminum layer

An arrangement is disclosed. In one example, the arrangement of a conductor and an aluminum layer soldered together comprises a substrate and the aluminum layer disposed over the substrate. The aluminum forms a first bond metal. An intermetallic compound layer is disposed over the aluminum layer. A solder layer is disposed over the intermetallic compound layer, wherein the solder comprises a low melting majority component. The conductor is disposed over the solder layer, wherein the conductor has a soldering surface which comprises a second bond metal. The intermetallic compound comprises aluminum and the second bond metal and is predominantly free of the low melting majority component.

一种半导体器件、电器件以及制作方法

本发明还提供了一种半导体器件、电器件以及制作方法，电器件包括电路基板、设于所述电路基板上的射频开关器、射频放大器、导线以及衬底、嵌于所述衬底下端面上的安装框，所述安装框与所述衬底之间形成安装空间，所述半导体器件还包括设于所述安装空间内的电路器件、嵌设于所述衬底上的导电的连接件以及埋入引线，所述导线与所述连接件相电连接。通过本方法制作的电器件能极好的控制电路器件和电路基板的间距，进而精确控制电路器件与其他器件之间产生的干涉等问题。

Display device and method of manufacturing the same

A display device includes a substrate, a plurality of pixel electrodes on the substrate and spaced apart from each other, a plurality of light-emitting elements on the plurality of pixel electrodes, respectively, and a common electrode layer on the plurality of light-emitting elements and to which a common voltage is applied. The plurality of light-emitting elements include a first light-emitting element that is configured to emit first light according to a first driving current and a second light-emitting element that is configured to emit second light according to a second driving current. An active layer of the first light-emitting element is the same as an active layer of the second light-emitting element.

ウェハ接合のための犠牲アライメントリング及び自己はんだ付けビア

第１の基板を第２の基板に接合する方法であって、第１の基板は、第１の基板の上面上に第１の電気接点を含み、第２の基板は、第２の基板の底面上に第２の電気接点を含む、方法。この方法は、第１の基板の上面上にポリイミドのブロックを形成するステップであって、ポリイミドのブロックは、丸みを帯びた上角部を有する、ステップと、第１の電気接点が第２の電気接点に当接するまで、第１の基板の上面及び第２の基板の底面を互いに向かって垂直に移動させるステップであって、移動中、第２の基板は、ポリイミドの丸みを帯びた上角部と接触して、第１及び第２の基板を互いに対して横方向に移動させる、ステップと、を含む。【選択図】図１２

Sacrificial alignment ring and self-soldering vias for wafer bonding

A method of bonding a first substrate to a second substrate, wherein the first substrate includes first electrical contacts on a top surface of the first substrate, and wherein the second substrate includes second electrical contacts on a bottom surface of the second substrate. The method includes forming a block of polyimide on the top surface of the first substrate, wherein the block of polyimide has a rounded upper corner, and vertically moving the top surface of the first substrate and the bottom surface of the second substrate toward each other until the first electrical contacts abut the second electrical contacts, wherein during the moving, the second substrate makes contact with the rounded upper corner of the polyimide causing the first and second substrates to move laterally relative to each other.

Sacrificial alignment ring and self-soldering vias for wafer bonding