PROCEDURE FOR THE PRODUCTION OF A MATRIX FOR THE DETECTION OF ELECTROMAGNETIC RADIATION IN PARTICULAR INFRARED RADIATION

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND ADHESIVE FOR MOUNTING FLIP CHIP

A purpose of the present invention is to provide a method for manufacturing a semiconductor device that can suppress voids and achieve high reliability. An additional purpose of the present invention is to provide an adhesive which is for mounting a flip chip and is used in the method for manufacturing the semiconductor device. The method for manufacturing the semiconductor devices has: a step 1 for positioning a semiconductor chip, having formed thereon a protruding electrode having a tip part formed from solder, on a substrate via an adhesive; a step 2 for heating the semiconductor chip to a temperature at or above the solder melting point, fusion bonding the protruding electrode of the semiconductor chip and an electrode part of the substrate, and also temporarily bonding with the adhesive; and a step 3 for eliminating voids by heating the adhesive in a pressurized atmosphere. The adhesive has an activation energy ?E found by differential scanning calorimetry and the Ozawa method of ...

Verfahren zur Positionierung eines elektrischen Schaltungselementes und Halterungselement zur Durchführung eines solchen Verfahrens

A method for calibrating a component-mounting apparatus.

Die Erfindung betrifft die Kalibrierung einer Bauelemente-Montagevorrichtung, die eingerichtet ist für die Montage von Bauelementen auf einem Substrat, dessen Montageplätze keine lokalen Markierungen enthalten. Das Substrat enthält entweder an seinem Rand angebrachte globale Substratmarkierungen oder andere globale Merkmale, die für die Montage der Bauelemente herangezogen werden können. Die Kalibrierung erfolgt mittels einer Kalibrierplatte (1), die mehrere, zweidimensional über die Kalibrierplatte (1) verteilte und mit ersten optischen Markierungen versehene Kalibrierpositionen (2) aufweist, einem Testchip, der zweite optische Markierungen aufweist, und einer an der Bondstation angebrachten Halterung für die temporäre Aufnahme der Kalibrierplatte (1). Die Anzahl und Anordnung der Kalibrierpositionen (2) der Kalibrierplatte (1) und die Anzahl und Anordnung der Montageplätze des Substrats sind – abgesehen von möglichen Ausnahmefällen – verschieden voneinander.

ELECTRICAL COMPONENTS AND MOUNTING THEREOF

얼라인먼트 방법, 전자 부품의 접속 방법, 접속체의 제조 방법, 접속체, 이방성 도전 필름

... 얼라인먼트 마크를 이방성 도전 필름이 첩착되는 영역과 중첩되는 위치에 형성함과 함께, 카메라에 의한 촬상 화상을 사용한 얼라인먼트를 정밀도 양호하게 행한다. 투명 기판(12)의 표면에, 도전성 접착제(1)를 개재하여 전자 부품(18)을 탑재하고, 투명 기판(12)의 이면측으로부터 기판측 얼라인먼트 마크(21) 및 부품측 얼라인먼트 마크(22)를 촬상하고, 촬상 화상으로부터 양 얼라인먼트 마크(21, 22)의 위치를 조정하고, 투명 기판(12)에 대한 전자 부품(18)의 탑재 위치를 맞추는 얼라인먼트 방법에 있어서, 도전성 접착제(1)는, 평면으로 볼 때에 도전성 입자(4)가 규칙적으로 배열되고, 촬상 화상에 있어서, 양 얼라인먼트 마크(21, 22)의 외측가장자리의 가상 선분을 따라, 도전성 입자(4) 사이로부터 면하는 양 얼라인먼트 마크(21, 22)의 외측가장자리가 선분(S)으로서 단속적으로 나타나 있다.

BONDING DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.

BONDING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Provided is a flip-chip bonding apparatus (500) capable of stacking and bonding a second-layer of the semiconductor chip (30) onto a first-layer of the semiconductor chip (20) having first through-silicon vias, the second-layer of the semiconductor chip (30) having second through-silicon vias at positions corresponding to the first through-silicon vias. The flip-chip bonding apparatus (500) includes: a double-view camera (16) configured to take images of the chips (20) and (30); and a control unit (50) having a relative-position detection program (53) for detecting relative positions of the first-layer of the semiconductor chip (20) and the second-layer of the semiconductor chip (30) that are stacked and bonded based on an image of the first through-silicon vias on a surface of the first-layer of the semiconductor chip (20) taken by the double-view camera (16) before stacked bonding, and an image of the second through-silicon vias on a surface of the second-layer of the semiconductor chip ...

Connection body

Even in case of conductive particles being clamped between stepped sections of substrate electrodes and electrode terminals, conductive particles sandwiched between each main surface of the substrate electrodes and electrode terminals are sufficiently compressed, ensuring electrical conduction. An electronic component is connected to a circuit substrate via an anisotropic conductive adhesive agent, on respective edge-side areas of substrate electrodes of the circuit substrate and electrode terminals of the electronic component, stepped sections are formed and abutted, conductive particles are sandwiched between each main surface and stepped sections of the substrate electrodes and electrode terminals; the conductive particles and stepped sections satisfy formula, a+b+c≦0.8 D (1), wherein a is height of the stepped section of the electrode terminals, b is height of the stepped section of the substrate electrodes, c is gap distance between each stepped sections and D is diameter of conductive ...

Connection components with rows of lead bond sections

A connection component for a microelectronic element includes a sheet-like support structure having top and bottom surfaces which extend in horizontal directions. The support structure includes a central region and a periphery surrounding the central region with terminals mounted on the central region of the support structure and exposed at the top surface thereof. A plurality of leads extend on the support structure with each lead having a terminal section connected to one of the terminals and attached to the bottom surface, a bond region and a horizontally curved section between the bond region and the terminal region. The bond regions of the leads are disposed side-by-side in one or more rows adjacent the periphery of the support structure. After the bond regions of the leads have been bonded to contacts of a microelectronic element, the support structure of the connection component is moveable upwardly so as to bend the curved sections of the leads.

MOUNTING STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor-device mounting structure includes a first semiconductor device and a plate-shaped second semiconductor device connected to the first semiconductor device. The first semiconductor device includes a flexible board, an electronic component, and a sealing resin. The flexible board includes a bendable flexible portion and a hard portion. The flexible portion is bent at a boundary with the hard portion, along a shape of the electronic component such that the flexible board covers the electronic component. The flexible board and the electronic component are sealed with the sealing resin. The first semiconductor device is provided vertical to the second semiconductor device such that the hard portion is provided parallel to the second semiconductor device, and a length of the hard portion in a direction perpendicular to a bend line of the flexible portion is equal to a thickness of a bottom surface of the electronic component in the direction.

SINTERED SOLDER FOR FINE PITCH FIRST-LEVEL INTERCONNECT (FLI) APPLICATIONS

Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.

CMOS CIRCUIT

PROBLEM TO BE SOLVED: To prevent a CMOS circuit from causing latch-up. SOLUTION: In the CMOS circuit 10, an N-channel transistor 11 and a P-channel transistor 12 are formed on different substrates 1A, 1B, respectively, and the transistors 11, 12 on both substrates 1A, 1B face each other and are connected. In the CMOS circuit 10, since a current path is not formed between the N-channel transistor 11 and the P-channel transistor 12 due to a parasitic transistor, the occurrence of latch-up can be completely prevented. COPYRIGHT: (C)2011,JPO&INPIT ...

Display device and manufacturing method of the same

PROCESS FOR the REALIZATION Of a MATRIX OF DETECTION OF ELECTROMAGNETIC RADIATIONS AND IN PARTICULAR OF INFRA-RED RADIATIONS

Ce procédé pour la réalisation d'une matrice de détection de rayonnements électromagnétiques, constituée d'une pluralité de modules de détection élémentaires 2 rapportés sur un substrat d'interconnexion, lesdits modules 2 étant eux-mêmes composés d'au moins un circuit de détection 4 dudit rayonnement, associé à un circuit de lecture 3 par hybridation, lesdits circuits de lecture étant eux-mêmes solidarisés au substrat d'interconnexion, consiste : ■ à ménager au niveau de la face arrière 15 du circuit de lecture 3 de chacun des modules élémentaires 2 : • des sillons ou rainures 16, • et des zones 17 exemptes de tels sillons ou rainures ; ■ à ménager ou à rapporter d'une part, sur la face avant du substrat d'interconnexion, et d'autre part sur la face avant du circuit de détection ou d'un composant inactif hybridé sur le circuit de lecture, des motifs d'indexation 12, destinés à assurer un positionnement précis, notamment selon les cotes X et Y de chacun des modules élémentaires 2 sur ledit ...

CHIP-ON-WAFER BONDING METHOD AND BONDING DEVICE, AND STRUCTURE COMPRISING CHIP AND WAFER

... [Problem] To provide a technique for efficiently bonding a chip to a wafer without leaving undesirable residue such as resin on the bonding interface, establishing electrical connections between the chip and wafer or among a plurality of layered chips, and increasing mechanical strength. [Solution] The method of the present invention for bonding a plurality of chips with chip-side bonding surfaces comprising metal regions to a substrate comprising a plurality of bonding sections is provided with the following steps: (S1) wherein the metal regions of the chip-side bonding surfaces are subjected to a surface activation treatment and a hydrophilization treatment; a step (S2) wherein the bonding sections of the substrate are subjected to a surface activation treatment and a hydrophilization treatment; a step (S3) wherein each of the plurality of chips, which have been subjected to the surface activation treatment and the hydrophilization treatment, is attached to the corresponding bonding section ...

MULTILAYER SUBSTRATE

Provided is a multilayer substrate obtained by laminating semiconductor substrates each having a trough electrode. The multilayer substrate has excellent conduction characteristics and can be manufactured at low cost. Conductive particles are each selectively present at a position where the through electrodes face each other as viewed in a plan view of the multilayer substrate. The multilayer substrate has a connection structure in which the facing through electrodes are connected by the conductive particles, and the semiconductor substrates each having the through electrode are bonded by an insulating adhesive. 1. A multilayer substrate comprising semiconductor substrates which each have a through electrode and are laminated to each other , whereinconductive particles are each selectively present at a position where the through electrodes face each other as viewed in a plan view of the multilayer substrate, andthe multilayer substrate has a connection structure in which the facing through electrodes are connected by the conductive particles, and the semiconductor substrates each having the through electrode are bonded together by an insulating adhesive.2. The multilayer substrate according to claim 1 , comprising a first semiconductor substrate having a through electrode and a second semiconductor substrate having a through electrode claim 1 , the first and second semiconductor substrates being laminated together claim 1 , the multilayer substrate having a connection structure in whichthe through electrode of the first semiconductor substrate and the through electrode of the second semiconductor substrate are connected by the conductive particle which is selectively disposed between the through electrodes.3. The multilayer substrate according to claim 2 , comprising a third semiconductor substrate having a through electrode laminated on the second semiconductor substrate claim 2 , and having a connection structure in whichthe through electrode of the second ...

Method of manufacturing semiconductor device and flip chip mounting adhesive for

Integrated module and its forming method

실장 장치 및 그 오프셋량 보정 방법

... 상하 2시야 카메라(20)에 의해 기준용 칩(12)의 상면의 화상과 보정용 칩(13)의 하면의 화상을 취득하여 각 칩(12, 13)의 각 위치를 계산하는 제1 칩 위치 계산 공정과, 각 칩의 각 위치로부터 계산한 각 칩 간의 어긋남량에 기초하여 각 칩 간의 이간 거리가 소정의 오프셋량이 되는 위치로 기준용 칩을 이동시킨 후, 보정용 칩(13)을 흡착 스테이지(11)에 재치하는 제2 칩 이동 공정과, 보정용 칩(13)의 상면의 화상을 취득하여 보정용 칩(13)의 제2 위치를 계산하는 제2 칩 위치 계산 공정과, 기준용 칩의 위치와 보정용 칩의 제2 위치에 기초하여 소정의 오프셋량의 보정량을 계산하는 보정량 계산 공정을 포함한다. 이것에 의해, 실장 위치의 경시적인 위치 어긋남을 억제하여 실장 품질의 향상을 도모한다.

ADHESIVE COMPOSITION CAPABLE OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH HIGH DENSITY AND HIGH CONCENTRATION, AN ADHESIVE SHEET, MATERIAL FOR PROTECTING A SEMICONDUCTOR DEVICE, AND A SEMICONDUCTOR DEVICE

PURPOSE: An adhesive composition is provided to have excellent adhesion, connection reliability, and insulation reliability after hardening. CONSTITUTION: An adhesive composition comprises a silicon resin in chemical formula 1. In chemical formula 1, R^1-R^4 are same or different C1-8 monovalent hydrocarbon groups, l and m are an integer of 1-100, a, b, c and d are 0 or positive number, and satisfy 0<(c+d)/(a+b+c+d)<=1.0, and X and Y is respectively an divalent organic group in chemical formula 2 or 3. COPYRIGHT KIPO 2012 ...

Three-dimensional mounting method and apparatus

Chip bonding apparatus and bonding method

Provided are a chip bonding apparatus and bonding method. The apparatus comprises: a chip supply unit; a substrate supply unit; a first pick-up assembly arranged between the chip supply unit and the substrate supply unit, comprising a first rotating component and a first pick-up head arranged on the first rotating component; a second pick-up assembly comprising a second rotating component and a second pick-up head arranged on the second rotating component, wherein the first pick-up assembly picks up a chip from the chip supply unit or the second pick-up assembly, and delivers the chip onto a substrate of the substrate supply unit to complete the bonding; and a vision unit for realizing the alignment of the chip and the substrate on the first pick-up assembly, wherein the chip supply unit, the substrate supply unit, the second pick-up assembly and the vision unit are respectively located on four work positions of the first pick-up head. The chip is transported through rotation, improving ...

STACKED DEVICE, STACKED STRUCTURE, AND METHOD OF MANUFACTURING STACKED DEVICE

A stacked device includes a stacked structure in which a plurality of semiconductors are electrically connected to each other, the semiconductor includes a surface on which a plurality of terminals are provided, the plurality of terminals include a terminal that bonds and electrically connects the semiconductors to each other and a terminal that bonds the semiconductors to each other and does not electrically connect the semiconductors to each other, an area ratio of the plurality of terminals on the surface of the semiconductor is 40% or higher, and an area ratio of the terminals that bond and electrically connect the semiconductors to each other among the plurality of terminals is lower than 50%.

HETEROGENEOUS INTEGRATED CIRCUITS WITH INTEGRATED COVERS

The system and method for a heterogeneous integrated circuit packaging method having an air-cavity lid to protect the active face of an integrated circuit, or other device, either active or passive, from the environment. The packaging is hermetic or near hermetic. In some examples, the cover provides electrical routing. In some examples, the cover also provides electromagnetic shielding. In some cases, an encapsulant and/or an overmoulding is provided to further protect the heterogeneous integrated circuit. 1. A method of making a heterogeneous integrated circuit , comprising:providing a first integrated circuit having a substrate side and an electronic circuit side;providing a cover with an integral air cavity, the integral air cavity being etched into the cover;bonding the cover with the integral air cavity to the electronic circuit side of the first integrated circuit via a bonding agent to form a hermetic or near-hermetic bond;providing a second integrated circuit having a substrate side and an electronic circuit side;bonding the substrate side of the first integrated circuit to the second integrated circuit via heterogeneous interconnects, wherein at least one of the first and second integrated circuits is a chiplet; andproviding an encapsulant over the cover and the first and second integrated circuits;thereby forming a heterogeneous integrated circuit with a chiplet with an integrated cover, wherein the cover with the integrated air cavity provides electrical routing and protects the electronic circuit side or active face of the chiplet.2. (canceled)3. The method of making a heterogeneous integrated circuit with an integrated cover according to claim 1 , wherein the cover comprises glass.4. (canceled)5. The method of making a heterogeneous integrated circuit with an integrated cover according to claim 1 , wherein the cover provides electrical shielding.6. The method of making a heterogeneous integrated circuit with an integrated cover according to claim 1 , ...

Connection body, method for manufacturing a connection body, connecting method and anisotropic conductive adhesive agent

Ensure conduction between an electronic component and a circuit substrate having reduced pitches in wiring of the circuit substrate or electrodes of the electronic component and prevent short circuits between electrode terminals of the electronic component. A connection body including an electronic component connected to a circuit substrate via an anisotropic conductive adhesive agent containing conductive particles; wherein the conductive particles are regularly arranged; and wherein the conductive particles have a particle diameter that is ½ or less than a height of a connecting electrode of the electronic component.

CHIP FABRICATION METHOD AND PRODUCT

The invention relates to the field of chip fabrication, in particular to the fabrication of superconducting integrated circuits for use in quantum computers. Raised and recessed alignment structures are provided on the surfaces of two substrate such that the raised and recessed alignment structure extends within the recessed alignment structure to a maximum depth determined by the geometry of the alignment structures. The alignment structures act as a hard stop for positioning and aligning the substrates for flip chip bonding.

Mounting device and offset amount correction method therefor

PROCESS FOR the REALIZATION Of a MATRIX OF DETECTION OF ELECTROMAGNETIC RADIATIONS AND IN PARTICULAR OF INFRA-RED RADIATIONS

Method for Aligning Micro-Electronic Components

Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves ...

Semiconductor device and method of manufacturing same

SEMICONDUCTOR ELEMENT AND WAFER LEVEL CHIP SIZE PACKAGE THEREFOR

ELECTRONIC-COMPONENT MOUNTED BODY, ELECTRONIC COMPONENT, AND CIRCUIT BOARD

접속체

... 도전성 입자가 기판 전극과 전극 단자의 단부 사이로 맞물려 들어가도, 기판 전극 및 전극 단자의 각 주면부에 협지되어 있는 도전성 입자를 충분히 압입하여, 도통성을 확보한다. 회로 기판(12)에 이방성 도전 접착제(1)를 개재하여 전자 부품(18)이 접속되고, 회로 기판(12)의 기판 전극(17a) 및 전자 부품(18)의 전극 단자(19)에는, 각 측가장자리부에 서로 맞대어지는 단부(27, 28)가 형성되고, 기판 전극(17a) 및 전극 단자(19)는 각 주면부 사이 및 단부(27, 28) 사이에 도전성 입자(4)가 협지되고, 도전성 입자(4)와 단부(27, 28)가 (1) a＋b＋c≤0.8D 를 만족한다. [a : 전극 단자의 단부 높이, b : 기판 전극의 단부 높이, c : 단부 사이 갭, D : 도전성 입자의 직경] ...

Sintered solder for fine pitch first-level interconnect (FLI) applications

Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.

LAMINATED CHIP, LAMINATED-CHIP-MOUNTED SUBSTRATE AND MANUFACTURING METHOD OF LAMINATED CHIP

A laminated chip includes: semiconductor chips that are laminated; and multiple types of adhesive insulating resin films that include mutually different characteristics and that are filled between the semiconductor chips, wherein the multiple types of the adhesive insulating resin films are arranged in a chip plane direction, depending on a demand characteristic for each region in a chip plane.

Integrated Circuit Dies Having Alignment Marks and Methods of Forming Same

Physical design symmetry and integrated circuits enabling three dimentional (3d) yield optimization for wafer to wafer stacking

One of the wafers in a semiconductor wafer to wafer stack can be rotated a predefined number of positions, relative to a previous wafer in the stack, and bonded in the position in which the maximum number of good die are aligned. An adjustment circuit on each die reroutes signals received from a pad that has been relocated due to rotation. A communication channel formed from a pair of pads that are interconnected by a Through Substrate Vias can be placed in each die and can convey selected information from one die to the next. A code representative of the position orientation of each die can be recorded in a Programmable Read Only Memory located on each die, or may be down loaded from a remote source. Any additional wafer may be stacked serially, and each one may be rotated relative to the wafer that precedes it in the stack.

Semiconductor wafer having a alignment mark for wafer bonding and processing method thereof

CHIP BONDING APPARATUS AND BONDING METHOD

Provided are a chip bonding apparatus and bonding method. The apparatus comprises: a chip supply unit (10); a substrate supply unit (20); a first pick-up assembly (30) arranged between the chip supply unit (10) and the substrate supply unit (20), comprising a first rotating component and a first pick-up head arranged on the first rotating component; a second pick-up assembly (40) comprising a second rotating component and a second pick-up head arranged on the second rotating component, wherein the first pick-up assembly (30) picks up a chip (60) from the chip supply unit (10) or the second pick-up assembly (40), and delivers the chip (60) onto a substrate of the substrate supply unit (20) to complete the bonding; and a vision unit (50) for realizing the alignment of the chip (60) and the substrate on the first pick-up assembly (30), wherein the chip supply unit (10), the substrate supply unit (20), the second pick-up assembly (40) and the vision unit (50) are respectively located on four ...

Self-Alignment for Redistribution Layer

An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value. 1. A method comprising:forming a functional through via (TV) within a die area of a substrate, the functional TV having a first protruding portion extending above a first surface of the substrate by a first height;forming an alignment mark within a die street region of the substrate, the die street region of the substrate surrounding the die area of the substrate, the alignment mark comprising a dummy TV, the dummy TV having a second protruding portion extending above the first surface of the substrate by a second height, the second height being equal to the first height;reducing the first height of the first protruding portion of the functional TV by a first amount; andreducing the second height of the second protruding portion of the dummy TV by a second amount, the second amount being less than the first amount.2. The method of claim 1 , further comprising:before reducing the first height of the first protruding portion of the functional TV and the second height of the second protruding portion of the dummy TV, forming a dielectric layer over the first surface of the substrate, the first protruding portion of the functional TV and the second protruding portion of the dummy TV; andbefore reducing the first height of the first protruding portion of the functional TV and ...

THREE-DIMENSIONAL MOUNTING METHOD AND THREE-DIMENSIONAL MOUNTING DEVICE

A three-dimensional mounting method for successively laminating N number of upper-layer joining materials includes positioning a first upper-layer joining material relative to a lowermost-layer joining material by recognizing an alignment position of the lowermost-layer joining material and a lower face alignment position of the first upper-layer joining material by a two-field image recognition unit, storing positional coordinates of the alignment position of the lowermost-layer joining material, positioning an (n+1)-th upper-layer joining material relative to an n-th upper-layer joining material by recognizing an upper face alignment position of the n-th upper-layer joining material and a lower face alignment position of the (n+1)-th upper-layer joining material, storing positional coordinates of the upper face alignment position of the n-th upper-layer joining material, recognizing an upper face alignment position of the N-th uppermost-layer joining material, and storing positional coordinates of the upper face alignment position of the N-th uppermost-layer joining material. 1. A three-dimensional mounting method in which N number of upper-layer joining materials with electrodes on upper and lower faces are successively laminated onto a lowermost-layer joining material with an electrode such that positions of the electrodes of the upper-layer joining materials and a position of the electrode of the lowermost-layer joining material are arranged in an aligned state , the three-dimensional mounting method comprising:when laminating a first upper-layer joining material over the lowermost-layer joining material, positioning the first upper-layer joining material relative to the lowermost-layer joining material by recognizing an alignment position of the lowermost-layer joining material and a lower face alignment position marked on a lower face of the first upper-layer joining material by a two-field image recognition unit, and storing positional coordinates of the ...

Three-dimensional mounting method and three-dimensional mounting device

A three-dimensional mounting method for successively laminating N number of upper-layer joining materials includes positioning a first upper-layer joining material relative to a lowermost-layer joining material by recognizing an alignment position of the lowermost-layer joining material and a lower face alignment position of the first upper-layer joining material by a two-field image recognition unit, storing positional coordinates of the alignment position of the lowermost-layer joining material, positioning an (n+1)-th upper-layer joining material relative to an n-th upper-layer joining material by recognizing an upper face alignment position of the n-th upper-layer joining material and a lower face alignment position of the (n+1)-th upper-layer joining material, storing positional coordinates of the upper face alignment position of the n-th upper-layer joining material, recognizing an upper face alignment position of the N-th uppermost-layer joining material, and storing positional coordinates ...

Verfahren zum Detektieren der Ausrichtung von in Z-Richtung gestapelter mehrerer Halbleiterchips eines Halbleiterbauelements

Verfahren zum Detektieren der Ausrichtung von in Z-Richtung gestapelter mehrerer Halbleiterchips (100, 100a, 100b) eines Halbleiterbauelements (1), bei dem die mehreren Halbleiterchips (100, 100a, 100b) jeweils mit mehreren Bump-Elektroden (102, 102a, 102b) gestapelt sind, wobei die mehreren Halbleiterchips (100, 100a, 100b) jeweils ein Halbleitersubstrat (105) und die mehreren Bump-Elektroden (102, 102a, 102b) auf dem Halbleitersubstrat (105) aufweisen,wobei die mehreren Halbleiterchips (100, 100a, 100b) einen Identifikationsabschnitt (104, 104A, 104B) umfassen, der so ausgebildet ist, dass er in Seitenoberflächen des Halbleitersubstrats (105) eingebettet ist, und der entlang der gesamten Dicke des Halbleitersubstrats (105) ausgebildet ist,wobei die mehreren Bump-Elektroden (102, 102a, 102b) auf die gleiche Weise auf den Halbleiterchips (100, 100a, 100b) angeordnet sind und die Identifikationsabschnitte (104, 104A, 104B) derart ausgebildet sind, dass sie die gleiche Positionsbeziehung ...

Waferjustiersystem mit optischer Kohärenz-Tomographie

System zum Durchführen einer Justierung von zwei Wafern, das aufweist:ein optisches Kohärenz-Tomographie-System [102]; undein Waferjustiersystem [104];wobei das Waferjustiersystem [104] so konfiguriert und angeordnet ist, dass es die relative Position eines ersten Wafers und eines zweiten Wafers steuert, und wobei das optische Kohärenz-Tomographie-System [102] so konfiguriert und angeordnet ist, dass es dreidimensionale Koordinatendaten für eine Vielzahl von Justiermarkierungen auf dem ersten Wafer und dem zweiten Wafer berechnet; und die Koordinatendaten zu dem Waferjustiersystem sendet.

Multilayer board

A multilayer board is provided which comprises semiconductor boards that have through-electrodes and are laminated together, and which has excellent conduction characteristics and can be manufactured at low cost. The multilayer board comprises conductive particles which, in plan view, are selectively present in positions where through-electrodes are opposed to each another. In the connection structure of this multilayer board, the opposed through-electrodes are connected by the conductive particles and the semiconductor boards in which the through-electrodes are formed are adhered together by means of an insulating adhesive.

Integrated circuit cooling apparatus

A chip fabricated from a semiconductor material is disclosed, which may include active devices located below a first depth from the chip back side, and a structure to remove heat from the active devices to the chip back side. The structure may include thermally conductive partial vias (TCPVs), which may include a recess with a depth, from the chip back side towards the active devices less than the first depth. Each TCPV may include a barrier layer deposited within the recess and deposited upon the back side of the chip. Each TCPV may also include a thermally conductive layer deposited upon the barrier layer. The structure may also include through-silicon vias (TSVs) electrically connected to active devices, extending from the back side to an active device side of the chip to conductively remove heat from the active devices to the back side of the chip.

Halbleiterbauelement

Dieses Halbleiterbauelement wird durch Stapeln mehrerer Halbleiterchips ausgebildet, die jeweils mehrere Bump-Elektroden besitzen, wobei jeder der mehreren Halbleiterchips mit einem auf einer jeweiligen Seitenfläche ausgebildeten Identifikationsabschnitt versehen ist. Jeder Halbleiterchip besitzt eine ähnliche Anordnung für seine jeweiligen mehreren Bump-Elektroden, und jeder Identifikationsabschnitt ist so ausgebildet, dass die Positionsbeziehung mit einer jeweiligen Referenz-Bump-Elektrode, an einem spezifischen Ort unter den jeweiligen mehreren Bump-Elektroden vorgesehen, in jedem Halbleiterchip die gleiche ist. Die mehreren Halbleiterchips werden derart gestapelt, dass die darauf vorgesehenen Bump-Elektroden elektrisch in der Reihenfolge des Stapelns der Halbleiterchips verbunden werden, während die Seitenflächen, auf denen die Identifikationsabschnitte ausgebildet sind, in der gleichen Richtung orientiert sind.

ELECTRICAL COMPONENTS AND MOUNTING THEREOF

... 1299541 Beam lead integrated circuits; assembing components WESTERN ELECTRIC CO Inc 15 Jan 1970 [21 Jan 1969 (2) 29 April 1969] 1998/70 Headings H1K and H1R A method of assembling an electrical component, e.g. a beam lead integrated circuit, in a predetermined position relative to external circuitry comprises providing co-operating ferromagnetic means in or affixed to the electrical component and the external circuitry such that the magnetic force exerted by the co-operating magnetic means serves to align the component in the predetermined position. The ferromagnetic means associated with the component may be in the leads or on the body of the component and may be in the form of a coating applied by, for example, sputtering, evaporating or plating or may be deposited during production of the component as an embedded layer. The ferromagnetic means associated with the external circuitry may be integral therewith or in the form of a coating. Alternatively, an electromagnet may be affixed to ...

Semiconductor device, solid-state imaging device and imaging apparatus

Semiconductor device and method of manufacturing the semiconductor device

According to one embodiment, a first electrode is formed on a first face of a first semiconductor chip, and a second electrode and a protrusion are formed on a second face of a second semiconductor chip. The first semiconductor chip and the second semiconductor chip are spaced from one another by the protrusion in such a manner that the first face and the second face face each other. The first semiconductor chip and the second semiconductor chip are subject to reflow to be electrically connected to each other, and then the protrusion is cured at a temperature lower than a reflow temperature.

FILM-LIKE ADHESIVE, ADHESIVE SHEET FOR SEMICONDUCTOR JUNCTION, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

This film-like adhesive contains a binder resin (A), epoxy resin (B), hardener (C), and filler (D), wherein the total light transmittance in a D65 standard light source is 70% or higher and the haze value is 50% or lower. Provided are a film-like adhesive that makes it possible to die bond semiconductor chips accurately at predetermined positions in flip mounting as well as to produce semiconductor devices having high package reliability, and an adhesive sheet for a semiconductor junction using the adhesive.

Verfahren zur Kalibrierung einer Vorrichtung für die Montage von Bauelementen

Die Erfindung betrifft die Kalibrierung einer Bauelemente-Montagevorrichtung, die eingerichtet ist für die Montage von Bauelementen auf einem Substrat, dessen Montageplätze keine lokalen Markierungen enthalten. Das Substrat enthält entweder an seinem Rand angebrachte globale Substratmarkierungen oder andere globale Merkmale, die für die Montage der Bauelemente herangezogen werden können. Die Kalibrierung erfolgt mittels einer Kalibrierplatte (1), die mehrere, zweidimensional über die Kalibrierplatte (1) verteilte und mit ersten optischen Markierungen (3) versehene Kalibrierpositionen (2) aufweist, einem Testchip (5), der zweite optische Markierungen (6) aufweist, und einer an der Bondstation (17) angebrachten Halterung (9) für die temporäre Aufnahme der Kalibrierplatte (1). Die Anzahl und Anordnung der Kalibrierpositionen (2) der Kalibrierplatte (1) und die Anzahl und Anordnung der Montageplätze des Substrats sind - abgesehen von möglichen Ausnahmefällen - verschieden voneinander.

Array substrate, flip-chip film, alignment method thereof and display device

Stacked chips with through electrodes

A semiconductor device according to the present invention includes: a combination object; and a chip having a front surface opposed to a front surface of the combination object. The chip includes: a multi-level wiring structure provided in the front surface of the chip; a connection electrode provided in the multi-level wiring structure and electrically connected to the combination object; an alignment mark set provided in the multi-level wiring structure and electrically isolated from the connection electrode; and an electrically conductive film provided at a higher level than the alignment mark set in association with the multi-level wiring structure to cover the alignment mark set and electrically isolated from the connection electrode.

Semiconductor device and a method of manufacturing the same

To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

Display device and manufacturing method of the same

The present invention enhances the mounting accuracy of a drive circuit chip on a substrate thus realizing a display of high quality. Bumps (for example, gold bumps) on the drive circuit chip are used for alignment. Here, to enhance the recognition property of the alignment bumps, a plane shape of a conductive layer which is formed between a semiconductor substrate (Si substrate) of the drive circuit chip and the alignment bump is set to be included within a profile of a plane shape of the alignment bump. That is, by preventing the conductive layer from being observed in a periphery of the alignment bump, it is possible to prevent a photographed pattern of the bump taken by a camera or the like from be influenced by the conductive layer.

Semiconductor device and a method of manufacturing the same

To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

Integrated circuit and display device including the same

An integrated circuit that includes a substrate, a semiconductor layer arranged on the substrate and an insulating layer arranged on an upper portion of the semiconductor layer and including a bump provided on an upper surface thereof, wherein the semiconductor layer includes a main semiconductor area and an including an internal alignment mark including a p-type semiconductor that is overlapped by a metallic external alignment mark arranged on the upper surface of the insulating layer. The p-type semiconductor internal alignment mark can be viewed by an infrared camera during a mounting process of the integrated circuit.

Semiconductor device

The utility model provides high semiconductor device's reliability. Probe regional (PBR) at the pad (PD) by protective insulation membrane (PIF) cover is formed with probe vestige (PM). And cylindrical electrode (PE) has: 1st part of formation on open area (OP2), go up the 2nd part of extending to probe regional (PBR) with follow open area (OP2). At this moment, open area's (OP2) center is skew for the cylindrical electrode's (PE) relative with joint finger -type portion center.

Semiconductor chip and stack chip semiconductor package

SEMICONDUCTOR PACKAGE AN AND METHOD FOR MANUFACTURING SAME

The present invention provides a semiconductor package and a method for manufacturing the same. The semiconductor package may include: a first semiconductor chip mounted on a substrate; a second semiconductor chip mounted on an upper plane of the first semiconductor chip; a connection bump which is intervened between the first semiconductor chip and the second semiconductor chip, and connects the second semiconductor chip to the first semiconductor chip electrically; and a thermal pad which is arranged on the upper plane of the first semiconductor chip, and is separated from a lower plane of the second semiconductor chip. The objective of the present invention is to provide the reliable semiconductor package, by improving heat radiation of the semiconductor chip. COPYRIGHT KIPO 2016 ...

Bonding apparatus and bonding method

Microelectronic element bonding with deformation of leads in rows

A method of making a microelectronic assembly includes bonding a plurality of lead connection sections arranged in a row to contacts of a microelectronic element such as a semiconductor chip having contacts in rows at the periphery of the chip. The leads have terminal sections secured to a dielectric support structure, and horizontally curved sections between the terminal regions and bond regions. After bonding, the dielectric support structure is lifted upwardly relative to the chip, so as to bend the leads into a vertically-extensive orientation. Partial straightening of the original horizontal curvature allows each lead to stretch and accommodate the vertical movement.

METHOD FOR PROCESSING A BASE

The present invention realizes a semiconductor device of high reliability which allows metal terminals which have a uniform height, are flat and smooth to be formed under low load and at low costs and to be mounted with low damage. The electrodes 5 and the insulating film 6 are both formed of materials having the property that they are solid and do not exhibit the adhesiveness at room temperature and exhibit the adhesiveness at a temperature not lower than a first temperature and cure at a temperature not lower than a second temperature higher than the first temperature. The surfaces of the electrodes 5 and the insulating film 6 of a semiconductor chip 1a are planarized in continuously flat with a hard cutting tool, as of diamond or others.

CONNECTION BODY, METHOD FOR MANUFACTURING A CONNECTION BODY, CONNECTING METHOD AND ANISOTROPIC CONDUCTIVE ADHESIVE AGENT

Ensure conduction between an electronic component and a circuit substrate having reduced pitches in wiring of the circuit substrate or electrodes of the electronic component and prevent short circuits between electrode terminals of the electronic component. A connection body including an electronic component connected to a circuit substrate via an anisotropic conductive adhesive agent containing conductive particles; wherein the conductive particles are regularly arranged; and wherein the conductive particles have a particle diameter that is ½ or less than a height of a connecting electrode of the electronic component.

Film-like adhesive, adhesive sheet for semiconductor joint, and method of manufacturing semiconductor device

Connection body

METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE

Provided is a method for manufacturing a semiconductor device that solders to connect a semiconductor chip having bumps via a heat-hardened bonding agent layer to a substrate having an electrode corresponding to the bumps that includes, in succession, (A) a process for forming the heat-hardened bonding layer in advance on a surface having the bumps of a semiconductor chip; (B) a process that matches the surface on the heat-hardened bonding agent layer side of the semiconductor chip formed with a heat-hardened bonding agent layer to a substrate, and pre-bonds by using a heat seal to obtain a pre-bonded layer; and (C) places a protective film having thermal conductivity of at least 100 W/mK between the heat seal and the surface on the semiconductor chip side of the pre-bonded layer and uses a heat seal to harden the heat-hardened bonding agent layer simultaneously to melting the solder between the semiconductor chip and the substrate. A method for manufacturing a semiconductor device is that ...

Semiconductor element and wafer level chip size package therefor

A semiconductor device, encapsulated in a wafer level chip size package (WLCSP), includes a plurality of pad electrodes formed on the surface of a semiconductor chip, wherein a first insulating layer is formed on the surface of the semiconductor chip except the pad electrodes; a plurality of connection electrodes and at least one heat-dissipation electrode are formed on the surface of the first insulating layer; the pad electrodes and the connection electrodes are mutually connected via a first wiring portion; the heat-dissipation electrode is connected with a second wiring portion; and a second insulating layer is formed to enclose the electrodes and wiring portions, wherein the second wiring portion is arranged in proximity to a heating portion of the semiconductor chip and is formed on the surface of the first insulating layer except the prescribed region corresponding to the first wiring portion.

SEMICONDUCTOR MANUFACTURING METHOD, SEMICONDUCTOR MANUFACTURING APPARATUS AND SEMICONDUCTOR DEVICE

A semiconductor manufacturing method of mounting a semiconductor chip or a stacked body of semiconductor chips on a support substrate placed on a stage, determines whether a predetermined condition is satisfied during a mounting processing of the semiconductor chip or the stacked body, evacuates, together with the support substrate, the semiconductor chip or the stacked body that has mounted on the support substrate before the determination when it is determined that the predetermined condition is satisfied, determines whether to resume the mounting processing of the semiconductor chip or the stacked body after the evacuation; and returns the evacuated semiconductor chip or the evacuated stacked body to a position before the evacuation and continuing the mounting processing when it is determined that the mounting processing is resumed. 1. A semiconductor manufacturing method of mounting a semiconductor chip or a stacked body of semiconductor chips on a support substrate placed on a stage , the method comprising:determining whether a predetermined condition is satisfied during a mounting processing of the semiconductor chip or the stacked body;evacuating, together with the support substrate, the semiconductor chip or the stacked body that has mounted on the support substrate before the determination when it is determined that the predetermined condition is satisfied;determining whether to resume the mounting processing of the semiconductor chip or the stacked body after the evacuation; andreturning the evacuated semiconductor chip or the evacuated stacked body to a position before the evacuation and continuing the mounting processing when it is determined that the mounting processing is resumed.2. The semiconductor manufacturing method according to claim 1 ,wherein the determining whether the predetermined condition is satisfied includes determining whether an apparatus performing the mounting processing stops, andwherein the evacuating the semiconductor chip or the ...

Method of manufacturing semiconductor device, and mounting device

The disclosure is provided with: a temporary crimping step in which one or more semiconductor chips 10 are sequentially laminated while being temporarily crimped in each of two or more locations on a substrate 30 to thereby form chip stacks ST in a temporarily crimped state; and a permanent crimping step in which the top surfaces of all of the chip stacks ST formed in the temporarily crimped state are sequentially heated, pressurized, and permanently crimped. Furthermore, a specifying step is provided prior to the temporary crimping step for specifying a separation distance Dd which is the distance from the chip stacks ST under permanent crimping to a location at which the temperature of the substrate 30, the temperature having been raised by heating for the permanent crimping, becomes less than or equal to a prescribed permissible temperature Td, and in the temporary crimping step, the chip stacks ST in the temporarily crimped state are formed separated from each other by the separation ...

SEMICONDUCTOR CHIP OF CHIP-ON-CHIP, SEMICONDUCTOR DEVICE, AND MOUNTING METHOD

PROBLEM TO BE SOLVED: To commercialize a chip-on-chip structure wherein a plurality of semiconductor chips are stacked and jointed so that the surfaces face each other. SOLUTION: A positioning small hole 28 penetrating from a front surface 21 to a rear surface 23 is formed on a daughter chip 2. The positioning small hole 28 is so formed as to establish a specified positional relation ship with an electrode formed on the surface 21. The positioning small hole 28 is formed with a very small drill, water drill using a high water pressure, laser ray, and etching, etc. The positioning small hole 28 has a specified positional relation ship with an electrode 23. So, when the daughter chip 2 is stacked facedown on the surface 11 of a mother chip 1, the mother chip 1 is aligned with the daughter chip 2 with the positional small hole 28 which is confirmed from the rear surface 24 of the daughter chip 2 as a reference. COPYRIGHT: (C)2000,JPO ...

Wafer alignment system with optical coherence tomography

A system for performing alignment of two wafers is disclosed. The system comprises an optical coherence tomography system and a wafer alignment system. The wafer alignment system is configured and disposed to control the relative position of a first wafer and a second wafer. The optical coherence tomography system is configured and disposed to compute coordinate data for a plurality of alignment marks on the first wafer and second wafer, and send that coordinate data to the wafer alignment system.

Semiconductor device and a method of manufacturing the same

To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layeras that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

ELECTRONIC-COMPONENT MOUNTED BODY, ELECTRONIC COMPONENT, AND CIRCUIT BOARD

Semiconductor element and wafer level chip size package therefor

A semiconductor device, encapsulated in a wafer level chip size package (WLCSP), includes a plurality of pad electrodes formed on the surface of a semiconductor chip, wherein a first insulating layer is formed on the surface of the semiconductor chip except the pad electrodes; a plurality of connection electrodes and at least one heat-dissipation electrode are formed on the surface of the first insulating layer; the pad electrodes and the connection electrodes are mutually connected via a first wiring portion; the heat-dissipation electrode is connected with a second wiring portion; and a second insulating layer is formed to enclose the electrodes and wiring portions, wherein the second wiring portion is arranged in proximity to a heating portion of the semiconductor chip and is formed on the surface of the first insulating layer except the prescribed region corresponding to the first wiring portion.

CHIP-PLACING METHOD PERFORMING AN IMAGE ALIGNMENT FOR CHIP PLACEMENT AND CHIP-PLACING APPARATUS THEREOF

A chip-placing method for performing an image alignment of chip placement comprises a chip pick-up step, a reference-image capturing step, an alignment-image capturing step, a calculating and processing step, a calibration adjusting step and a placing step. An image(s) of a marking member and a chip sucked by a chip-placing member is/are captured from an opposite direction so as to obtain a relative position information of the chip in relation to the marking member. An image showing the marking member and the substrate is captured from a backside so as to obtain a relative position information of the marking member in relation to the substrate. A position calibration relationship information of the position of the chip in relation to a to-be-placed location of the substrate is obtained according to those relative position information. Therefore, a relative position of the chip-placing member in relation to the to-be-placed location is calibrated.

접속체, 접속체의 제조 방법, 전자 기기

... 도전성 입자가 기판 전극과 전극 단자의 단부 사이로 맞물려 들어가도, 기판 전극 및 전극 단자의 각 주면부에 협지되어 있는 도전성 입자를 충분히 압입하여, 도통성을 확보한다. 회로 기판(12)에 이방성 도전 접착제(1)를 개재하여 전자 부품(18)이 접속되고, 회로 기판(12)의 기판 전극(17a) 및 전자 부품(18)의 전극 단자(19)에는, 각 측가장자리부에 서로 맞대어지는 단부(27, 28)가 형성되고, 기판 전극(17a) 및 전극 단자(19)는 각 주면부 사이 및 단부(27, 28) 사이에 도전성 입자(4)가 협지되고, 도전성 입자(4)와 단부(27, 28)가 (1) a＋b＋c≤0.8D 를 만족한다. [a : 전극 단자의 단부 높이, b : 기판 전극의 단부 높이, c : 단부 사이 갭, D : 도전성 입자의 직경] ...

SEMICONDUCTOR ELEMENT AND WAFER LEVEL CHIP SIZE PACKAGE THEREFOR

Semiconductor device and method for manufacturing the same

A system and method for determining underfill expansion is provided. An embodiment includes forming cover masks along a top surface of a substrate, attaching a semiconductor substrate to the top surface of the substrate, placing an underfill material between the semiconductor substrate and the substrate, and then using the cover masks to determine the expansion of the underfill over the top surface of the substrate. Additionally, cover masks on both the substrate and the semiconductor substrate may be used together as alignment masks during the alignment of the substrate and the semiconductor substrate.

Self-alignment for redistribution layer

An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value.

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME

To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1is formed in the same layer as that of a second layer wiring and the pattern P1is formed in the same layer as that of a first layer wiring. Further, the pattern P is formed in the same layer as that of a gate electrode, and the pattern P is formed in the same layer as that of an element isolation region. 128-. (canceled)29. A semiconductor device comprising:a semiconductor substrate;an integrated circuit region in which a plurality of MISFETs are formed;an alignment mark region in which an alignment mark is formed;a first wiring layer formed over the integrated circuit region and the alignment mark region;a second wiring layer formed over the first wiring layer; anda plurality of STI regions formed in the semiconductor substrate and in the alignment mark region, a plurality of first wirings formed in the integrated circuit region, and which are electrically coupled to the plurality of MISFETs; and', 'a plurality of dummy wiring regions formed in the alignment mark region, and which are not electrically coupled to the plurality of MISFETs,, 'wherein the first wiring layer comprises the alignment mark formed in the alignment mark region; and', 'a plurality of second wirings formed in the integrated circuit region,, 'wherein the second wiring layer comprises a first dummy wiring region disposed to overlap with the alignment mark; and', 'a second dummy wiring region disposed to not overlap with the alignment ...

Semiconductor package and method of fabricating the same

Array substrate three,chip on,film display device and alignment method

BONDING METHOD OF THE SEMICONDUCTOR SUBSTRATE TO PREVENT MISMATCH OF WAFER AND THE LAMINATE MANUFACTURED THEREBY

PURPOSE: A bonding method and the laminate of the semiconductor substrate manufactured thereby are provided to prevent the mismatch of wafer and bond the bump and the pad. CONSTITUTION: The interlayer adhesive is coated between the side having the pad of the first semiconductor substrate and the side having the bump of the second semiconductor substrate to interconnect each other. The location of the second semiconductor substrate and the first semiconductor substrate are adjusted. In the second process, the adhesive(27) is coated on the first semiconductor substrate whose location is adjusted and the neighboring of the second semiconductor substrate and then it is cured. Thereafter, the first semiconductor substrate and the second semiconductor substrate are heated up and compressed to connect the pad and the bump. © KIPO 2009 ...

BONDING APPARATUS AND BONDING METHOD

半導体装置の検査装置及び半導体装置の検査方法

Verfahren zur Positionierung eines elektrischen Schaltungselementes sowie Schaltungselement und Halterungselement zur Durchfuehrung eines solchen Verfahrens

접착제 조성물 및 접착제 시트, 반도체 장치 보호용 재료, 및 반도체 장치

... 본 발명은 압착시의 접착성이 우수하고, 경화했을 때의 접속 신뢰성 및 절연 신뢰성이 우수한 반도체 장치용의 접착제 조성물 및 그것을 사용한 접착제 시트를 제공하는 것을 목적으로 한다. 구체적으로는 (A) 하기 화학식 1로 표시되는 반복 단위로 구성되는 실리콘 수지, (B) 열경화성 수지 및 (C) 플럭스 활성을 갖는 화합물을 포함하는 것임을 특징으로 하는 접착제 조성물을 제공한다. <화학식 1> (식 중, R1 내지 R4는 동일하거나 상이할 수 있는 탄소수 1 내지 8의 1가 탄화수소기를 나타내고, l 및 m은 1 내지 100의 정수이고, a, b, c 및 d는 0 또는 양수이고, 0<(c+d)/(a+b+c+d)≤1.0을 만족하고, X, Y는 2가의 유기기임) ...

Microelectronic packages with dual or multiple-etched flip-chip connectors

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Semiconductor Structures and Method for Fabricating the Same

A semiconductor structure is provided. The semiconductor structure includes a first substrate, a second substrate opposite to the first substrate, a plurality of spacers disposed between the first substrate and the second substrate, and an adhesive material bonded with the first substrate and the second substrate within the two adjacent spacers. The invention also provides a method for fabricating the semiconductor structure.

Method of manufacturing semiconductor device including plural semiconductor chips stacked together

Such a method is disclosed that includes preparing first and second semiconductor chips, the first semiconductor chip including a first electrode formed on one surface thereof and a second electrode formed on the other surface thereof so as to overlap the first electrode as viewed from a stacking direction, and the second semiconductor chip including a third electrode formed on one surface thereof and a fourth electrode formed on the other surface thereof so as not to overlap the third electrode as viewed from the stacking direction, and stacking the first and second semiconductor chips in the stacking direction so that the second electrode is connected to the third electrode by using a bonding tool including a concave at a position corresponding to the fourth electrode.

Semiconductor device and method of fabricating the semiconductor device

A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal.

Chip package with plank stack of semiconductor dies

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

Interconnection and assembly of three-dimensional chip packages

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are aligned by positive features that are mechanically coupled to negative features recessed below the surfaces of adjacent semiconductor dies. Moreover, the chip package includes an interposer plate at approximately a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the interposer plate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as solder balls or spring connectors. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the interposer plate.

Semiconductor Device and Method of Forming a Metallurgical Interconnection Between a Chip and a Substrate in a Flip Chip Package

A method for forming metallurgical interconnections and polymer adhesion of a flip chip to a substrate includes providing a chip having a set of bumps formed on a bump side thereof and a substrate having a set of interconnect points on a metallization thereon, providing a measured quantity of a polymer adhesive in a middle region of the chip on the bump side, aligning the chip with the substrate so that the set of bumps aligns with the set of interconnect points, pressing the chip and the substrate toward one another so that a portion of the polymer adhesive contacts the substrate and the bumps contact the interconnect points, and heating the bumps to a temperature sufficiently high to form a metallurgical connection between the bumps and the interconnect points.

Packaging Process Tools and Systems, and Packaging Methods for Semiconductor Devices

Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.

Substrate and semiconductor device

A substrate includes a base member having a predetermined thickness, and an electrode array provided in one surface in a thickness direction of the base member and having a plurality of electrodes arranged two-dimensionally in a plan view, and the electrode array includes a central portion and an incremental region provided around the central portion in the planar view and is formed so that a height of the electrodes in the incremental region gradually increase as approaching toward the central portion.

Wiring substrate, manufacturing method thereof, and semiconductor package

A disclosed wiring substrate includes an insulating layer, a recess formed on a surface of the insulating layer, and an alignment mark formed inside of the recess, wherein a face of the alignment mark is roughened, recessed from the surface of the insulating layer, and exposed from the recess.

Integrated circuit and display device including the same

An integrated circuit that includes a substrate, a semiconductor layer arranged on the substrate and an insulating layer arranged on an upper portion of the semiconductor layer and including a bump provided on an upper surface thereof, wherein the semiconductor layer includes a main semiconductor area and an including an internal alignment mark including a p-type semiconductor that is overlapped by a metallic external alignment mark arranged on the upper surface of the insulating layer. The p-type semiconductor internal alignment mark can be viewed by an infrared camera during a mounting process of the integrated circuit.

COMPONENT MOUNTING SYSTEM, RESIN SHAPING DEVICE, RESIN PLACING DEVICE, COMPONENT MOUNTING METHOD, AND RESIN SHAPING METHOD

A chip mounting system () includes: a chip supplying unit () for supplying a chip (CP); a stage () for holding a substrate (WT) in an orientation in which a mounting face (WTf) for mounting the chip (CP) faces vertically downward (−Z direction); a head (H) for holding the chip (CP) from the vertically downward direction (−Z direction); and a head drive unit () for, by causing vertically upward (+Z direction) movement of the head (H) holding the chip (CP), causes the head (H) to approach the stage () to mount the chip (CP) on the mounting face (WTf) of the substrate (WT). 1. A component mounting system for mounting a component on a substrate , the mounting system comprising:a component supplying unit configured to supply the component;a substrate holding unit configured to hold the substrate in an orientation such that a mounting face for mounting the component on the substrate is facing vertically downward;a head configured to hold the component from vertically below; anda head drive unit that, by causing vertically upward movement of the head holding the component, causes the head to approach the substrate holding unit to mount the component on the mounting face of the substrate.2. The component mounting system according to claim 1 , wherein the component supplying unit comprises (i) a sheet holding unit configured to hold a dicing substrate such that a sheet is positioned vertically upward of the dicing substrate claim 1 , the dicing substrate being the substrate diced and attached to the sheet claim 1 , and (ii) a picking mechanism configured to the component included in the dicing substrate by pick out vertically downward from vertically above the sheet.3. The component mounting system according to claim 1 , wherein the component mounting system further comprises a component conveying unit configured to convey the component supplied from the component supplying unit to a receiving position for the head to receive the component.4. The component mounting system ...

Thin Wafer Handling and Known Good Die Test Method

A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate. 1. A method of attaching a microelectronic element to a substrate , comprising:aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, the bumps exposed at a front surface of the microelectronic element, the substrate having a plurality of spaced-apart recesses extending from a first surface thereof, the recesses each having at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed; andreflowing the bumps so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.2. The method as claimed in claim 1 , wherein the substrate is a handling substrate claim 1 , and all of the inner surfaces of at least some of the recesses are non-wettable by the bond metal of which the bumps are formed.3. The method as claimed in claim 1 , wherein the ...

METAL-FREE FRAME DESIGN FOR SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES

Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate. 1. A semiconductor structure , comprising:a substrate having an insulating layer thereon, the substrate having a perimeter, and the substrate comprising silicon;a metallization structure on the insulating layer, the metallization structure comprising conductive routing in a dielectric material stack;a first metal guard ring in the dielectric material stack and continuous around the conductive routing;a second metal guard ring in the dielectric material stack and continuous around the first metal guard ring;a plurality of staggered mini guard rings between the first metal guard ring and the second metal guard ring; anda metal-free region of the dielectric material stack surrounding the second metal guard ring, the metal-free region adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.2. The semiconductor structure of claim 1 , wherein at least one of the first metal guard ring or the second metal guard ring provides a hermetic seal for the metallization structure.3. The semiconductor structure of claim 1 , further comprising:a metal feature between the first metal ...

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

A solder connection may be surrounded by a solder locking layer () and may be recessed in a hole () in that layer. The recess may be obtained by evaporating a vaporizable portion () of the solder connection. Other features are also provided. 1. A manufacturing method comprising: one or more first components each of which comprises solder and a material sublimatable or vaporizable when the solder is melted; and', 'a first layer comprising a top surface and one or more holes in the top surface, each hole containing at least a segment of a corresponding first component;, 'obtaining a first structure comprisingheating each first component to sublimate or vaporize at least part of each sublimatable or vaporizable material and provide an electrically conductive connection at a location of each first component;wherein in the heating operation at least part of each first component recedes down from the top surface to provide or increase a recess in each hole at the top surface.2. The method of wherein each hole is a through-hole.3. The method of wherein each hole's sidewall is a dielectric sidewall.4. The method of wherein the first layer is dielectric.5. The method of wherein the first layer is formed by molding.6. The method of further comprising:obtaining a second structure with one or more protruding conductive posts; andinserting each conductive post into a corresponding recess provided or increased in the heating operation, and forming a solder bond in each recess between the corresponding conductive post and the corresponding electrically conductive connection.7. The method of wherein before the heating operation claim 1 , at least a segment of each first component either:comprises of a solder core coated with the sublimatable or vaporizable material; orconsists of the sublimatable or vaporizable material.8. The method of wherein in obtaining the first structure claim 7 , the one or more first components are formed before the first layer.9. The method of wherein in ...

Methods of fluxless micro-piercing of solder balls, and resulting devices

A method of establishing conductive connections is disclosed. The method includes providing an integrated circuit die having a plurality of solder balls each of which has an oxide layer on an outer surface of the solder ball. The method also includes performing a heating process to heat at least the solder balls and applying a force causing each of a plurality of piercing bond structures on a substrate to pierce one of the solder balls and its associated oxide layer to thereby establish a conductive connection between the solder ball and the piercing bond structure.

Semiconductor device and a method of manufacturing the same

To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P 1 a is formed in the same layer as that of a second layer wiring and the pattern P 1 b is formed in the same layer as that of a first layer wiring. Further, the pattern P 2 is formed in the same layer as that of a gate electrode, and the pattern P 3 is formed in the same layer as that of an element isolation region.

Underfill film, sealing sheet, method of manufacturing semiconductor device, and semiconductor device

The present invention provides an underfill film and a sealing sheet that are excellent in thermal conductive property and are capable of satisfactorily filling the space between the semiconductor element and the substrate. The present invention relates to an underfill film having a resin and a thermally conductive filler, in which a content of the thermally conductive filler is 50% by volume or more, an average particle size of the thermally conductive filler is 30% or less of a thickness of the underfill film, and a maximum particle size of the thermally conductive filler is 80% or less of the thickness of the underfill film.

METHOD OF MANUFACTURING ELECTRONIC DEVICE, AND ELECTRONIC COMPONENT MOUNTING DEVICE

An electronic component mounting device, includes a stage in which a plurality of stage portions are defined, a first heater provided in the plurality of stage portions respectively, and the first heater which can be controlled independently, a mounting head arranged over the stage, and a second heater provided in the mounting head. 110-. (canceled)11. A method of manufacturing an electronic device , comprising: a plurality of stage portions which are defined in the stage,', 'a groove portion formed on a surface of the stage portions,', 'an air supply route which is communicated with a bottom part of the groove portion;', 'wherein groove portion and the air supply route are provided independently in the stage portion respectively, and', 'a first pulse heater provided as individual heaters in the plurality of stage portions respectively, and wherein heating of each of the first pulse heater can be controlled independently;', 'a mounting head arranged over the stage in the process chamber, the mounting head being provided with in a second pulse heater;', 'a flux transfer head for transferring flux to an electronic component, the flux transfer head arranged over the stage in the process chamber;', 'a flux table into which flux is put, the flux table arranged in the process chamber;', 'a first alignment camera imaging an alignment mark of an electronic component structure which is to be arranged on the stage; and', 'a second alignment camera imaging an alignment mark of the electronic component fixed to the mounting head or the flux transfer head, 'a stage arranged in a process chamber, the stage including, 'preparing an electronic component mounting device which includesarranging an electronic component structure on the stage;transferring the flux onto a solder electrode of a first electronic component which is disposed on a first stage portion in the plurality of stage portions, by pushing the solder electrode of the first electronic component fixed to the flux ...

TOOLING FOR COUPLING MULTIPLE ELECTRONIC CHIPS

A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface. 1. A method comprising:constraining a portion of multiple chips adjacent a hardened material such that the hardened material and the multiple chips behave as a rigid body;transferring a force from the hardened material on the rigid body to the multiple chips to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element, without causing damage to the multiple chips or the bonding surface of the element; andremoving the hardened material from contact with the multiple chips.2. The method of claim 1 , further comprising moving the multiple chips constrained by the hardened material from a first location to a second location.3. The method of claim 1 , further comprising bonding each of the multiple chips to the element.4. The method of claim 1 , further comprising removing the rigid body using at least one of a chemical process claim 1 , a mechanical process claim 1 , or a chemical-mechanical process.5. The method of claim 1 , further comprising removing at least a portion of the hardened material through at least one of a chemical process claim 1 , a mechanical process claim 1 ...

Die-on-Interposer Assembly with Dam Structure and Method of Manufacturing the Same

A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip. 1. A package comprising:a chip having a frontside and a backside, the chip comprising four corner areas;a die bonded to the frontside of the chip by a first set of conductive connectors;a molding layer on the frontside of the chip and surrounding sidewalls of the die;a dam structure in each of the four corner areas on the backside of the chip, each of the dam structures being disposed a distance from an edge of the chip, each of the dam structures being circular in a plane parallel to the backside of the chip; anda second set of conductive connectors on the backside of the chip.2. The package of claim 1 , wherein the dam structure is electrically isolated from the chip.3. The package of claim 1 , wherein a distance between the frontside of the chip and a surface of the molding layer distal the frontside of the chip is greater than a distance between the frontside of the chip and a surface of the die distal the frontside of the chip.4. The package of claim 1 , further comprising a through via extending through the chip.5. The package of claim 4 , wherein the through via comprises a metal via and a barrier layer lining sidewalls of the metal via.6. The package of claim 5 , further comprising an insulation layer between the chip and the through via claim 5 , the insulation layer comprising an oxide.7. The package of claim 1 , wherein the dam structure comprises a polymer material.8. The package of claim 1 , wherein a diameter of the dam structure is less than a diameter of each of the conductive ...

Method and apparatus for producing semiconductor device

Disclosed is a method for producing a semiconductor device in which solder joints are made between a semiconductor chip with bumps and a substrate with electrodes corresponding to the bumps through a thermosetting adhesive layer, the method including the successive steps of: (A) forming a thermosetting adhesive layer in advance on a surface including bumps of the semiconductor chip; (B) laying a surface on the thermosetting adhesive layer side of the semiconductor chip, on which the thermosetting adhesive layer is formed, and a substrate one upon another, followed by pre-bonding using a heat tool to obtain a pre-bonded laminate; and (C) interposing a protective film having a thermal conductivity of 100 W/mK or more between the heat tool and a surface on the semiconductor chip side of the pre-bonded laminate, melting a solder between the semiconductor chips and the substrate and simultaneously curing the thermosetting adhesive layer using the heat tool. There is provided a method and an apparatus for producing a semiconductor device, which is capable of making a satisfactory joint without causing catching of a resin of an adhesive film between bumps and electrode pads.

High Speed Handling of Ultra-Small Chips by Selective Laser Bonding and Debonding

Techniques for high speed handling of ultra-small chips (e.g., micro-chips) by selective laser bonding and/or debonding are provided. In one aspect, a method includes: providing a first wafer including chips bonded to a surface thereof; contacting the first wafer with a second wafer, the second wafer including a substrate bonded to a surface thereof, wherein the contacting aligns individual chips with bonding sites on the substrate; and debonding the individual chips from the first wafer using a debonding laser having a small spot size of about 0.5 μm to about 100 μm, and ranges therebetween. A system is also provided that has digital cameras, a motorized XYZ-axis stage, and a computer control system configured to i) control a spot size of the at least one laser source and ii) adjust a positioning of the sample to align individual chips with a target area of the laser. 1. A system , comprising:at least one optical scannerat least one laser source optically connected to the at least one optical scanner, wherein the at least one laser source is configured to produce one or more of a bonding laser and a debonding laser;digital cameras optically connected to the at least one optical scanner;a motorized XYZ-axis stage;a sample on the motorized XYZ-axis stage, wherein the sample comprises a first wafer having chips bonded to a surface thereof in contact with a second wafer having a substrate bonded to a surface thereof; anda computer control system configured to i) control the at least one laser source, ii) read image information from the digital cameras to calculate alignment position; and iii) adjust a position of the motorized XYZ-axis stage to align individual chips with a target area of the at least one laser source.2. The system of claim 1 , wherein the at least one laser source comprises:a debonding laser source located on a first side of the sample; anda bonding laser source located on a second side of the sample opposite the first side.3. The system of claim 2 , ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

A semiconductor device including: a semiconductor chip; a plurality of insulating substrates mounted with the semiconductor chip; a printed circuit board facing the plurality of insulating substrates; and a conductive member for electrically connecting the plurality of insulating substrates and the printed circuit board is provided. The printed circuit board has a first through part arranged between the plurality of insulating substrates being adjacent to each other in a top view, and a second through part different from the first through part in shape in the top view. 1. A semiconductor device , comprising:a semiconductor chip;a plurality of insulating substrates mounted with the semiconductor chip;a printed circuit board facing the plurality of insulating substrates; anda conductive member for electrically connecting the plurality of insulating substrates and the printed circuit board, wherein a first through part arranged between the plurality of insulating substrates being adjacent to each other in a top view; and', 'a second through part different from the first through part in shape in a top view., 'the printed circuit board has2. The semiconductor device according to claim 1 , wherein the second through part is arranged between the plurality of insulating substrates being adjacent to each other in a top view.3. The semiconductor device according to claim 1 , whereinthe second through part has a cross-sectional shape having a major axis and a minor axis, andthe major axis is larger than a maximum width of a cross-sectional shape of the first through part.4. The semiconductor device according to claim 2 , whereinthe second through part has a cross-sectional shape having a major axis and a minor axis, andthe major axis is larger than a maximum width of a cross-sectional shape of the first through part.5. The semiconductor device according to claim 1 , whereinthe first through part and the second through part are aligned in a predetermined alignment direction, ...

Method for manufacturing semiconductor device and adhesive for mounting flip chip

The present invention aims to provide a method for producing a semiconductor device, the method being capable of achieving high reliability by suppressing voids. The present invention also aims to provide a flip-chip mounting adhesive for use in the method for producing a semiconductor device. The present invention relates to a method for producing a semiconductor device, including: step 1 of positioning a semiconductor chip on a substrate via an adhesive, the semiconductor chip including bump electrodes each having an end made of solder; step 2 of heating the semiconductor chip at a temperature of the melting point of the solder or higher to solder and bond the bump electrodes of the semiconductor chip to an electrode portion of the substrate, and concurrently to temporarily attach the adhesive; and step 3 of removing voids by heating the adhesive under a pressurized atmosphere, wherein the adhesive has an activation energy ΔE of 100 kJ/mol or less, a reaction rate of 20% or less at 2 seconds at 260° C., and a reaction rate of 40% or less at 4 seconds at 260° C., as determined by differential scanning calorimetry and Ozawa method.

SYSTEM AND METHODS FOR PRODUCING MODULAR STACKED INTEGRATED CIRCUITS

A system according to some examples herein includes a base chip which may include a plurality of attachment slots for attaching dies thereto. One or more of the attachment slots may be programmable attachment slots. The base chip may further include circuitry for interconnecting the dies attached to the base chip. For example, the base chip may include a plurality of cross bar switches, each of which is associated with respective ones of the plurality of attachment slots. The base chip may further include a configuration block, which is adapted to receive and transmit test signals for determining electrically connected signal lines of one or more attachment slots when one or more dies are attached to the base chip and which is further adapted to receive configuration data for programming signal (including power and ground) channels of the cross bar switches. 1. A system comprising: a plurality of attachment slots for attaching dies thereto;', 'a plurality of cross bar switches, each of the plurality of cross bar switches associated with respective ones of the plurality of attachment slots; and', 'a test and configuration block configured to receive and transmit test signals for determining electrically connected signal lines of one or more attachment slots when one or more dies are attached to the base chip and further configured to receive configuration data for programming one or more of the cross bar switches., 'a base chip including2. The system of claim 1 , wherein the test and configuration block comprises circuitry configured to generate the test signals for determining connectivity between metal contacts of the base chip and metal contacts of a die attached to the base chip.3. The system of claim 1 , wherein the test and configuration block comprises circuitry configured to determine connectivity between metal contacts of the base chip and metal contacts of a die attached to the base chip claim 1 , the metal contacts of the die having a different size or ...

Bonded assembly and display device including the same

A bonded assembly including: a first electronic component including a first substrate and a plurality of first electrodes disposed in a pressed area at a first height from a surface of the first substrate; a second electronic component including a second substrate and a plurality of second electrodes disposed at a second height from a surface of the second substrate, a second electrode overlapping with a corresponding first electrode to face the first electrode; a conductive bonding layer disposed between the first electrode and the second electrode overlapped with each other to bond the first electrode and the second electrode; and at least one spacer disposed between the first substrate and the second substrate to overlap the pressed area, the at least one spacer having a thickness that is greater than a value obtained by summing the first height and the second height.

MICRO-SELECTIVE SINTERING LASER SYSTEMS AND METHODS THEREOF

A microscale selective laser sintering (μ-SLS) that improves the minimum feature-size resolution of metal additively manufactured parts by up to two orders of magnitude, while still maintaining the throughput of traditional additive manufacturing processes. The microscale selective laser sintering includes, in some embodiments, ultra-fast lasers, a micro-mirror based optical system, nanoscale powders, and a precision spreader mechanism. The micro-SLS system is capable of achieving build rates of at least 1 cm/hr while achieving a feature-size resolution of approximately 1 μm. In some embodiments, the exemplified systems and methods facilitate a direct write, microscale selective laser sintering μ-SLS system that is configured to write 3D metal structures having features sizes down to approximately 1 μm scale on rigid or flexible substrates. The exemplified systems and methods may operate on a variety of material including, for example, polymers, dielectrics, semiconductors, and metals. 1. A system for additively producing a three-dimensional workpiece , the system comprising:an electromagnetic radiation source configured to coherently and intermittently emit an electromagnetic radiation beam; anda lens assembly having a plurality of micro-mirrors, collectively, forming a matrixed mirror array, each micro-mirror being configured to selectively direct the emitted electromagnetic radiation beam to a focus point on a sintering plane comprising a layer of particles to form one or a plurality of sintered layers, wherein each sintered layer is successively produced, in a layer-by-layer manner, to form the three-dimensional workpiece.2. The system of claim 1 , wherein the plurality of micro-mirrors direct the plurality of emitted electromagnetic radiation beams onto an area spanning a maximum cross-sectional profile of the three-dimensional workpiece.3. The system of claim 1 , comprising:a slot die coater, the slot die coater being configured to dispense a solvent having ...

Semiconductor device, solid-state imaging device, and imaging device

A semiconductor device includes a first substrate, a second substrate, a connection part, and an alignment mark. The connection part includes a first electrode which is disposed on the first substrate, a second electrode which is disposed on the second substrate, and a connection bump which connects the first electrode and the second electrode. The alignment mark includes a first mark which is disposed on the first substrate and a second mark which is disposed on the second substrate. A sum of a height of the first mark and a height of the second mark is substantially equal to a sum of a height of the first electrode, a height of the second electrode, and a height of the connection bump.

Method and apparatus for manufacturing a semiconductor device including a plurality of semiconductor chips connected with bumps

A method for manufacturing a semiconductor device including a plurality of semiconductor chips includes steps of placing, on a first semiconductor chip, a second semiconductor chip, such that a plurality of bumps is located between the first semiconductor chip and the second semiconductor chip, determining a distance between the first semiconductor chip and the second semiconductor chip, and determining whether or not the distance is within a predetermined range and stopping placement of additional chips if the distance is determined to be outside the predetermined range.

Circuit board structure and method for manufacturing a circuit board structure

The present publication discloses a method for manufacturing a circuit-board structure. In the method, a conductor layer is made, which comprises a conductor foil and a conductor pattern on the surface of the conductor foil. A component is attached to the conductor layer and the conductor layer is thinned, in such a way that the conductor material of the conductor layer is removed from outside the conductor pattern. 2. The circuit-board structure of claim 1 , wherein the conductor foil is on an insulating material layer.3. The circuit-board structure of claim 2 , further comprising a recess formed in the conductor foil and insulating material layer.4. The circuit-board structure of claim 3 , wherein the component is at least partially inside of the recess.5. The circuit-board structure of wherein the conductor pattern is on top of the conductor foil in openings of a conductor-pattern mask formed by a patterned insulating layer spread on the conductor foil.6. The circuit-board structure of claim 5 , wherein the patterned insulating layer is a resist layer.7. The circuit-board structure of claim 5 , wherein the patterned insulating layer is a photoresist layer.8. The circuit-board structure of further comprising a layer of a metal or metal alloy on the surface of the conductor pattern or on an interface between the conductor foil and the conductor pattern.9. The circuit-board structure of claim 1 , further comprising contact openings in the conductor pattern.10. The circuit-board structure of claim 8 , wherein the contact openings are through the conductor pattern and the conductor foil.11. The circuit-board structure of claim 1 , further comprising contact openings in the insulating material layer and the conductor foil.12. The circuit-board structure of claim 10 , further comprising contact openings in the conductor pattern.13. The circuit-board structure of claim 11 , wherein the contact openings in the conductor pattern layer corresponding to the contact openings ...

Methods and systems for manufacturing semiconductor devices

A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING APPARATUS

A method for manufacturing a semiconductor device includes determining a position of a first semiconductor chip having a plurality of first electrodes, using one or more first alignment marks formed on the first semiconductor chip, determining a position of a second semiconductor chip having a plurality of second electrodes, using one or more second alignment marks formed on the second semiconductor chip, moving the second semiconductor chip relative to the first semiconductor chip, based on the determined positions of the first and second semiconductor chips, such that the second electrodes are aligned with the first electrodes, after said moving, stacking the second semiconductor chip on the first semiconductor chip, such that the first electrodes are electrically connected to the second electrodes, and calculating a misalignment amount between the first semiconductor chip and the second semiconductor chip stacked thereon. 1. A method for manufacturing a semiconductor device , comprising:determining a position of a first semiconductor chip having a plurality of first electrodes, using one or more first alignment marks formed on the first semiconductor chip;determining a position of a second semiconductor chip having a plurality of second electrodes, using one or more second alignment marks formed on the second semiconductor chip;moving the second semiconductor chip relative to the first semiconductor chip, based on the determined positions of the first and second semiconductor chips, such that the second electrodes are aligned with the first electrodes;after said moving, stacking the second semiconductor chip on the first semiconductor chip, such that the first electrodes are electrically connected to the second electrodes; andcalculating a misalignment amount between the first semiconductor chip and the second semiconductor chip stacked thereon.2. The method according to claim 1 , whereinthe position of the first semiconductor chip is determined when the first ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a semiconductor substrate; a first pad and a second pad on a first top surface of the semiconductor substrate; a circuit board including a second top surface, a recess indented from the second top surface into the circuit board, a polymeric pad disposed on the second top surface and corresponding to the first pad, and an active pad disposed within the recess and corresponding to the second pad; a first bump disposed between and contacting the polymeric pad and the first pad; and a second bump disposed between and contacting the active pad and the second pad, wherein a height of the first bump is substantially shorter than a height of the second bump. 2. The semiconductor structure of claim 1 , wherein the height of the second bump is substantially equal to a total of the height of the first bump and a thickness of the polymeric pad.3. The semiconductor structure of claim 1 , wherein a depth of the recess is substantially equal to a thickness of the active pad.4. The semiconductor structure of claim 1 , wherein a first angle between the first bump and the polymeric pad is substantially greater than a second angle between the second bump and the active pad.5. The semiconductor structure of claim 1 , wherein the second angle is about 10% to 30% smaller than the first angle.6. The semiconductor structure of claim 1 , wherein the second top surface of the circuit board is substantially coplanar with a third top surface of the active pad.7. The semiconductor structure of claim 1 , wherein an aspect ratio of the first bump is substantially less than an aspect ratio of the second bump.8. The semiconductor structure of claim 1 , wherein the first bump is electrically isolated from the circuit board by the polymeric pad.9. The semiconductor structure of claim 1 , wherein a width of the active pad is substantially equal to a width of the polymeric pad.10. The semiconductor structure of claim 1 , wherein a thickness of the active pad is ...

Chip handling and electronic component integration

Small size chip handling and electronic component integration are accomplished using handle fixturing to transfer die or other electronic components from a full area array to a targeted array. Area array dicing of a thinned device wafer on a handle wafer/panel may be followed by selective or non-selective de-bonding of targeted die or electronic components from the handle wafer and optional attachment to a carrier such as a transfer head or tape. Alignment fiducials may facilitate precision alignment of the transfer head or tape to the device wafer and subsequently to the targeted array. Alternatively, the dies or other electronic elements are transferred selectively from either a carrier or the device wafer to the targeted array.

Semiconductor packages

A semiconductor package includes a first substrate, a first flow channel and a second flow channel. The first flow channel is on the first substrate. The second flow channel is on the first substrate and in fluid communication with the first flow channel. The second flow channel is spaced from an inlet and an outlet of the first flow channel. The first flow channel and the second flow channel constitute a bonding region of the first substrate.

METAL-FREE FRAME DESIGN FOR SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES

Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate. 1. A semiconductor structure , comprising:a substrate having an insulating layer thereon, the substrate having a perimeter, and the substrate comprising silicon;a metallization structure on the insulating layer, the metallization structure comprising conductive routing in a dielectric material stack;a first metal ring in the dielectric material stack and continuous around the conductive routing;a second metal ring in the dielectric material stack and continuous around the first metal ring;a plurality of staggered non-continuous metal rings between the first metal ring and the second metal ring; anda metal-free region of the dielectric material stack surrounding the second metal ring, the metal-free region adjacent to the second metal ring and adjacent to the perimeter of the substrate.2. The semiconductor structure of claim 1 , wherein at least one of the first metal ring or the second metal ring provides a hermetic seal for the metallization structure.3. The semiconductor structure of claim 1 , further comprising:a metal feature between the first metal ring and the second metal ring, the metal ...

SOLDER MEMBER MOUNTING METHOD AND SYSTEM

A solder member mounting method includes providing a substrate having bonding pads formed thereon, detecting a pattern interval of the bonding pads, selecting one of solder member attachers having different pattern intervals from each other, such that the one selected solder member attacher of the solder member attachers has a pattern interval corresponding to the detected pattern interval of the bonding pads, and attaching solder members on the bonding pads of the substrate, respectively, using the one selected solder member attacher. 1. A solder member mounting method , comprising:providing a substrate having bonding pads formed thereon;detecting a pattern interval of the bonding pads;selecting one of solder member attachers having different pattern intervals from each other, such that the one selected solder member attacher of the solder member attachers has a pattern interval corresponding to the detected pattern interval of the bonding pads; andattaching solder members on the bonding pads of the substrate, respectively, using the one selected solder member attacher.2. The method as claimed in claim 1 , wherein attaching the solder members on the bonding pads includes:applying a vacuum pressure to holding-holes of the solder member attacher to hold solder balls; andremoving the vacuum pressure from the holding-holes of the solder member attacher, such that the solder balls are attached on the bonding pads of the substrate.3. The method as claimed in claim 1 , wherein attaching the solder members on the bonding pads includes:positioning a ball mask having through-holes for passing solder balls therethrough;moving the solder balls into the through-holes of the ball mask; andremoving the ball mask from the substrate to attach the solder balls on the bonding pads.4. The method as claimed in claim 1 , wherein attaching the solder members on the bonding pads includes:positioning a paste mask having through-holes for coating solder paste; andprinting the solder paste ...

ROOM TEMPERATURE METAL DIRECT BONDING

A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed. 1. A bonded structure comprising:a first plurality of metallic pads disposed on a first substrate;a first non-metallic region located on a first surface of said first substrate proximate to the first plurality of metallic pads;a second plurality of metallic pads disposed on a second substrate; anda second non-metallic region located on a second surface of the second substrate proximate to the second plurality of metallic pads,wherein a portion of each metallic pad of the first plurality of metallic pads directly contacts a corresponding metallic pad of the second plurality of metallic pads to form a metallic contact, andwherein the first non-metallic region contacts and is directly bonded to the second non-metallic region along an interface, the interface between the first non-metallic region and the second non-metallic region extending substantially to the metallic contact.2. The bonded structure of claim 1 , wherein each metallic pad comprises a reflowable material.3. The bonded structure of claim 1 , wherein the first non-metallic region comprises silicon oxide. This application is a continuation of application Ser. No. 14/959,204 filed Dec. 4, 2015, which is a continuation of application Ser. No. 14/474,476 ...

Chip stack with electrically insulating walls

A chip stack is provided and includes two or more chips, a solder joint operably disposed between adjacent ones of the two or more chips, the solder joint occupying about 25-30% or more of an area of the chip stack and insulating walls disposed on at least one of the two or more chips to separate the solder joint from an adjacent solder joint.

SEMICONDUCTOR DEVICES WITH UNDERFILL CONTROL FEATURES, AND ASSOCIATED SYSTEMS AND METHODS

Semiconductor devices with underfill control features, and associated systems and methods. A representative system includes a substrate having a substrate surface and a cavity in the substrate surface, and a semiconductor device having a device surface facing toward the substrate surface. The semiconductor device further includes at least one circuit element electrically coupled to a conductive structure. The conductive structure is electrically connected to the substrate, and the semiconductor device further has a non-conductive material positioned adjacent the conductive structure and aligned with the cavity of the substrate. An underfill material is positioned between the substrate and the semiconductor device. In other embodiments, in addition to or in lieu of the con-conductive material, a first conductive structure is connected within the cavity, and a second conductive structure connected outside the cavity. The first conductive structure extends away from the device surface a greater distance than does the second conductive structure. 1. A semiconductor device assembly , comprisinga substrate having a substrate surface and a cavity in the substrate surface;a semiconductor device having a device surface facing toward the substrate surface, the semiconductor device further having at least one circuit element electrically coupled to a conductive structure, wherein the conductive structure is electrically connected to the substrate, the semiconductor device further having a non-conductive material positioned adjacent the conductive structure and aligned with the cavity of the substrate; andan underfill material positioned between the substrate and the semiconductor device.2. The system of wherein the non-conductive material does not extend laterally outwardly beyond the cavity.3. The system of wherein a thickness of the non-conductive material and a depth of the cavity are at least approximately the same.4. The system of wherein the non-conductive material ...

Method of aligning wafers, method of bonding wafers using the same, and apparatus for performing the same

In a method of aligning wafers, a second wafer having at least one second alignment key may be arranged over a first wafer having at least one first alignment key. At least one alignment hole may be formed by passing through the second wafer to expose the second alignment key and the first alignment key. The first wafer and the second wafer may be aligned with each other using the first alignment key and the second alignment key exposed through the alignment hole. Thus, the first alignment key and the second alignment key exposed through the alignment hole may be positioned at a same vertical line to accurately align the first wafer with the second wafer.

BONDING SUBSTRATES USING SOLDER SURFACE TENSION DURING SOLDER REFLOW FOR THREE DIMENSIONAL SELF-ALIGNMENT OF SUBSTRATES

Methods are provided for bonding substrates together using alignment structures and solder reflow techniques which achieve self-alignment in three dimensions, as well as semiconductor structures that are formed using such methods. A first alignment structure is formed on a bonding surface of a first substrate, which includes an alignment trench formed in the bonding surface of the first substrate. A second alignment structure is formed on a bonding surface of a second substrate, which includes a bonding pad with solder formed on the bonding pad. The first and second substrates are placed together with the solder of the second alignment structure in contact with the first alignment structure. A solder reflow process causes the solder to melt and flow into the alignment trench while pulling on the bonding pad to cause the second substrate to move into alignment with the first substrate in each of X, Y, and Z directions. 1. A method , comprising:forming a first alignment structure on a first substrate, wherein the first alignment structure comprises an alignment trench formed in a bonding surface of the first substrate;forming a second alignment structure on a bonding surface of a second substrate, wherein the second alignment structure comprises a bonding pad with solder formed on the bonding pad;placing the bonding surfaces of the first and second substrates together with at least a portion of the solder of the second alignment structure in contact with at least a portion of the first alignment structure; andperforming a solder reflow process to cause the solder on the bonding pad to melt and flow into the alignment trench while pulling on the bonding pad to cause the second substrate to move into alignment with the first substrate in each of X, Y, and Z directions;wherein the second alignment structure further comprises one or more standoff pads formed on the bonding surface of the second substrate, wherein alignment in the Z direction comprises contacting the one ...

CHIP BONDING APPARATUS, CHIP BONDING METHOD AND A CHIP PACKAGE STRUCTURE

A chip bonding apparatus for bonding a chip and a redistribution structure with each other is provided. The chip bonding apparatus includes a pick and place module and an alignment module. The pick and place module is suitable for picking up and placing the chip. The alignment module is movably connected to the pick and place module. The alignment module includes at least one alignment protrusion, wherein the at least one alignment protrusion extends toward at least one alignment socket included in the redistribution structure. Furthermore, a chip bonding method and a chip package structure are provided. 1. A chip bonding apparatus for bonding a chip and a redistribution structure with each other , the chip bonding apparatus comprising:a pick and place module, suitable for picking up and placing the chip; andan alignment module, moveably connected to the pick and place module, and the alignment module comprising at least one alignment protrusion, wherein the at least one alignment protrusion extends towards at least one alignment socket included in the redistribution structure.2. The chip bonding apparatus according to claim 1 , wherein the alignment module further comprises a force sensor disposed between the pick and place module and the at least one alignment protrusion.3. The chip bonding apparatus according to claim 1 , wherein the alignment module further comprises at least one optical sensor surrounded the at least one alignment protrusion and the pick and place module.4. The chip bonding apparatus according to claim 1 , wherein on a direction of the pick and place module picks and places the chip claim 1 , the at least one alignment protrusion and the pick and place module do not overlap.5. The chip bonding apparatus according to claim 1 , wherein the at least one alignment protrusion comprises a plurality of alignment protrusions separated from each other.6. The chip bonding apparatus according to claim 1 , wherein the at least one alignment protrusion ...

SEMICONDUCTOR DEVICE ASSEMBLY WITH DIE SUPPORT STRUCTURES

A semiconductor device assembly is provided. The assembly includes a first semiconductor die and a second semiconductor die disposed over the first semiconductor die. The assembly further includes a plurality of die support structures between the first and second semiconductor dies and a plurality of interconnects between the first and second semiconductor dies. Each of the plurality of die support structures includes a stand-off pillar and a stand-off pad having a first bond material with a first solder joint thickness between them. Each of the plurality of interconnects includes a conductive pillar and a conductive pad having a second bond material with a second solder joint thickness between them. The first solder joint thickness is less than the second solder joint thickness. 1. A semiconductor package comprising a plurality of dies arranged in a stack ,wherein adjacent ones of the plurality of dies are separated by a plurality of interconnects and a plurality of die support structures,wherein each of the plurality of die support structures includes a stand-off pillar and a stand-off pad with a first distance between the stand-off pillar and the stand-off pad,wherein each of the plurality of interconnects includes a conductive pillar, a conductive pad, and a bond material with a solder joint thickness between the conductive pillar and the conductive pad, andwherein the first distance is less than the solder joint thickness.2. The semiconductor package of claim 1 , wherein the plurality of die support structures includes die support structures disposed about a periphery of the semiconductor package.3. The semiconductor package of claim 1 , wherein the plurality of die support structures includes die support structures disposed in a medial region of the semiconductor device assembly.4. The semiconductor package of claim 1 , wherein the plurality of dies includes more than two dies.5. The semiconductor package of claim 1 , wherein the plurality of dies includes at ...

OPTIMIZED SOLDER PADS FOR MICROELECTRONIC COMPONENTS

A multi-chip system includes a top chip stack element comprising a top chip having two major surfaces and top solder pads arrayed along a plane of one of the major surfaces; a bottom chip stack element comprising a bottom substrate having two major surfaces and bottom solder pads arrayed along a plane of one of the major surfaces; one or more solder reservoir pads connected to one or more of the top solder pads or of the bottom solder pads; and solder material; and wherein at least one of the top solder pads is connected to one of the bottom solder pads by one of the solder material. 1. A multi-chip system , comprisinga top chip stack element comprising a top chip having two major surfaces and top solder pads arrayed along a plane of one of the major surfaces;a bottom chip stack element comprising a bottom substrate having two major surfaces and bottom solder pads arrayed along a plane of one of the major surfaces;one or more solder reservoir pads connected to one or more of the top solder pads or of the bottom solder pads; andsolder material; andwherein at least one of the top solder pads is connected to one of the bottom solder pads by one of the solder material.2. The multi-chip system of claim 1 , wherein the at least one of the solder material contacts one of the solder reservoir pads.3. The multi-chip system of claim 1 , further comprising a conduit claim 1 , wherein the conduit connects one of the top solder pads or one of the bottom solder pads to one of the reservoir pads.4. The multi-chip system of claim 3 , wherein the solder pad and conduit comprise a metal selected from the group consisting of titanium claim 3 , chromium claim 3 , copper claim 3 , nickel claim 3 , iron claim 3 , aluminum claim 3 , silver and gold.5. The multi-chip system of claim 1 , wherein the solder material comprises a metal selected from the group consisting of tin claim 1 , silver claim 1 , gold claim 1 , lead claim 1 , bismuth claim 1 , and indium.6. The multi-chip system of ...

Semiconductor device and a method of manufacturing the same

To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

BONDING APPARATUS AND BONDING METHOD

A bonding apparatus includes: a bonding head configured to move a top camera facing toward a bonding surface and a collet disposed with an offset from the top camera , while integrally holding the top camera and the collet ; a bottom camera facing toward the collet so as to detect a position of a semiconductor chip held by the collet with respect to the collet ; a reference mark disposed within a view field of the bottom camera ; and a control unit . The control unit moves the bonding head based on a position of the mark recognized by the top camera , and then calculates a value of the offset based on a position of the collet with respect to the mark recognized by the bottom camera . With this, it is possible to provide a bonding apparatus capable of easily detecting an offset between a bonding tool and a position detection camera without providing a dedicated camera. 1. A bonding apparatus for bonding a chip onto a substrate , the apparatus comprising:a bonding head configured to move a first camera facing toward a bonding surface and a bonding tool disposed with an offset from the first camera, while integrally holding the first camera and the bonding tool;a second camera facing toward the bonding tool so as to detect a position of the chip held by the bonding tool with respect to the bonding tool;a reference mark disposed within a view field of the second camera; anda control unit configured to control movement of the bonding head, whereinthe control unit moves the bonding head based on a position of the reference mark recognized by the first camera, and then calculates a value of the offset based on a position of the bonding tool with respect to the reference mark recognized by the second camera.2. The bonding apparatus according to claim 1 , whereinbonding is performed by feeding back the value of the offset calculated by the control unit to a subsequent bonding process.3. The bonding apparatus according to claim 1 , whereinone of the first camera and the ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and one or more conductive layers and a solder resist layer that are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the one or more conductive layers, and has one or more apertures on each of the one or more conductive layers. The plurality of solder-including electrodes include two or more first electrodes having a same function other than a function of power supply. The one or more conductive layers include a continuous first conductive layer. The two or more first electrodes are connected to the continuous first conductive layer. The one or more apertures are confronted with the respective two or more first electrodes. 1. A semiconductor device , comprising:a semiconductor chip; anda packaging substrate on which the semiconductor chip is mounted,wherein the semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body,the packaging substrate includes a substrate body, one or more conductive layers, and a solder resist layer, the one or more conductive layers and the solder resist layer being provided on a front surface of the substrate body,the solder resist layer is provided as a continuous layer on the front surface of the substrate body and the one or more conductive layers, and has one or more apertures on each of the one or more conductive layers,the plurality of solder-including electrodes include two or more first electrodes having a same function other than a function of power supply,the one or more conductive layers include a continuous first conductive layer,the two or more first electrodes are connected to the continuous first conductive layer, andthe one or more ...

SOLDER IN CAVITY INTERCONNECTION STRUCTURES

The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate. 1. A microelectronic device , comprising:a first substrate having a plurality of bond pads proximate a first surface of the first substrate;a first dielectric layer disposed over the first substrate bond pads and the first substrate contact surface having a plurality of cavities extending therethrough to corresponding bond pads;a second substrate having a plurality of contact lands proximate a contact surface of the second substrate;a second dielectric layer on the second substrate surface adjacent the plurality of second substrate contact lands having a plurality of cavities extending therethrough to corresponding contact lands;a solder interconnection between the first substrate bond pads and the second substrate contact lands;an underfill material between the first dielectric layer and the second dielectric layer, wherein a portion of the underfill material extends into the plurality of cavities extending through the first dielectric layer and into the plurality of cavities extending through the second dielectric layer.2. The microelectronic device of claim 1 , wherein the plurality of cavities extending through the first dielectric layer each ...

Solderless interconnect for semiconductor device assembly

Semiconductor device assemblies with solderless interconnects, and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly includes a first conductive pillar extending from a semiconductor die and a second conductive pillar extending from a substrate. The first conductive pillar may be connected to the second conductive pillar via an intermediary conductive structure formed between the first and second conductive pillars using an electroless plating solution injected therebetween. The first and second conductive pillars and the intermediary conductive structure may include copper as a common primary component, exclusive of an intermetallic compound (IMC) of a soldering process. A first sidewall surface of the first conductive pillar may be misaligned with respect to a corresponding second sidewall surface of the second conductive pillar. Such interconnects formed without IMC may improve electrical and metallurgical characteristics of the interconnects for the semiconductor device assemblies.

Tools and Systems for Processing Semiconductor Devices, and Methods of Processing Semiconductor Devices

Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices are disclosed. In some embodiments, a method of using a tool for processing semiconductor devices includes a tool with a second material disposed over a first material, and a plurality of apertures disposed within the first material and the second material. The second material comprises a higher reflectivity than the first material. Each of the apertures is adapted to retain a package component over a support during an exposure to energy.

CHIP ATTACH FRAME

A chip attach frame is used to align pins of an integrated circuit chip with pads on a chip carrier. A frame block has a socket defining two alignment edges that form a reference corner. The chip is lowered into the socket, and the chip carrier is inclined while it supports the frame block and chip until the chip moves under force of gravity to the reference corner. Once located at the reference corner, the chip position is carefully adjusted by moving the frame block in the x- and y-directions until the pins are aligned with the pads. The frame block is spring biased against movement in the x- and y-directions, and the position of the frame block is adjusted using thumbscrews. A plunger mechanism can be used to secure the integrated circuit chip in forcible engagement with the chip carrier once the pins are aligned with the pads. 113.-. (canceled)14. A chip attach frame for attaching an integrated circuit chip to a chip carrier , comprising:a frame block having a generally rectangular socket with two adjacent alignment edges forming an orthogonal reference corner, the socket being larger than the integrated circuit chip and located such that pads of the chip carrier are accessible through the socket when said frame block is placed on the chip carrier, said frame block being movable in at least first and second non-parallel directions along the chip carrier;first means for adjusting a position of said frame block relative to the chip carrier along the first direction;second means for adjusting the position of said frame block relative to the chip carrier along the second direction; andplunger means for securing the integrated circuit chip in forcible engagement with the chip carrier.15. The chip attach frame of wherein said plunger means includes:a pressure plate which contacts an upper surface of the integrated circuit chip;one or more elastomeric strips interposed between said pressure plate and an upper surface of said frame block;a plunger block which drives ...

Alignment of three dimensional integrated circuit components

A method for aligning a chip onto a substrate is disclosed. The method includes, depositing a ferrofluid, onto a substrate that has one or more pads that electrically couple to a semiconductor layer. The method can include a chip with solder balls electrically coupled to the logic elements of the chip, which can be placed onto the deposited ferrofluid, where the chip is supported on the ferrofluid, in a substantially coplanar orientation to the substrate. The method can include determining if the chip is misaligned from a desired location on the substrate. The method can include adjusting the current location of the chip in response to determining that the solder balls of the chip are misaligned from the desired location on the pads of the substrate, until the chip is aligned in the desired location.

SEMICONDUCTOR PACKAGE ALIGNMENT FRAME FOR LOCAL REFLOW

Embodiments of the present disclosure describe package alignment frames for a local reflow process to attach a semiconductor package to an interposer. The frame may comprise a two frame system. The interposer may be on a mounting table or on a circuit board. The frame may include a body with a rectangular opening dimensioned to receive a semiconductor package to be coupled to the interposer. The frame may be to align a ball grid array of the semiconductor package with pads of the interposer. A second frame may be to receive the first frame and may be to align a ball grid array of the interposer with pads of the circuit board. A single frame may be used to couple a semiconductor package to an interposer and to couple the interposer to a circuit board. Other embodiments may be described and/or claimed. 1. A semiconductor package alignment frame for local reflow , comprising:a body that frames a rectangular opening dimensioned to receive a semiconductor package having a ball grid array;an interlock on a bottom of the body to couple with a complementary interlock on at least one of a circuit board or an interposer coupled to the circuit board to provide an interlocking mechanism to center the rectangular opening over the interposer and to align the ball grid array of the package with pads of the interposer; andelectrical routing features to couple with a plurality of interconnects of the interposer and electrical lines to provide power to and communications with the interposer via the electrical routing features.2. The semiconductor package alignment frame of claim 1 , wherein the electrical routing features traverse through the body from the bottom to a top of the body.3. The semiconductor package alignment frame of claim 1 , wherein the interlocking mechanism is to lock the package alignment frame to attach the package to the interposer via local reflow of the ball grid array.4. The semiconductor package alignment frame of claim 1 , further comprising:a lock feature ...

ARRAY SUBSTRATE AND METHOD OF MOUNTING INTEGRATED CIRCUIT USING THE SAME

An electronic device, including an array substrate, a pad portion disposed on the array substrate, and an integrated circuit disposed on the pad portion and comprising a bump portion. The pad portion includes a first sub-pad unit including a first pad having an inclined shape and a second sub-pad unit including a second pad having an inclined shape. The first pad and the second pad are symmetrically arranged with respect to an imaginary line that divides the pad portion. The pad portion is electrically connected with the bump portion. 1. An electronic device , comprising:an array substrate;a pad portion disposed on the array substrate; andan integrated circuit disposed on the pad portion and comprising a bump portion;wherein:the pad portion comprises a first sub-pad unit comprising a first pad having an inclined shape and a second sub-pad unit comprising a second pad having an inclined shape;the first pad and the second pad are symmetrically arranged with respect to an imaginary line that divides the pad portion; andthe pad portion is electrically connected with the bump portion.2. The electronic device of claim 1 , wherein at least one of the first pad and the second pad has a parallelogram shape.3. The electronic device of claim 1 , wherein:the bump portion comprises a first sub-bump unit comprising a first bump having an inclined shape and a second sub-bump unit comprising a second bump having an inclined shape; andthe first bump and the second bump are symmetrically arranged with respect to the imaginary line that divides the pad portion.4. The electronic device of claim 3 , wherein a shape of the first bump corresponds to a shape of the first pad claim 3 , and a shape of the second bump corresponds to a shape of the second pad.5. The electronic device of claim 3 , wherein the first pad is electrically connected with the first bump and the second pad is electrically connected with the second bump.6. The electronic device of claim 3 , wherein an area of the first ...

ELECTRONIC DEVICE, ELECTRONIC DEVICE FABRICATION METHOD, AND ELECTRONIC APPARATUS

An electronic device includes an electronic part including a first substrate having a group of first terminals over a first front surface and having a concavity in a back surface, a filler placed in the concavity, and a flat plate placed over the back surface with the filler therebetween, and further includes a second substrate disposed on the first front surface side of the first substrate and having a group of second terminals bonded to the group of first terminals over a second front surface opposite the first front surface. The filler and flat plate minimize deformation of the first substrate and variation in the distance between the group of first terminals and the group of second terminals caused by the deformation of the first substrate, which thereby reduces the occurrence of a failure in bonding together the group of first terminals and the group of second terminals. 1. An electronic device comprising:a first substrate having a group of first terminals over a first surface and having a concavity in a second surface opposite to the first surface;a filler placed in the concavity;a flat plate placed over the second surface with the filler therebetween; anda second substrate disposed on a first surface side of the first substrate and having a group of second terminals bonded to the group of first terminals over a third surface opposite the first surface.2. The electronic device according to claim 1 , wherein the first substrate is a wafer including semiconductor elements.3. The electronic device according to claim 1 , wherein the first substrate is a semiconductor element.4. The electronic device according to claim 1 , wherein at least one of the group of first terminals and the group of second terminals are protrusions.5. The electronic device according to claim 1 , wherein the filler has a heat conduction property higher than or equal to a heat conduction property of the first substrate.6. The electronic device according to claim 1 , wherein the flat plate ...

Multiple chip carrier for bridge assembly

A multiple chip carrier assembly including a carrier having a first surface and a second surface is attached to a plurality of chips is described. The plurality of chips include a first chip and a second chip. Each of the chips has first surface with a first set of solder balls for connecting to a package and a second set of solder balls for connecting to a high signal density bridge element. A second surface of each chip is bonded to the first surface of the carrier. A package has a first surface which is connected to the first sets of solder balls of the first and second chips. A high signal density bridge element having high signal density wiring on one or more layers is connected to the second sets of solder balls of the first and second chips. The bridge element is disposed between the first surface of the package and the first surfaces of the first and second chips.

PILLARS AS STOPS FOR PRECISE CHIP-TO-CHIP SEPARATION

A stacked device including a first substrate that includes a quantum information processing device, a second substrate bonded to the first substrate, and multiple bump bonds and at least one pillar between the first substrate and the second substrate. Each bump bond of the multiple bump bonds provides an electrical connection between the first substrate and the second substrate. At least one pillar defines a separation distance between a first surface of the first substrate and a first surface of the second substrate. A cross-sectional area of each pillar is greater than a cross-sectional area of each bump bond of the multiple bump bonds, where the cross-sectional area of each pillar and of each bump bond is defined along a plane parallel to the first surface of the first substrate or to the first surface of the second substrate. 1. A device comprising:a first substrate comprising a quantum information processing device;a second substrate bonded to the first substrate;a plurality of bump bonds between the first substrate and the second substrate, each bump bond of the plurality of bump bonds providing an electrical connection between the first substrate and the second substrate; andat least one pillar between the first substrate and the second substrate, the at least one pillar defining a separation distance between a first surface of the first substrate and a first surface of the second substrate, wherein a cross-sectional area of each pillar is greater than a cross-sectional area of each bump bond of the plurality of bump bonds, the cross-sectional area of each pillar and of each bump bond being defined along a plane parallel to the first surface of the first substrate or to the first surface of the second substrate.2. The device of claim 1 , wherein the plurality of bump bonds are superconducting bump bonds.3. The device of claim 2 , wherein the plurality of bump bonds are indium bump bonds.4. The device of claim 1 , wherein a first bump bond of the plurality of ...

Chip attach frame

A chip attach frame is used to align pins of an integrated circuit chip with pads on a chip carrier. A frame block has a socket defining two alignment edges that form a reference corner. The chip is lowered into the socket, and the chip carrier is inclined while it supports the frame block and chip until the chip moves under force of gravity to the reference corner. Once located at the reference corner, the chip position is carefully adjusted by moving the frame block in the x- and y-directions until the pins are aligned with the pads. The frame block is spring biased against movement in the x- and y-directions, and the position of the frame block is adjusted using thumbscrews. A plunger mechanism can be used to secure the integrated circuit chip in forcible engagement with the chip carrier once the pins are aligned with the pads.

ULTRASONIC-ASSISTED SOLDER TRANSFER

Apparatus and methods are disclosed for transferring solder to a substrate. A substrate belt moves one or more substrates in a belt direction. A decal has one or more through holes in a hole pattern that hold solder. Each of the solder holes can align with respective locations on one of the substrates. An ultrasonic head produces an ultrasonic vibration in the solder in a longitudinal direction perpendicular to the belt direction. The ultrasonic head and substrate can be moved together in the longitudinal direction to maintain the ultrasonic head in contact with the solder while the ultrasonic head applies the ultrasonic vibration. Various methods are disclosed including methods of transferring the solder with or without external heating. 1. An apparatus for transferring solder to a substrate comprising:a substrate belt capable of moving one or more substrates in a belt direction;a decal having one or more through holes in a hole pattern, each of the holes having a solder volume capable of holding a solder; andan ultrasonic head capable of producing an ultrasonic vibration in a longitudinal direction, the longitudinal direction being perpendicular to the belt direction, where the ultrasonic head and substrate can be moved together in the longitudinal direction to maintain the ultrasonic head in contact with the solder while applying the ultrasonic vibration.2. An apparatus claim 1 , as in claim 1 , where the ultrasonic head can move in the longitudinal direction toward the substrate belt and cause the decal to be in contact with one or more of the substrates and move away from the substrate belt and cause the decal not to be in contact with the substrates.3. An apparatus claim 1 , as in claim 1 , further comprising a pressure plate below the substrate belt.4. An apparatus claim 3 , as in claim 3 , where the pressure plate can move in the longitudinal direction toward the substrate belt to put the ultrasonic head and the substrate in contact with the decal and move ...

ALIGNMENT METHOD, METHOD FOR CONNECTING ELECTRONIC COMPONENT, METHOD FOR MANUFACTURING CONNECTION BODY, CONNECTION BODY AND ANISOTROPIC CONDUCTIVE FILM

An alignment mark at a position that overlaps an area in which an anisotropic conductive film is pasted, and to accurately perform alignment using an image captured by a camera. An alignment method in which an electronic component is mounted on the obverse surface of a transparent substrate with a conductive adhesive agent interposed therebetween, a substrate-side alignment mark and a component-side alignment mark are adjusted from the captured image, and the position at which the electronic component is mounted on the transparent substrate is aligned, wherein in the conductive adhesive agent, conductive particles are in a regular arrangement as viewed from a planar perspective, and in the captured image, the outside edges of the alignment marks exposed between the conductive particles are intermittently visible as line segments (S) along the imaginary line segments of the outside edges of the alignment mark. 1. An alignment method comprising:mounting an electronic component having a component-side alignment mark onto a surface of a transparent substrate having a substrate-side alignment mark via an adhesive agent containing conductive particles interposed therebetween;imaging the substrate-side alignment mark and the electronic component-side alignment mark from the back surface side of the transparent substrate; andadjusting a position of the substrate-side alignment mark and the component-side alignment mark by using a captured image obtained by imaging to adjust a mounting position of the electronic component with respect to the transparent substrate;wherein the adhesive agent has the conductive particles arranged regularly as viewed from a planar perspective; andwherein in the captured image, outside edges of the substrate-side alignment mark or the component-side alignment mark exposed between the conductive particles are intermittently visible as line segments along imaginary line segments of the outside edges of the substrate-side alignment mark or the ...

SEMICONDUCTOR MANUFACTURING APPARATUS

A semiconductor manufacturing method of mounting a semiconductor chip or a stacked body of semiconductor chips on a support substrate placed on a stage, determines whether a predetermined condition is satisfied during a mounting processing of the semiconductor chip or the stacked body, evacuates, together with the support substrate, the semiconductor chip or the stacked body that has mounted on the support substrate before the determination when it is determined that the predetermined condition is satisfied, determines whether to resume the mounting processing of the semiconductor chip or the stacked body after the evacuation; and returns the evacuated semiconductor chip or the evacuated stacked body to a position before the evacuation and continuing the mounting processing when it is determined that the mounting processing is resumed. 1. A semiconductor manufacturing method of mounting a semiconductor chip or a stacked body of semiconductor chips on a support substrate placed on a stage , the method comprising:determining whether a mounting processing is stopped during the mounting processing of the semiconductor chip or the stacked body;evacuating, together with the support substrate, the semiconductor chip or the stacked body that has mounted on the support substrate before the determination when it is determined that the mounting processing is stopped;determining whether to resume the mounting processing of the semiconductor chip or the stacked body after the evacuation; andreturning the evacuated semiconductor chip or the evacuated stacked body to a position before the evacuation and continuing the mounting processing when it is determined that the mounting processing is resumed.2. The semiconductor manufacturing method according to claim 1 ,wherein the determining whether the mounting processing is stopped includes determining whether an apparatus performing the mounting processing stops, andwherein the evacuating the semiconductor chip or the stacked body ...

Method of Manufacturing Semiconductor Device and Semiconductor Device Manufacturing Apparatus

A method of manufacturing a semiconductor device according to the present invention comprises: a bump forming step of forming a bump electrode 100 on a semiconductor chip 1, the bump electrode 100 protruding in a substantially conical shape; a pad forming step of forming a pad electrode 200 on a substrate 10, the pad electrode 200 having a recess 210 with inner lateral surfaces thereof defining a substantially pyramidal shape or a prism shape; a pressing step of pressing the bump electrode 100 and the pad electrode 200 in a direction which brings them closer to each other, with the bump electrode 100 being inserted in the recess 210 so that the central axis of the bump electrode 100 and the central axis of the recess 210 coincide with each other; and an ultrasonic joining step of joining the bump electrode 100 and the pad electrode 200 by vibrating at least one of the bump electrode 100 and the pad electrode 200 using ultrasonic waves.

Metal-free frame design for silicon bridges for semiconductor packages

Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semi-conductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

Display devices and methods for manufacturing the same

A method for manufacturing a display device is provided. The method includes providing an array module having at least one first alignment mark. The method also includes providing a light-emitting module having at least one second alignment mark. The method further includes aligning the light-emitting module and the array module by the at least one first alignment mark and the at least one second alignment mark. In addition, the method includes bonding the light-emitting module onto the array module.

BONDING TOOLS FOR BONDING MACHINES, BONDING MACHINES FOR BONDING SEMICONDUCTOR ELEMENTS, AND RELATED METHODS

A bonding tool for bonding a semiconductor element to a substrate on a bonding machine is provided. The bonding tool includes a body portion including a contact region for contacting the semiconductor element during a bonding process on the bonding machine. The bonding tool also includes a standoff extending from the body portion, and configured to contact the substrate during at least a portion of the bonding process. 1. A bonding tool for bonding a semiconductor element to a substrate on a bonding machine , the bonding tool comprising:a body portion including a contact region for contacting the semiconductor element during a bonding process on the bonding machine; anda standoff extending from the body portion, and configured to contact the substrate during at least a portion of the bonding process.2. The bonding tool of wherein the bonding tool includes a plurality of the standoffs extending from the body portion and configured to contact the substrate during at least the portion of the bonding process.3. The bonding tool of wherein the standoff extends from the contact region of the body portion.4. The bonding tool of wherein the standoff is coupled to the body portion.5. The bonding tool of wherein the standoff is formed from a unitary piece of material including the body portion.6. The bonding tool of wherein the bonding process is a thermocompression bonding process.7. The bonding tool of wherein the standoff is configured to contact a solder mask portion of the substrate during at least the portion of the bonding process.8. The bonding tool of wherein the standoff is a post.9. The bonding tool of wherein the standoff is a wall.10. The bonding tool of wherein the semiconductor element is an interposer.11. The bonding tool of wherein the bonding tool is a die attach tool claim 1 , and wherein the bonding process is a die attach process.12. The bonding tool of wherein the standoff is configured to control a thickness of an adhesive between the semiconductor ...

AUXILIARY JOINING AGENT AND METHOD FOR PRODUCING THE SAME

The purpose is, in mounting a semiconductor device onto a substrate, to make it easy to identify the remaining amount of an auxiliary joining agent, to stabilize the dispensing amount of the auxiliary joining agent, and to prevent a shortage of the auxiliary joining agent. Also for the purpose of efficient maintenance of a mounting machine, provided is an auxiliary joining agent adapted to aid joining of metals and prepared by dissolving a colorant in a solvent having a reducing property of removing an oxide film on a metal surface. The auxiliary joining agent is produced by a method including a step of mixing a solvent having a reducing property of removing an oxide film on a metal surface, and a colorant having a property of dissolving in the solvent. 1. A mounting method of a semiconductor device , the method comprising the steps of:preparing a colored auxiliary joining agent having a reducing property of removing an oxide film on a metal surface;allowing a substrate having a first electrode to be held on a substrate stage, with the first electrode facing upward;providing the auxiliary joining agent onto the substrate held on the substrate stage, so as to cover the first electrode; and,mounting the semiconductor device onto the substrate by pressing a second electrode of a supplied semiconductor device against the first electrode of the substrate which is held on the substrate stage and has the auxiliary joining agent dispensed on the first electrode, to join the first electrode and the second electrode to each other,the auxiliary joining agent comprises a solvent having a reducing property of removing an oxide film on the metal surface, and a colorant having a property of dissolving in the solvent;the solvent includes a multi-functional alcohol having a molecular weight of 50 to 200; andthe colorant has a property of volatilizing along with the solvent.2. The mounting method of a semiconductor device according to claim 1 , whereinthe solvent has a boiling point ...

Semiconductor Device Package and Method of the Same

The invention proposes a semiconductor device package structure, comprising a substrate, an adhesive layer and a die. The substrate has electrical through-holes to inter-connect a first and second wiring circuit on a top surface and a bottom surface of the substrate respectively, wherein a contact conductive bump is formed on the first wiring circuit. The under-fill adhesive layer is formed on the top surface and the first wiring circuit of the substrate except the area of the die. The die has a bump structure on the bonding pads of the die, wherein the bump structure of the die is electrically connected to the contact conductive bump of the first wiring circuit of the substrate. 1. A method for forming a semiconductor device package , comprising:preparing a first substrate and a second substrate, wherein said first substrate includes a wiring circuit and an aligning mark disposed on a top surface thereof and a contact conductive bump is formed on said wiring circuit;opening a die opening window through said second substrate by using a laser or punching method;preparing an adhesive material;attaching said second substrate to said first substrate by said adhesive material such that said adhesive material is disposed between said top surface of said first substrate and a bottom surface of said second substrate to directly attach said second substrate onto said first substrate;aligning a die with a bump structure on the bonding pads of said die by using said aligning mark and attaching said die onto said contact conductive bump with force by said adhesive material such that said bump structure of said die is electrically connected to said contact conductive bump of said wiring circuit of said first substrate;forming a dielectric layer on a top surface of said second substrate and said die and pushing said dielectric layer into a gap between a side wall of said die and a side wall of said die opening window;opening a plurality of via openings in said dielectric layer; ...

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device including a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.

Drive chip and display apparatus

This drive chip has a configuration that is provided with: a base main body; two terminal groups that are respectively disposed along the base main body sides in the longitudinal direction of the base main body, said sides facing each other; a narrow-pitch section in one terminal group wherein terminals are disposed in a zigzag manner in two or more rows, said narrow-pitch section having a narrow terminal pitch in the longitudinal direction; a rough pitch section in the one terminal group, said rough pitch section having a terminal pitch in the longitudinal direction wider than that of the narrow pitch section; and a dummy bump that is disposed between the two terminal groups, said dummy bump being disposed parallel to the rough pitch section.

Magnetic alignment for flip chip microelectronic devices

Incorporating at least one magnetic alignment structure on a microelectronic device and incorporating at least one alignment coil within a microelectronic substrate, wherein the alignment coil may be powered to form a magnetic field to attract the magnetic alignment structure, thereby aligning the microelectronic device to the microelectronic substrate. After alignment, the microelectronic device may be electrically attached to the substrate. Embodiments may include additionally incorporating an alignment detection coil within the microelectronic substrate, wherein the alignment detection coil may be powered to form a magnetic field to detect variations in the magnetic field generated by the alignment coil in order verify the alignment of the microelectronic device to the microelectronic substrate.

INJECTION MOLDED SOLDER BUMPING

Methods for depositing material on a chip include forming a mold layer. The mold layer includes one or more openings over respective contact areas, each of the one or more openings having an upper volume and a lower volume. The upper volume has a smaller diameter than a diameter of the lower volume. Each contact area is within the respective lower volume. A material is injected into the one or more openings under pressure. 1. A method for depositing material on a chip , comprising:forming a mold layer, the mold layer comprising one or more openings over respective contact areas, each of the one or more openings including an upper volume and a lower volume, the upper volume having a smaller diameter than a diameter of the lower volume, wherein each contact area is within the respective lower volume; andinjecting a material into the one or more openings under pressure.2. The method of claim 1 , wherein forming the mold comprises depositing only a single resist layer on the substrate.3. The method of claim 2 , wherein forming the mold layer further comprises exposing the resist layer over the respective contact areas claim 2 , defocusing a light beam during exposure.4. The method of claim 1 , wherein forming the mold comprises depositing a first resist layer over a substrate and a second resist layer over the first resist layer.5. The method of claim 4 , wherein forming the mold further comprises exposing the second resist layer in a volume above each respective contact area.6. The method of claim 5 , wherein forming the mold further comprises etching away the exposed volume of the second resist layer and underlying material of the first resist layer to form the one or more openings.7. The method of claim 5 , wherein forming the mold further comprises exposing the first resist layer before depositing the second resist layer over the first resist layer.8. The method of claim 1 , wherein the diameter of the upper volume is substantially similar to a diameter of the ...

DISPLAY DEVICE

A display device includes a display substrate including a display area and a pad area, which is disposed on the periphery of the display area; and a display panel including at least one wire pad, which is disposed in the pad area of the display substrate, where the wire pad includes a main pad portion, which extends in a first direction, a first protruding pad portion, which protrudes from a first side, in a second direction intersecting the first direction, of the main pad portion, and a second protruding pad portion, which protrudes from a second side, in the second direction, of the main pad portion, and the first protruding pad portion is disposed closer than the second protruding pad portion to the display area. 1. A display device comprising:a display substrate including a display area and a pad area, which is disposed on a periphery of the display area; and a main pad portion, which extends in a first direction;', 'a first protruding pad portion, which protrudes from a first side, in a second direction intersecting the first direction, of the main pad portion; and', 'a second protruding pad portion, which protrudes from a second side, in the second direction, of the main pad portion,, 'a display panel including a wire pad, which is disposed in the pad area of the display substrate, the wire pad includingwherein the first protruding pad portion is disposed closer than the second protruding pad portion to the display area.2. The display device of claim 1 , whereinthe first direction is a direction from the display area toward an end of the pad area where the wire pad is disposed, andthe second side, in the second direction, of the main pad portion is opposite to the first side, in the second direction, of the main pad portion.3. The display device of claim 2 , wherein the wire pad further includes a third protruding pad portion claim 2 , which protrudes from the first side claim 2 , in the second direction claim 2 , of the main pad portion claim 2 , and a ...

Semiconductor device and method of manufacturing the same

A method of manufacturing a semiconductor device by connecting a semiconductor chip to a lead frame using a jig, the semiconductor chip including a main electrode provided at a surface of the semiconductor chip, the lead frame including a connection projecting portion and a positioning portion, the positioning portion including at least one of a convex shape and a concave shape provided around the connection projecting portion, the method may include: engaging the jig to the positioning portion in a state where a clearance is provided between the connection projecting portion and the jig; engaging the jig to the semiconductor chip; and connecting the connection projecting portion to the main electrode of the semiconductor chip via solder in a state where the jig is engaged to the positioning portion and the semiconductor chip.

Semiconductor device and manufacturing method for the same

A semiconductor substrate provided with an integrated circuit is polished by CMP or the like, and the semiconductor substrate is made into a thin film by forming an embrittlement layer in the semiconductor substrate and separating a part of the semiconductor substrate; thus, semiconductor chips such as IC chips and LSI chips which are thinner than ever are obtained. Moreover, such thinned LSI chips are stacked and electrically connected through wirings penetrating through the semiconductor substrate; thus, a three dimensional semiconductor integrated circuit with improved packing density is obtained.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a semiconductor substrate; a first pad and a second pad on a top surface of the semiconductor substrate; a circuit board including a polymeric pad and an active pad corresponding to the first pad and the second pad on the top surface of the semiconductor substrate respectively; a first bump disposed between the polymeric pad and the first pad; and a second bump disposed between the active pad and the second pad; wherein a first thickness of the polymeric pad is greater than a second thickness of the active pad. 1. A semiconductor structure , comprising:a semiconductor substrate;a first pad and a second pad on a top surface of the semiconductor substrate;a circuit board including a polymeric pad and an active pad corresponding to the first pad and the second pad on the top surface of the semiconductor substrate respectively:a first bump disposed between the polymeric pad and the first pad; anda second bump disposed between the active pad and the second pad, wherein a first thickness of the polymeric pad is greater than a second thickness of the active pad.2. The semiconductor structure of claim 1 , wherein the circuit board comprises a first recess and a second recess claim 1 , and the polymeric pad and the active pad are disposed within the first recess and the second recess respectively.3. The semiconductor structure of claim 2 , wherein a width of the polymeric pad is substantially less than a width of the first recess.4. The semiconductor structure of claim 2 , wherein a width of the active pad is substantially less than a width of the second recess.5. The semiconductor structure of claim 1 , wherein the polymeric pad is protruded from a top surface of the circuit board.6. The semiconductor structure of claim 1 , wherein the polymeric pad is electrically insulative.7. The semiconductor structure of claim 1 , wherein the first bump and the second bump have a first height and a second height respectively claim 1 , and the second ...

TOOLING FOR COUPLING MULTIPLE ELECTRONIC CHIPS

A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface. 1. A method comprising:bringing a material located on a body into contact with multiple chips;hardening the material to increasingly constrain at least a portion of each of the multiple chips therewithin such that the hardened material and the multiple chips behave as a rigid body;applying a force to the body to uniformly transfer a force from the hardened material on the body to the multiple chips to bring, under pressure, the bonding surface of each individual chip into contact with a bonding surface of an element, without causing damage to the multiple chips or the bonding surface of the element; andremoving all of the hardened material from contact with the multiple chips.2. The method of claim 1 , further comprising moving the multiple chips constrained by the hardened material from a first location to a second location where the element claim 1 , to which the multiple chips are to be bonded claim 1 , is located.3. The method of claim 1 , further comprising bonding each of the multiple chips to the element.4. The method of claim 1 , further comprising removing the body using at least one of a chemical process claim 1 , a ...

MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE

A method for forming a semiconductor structure includes: providing a semiconductor substrate having a first pad and a second pad on a top surface of the semiconductor substrate; providing a circuit board having an active pad and a non-metallic surface; providing a first solder ball and a second solder ball on the active pad and the non-metallic surface respectively; attaching the first pad and the second pad on the first solder ball and the second solder ball respectively; and reflowing the first solder ball and the second solder ball to form a first bump wetted on the active pad and a second bump not wetted on the non-metallic surface. 1. A method for forming a semiconductor structure , comprising:providing a semiconductor substrate, having a first pad and a second pad on a top surface of the semiconductor substrate;providing a circuit board having an active pad and a non-metallic surface;providing a first solder ball and a second solder ball on the active pad and the non-metallic surface respectively;attaching the first pad and the second pad on the first solder ball and the second solder ball respectively; andreflowing the first solder ball and the second solder ball to form a first bump wetted on the active pad and a second bump not wetted on the non-metallic surface.2. The method of claim 1 , wherein reflowing the first solder ball and the second solder ball to form the first bump wetted on the active pad and the second bump not wetted on the non-metallic surface comprises:reflowing the first solder ball and the second solder ball to cause the second bump to elongate the first bump.3. The method of claim 1 , further comprising:providing a recessed portion on a surface of the circuit board for accommodating the active pad.4. The method of claim 1 , wherein a first contact angle is formed between a first contact surface of the first bump on the active pad and a surface of the active pad claim 1 , a second contact angle is formed between a second contact surface ...

OPTICAL-ELECTRICAL INTERPOSERS

The disclosed embodiments provide a method for integrating an optical interposer with one or more electronic dies and an optical-electronic (OE) printed circuit board (PCB). This method involves first applying surface-connection elements to a surface of the optical interposer, and then bonding the one or more electrical dies to the optical interposer using the surface-connection elements. Next, the method integrates the OE-PCB onto the surface of the optical interposer, wherein the integration causes the surface-connection elements to provide electrical connections between the optical interposer and the OE-PCB. 1. A method for integrating an optical interposer with one or more electronic dies and an optical-electronic (OE) printed circuit board (PCB) , comprising:applying surface-connection elements to a surface of the optical interposer;bonding the one or more electrical dies to the optical interposer using the surface-connection elements; andintegrating the OE-PCB onto the surface of the optical interposer, wherein the integration causes the surface-connection elements to provide electrical connections between the optical interposer and the OE-PCB.2. The method of claim 1 , wherein the surface-connection elements can include one or more of the following:C4 solder bumps;microbumps;copper pillars;bond pads; andmetal diffusion bonding elements.3. The method of claim 1 , wherein bonding the one or more electrical dies to the optical interposer involves using one or more of the following bonding techniques:flip-chip bonding;hybrid oxide bonding; andhybrid polymer bonding.4. The method of claim 1 ,wherein the optical interposer includes one or more recesses to provide room for the one or more electronic dies; andwherein the one or more electronic dies are bonded within the one or more recesses.5. The method of claim 1 , wherein the optical interposer includes one or more alignment grooves to facilitate optical waveguide alignment and physical interconnection claim 1 , ...

ALIGNED CORE BALLS FOR INTERCONNECT JOINT STABILITY

Embodiments herein relate to systems, apparatuses, or processes directed to an interconnect joint that includes multiple core balls within a solder compound where the multiple core balls are substantially linearly aligned. The multiple core balls, which may include copper or be a polymer, couple with each other within the solder and form a substantially linear alignment during reflow. In embodiments, four or more core balls may be used to achieve a high aspect ratio interconnect joint with a tight pitch. 1. An apparatus comprising:a volume of solder having a first end and a second end opposite the first end;a plurality of core balls disposed within the volume of solder, wherein the plurality of core balls are in a substantially linear alignment from a first location in the volume of solder proximate to the first end to a second location in the volume of solder proximate to the second end; andwherein the plurality of core balls are to increase the compressive or tensile strength of the apparatus.2. The apparatus of claim 1 , wherein the first end is to attach to a first substrate and the second end is to attach to a second substrate.3. The apparatus of claim 1 , wherein the core ball includes copper or a polymer.4. The apparatus of claim 3 , wherein the core ball includes a copper claim 3 , a nickel claim 3 , or a solder plating.5. A package comprising:a first substrate with a first side and a second side opposite the first side;a second substrate with a first side and a second side opposite the first side; andan interconnect joint to couple the second side of the first substrate with the first side of the second substrate, wherein the interconnect joint includes a plurality of core balls aligned substantially linearly to provide stability to the interconnect joint.6. The package of claim 5 , wherein the plurality of core balls are within a solder compound.7. The package of claim 5 , further including one or more second interconnect joint to couple the second side of ...

SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR PACKAGE STRUCTURE HAVING THE SAME

A semiconductor package structure includes a substrate, a semiconductor chip, and a solder material. The substrate includes an insulating layer, a conductive circuit layer, and a conductive bump. The conductive circuit layer is recessed from a top surface of the insulating layer. The conductive circuit layer includes a pad, and a side surface of the pad extends along a side surface of the insulating layer. The conductive bump is disposed on the pad. A side surface of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space. A solder material electrically connects the conductive bump and the semiconductor chip. A portion of the solder material is disposed in the accommodating space. 1. A semiconductor package structure , comprising: an insulating layer having a top surface and a side surface;', 'a conductive circuit layer recessed from the top surface of the insulating layer, wherein the conductive circuit layer comprises at least one pad, and a side surface of the pad extends along the side surface of the insulating layer; and', 'a conductive bump disposed on the pad, wherein a side surface of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space;, 'a substrate comprisinga semiconductor chip; anda solder material electrically connecting the conductive bump and the semiconductor chip, wherein a portion of the solder material is disposed in the accommodating space.2. The semiconductor package structure of claim 1 , wherein the pad is fully exposed by the insulating layer.3. The semiconductor package structure of claim 1 , wherein the conductive bump comprises a main portion and a protrusion portion.4. The semiconductor package structure of claim 3 , wherein the protrusion portion is disposed on the pad and the main portion is disposed over the protrusion portion.5. The semiconductor package structure of claim 3 , further ...

ARRAY SUBSTRATE AND METHOD OF MOUNTING INTEGRATED CIRCUIT USING THE SAME

An electronic device, including an array substrate, a pad portion disposed on the array substrate, and an integrated circuit disposed on the pad portion and comprising a bump portion. The pad portion includes a first sub-pad unit including a first pad having an inclined shape and a second sub-pad unit including a second pad having an inclined shape. The first pad and the second pad are symmetrically arranged with respect to an imaginary line that divides the pad portion. The pad portion is electrically connected with the bump portion.

ANGLED DIE SEMICONDUCTOR DEVICE

A semiconductor device is disclosed mounted at an angle on a signal carrier medium such as a printed circuit board. The semiconductor device includes a stack of semiconductor die stacked in a stepped offset configuration. The die stack may then be encapsulated in a block of molding compound. The molding compound may then be singulated with slanted cuts along two opposed edges. The slanted edge may then be drilled to expose the electrical contacts on each of the semiconductor die. The slanted edge may then be positioned against a printed circuit board having solder or other conductive bumps so that the conductive bumps engage the semiconductor die electrical contacts in the drilled holes. The device may then be heated to reflow and connect the electrical contacts to the conductive bumps. 1. A semiconductor device , comprising:a plurality of semiconductor die mounted together in a stepped, offset stack, the plurality of semiconductor die each including a plurality of electrical contacts; anda mold compound encasing the plurality of semiconductor die, the mold compound having a first major surface, and a leading edge, the leading edge formed at a non-perpendicular angle to the major surface and the plurality of electrical contacts exposed at the leading edge.2. The semiconductor device of claim 1 , wherein the electrical contacts comprise die bond pads defined in or on surfaces of the plurality of semiconductor die.3. The semiconductor device of claim 1 , wherein the electrical contacts comprise conductive bumps formed on die bond pads defined in or on surfaces of the plurality of semiconductor die.4. The semiconductor device of claim 1 , wherein the mold compound includes holes formed in the mold compound claim 1 , the holes exposing the electrical contacts.5. The semiconductor device of claim 1 , wherein the semiconductor device is configured to be mounted to a signal carrier medium at an angle greater than 0° and less than 90° claim 1 , said angle defined by the ...

ADHESIVE COMPOSITION, SEMICONDUCTOR DEVICE CONTAINING CURED PRODUCT THEREOF, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING SAME

The purpose of the present invention is to provide an adhesive composition which allows an alignment mark to be recognized, ensures sufficient solder wettability of a joining section, and is excellent in suppression of void generation. The adhesive composition includes: a high-molecular compound (A); an epoxy compound (B) having a weight average molecular weight of 100 or more and 3,000 or less; and a flux (C); and inorganic particles (D) which have on the surfaces thereof an alkoxysilane having a phenyl group and which have an average, particle diameter of 30 to 200 nm, the flux (C) containing an acid-modified rosin. 1. An adhesive composition comprising: a high-molecular compound (A); an epoxy compound (B) having a weight average molecular weight of 100 or more and 3 ,000 or less; and a flux (C); and inorganic particles (D) which have on the surfaces thereof an alkoxysilane having a phenyl group and which have an average particle diameter of 30 to 200 nm , the flux (C) containing an acid-modified rosin.2. The adhesive composition according to claim 1 , wherein the high-molecular compound (A) is a phenoxy resin having a weight average molecular weight of 10 claim 1 ,000 or more and 100 claim 1 ,000 or less.3. The adhesive composition according to claim 1 , wherein the content of the acid-modified rosin in the flux (C) is 50 wt % or more and 100 wt % or less.4. The adhesive composition according to claim 1 , wherein the content of the acid-modified rosin in the flux (C) is 5 to 35 parts by mass based on 100 parts by mass of the inorganic particles (D) which have on the surfaces thereof an alkoxysilane having a phenyl group and which have an average particle diameter of 30 to 200 nm.5. The adhesive composition according to claim 1 , further comprising a curing accelerator (E).6. The adhesive composition according to claim 1 , wherein the content of the inorganic particles (D) which have on the surfaces thereof an alkoxysilane having a phenyl group and which have an ...

High Speed Handling of Ultra-Small Chips by Selective Laser Bonding and Debonding

Techniques for high speed handling of ultra-small chips (e.g., micro-chips) by selective laser bonding and/or debonding are provided. In one aspect, a method includes: providing a first wafer including chips bonded to a surface thereof; contacting the first wafer with a second wafer, the second wafer including a substrate bonded to a surface thereof, wherein the contacting aligns individual chips with bonding sites on the substrate; and debonding the individual chips from the first wafer using a debonding laser having a small spot size of about 0.5 μm to about 100 μm, and ranges therebetween. A system is also provided that has digital cameras, a motorized XYZ-axis stage, and a computer control system configured to i) control a spot size of the at least one laser source and ii) adjust a positioning of the sample to align individual chips with a target area of the laser. 1. A method , comprising:providing a first wafer comprising chips bonded to a surface thereof;contacting the first wafer with a second wafer, the second wafer comprising a substrate bonded to a surface thereof, wherein the contacting aligns individual chips with bonding sites on the substrate; anddebonding the individual chips from the first wafer using a debonding laser having a small spot size of about 0.5 μm to about 100 μm, and ranges therebetween.2. The method of claim 1 , wherein the first wafer is oriented with the chips facing downward.3. The method of claim 1 , further comprising:positioning a third wafer over the first wafer, the third wafer comprising a pattern having openings therein over the individual chips which are targeted for debonding; andirradiating the first wafer with the debonding laser through the pattern creating the small spot size to selectively debond the individual chips from the first wafer.4. The method of claim 1 , wherein the first wafer and the second wafer are present on a motorized XYZ-axis stage claim 1 , the method further comprising the step of:adjusting a ...

Tools and Systems for Processing Semiconductor Devices, and Methods of Processing Semiconductor Devices

Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices are disclosed. In some embodiments, a method of using a tool for processing semiconductor devices includes a tool with a second material disposed over a first material, and a plurality of apertures disposed within the first material and the second material. The second material comprises a higher reflectivity than the first material. Each of the apertures is adapted to retain a package component over a support during an exposure to energy. 1. A tool for processing semiconductor devices , comprising:a second material disposed over a first material; anda plurality of apertures disposed within the first material and the second material, wherein the second material comprises a higher reflectivity than the first material, and wherein each of the plurality of apertures is adapted to retain a package component over a support, the package component comprising a substrate with contact pads formed thereon.2. The tool according to claim 1 , wherein the second material comprises a metal.3. The tool according to claim 2 , wherein the metal comprises a material selected from the group consisting essentially of Au claim 2 , Ag claim 2 , Cu claim 2 , Cr claim 2 , Zn claim 2 , Sn claim 2 , and combinations thereof.4. The tool according to claim 1 , wherein the second material comprises a thin film material having a thickness of about 1 μm or less.5. The tool according to claim 4 , wherein the thin film material comprises a material selected from the group consisting essentially of TiO-doped epoxy claim 4 , TiO-doped polymer claim 4 , and combinations thereof.6. The tool according to claim 1 , wherein the first material comprises a material selected from the group consisting essentially of a metal claim 1 , a metal alloy claim 1 , a ceramic material claim 1 , and combinations thereof.7. The tool according to claim 1 , wherein the first material comprises a first reflectivity claim 1 ...

SEMICONDUCTOR DEVICES WITH UNDERFILL CONTROL FEATURES, AND ASSOCIATED SYSTEMS AND METHODS

Semiconductor devices with underfill control features, and associated systems and methods. A representative system includes a substrate having a substrate surface and a cavity in the substrate surface, and a semiconductor device having a device surface facing toward the substrate surface. The semiconductor device further includes at least one circuit element electrically coupled to a conductive structure. The conductive structure is electrically connected to the substrate, and the semiconductor device further has a non-conductive material positioned adjacent the conductive structure and aligned with the cavity of the substrate. An underfill material is positioned between the substrate and the semiconductor device. In other embodiments, in addition to or in lieu of the con-conductive material, a first conductive structure is connected within the cavity, and a second conductive structure connected outside the cavity. The first conductive structure extends away from the device surface a greater distance than does the second conductive structure. 1. A method for manufacturing a semiconductor device assembly , comprising:positioning a semiconductor device proximate to a substrate, the semiconductor device having a circuit element, the substrate having a cavity;aligning a non-conductive material, carried by the semiconductor device, with the cavity;connecting an electrically conductive structure between the semiconductor device and the substrate, the electrically conductive structure being adjacent the non-conductive material; andat least partially flowing an underfill material positioned between the semiconductor device and the substrate.2. The method of claim 1 , further comprising applying the underfill material to the semiconductor device.3. The method of wherein applying the underfill material includes applying a sheet of the underfill material.4. The method of wherein connecting includes reflowing a volume of solder.5. The method of wherein at least partially ...

Method and apparatus for multiple direct transfers of semiconductor devices

An apparatus for a direct transfer of a semiconductor device die from a wafer tape to a substrate. A first frame holds the wafer tape and a second frame secures the substrate. The second frame holds the substrate such that a transfer surface is disposed facing the semiconductor device die on a first side of the wafer tape. Two or more needles are disposed adjacent a second side of the wafer tape opposite the first side. A length of the two or more needles extends in a direction toward the wafer tape. A needle actuator actuates the two or more needles into a die transfer position at which at least one needle of the two or more needles presses on the second side of the wafer tape to press a semiconductor device die of the one or more semiconductor device die into contact with the transfer surface of the substrate.

BATCH BONDING APPARATUS AND BONDING METHOD

A batch bonding apparatus and bonding method. The bonding apparatus comprises: a chip supply unit () for providing a chip () to be bonded; a substrate supply unit () for providing a substrate; a transfer unit () for transferring the chip () between the chip supply unit () and the substrate supply unit (); and a pickup unit () disposed above the chip supply unit (), for picking up the chip () from the chip supply unit () and uploading the chip () to the transfer unit () after flipping a marked surface of the chip () in a required direction. In the present invention pickup of each chip is completed individually, but transfer processes and bonding processes can be carried out for multiple chips at the same time, greatly increasing yield. 1. A batch bonding apparatus , comprising:a chip supply unit, configured to provide chips to be bonded;a substrate supply unit, configured to provide a substrate;a conveying unit, configured to transfer the chips between the chip supply unit and the substrate supply unit; anda pickup unit, disposed above the chip supply unit and configured to, pick up each chip from the chip supply unit and load the chip onto the conveying unit after flipping a mark surface of the chip to a required orientation.2. The batch bonding apparatus of claim 1 , wherein the pickup unit comprises a first pickup assembly and a second pickup assembly claim 1 , wherein the first pickup assembly is disposed above the chip supply unit claim 1 , and comprises a first rotating part and a first pickup head disposed on the first rotating part claim 1 , wherein the second pickup assembly comprises a second rotating part and a second pickup head disposed on the second rotating part claim 1 , wherein the first pickup head picks up the chip from the chip supply unit and transfers the chip to the conveying unit or to the second pickup head.3. The batch bonding apparatus of claim 2 , wherein a rotational angle of each rotation of the first rotating part is 90° or 180°.4. The ...

Method and apparatus for direct transfer of multiple semiconductor devices

An apparatus for a direct transfer of a semiconductor device die from a wafer tape to a substrate. A first frame holds the wafer tape and a second frame secures the substrate. The second frame holds the substrate such that a transfer surface is disposed facing the semiconductor device die on a first side of the wafer tape. Two or more needles are disposed adjacent a second side of the wafer tape opposite the first side. A length of the two or more needles extends in a direction toward the wafer tape. A needle actuator actuates the two or more needles into a die transfer position at which at least one needle of the two or more needles presses on the second side of the wafer tape to press a semiconductor device die of the one or more semiconductor device die into contact with the transfer surface of the substrate.

電子デバイス、および、電子デバイスの製造方法

Multichip semi-conductor component and method for the production thereof

The invention relates to a multichip semi-conductor component (1) comprising at least one group of chips which is made of at least two semi-conductor chips (2, 3) having a first and a second surface side, whereby the first surface sides thereof face each other. The adjacent surface sides of the semi-conductor chips (2, 3) respectively have a spatial structure (7) and the spatial structures (7) engage with each other in a positive fit in such a manner that the geometric arrangement of the surface sides of the semi-conductor chips (2, 3), facing each other, is distinct and the metal connection of the semi-conductor chips (2, 3) facing each other is reliably conductive. The semi-conductor chips (2, 3) are mounted by vibrating said semi-conductor chips (2, 3) on a machine system.