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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 1397. Отображено 100.
01-03-2012 дата публикации

Process for assembling two parts of a circuit

Номер: US20120052629A1
Автор: Patrick Lamontagne, Perceval Coudrain, Yacine Felk
Принадлежит: STMICROELECTRONICS SA

A three-dimensional integrated structure is fabricated by assembling at least two parts together, wherein each part contains at least one metallic line covered with a covering region and having a free side. A cavity is formed in the covering region of each part, that cavity opening onto the metallic line. The two parts are joined together with the free sides facing each other and the cavities in each covering region aligned with each other. The metallic lines are then electrically joined to each other through an electromigration of the metal within at least one of the metallic lines, the electromigrated material filling the aligned cavities.

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Номер записи: 1
21-06-2012 дата публикации

Tsv for 3d packaging of semiconductor device and fabrication method thereof

Номер: US20120153496A1
Автор: Chang-woo Lee, Jae-hak Lee, Joon-Yub Song, Tae-Ho Ha
Принадлежит: Korea Institute of Machinery and Materials KIMM

The present invention relates to a through silicon via (TSV) for 3D packaging to integrate a semiconductor device and a method for manufacturing the same, and more particularly, to a through silicon via (TSV) for 3D packaging of a semiconductor device that is capable of improving production efficiency, having very high electric conductivity, and minimizing electrical signal delay, without using a carrier wafer by self-aligning substrates in a low temperature state and sequentially bonding a plurality of semiconductor dies (or semiconductor chips), and a method of manufacturing the same.

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Номер записи: 2
15-11-2012 дата публикации

Electronic device and manufacturing thereof

Номер: US20120286293A1
Автор: Josef Hoeglauer, Ralf Otremba
Принадлежит: INFINEON TECHNOLOGIES AG

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

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Номер записи: 3
29-11-2012 дата публикации

Power Semiconductor Module with Embedded Chip Package

Номер: US20120299150A1
Автор: Benjamin Tang, Frank Daeche, Kenneth Ostrom, Laura Carpenter
Принадлежит: INFINEON TECHNOLOGIES AG, Primarion Inc

A power semiconductor module includes a power semiconductor die, a metal substrate, a patterned metallization layer, a plurality of padless electrical connections, a plurality of vias and an inductor. The power semiconductor die has a top surface, an opposing bottom surface and a plurality of sides extending between the top and bottom surfaces. The metal substrate is attached to the bottom surface of the die. The patterned metallization layer is disposed above the top surface of the die. The plurality of padless electrical connections are at the top surface of the die and connect the patterned metallization layer to the die. The plurality of vias are disposed adjacent one or more of the sides of the die and electrically connected to the patterned metallization layer at a first end of the plurality of vias and to the metal substrate at a second end of the plurality of vias.

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Номер записи: 4
13-12-2012 дата публикации

Layered chip package and method of manufacturing same

Номер: US20120313260A1
Автор: Atsushi Iijima, Hiroshi Ikejima, Hiroyuki Ito, Yoshitaka Sasaki
Принадлежит: Headway Technologies Inc, SAE Magnetics HK Ltd

A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

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Номер записи: 5
27-12-2012 дата публикации

Semiconductor device package and method of manufacturing thereof

Номер: US20120329207A1
Автор: Arun Virupaksha Gowda, Paul Alan McConnelee, Richard Alfred Beaupre, Thomas Bert Gorczyca
Принадлежит: General Electric Co

A semiconductor device package includes a semiconductor device having connection pads formed thereon, with the connection pads being formed on first and second surfaces of the semiconductor device with edges of the semiconductor device extending therebetween. A first passivation layer is applied on the semiconductor device and a base dielectric laminate is affixed to the first surface of the semiconductor device that has a thickness greater than that of the first passivation layer. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface and the edges of the semiconductor device, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads.

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Номер записи: 6
24-01-2013 дата публикации

Semiconductor packages and methods of forming the same

Номер: US20130020720A1
Автор: Chul-Yong JANG, JONGHO LEE, Taehoon Kim, Young Lyong Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.

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Номер записи: 7
07-02-2013 дата публикации

Three dimensional semiconductor assembly board with bump/flange supporting board, coreless build-up circuitry and built-in electronic device

Номер: US20130032938A1
Автор: Charles W.C. Lin, Chia-Chung Wang
Принадлежит: Individual

A semiconductor assembly board includes a supporting board, a coreless build-up circuitry and a built-in electronic device. The supporting board includes a bump, a flange and a via hole in the bump. The built-in electronic device extends into the via hole and is electrically connected to the build-up circuitry. The build-up circuitry extends from the flange and the built-in electronic device and provides signal routing for the built-in electronic device. The supporting board provides mechanical support, ground/power plane and heat sink for the coreless build-up circuitry.

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Номер записи: 8
02-05-2013 дата публикации

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

Номер: US20130105989A1
Автор: Reza A. Pagaila, Seng Guan Chow, Seung Uk Yoon
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

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Номер записи: 9
23-01-2014 дата публикации

Method of Manufacturing a Semiconductor Device with a Carrier Having a Cavity and Semiconductor Device

Номер: US20140021634A1
Автор: Ivan Nikitin, Joachim Mahler
Принадлежит: INFINEON TECHNOLOGIES AG

A method includes providing a carrier having a first cavity, providing a dielectric foil with a metal layer attached to the dielectric foil, placing a first semiconductor chip in the first cavity of the carrier, and applying the dielectric foil to the carrier.

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Номер записи: 10
27-02-2014 дата публикации

Electronic Assembly With Three Dimensional Inkjet Printed Traces

Номер: US20140054795A1
Автор: Frank Stepniak, Lance Cole Wright, Leslie Edward Stark, Matthew David Romig, Sreenivasan K. Koduri
Принадлежит: Texas Instruments Inc

One method of making an electronic assembly includes mounting one electrical substrate on another electrical substrate with a face surface on the one substrate oriented transversely of a face surface of the other substrate. The method also includes inkjet printing on the face surfaces a conductive trace that connects an electrical contact on the one substrate with an electrical connector on the other substrate. An electronic assembly may include a first substrate having a generally flat surface with a first plurality of electrical contacts thereon; a second substrate having a generally flat surface with a second plurality of electrical contacts thereon, the surface of the second substrate extending transversely of the surface of said first substrate; and at least one continuous conductive ink trace electrically connecting at least one of the first plurality of electrical contacts with at least one of the second plurality of electrical contacts.

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Номер записи: 11
06-03-2014 дата публикации

Method of manufacturing semiconductor device

Номер: US20140065767A1
Автор: Michiaki Sugiyama, Nobuhiro Kinoshita
Принадлежит: Renesas Electronics Corp

In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.

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Номер записи: 12
13-03-2014 дата публикации

Techniques for reducing inductance in through-die vias of an electronic assembly

Номер: US20140071652A1
Автор: Kevin J. Hess, Michael B. McShane, Perry H. Pelley, Tab A. Stephens
Принадлежит: FREESCALE SEMICONDUCTOR INC

An electronic assembly includes a processor die assembly, a first die assembly, and a second die assembly. The first die assembly is positioned on a first side of the processor die assembly. The second die assembly is positioned on a second side of the processor die assembly opposite the first side of the processor die assembly. Through-die vias couple the first and second die assemblies to the processor die assembly.

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Номер записи: 13
07-01-2021 дата публикации

Electronic circuit device and method of manufacturing electronic circuit device

Номер: US20210005555A1
Автор: Shuzo Akejima
Принадлежит: Rising Technologies Co Ltd

The electronic circuit device according to the present invention including the wiring layer 13 including a plurality of the metal wirings, the photosensitive resin layer 21 made of the photosensitive resin arranged on the wiring layer 13, and the first electronic circuit element 33 arranged in the photosensitive resin layer 21. In this electronic circuit device, a plurality of opening 41 for exposing a part of the wiring layer 13 is formed on the photosensitive resin layer 21, and further, together with three-dimensionally connected to the first electronic circuit element 33, the re-distribution layer 42 on the first electronic circuit element including a plurality of the metal wirings which is three-dimensionally connected via a plurality of openings to a part of the wiring layer 13, and the first external connection terminal 51 connected to the re-distribution layer 42 are formed.

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Номер записи: 14
03-01-2019 дата публикации

DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20190006335A1
Автор: KIM Hanseok, Lee Changho, Lee SeungChul, YUN Mira
Принадлежит: LG DISPLAY CO., LTD.

Disclosed herein are a display device with a reduced bezel area and a method for fabricating the same. A wiring electrode disposed on a substrate is electrically connected to a connection electrode disposed on an inclined surface of a circuit board in contact with the substrate, and the connection electrode is electrically connected to a circuit wiring disposed on the circuit board. Therefore, an inactive area such as a pad portion for connecting the substrate with the circuit board is not required, such that the bezel area can be reduced. 1. A display device comprising:a substrate with light-emitting elements and wiring electrodes for supplying driving signals and current thereto;a circuit board disposed on the substrate and covering a part of the wiring electrodes, a plurality of circuit wirings being disposed on a first surface of the circuit board; anda plurality of connection electrodes respectively connecting the wiring electrodes to the circuit wirings,wherein the circuit board has an inclined surface and the connection electrodes extend on the inclined surface to the first surface of the circuit board.2. The display device of claim 1 , wherein the inclined surface is disposed between the first surface and the substrate and/or wherein the first surface extends in parallel to the substrate.3. The display device of claim 1 , further comprising: a buffer layer at the inclined surface of the circuit board for compensating a step difference between the circuit board and the substrate.4. The display device of claim 3 , wherein the buffer layer has a tapered shape with an inclination angle with respect to the substrate corresponding to that of the inclined surface of the circuit board.5. The display device of claim 1 , wherein a reflective layer is disposed between the circuit board and the substrate.6. The display device of claim 1 , wherein the connection electrodes and/or at least one dummy electrode extend from the substrate on the inclined surface to the first ...

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Номер записи: 15
11-01-2018 дата публикации

SEMICONDUCTOR PACKAGE WITH CONDUCTIVE CLIP

Номер: US20180012859A1
Автор: Standing Martin
Принадлежит:

A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can. 117-. (canceled)18. A method comprising:forming at least one terminal for a semiconductor package;forming a dielectric body to electrically insulate said at least one terminal from a conductive clip of said semiconductor package;connecting a power electrode of a power semiconductor device to said conductive clip.19. The method of further comprising depositing a solder resist over at least a portion of said at least one terminal.20. The method of further comprising forming a conductive pad for said semiconductor package.21. The method of further comprising forming a track to connect said conductive pad to said at least one terminal.22. The method of claim 18 , wherein said conductive clip is plated with either gold or silver.23. The method of claim 18 , wherein said dielectric body comprises polymer.24. The method of claim 18 , wherein said dielectric body comprises dielectric particles in an organic base.25. The method of claim 24 , wherein said organic base comprises one of epoxy claim 24 , acrylate claim 24 , polyimide and organopolysiloxane.26. The method of claim 24 , wherein said dielectric particles comprise a metal oxide.27. The method of claim 26 , wherein said metal oxide is alumina. This application is a continuation of U.S. application Ser. No. 11/799,140, filed May 1, 2007, entitled Semiconductor Package which is a division of U.S. application Ser. No. 11/405,825, filed Apr. 18, 2006, entitled Semiconductor Package which is based on and claims benefit of U.S. Provisional Application No. 60/674,162, filed on Apr. 21, 2005, entitled Semiconductor Package, to which a claim of priority is hereby made and the disclosure of which is incorporated by reference.The present invention relates to semiconductor packages ...

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Номер записи: 16
09-01-2020 дата публикации

Semiconductor Structure and Method of Forming the Same

Номер: US20200013750A1
Автор: Chang Tai-Min, Hsieh Yun Chen, Kuo Hung-Jui, Lei Yi-Yang, Peng Jyun-Siang, Tsai Hui-Jung, Yu Chen-Hua
Принадлежит:

A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region. 1. A structure comprising:a device die;an encapsulant encapsulating the device die therein;a first plurality of Redistribution Lines (RDLs) overlying and electrically coupling to the device die, wherein the first plurality of RDLs have a first pitch, and the first plurality of RDLs are substantially free from undercuts; anda second plurality of RDLs overlying and electrically coupling to the device die, wherein the second plurality of RDLs have a second pitch greater than the first pitch, and the second plurality of RDLs have undercuts.2. The structure of claim 1 , wherein each of the first plurality of RDLs and the second plurality of RDLs comprises an adhesion layer and a metal region over the adhesion layer claim 1 , wherein the adhesion layers in the first plurality of RDLs are free from undercuts claim 1 , and the adhesion layers in the second plurality of RDLs have undercuts.3. The structure of claim 1 , wherein all RDLs at a same level as the first plurality of RDLs are substantially free from undercuts claim 1 , and all RDLs at a same level as the second plurality of RDLs have undercuts.4. The structure of claim 1 , wherein all RDLs at levels underlying the first plurality of RDLs and over the device die are substantially free from ...

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Номер записи: 17
09-01-2020 дата публикации

Semiconductor Device and Method

Номер: US20200014169A1
Автор: An-Jhih Su, Chen-Hua Yu, Chia-Nan Yuan, Der-Chyang Yeh, Ming Shih Yeh, Shih-Guo Shen, Yu-Hung Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

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Номер записи: 18
21-01-2016 дата публикации

Selective die electrical insulation by additive process

Номер: US20160020188A1
Автор: Jeffrey S. Leal
Принадлежит: Invensas LLC

Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a stack of die, include additive processes for electrically insulating selected surface regions of the die. Regions that are not insulated according to the invention are available for electrical connection using electrically conductive material applied in flowable form to make electrically conductive traces.

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Номер записи: 19
19-01-2017 дата публикации

Microelectronic assemblies formed using metal silicide, and methods of fabrication

Номер: US20170018517A1
Автор: Arkalgud R. Sitaram, HONG Shen, Liang Wang
Принадлежит: Invensas LLC

Two microelectronic components ( 110, 120 ), e.g. a die and an interposer, are bonded to each other. One of the components' contact pads ( 110 C) include metal, and the other component has silicon ( 410 ) which reacts with the metal to form metal silicide ( 504 ). Then a hole ( 510 ) is made through one of the components to reach the metal silicide and possibly even the unreacted metal ( 110 C) of the other component. The hole is filled with a conductor ( 130 ), possibly metal, to provide a conductive via that can be electrically coupled to contact pads ( 120 C.B) attachable to other circuit elements or microelectronic components, e.g. to a printed circuit board.

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Номер записи: 20
03-02-2022 дата публикации

FLEXIBLE CIRCUITS ON SOFT SUBSTRATES

Номер: US20220037278A1
Автор: MAHAJAN Ankit, Meyers Kara A., Niccum Kayla C., Pekurovsky Mikhail L., PITERA Gino L., Rowe David J., Shah Saagar A., Taylor Daniel B.
Принадлежит:

An article includes a solid circuit die on a first major surface of a substrate, wherein the solid circuit die includes an arrangement of contact pads, and wherein at least a portion of the contact pads in the arrangement of contact pads are at least partially exposed on the first major surface of the substrate to provide an arrangement of exposed contact pads; a guide layer including an arrangement of microchannels, wherein the guide layer contacts the first major surface of the substrate such that at least some microchannels in the arrangement of microchannels overlie the at least some exposed contact pads in the arrangement of exposed contact pads; and a conductive particle-containing liquid in at least some of the microchannels. Other articles and methods of manufacturing the articles are described. 1. An article , comprising:a solid circuit die on a first major surface of a substrate, wherein the solid circuit die comprises an arrangement of contact pads, and wherein at least a portion of the contact pads in the arrangement of contact pads are at least partially exposed on the first major surface of the substrate to provide an arrangement of exposed contact pads;a guide layer comprising an arrangement of microchannels, wherein the guide layer contacts the first major surface of the substrate such that at least some microchannels in the arrangement of microchannels overlie the at least some exposed contact pads in the arrangement of exposed contact pads; anda conductive particle-containing liquid in at least some of the microchannels.2. The article of claim 1 , wherein the solid circuit die is at least partially embedded in the first major surface of the substrate.3. The article of claim 1 , wherein the solid circuit die is embedded in the first major surface of the substrate.4. The article of claim 1 , wherein the substrate comprises a flexible polymeric material.5. The article of claim 1 , wherein the guide layer comprises a layer of a polymeric material and a ...

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Номер записи: 21
03-02-2022 дата публикации

Multi-layer semiconductor package with stacked passive components

Номер: US20220037280A1
Автор: Liang Wan, Michael Gerald Amaro, Naweed Anjum, Yiqi Tang
Принадлежит: Texas Instruments Inc

A semiconductor package includes a first layer including a semiconductor die embedded within a dielectric substrate, and a first set of metal pillars extending through the dielectric substrate, a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer, and a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.

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Номер записи: 22
18-01-2018 дата публикации

Chip packaging and composite system board

Номер: US20180019178A1
Автор: Jing-Yao Chang, Kuo-Shu Kao, Tao-Chih Chang, Yu-Min Lin
Принадлежит: Industrial Technology Research Institute ITRI

A chip packaging includes a substrate, a first chip, a molding material, a first circuit, and a second circuit. The substrate includes a bottom surface, a first top surface disposed above the bottom surface with a first height, and a second top surface disposed above the bottom surface with a second height. The first height is smaller than the second height. The first chip is disposed on the first top surface. The molding material is disposed on the substrate and covers the first chip. The first and second circuits are disposed on the molding material, and are respectively and electrically connected to the first chip and the second top surface of the substrate. The substrate is made of copper material with huge area and has the properties of high current withstand capacity and high thermal efficiency. The second top surface protects the first chip from damage.

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Номер записи: 23
18-01-2018 дата публикации

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

Номер: US20180019191A1
Автор: Katkar Rajesh, Uzoh Cyprian Emeka
Принадлежит: INVENSAS CORPORATION

A solder connection may be surrounded by a solder locking layer () and may be recessed in a hole () in that layer. The recess may be obtained by evaporating a vaporizable portion () of the solder connection. Other features are also provided. 1. A manufacturing method comprising: one or more first components each of which comprises solder and a material sublimatable or vaporizable when the solder is melted; and', 'a first layer comprising a top surface and one or more holes in the top surface, each hole containing at least a segment of a corresponding first component;, 'obtaining a first structure comprisingheating each first component to sublimate or vaporize at least part of each sublimatable or vaporizable material and provide an electrically conductive connection at a location of each first component;wherein in the heating operation at least part of each first component recedes down from the top surface to provide or increase a recess in each hole at the top surface.2. The method of wherein each hole is a through-hole.3. The method of wherein each hole's sidewall is a dielectric sidewall.4. The method of wherein the first layer is dielectric.5. The method of wherein the first layer is formed by molding.6. The method of further comprising:obtaining a second structure with one or more protruding conductive posts; andinserting each conductive post into a corresponding recess provided or increased in the heating operation, and forming a solder bond in each recess between the corresponding conductive post and the corresponding electrically conductive connection.7. The method of wherein before the heating operation claim 1 , at least a segment of each first component either:comprises of a solder core coated with the sublimatable or vaporizable material; orconsists of the sublimatable or vaporizable material.8. The method of wherein in obtaining the first structure claim 7 , the one or more first components are formed before the first layer.9. The method of wherein in ...

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Номер записи: 24
16-01-2020 дата публикации

Integrated fan-out packages and methods of forming the same

Номер: US20200020628A1
Автор: Chang-Wen Huang, Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yu-Sheng Hsieh, Yung-Ping Chiang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

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Номер записи: 25
28-01-2021 дата публикации

Electrical Interconnection Of Circuit Elements On A Substrate Without Prior Patterning

Номер: US20210028141A1
Автор: Fogel Ofer, Kotler Zvi, Zenou Michael
Принадлежит:

A method for producing electronic devices includes fixing a die that includes an electronic component with integral contacts to a dielectric substrate. After fixing the die, a conductive trace is printed over both the dielectric substrate and at least one of the integral contacts, so as to create an ohmic connection between the conductive trace on the substrate and the electronic component. 1. A method for producing electronic devices , the method comprising:fixing a die that includes an electronic component with integral contacts to a dielectric substrate; andafter fixing the die, printing a conductive trace over both the dielectric substrate and at least one of the integral contacts, so as to create an ohmic connection between the conductive trace on the dielectric substrate and the electronic component.2. The method according to claim 1 , wherein printing the conductive trace comprises ejecting droplets of a conductive material onto both the dielectric substrate and the at least one of the integral contacts.3. The method according to claim 2 , wherein ejecting the droplets comprises directing a pulsed laser beam to impinge on a donor film comprising the conductive material claim 2 , whereby the droplets are ejected by laser-induced forward transfer (LIFT).4. The method according to claim 3 , wherein ejecting the droplets comprises directing the pulsed laser beam so that the droplets are ejected toward the die at an oblique angle relative to a surface of substrate.5. The method according to claim 3 , wherein ejecting the droplets comprises directing the pulsed laser beam to impinge on a first donor film comprising a first metal having a first melting temperature so as to form an adhesion layer on the dielectric substrate along a track of the conductive trace claim 3 , and then directing the pulsed laser beam to impinge on a second donor film comprising a second metal having a second melting temperature claim 3 , higher than the first melting temperature claim 3 , ...

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Номер записи: 26
08-02-2018 дата публикации

Remapped Packaged Extracted Die with 3D Printed Bond Connections

Номер: US20180040529A1
Автор: Erick Merle Spory
Принадлежит: Global Circuit Innovations Inc

An integrated circuit is provided. The integrated circuit includes a package base including package leads, an extracted die removed from a previous packaged integrated circuit, and an an interposer bonded to the extracted die and the package base. The extracted die includes original bond pads and one or more original ball bonds on the original bond pads. The interposer includes first bond pads electrically connected to the original bond pads with 3D printed first bond connections conforming to the shapes and surfaces of the extracted die and the interposer and second bond pads electrically connected to the package leads with 3D printed second bond connections conforming to shapes and surfaces of the interposer and package base.

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Номер записи: 27
12-02-2015 дата публикации

Fan-Out WLP With Package

Номер: US20150044824A1
Автор: Belgacem Haba, Hiroaki Sato, Ilyas Mohammed, Kiyoaki Hashimoto, Norihito Masuda, Philip Damberg, Yoshikuni Nakadaira
Принадлежит: Tessera LLC

The present disclosure is directed to a method for making a microelectronic package that includes assembling a microelectronic unit with a substrate, and electrically connecting redistribution contacts on the microelectronic unit and terminals on the substrate with a conductive matrix material extending within at least one opening extending through the substrate.

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Номер записи: 28
08-05-2014 дата публикации

Method for fabricating a semiconductor and semiconductor package

Номер: US20140127859A1
Автор: Gottfried Beer, Irmgard Escher-Poeppel
Принадлежит: Intel Mobile Communications GmbH

A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.

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Номер записи: 29
03-03-2022 дата публикации

SEMICONDUCTOR PACKAGE, REDISTRIBUTION STRUCTURE AND METHOD FOR FORMING THE SAME

Номер: US20220068869A1
Автор: Ho MIng-Che, Kuo Hung-Jui, Lee Chiang-Hao
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor package, a redistribution structure and a method for forming the same are provided. The redistribution structure for coupling an encapsulated die is provided, the redistribution structure includes a conductive pattern disposed over and electrically coupled to the encapsulated die. The conductive pattern extends beyond an edge of the encapsulated die along a first extending direction which intersects a second extending direction of the edge of the encapsulated die by an angle in a top view, and an impurity concentration of sulfur in the conductive pattern is less than about 0.1 ppm.

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Номер записи: 30
22-02-2018 дата публикации

3D Printed Hermetic Package Assembly and Method

Номер: US20180053702A1
Автор: Erick Merle Spory
Принадлежит: Global Circuit Innovations Inc

A method is provided. The method includes one or more of removing existing ball bonds from an extracted die, placing the extracted die into a recess of a hermetic substrate, the extracted die having a centered orientation in the recess, and applying a side fill compound into the recess between the extracted die and the hermetic substrate. The method also includes 3D printing, by a 3D printer, a plurality of bond connections between die pads of the extracted die and first bond pads of the hermetic substrate in order to create a 3D printed die substrate, and 3D printing a hermetic encapsulation over the die, the side fill compound, and the 3D printed bond connections in order to create a hermetic assembly. The extracted die includes a fully functional semiconductor die removed from a previous package. The hermetic substrate includes the first bond pads coupled to second bond pads.

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Номер записи: 31
13-02-2020 дата публикации

Semiconductor Structure and Method of Forming the Same

Номер: US20200051949A1
Автор: Chang Tai-Min, Hsieh Yun Chen, Kuo Hung-Jui, Lei Yi-Yang, Peng Jyun-Siang, Tsai Hui-Jung, Yu Chen-Hua
Принадлежит:

A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region. 1. A method comprising:encapsulating a device die in an encapsulating material;planarizing the encapsulating material and the device die; an adhesion layer; and', 'a metal region over the adhesion layer; and, 'forming a conductive feature over and electrically coupling to the device die, wherein the conductive feature comprisesafter the conductive feature is formed, performing a re-etching process, wherein in the re-etching process, the metal region is etched faster than the adhesion layer.2. The method of claim 1 , wherein before the re-etching process claim 1 , a first edge of the adhesion layer is laterally recessed more than a corresponding second edge of the metal region to form an undercut claim 1 , and the undercut is at least reduced in size by the re-etching process.3. The method of claim 2 , wherein the undercut is eliminated by the re-etching process.4. The method of claim 2 , wherein after the re-etching process claim 2 , the adhesion layer extends laterally beyond the corresponding second edge of the metal region.5. The method of claim 1 , wherein the forming the conductive feature comprises:depositing a first conductive material to form a first seed layer;depositing a second conductive material different from the first conductive ...

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Номер записи: 32
10-03-2022 дата публикации

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20220077051A1
Автор: Chou Hsin-Hung, Chu Yen-Jui, Lin Chun-Hung
Принадлежит: WINBOND ELECTRONICS CORP.

A package structure including a lead frame structure, a die, an adhesive layer, and at least one three-dimensional (3D) printing conductive wire is provided. The lead frame structure includes a carrier and a lead frame. The carrier has a recess. The lead frame is disposed on the carrier. The die is disposed in the recess. The die includes at least one pad. The adhesive layer is disposed between a bottom surface of the die and the carrier and between a sidewall of the die and the carrier. The 3D printing conductive wire is disposed on the lead frame, the adhesive layer, and the pad, and is electrically connected between the lead frame and the pad. 1. A package structure , comprising:{'claim-text': ['a carrier having a recess; and', 'a lead frame disposed on the carrier;'], '#text': 'a lead frame structure comprising:'}a die disposed in the recess and comprising at least one pad;an adhesive layer disposed between a bottom surface of the die and the carrier and between a sidewall of the die and the carrier; andat least one three-dimensional (3D) printing conductive wire disposed on the lead frame, the adhesive layer, and the at least one pad, and electrically connected between the lead frame and the at least one pad.2. The package structure according to claim 1 , wherein a height of a top surface of the die is equal to or higher than a height of a top surface of the lead frame.3. The package structure according to claim 1 , wherein a top surface of the adhesive layer is equal to or higher than a top surface of the die and a top surface of the lead frame.4. The package structure according to claim 1 , wherein in a case that a top surface of the adhesive layer is higher than a top surface of the die and a top surface of the lead frame claim 1 , the adhesive layer does not completely cover the at least one pad and the lead frame.5. The package structure according to claim 1 , wherein the carrier covers a portion of the lead frame to cause the carrier to be higher than the ...

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Номер записи: 33
01-03-2018 дата публикации

Semiconductor Device with Plated Lead Frame

Номер: US20180061671A1
Автор: Brockmeier Andre, Fastner Ulrike, von Koblinski Carsten, Zorn Peter
Принадлежит:

A semiconductor device includes an insulating carrier structure comprised of an insulating inorganic material. The carrier structure has a receptacle in which a semiconductor chip is disposed. The semiconductor chip has a first side, a second side and a lateral rim. The carrier structure laterally surrounds the semiconductor chip and the lateral rim. The semiconductor device also includes a metal structure on and in contact with the second side of the semiconductor chip and embedded in the carrier structure. 1. A semiconductor device , comprising:an insulating carrier structure comprised of an insulating inorganic material, the carrier structure comprising a receptacle;a semiconductor chip comprising a first side, a second side and a lateral rim, the semiconductor chip being disposed in the receptacle, wherein the carrier structure laterally surrounds the semiconductor chip and the lateral rim; anda metal structure on and in contact with the second side of the semiconductor chip and embedded in the carrier structure.2. The semiconductor device of claim 1 , wherein the metal structure has a thickness between about 30 μm to about 500 μm.3. The semiconductor device of claim 1 , wherein the insulating carrier structure comprises a carrier substrate and a cover substrate joined with the carrier substrate by an adhesive bond.4. The semiconductor device of claim 3 , wherein the carrier substrate comprises at least one of glass and ceramic.5. The semiconductor device of claim 3 , wherein the cover substrate comprises at least one of glass and ceramic.6. The semiconductor device of claim 1 , wherein the insulating carrier structure comprises a circumferential groove encompassing a peripheral region of the semiconductor chip.7. The semiconductor device of claim 1 , wherein the semiconductor chip comprises a semiconductor material comprising a first doping region formed in the semiconductor material at a first side of the semiconductor material and a second doping region ...

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Номер записи: 34
17-03-2022 дата публикации

Electronic circuit device

Номер: US20220084974A1
Автор: Shuzo Akejima
Принадлежит: Rising Technologies Co Ltd

An electronic circuit device according to the present invention includes a plane-shaped shield member having conductivity, at least one electronic circuit element having a first surface opposed to a second surface on which a connecting part is formed, the first surface arranged on the plane-shaped shield member, a rewiring layer comprises an insulating photosensitive resin layer enclosing the electronic circuit element on the plane-shaped shield member, a plurality of wiring photo vias having a plurality of first conductors electrically connected to a connecting part of the electronic element, a wiring having a second conductor electrically connected to each of the plurality of wiring photo vias on the same surface parallel to the plane-shaped shield member, and a wall-shaped shield groove having a third conductor for a sealing arranged to surround a thickness direction of the electronic circuit element.

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Номер записи: 35
17-03-2022 дата публикации

FAN-OUT PACKAGING STRUCTURE AND METHOD

Номер: US20220084997A1
Автор: Chen Yenheng, Lin Chengchung
Принадлежит:

The present disclosure provides a fan-out packaging structure and a method of fabricating the same. The fan-out packaging structure includes a redistribution layer, a passivation layer, a semiconductor chip, a first packaging layer, a groove, first metal bumps, second metal bumps, an adapter board, a stacked chip package, a passive element, and a filling layer. By means of the present disclosure, various chips performing different functions can be integrated into one packaging structure, thereby improving the integration level of the fan-out packaging structure. By means of the redistribution layer, the adapter board, and the first and second metal bumps, a three-dimensional vertically stacked packaging is achieved. As the result, in addition to improved integration level, the conduction paths in the packaging structure can be effectively shortened, thereby reducing power consumption, increasing the transmission speed, and increasing the data processing capacity. 1. A method of fabricating a fan-out chip package , comprising following steps:providing a support substrate, and forming a separation layer on the support substrate;forming a passivation layer on the separation layer, wherein the passivation layer comprises a first surface in contact with the separation layer and a second surface opposite to the first surface;providing a semiconductor chip, wherein the semiconductor chip is disposed on the second surface of the passivation layer, a back side of the semiconductor chip is bonded to the passivation layer, and a front side of the semiconductor chip faces away from the second surface of the passivation layer;packaging the passivation layer and the semiconductor chip by a first packaging layer, wherein a pad of the semiconductor chip is configured to be exposed from the first packaging layer;forming a redistribution layer on the first packaging layer, wherein the redistribution layer comprises a first surface in contact with the first packaging layer and a ...

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Номер записи: 36
08-03-2018 дата публикации

Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units

Номер: US20180068937A1
Автор: Chen Kang, Choi Won Kyoung, Gu Yu, Lin Yaojian, Marimuthu Pandi C.
Принадлежит: STATS ChipPAC Pte. Ltd.

A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die. 1. A semiconductor device , comprising:a substrate including a conductive via formed through the substrate;a modular interconnect unit including a vertical interconnect structure disposed over the substrate;a first semiconductor die disposed over the substrate adjacent to the modular interconnect unit; andan encapsulant deposited around the first semiconductor die and over modular interconnect unit with an opening in the encapsulant extending to the modular interconnect unit.2. The semiconductor device of claim 1 , further including a second semiconductor die disposed over the first semiconductor die with a bump of the second semiconductor die within the opening of the encapsulant to contact the vertical interconnect structure.3. The semiconductor device of claim 1 , further including a first interconnect structure disposed between the substrate and modular interconnect unit.4. The semiconductor device of claim 3 , further including a second interconnect structure disposed between the first interconnect structure and ...

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Номер записи: 37
19-03-2015 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20150076699A1
Автор: HISAZATO Yuuji, KODANI Kazuya, MATSUMURA Hitoshi, Sasaki Yo, YAMAMOTO Atsushi
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, a semiconductor device includes a semiconductor element, an interconnection layer, and a bonding layer. The interconnection layer includes Cu. The bonding layer includes a first alloy that is an alloy of Cu and a first metal other than Cu between the semiconductor element and the interconnection layer. A melting point of the first alloy is higher than a melting point of the first metal. 1. A semiconductor device comprising:a semiconductor element;an interconnection layer including Cu; anda bonding layer including a first alloy that is an alloy of Cu and a first metal other than Cu between the semiconductor element and the interconnection layer, a melting point of the first alloy being higher than a melting point of the first metal.2. The device according to claim 1 , wherein the first metal is one selected from the group consisting of tin (Sn) claim 1 , zinc (Zn) claim 1 , and indium (In).3. The device according to claim 1 , wherein the first metal is a second alloy of at least two selected from the group consisting of tin (Sn) claim 1 , zinc (Zn) claim 1 , indium (In) claim 1 , gold (Au) claim 1 , silver (Ag) claim 1 , and copper (Cu).4. The device according to claim 1 , wherein the bonding layer has a fillet portion spreading to an outside of an end of the semiconductor element as viewed in a direction from the semiconductor element toward the interconnection layer.5. The device according to claim 4 , wherein the fillet portion includes the first metal in a larger amount than the first alloy.6. The device according to claim 4 , whereinthe bonding layer has a central portion provided between the semiconductor element and the interconnection layer, and the fillet portion, andthe central portion is configured to form an alloy with the interconnection layer more easily than the fillet portion.7. The device according to claim 4 , whereinthe bonding layer has a central portion provided between the semiconductor element and the ...

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Номер записи: 38
11-03-2021 дата публикации

Method of manufacturing chip packaging structure

Номер: US20210074633A1
Автор: Chien-Chou Chen, Chun-Hsien Chien, Wei-Ti Lin, Wen-Liang Yeh
Принадлежит: Unimicron Technology Corp

A chip packaging structure includes a circuit redistribution structure, a chip, a sealing layer, and an antenna pattern. The circuit redistribution structure includes a first and a second circuit layer, and a conductive pad. The second circuit layer is disposed on and electrically connected to the first circuit layer. The conductive pad is electrically connected to the second circuit layer. The chip is disposed on the circuit redistribution structure and electrically connected to the second circuit layer. The sealing layer having an opening and a groove covers the chip and the circuit redistribution structure. The opening exposes the conductive pad. A portion of the groove communicates with the opening. The antenna pattern includes a first and a second portion. The first portion covers sidewalls of the opening and is electrically connected to the conductive pad. The second portion is filled in the groove and electrically connected to the first portion.

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Номер записи: 39
11-03-2021 дата публикации

SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Номер: US20210074665A1
Автор: Chen Wei-Chih, Hu Yu-Hsiang, Kuo Hung-Jui, LIAO SIH-HAO, Wang Po-Han
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor structure includes an insulating encapsulant, a semiconductor element, a redistribution layer and an insulating layer. The semiconductor element is embedded in the insulating encapsulant. The redistribution layer is disposed over the insulating encapsulant and electrically connected to the semiconductor element. The insulating layer is disposed in between the insulating encapsulant and the redistribution layer, wherein an uneven interface exists between the insulating layer and the insulating encapsulant, and a planar interface exists between the insulating layer and the redistribution layer. 1. A semiconductor structure , comprising:an insulating encapsulant;a semiconductor element embedded in the insulating encapsulant;a redistribution layer disposed over the insulating encapsulant and electrically connected to the semiconductor element; andan insulating layer disposed in between the insulating encapsulant and the redistribution layer, wherein an uneven interface exists between the insulating layer and the insulating encapsulant, and a planar interface exists between the insulating layer and the redistribution layer.2. The semiconductor structure according to claim 1 , further comprising:a patterned first seed layer and a plurality of conductive pillars embedded in the insulating layer in between the uneven interface and the planar interface, wherein the patterned first seed layer is located at a first surface of the insulating layer having the uneven interface, and the plurality of conductive pillars is located at a second surface of the insulating layer having the planar interface.3. The semiconductor structure according to claim 2 , further comprising:a patterned second seed layer disposed on the insulating layer over the planar interface, wherein the patterned second seed layer is surrounded by a dielectric layer of the redistribution layer, and the patterned second seed layer is physically separated from the patterned first seed layer.4. The ...

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Номер записи: 40
24-03-2022 дата публикации

Semiconductor Device and Method of Manufacture

Номер: US20220091505A1
Автор: Chen-Hua Yu, Hung-Jui Kuo, Sih-Hao Liao, Yu-Hsiang Hu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method of manufacturing a semiconductor device includes applying a polymer mixture over a substrate, exposing and developing at least a portion of the polymer mixture to form a developed dielectric, and curing the developed dielectric to form a dielectric layer. The polymer mixture includes a polymer precursor, a photosensitizer, and a solvent. The polymer precursor may be a polyamic acid ester.

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Номер записи: 41
15-03-2018 дата публикации

Method for fabricating a semiconductor package

Номер: US20180076185A1
Автор: Shiann-Tsong Tsai
Принадлежит: MediaTek Inc

A method for fabricating a semiconductor package is provided. Semiconductor dice are disposed on a top surface of a carrier. Each of the semiconductor dice has an active surface and a bottom surface that is opposite to the active surface. Input/output (I/O) pads are distributed on the active surface. Interconnect features are printed on the carrier and on the active surface of each of the semiconductor dice. The top surface of the carrier, the semiconductor dice and the interconnect features is encapsulated with an encapsulant. The carrier is then removed.

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Номер записи: 42
26-03-2015 дата публикации

Embedded semiconductor device package and method of manufacturing thereof

Номер: US20150084207A1
Автор: Arun Virupaksha Gowda, Paul Alan McConnelee, Shakti Singh Chauhan
Принадлежит: General Electric Co

A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).

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Номер записи: 43
18-03-2021 дата публикации

Wireless transmission module and manufacturing method

Номер: US20210082842A1
Автор: Qijing HE, Xiaojing Liao, Zhaozheng Hou
Принадлежит: Huawei Technologies Co Ltd

A wireless transmission module, chips, a passive component, and a coil are integrated into an integral structure, so that an integration level of the wireless transmission module is improved. In addition, the integral structure can effectively implement independence of the module, and the independent module can be flexibly arranged inside structural design of an electronic device, and does not need to be disposed on a mainboard of the electronic device. Only an input terminal of the wireless transmission module needs to be retained on the mainboard of the electronic device. In addition, the integral structure can further effectively increase a capability of a product for working continuously and normally in an extremely harsh scenario, and improve product reliability. In addition, in the structure of the wireless transmission module, the chips and the coil are integrated, and signal transmission paths between the chips and the coil are relatively short.

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Номер записи: 44
31-03-2022 дата публикации

DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE

Номер: US20220102604A1
Автор: DO Young Rag, YOO Gang Yeol
Принадлежит: Samsung Display Co., Ltd.

A display device includes a first electrode disposed on a substrate, a second electrode disposed on the substrate, and spaced apart from and facing the first electrode, at least one light emitting element disposed between the first electrode and the second electrode, a first conductive contact pattern disposed on the first electrode and electrically contacting the first electrode and an end of the at least one light emitting element, and a second conductive contact pattern disposed on the second electrode and electrically contacting the second electrode and another end of the at least one light emitting element. 1. A display device comprising:a first electrode disposed on a substrate;a second electrode disposed on the substrate, and spaced apart from and facing the first electrode;at least one light emitting element disposed between the first electrode and the second electrode;a first conductive contact pattern disposed on the first electrode and electrically contacting the first electrode and an end of the at least one light emitting element; anda second conductive contact pattern disposed on the second electrode and electrically contacting the second electrode and another end of the at least one light emitting element.2. The display device of claim 1 , whereinthe first conductive contact pattern and the second conductive contact pattern overlap the first electrode and the second electrode, respectively, in a plan view,the first conductive contact pattern and the second conductive contact pattern are directly connected to the first electrode and the second electrode, respectively, andan insulating material layer is not disposed in a region in which the first conductive contact pattern and the first electrode overlap in a plan view and a region in which the second conductive contact pattern and the second electrode overlap in a plan view.3. The display device of claim 2 , wherein the first electrode claim 2 , the second electrode claim 2 , the first conductive ...

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Номер записи: 45
01-04-2021 дата публикации

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Номер: US20210098328A1
Автор: Chu Yung-Chi, Hu Tian, Hu Yu-Hsiang, Kuo Hung-Jui, LIAO SIH-HAO
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor package includes a semiconductor die including a sensing component, an encapsulant extending along sidewalls of the semiconductor die, a through insulator via (TIV) and a dummy TIV penetrating through the encapsulant and disposed aside the semiconductor die, a patterned dielectric layer disposed on the encapsulant and exposing the sensing component of the semiconductor die, a conductive pattern disposed on the patterned dielectric layer and extending to be in contact with the TIV and the semiconductor die, and a first dummy conductive pattern disposed on the patterned dielectric layer and connected to the dummy TIV through an alignment opening of the first patterned dielectric layer. The semiconductor die is in a hollow region of the encapsulant, and a top width of the hollow region is greater than a width of the semiconductor die. 1. A semiconductor package , comprising:a semiconductor die comprising a sensing component;an encapsulant extending along sidewalls of the semiconductor die, the semiconductor die being in a hollow region of the encapsulant, and a top width of the hollow region being greater than a width of the semiconductor die;a through insulator via (TIV) and a dummy TIV penetrating through the encapsulant and disposed aside the semiconductor die;a patterned dielectric layer disposed on the encapsulant and exposing the sensing component of the semiconductor die;a conductive pattern disposed on the patterned dielectric layer and extending to be in contact with the TIV and the semiconductor die; anda first dummy conductive pattern disposed on the patterned dielectric layer and connected to the dummy TIV through an alignment opening of the patterned dielectric layer.2. The semiconductor package of claim 1 , wherein a surface roughness of a top surface of the encapsulant is greater than a surface roughness of a top surface of the dummy TIV where the first dummy conductive pattern lands on.3. The semiconductor package of claim 1 , wherein ...

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Номер записи: 46
01-04-2021 дата публикации

METHOD OF FABRCATING PACKAGE STRUCTURE

Номер: US20210098417A1
Автор: Chang Yu-Tzu, Kuo Hung-Jui, Tsai Hui-Jung, WANG Chia-Wei
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

Provided is a method for forming a conductive feature including forming a seed layer over a substrate; forming a patterned mask layer on the seed layer, wherein the patterned mask layer has an opening exposing the seed layer; forming a conductive material in the opening; removing the patterned mask layer to expose a portion of the seed layer; and removing the portion of the seed layer by using an etching solution including a protective agent, thereby forming a conductive feature, wherein the protective agent has multiple active sites to adsorb on the conductive material. 1. A method for forming a conductive feature , comprising:forming a seed layer over a substrate;forming a patterned mask layer on the seed layer, wherein the patterned mask layer has an opening exposing the seed layer;forming a conductive material in the opening;removing the patterned mask layer to expose a portion of the seed layer; andremoving the portion of the seed layer by using an etching solution comprising a protective agent, thereby forming a conductive feature, wherein the protective agent has multiple active sites to adsorb on the conductive material.4. The method of claim 1 , wherein the protective agent comprises an amine and the multiple active sites comprise nitrogen atoms claim 1 , oxygen atoms claim 1 , sulfur atoms or a combination thereof.5. The method of claim 1 , wherein the multiple active sites comprise nitrogen atoms claim 1 , and a ratio of a number of nitrogen atoms to a number of carbon atoms in the protective agent is greater than 0.08.6. The method of claim 1 , wherein during the removing the portion of the seed layer claim 1 , an etch rate of the conductive material is less than an etch rate of the seed layer.7. The method of claim 1 , wherein the patterned mask layer has an aspect ratio less than 5.8. A method for fabricating an integrated circuit claim 1 , comprising:forming a seed layer over a substrate;forming a patterned mask layer on the seed layer, wherein the ...

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Номер записи: 47
03-07-2014 дата публикации

Three-dimensional structure in which wiring is provided on its surface

Номер: US20140183751A1
Автор: Hiroaki Fujiwara, Hiromitsu Takashita, Shingo Yoshioka, Tsuyoshi Takeda
Принадлежит: Panasonic Corp

One aspect of the present invention is a three-dimensional structure in which a wiring is formed on a surface, the three-dimensional structure having an insulating resin layer that contains a filler formed from at least one element selected from typical non-metal elements and typical metal elements, wherein a recessed gutter for wiring is formed on a surface of the insulating resin layer, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring.

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Номер записи: 48
12-04-2018 дата публикации

ELECTRONIC SYSTEM HAVING INCREASED COUPLING BY USING HORIZONTAL AND VERTICAL COMMUNICATION CHANNELS

Номер: US20180102353A1
Автор: PAGANI Alberto
Принадлежит: STMICROELECTRONICS S.R.L.

An electronic system supports superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in printed circuit boards coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced. 1. An apparatus , comprising:an integrated circuit die comprising a semiconductor substrate and a metallization structure;wherein the semiconductor substrate includes integrated circuits and has a top surface and an oppositely arranged bottom surface and a side surface where the integrated circuit die was singulated from a wafer;wherein the metallization structure is mounted above the top surface of the semiconductor substrate and includes at least one contact pad and an electrical connection between the at least one contact pad and the integrated circuits; anda dielectric layer disposed in contact with a top surface of the metallization structure and the side surface of the semiconductor substrate;wherein the dielectric layer comprises a first communication pad that is electrically connected to said at least one contact pad and a second communication pad that is electrically connected to said at least one contact pad;wherein the first communication pad is disposed on a first face of the dielectric layer extending parallel to the top surface of the metallization structure and the second communication pad is disposed on a second face of the dielectric layer extending parallel to the side surface of the semiconductor substrate.2. The apparatus of claim 1 , wherein the second communication pad is electrically insulated from the side surface of the semiconductor substrate by said dielectric layer and ...

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Номер записи: 49
12-04-2018 дата публикации

LIGHT EMITTING DIODE DISPLAY WITH REDUNDANCY SCHEME

Номер: US20180102492A1
Автор: Bibl Andreas, Griggs Charles R., Perkins James Michael, Sakariya Kapil V.
Принадлежит:

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities. 1. A display panel with redundancy scheme comprising:a display substrate including a pixel area that includes an array of subpixels, each subpixel including a pair of landing areas;an array of redundant LED bonding site pairs, each landing area including a corresponding LED bonding site;wherein the array of subpixels includes a first subpixel array, a second subpixel array, and a third subpixel array, wherein the first, second, and third subpixel arrays are designed to emit different primary color emissions;circuitry to switch and drive the array of subpixels; andone or more LED device irregularities among the array of redundant LED bonding site pairs, wherein each corresponding landing area containing a micro LED device irregularity is electrically disconnected from the circuitry.2. The display panel of claim 2 , wherein each corresponding landing area is cut to electrically disconnect the corresponding landing area from the circuitry.3. The display panel of claim 3 , wherein the circuitry is contained within an array of micro controller chips.4. The display panel of claim 3 , wherein the array of micro controller chips is bonded to the display substrate.5. The display panel of claim 4 , wherein each micro controller chip is bonded to the display substrate within the pixel area.6. The display panel of claim 5 , wherein each micro controller chip is connected to a scan driver ...

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Номер записи: 50
08-04-2021 дата публикации

SILICON ON DIAMOND THERMAL AND SHIELDING MITIGATION

Номер: US20210104447A1
Автор: Dutta Ranadeep, Kim Jonghae, Lan Je-Hsiung
Принадлежит:

Active devices in an integrated circuit (IC) die package, such as in a radio frequency front end (RFFE) package can generate significant amount of heat. This problem can become acute especially as the operating frequency is high such as in 5G NR. Also, electromagnetic interference issues can arise in such packages. One or more techniques to mitigate thermal and electrical interference issues in IC die packages are presented. 1. A package , comprising:a laminate comprising a laminate redistribution layer (RDL); one or more active devices above a lower surface of the IC die and electrically coupled with the laminate RDL through one or more interconnects at the lower surface of the IC die, and', 'a thermal spreader on the one or more active devices, the thermal spreader being thermally conductive and electrically insulative;, 'an integrated circuit (IC) die on the laminate and comprising'}a mold on the laminate and on the IC die, the mold structured to surround side and upper surfaces of the IC die; anda cage within the mold, the cage structured to conduct heat generated by the one or more active devices emanating through the thermal spreader above an upper surface of the IC die from an interior of an IC die boundary to an exterior of the IC die boundary.2. The package of claim 1 , wherein the thermal spreader is a diamond layer.3. The package of claim 1 , a lateral mold part on the upper surface of the IC die, and', 'a side mold part on an upper surface of the laminate and on the side surfaces of the IC die, and, 'wherein the mold comprises'} a lateral cage part within the lateral mold part, the lateral cage part structured to conduct the heat emanating through the thermal spreader above the upper surface of the IC die from the interior of the IC die boundary to the exterior of the IC die boundary, and', 'a side cage part within the side mold part, the side cage part in contact with the lateral cage part such that the heat conducted to the exterior of the IC die ...

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Номер записи: 51
08-04-2021 дата публикации

Housing comprising a semiconductor body and a method for producing a housing with a semiconductor body

Номер: US20210104653A1
Автор: Martin Unterburger
Принадлежит: OSRAM OLED GmbH

A method for producing a component having a semiconductor body includes providing the semiconductor body including a radiation passage surface and a rear side facing away from the radiation passage surface, wherein the semiconductor body comprises on the rear side a connection location for the electrical contacting of the semiconductor body, providing a composite carrier including a carrier layer and a partly cured connecting layer, applying the semiconductor body on the composite carrier, such that the connection location penetrates into the partly cured connecting layer, curing the connecting layer to form a solid composite, applying a molded body material on the composite carrier after curing the connecting layer, wherein the molded body covers side surfaces of the semiconductor body, forming a cutout through the carrier layer and the connecting layer in order to expose the connection location, and filling the cutout with an electrically conductive material.

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Номер записи: 52
21-04-2016 дата публикации

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

Номер: US20160111410A1
Автор: Byung Tai Do, Linda Pei Ee CHUA, Reza A. Pagaila, Seng Guan Chow, Seung Uk Yoon
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

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Номер записи: 53
02-06-2022 дата публикации

METHOD FOR PRODUCING ELECTRONIC DEVICE

Номер: US20220173089A1
Автор: AKIYAMA Tomohiro, FURUYA Shogo, ISHIZAKI Junya
Принадлежит: SHIN-ETSU HANDOTAI CO., LTD.

The present invention is a method for producing an electronic device having a drive circuit including a solar cell structure, the method including the steps of: obtaining a bonded wafer by bonding a first wafer having a plurality of independent solar cell structures including a compound semiconductor, the solar cell structures being formed on a starting substrate by epitaxial growth, and a second wafer having a plurality of independent drive circuits formed, so that the plurality of solar cell structures and the plurality of drive circuits are respectively superimposed; wiring the bonded wafer so that electric power can be supplied from the plurality of solar cell structures to the plurality of drive circuits respectively; and producing an electronic device having the drive circuit including the solar cell structure by dicing the bonded wafer. This provides a method for producing an electronic device including a drive circuit and a solar cell structure in one chip and having a suppressed production cost. 15-. (canceled)6. A method for producing an electronic device having a drive circuit comprising a solar cell structure , the method comprising the steps of:obtaining a bonded wafer by bonding a first wafer having a plurality of independent solar cell structures comprising a compound semiconductor, the solar cell structures being formed on a starting substrate by epitaxial growth, and a second wafer having a plurality of independent drive circuits formed, so that the plurality of solar cell structures and the plurality of drive circuits are respectively superimposed;wiring the bonded wafer so that electric power can be supplied from the plurality of solar cell structures to the plurality of drive circuits respectively; andproducing an electronic device having the drive circuit comprising the solar cell structure by dicing the bonded wafer.7. The method for producing an electronic device according to claim 6 , wherein the bonding is carried out using a thermosetting ...

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Номер записи: 54
11-04-2019 дата публикации

Multi-Chip Fan Out Package and Methods of Forming the Same

Номер: US20190109118A1
Автор: Hung Jui-Pin, Lin Jing-Cheng, Yu Chen-Hua
Принадлежит:

A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line. 1. A method comprising:placing a first device die over a carrier, the first device die comprising a surface conductive feature;forming a first stud bump on the first device die;placing a second device die over the carrier;encapsulating the first device die and the second device die in an encapsulant;performing a planarization to planarize top surfaces of the encapsulant, the first stud bump, and a conductive feature of the second device die; andforming redistribution lines over and electrically coupling to the first stud bump and the surface conductive feature.2. The method of claim 1 , wherein the forming the first stud bump comprises:performing a wire bonding on the first device die; andcutting a metal wire used for the wire bonding to leave the first stud bump on the first device die.3. The method of further comprising:forming a second stud bump on the second device die through wire bonding; andsawing a wafer comprising the second device die and the second stud bump into discrete dies, wherein the discrete dies comprise the second device die.4. The method of claim 3 , wherein the first stud bump is formed after the first device die is placed claim 3 , and the second device die is placed on the wafer after the sawing.5. The method of further comprising claim 3 , before the sawing claim 3 , forming a polymer layer to embed a lower portion of the second stud bump therein claim 3 , wherein after the planarization claim 3 , the polymer layer is exposed.6. The method of claim 3 , wherein after the second device die is placed on the carrier claim 3 , an entirety of the second stud bump is higher than a surface dielectric layer of the second device die.7. The method of claim 6 , wherein after the ...

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Номер записи: 55
09-06-2022 дата публикации

Method for Contacting and Packetising a Semiconductor Chip

Номер: US20220181291A1
Автор: Lorenz Fabian, Rudolph Johannes, Seidel Peter, Werner Ralf
Принадлежит:

A method for contacting and packaging a semiconductor chip of a power electronic component. The power electronic component has a first contact face produced in a first step via a multi-material printing process and a semiconductor chip, which is placed in a second step onto the first contact face. A ceramic insulation layer, which surrounds the semiconductor chip along its circumference and extends over the first contact face not covered by the semiconductor chip, is printed in a third step onto the first contact face. A second contact face is printed in a fourth step onto the ceramic insulation layer and the semiconductor chip. In a fifth step, the power electronic component is sintered by means of heat treatment. 121232121432143. Method for contacting and packaging a semiconductor chip () of a power electronic component , wherein the power electronic component has a first , lower contact face () and a semiconductor chip () positioned thereon , characterized in that a ceramic insulation layer () , which surrounds the semiconductor chip () along its circumference and extends over the first contact face () not covered by the semiconductor chip () , is printed onto the lower contact face () , and in that a second , upper contact face () is printed onto the ceramic insulation layer () and the semiconductor chip () , wherein the first and second contact face ( , ) and the ceramic insulation layer () are created in a printing process by means of a 3D multi-material printer such that{'b': '1', 'in a first method step the first contact face () is produced by means of the multi-material printing process,'}{'b': 2', '1, 'in a second method step the semiconductor chip () is placed onto the first, lower contact face (),'}{'b': 3', '2', '1, 'in a third method step a ceramic insulation layer (), which surrounds the circumference of the semiconductor chip (), is printed onto the first contact face ),'}{'b': 4', '3', '2, 'in a fourth method step the second contact face () is ...

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Номер записи: 56
04-05-2017 дата публикации

PRINTING COMPLEX ELECTRONIC CIRCUITS

Номер: US20170125372A1
Автор: Blanchard Richard Austin, Lowenthal Mark David, Oraw Bradley Steven, Ray William Johnstone
Принадлежит:

A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. The devices in each group are connected in parallel so that each group acts as a single device. In one embodiment, about 10 devices are contained in each group so the redundancy makes each group very reliable. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits. 1. A method for forming a circuit comprising:providing an ink containing a plurality of pre-formed, semiconductor electrical devices mixed in a solvent, each of the devices having at least a first electrode and a second electrode;printing the ink, on a substrate, to form a plurality of separate groups of the pre-formed, semiconductor electrical devices, each group containing a plurality of substantially identical electrical devices forming a random two-dimensional arrangement of the electrical devices on the substrate;forming at least one conductor layer to connect the electrical devices in each group in parallel; andinterconnecting at least some of the groups, using an interconnection pattern, to achieve an electrical function.2. The method of wherein each of the electrical devices include three electrodes.3. The method of wherein the electrical devices include at least one of transistors or diodes.4. The method of wherein the step of interconnecting at least some of the groups comprises interconnecting at least some of the groups to create logic gates.5. The method of further comprising forming at least one input conductor for ...

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Номер записи: 57
16-04-2020 дата публикации

Package structure, semiconductor device and method of fabricating the same

Номер: US20200118960A1
Автор: Hung-Jui Kuo, Po-Han Wang, Sih-Hao Liao, Wei-Chih Chen, Yu-Hsiang Hu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die has a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars.

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Номер записи: 58
16-04-2020 дата публикации

Stack of electrical components and method of producing the same

Номер: US20200118963A1
Автор: Hiroshi Yamazaki, Hitoshi Iwama, Yohei Hirota, Yusuke Takahashi
Принадлежит: TDK Corp

A stack of electrical components has a first electrical component having a first surface, a second surface that is opposite to the first surface and a side surface that is located between the first surface and the second surface; a second electrical component having a third surface on which the first electrical component is mounted, the third surface facing the second surface and forming a corner portion between the third surface and the side surface; an adhesive layer that bonds the first electrical component to the second electrical component, wherein the adhesive layer has a first portion that is located between the second surface and the third surface and a curved second portion that fills the corner portion; and a conductive layer that extends on a side of the side surface, curves along the second portion and extends to the third surface.

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Номер записи: 59
10-05-2018 дата публикации

INTERCONNECTION STRUCTURES AND METHODS FOR TRANSFER-PRINTED INTEGRATED CIRCUIT ELEMENTS WITH IMPROVED INTERCONNECTION ALIGNMENT TOLERANCE

Номер: US20180130751A1
Автор: Bower Christopher
Принадлежит:

An electronic component array includes a backplane substrate, and a plurality of integrated circuit elements on the backplane substrate. Each of the integrated circuit elements includes a chiplet substrate having a connection pad and a conductor element on a surface thereof. The connection pad and the conductor element are electrically separated by an insulating layer that exposes at least a portion of the connection pad. At least one of the integrated circuit elements is misaligned on the backplane substrate relative to a desired position thereon. A plurality of conductive wires are provided on the backplane substrate including the integrated circuit elements thereon, and the connection pad of each of the integrated circuit elements is electrically connected to a respective one of the conductive wires notwithstanding the misalignment of the at least one of the integrated circuit elements. Related fabrication methods are also discussed. 110-. (canceled)11. An electronic component array , comprising:a backplane substrate;a plurality of integrated circuit elements disposed on the backplane substrate, each of the integrated circuit elements comprising a chiplet substrate, a connection pad, and a conductor element disposed on a surface of the chiplet substrate, wherein the connection pad and the conductor element are electrically separated by an insulating layer that exposes at least a portion of the connection pad, and wherein at least one of the integrated circuit elements is misaligned on the backplane substrate relative to a desired position thereon at a distance from the desired position that is greater than or equal to a distance between the conductor element and the connection pad; anda plurality of conductive wires on the backplane substrate, wherein the connection pad of each of the plurality of integrated circuit elements is electrically connected to a respective one of the conductive wires notwithstanding that the at least one of the integrated circuit ...

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Номер записи: 60
10-05-2018 дата публикации

ELECTRONIC SYSTEM HAVING INCREASED COUPLING BY USING HORIZONTAL AND VERTICAL COMMUNICATION CHANNELS

Номер: US20180130784A1
Автор: PAGANI Alberto
Принадлежит: STMICROELECTRONICS S.R.L.

An electronic system supports superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in printed circuit boards coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced. 1. An apparatus , comprising:a first integrated circuit die singulated from a wafer and comprising a first semiconductor substrate and a first metallization structure mounted to the first semiconductor substrate, wherein the first metallization structure includes a first contact pad;a second integrated circuit die singulated from a wafer and comprising a second semiconductor substrate and a second metallization structure mounted to the second semiconductor substrate, wherein the second metallization structure includes a second contact pad;a first dielectric layer disposed in contact with the first metallization structure and a side surface of the first semiconductor substrate, said first dielectric layer including a first communication pad that is electrically connected to said first contact pad;a second dielectric layer disposed in contact with the second metallization structure and a side surface of the second semiconductor substrate, said second dielectric layer including a second communication pad that is electrically connected to said second contact pad;wherein the first dielectric layer is positioned in physical contact with the second dielectric layer, andwherein the first communication pad is positioned for direct mechanical and electrical connection with the second communication pad.2. The apparatus of claim 1 , wherein the first communication pad is disposed on a face of the first dielectric ...

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Номер записи: 61
07-08-2014 дата публикации

Semiconductor light emitting device and method for manufacturing same

Номер: US20140217438A1
Автор: Akihiro Kojima, Hideto Furuyama, Hideyuki Tomizawa, Miyoko Shimada, Yoshiaki Sugizaki, Yosuke Akimoto
Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor light emitting device includes: a semiconductor layer; a first electrode; a first interconnection layer; a second electrode; a second interconnection layer; a support substrate; a bonding layer; a first terminal; and a second terminal. The support substrate has a third face facing the semiconductor layer, the first interconnection layer, and the second interconnection layer and a fourth face opposite to the third face. The support substrate has a first opening extending from the fourth face to the first interconnection layer and a second opening extending from the fourth face to the second interconnection layer. The bonding layer is provided between the support substrate and each of the semiconductor layer, the first interconnection layer, and the second interconnection layer.

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Номер записи: 62
07-08-2014 дата публикации

Package Structure and Methods of Forming Same

Номер: US20140217604A1
Автор: Bruce C.S. Chou, Chen-hua Lin, Chih-Hsien Lin, Hsiang-Tai Lu, Jung-Kuo Tu, Mingo Liu, Tung-Hung Hsieh
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes a first die having a first active surface and a first backside surface opposite the first active surface, a second die having a second active surface and a second backside surface opposite the second active surface, and an interposer, the first active surface of the first die being electrically coupled to a first side of the interposer, the second active surface of the second die being electrically coupled to a second side of the interposer. The semiconductor device also includes a first connector over the interposer, a first encapsulating material surrounding the second die, the first encapsulating material having a first surface over the interposer, and a via electrically coupling the first connector and the interposer. A first end of the via is substantially coplanar with the first surface of the first encapsulating material.

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Номер записи: 63
28-05-2015 дата публикации

Vertically connected integrated circuits

Номер: US20150145136A1
Автор: Ronald J. Jensen
Принадлежит: Honeywell International Inc

In some examples, an integrated circuit (IC) includes a semiconductor substrate defining a perimeter of the integrated circuit and a castellation formed at the perimeter. The IC also may include a layer including an electrically conductive material formed on a surface of the castellation. In some examples, the layer including the electrically conductive material is not substantially parallel to adjacent portions of the perimeter of the IC. The integrated circuit may be used in a system, in which the metallized castellation may be used to electrically connect the IC to an external structure, such as another IC or a printed board.

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Номер записи: 64
18-05-2017 дата публикации

THREE LAYER STACK STRUCTURE

Номер: US20170141088A1
Автор: Hu Kunzhong, Zhai Jun
Принадлежит:

Vertically stacked system in package structures are described. In an embodiment, a package includes a first level molding and fan out structure, a third level molding and fan out structure, and a second level molding and fan out structure between the first and third levels. The second level molding and fan out structure includes back-to-back facing die, with a front surface of each die bonded to a redistribution layer. 1. A vertical stack system in package (SiP) comprising:a pair of first level die encapsulated in a first level molding compound;a first redistribution layer (RDL) on the encapsulated pair of first level die;a second level die stack including a pair of back-to-back stacked die on the first RDL and encapsulated in a second level molding compound;a second RDL on the encapsulated second level die stack;a third level die on the second RDL and encapsulated in a third level molding compound, wherein the third level die is back facing toward the second RDL; anda third RDL on the encapsulated third level die;wherein each of the first level die is a first type of die and each of the back-to-back stacked die are a second type of die that is different than the first type of die, and each of the back-to-back stacked die have larger x-y dimensions than each of the first level die.2. The vertical stack SiP of claim 1 , wherein the third RDL is directly on a stud bump of the third level die.3. The vertical stack SiP of claim 1 , wherein the third RDL is directly on a contact pad of the third level die.4. The vertical stack SiP of claim 1 , wherein the third level die is attached to the second RDL with a die attach film.5. The vertical stack SiP of claim 1 , wherein each of the first level die is front facing toward the first RDL and the first RDL is directly on a conductive bump for each of the first level die.6. The vertical stack SiP of claim 1 , wherein the pair of back-to-back stacked die includes a first-second level die bonded to the first RDL claim 1 , and a ...

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Номер записи: 65
09-05-2019 дата публикации

PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

Номер: US20190139924A1
Автор: Chen Wei-Chih, Hu Yu-Hsiang, Kuo Hung-Jui, LIAO SIH-HAO, Wang Po-Han
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die have a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars. 1. A package structure , comprising:at least one semiconductor die having a first surface and a second surface opposite to the first surface;an insulating encapsulant encapsulating the at least one semiconductor die;an insulating layer disposed on the first surface of the at least one semiconductor die and on the insulating encapsulant;conductive pillars, located on the at least one semiconductor die and inlaid in the insulating layer;at least one dummy pillar, located on the insulating encapsulant and inlaid in the insulating layer;a first seed layer embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the at least one semiconductor die, and is located in between the at least one dummy pillar and the insulating encapsulant; anda redistribution layer disposed over the insulating layer, wherein the redistribution layer is electrically connected to the at least one semiconductor die through the conductive pillars.2. The package structure according ...

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Номер записи: 66
30-04-2020 дата публикации

SEMICONDUCTOR PACKAGE AND ANTENNA MODULE COMPRISING THE SAME

Номер: US20200135654A1
Автор: KANG Myung Sam, Ko Young Chan, KO Young Gwan, Lee Chang Bae, LEE Yong Koon
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor package includes a core structure having a first through-hole and including a frame having an opening, a passive component disposed in the opening, a first encapsulant covering the frame and the passive component, a first metal layer disposed on an inner surface of the first through-hole, and a second metal layer disposed on an inner surface of the opening; a first semiconductor chip disposed in the first through-hole and having a first connection pad; a second encapsulant covering the core structure and the first semiconductor chip; a connection structure disposed on the core structure and the first semiconductor chip and including a redistribution layer; and a metal pattern layer disposed on the second encapsulant. The first and second metal layers are connected to the metal pattern layer through first and second metal vias having heights different from each other. 1. A semiconductor package comprising:a core structure having a first through-hole, the core structure including a frame having an opening, a passive component disposed in the opening, a first encapsulant covering at least a portion of each of the frame and the passive component and filling at least a portion of the opening, a first metal layer disposed on an inner surface of the first through-hole, and a second metal layer disposed on an inner surface of the opening;a first semiconductor chip disposed in the first through-hole, the first semiconductor chip having a first active surface on which a first connection pad is disposed, and a first inactive surface opposite to the first active surface;a second encapsulant covering at least a portion of each of the core structure and the first semiconductor chip, and filling at least a portion of the first through-hole;a connection structure disposed on the core structure and the first active surface, and including a redistribution layer electrically connected to the first connection pad and the passive component; anda metal pattern layer ...

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Номер записи: 67
08-09-2022 дата публикации

Component Carrier Comprising at Least Two Components

Номер: US20220287181A1
Автор: Baftiri Artan, WILDING Dominik
Принадлежит:

A component carrier includes a stack with at least one electrically conductive layer structure and a plurality of electrically insulating layer structure, a first component, a second component, a central core in which both the first component and the second component are embedded. A first electrically insulating structure encapsulates the first component. A second electrically insulating structure encapsulates the second component. The first component and the second component are electrically connected to an external electrically conductive structure through at least one electrically conductive contact passing through the first electrically insulating structure and/or the second electrically insulating structure. 1. A component carrier , comprising:a stack comprising at least one electrically conductive layer structure and a plurality of electrically insulating layer structure;a first component;a second component;a central core in which both the first component and the second component are embedded;a first electrically insulating structure encapsulating the first component;a second electrically insulating structure encapsulating the second component;wherein the first component and the second component are electrically connected to an external electrically conductive structure through at least one electrically conductive contact passing through the first electrically insulating structure and/or the second electrically insulating structure.2. The component carrier according to claim 1 , wherein at least one of the first and the second components comprises at least one pad provided on a first main surface of the first or second component claim 1 , the at least one pad being electrically connected to the external electrically conductive structure and passes through the first electrically insulating structure and/or the second electrically insulating structure.3. The component carrier according claim 1 , wherein at least one of the first and the second components ...

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Номер записи: 68
10-06-2021 дата публикации

Interconnect Structure for High Power GaN Module

Номер: US20210175195A1
Автор: Chen Jie, KIM Woochan, Murugan Rajen Manicon, XIE YONG
Принадлежит:

In described examples of a circuit module, a multilayer substrate has a conductive pad formed on a surface of the multilayer substrate. An integrated circuit (IC) die is bonded to the surface of the substrate in dead bug manner, such that a set of bond pads formed on a surface of the IC die are exposed. A planar interconnect line formed by printed ink couples the set of bond pads to the conductive pad. 1. A circuit module comprising:a multilayer substrate having a first surface and an opposite second surface;a conductive pad formed within one of the layers of the multilayer substrate;an integrated circuit (IC) die having a first surface and an opposite second surface, the IC die having a semiconductor device formed therein, the semiconductor device having a set of bond pads formed on the first surface of the IC die, the second surface of the IC die being bonded to the first surface of the multilayer substrate; anda printed ink planar interconnect line coupled to the set of bond pads and to the conductive pad.2. The module of claim 1 , further comprising a second conductive pad formed within a second one of the layers of the multilayer substrate;wherein the set of bond pads is a first set of bond pads and the semiconductor device has a second set of bond pads formed on the first surface of the IC die; anda second printed ink planar interconnect line coupled to the second set of bond pads and to the second conductive pad.3. The module of claim 1 , wherein the printed ink includes copper particles.4. The module of claim 1 , wherein the printed ink includes silver or gold particles.5. The module of claim 1 , wherein a heat dispersing layer of the multilayer substrate forms the second surface of the multilayer substrate.6. The module of claim 1 , wherein the semiconductor device is a GaN FET.7. The module of claim 1 , further comprising:a second IC die mounted to the first surface of the multilayer substrate;at least one passive component coupled to the first surface of ...

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Номер записи: 69
15-09-2022 дата публикации

LIGHT EMITTING DIODE DISPLAY WITH REDUNDANCY SCHEME

Номер: US20220293876A1
Автор: Bibl Andreas, Griggs Charles R., Perkins James Michael, Sakariya Kapil V.
Принадлежит:

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities. 1. A display panel redundancy scheme comprising:a display substrate;a first micro light emitting diode (LED) and a second LED arranged within a subpixel;wherein the first micro LED and the second micro LED each comprises a p-n diode, a top conductive contact, and a bottom conductive contact that is bonded to the display substrate;a passivation material over the second micro LED; anda top electrode layer over the first micro LED and the second micro LED, wherein the top electrode layer is in electrical contact with the first micro LED and the passivation material physically separates the top electrode layer from the second micro LED.2. The display panel of claim 1 , wherein each of the first micro LED and the second micro LED has a maximum width of 1 to 100 μm.3. The display panel of claim 2 , wherein the top electrode layer is formed of a material selected from the group consisting of a transparent conductive oxide and a transparent conducting polymer.4. The display panel of claim 2 , further comprising a Vss tie line.5. The display panel of claim 4 , wherein the top electrode layer is in electrical contact with the Vss tie line.6. The display panel of claim 5 , further comprising a passivation layer covering sidewalls of the first micro LED and the second micro LED claim 5 , and the top electrode layer spans over a top surface of the passivation layer.7. The display panel of ...

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Номер записи: 70
07-05-2020 дата публикации

Chip packaging structure and manufacturing method thereof

Номер: US20200144179A1
Автор: Chien-Chou Chen, Chun-Hsien Chien, Wei-Ti Lin, Wen-Liang Yeh
Принадлежит: Unimicron Technology Corp

A chip packaging structure includes a circuit redistribution structure, a chip, a sealing layer, and an antenna pattern. The circuit redistribution structure includes a first and a second circuit layer, and a conductive pad. The second circuit layer is disposed on and electrically connected to the first circuit layer. The conductive pad is electrically connected to the second circuit layer. The chip is disposed on the circuit redistribution structure and electrically connected to the second circuit layer. The sealing layer having an opening and a groove covers the chip and the circuit redistribution structure. The opening exposes the conductive pad. A portion of the groove communicates with the opening. The antenna pattern includes a first and a second portion. The first portion covers sidewalls of the opening and is electrically connected to the conductive pad. The second portion is filled in the groove and electrically connected to the first portion.

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Номер записи: 71
07-05-2020 дата публикации

Semiconductor device structure and method for manufacturing the same

Номер: US20200144244A1
Автор: Cheng-Ying Ho, Dun-Nian Yaung, Jen-Cheng Liu, Wen-De Wang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device structure includes a first chip, second chip, a first metal structure, a second metal structure, a first via structure and a second via structure. The first chip includes n inter metal dielectric (IMD) layer, which includes different materials adjacent to generate a number of staggered portions having a zigzag configuration. The second chip bonded to the first chip generates a bonding interface. The first metal structure is disposed in the first chip and between the staggered portions and the bonding interface. The first via structure in the first chip stops at the first metal structure. The first via structure includes a first via metal and a first via dielectric layer. A surface roughness of the staggered portions is substantially greater than a surface roughness of the first via dielectric layer. The second via structure extends from the first via structure to the second metal structure.

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Номер записи: 72
11-06-2015 дата публикации

CONNECTING TECHNIQUES FOR STACKED CMOS DEVICES

Номер: US20150162295A1
Автор: Chen Wei-yu, CHIANG Ting-Wei, TIEN Li-Chun, Tseng Hsiang-Jen
Принадлежит:

A stacked integrated circuit includes multiple tiers vertically connecting together. A multi-layer horizontal connecting structure is fabricated inside a substrate of a tier. Layers of the horizontal connecting structure have different patterns as viewed from above the substrate. 1. A semiconductor integrated circuit (IC) , comprising:a first device tier with an first inter-tier horizontal interconnecting structure inside a first substrate, anda second device tier being electrically connected to the first device tier by the first inter-tier horizontal interconnecting structure,wherein the first inter-tier horizontal interconnecting structure comprises a first conductive layer and a second conductive layer with different patterns.2. The IC of claim 1 , wherein the first inter-tier horizontal interconnecting structure comprises:a first vertical connection element disposed in the first substrate and electrically coupled to a device of the second device tier, anda first horizontal layer disposed in the first substrate above the first vertical connection element,wherein the first horizontal layer is electrically coupled to the device of the second device tier through the first vertical connection element.3. The IC of claim 2 , wherein the second device tier further comprises an electrical interconnect structure arranged over the device of the second device tier claim 2 , the electrical interconnect structure having an upper surface to which the first vertical connection element is coupled.4. The IC of claim 1 , wherein the first inter-tier horizontal interconnecting structure comprises claim 1 ,a first vertical connection element disposed in the first substrate and electrically coupled to a device of the second device tier,a first horizontal layer disposed in the first substrate above the first vertical connection element, anda second horizontal layer disposed in the first substrate above the first horizontal layer and being electrically coupled to the first device ...

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Номер записи: 73
23-05-2019 дата публикации

Three-step Etching to Form RDL

Номер: US20190157240A1
Автор: Chang Tai-Min, Hsieh Yun Chen, Kuo Hung-Jui, Lei Yi-Yang, Peng Jyun-Siang, Tsai Hui-Jung, Yu Chen-Hua
Принадлежит:

A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region. 1. A method comprising:encapsulating a device in an encapsulating material;planarizing the encapsulating material and the device; and depositing a first conductive material to from a first seed layer;', 'depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer;', 'plating a metal region over the second seed layer;', 'performing a first etching on the second seed layer;', 'performing a second etching on the first seed layer; and', 'after the first seed layer is etched, performing a third etching on the second seed layer and the metal region., 'forming a conductive feature over the encapsulating material and the device, wherein the forming the conductive feature comprises2. The method of claim 1 , wherein the first seed layer comprises titanium claim 1 , tantalum claim 1 , titanium nitride claim 1 , or tantalum nitride claim 1 , and the second seed layer and the metal region each comprise copper.3. The method of claim 1 , wherein the third etching comprises a wet etching.4. The method of claim 1 , wherein undercuts are generated by the second etching claim 1 , and the third etching eliminates the undercuts.5. The method of claim 1 , wherein the conductive feature ...

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Номер записи: 74
14-06-2018 дата публикации

Wafer level chip-on-chip semiconductor structure

Номер: US20180166417A1
Автор: Po-Chun Lin
Принадлежит: Nanya Technology Corp

A semiconductor structure includes a first semiconductor device; at least one conductive member disposed over the first semiconductor device; a second semiconductor device disposed over the first semiconductor device; a molding member disposed over the first semiconductor device; and a redistribution layer (RDL) disposed over the second semiconductor device and the at least one conductive member. The molding member surrounds the second semiconductor device and the at least one conductive member. The molding member does not extend into an interface between the first semiconductor device and the second semiconductor device.

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Номер записи: 75
21-05-2020 дата публикации

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MAKING THE SAME

Номер: US20200161234A1
Автор: HSU CHE-WEI, HSU SHIH-PING, Tseng Chao-Tsung
Принадлежит:

A semiconductor package structure includes a chip, a conductive pillar, a dielectric layer, a first patterned conductive layer and a second patterned conductive layer. The chip has a first side with at least a first metal electrode pad and a second side with at least a second metal electrode pad. The conductive pillar, which has a first end and a second end, is disposed adjacent to the chip. The axis direction of the conductive pillar is parallel to the height direction of the chip. The dielectric layer covers the chip and the conductive pillar and exposes the first and second metal electrode pads of the chip and the first and second ends of the conductive pillar. The first patterned conductive layer is disposed on a second surface of the dielectric layer and electrically connected between the second metal electrode pad and the second end of the conductive pillar. The second patterned conductive layer is disposed on a first surface of the dielectric layer and electrically connected between the first metal electrode pad and the first end of the conductive pillar. 1. A semiconductor package structure , comprising:a chip having a first side and a second side, with the first side having at least a first metal electrode pad and the second side having at least a second metal electrode pad;at least a conductive pillar having a first end and a second end, with the conductive pillar is disposed adjacent to the chip, and an axis direction of the conductive pillar is parallel to a height direction of the chip;a dielectric layer, which covers the chip and the conductive pillar, and at least exposes the first and second metal electrode pads of the chip and the first and second ends of the conductive pillar;a first patterned conductive layer, which is disposed on a second surface of the dielectric layer and electrically connected between the second metal electrode pad and the second end of the conductive pillar; anda second patterned conductive layer, which is disposed on a first ...

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Номер записи: 76
21-05-2020 дата публикации

CAMERA ASSEMBLY AND PACKAGING METHOD THEREOF, LENS MODULE, AND ELECTRONIC DEVICE

Номер: US20200161289A1
Автор: Chen Da, LIU Mengbin
Принадлежит:

The present disclosure provides a method for packaging a camera assembly. The method includes: providing a photosensitive chip; mounting an optical filter on the photosensitive chip; temporarily bonding the photosensitive chip and functional components on a carrier substrate, where the photosensitive chip has soldering pads facing away from the carrier substrate and the functional components have soldering pads facing toward the carrier substrate; forming an encapsulation layer covering the carrier substrate, the photosensitive chip, and the functional components, and exposing the optical filter; after the encapsulation layer is formed, removing the carrier substrate; and after the carrier substrate is removed, forming a redistribution layer structure on a side of the encapsulation layer facing away from the optical filter to electrically connect the soldering pads of the photosensitive chip with the soldering pads of the functional components. 1. A method for packaging a camera assembly , comprising:providing a photosensitive chip;mounting an optical filter on the photosensitive chip;temporarily bonding the photosensitive chip and functional components on a carrier substrate, wherein the photosensitive chip has soldering pads facing away from the carrier substrate and the functional components have soldering pads facing toward the carrier substrate;forming an encapsulation layer covering the carrier substrate, the photosensitive chip, and the functional components, and exposing the optical filter;after the encapsulation layer is formed, removing the carrier substrate; andafter the carrier substrate is removed, forming a redistribution layer structure on a side of the encapsulation layer facing away from the optical filter to electrically connect the soldering pads of the photosensitive chip with the soldering pads of the functional components.2. The method according to claim 1 , wherein forming the redistribution layer structure includes:forming conductive posts in ...

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Номер записи: 77
01-07-2021 дата публикации

Arrangement With Central Carrier And Two Opposing Layer Stacks, Component Carrier and Manufacturing Method

Номер: US20210202427A1
Автор: Mikael Tuominen, Nick Xin, Seok Kim Tay
Принадлежит: AT&S China Co Ltd

An arrangement, a method of manufacturing component carriers and a component carrier are provided. The arrangement includes a central carrier structure having a front side and a back side, a first layer stack having a first surface structure made of another material than the interior of the first layer stack and covered by a first release layer which is attached to the front side, and a second layer stack covered by a second release layer which is attached to the back side.

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Номер записи: 78
01-07-2021 дата публикации

Method for Producing Conductive Tracks, and Electronic Module

Номер: US20210202434A1
Автор: CASSIGNOL Caroline, Hensel Alexander, Pecanac Dulijano, Raab Oliver, Stegmeier Stefan, Weisbrod Erik
Принадлежит: SIEMENS AKTIENGESELLSCHAFT

Various embodiments include a method for producing a least one conductive track comprising: forming a surface with a thermoplastic; and depositing conductive track material on the surface by thermal spraying. 1. A method for producing a least one conductive track , the method comprising:forming a surface with a thermoplastic; anddepositing conductive track material on the surface by thermal spraying.2. The method as claimed in claim 1 , wherein the conductive track material comprises a material converted into an electrically conductive material by heating or irradiation.3. (canceled)4. The method as claimed in claim 1 , further comprising producing the surface using a coating.5. The method as claimed in claim 1 , wherein the thermoplastic comprises at least one material selected from the group consisting of: polyamide-imide claim 1 , polyimide claim 1 , polyarylether claim 1 , BMI claim 1 , polyamide claim 1 , functionalized polyamides claim 1 , polyether ether ketone (PEEK) claim 1 , and PES.6. The method as claimed in claim 1 , further comprising constructing the conductive track using a stencil and/or a thermosetting plastic.7. The method as claimed in claim 1 , wherein the thermal spraying comprises spraying particles at a temperature of at least 800 degrees Celsius and/or particles having an oxide proportion of at most 10 percent and/or particles having a velocity of at most 700 m/s.8. The method as claimed in claim 1 , wherein the particles comprise at least one element selected from the group consisting of: copper claim 1 , silver claim 1 , gold claim 1 , aluminum claim 1 , nickel claim 1 , and tin.9. The method as claimed in claim 1 , wherein the conductive track material is deposited at least regionally as a layer having a layer thickness of at least 10 micrometers.10. The method as claimed in claim 1 , wherein the conductive track is part of an electronic module.11. An electronic module comprising:a surface formed by a thermoplastic; anda thermally sprayed ...

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Номер записи: 79
21-06-2018 дата публикации

Fan-out semiconductor package

Номер: US20180174974A1
Автор: Dae Hyun Park, Han Kim, Hyung Joon Kim, Jung Ho Shim
Принадлежит: Samsung Electro Mechanics Co Ltd

The present disclosure relates to a fan-out semiconductor package in which a plurality of semiconductor chips are stacked and packaged, and are disposed in a special form to be thus electrically connected to a redistribution layer of a connection member through vias rather than wires. The fan-out semiconductor package can further include a connection member having a through-hole, and at least one of the semiconductor chips can be disposed in the through-hole.

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Номер записи: 80
08-07-2021 дата публикации

Package structure and method of manufacturing the same

Номер: US20210210464A1
Автор: Chi-Yang Yu, Chien-Hsun Lee, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min LIANG
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A package structure and a method of forming the same are provided. The package structure includes a first die and a second die, a first encapsulant, a second encapsulant and a RDL structure. The first die includes a first connector and a first protection layer covering sidewalls of the first connector, and the second die includes a second connector. The first encapsulant is at least disposed laterally between the first die and the second die to encapsulate first sidewalls of the first die and the second die that faces each other. The second encapsulant encapsulates second sidewalls of the first die and the second die. The RDL structure is disposed on and electrically connected to the first die and the second die. The top surfaces of the first protection layer, the first encapsulant, and the second encapsulant are in contact with a bottom surface of the RDL structure.

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Номер записи: 81
08-07-2021 дата публикации

Flexible device including conductive traces with enhanced stretchability

Номер: US20210212216A1
Автор: Ankit Mahajan, Benjamin R. COONCE, Chad M. AMB, Jeremy K. Larsen, Jessica Chiu, Jonathan W. Kemling, Kara A. MEYERS, Lyudmila A. Pekurovsky, Mikhail L. Pekurovsky, Richard J. Pokorny, Saagar Shah, Teresa M. GOEDDEL, Thomas J. METZLER, Thomas P. Klun
Принадлежит: 3M Innovative Properties Co

Flexible devices including conductive traces with enhanced stretchability, and methods of making and using the same are provided. The circuit die is disposed on a flexible substrate. Electrically conductive traces are formed in channels on the flexible substrate to electrically contact with contact pads of the circuit die. A first polymer liquid flows in the channels to cover a free surface of the traces. The circuit die can also be surrounded by a curing product of a second polymer liquid.

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Номер записи: 82
04-06-2020 дата публикации

Redistribution Layers in Semiconductor Packages and Methods of Forming Same

Номер: US20200176432A1
Автор: An-Jhih Su, Chen-Hua Yu, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien HUANG
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An embodiment package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, a conductive line electrically connecting a first conductive via to a second conductive via, the conductive line including a first segment over the first integrated circuit die and having a first width, and a second segment over the first integrated circuit die having a second width larger than the first width, the second segment extending over a first boundary between the first integrated circuit die and the encapsulant.

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Номер записи: 83
04-06-2020 дата публикации

Cavity structures

Номер: US20200176671A1
Автор: Alexandre Chikhaoui, António José Marques Trindade, Raja Fazan Gul, Robert R. Rotzoll, Ronald S. Cok
Принадлежит: X Display Company Technology Ltd

A cavity structure comprises a cavity substrate comprising a substrate surface, one or more cavity walls extending from the substrate surface, a cap disposed on the one or more cavity walls, and at least a portion of a module tether physically attached to the cavity substrate. The cavity substrate, the cap, and the one or more cavity walls form a cavity enclosing a volume, for example enclosing a vacuum, air, an added gas, or a liquid. The cavity structure can be a micro-transfer printable structure provided on a cavity structure source wafer. A plurality of cavity structures can be disposed on a destination substrate, for example by transfer printing, dry contact printing, or micro-transfer printing.

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Номер записи: 84
15-07-2021 дата публикации

Semiconductor devices including thick pad

Номер: US20210217720A1
Автор: Daehee Lee, Hyunchul Jung, Taeho Ko
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device may include a semiconductor chip in an encapsulant. A first insulation layer may be disposed on the encapsulant and the semiconductor chip. A horizontal wiring and a primary pad may be disposed on the first insulation layer. A secondary pad may be disposed on the primary pad. A second insulation layer covering the horizontal wiring may be disposed on the first insulation layer. A solder ball may be disposed on the primary pad and the secondary pad. The primary pad may have substantially the same thickness as a thickness of the horizontal wiring.

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Номер записи: 85
18-06-2020 дата публикации

ELECTRONIC DEVICE INCLUDING ELECTRICAL CONNECTIONS ON AN ENCAPSULATION BLOCK

Номер: US20200194397A1
Автор: Coffy Romain, Laurent Patrick, SCHWARTZ Laurent
Принадлежит:

An integrated circuit chip includes a front face having an electrical connection pad. An overmolded encapsulation block encapsulates the integrated circuit chip and includes a front layer at least partially covering a front face of the integrated circuit chip. A through-hole the encapsulation block is located above the electrical connection pad of the integrated circuit chip. A wall of the through-hole is covered with an inner metal layer that is joined to the front pad of the integrated circuit chip. A front metal layer covers a local zone of the front face of the front layer, with the front metal layer being joined to the inner metal layer to form an electrical connection. The inner metal layer and the front metal layer are attached or anchored to activated additive particles that are included in the material of the encapsulation block. 1. An electronic device , comprising:an integrated circuit chip having a front face provided with an electrical connection pad; andan overmolded encapsulation block for encapsulating the integrated circuit chip, the overmolded encapsulation block comprising a front layer at least partially covering the front face of the integrated circuit chip,wherein the overmolded encapsulation block comprises a plastic material containing additive particles in the form of active metal grains;wherein the overmolded encapsulation block includes a through-hole located above the electrical connection pad of the integrated circuit chip;an inner metal layer covering a wall of the through-hole, wherein the inner metal layer is joined to the electrical connection pad of the integrated circuit chip and attached or anchored to the additive particles at the wall; anda local front metal layer on a local zone of the front face of the overmolded encapsulation block, said local zone extending adjacent to the through-hole, wherein the local front metal layer is joined to the inner metal layer and is attached or anchored to the additive particles at the local ...

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Номер записи: 86
06-08-2015 дата публикации

Semiconductor device with reduced thickness

Номер: US20150221586A1
Автор: Doo Hyun Park, Jong Sik Paek
Принадлежит: Amkor Technology Inc

A semiconductor device with reduced thickness is disclosed and may include forming a back end of line (BEOL) comprising a redistribution layer on a dummy substrate. A first semiconductor die may be bonded to a first surface of the BEOL and a second semiconductor die may be bonded to the first semiconductor die. The first and second semiconductor dies may be electrically coupled to the BEOL. The first and second semiconductor dies and the BEOL may be encapsulated utilizing a first encapsulant. The dummy substrate may be removed thereby exposing a second surface of the BEOL opposite to the first surface. A solder ball may be placed on the exposed second surface of the BEOL. The second semiconductor may be stacked stepwise on the first semiconductor and may be flip-chip bonded. The semiconductor dies may be electrically coupled to the BEOL utilizing a lateral plating layer or conductive wires.

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Номер записи: 87
25-06-2020 дата публикации

CHIP PACKAGING METHOD AND CHIP STRUCTURE

Номер: US20200203302A1
Автор: CHEW JIMMY
Принадлежит:

The present disclosure provides a chip packaging method and a chip structure. The chip packaging method comprises: providing a wafer, and forming a protective layer on a wafer active surface of the wafer; cutting and separating the wafer to form a die; providing a metal structure, the metal structure including at least one metal unit; adhering the die and the metal structure onto a carrier; and forming a molding layer. The chip structure comprises: at least one die; a protective layer; a metal unit, the metal unit including at least one metal feature; and a molding layer, encapsulating the at least one die and the metal unit, and the chip structure is connected with an external circuit through the at least one metal feature. By adopting a plurality of metal features of the metal unit, the present disclosure achieves improved packaging performance brought by different metal features; and the wafer active surface is provided with the protective layer in the present disclosure, so that a step of applying an insulating layer after the formation of the molding layer is omitted. 1. A chip structure , comprising:at least one die;a protective layer;a metal unit, the metal unit including at least one metal feature; anda molding layer, encapsulating the at least one die and the metal unit, wherein the chip structure is connected with an external circuit via the at least one metal feature.2. The chip structure according to claim 1 , wherein the chip structure further comprises a conductive structure claim 1 , and the at least one metal feature of the metal unit is connected with the at least one die via the conductive structure.3. The chip structure according to claim 2 , whereinthe conductive structure comprises conductive filled vias and a panel-level conductive layer;the conductive filled vias are provided by filling protective layer openings with a conductive material, and the protective layer openings are provided in the protective layer;at least one of the conductive ...

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Номер записи: 88
05-08-2021 дата публикации

SEMICONDUCTOR PACKAGES USING PACKAGE IN PACKAGE SYSTEMS AND RELATED METHODS

Номер: US20210242167A1
Автор: EOM JooYang, ESTACIO Maria Cristina, IM Seungwon, Teysseyre Jerome, YOO Inpil
Принадлежит: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Implementations of a semiconductor package may include two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes; a first interconnect layer coupled at a source of each of the two more die; a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; and an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer. 1. A semiconductor package comprising:two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes;a first interconnect layer coupled at a source of each of the two more die;a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; andan encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer.2. The package of claim 1 , wherein the encapsulant encapsulates a portion of the gate package contact.3. The package of claim 1 , wherein each metal layer and the gate package contact are configured to couple with a substrate.4. The package of claim 1 , wherein the first interconnect layer is configured to couple with a clip and electrically coupled with a substrate through the clip.5. The package of claim 1 , wherein the second interconnect layer is configured to couple with a clip.6. The package of claim 1 , wherein the two or more die are power semiconductor die.7. The package of claim 1 , wherein the two or more die comprise silicon carbide.8. The package of claim 1 , further comprising a leadframe where the first interconnect layer claim 1 , the second interconnect layer claim 1 , ...

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Номер записи: 89
04-08-2016 дата публикации

Electrode connection structure and electrode connection method

Номер: US20160225730A1
Автор: Kohei Tatsumi
Принадлежит: WASEDA UNIVERSITY

An electrode connection structure includes: a first electrode of an electrical circuit; and a second electrode of the electrical circuit that is electrically connected to the first electrode. The first and second electrodes are oppositely disposed in direct or indirect contact with each other. A plated lamination is substantially uniformly formed by plating process from a surface of a contact region and opposed surfaces of the first and second electrodes. A void near the surface of the contact region is filled by formation of the plated lamination. Portions of the plated lamination formed from the opposed surfaces of the first and second electrodes in a region other than the contact region are not joined together.

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Номер записи: 90
02-08-2018 дата публикации

METHOD FOR PRODUCING A COMPONENT AND COMPONENT

Номер: US20180219145A1
Автор: Unterburger Martin
Принадлежит:

A method for producing a component having a semiconductor body includes providing the semiconductor body including a radiation passage surface and a rear side facing away from the radiation passage surface, wherein the semiconductor body comprises on the rear side a connection location for the electrical contacting of the semiconductor body, providing a composite carrier including a carrier layer and a partly cured connecting layer, applying the semiconductor body on the composite carrier, such that the connection location penetrates into the partly cured connecting layer, curing the connecting layer to form a solid composite, applying a molded body material on the composite carrier after curing the connecting layer, wherein the molded body covers side surfaces of the semiconductor body, forming a cutout through the carrier layer and the connecting layer in order to expose the connection location, and filling the cutout with an electrically conductive material. 1. A method for producing a component comprising a semiconductor body , the method comprising:a) providing the semiconductor body comprising a radiation passage surface and a rear side facing away from the radiation passage surface, wherein the semiconductor body comprises on the rear side a connection location for the electrical contacting of the semiconductor body,b) providing a composite carrier comprising a carrier layer and a partly cured connecting layer applied on the carrier layer,c) applying the semiconductor body on the composite carrier, such that the connection location penetrates into the partly cured connecting layer,d) curing the connecting layer in order to form a solid composite comprising the semiconductor body and the composite carrier,e) applying a molded body material on the composite carrier in order to form a molded body after curing the connecting layer, wherein the molded body covers side surfaces of the semiconductor body,f) forming a cutout through the carrier layer and the ...

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Номер записи: 91
02-07-2020 дата публикации

Methods of making printed structures

Номер: US20200214141A1
Автор: Brook Raymond, Christopher Andrew Bower, Matthew Alexander Meitl, Salvatore Bonafede
Принадлежит: X Display Company Technology Ltd

An example of a method of making a printed structure comprises providing a destination substrate, contact pads disposed on the destination substrate, and a layer of adhesive disposed on the destination substrate. A stamp with a component adhered to the stamp is provided. The component comprises a stamp side in contact with the stamp and a post side opposite the stamp side, a circuit, and connection posts extending from the post side. Each of the connection posts is electrically connected to the circuit. The component is pressed into contact with the adhesive layer to adhere the component to the destination substrate and to form a printed structure having a volume defined between the component and the destination substrate. The stamp is removed and the printed structure is processed to fill or reduce the volume.

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Номер записи: 92
19-08-2021 дата публикации

LIGHT EMITTING DIODE DISPLAY WITH REDUNDANCY SCHEME

Номер: US20210257572A1
Автор: Bibl Andreas, Griggs Charles R., Perkins James Michael, Sakariya Kapil V.
Принадлежит:

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities. 1. (canceled)2. A display panel redundancy scheme comprising:an array of micro controller chips;an array of micro light emitting diode (LED) pairs connected with the array of micro controller chips in an array of pixel areas;wherein each pixel area includes a micro controller chip connected to a corresponding group of micro LED pairs arranged in a plurality of subpixels; andwherein the group of micro LED pairs includes a group of primary micro LEDs arranged in the plurality of subpixels, and a group of redundant micro LEDs arranged in the plurality of subpixels such that each subpixel includes a micro LED pair.3. The display panel of claim 2 , wherein each pixel area includes a first subpixel claim 2 , a second subpixel claim 2 , and a third subpixel.4. The display panel of claim 3 , wherein:each first subpixel includes a first primary micro LED and a first redundant micro LED to emit a first primary color emission;each second subpixel includes a second primary micro LED and a second redundant micro LED to emit a second primary color emission;each third subpixel includes a third primary micro LED and a third redundant micro LED to emit a third primary color emission; andwherein the first, second and third primary color emissions are different from one another.5. The display panel of claim 2 , wherein each primary micro LED and each redundant micro LED is a separate device that has ...

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Номер записи: 93
18-08-2016 дата публикации

Semiconductor Package with Multi-Section Conductive Carrier

Номер: US20160240461A1
Автор: Eung San Cho
Принадлежит: Infineon Technologies North America Corp

In one implementation, a power semiconductor package includes a non-contiguous, multi-section conductive carrier. A control transistor with a control transistor terminal is coupled to a first section of the multi-section conductive carrier, while a sync transistor with a sync transistor terminal is coupled to a second section of the multi-section conductive carrier. The first and second sections of the multi-section conductive carrier sink heat generated by the control and sync transistors. The first and second sections of the multi-section conductive carrier are electrically connected only through a mounting surface attached to the power semiconductor package. Another implementation of the power semiconductor package includes a driver IC coupled to a third section of the multi-section conductive carrier. A method for fabricating the power semiconductor package is also disclosed. The power semiconductor package according to the present disclosure results in effective thermal protection, current carrying capability, and a relatively small size.

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Номер записи: 94
10-09-2015 дата публикации

Semiconductor Package with Conductive Clip

Номер: US20150255382A1
Автор: Martin Standing
Принадлежит: International Rectifier Corp USA

A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.

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Номер записи: 95
09-09-2021 дата публикации

Semiconductor Device and Method

Номер: US20210281037A1
Автор: An-Jhih Su, Chen-Hua Yu, Chia-Nan Yuan, Der-Chyang Yeh, Ming Shih Yeh, Shih-Guo Shen, Yu-Hung Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

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Номер записи: 96
30-07-2020 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20200243406A1
Автор: Che Wei Chang, Chi-Yu Wang, Yuan-Ting Lin
Принадлежит: Advanced Semiconductor Engineering Inc

A semiconductor device includes a first semiconductor die, a second semiconductor die, a dielectric layer, a first redistribution layer and a second redistribution layer. The first semiconductor die includes a first bonding pad and a second bonding pad. The second semiconductor die includes a third bonding pad and a fourth bonding pad. The dielectric layer covers the first semiconductor die and the second semiconductor die, and defines a first opening exposing the first bonding pad and the second bonding pad and a second opening exposing the third bonding pad and the fourth bonding pad. The first redistribution layer is disposed on the dielectric layer, and electrically connects the first bonding pad and the third bonding pad. The second redistribution layer is disposed on the dielectric layer, and electrically connects the second bonding pad and the fourth bonding pad.

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Номер записи: 97
14-10-2021 дата публикации

Electronic module

Номер: US20210321520A1
Автор: Petteri Palm, Risto Tuominen
Принадлежит: Imberatek LLC

The present invention relates to an electronic module. In particular, to an electronic module which includes one or more components embedded in an installation base. The electronic module can be a module like a circuit board, which includes several components, which are connected to each other electrically, through conducting structures manufactured in the module. The components can be passive components, microcircuits, semiconductor components, or other similar components. Components that are typically connected to a circuit board form one group of components. Another important group of components are components that are typically packaged for connection to a circuit board. The electronic modules to which the invention relates can, of course, also include other types of components.

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Номер записи: 98
13-09-2018 дата публикации

FABRICATION METHOD OF SEMICONDUCTOR PACKAGE WITH STACKED SEMICONDUCTOR CHIPS

Номер: US20180261563A1
Автор: Chen Lu-Yi
Принадлежит:

A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency. 126-. (canceled)27. A fabrication method of a semiconductor package , comprising the steps of:providing a carrier having opposite first and second surfaces, wherein a build-up structure is formed on the first surface of the carrier and has a plurality of conductive pads exposed from the a top surface thereof;disposing a first semiconductor chip on the build-up structure in a flip-chip manner, wherein the first semiconductor chip has a first active surface and a first non-active surface opposite to the first active surface, and the first active surface has a plurality of first electrode pads electrically connected to the conductive pads, respectively;thinning the first semiconductor chip from the first non-active surface thereof;forming a plurality of first through holes in the first semiconductor chip via the first non-active surface thereof;forming in the first through holes a plurality of first bumps electrically connected to the first electrode pads;disposing an electronic element on the first semiconductor chip for electrically connecting the electronic element to the first bumps; andforming on the build-up structure an encapsulant that encapsulates the first semiconductor chip and the electronic element.28. The fabrication method of claim 27 , wherein the first electrode pads are exposed through the first through holes claim 27 , respectively.29. The fabrication method of claim 27 , wherein a circuit layer that is electrically connected to the first electrode pads is exposed through the first through holes.30. The ...

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Номер записи: 99
01-10-2015 дата публикации

Semiconductor Device and Method of Forming RDL and Vertical Interconnect by Laser Direct Structuring

Номер: US20150279778A1
Автор: Bartholomew Liao, HeeJo Chi, Kelvin Dao, Sheila Marie L. Alvarez, Zigmund R. Camacho
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. An insulating layer is formed over the semiconductor die and encapsulant. A first channel including a first conductive surface is formed in the insulating layer by laser radiation. A laser-activated catalyst is infused in the insulating layer to form the first conductive surface in the first channel upon laser radiation. A vertical interconnect is formed through the encapsulant. A first conductive layer is formed in the first channel over the first conductive surface. A second channel including a second conductive surface is formed in the encapsulant by laser radiation. The catalyst is infused in the encapsulant to form the second conductive surface in the second channel upon laser radiation. A second conductive layer is formed in the second channel over the second conductive surface. An interconnect structure is formed over the first conductive layer.

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Номер записи: 100