METHOD FOR CHIP TO WAFER BONDING

METHOD FOR BONDING SUBSTRATES

The present invention relates to a method for bonding a first contact area (3) of a first, at least predominantly transparent substrate (1) to a second contact area (4) of a second, at least predominantly transparent substrate (2) wherein an oxide is used at at least one of the contact areas for bonding, from which oxide an at least predominantly transparent connecting layer (14) having: an electrical conductivity of at least 10e1 S/cm2 (measurement: four-point method, relative to temperature of 300K) and an optical transmittance of greater than 0.8 (for a wavelength range of 400 nm to 1500 nm) is formed at the first and second contact areas (3 4).

HIGH TEMPERATURE SOLDER, HIGH TEMPERATURE SOLDER PASTE MATERIAL AND POWER SEMICONDUCTOR EQUIPMENT USING THE SAME

PROBLEM TO BE SOLVED: To provide power semiconductor equipment using a high temperature lead-free solder material having excellent heat resistance at ≥280°C, joinability at ≤400°C, solder feedability and wettability, high temperature holding reliability and temperature cycle reliability. SOLUTION: The power semiconductor equipment is obtained by joining a semiconductor device and a metal electrode member with a high temperature solder material having a composition comprising Sn, Sb, Ag and Cu as the main constituting elements and satisfying 42 wt.%≤Sb/(Sn+Sb)≤48 wt.%, 5 wt.%≤Ag<20 wt.%, 3 wt.%≤Cu<10 wt.% and 5 wt.%≤Ag+Cu≤25 wt.%, and the balance other inevitable impurity elements. COPYRIGHT: (C)2007,JPO&INPIT ...

Power conversion device

FORMED TOP CONTACT FOR NON-FLAT SEMICONDUCTOR DEVICE SPACKAGE

내용 없음 No content

CHIP-ON-WAFER BONDING METHOD AND BONDING DEVICE, AND STRUCTURE COMPRISING CHIP AND WAFER

... [Problem] To provide a technique for efficiently bonding a chip to a wafer without leaving undesirable residue such as resin on the bonding interface, establishing electrical connections between the chip and wafer or among a plurality of layered chips, and increasing mechanical strength. [Solution] The method of the present invention for bonding a plurality of chips with chip-side bonding surfaces comprising metal regions to a substrate comprising a plurality of bonding sections is provided with the following steps: (S1) wherein the metal regions of the chip-side bonding surfaces are subjected to a surface activation treatment and a hydrophilization treatment; a step (S2) wherein the bonding sections of the substrate are subjected to a surface activation treatment and a hydrophilization treatment; a step (S3) wherein each of the plurality of chips, which have been subjected to the surface activation treatment and the hydrophilization treatment, is attached to the corresponding bonding section ...

SEMICONDUCTOR DEVICE

The surface on the mounting substrate side of a semiconductor element is layered with an ohmic contact layer contiguous to said surface, a metal diffusion barrier layer contiguous to the ohmic contact layer, a solder bond barrier layer contiguous to the metal diffusion barrier layer, and a bismuth-containing solder layer contiguous to the solder bond barrier layer. The bonding reliability of a semiconductor device formed by bonding a semiconductor element and a mounting substrate with a solder material having Bi as a main ingredient is improved.

METHOD OF MANUFACTURING POWER SEMICONDUCTOR DEVICE AND POWER SEMICONDUCTOR DEVICE

A metal mask is disposed on a copper base plate. A solder paste is introduced into each of a plurality of openings in the metal mask, to thereby form a pattern of the solder paste on each of copper plates of the copper base plate. A semiconductor element and a conductive component are placed on the respective patterns of the solder pastes. A metal mask is disposed on the copper base plate. Then, a solder paste is introduced into each of a plurality of openings in the metal mask, to thereby form a pattern of the solder paste covering each of the semiconductor element and the conductive component. A large-capacity relay board is disposed so as to come into contact with a corresponding pattern of the solder paste. A power semiconductor device is completed by performing heat treatment under a temperature condition of 200° C. or higher.

半導体装置接合材

SEMICONDUCTOR LASER MOUNTING FOR IMPROVED FREQUENCY STABILITY

A first contact surface ( 310 ) of a semiconductor laser chip ( 302 ) can be formed to a target surface roughness selected to have a maximum peak to valley height that is substantially smaller than a barrier layer thickness of a metallic barrier layer to be applied to the first contact surface ( 310 ). A metallic barrier layer having the barrier layer thickness can be applied to the first contact surface, and the semiconductor laser chip ( 302 ) can be soldered to a carrier mounting along the first contact surface ( 310 ) using a solder composition ( 306 ) by heating the soldering composition to less than a threshold temperature at which dissolution of the metallic barrier layer into the soldering composition occurs. Related systems, methods, articles of manufacture, and the like are also described.

Soldered joint and method for forming soldered joint

Provided are: a soldered joint which suppresses detachment between a back metal and a solder alloy during formation of the soldered joint, and which offers higher reliability by suppressing non-wetting of the solder alloy, splashing of molten solder, and breakage of an electronic component due to chip cracking; and a method for forming such a soldered joint. In this soldered joint, an electronic component equipped with a back metal is bonded to a substrate via a solder alloy. The solder alloy has: a solder alloy layer having an alloy composition comprising, in mass%, 2-4% of Ag, 0.6-2% of Cu, 9.0-12% of Sb, 0.005-1% of Ni with the remainder being Sn; a Sn-Sb intermetallic compound phase; a back metal-side intermetallic compound layer; and a substrate-side intermetallic compound layer. The solder alloy layer is interposed between the Sn-Sb intermetallic compound phase and the back metal-side intermetallic compound layer and/or between the Sn-Sb intermetallic compound phase and the substrate-side ...

SEMICONDUCTOR LASER MOUNTING FOR IMPROVED FREQUENCY STABILITY

A first contact surface ( 310 ) of a semiconductor laser chip ( 302 ) can be formed to a target surface roughness selected to have a maximum peak to valley height that is substantially smaller than a barrier layer thickness of a metallic barrier layer to be applied to the first contact surface ( 310 ). A metallic barrier layer having the barrier layer thickness can be applied to the first contact surface, and the semiconductor laser chip ( 302 ) can be soldered to a carrier mounting along the first contact surface ( 310 ) using a solder composition ( 306 ) by heating the soldering composition to less than a threshold temperature at which dissolution of the metallic barrier layer into the soldering composition occurs. Related systems, methods, articles of manufacture, and the like are also described.

SOLDERING A CONDUCTOR TO AN ALUMINUM METALLIZATION

A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material. 1. A method of soldering a conductor to an aluminum metallization , the method comprising:substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer;at least partly reducing a substitute metal oxide in the substitute metal oxide layer or in the substitute metal alloy oxide layer; andsoldering the conductor to the aluminum metallization using a solder material.2. The method of claim 1 , wherein a substitute metal of the substitute metal oxide layer is one of Zn claim 1 , Cr claim 1 , Cu claim 1 , Pb claim 1 , or Sn.3. The method of claim 2 , wherein substituting comprises depositing the substitute metal over the aluminum oxide layer by an electrochemical deposition process or by an electroless deposition process.4. The method of claim 1 , wherein a substitute metal alloy of the substitute metal alloy oxide layer comprises at least two of the elements Zn claim 1 , Cr claim 1 , V claim 1 , Cu claim 1 , Pb claim 1 , Sn and Mo.5. The method of claim 4 , wherein substituting comprises depositing the substitute metal alloy over the aluminum oxide layer by an electrochemical deposition process or by an electroless deposition process.6. The method of claim 1 , wherein substituting comprises applying one or more of hydrofluoric acid (HF) and methanesulfonic acid (MSA) to the aluminum oxide layer.7. The method of claim 1 , wherein substituting comprises applying a halogenide via a plasma process to ...

Apparatus and method for bonding substrates

Vorrichtung zum Bonden einer Bondseite eines ersten Substrats mit einer Bondseite eines zweiten Substrats, wobei die Vorrichtung schließbar und gasdicht gegenüber einer Umgebung ausgebildet ist, mit folgenden Merkmalen: einer Modulgruppe (9), aufweisend: zumindest ein Zentralmodul aufweisend eine darin angeordnete Bewegungseinrichtung (10); zumindest ein Reduktionsmodul (4) mit einem Reduktionsraum (12), wobei der Redaktionsraum (12) dichtend mit dem Zentralmodul verbunden ist, wobei das Reduktionsmodul (4) zur Reduktion der Bondseiten ausgebildet ist; zumindest ein Bondmodul (5) mit einem Bondraum (13), wobei das Bondmodul (5) dichtend mit dem Zentralmodul verbunden ist, wobei das Bondmodul (5) zum Bonden der Substrate an den Bondseiten ausgebildet ist; und zumindest ein dichtend mit dem Zentralmodul verbundenes Prozessmodul, wobei das Prozessmodul zur Durchführung von weiteren Prozessen in Hinblick auf die zu bondenden Substrate im Bondmodul ausgebildet ist; wobei die Bewegungseinrichtung (10) zur Bewegung des ersten und zweiten Substrats in der Vorrichtung zwischen den Modulen ausgebildet ist,wobei der Reduktionsraum im Reduktionsmodul und/oder der Bondraum im Bondmodul abdichtend vom Zentralmodul abtrennbar ist, wobei das zumindest eine Prozessmodul ein Ausrichtungsmodul zur Ausrichtung der Substrate zueinander aufweist, und wobei das mindestens eine Prozessmodul weiter aufweist ein Reinigungsmodul zum Vorreinigen, zur groben Reinigung, und/oder kompletten Reduzierung von Oxiden von den Oberflächen der Substrate. Device for bonding a bond side of a first substrate to a bond side of a second substrate, the device being closable and gas-tight with respect to an environment, with the following features: a module group (9), comprising: at least one central module having a movement device (10) arranged therein ; at least one reduction module (4) with a reduction space (12), the editorial space (12) being sealingly connected to the central module, the reduction module ...

Apparatus and method for bonding substrates

Die Erfindung betrifft eine Vorrichtung zum Bonden einer Bondseite eines ersten Substrats mit einer Bondseite eines zweiten Substrats mit folgenden Merkmalen: einer Modulgruppe (9) mit einem zur Umgebung, insbesondere gasdicht, schließbaren gemeinsamen Arbeitsraum, mindestens einem an den Arbeitsraum, insbesondere dichtend, angeschlossenen Bondmodul (5) der Modulgruppe (9), einer Bewegungseinrichtung zur Bewegung des ersten und zweiten Substrats im Arbeitsraum dadurch gekennzeichnet, dass die Modulgruppe (9) ein an den Arbeitsraum, insbesondere dichtend, angeschlossenes Reduktionsmodul ( 4) zur Reduzierung der Bondseiten aufweist. Weiterhin betrifft die Erfindung ein korrespondierendes Verfahren mit folgendem Ablauf: Reduzierung der Bondseiten in einem an den Arbeitsraum angeschlossenen Reduktionsmodul der Modulgruppe (9), Bewegung des ersten und zweiten Substrats im Arbeitsraum von dem Reduktionsmodul in einem Bondraum eines Bondmoduls (5) der Modulgruppe (9) und Bonden des ersten Substrats mit dem zweiten Substrat an den Bondseiten. The invention relates to a device for bonding a bond side of a first substrate to a bond side of a second substrate having the following features: a module group (9) having a common working space which can be closed to the environment, in particular gas-tight, at least one bonding module connected to the work space, in particular sealingly (5) of the module group (9), a movement device for moving the first and second substrate in the working space, characterized in that the module group (9) has a to the working space, in particular sealing, connected reduction module (4) for reducing the bond sides. Furthermore, the invention relates to a corresponding method with the following sequence: reduction of the bond sides in a reduction module of the module group (9) connected to the working space, movement of the first and second substrate in the working space of the reduction module in a bonding space of a bonding module (5) of the module ...

SEMICONDUCTOR LASER MOUNTING FOR IMPROVED FREQUENCY STABILITY

A first contact surface ( 310 ) of a semiconductor laser chip ( 302 ) can be formed to a target surface roughness selected to have a maximum peak to valley height that is substantially smaller than a barrier layer thickness of a metallic barrier layer to be applied to the first contact surface ( 310 ). A metallic barrier layer having the barrier layer thickness can be applied to the first contact surface, and the semiconductor laser chip ( 302 ) can be soldered to a carrier mounting along the first contact surface ( 310 ) using a solder composition ( 306 ) by heating the soldering composition to less than a threshold temperature at which dissolution of the metallic barrier layer into the soldering composition occurs. Related systems, methods, articles of manufacture, and the like are also described.

Method for chip to wafer bonding

기판을 본딩하기 위한 방법

... 본 발명은 적어도 대부분 광투과성인 제1 기판(1)의 제1 접촉 영역(3)을 적어도 대부분 광투과성인 제2 기판(2)의 제2 접촉 영역(4)에 본딩하기 위한 방법에 관한 것이고, 접촉 영역 중 적어도 하나에, 산화물이 본딩을 위해 사용되고, 적어도 대부분 광투과성인 상호연결층(14)은 제1 및 제1 접촉 영역(3, 4) 상에,- 적어도 10e1S/㎠ 의 전기 전도성(300K의 온도에 대해, 네 점 방법(four point method)으로 측정)과,- 0.8 초과의 광 투과율(400 nm 내지 1500 nm 의 파장 범위에 대하여)로 형성된다.

COPPER PASTE FOR PRESSURELESS BONDING, BONDED BODY AND SEMICONDUCTOR DEVICE

A copper paste for pressureless bonding is a copper paste for pressureless bonding, containing: metal particles; and a dispersion medium, in which the metal particles include sub-micro copper particles having a volume average particle diameter of greater than or equal to 0.01 μm and less than or equal to 0.8 μm, and micro copper particles having a volume average particle diameter of greater than or equal to 2.0 μm and less than or equal to 50 μm, and the dispersion medium contains a solvent having a boiling point of higher than or equal to 300° C., and a content of the solvent having a boiling point of higher than or equal to 300° C. is greater than or equal to 2 mass % on the basis of a total mass of the copper paste for pressureless bonding.

MANUFACTURE OF SEMICONDUCTOR DEVICE

PURPOSE: To obtain a stable coupling layer by a method wherein a metallic plate and a semiconductor substrate are arranged oppositely while forming a clearance of predetermined thickness as an introducing path is set up to the metallic plate, a solder material under a solid state is heated and melted, and the material is flowed in the clearance through the introducing path. CONSTITUTION: The radiating metallic plate 7 and the semiconductor substrate 3 are set up at positions where they must be combined through braze while being separated only by a distance H. The introducing path B introducing melted solder to a solder combining region is formed on the metallic plate 7. The solder material 2 is placed on a metallic film 6 separated from a region of which the outer circumferential line of the metallic film 4 of the substrate 3 is projected on the metallic film 6 formed on the metallic plate 7. The solder material 2 is melted by heating the whole in a reducing-gas atmosphere such as hydrogen ...

Verfahren zur Herstellung eines Halbleitermoduls

Verfahren zur Herstellung eines Elektronikmoduls mit den Schritten:Bereitstellen einer Baugruppe (99), die aufweist:• einen Schaltungsträger (3) mit einem ersten metallischen Oberflächenabschnitt (311);• einen ersten Fügepartner (1), der mittels einer ersten Verbindungsschicht (41) mit dem ersten metallischen Oberflächenabschnitt (311) stoffschlüssig verbunden ist; und• einen zweiten metallischen Oberflächenabschnitt (111; 312);Durchführen einer Wärmebehandlung, bei der der zweite metallische Oberflächenabschnitt (111; 312) ununterbrochen auf Temperaturen gehalten wird, die höher sind als eine Wärmebehandlungsmindesttemperatur von wenigstens 300°C, wobei während der Wärmebehandlung kein metallischer Bestandteil der Baugruppe (99) aufgeschmolzen wird;Bereitstellen eines zweiten Fügepartners (2);Herstellen einer festen Verbindung zwischen dem zweiten Fügepartner (2) und der Baugruppe (99), indem der zweite Fügepartner (2) nach Abschluss der Wärmebehandlung an dem durch die Wärmebehandlung gereinigten zweiten Oberflächenabschnitt (111; 312) stoffschlüssig mit der Baugruppe (99) verbunden wird, wobei das Herstellen der festen Verbindung dadurch erfolgt, dass(a) der zweite Fügepartner (2) unmittelbar an den zweiten Oberflächenabschnitt (111; 312) gebondet wird; oder(b) der zweite Fügepartner (2) mittels einer zweiten Verbindungsschicht (42) derart fest mit der Baugruppe (99) verbunden wird, dass die zweite Verbindungsschicht (42) als elektrisch leitender Kleber ausgebildet ist und sich durchgehend zwischen dem zweiten Oberflächenabschnitt (111; 312) und dem zweiten Fügepartner (2) erstreckt. Method for producing an electronic module comprising the steps of: providing an assembly (99) which comprises: a circuit carrier (3) having a first metallic surface section (311), a first joining partner (1) connected by means of a first connecting layer (41) is materially connected to the first metallic surface portion (311); and • a second metallic surface portion (111; 312); ...

Die bonding device and die bonding method

A die bonding device for bonding a second component to a first component is provided with: a mounting base on which the first component is mounted in a mounting region; a heater provided under the mounting base; a side wall provided so as to surround the mounting region of the mounting base; a lid which has a hole of a size allowing the first and the second components to pass therethrough, and which is mounted on the side wall; a collet capable of holding the second component by vacuum-chucking the second component at a tip-end portion thereof; a moving mechanism for moving the collet so that the second component being held by the collet can pass through the hole and be bonded to the first component; and a gas supply pipe provided in the side wall to supply heating gas into a heating space formed by the side wall and the lid, wherein the lid includes a material that can reflect or absorb and re-radiate infrared radiation generated by the heater and the heating gas.

Semiconductor module bonding wire connection method

A method includes providing a subassembly having a circuit carrier with a first metallic surface portion, a first joining partner, which is integrally connected to the first metallic surface portion by means of a first connecting layer, and a second metallic surface portion. In a heat treatment, the second metallic surface portion is held uninterruptedly at temperatures which are higher than a minimum heat-treatment temperature of at least 300° C. Moreover, a second joining partner is provided. A fixed connection is produced between the second joining partner and the subassembly in that the second joining partner is integrally connected to the subassembly following completion of the heat treatment on the second surface portion.

METHOD OF FORMING A CHIP ASSEMBLY AND CHIP ASSEMBLY

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier. 1. A chip assembly , comprising:a carrier with a top side comprising a cavity formed in the top side of the carrier, the cavity configured to receive a chip;a chip, arranged in the cavity, and comprising a chip contact fixed to the bottom of the cavity; andan interconnect material, between the chip contact and the bottom of the cavity;wherein the top side of the carrier outside the cavity is not flush with the chip; andwherein the chip is diffusion-soldered to the bottom of the cavity.2. The chip assembly of claim 1 ,wherein side walls of the cavity are inclined away from the cavity in a direction from a bottom of the cavity to a top of the cavity.3. The chip assembly of claim 1 ,wherein the cavity is formed with a channel at a bottom of the cavity.4. The chip assembly of claim 1 ,the chip has a thickness that is smaller than a depth of the cavity.5. The chip assembly of claim 1 ,wherein the chip protrudes from the cavity.6. The chip assembly of claim 1 ,wherein the cavity has a convex-shaped bottom that is configured to self-center the chip in the associated cavity.7. The chip assembly of claim 1 ,wherein the cavity has side walls that are convex that are configured to self-center the chip in the cavity.8. The chip assembly of claim 1 ,wherein the cavity has side walls that have a non-constant distance between opposite sides of the cavity along a length of a side.9. The chip assembly of claim 1 ,wherein the chip is ...

SEMICONDUCTOR DEVICE

A semiconductor chip () is bonded to an upper surface of an electrode substrate () via a first solder (). A lead frame () is bonded to an upper surface of the semiconductor chip () via a second solder (). An intermediate plate () is provided in the first solder () between the electrode substrate () and the semiconductor chip (). A yield strength of the intermediate plate () is higher than yield strengths of the electrode substrate () and the first solder () within the whole operating temperature range of the semiconductor device. 1. A semiconductor device comprising:an electrode substrate;a semiconductor chip bonded to an upper surface of the electrode substrate via a first solder;a lead frame bonded to an upper surface of the semiconductor chip via a second solder; andan intermediate plate provided in the first solder between the electrode substrate and the semiconductor chip,wherein a yield strength of the intermediate plate is higher than yield strengths of the electrode substrate and the first solder within the whole operating temperature range of the semiconductor device.2. The semiconductor device according to claim 1 , wherein the operating temperature range is −55° C. to 200° C.3. The semiconductor device according to claim 1 , wherein the intermediate plate is positioned inward of the semiconductor chip and the first solder in planar view.4. The semiconductor device according to claim 3 , wherein a distance between an end part of the semiconductor chip and an end part of the intermediate plate is larger than a thickness of the first solder.5. The semiconductor device according to claim 1 , wherein the second solder is positioned inward of the intermediate plate in planar view.6. The semiconductor device according to claim 1 , further comprising a plating film covering a surface of the intermediate plate and having higher wettability to the first solder than that of the intermediate plate.7. The semiconductor device according to claim 6 , wherein a main ...

半導体モジュールと接続相手との間に高温および温度変化に強い接続を形成する方法

Nickel particle composition, bonding material, and bonding method in which said material is used

A nickel particle composition contains: A) nickel particles having an average particle diameter of 0.5-20 [mu]m as measured with laser diffraction/scattering, the particles containing at least 50% by weight or more of elemental nickel; B) nickel particles having an average primary particle diameter of 30-200 nm as measured with a scanning electron microscope, the particles containing 50% by weight or more of elemental nickel; and C) an organic binder in an amount of 0.1-2.5% by weight in relation to the total metal content, the weight ratio of component A and component B (component A:component B) being 30:70 to 70:30.

SEMICONDUCTOR MODULE

This invention is provided with: a metal block (1); a heat-dissipating insulating layer (2) formed by directly layering a ceramic material on at least the first surface (1a) side of the metal block (1); a relay electrode insulating layer (4) formed by directly layering a ceramic material on one portion of the second surface (1b) of the metal block (1); a relay electrode (3) formed by layering a metal material on the upper surface of the relay electrode insulating layer (4); a circuit element (7) bonded to the second surface (1b) of the metal block (1) by solder (23); and an external lead terminal (9). This invention has a configuration in which a bonding wire (11a) or a lead frame (13) from the circuit element (7) is bonded to the relay electrode (3), and the relay electrode (3) and the external lead terminal (9) are connected to each other.

DEVICE AND METHOD FOR BONDING SUBSTRATES

The invention relates to a device for bonding a bonding face of a first substrate to a bonding face of a second substrate, the device having the features of a module group (9) having a common working chamber closable with respect to the surroundings, in particular in a gas-tight manner, at least one bonding module (5) of the module group (9) connected to the working chamber, in particular in a seal-forming manner, a movement device for moving the first and the second substrate in the working chamber, characterised in that the module group (9) comprises a reduction module (4) for reducing the bonding faces and connected to the working chamber, in particular in a seal-forming manner. The invention further relates to a corresponding method having the following sequence: reduction of the bonding faces in a reduction module of the module group (9), the reduction module being connected to the working chamber, movement of the first and second substrate in the working chamber from the reduction ...

SEMICONDUCTOR DEVICES AND METHODS FOR PRODUCING THE SAME

Semiconductor devices, such as vertical-cavity surface-emitting lasers, and methods for manufacturing the same, are disclosed. The semiconductor devices include contact extensions and electrically conductive adhesive material, such as fusible metal alloys or electrically conductive composites. In some instances, the semiconductor devices further include structured contacts. These components enable the production of semiconductor devices having minimal distortion. For example, arrays of vertical-cavity surface-emitting lasers can be produced exhibiting little to no bowing. Semiconductor devices having minimal distortion exhibit enhanced performance in some instances.

METHOD OF DIFFUSION SOLDERING A SEMICONDUCTOR DEVICE USING A SOLDER PREFORM WITH VARYING SURFACE PROFILE

A method of soldering a semiconductor device includes providing a substrate (102) having a first metal joining surface (106), providing a semiconductor die (104) having a second metal joining surface (114), providing a solder preform (100) having a first interface surface (110) and a second interface surface (112), arranging the solder preform (100) between the substrate (102) and the semiconductor die (104) such that the first interface surface (110) of the solder preform (100) faces the first metal joining surface (106) of the substrate (102) and such that the second interface surface (112) of the solder preform (100) faces the second metal joining surface (114) of the semiconductor die (104), and performing a mechanical pressure-free diffusion soldering process that forms a soldered joint between the substrate (102) and the semiconductor die (104) by melting the solder preform (100) and forming intermetallic phases in the solder. One or both of the first interface surface (110) and the ...

The method of joining substrates

High-temperature solder, high-temperature solder paste and power semiconductor device using same

METHOD FOR CHIP TO WAFER BONDING

Sheet for sintering bonding and sheet for sintering bonding with base material

To provide a sheet for sintering bonding and the same with a base material suited for lamination and integration and also suited for realizing satisfactory operational efficiency in a sintering process in a process of producing semiconductor devices that go through sintering bonding of semiconductor chips. A sheet for sintering bonding 10 of the present invention comprises an electrically conductive metal containing sinterable particle and a binder component. In this sheet, the minimum load, reached during an unloading process in load-displacement measurement according to a nanoindentation method, is -100 to -30 [mu]N. Alternatively, the ratio of the minimum load to a maximum load, reached during a load applying process in the above measurement, is -0.2 to -0.06. A sheet body X, a sheet for sintering bonding with a base material of the present invention, has a laminated structure comprising a base material B and the sheet 10.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

The purpose of the present invention is to provide a highly reliable semiconductor device, wherein the thickness of a bonding portion can be controlled even if a part of a second substrate (4) to be bonded with a first substrate (1) is bent. A bonding material of the present invention is configured of a porous metal and a solder, said bonding material bonding the first and the second substrates to each other. In the peripheral portion, the porous metal is provided to both the ends in the thickness direction, and adjusts an interval between both the substrates, and in the center portion, the porous metal is provided not in the whole portion in the thickness direction, thereby absorbing, by means of the solder in the center portion, a design error due to bending of the substrate.

BONDED BODY, POWER MODULE SUBSTRATE WITH HEAT SINK, HEAT SINK, METHOD OF MANUFACTURING BONDED BODY, METHOD OF MANUFACTURING POWER MODULE SUBSTRATE WITH HEAT SINK, AND METHOD OF MANUFACTURING HEAT SINK

The present invention is a bonded body in which an aluminum member constituted by an aluminum alloy, and a metal member constituted by copper, nickel, or silver are bonded to each other. The aluminum member is constituted by an aluminum alloy in which a Si concentration is set to be in a range of 1 mass % to 25 mass %. A Ti layer is formed at a bonding portion between the aluminum member and the metal member, and the aluminum member and the Ti layer, and the Ti layer and the metal member are respectively subjected to solid-phase diffusion bonding.

VERFAHREN ZUR VERBINDUNG EINES SUBSTRATS UND CHIPANORDNUNG

Es wird ein Verfahren zur Verbindung eines Substrats bereitgestellt, wobei das Substrat eine erste Hauptfläche und eine zweite Hauptfläche gegenüber der ersten Hauptfläche umfassen kann. Das Verfahren kann das Bilden mindestens eines Vorsprungs auf der ersten Hauptfläche des Substrats; Bilden eines Fixiermittels über der ersten Hauptfläche des Substrats und über dem mindestens einen Vorsprung und Anordnen des Substrats auf einem Träger umfassen. Der mindestens eine Vorsprung kann eine Oberfläche des Trägers berühren und so ausgelegt sein, dass er die erste Hauptfläche des Substrats in einem Abstand zur Berührungsfläche des Trägers hält, der einer Höhe des Vorsprungs entspricht, um dadurch einen Raum zwischen der ersten Hauptfläche des Substrats und dem Träger zu bilden. Während des Anordnens des Substrats auf dem Träger kann wenigstens ein Teil des über dem mindestens einen Vorsprung ausgebildeten Fixiermittels in den Raum zwischen der ersten Hauptfläche des Substrats und dem Träger verdrängt ...

Bonding device and bonding method

A bonding device of this embodiment includes: a first blower part (11h) generating a first airflow (D1) from a bonding opening (26) that is formed at a conveyer (20) to traverse an imaging space (VS) for identifying a bonding target; and a second blower part (12h) generating a second airflow (D2) along the imaging space. The second blower part (12h) forms a barrier with the second airflow (D2) to suppress a surrounding gas (G2) from being involved into the imaging space (VS) by the first airflow (D1), thereby suppressing influence of heat wave that is generated by the bonding target, such as a substrate or a lead frame.

Conductive paste

An objective of the present invention is to provide a conductive paste that realizes both low resistance and high adhesive strength (die shear strength) of the obtained conductor after firing. The present invention provides a conductive paste which includes: (A) copper fine particles having an average particle diameter of 50 nm or more and 400 nm or less and a crystallite diameter of 20 nm or more and 50 nm or less; (B) copper particles having an average particle diameter of 0.8 [mu]m or more and 5 [mu]m or less, and the ratio of the crystallite diameter to the crystallite diameter of the (A) copper fine particles is 1.0 or more and 2.0 or less; and (C) a solvent.

MOUNTING METHOD

A mounting method for mounting a plurality of chips upon a substrate, comprising: a provisional bonding step in which each of the plurality of chips are provisionally bonded to the substrate; and a main bonding step in which each of the plurality of chips provisionally bonded to the substrate undergo main bonding to the substrate. In the provisional bonding step, a first basic bonding step comprising a first step and a second step is repeated as many times as there are chips to be mounted to the substrate. In the first step, a first metal layer in the substrate (1) and a second metal layer in the chip are positioned. In the second step, the second metal layer and the first metal layer are provisionally bonded using solid phase diffusion bonding. In the main bonding step, a second basic bonding step comprising a third step and a fourth step is repeated as many times as there are chips to be mounted to the substrate. In the third step, the positions of the chips provisionally bonded to the substrate are recognized. In the fourth step, the second metal layer and the first metal layer undergo main bonding using liquid phase diffusion bonding.

METHOD FOR PRODUCING A CONNECTION BETWEEN A SEMICONDUCTOR COMPONENT AND SEMICONDUCTOR MODULE RESISTANT TO HIGH TEMPERATURES AND TEMPERATURE CHANGES BY MEANS OF A TEMPERATURE IMPINGING PROCESS

The invention relates to a method for producing a connection between a semiconductor component and semiconductor module resistant to high temperatures and temperature changes by means of a temperature impinging process, wherein a metal powder suspension is applied to the areas of the semiconductor module to be connected later; the suspension layer is dried, outgassing the volatile components and generating a porous layer; the porous layer is pre-sealed without complete sintering taking place throughout the suspension layer; and, in order to obtain a solid electrically and thermally conductive connection of a semiconductor module to a connection partner from the group of: substrate, further semiconductor or interconnect device, the connection is a sintered connection generated without compression by increasing the temperature and made of a dried metal powder suspension that has undergone a first transport-safe contact with the connection partner in a pre-compression step and has been solidified ...

Bonded body, power module substrate with heat sink, heat sink, method of manufacturing bonded body, method of manufacturing power module substrate with heat sink, and method of manufacturing heat sink

The present invention is a bonded body in which an aluminum member constituted by an aluminum alloy, and a metal member constituted by copper, nickel, or silver are bonded to each other. The aluminum member is constituted by an aluminum alloy in which a Si concentration is set to be in a range of 1 mass % to 25 mass %. A Ti layer is formed at a bonding portion between the aluminum member and the metal member, and the aluminum member and the Ti layer, and the Ti layer and the metal member are respectively subjected to solid-phase diffusion bonding.

Chip assembly

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

Formed top contact for non-flat semiconductor devices

Mounting method

기판을 코팅 및 본딩하기 위한 방법

... 본 발명은 제 1 확산 본드 층(5)이 제 1 표면(1o)에 평행인 방향으로 1㎛ 미만의 평균 결정립 지름 H를 갖는 결정립 표면을 형성하도록, 제 1 기판(1)의 제 1 표면(1o) 상에 제 1 확산 본드 층(5)을 형성하는 제 1 물질을 증착하는, 제 1 확산 본드 층(5)으로 제 1 기판(1)을 코팅하는 방법과 관련된다. 덧붙여, 본 발명은 이러한 방식으로 코팅된 제 1 기판(1)을 제 2 확산 본드 층(4)을 갖는 제 2 기판(3)에 본딩하기 위한 방법과 관련되며, - 제 1 기판(1)의 제 1 확산 본드 층(5)을 제 2 기판(3)의 제 2 확산 본드 층에 접촉시키는 단계, - 제 1 기판(1)과 제 2 기판(3) 사이에 영구 금속 확산 본드를 형성하기 위해 기판(1, 3)을 압착시키는 단계를 포함한다.

Method for producing a connection between a semiconductor component and semiconductor module resistant to high temperatures and temperature changes by means of a temperature impinging process

Zn-based lead-free solder and semiconductor power module

本发明得到实用的熔点范围为300～350℃的Zn系无铅焊料。Zn系无铅焊料，其含有：0.05～0.2wt％的Cr、0.25～1.0wt％的Al、0.5～2.0wt％的Sb、1.0～5.8wt％的Ge、和5～10wt％的Ga。或者，Zn系无铅焊料，其含有：0.05～0.2wt％的Cr、0.25～1.0wt％的Al、0.5～2.0wt％的Sb、1.0～5.8wt％的Ge、和10～20wt％的In。

Dual-phase intermetallic interconnection structure and method of fabricating the same

Provided are a dual-phase intermetallic interconnection structure and a fabricating method thereof. The dual-phase intermetallic interconnection structure includes a first intermetallic compound, a second intermetallic compound, a first solder layer, and a second solder layer. The second intermetallic compound covers and surrounds the first intermetallic compound. The first intermetallic compound and the second intermetallic compound contain different high-melting point metal. The first solder layer and the second solder layer are disposed at the opposite sides of the second intermetallic compound, respectively. The first intermetallic compound is adapted to fill the micropore defects generated during the formation of the second intermetallic compound.

Bond-Material, Bond-Verfahren und Halbleitervorrichtung für elektrische Energie

Ein flächenkörperartiges Bond-Material (1), das aus einer Silber-Bismut-Legierung hergestellt ist, welche, wenn sie in einem Zustand erwärmt wird, in welchem sie in Kontakt mit einem Metallmaterial als ein Bond-Objekt (z. B. Flächenschichten 2f, 3f) ist, in dem Metallmaterial (als Material z. B. Gold, Silber oder Kupfer) eine Diffusionsschicht (Ld2, Ld3) aus Silber ausbildet, und zwar infolge einer Festphasen-Diffusionsreaktion, so dass sie an das Metallmaterial gebondet wird, wobei das Bond-Material nicht weniger als 1 Gew.-% und nicht mehr als 5 Gew.-% an Bismut enthält.

VERFAHREN ZUR VERBINDUNG EINES SUBSTRATS

Verfahren zur Verbindung eines Substrats, wobei das Substrat ein Wafer ist und eine erste Hauptfläche und eine zweite Hauptfläche gegenüber der ersten Hauptfläche umfasst, umfassend: Bilden mindestens eines Vorsprungs auf der ersten Hauptfläche des Substrats, aufweisend ein Bilden einer Struktur, die eine Mehrzahl von Wänden aufweist, auf der ersten Hauptfläche des Substrats, wobei die Mehrzahl von Wänden mindestens eine Vertiefung dazwischen definiert und wobei die Wände in Schnittregionen des Substrats gebildet werden; Bilden eines Fixiermittels über der ersten Hauptfläche des Substrats und über dem mindestens einen Vorsprung; Trennen des Substrats in einzelne Chips vor dem Anordnen des Substrats auf einem Träger; und Anordnen des Substrats auf dem Träger, wobei der mindestens eine Vorsprung eine Oberfläche des Trägers berührt und so ausgelegt ist, dass er die erste Hauptfläche des Substrats in einem Abstand zu einer Berührungsfläche des Trägers hält, der einer Höhe des Vorsprungs entspricht ...

Method for coating and bonding of substrates

This invention relates to a method for coating of a first substrate (1) with a first diffusion bond layer (5) by deposition of a first material which forms the first diffusion bond layer (5) on a first surface (1o) of the first substrate (1) such that the first diffusion bond layer (5) forms a grain surface with an average grain diameter H parallel to the first surface (1o) smaller than 1 m. Furthermore this invention relates to a method for bonding of a first substrate (1) which has been coated in this way to a second substrate (3) which has a second diffusion bond layer (4) with the following steps, especially the following sequence: contact-making of the first diffusion bond layer (5) of the first substrate (1) to the second diffusion bond layer of the second substrate (3), pressing the substrates (1, 3) together for forming a permanent metal diffusion bond between the first and second substrate (1, 3).

Bondaufbau, Bondmaterieal und Bondverfahren

Ein Bondaufbau (20) bondet eine Cu-Verdrahtungsleitung (12) und eine Bauelementelektrode (14) aneinander. Der Bondaufbau (20) ist zwischen der Cu-Verdrahtungsleitung (12) und der Bauelementelektrode (14) angeordnet und umfasst eine erste intermetallische Verbindungsschicht (21) (eine Schicht aus einer intermetallischen Verbindung (IMV) aus Cu und Sn), die auf der Grenzfläche mit der Cu-Verdrahtungsleitung (12) ausgebildet ist, eine zweite intermetallische Verbindungsschicht (22) (eine Schicht aus einer intermetallischen Verbindung (IMV) aus Cu und Sn), die auf der Grenzfläche mit der Bauelementelektrode (14) ausgebildet ist, und eine Zwischenschicht (25), die zwischen den intermetallischen Verbindungsschichten vorhanden ist. In der Zwischenschicht (25) ist in Sn (23) eine netzwerkartige IMV (24) (eine netzwerkartige intermetallische Verbindung aus Cu und Sn) vorhanden.

SEMICONDUCTOR DEVICE BONDING MATERIAL

High-temperature solder, high-temperature solder paste and power semiconductor using same

The present invention intends to provide a power semiconductor device using a high-temperature lead-free solder material, the high-temperature lead-free solder material having the heat resistant property at 280° C. or more, and the bondability at 400° C. or less, and excellent in the suppliabilty and wettability of solder, and in the high-temperature storage reliability and the temperature cycle reliability. In the power semiconductor device according to the present invention, a semiconductor element and a metal electrode member were bonded each other by a high-temperature solder material comprising Sn, Sb, Ag, and Cu as the main constitutive elements and the rest of other unavoidable impurity elements wherein the high-temperature solder material comprises 42 wt %Sb/(Sn+Sb)48 wt %, 5 wt %Ag<20 wt %, 3 wt %Cu<10 wt %, and Ag+Cu25 wt %.

Micro-bonding structure and method of forming the same

A micro-bonding structure including a substrate, a conductive pad, a bonding layer, a micro device, and a diffusive bonding portion is provided. The conductive pad is on the substrate. The bonding layer is on the conductive pad. A thickness of the bonding layer ranges from about 0.2 μm to about 2 μm. The micro device is on the bonding layer. The diffusive bonding portion is between and electrically connected with the bonding layer and the conductive pad. The diffusive bonding portion consists of at least a part of elements from the bonding layer and at least a part of elements from the conductive pad. A plurality of voids are between the bonding layer and the conductive pad, and one of the voids is bounded by the diffusive bonding portion and at least one of the conductive pad and the bonding layer.

METHOD FOR BONDING OF CHIPS ON WAFERS

Method for bonding of a plurality of chips onto a base wafer which contains chips on the front, the chips being stacked in at least one layer on the back of the base wafer and electrically conductive connections are established between the vertically adjacent chips, with the following steps: a) fixing of the front of the base wafer on a carrier, b) placing at least one layer of chips in defined positions on the back of the base wafer, and c) heat treatment of the chips on the base wafer fixed on the carrier, characterized in that prior to step c) at least partial separation of the chips of the base wafer into separated chip stack sections of the base after takes place.

SHEET FOR SINTERING BONDING AND SHEET FOR SINTERING BONDING WITH BASE MATERIAL

To provide a sheet for sintering bonding and a sheet for sintering bonding with a base material that are suited for properly supplying a material for sintering bonding to a face planned to be bonded of a bonding object. A sheet for sintering bonding 10 according to the present invention comprises an electrically conductive metal containing sinterable particle and a binder component. In the sheet for sintering bonding 10 , the shear strength at 23° C., F (MPa), measured in accordance with a SAICAS method and the minimum load, f (μN), which is reached during an unloading process in load-displacement measurement in accordance with a nanoindentation method, satisfy 0.1≤F/f≤1. A sheet body X, which is a sheet for sintering bonding with a base material according to the present invention, has a laminated structure comprising a base material B and the sheet for sintering bonding 10.

Halbleiteranordnung und Verfahren zu ihrer Herstellung

Semiconductor laser mounting for improved frequency stability

A first contact surface ( 310 ) of a semiconductor laser chip ( 302 ) can be formed to a target surface roughness selected to have a maximum peak to valley height that is substantially smaller than a barrier layer thickness of a metallic barrier layer to be applied to the first contact surface ( 310 ). A metallic barrier layer having the barrier layer thickness can be applied to the first contact surface, and the semiconductor laser chip ( 302 ) can be soldered to a carrier mounting along the first contact surface ( 310 ) using a solder composition ( 306 ) by heating the soldering composition to less than a threshold temperature at which dissolution of the metallic barrier layer into the soldering composition occurs. Related systems, methods, articles of manufacture, and the like are also described.

Semiconductor device bonding material

Provided is a semiconductor device wherein an internal bonding section does not melt at the time of substrate mounting by means of filling the hole portions of a porous metal body having a mesh structure with an Sn or Sn-based solder alloy and using a bonding material obtained by covering the surface thereof for internal bonding of the semiconductor device.

Jointed structure and method of manufacturing same

A jointed structure comprises a first metal layer and a second metal layer. The first metal layer and the second metal layer are jointed together and have different coefficients of thermal expansion. The first metal layer and the second metal layer are jointed together by solid-phase joining via a jointing interface microstructure, wherein the jointing interface microstructure includes an amorphous oxide phase and having a thickness of 50 nm or less.

DIE BONDING APPARATUS AND DIE BONDING METHOD

A die bonding apparatus includes: a mounting base including a mounting area on which a first member is mounted; a heater arranged below the mounting base; a side wall configured to surround the mounting area; a collet configured to hold a second member by vacuum-chucking at an end portion; a lid including a hole, the lid being mounted on the side wall; a moving structure configured to move the collet to transport the second member held by the collet through the hole for bonding the second member to the first member; and a gas-supplying tube arranged on the side wall and configured to supply a heating gas to a heating space formed by the side wall and the lid. The lid contains a material capable of: reflecting an infrared radiation caused by the heater and the heating gas; or absorbing and re-radiating the infrared radiation.

Method of Forming an Interconnection between an Electric Component and an Electronic Component

A method of forming an interconnection includes: providing an electronic component having a first main face and a first metallic layer disposed on the first main face; providing an electric component having a second main face and a second metallic layer disposed on the second main face, at least one of the first or second metallic layers including an oxide layer provided on a main face thereof; disposing a reducing agent on one or both of the electronic component and the electric component such that the reducing agent is enabled to remove the oxide layer; and connecting the electronic component to the electric component by directly connecting the first metallic layer of the electronic component with the second metallic layer of the electric component by applying pressure and heat.

STARTER MATERIAL FOR A SINTERING COMPOUND AND METHOD FOR PRODUCING SAID SINTERING COMPOUND

Verfahren zum Beschichten und Bonden von Substraten

The welding method for manufacturing products of

CONDUCTIVE JUNCTION MATERIAL, CAPABLE OF IMPROVING A HEAT RADIATING PROPERTY AND A JUNCTION RELIABILITY, A JUNCTION METHOD, AND A SEMICONDUCTOR DEVICE USING THE SAME

PURPOSE: A conductive junction material, a junction method, and a semiconductor device using the same are provided to secure the high heat resistant property and the high heat radiating property of a junction part by performing a pressureless junction process without an adhesive. CONSTITUTION: A conductive junction material is arranged between junction units(201). The conductive junction material includes a silver oxide particle(202), silver flake(203), and a dispersing agent. The dispersing agent includes an organic compound with 30 or less carbon numbers. The conductive junction material is heated to be sintered in order to form a sintered silver layer(205). The sintered silver layer is bonded with the junction interface of the junction units by a metallic bond. COPYRIGHT KIPO 2011 ...

Semiconductor device having a stacked electrode with an electroless nickel plating layer

A semiconductor device including: a semiconductor element; and a first electrode formed on a first surface of the semiconductor element. The first electrode has a stacked structure including a first electroless Ni plating layer. The first electroless Ni plating layer contains nickel (Ni) and phosphorus (P) as a composition. A phosphorus (P) concentration of the first electroless Ni plating layer is 2.5 wt % to 6 wt % inclusive, and a crystallization rate of Ni3P in the first electroless Ni plating layer is 0% to 20% inclusive.

Method for producing soldered product

The present invention relates to a method for producing a soldered product by which soldering can be accomplished without using a jig. The method for producing a soldered product of the present invention comprises: a provision step of providing a solder and a temporary fixing agent for temporarily fixing the solder; a temporary fixing step of temporarily fixing the solder to a soldering target with the temporary fixing agent; a vaporization step of placing the soldering target with the solder temporarily fixed thereto in a vacuum or heating the soldering target with the solder temporarily fixed thereto to a predetermined temperature lower than the melting temperature of the solder, to vaporize the temporary fixing agent in order to form gaps between the solder and the soldering target; a reduction step, performed concurrently with or after the vaporization step, of reducing, with a reducing gas at a predetermined temperature lower than the melting temperature of the solder, the solder and ...

ASSEMBLY JIG FOR A SEMICONDUCTOR DEVICE AND ASSEMBLY METHOD FOR A SEMICONDUCTOR DEVICE

In aspects of the assembly jig and method of the invention, when a packaging substrate is curved concaving upward at temperatures of melting solder, the gap between the assembly jig and the packaging substrate can be made smaller than the dimension of the sum of the thickness of the semiconductor chip and the thickness of the melted solder by allowing a part of the bottom surface of the chip positioning piece to become always, or substantially always, in contact with the upper surface of the packaging substrate owing to the weight of the chip positioning jig itself. As a consequence, the semiconductor chip does not slip aside out of the opening of the chip positioning piece. Therefore, the semiconductor chip can be positioned accurately on the packaging substrate.

SINTERING BONDING METHOD FOR SEMICONDUCTOR DEVICE

Discloses is a method of bonding a semiconductor device, for example, a sintering bonding method for a semiconductor device that can mix pure particles and copper (I) oxide nano particles on a metal substrate. The paste of the present invention may provide low-cost copper paste increasing a copper density as a bonding material when bonding a semiconductor chip continuously used at a high temperature. The copper paste of the present invention may suppress the occurrence of pores or cracks when sintering by heating the copper paste under the reduction atmosphere as saving material costs and implementing an optimum high heat-resistance bonding.

Bonded structure and method of manufacturing the same

A highly reliable bonded structure having excellent thermal fatigue resistance characteristics and thermal stress relaxation characteristics is provided. The bonded structure of the present invention comprises a first member, a second member capable of being bonded to the first member, and a bonding part interposed between a first bond surface at the first member side and a second bond surface at the second member side to bond the first member and the second member. The bonding part has at least a bonding layer, a reinforcing layer, and an intermediate layer. The bonding layer is composed of an intermetallic compound and bonded to the first bond surface.

Stromrichtvorrichtung

Stromrichtvorrichtung, enthaltend:eine auf einem wärmeabführenden Kühlkörper angeordnete gedruckte Leiterplatte mit einem elektrisch isolierenden Substratkörper, welche ein Durchgangsloch aufweist und mit Drähten versehen ist, wobei die gedruckte Leiterplatte direkt am Kühlkörper montiert ist;ein Metallgehäuse mit einem in das Durchgangsloch einzufügenden abgesenkten Teil, dessen abgesenkter Teil über eine aus einem Keramikwerkstoff bestehende wärmeabführende Isolierschicht an der Oberseite des Kühlkörpers montiert ist, wobei eine unterseitige Oberfläche der wärmeabführenden Isolierschicht bündig mit einer unterseitigen Oberfläche der gedruckten Leiterplatte verläuft; undein in dem abgesenkten Teil montiertes Leistungshalbleiterelement, welches mit den Drähten der gedruckten Leiterplatte elektrisch verbunden ist.

Zn-Basiertes bleifreies Lot und Halbleiterleistungsmodul

Es wird ein Zn-basiertes bleifreies Lot (2) angegeben, bei dem sein Bereich der praktischen Schmelzpunkte zwischen 300 °C und 350 °C liegt. Das Zn-basierte bleifreie Lot (2) weist Folgendes auf: einen Cr-Gehalt von 0,05 bis 0,2 Gew.-%, einen Al-Gehalt von 0,25 bis 1,0 Gew.-%, einen Sb-Gehalt von 0,5 bis 2,0 Gew.-%, einen Ge-Gehalt von 1,0 bis 5,8 Gew.-% und einen Ga-Gehalt von 5 bis 10 Gew.-%; oder das Zn-basierte bleifreie Lot (2) weist Folgendes auf: einen Cr-Gehalt von 0,05 bis 0,2 Gew.-%, einen Al-Gehalt von 0,25 bis 1,0 Gew.-%, einen Sb-Gehalt von 0,5 bis 2,0 Gew.-%, einen Ge-Gehalt von 1,0 bis 5,8 Gew.-%, und einen In-Gehalt von 10 bis 20 Gew.-%.

Semiconductor Device and Power Conversion Apparatus

A semiconductor device including: a semiconductor element; and a first electrode formed on a first surface of the semiconductor element. The first electrode has a stacked structure including a first electroless Ni plating layer. The first electroless Ni plating layer contains nickel (Ni) and phosphorus (P) as a composition. A phosphorus (P) concentration of the first electroless Ni plating layer is 2.5 wt % to 6 wt % inclusive, and a crystallization rate of Ni3P in the first electroless Ni plating layer is 0% to 20% inclusive.

CMOS-MEMS integration by sequential bonding method

Methods for bonding two wafers are disclosed. In one aspect, a first wafer includes an integrated circuit and the second wafer including a MEMS device. The method comprises depositing a bond pad on a metal on the first wafer and sequentially bonding the first wafer to the second wafer utilizing first and second temperatures. The second wafer is bonded to the bond pad at the first temperature and the bond pad and the metal are bonded at the second temperature. In another aspect, a first wafer including an integrated circuit, the second wafer includes a MEMS device. The method comprises depositing a bond pad on a metal on one of the first wafer and the second wafer and bonding the first wafer to the second wafer at a first temperature via a direct bond interface. The method includes bonding the bond pad to the metal at a second temperature.

SOLDERING A CONDUCTOR TO AN ALUMINUM METALLIZATION

A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.

METHOD FOR PRODUCING A CONNECTION BETWEEN A SEMICONDUCTOR COMPONENT AND SEMICONDUCTOR MODULE RESISTANT TO HIGH TEMPERATURES AND TEMPERATURE CHANGES BY MEANS OF A TEMPERATURE IMPINGING PROCESS

The invention relates to a method for producing a connection between a semiconductor component and semiconductor module resistant to high temperatures and temperature changes by means of a temperature impinging process, wherein a metal powder suspension is applied to the areas of the semiconductor module to be connected later; the suspension layer is dried, outgassing the volatile components and generating a porous layer; the porous layer is pre-sealed without complete sintering taking place throughout the suspension layer; and, in order to obtain a solid electrically and thermally conductive connection of a semiconductor module to a connection partner from the group of: substrate, further semiconductor or interconnect device, the connection is a sintered connection generated without compression by increasing the temperature and made of a dried metal powder suspension that has undergone a first transport-safe contact with the connection partner in a pre-compression step and has been solidified ...

DUAL-PHASE INTERMETALLIC INTERCONNECTION STRUCTURE AND METHOD OF FABRICATING THE SAME

Provided are a dual-phase intermetallic interconnection structure and a fabricating method thereof. The dual-phase intermetallic interconnection structure includes a first intermetallic compound, a second intermetallic compound, a first solder layer, and a second solder layer. The second intermetallic compound covers and surrounds the first intermetallic compound. The first intermetallic compound and the second intermetallic compound contain different high-melting point metal. The first solder layer and the second solder layer are disposed at the opposite sides of the second intermetallic compound, respectively. The first intermetallic compound is adapted to fill the micropore defects generated during the formation of the second intermetallic compound.

Semiconductor laser mounting for improved frequency stability

A first contact surface of a semiconductor laser chip can be formed to a target surface roughness selected to have a maximum peak to valley height that is substantially smaller than a barrier layer thickness of a metallic barrier layer to be applied to the first contact surface. A metallic barrier layer having the barrier layer thickness can be applied to the first contact surface, and the semiconductor laser chip can be soldered to a carrier mounting along the first contact surface using a solder composition by heating the soldering composition to less than a threshold temperature at which dissolution of the metallic barrier layer into the soldering composition occurs. Related systems, methods, articles of manufacture, and the like are also described.

Sintervorrichtung

Die Erfindung geht aus von einer Sintervorrichtung (10) zum Herstellen eines Werkstücks (30) aus zumindest einer Komponente mittels Drucksintern. Die Sintervorrichtung weist ein Oberwerkzeug (12) und ein Unterwerkzeug (14) auf, zwischen denen die zumindest eine Komponente aufgenommen ist. Das Oberwerkzeug (12) und das Unterwerkzeug (14) sind zum Aufbringen einer Presskraft auf das zu sinternde Werkstück (30) relativ zueinander verstellbar. Es ist zumindest einer Heizvorrichtung (18a, 18b) zum Erwärmen des zu sinternden Werkstücks (30) vorgesehen. Es wird vorgeschlagen, dass die Sintervorrichtung ferner zumindest eine Kühlvorrichtung (22a, 22b) aufweist. The invention is based on a sintering device (10) for producing a workpiece (30) from at least one component by means of pressure sintering. The sintering device has an upper tool (12) and a lower tool (14), between which the at least one component is received. The upper tool (12) and the lower tool (14) are adjustable for applying a pressing force on the workpiece to be sintered (30) relative to each other. At least one heating device (18a, 18b) is provided for heating the workpiece (30) to be sintered. It is proposed that the sintering device further comprises at least one cooling device (22a, 22b).

LÖTEN EINES LEITERS AN EINE ALUMINIUMMETALLISIERUNG

Ein Verfahren zum Löten eines Leiters an eine Aluminiummetallisierung beinhaltet Substituieren einer Aluminiumoxidschicht auf der Aluminiummetallisierung durch eine Substitutmetalloxidschicht oder eine Substitutmetalllegierungsoxidschicht. Dann werden Substitutmetalloxide in der Substitutmetalloxidschicht oder der Substitutmetalllegierungsoxidschicht wenigstens teilweise reduziert. Der Leiter wird unter Verwendung eines Lotmaterials an die Aluminiummetallisierung gelötet.

Ausgangswerkstoff einer Sinterverbindung und Verfahren zur Herstellung der Sinterverbindung

Der erfindungsgemäße Ausgangswerkstoff einer Sinterverbindung umfasst Partikel, die zumindest anteilig eine organische Metallverbindung und/oder ein Edelmetalloxid enthalten, wobei die organische Metallverbindung und/oder das Edelmetalloxid bei einer Temperaturbehandlung des Ausgangswerkstoffes in das elementare Metall und/oder Edelmetall umgewandelt wird. Kennzeichnend für die Erfindung ist, dass die Partikel eine Beschichtung enthaltend ein Reduktionsmittel aufweisen, mittels welchem die Reduktion der organischen Metallverbindung und/oder des Edelmetalloxids zu dem elementaren Metall und/oder Edelmetall bei einer Temperatur unterhalb der Sintertemperatur des elementaren Metalls und/oder Edelmetalls erfolgt. The starting material of a sintered compound according to the invention comprises particles which at least partially contain an organic metal compound and / or a noble metal oxide, the organic metal compound and / or the noble metal oxide being converted into the elemental metal and / or noble metal during a temperature treatment of the starting material. It is characteristic of the invention that the particles have a coating containing a reducing agent, by means of which the reduction of the organic metal compound and / or the noble metal oxide to the elemental metal and / or noble metal takes place at a temperature below the sintering temperature of the elemental metal and / or noble metal ,

Chip-on-wafer bonding method and bonding device, and structure comprising chip and wafer

Method for coating and bonding of substrates

Sheet for sintering bonding and sheet for sintering bonding with base material

A sheet for sintering bonding which can be manufactured with a good efficiency, and which is suitable for a sintering process in a semiconductor device manufacturing process including semiconductor chip sintering bonding with a good efficiency, and a sheet for sintering bonding with a base material are provided. The sheet for sintering bonding (10) compriseselectrically conductive metal containingsinterable particles and a binder component, and has a shear strength at 23 DEG C of 2 to 40 MPa measured in accordance with a SAICAS method. A sheet body (X) of the sheet for sintering bonding with the base material has a laminated structure comprising the base material (B) and the sheet for sintering bonding (10).

SHEET FOR SINTERING BONDING, SHEET FOR SINTERING BONDING WITH BASE MATERIAL, AND SEMICONDUCTOR CHIP WITH LAYER OF MATERIAL FOR SINTERING BONDING

A sheet for sintering bonding 10 of the present invention comprises an electrically conductive metal containing sinterable particle and a binder component, and upon subjecting the sheet to a pressurization treatment onto a silver plane of a 5 mm square Si chip under predetermined conditions, the ratio of the area of a layer of a material for sintering bonding transferred onto the silver plane to the silver plane area is 0.75 to 1. A sheet body X of the present invention has a laminated structure comprising a base material B and the sheet 10 . A semiconductor chip with a layer of a material for sintering bonding of the present invention comprises a semiconductor chip and a material layer derived from the sheet 10 on one face of the chip, and the ratio of the area of the material layer to the area of that face is 0.75 to 1.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Provided is a semiconductor device capable of accurately positioning a semiconductor element with respect to a metal circuit pattern or positioning an insulating substrate with respect to a base plate without using a dedicated positioning jig, thereby being able to be manufactured inexpensively and a method of manufacturing the semiconductor device. The semiconductor device includes: an insulating substrate; and a semiconductor element, wherein the insulating substrate includes an insulating layer and a metal circuit pattern provided on an upper surface of the insulating layer, the semiconductor element is solder joined to an upper surface of the metal circuit pattern, and an oxide film or a nitride film is provided in a region where the semiconductor element is not solder joined in the upper surface of the metal circuit pattern. 1. A semiconductor device , comprising:an insulating substrate; anda semiconductor element, whereinthe insulating substrate includes an insulating layer and a metal circuit pattern provided on an upper surface of the insulating layer,the semiconductor element is solder joined to an upper surface of the metal circuit pattern, andan oxide film or a nitride film is provided in a region where the semiconductor element is not solder joined in the upper surface of the metal circuit pattern.2. The semiconductor device according to claim 1 , whereinthe oxide film or the nitride film is provided in 95% or more of an area of the region where a solder joint is not performed in the upper surface of the metal circuit pattern.3. The semiconductor device according to claim 1 , whereinthe region where the semiconductor element is solder joined in the upper surface of the metal circuit pattern is rougher than the region where the solder joint is not performed in the upper surface of the metal circuit pattern.4. The semiconductor device according to claim 1 , whereina depression portion is formed on the upper surface of the metal circuit pattern, andthe ...

SINTERED COMPOUND STARTING MATERIAL AND METHOD FOR PRODUCING THE SINTERED COMPOUND

Verpackte Vorrichtung mit nicht ganzzahligen Anschlussrastern und Verfahren zu deren Herstellung

Verpackte Vorrichtung, umfassend:einen ersten Chip (300);eine Verpackung (310), die den ersten Chip (300) einkapselt; undmehrere für eine Durchsteckmontage ausgelegte Anschlüsse (320, 322, 324, 326), die aus der Verpackung (310) herausragen, wobei die mehreren Anschlüsse (320, 322, 324, 326) unterschiedliche nicht ganzzahlig vielfache Anschluss-Rastermaße umfassen, wobei die mehreren Anschlüsse (320, 322, 324, 326) konstante Anschluss-zu-Anschluss Abstände umfassen, wobei die mehreren Anschlüsse (320, 322, 324, 326) verschiedene Anschlussbreiten umfassen.

Starting material for a sintered bond and process for producing the sintered bond

The invention relates to a starter material for a sintering compound, said starter material comprising particles which at least proportionally contain an organic metal compound and/or a precious metal oxide, the organic metal compound and/or the precious metal oxide being converted during heat treatment of the starter material into the elemental metal and/or precious metal. The invention is characterized in that the particles have a coating containing a reducing agent by means of which the organic metal compound and/or precious metal oxide is reduced to the elemental metal and/or precious metal at a temperature below the sintering temperature of the elemental metal and/or precious metal.

Pre-Plating of Solder Layer on Solderable Elements for Diffusion Soldering

A pre-soldered circuit carrier includes a carrier having a metal die attach surface, a plated solder region on the metal die attach surface, wherein a maximum thickness of the plated solder region is at most 50 μm, the plated solder region has a lower melting point than the first bond pad, and the plated solder region forms one or more intermetallic phases with the die attach surface at a soldering temperature that is above the melting point of the plated solder region.

Joint Manufacturing Method

Provided is a joint manufacturing method including: a step A of preparing a laminate in which two objects to be joined are temporarily adhered with a heat-joining sheet including a pre-sintering layer interposed between the two objects to be joined; a step B of increasing a temperature of the laminate from a temperature equal to or lower than a first temperature defined below to a second temperature; and a step C of holding the temperature of the laminate in a predetermined range after the step B, in which the laminate is pressurized during at least a part of the step B and at least a part of the step C. The first temperature is a temperature at which an organic component contained in the pre-sintering layer is decreased by 10% by weight when the pre-sintering layer is subjected to thermogravimetric measurement.

Method of forming a chip assembly and chip assembly

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

Method of joining a surface-mount component to a substrate with solder that has been temporarily secured

A method of joining a surface-mount component to a substrate includes placing a piece of solder on top of the substrate and temporarily bonding the piece of solder to the substrate with at least one temporary bond. The method also includes placing a surface-mount component on top of the substrate with a bottom face of the surface-mount component facing the substrate. The surface-mount component has at least one lateral side. The method further includes positioning the surface-mount component with the at least one lateral side proximate the piece of solder, heating the substrate and the piece of solder to a joining temperature for a time sufficient for the solder to flow into an area between the bottom face of the surface-mount component and the substrate, and cooling the substrate and solder.

METHOD FOR PRODUCING MEMBER FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE, AND MEMBER FOR SEMICONDUCTOR DEVICE

A member for semiconductor device includes a metal portion configured to be bonded to another member by solder, and a treated coating covering a surface of the metal portion, the treated coating including a treatment agent. The treated coating vaporizes at a temperature lower than or equal to a solidus temperature of the solder. 1. A member for semiconductor device , comprising:a metal portion configured to be bonded to another member by solder, anda treated coating covering a surface of the metal portion, the treated coating including a treatment agent,wherein the treated coating vaporizes at a temperature lower than or equal to a solidus temperature of the solder.2. The member for semiconductor device according to claim 1 , wherein a vaporization temperature of the treated coating is in a range from 80 to 250° C.3. The member for semiconductor device according to claim 1 , wherein the treatment agent comprises at least one organic substance selected from a carboxylic acid claim 1 , a metal salt of carboxylic acid claim 1 , an ammonium salt of carboxylic acid claim 1 , an amine salt of carboxylic acid claim 1 , and a carboxylic acid ester.4. The member for semiconductor device according to claim 3 , wherein the organic substance comprises 1 to 25 carbons.5. The member for semiconductor device according to claim 3 , wherein the organic substance has a molecular weight from 30 to 400 g/mol.6. The member for semiconductor device according to claim 3 , wherein the treatment agent comprises the at least one organic substance claim 3 , and water or alcohol dissolving the at least one organic substance.7. The member for semiconductor device according to claim 3 , wherein the carboxylic acid is a fatty acid.8. The member for semiconductor device according to claim 1 , wherein the treated coating of the treatment agent is physically adsorbed onto the surface of metal portion.9. The member for semiconductor device according to claim 3 , wherein the organic substance is the ...

NICKEL PARTICLE COMPOSITION, BONDING MATERIAL, AND BONDING METHOD IN WHICH SAID MATERIAL IS USED

A nickel particle composition is shown, including: A) a nickel particle having an average particle size in the range of 0.5 μm to 20 μm obtained via a laser diffraction/scattering method and containing 50 wt % or more of a nickel element; B) a nickel fine particle having an average primary particle size in the range of 30 nm to 200 nm observed via a scanning electron microscope and containing 50 wt % or more of a nickel element; and C) an organic binder in the range of 0.1 wt % to 2.5 wt % relative to the total metal content; and the weight ratio of a component A to a component B (component A:component B) is in the range of 30:70 to 70:30. 1. A nickel particle composition , comprising the following component A to component C:component A: a nickel particle having an average particle size in a range of 0.5 to 20 μm obtained via a laser diffraction/scattering method and containing 50 wt % or more of a nickel element;component B: a nickel fine particle having an average primary particle size in a range of 30 nm to 200 nm observed via a scanning electron microscope and containing 50 wt % or more of the nickel element; andcomponent C: an organic binder in a range of 0.1 wt % to 2.5 wt % relative to a total metal content; anda weight ratio of the component A to the component B (component A:component B) is in a range of 30:70 to 70:30.2. The nickel particle composition of claim 1 , wherein a content of the nickel element of the component A is 99.0 wt % or more.3. The nickel particle composition of claim 1 , wherein a content of the nickel element of the component B is in a range of 90 wt % to 99.0 wt %.4. The nickel particle composition of claim 1 , wherein a content of the nickel element of the component A is 99.0 wt % or more claim 1 , and a content of the nickel element of the component B is in a range of 90 wt % to 99.0 wt %.5. (canceled)6. The nickel particle composition of claim 1 , wherein a content of the nickel element of the component A is 99.0 wt % or more claim ...

Soldering a conductor to an aluminum metallization

A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.

APPARATUS FOR ESPECIALLY THERMALLY JOINING MICRO-ELECTROMECHANICAL PARTS

The invention relates to an apparatus for especially thermally joining micro-electromechanical parts () in a process chamber (), comprising a bottom support plate () for holding at least one first () of the parts () to be joined, and a pressing device () for applying pressure to at least one second () of the parts () to be joined in relation to the at least one first part (). The pressing device () is equipped with an expandable membrane () provided for entering in contact with the at least one second part (). Fluid pressure, in particular gas pressure, can be applied to said membrane () on the side thereof facing away from the parts () to be joined. 12311223153232151931923. An apparatus for especially thermally joining micro-electromechanical components ( , ) in a process chamber (B) with a lower support plate () for receiving at least one first component () of the components ( , ) to be joined and with a pressing device () for applying pressure onto at least one second component () of the components ( , ) to be joined , in direction of the least one first component () , characterized in that said pressing device () is formed with an expandable membrane () provided for contacting the at least one second component () , wherein fluid pressure , in particular gas pressure , can be applied onto said membrane () on its side facing away from the components ( , ) to be joined.219. The apparatus according to claim 1 , characterized in that the membrane () is made of a gas-tight sheet material claim 1 , in particular a rubberlike material.319231923. The apparatus according to or claim 1 , characterized in that the thickness of the membrane () and its expansibility are preferably selected according to the topography of the components ( claim 1 , ) to be joined such that the membrane () claim 1 , in the contacting operating condition claim 1 , applies at least approximately the same contact pressure onto the components ( claim 1 , ) claim 1 , regardless of any differences in ...

SOLDERING A CONDUCTOR TO AN ALUMINUM METALLIZATION

A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material. 1. A method of soldering a conductor to an aluminum metallization , the method comprising:substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer;applying a flux material to the substitute metal oxide layer or to the substitute metal alloy oxide layer; andsoldering the conductor to the aluminum metallization using a solder material.2. The method of claim 1 , wherein the flux material is applied during soldering the conductor to the aluminum metallization.3. The method of claim 1 , wherein a substitute metal of the substitute metal oxide layer is one of Zn claim 1 , Cr claim 1 , Cu claim 1 , Pb claim 1 , or Sn.4. The method of claim 3 , wherein substituting comprises depositing the substitute metal over the aluminum oxide layer by an electrochemical deposition process.5. The method of claim 3 , wherein substituting comprises depositing the substitute metal over the aluminum oxide layer by an electroless deposition process.6. The method of claim 1 , wherein a substitute metal alloy of the substitute metal alloy oxide layer comprises at least two of the elements Zn claim 1 , Cr claim 1 , V claim 1 , Cu claim 1 , Pb claim 1 , Sn claim 1 , and Mo.7. The method of claim 6 , wherein substituting comprises depositing the substitute metal alloy over the aluminum oxide layer by an electrochemical deposition process.8. The method of claim 6 , wherein substituting comprises depositing the ...

Mounting method

A mounting method of mounting chips on a substrate includes a temporarily-bonding process, and a main-bonding process. Temporarily-bonding process is to perform a first basic process, repeatedly depending on the number of the chips. First basic process includes a first step and a second step. First step is to align, on a first metal layer of the substrate, a second metal layer of each chip. Second step is to temporarily bond each chip by subjecting the first and second metal layers to solid phase diffusion bonding. Main-bonding process is to perform a second basic process, repeatedly depending on the number of the chips. Second basic process includes a third step and a fourth step. Third step is to recognize a position of each chip temporarily mounted on the substrate. Fourth step is to firmly bond each chip by subjecting the first and second metal layers to liquid phase diffusion bonding.

POWER MODULE SUBSTRATE WITH Ag UNDERLAYER AND POWER MODULE

A power module substrate with a Ag underlayer of the invention includes: a circuit layer that is formed on one surface of an insulating layer; and a Ag underlayer that is formed on the circuit layer, in which the Ag underlayer is composed of a glass layer that is formed on the circuit layer side and a Ag layer that is formed by lamination on the glass layer, and regarding the Ag underlayer, in a Raman spectrum obtained by a Raman spectroscopy with incident light made incident from a surface of the Ag layer on a side opposite to the glass layer, when a maximum value of intensity in a wavenumber range of 3,000 cm −1 to 4,000 cm −1 indicated by I A , and a maximum value of intensity in a wavenumber range of 450 cm −1 to 550 cm −1 is indicated by I B , I A /I B is 1.1 or greater.

CMOS-MEMS INTEGRATION BY SEQUENTIAL BONDING METHOD

Methods for bonding two wafers are disclosed. In one aspect, a first wafer includes an integrated circuit and the second wafer including a MEMS device. The method comprises depositing a bond pad on a metal on the first wafer and sequentially bonding the first wafer to the second wafer utilizing first and second temperatures. The second wafer is bonded to the bond pad at the first temperature and the bond pad and the metal are bonded at the second temperature. In another aspect, a first wafer including an integrated circuit, the second wafer includes a MEMS device. The method comprises depositing a bond pad on a metal on one of the first wafer and the second wafer and bonding the first wafer to the second wafer at a first temperature via a direct bond interface. The method includes bonding the bond pad to the metal at a second temperature. 1. A method for bonding a first wafer and a second wafer , comprising:depositing a bond pad on a metal on the first wafer, the first wafer including an integrated circuit, and the second wafer including a MEMS device; andsequentially bonding the first wafer to the second wafer utilizing first and second temperatures; wherein the second wafer is bonded to the bond pad at the first temperature and wherein the bond pad and the metal are bonded at the second temperature.2. The method of claim 1 , wherein the sequential bonding step comprises:bonding the bond pad and the second wafer at a temperature not to exceed 300° C.; andbonding the bond pad and the metal to form a eutectic bond at a temperature greater than 420° C.3. The method of claim 1 , wherein the first temperature is less than the second temperature.4. The method of claim 1 , wherein the first temperature is lesser than 400° C. and the second temperature is greater than 400° C.5. The method of claim 1 , wherein the bond pad comprises a germanium bond pad and the metal comprises aluminum.6. The method of claim 1 , wherein the bond between the germanium bond pad and the ...

SEMICONDUCTOR MODULE BONDING WIRE CONNECTION METHOD

A method includes providing a subassembly having a circuit carrier with a first metallic surface portion, a first joining partner, which is integrally connected to the first metallic surface portion by means of a first connecting layer, and a second metallic surface portion. In a heat treatment, the second metallic surface portion is held uninterruptedly at temperatures which are higher than a minimum heat-treatment temperature of at least 300° C. Moreover, a second joining partner is provided. A fixed connection is produced between the second joining partner and the subassembly in that the second joining partner is integrally connected to the subassembly following completion of the heat treatment on the second surface portion.

Die bonding apparatus and die bonding method

A die bonding apparatus includes: a mounting base including a mounting area on which a first member is mounted; a heater arranged below the mounting base; a side wall configured to surround the mounting area; a collet configured to hold a second member by vacuum-chucking at an end portion; a lid including a hole, the lid being mounted on the side wall; a moving structure configured to move the collet to transport the second member held by the collet through the hole for bonding the second member to the first member; and a gas-supplying tube arranged on the side wall and configured to supply a heating gas to a heating space formed by the side wall and the lid. The lid contains a material capable of: reflecting an infrared radiation caused by the heater and the heating gas; or absorbing and re-radiating the infrared radiation.

Cmos-mems integration by sequential bonding method

Methods for bonding two wafers are disclosed. In one aspect, a first wafer includes an integrated circuit and the second wafer including a MEMS device. The method comprises depositing a bond pad on a metal on the first wafer and sequentially bonding the first wafer to the second wafer utilizing first and second temperatures. The second wafer is bonded to the bond pad at the first temperature and the bond pad and the metal are bonded at the second temperature. In another aspect, a first wafer including an integrated circuit, the second wafer includes a MEMS device. The method comprises depositing a bond pad on a metal on one of the first wafer and the second wafer and bonding the first wafer to the second wafer at a first temperature via a direct bond interface. The method includes bonding the bond pad to the metal at a second temperature.

Apparatus for especially thermally joining micro-electromechanical parts

본 발명은 프로세스 챔버(8)에서 마이크로 전자기계 부품(2, 3)들을 특히 열에 의해 결합하는 장치에 관한 것으로, 그 장치는 결합될 부품(2, 3)들 중 적어도 하나의 제1 부품(2)을 수용하는 하부 지지 플레이트(11)와, 결합될 부품(2, 3)들 중 적어도 하나의 제2 부품(3) 상에 적어도 하나의 제1 부품(2)의 방향으로 압력을 인가하는 프레싱 장치(15)를 구비한다. 그 프레싱 장치(15)에는 적어도 하나의 제2 부품(3)과 접촉하도록 마련된 팽창 가능 맴브레인(19)이 구비된다. 유체 압력, 특히 가스 압력이 결합될 부품(2, 3)들과는 반대측에서 맴브레인(19) 상에 인가될 수 있다.

Method for coating substrates and method for bonding substrates

Joined body, substrate for power module provided with heat sink, heat sink, method for manufacturing joined body, method for manufacturing substrate for power module provided with heat sink, and method for manufacturing heat sink

알루미늄 합금으로 이루어지는 알루미늄 부재와, 구리, 니켈 또는 은으로 이루어지는 금속 부재가 접합된 접합체로서, 알루미늄 부재는, Si 농도가 1 mass％ 이상 25 mass％ 이하인 범위 내로 된 알루미늄 합금으로 구성되어 있고, 알루미늄 부재와 금속 부재의 접합부에는 Ti 층이 형성되어 있고, 알루미늄 부재와 Ti 층, 및 Ti 층과 금속 부재가, 각각 고상 확산 접합되어 있다. A joined body in which an aluminum member made of an aluminum alloy and a metal member made of copper, nickel or silver are joined, wherein the aluminum member is composed of an aluminum alloy having a Si concentration within a range of 1 mass% or more and 25 mass% or less, and the aluminum member A Ti layer is formed in the junction of the metal member and the aluminum member, and the Ti layer and the metal member are solid-phase diffusion bonded to each other.

Batch diffusion soldering and electronic devices produced by batch diffusion soldering

A method of batch soldering includes: forming a soldered joint between a metal region of a first semiconductor die and a metal region of a substrate using a solder preform via a soldering process which does not apply pressure directly to the first semiconductor die, the solder preform having a maximum thickness of 30 μm and a lower melting point than the metal regions; setting a soldering temperature of the soldering process so that the solder preform melts and fully reacts with the metal region of the first semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the preform melting point and the soldering temperature; and soldering a second semiconductor die to the same or different metal region of the substrate, without applying pressure directly to the second semiconductor die.

Method for coating and bonding substrates

본 발명은 제 1 확산 본드 층(5)이 제 1 표면(1o)에 평행인 방향으로 1㎛ 미만의 평균 결정립 지름 H를 갖는 결정립 표면을 형성하도록, 제 1 기판(1)의 제 1 표면(1o) 상에 제 1 확산 본드 층(5)을 형성하는 제 1 물질을 증착하는, 제 1 확산 본드 층(5)으로 제 1 기판(1)을 코팅하는 방법과 관련된다. 덧붙여, 본 발명은 이러한 방식으로 코팅된 제 1 기판(1)을 제 2 확산 본드 층(4)을 갖는 제 2 기판(3)에 본딩하기 위한 방법과 관련되며, - 제 1 기판(1)의 제 1 확산 본드 층(5)을 제 2 기판(3)의 제 2 확산 본드 층에 접촉시키는 단계, - 제 1 기판(1)과 제 2 기판(3) 사이에 영구 금속 확산 본드를 형성하기 위해 기판(1, 3)을 압착시키는 단계를 포함한다. The present invention is characterized in that the first diffusion bond layer 5 is formed on the first surface 1 of the first substrate 1 so as to form a crystal grain surface having an average crystal grain diameter H of less than 1 mu m in a direction parallel to the first surface 1o (1) with a first diffusion bond layer (5) which deposits a first material forming a first diffusion bond layer (5) on the first diffusion bond layer (1o). In addition, the invention relates to a method for bonding a first substrate 1 coated in this way to a second substrate 3 having a second diffusion bond layer 4, - contacting the first diffusion bond layer (5) of the first substrate (1) with the second diffusion bond layer of the second substrate (3) - pressing the substrate (1, 3) to form a permanent metal diffusion bond between the first substrate (1) and the second substrate (3).

Method for bonding substrates

本发明涉及一种将第一至少大致透明衬底(1)的第一接触面(3)接合至第二至少大致透明衬底(2)的第二接触面(4)的方法，在所述接触面的至少一者上使用氧化物来进行接合，在第一及第二接触面(3、4)上由该氧化物形成至少大致透明的连接层(14)，其具有：至少10e1 S/cm 2 的电导率(测量：四点法，相对于300K的温度)及大于0.8的光透射率(针对400 nm至1500 nm的波长范围)。

Semiconductor device with an electrode structure comprising an aluminium or aluminium alloy layer with {110} texture, method of manufacturing said semiconductor device and power conversion device comprising said semiconductor device

A semiconductor device (200, 300, 400) includes a semiconductor substrate (108, 208) in which a semiconductor element (150) is formed, an electrode structure (151, 202, 207) provided on a first surface (108d) of the semiconductor substrate (108, 208) to be electrically connected to the semiconductor element (150) and in which a first Al metal layer (105) composed of Al or Al alloy, a Cu diffusion-prevention layer (107) composed of e.g. Ti, TiN, TiW or W, a second Al metal layer (106) composed of Al or Al alloy and a Ni, Cu or Cu alloy layer (104) are formed in this order, and a conductive member (102) which is bonded to the electrode structure (151, 202, 207) via a sintered copper layer (103) disposed on a surface (104a) of the Ni, Cu or Cu alloy layer (104). In this semiconductor device, a crystal plane orientation of Al crystal grains on a surface (106a) of the second Al metal layer (106) is principally on the (110) plane. The semiconductor device (200) may comprise a second electrode structure (152) on the second surface (108e) of the semiconductor substrate (108), also formed of the layers (105), (107), (106) and (104) and bonded to a conductive member (102) via a sintered copper layer (103). Alternatively, the semiconductor device (300, 400) may comprise a plurality of semiconductor elements such as transistors, diodes and resistive elements formed on a semiconductor LSI chip (201, 205, 206) and a plurality of input/output electrode pads (202, 207) each formed of the layers (105), (107), (106) and (104). The LSI chip (201, 205, 206) may be bonded to another semiconductor LSI chip (205, 206), also having electrode pads (202, 207) formed of the layers (105), (107), (106) and (104), and/or to a conductive member (102) via a sintered copper layer (103).

Sintered compound starting material and method for producing the sintered compound

Der erfindungsgemäße Ausgangswerkstoff einer Sinterverbindung umfasst Partikel, die zumindest anteilig eine organische Metallverbindung und/oder ein Edelmetalloxid enthalten, wobei die organische Metallverbindung und/oder das Edelmetalloxid bei einer Temperaturbehandlung des Ausgangswerkstoffes in das elementare Metall und/oder Edelmetall umgewandelt wird. Kennzeichnend für die Erfindung ist, dass die Partikel eine Beschichtung enthaltend ein Reduktionsmittel aufweisen, mittels welchem die Reduktion der organischen Metallverbindung und/oder des Edelmetalloxids zu dem elementaren Metall und/oder Edelmetall bei einer Temperatur unterhalb der Sintertemperatur des elementaren Metalls und/oder Edelmetalls erfolgt. The starting material of a sintered compound according to the invention comprises particles which at least partially contain an organic metal compound and / or a noble metal oxide, the organic metal compound and / or the noble metal oxide being converted into the elemental metal and / or noble metal during a temperature treatment of the starting material. It is characteristic of the invention that the particles have a coating containing a reducing agent, by means of which the reduction of the organic metal compound and / or the noble metal oxide to the elemental metal and / or noble metal takes place at a temperature below the sintering temperature of the elemental metal and / or noble metal .

The power module substrate and its manufacturing method, Radiator and its preparation method of conjugant and its manufacturing method, included radiator

本发明提供一种解决了铝部件和金属部件的接合可靠性降低的技术问题的接合体。本发明的接合体为接合由铝合金构成的铝部件与由铜、镍或银构成的金属部件而成的接合体，铝部件由Si浓度在1质量％以上且25质量％以下的范围内的铝合金构成，在铝部件与金属部件的接合部形成有Ti层，铝部件与Ti层及Ti层与金属部件分别被固相扩散接合。这样的接合体适合于大功率控制用功率半导体元件。

Method for manufacturing soldered products

【課題】治具を用いることなく半田付けを行う半田付け製品の製造方法を得ること。【解決手段】本願の半田付け製品の製造方法は、半田と、半田を仮止めする仮固定剤とを提供する提供工程と；仮固定剤で半田を半田付け対象物に仮止めする仮止工程と；半田を仮止めした半田付け対象物を、真空中に置くか、または、半田が溶融する温度よりも低い所定の温度に加熱して、仮固定剤を気化させ半田と半田付け対象物の間に間隙を生じさせる気化工程と；気化工程に並行して、またはその後に、半田が溶融する温度よりも低い所定の温度で、気化工程により残された半田と半田付け対象物を還元ガスで還元する還元工程と；還元工程の後に、半田付け対象物を半田が溶融する温度以上の所定の温度に加熱して半田を溶融する半田溶融工程を備える。【選択図】図１ A method for manufacturing a soldered product in which soldering is performed without using a jig is provided. A method of manufacturing a soldered product of the present application includes a providing step of providing solder and a temporary fixing agent for temporarily fixing the solder; and a temporary fixing step of temporarily fixing the solder to the soldering object with the temporary fixing agent. And placing the soldering object temporarily fixed with solder in a vacuum or heating to a predetermined temperature lower than the temperature at which the solder melts to vaporize the temporary fixing agent and A vaporizing step that creates a gap therebetween; parallel to or after the vaporizing step, the solder remaining in the vaporizing step and the soldering object are reduced with a reducing gas at a predetermined temperature lower than the temperature at which the solder melts. A reduction step of reducing; and a solder melting step of melting the solder by heating the soldering object to a predetermined temperature equal to or higher than a temperature at which the solder melts after the reduction step. [Selection] Figure 1

Joined body, substrate for power module provided with heat sink, heat sink, method for manufacturing joined body, method for manufacturing substrate for power module provided with heat sink, and method for manufacturing heat sink

Bonding material manufacturing method, bonding method, and power semiconductor device

Power module substrate and power module with Ag underlayer

Method for bonding substrates

The present invention relates to a method for bonding a first contact area (3) of a first, at least predominantly transparent substrate (1) to a second contact area (4) of a second, at least predominantly transparent substrate (2) wherein an oxide is used at at least one of the contact areas for bonding, from which oxide an at least predominantly transparent connecting layer (14) having: an electrical conductivity of at least 10e1 S/cm 2 (measurement: four-point method, relative to temperature of 300K) and an optical transmittance of greater than 0.8 (for a wavelength range of 400 nm to 1500 nm) is formed at the first and second contact areas (3 4).

Semiconductor device bonding material

Semiconductor Device Manufacturing Method And Soldering Weight

本发明提供一种半导体装置的制造方法以及用于该制造方法的焊接用压块,其在制造功率半导体模块的焊接工序中，抑制在接合面的熔融焊锡中产生厚度不均及空隙，并且即使在焊接构件上配置有布线等上部结构物，上部结构物与焊接用压块也互不干扰而使稳定的焊接成为可能。在因基材的翘曲而在基材接合面上出现高度差时，重心从压块主体的中心偏移，使用只在压块主体的与焊接物面对的一侧的边缘部配置有腿的焊接用压块，在基材主面的预定范围的边缘部中因翘曲而高度相对变低的一侧的边缘部配置阻隔材料，并且以使重心位于因翘曲而高度相对变低的一侧的方式将压块载置于焊接物上，然后实施使焊锡熔融的升温处理。

Dual-phase intermetallic interconnection structure and method of fabricating the same

一种双相介金属互连结构及其制作方法。所述双相介金属互连结构介于芯片与载板之间，包括第一介金属相、第二介金属相、第一焊接金属层以及第二焊接金属层。第二介金属相包覆第一介金属相，且第一介金属相与第二介金属相含有不同的高熔点金属。第一焊接金属层与第二焊接金属层分别配置于第二介金属相的相对两侧，其中第一介金属相是用以填补第二介金属相形成时产生的微孔洞缺陷。

Semiconductor device

A semiconductor chip (3) is bonded to an upper surface of an electrode substrate (1) via a first solder (2). A lead frame (5) is bonded to an upper surface of the semiconductor chip (3) via a second solder (4). Between the electrode substrate (1) and the semiconductor chip (3), an intermediate plate (6) is provided in the first solder (2). The yield strength of the intermediate plate (6) is higher than that of the electrode substrate (1) and that of the first solder (2) within the service temperature range of the semiconductor device.

Fluxless bonding of microelectronic chips

Metal joining structure using metal nanoparticles and metal joining method and metal joining material

The present invention can give a joining structure using metal nanoparticles to join the same types or different types of metal where when one surface metal is Al based, the parts are joined through a joining layer containing Ni nanoparticles, whereby a good joining strength is obtained. Further, by using two joining layers ( 6, 8 ) including metal nanoparticles to sandwich metal foil ( 7 ) so as to form a joining layer and joining the same type or different types of surface metals ( 3 - 4 ) through this joining layer, it is possible to ease the thermal stress due to the difference in amounts of thermal expansion of joined members which have two surface metals.

SUBSTRATE FOR POWER MODULE WITH Ag UNDERLAYER AND POWER MODULE

본 발명의 Ag 하지층이 형성된 파워 모듈용 기판은, 절연층의 일방의 면에 형성된 회로층과, 상기 회로층에 형성된 Ag 하지층을 구비한 Ag 하지층이 형성된 파워 모듈용 기판으로서, 상기 Ag 하지층은, 상기 회로층측에 형성된 유리층과, 이 유리층에 적층 형성된 Ag 층으로 이루어지고, 상기 Ag 하지층은, 상기 Ag 층의 상기 유리층과는 반대측의 면으로부터 입사광을 입사시켜, 라만 분광법에 의해 얻어진 라만 스펙트럼에 있어서, 3000 ㎝ -1 내지 4000 ㎝ -1 의 파수 범위에 있어서의 강도의 최고치를 I A 로 하고, 450 ㎝ -1 내지 550 ㎝ -1 의 파수 범위에 있어서의 강도의 최고치를 I B 로 했을 때, I A /I B 가 1.1 이상인 것을 특징으로 한다.

Chip assembly

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

Sintering silver paste material and method for bonding semiconductor chip

An object of the present invention is to provide a composition of a sintering Ag paste which can metallically bond to a nonprecious metal member with high strength as well as to a precious metal member, in a sintering Ag paste which metallically bonds to a metal at a low temperature, and to provide a bonding method to obtain a joint part having high strength. The sintering Ag paste is a material containing a solution of an organic silver complex that is easily decomposed by heat regardless of an atmosphere. Furthermore, the bonding method includes: metallizing a face of a nonprecious metal with Ag in a non-oxidizing atmosphere in a step prior to sintering Ag particles; and then sintering the Ag particles in an oxidizing atmosphere.

Copper paste for bonding, method for producing bonded body, and method for producing semiconductor device

本发明的接合用铜糊料含有金属粒子和分散介质，金属粒子含有体积平均粒径为0.12μm以上且0.8μm以下的亚微米铜粒子和体积平均粒径为2μm以上且50μm以下的微米铜粒子，亚微米铜粒子的含量及微米铜粒子的含量之和以金属粒子的总质量为基准计为80质量％以上，亚微米铜粒子的含量以亚微米铜粒子的质量及微米铜粒子的质量之和为基准计为30质量％以上且90质量％以下。

Grafting material, joint method and power semiconductor device

本发明的目的在于得到同时实现耐热性和应力缓和性的接合，设为如下结构：一种板状的接合材料(1)，通过在与作为接合对象的金属部件(例如表面层(2f)、(3f))接触的状态下进行加热，从而在金属部件(例如作为材料是金、银、铜)中形成利用固相扩散反应的银的扩散层(Ld2)、(Ld3)，与金属部件接合，所述接合材料含有铋与银的合金，其中，所述接合材料含有1质量％以上且5质量％以下的铋。

Wafer stack protection seal

A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing first and second wafers with top and bottom surfaces. The wafers include edge and non-edge regions, and the first wafer includes devices formed in the non-edge region. A first protection seal may be formed at the edge region of the first wafer. The first and second wafers may further be bonded to form a device stack. The protection seal in the device stack contacts the first and second wafers to form a seal, and protects the devices in subsequent processing.

Device for in particular thermal connection of microelectromechanical components

Gegenstand der Erfindung ist eine Vorrichtung zum insbesondere thermischen Verbinden mikro-elektromechanischer Bauteile (2, 3) in einem Prozessraum (8), mit einer unteren Auflageplatte (11) zur Aufnahme wenigstens eines ersten Bauteils (2) der zu verbindenden Bauteile (2, 3) und mit einer Anpresseinrichtung (15) zur Druckbeaufschlagung wenigstens eines zweiten Bauteils (3) der zu verbindenden Bauteile (2, 3) gegenüber dem wenigstens einen ersten Bauteil (2). Die Anpresseinrichtung (15) ist dabei mit einer zur Kontaktierung mit dem wenigsten einen zweiten Bauteil (3) vorgesehenen, dehnbaren Membran (19) ausgebildet. Diese Membran (19) ist auf ihrer den zu verbindenden Bauteilen (2, 3) abgewandten Seite mit Fluiddruck, insbesondere Gasdruck, beaufschlagbar. The invention relates to a device for in particular thermally connecting microelectromechanical components (2, 3) in a process chamber (8), with a lower support plate (11) for receiving at least a first component (2) of the components to be connected (2, 3 ) and with a pressing device (15) for pressurizing at least one second component (3) of the components to be connected (2, 3) relative to the at least one first component (2). The pressing device (15) is formed with a stretchable membrane (19) provided for contacting the at least one second component (3). This membrane (19) can be acted upon with fluid pressure, in particular gas pressure, on its side facing away from the components (2, 3) to be connected.

Metal paste for joints, assembly, production method for assembly, semiconductor device, and production method for semiconductor device

Provided is a metal paste for joints which contains metal particles and a linear or branched C1–20 monovalent aliphatic alcohol, and in which the metal particles include submicrometer copper particles having a volume mean diameter of 0.12–0.8 μm.

Power semiconductor device manufacturing method and power semiconductor device

銅ベース板（３）に対してメタルマスク（５１）が配置される。メタルマスク（５１）の複数の開口部（５３）に、はんだペースト（１５）を充填することによって、銅ベース板（３）の銅板（５ｂ、５ｃ、５ｄ）のそれぞれに、はんだペースト（１５）のパターンが形成される。はんだペースト（１５）のパターンに、半導体素子（９、１１）および導電部品（１３）が載置される。銅ベース板（３）に対してメタルマスク（５５）が配置される。次に、メタルマスク（５５）の複数の開口部（５７）に、はんだペースト（１７）を充填することによって、半導体素子（９、１１）および導電部品（１３）のそれぞれを覆うはんだペースト（１７）のパターンが形成される。対応するはんだペースト（１７）のパターンに接触するように、大容量中継基板（２１）が配置される。２００℃以上の温度条件のもとで熱処理を行うことによって、パワー半導体装置（１）が完成する。 A metal mask (51) is disposed on the copper base plate (3). By filling the plurality of openings (53) of the metal mask (51) with the solder paste (15), the solder paste (15) is applied to each of the copper plates (5b, 5c, 5d) of the copper base plate (3). Pattern is formed. The semiconductor element (9, 11) and the conductive component (13) are placed on the pattern of the solder paste (15). A metal mask (55) is disposed on the copper base plate (3). Next, the solder paste (17) covering each of the semiconductor element (9, 11) and the conductive component (13) by filling the plurality of openings (57) of the metal mask (55) with the solder paste (17). ) Pattern is formed. A large-capacity relay substrate (21) is arranged so as to contact the corresponding solder paste (17) pattern. By performing heat treatment under a temperature condition of 200 ° C. or higher, the power semiconductor device (1) is completed.

Method for bonding electronic component and method for manufacturing bonded body

Disclosed is a method for bonding an electronic component using a silver paste containing silver particles, the method including: applying a silver paste containing silver particles on a surface of a substrate and setting electronic components on the silver paste applied, heating in a reducing atmosphere at a temperature of lower than 300° C., and after heating in the reducing atmosphere, heating in an oxidizing atmosphere at a temperature of 300° C. or lower.

Joined body, substrate for power module provided with heat sink, heat sink, method for manufacturing joined body, method for manufacturing substrate for power module provided with heat sink, and method for manufacturing heat sink

알루미늄 합금으로 이루어지는 알루미늄 부재와, 구리, 니켈 또는 은으로 이루어지는 금속 부재가 접합된 접합체로서, 알루미늄 부재는, Si 농도가 1 mass％ 이상 25 mass％ 이하인 범위 내로 된 알루미늄 합금으로 구성되어 있고, 알루미늄 부재와 금속 부재의 접합부에는 Ti 층이 형성되어 있고, 알루미늄 부재와 Ti 층, 및 Ti 층과 금속 부재가, 각각 고상 확산 접합되어 있다.

Manufacturing method of power semiconductor device and power semiconductor device

Bonding device and bonding method

Sintering paste and use thereof for connecting components

The invention relates to a sintering paste consisting of: (A) 30 to 40 wt.% of silver flakes with an average particle size ranging from 1 to 20 µm, (B) 8 to 20 wt.% of silver particles with an average particle size ranging from 20 to 100 nm, (C) 30 to 45 wt.% of silver(I) oxide particles, (D) 12 to 20 wt.% of at least one organic solvent, (E) 0 to 1 wt.% of at least one polymer binder, and (F) 0 to 0.5 wt.% of at least one additive differing from the components (A) to (E).

Method for bonding a chip to a wafer

本発明は、前面側にチップ（３’）を含むベースウエハ（１）に複数のチップ（３）を結合する方法であって、前記チップ（３）が、前記ベースウエハ（１）の背面側で少なくとも一層に積層され、導電接続部が垂直に隣接するチップ（３、３’）間に組み立てられる方法に関連する。前記方法は、（ａ）前記ベースウエハ（１）の前面側（２）がキャリア（５）に固定される段階、（ｂ）チップ（３）の少なくとも一層が前記ベースウエハ（１）の背面側（６）の画定された位置に配置される段階、（ｃ）前記キャリア（５）に固定される前記ベースウエハ（１）の前記チップ（３、３’）が熱処理される段階を含む。前記方法は、段階（ｃ）の前に、前記ベースウエハ（１）のチップ（３’）が前記ベースウエハの積層チップ部分（１ｃ）に少なくとも分離されることによって特徴付けられる。

Electronic device and method for manufacturing an electronic device

Ein Ausführungsverfahren zur Herstellung von elektronischen Vorrichtungen, die zwei von einer Metallschicht verbundene Bauteile aufweisen, enthält das Auftragen einer Metallschicht auf jedes Bauteil und das Verbinden der Metallschichten, sodass eine einzelne Metallschicht gebildet wird. An embodiment method for manufacturing electronic devices having two components joined by a metal layer includes applying a metal layer to each component and bonding the metal layers to form a single metal layer.

The manufacture method of engagement copper thickener, the manufacture method of conjugant and semiconductor device

本发明的接合用铜糊料含有金属粒子和分散介质，金属粒子含有体积平均粒径为0.12μm以上且0.8μm以下的亚微米铜粒子和体积平均粒径为2μm以上且50μm以下的微米铜粒子，亚微米铜粒子的含量及微米铜粒子的含量之和以金属粒子的总质量为基准计为80质量％以上，亚微米铜粒子的含量以亚微米铜粒子的质量及微米铜粒子的质量之和为基准计为30质量％以上且90质量％以下。

Copper paste for pressureless bonding, bonded body and semiconductor device

A copper paste for pressureless bonding is a copper paste for pressureless bonding, containing: metal particles; and a dispersion medium, in which the metal particles include sub-micro copper particles having a volume average particle diameter of greater than or equal to 0.01 μm and less than or equal to 0.8 μm, and micro copper particles having a volume average particle diameter of greater than or equal to 2.0 μm and less than or equal to 50 μm, and the dispersion medium contains a solvent having a boiling point of higher than or equal to 300° C., and a content of the solvent having a boiling point of higher than or equal to 300° C. is greater than or equal to 2 mass % on the basis of a total mass of the copper paste for pressureless bonding.

Copper paste for joining, method for producing joined body, and method for producing semiconductor device

Provided is copper paste for joining including metal particles, and a dispersion medium. The metal particles include sub-micro copper particles having a volume-average particle size of 0.12 µm to 0.8 µm, and micro copper particles having a volume-average particle size of 2 µm to 50 µm, a sum of the amount of the sub-micro copper particles contained and the amount of the micro copper particles contained is 80% by mass or greater on the basis of a total mass of the metal particles, and the amount of the sub-micro copper particles contained is 30% by mass to 90% by mass on the basis of a sum of a mass of the sub-micro copper particles and a mass of the micro copper particles.

A method for manufacturing a power semiconductor device, a sheet for hot pressing and a thermosetting resin composition for hot pressing.

配線基板及び該配線基板に搭載されたパワー半導体素子を備えるパワー半導体装置を製造する方法が開示される。当該方法は、配線基板とパワー半導体素子と金属粒子を含む焼結材とを有する積層体を、ステージ及び圧着ヘッドで挟むことによって加熱及び加圧し、それにより、焼結材の焼結により形成された焼結金属層を介して配線層と電極とを電気的に接続する工程を備える。積層体と圧着ヘッドとの間に、熱硬化性樹脂層を有する熱プレス用シートを介在させた状態で、積層体が加熱及び加圧される。 A method for manufacturing a wiring board and a power semiconductor device including a power semiconductor element mounted on the wiring board is disclosed. In this method, a laminate having a wiring substrate, a power semiconductor element, and a sintered material containing metal particles is heated and pressurized by sandwiching it between a stage and a crimping head, and thereby formed by sintering the sintered material. A step of electrically connecting the wiring layer and the electrode via the sintered metal layer is provided. The laminate is heated and pressurized with a thermosetting sheet having a thermosetting resin layer interposed between the laminate and the crimping head.

Semiconductor module

本发明涉及一种半导体模块。本发明涉及一种用于制造电子模块的方法。对此，提供组件（99），该组件具有：电路载体（3），该电路载体具有金属的第一表面区段（311）；第一接合配对件（1），该第一接合配对件借助于第一连接层（41）与金属的第一表面区段（311）以材料决定的方式连接；和金属的第二表面区段（111；312）。在热处理中，将金属的第二表面区段（111；312）不中断地保持在下述温度上，该温度高于至少为300℃的热处理最低温度。此外，提供第二接合配对件（2）。通过将第二接合配对件（2）在对第二表面区段（111；312）进行热处理结束之后以材料决定的方式与组件（99）连接，建立第二接合配对件（2）和组件（99）之间的牢固的连接。

Semiconductor device and method of forming it

Semiconductor laser mounting for improved frequency stability

半导体激光器芯片（302）的第一接触表面（310）可形成为具有目标表面粗糙度，该目标表面粗糙度选择为具有基本上小于要施加至第一接触表面（310）的金属阻挡层的阻挡层厚度的最大峰谷高度。具有该阻挡层厚度的金属阻挡层可施加至第一接触表面；以及利用焊料组成物（306），通过将焊接组成物加热至小于发生金属阻挡层溶解进入焊接组成物的阈值温度，可以将半导体激光器芯片（302）沿第一接触表面（310）焊接至载体安装座。还公开了有关的系统、方法、制造的制品等等。

There is power module substrate and the power model of Ag basal layer

本发明的具有Ag基底层的功率模块用基板，其具备形成于绝缘层的一个表面的电路层及形成于所述电路层的Ag基底层，所述具有Ag基底层的功率模块用基板的特征在于，所述Ag基底层包括形成于所述电路层侧的玻璃层和层压形成于该玻璃层的Ag层，所述Ag基底层中，从所述Ag层的与所述玻璃层相反侧的表面射入入射光，通过拉曼光谱法得到的拉曼光谱中，将3000cm ‑1 至4000cm ‑1 的波数范围中的强度最高值设为I A ，将450cm ‑1 至550cm ‑1 的波数范围中的强度最高值设为I B 时，I A /I B 为1.1以上。

Method for bonding of chips on wafers

Method for bonding of a plurality of chips onto a base wafer which contains chips on the front, the chips being stacked in at least one layer on the back of the base wafer and electrically conductive connections are established between the vertically adjacent chips, with the following steps: a) fixing of the front of the base wafer on a carrier, b) placing at least one layer of chips in defined positions on the back of the base wafer, and c) heat treatment of the chips on the base wafer fixed on the carrier, characterized in that prior to step c) at least partial separation of the chips of the base wafer into separated chip stack sections of the base after takes place.

Method for producing a connection between a semiconductor component and semiconductor module resistant to high temperatures and temperature changes by means of a temperature impinging process

本发明涉及一种用于通过温度碰撞过程产生在半导体部件和半导体模块之间耐高温和温度变化的连接的方法，其中金属粉末悬浮体应用到半导体模块区域以连接半导体模块；悬浮体层被干燥，排出挥发成分气体并且产生多孔层；多孔层是预密封的而没有完全烧结发生穿过悬浮体层；并且，为了实现半导体模块从基底，进一步的半导体或者相互连接装置的组到连接配合件的坚固的，电地和热地传导连接，该连接是通过温度增加没有压缩产生的烧结的连接并且由干燥的金属粉末悬浮体构成，该金属粉末悬浮体已经经历与连接配合件在预压缩步骤中的第一移动安全接触和利用温度烧结在0压下固化。

Substrate for power module with silver underlayer and power module

Semiconductor device and power conversion device

Halbleitervorrichtung (100), die umfasst:ein Halbleiterelement (150); undeine erste Elektrode (112), die auf einer ersten Oberfläche (108d) des Halbleiterelements (150) gebildet ist, wobeidie erste Elektrode (112) eine Stapelstruktur aufweist, die eine erste stromlos Ni-plattierte Schicht (104) enthält,die erste stromlos Ni-plattierte Schicht (104) Nickel (Ni) und Phosphor (P) als eine Zusammensetzung enthält, undeine Phosphor-(P-)Konzentration der ersten stromlos Ni-plattierten Schicht 2,5 Gew.-% bis einschließlich 6 Gew.-% beträgt, Ni (111) und Ni (200) im Röntgenbeugungsprofil der ersten stromlos Ni-plattierte Schicht (104) enthalten sind, und eine Kristallisationsrate von Ni3P in der ersten stromlos Ni-plattierten Schicht O % bis einschließlich 20 % beträgt. A semiconductor device (100) comprising: a semiconductor element (150); and a first electrode (112) formed on a first surface (108d) of said semiconductor element (150), said first electrode (112) having a stacked structure including a first electroless Ni-plated layer (104), the first electroless Ni - the plated layer (104) contains nickel (Ni) and phosphorus (P) as a composition, and a phosphorus (P) concentration of the first electroless Ni plated layer is 2.5 wt% to 6 wt% inclusive , Ni(111) and Ni(200) are included in the X-ray diffraction profile of the first electroless Ni plating layer (104), and a crystallization rate of Ni3P in the first electroless Ni plating layer is 0% to 20% inclusive.

Assembly jig for a semiconductor device and assembly method for a semiconductor device

In aspects of the assembly jig and method of the invention, when a packaging substrate is curved concaving upward at temperatures of melting solder, the gap between the assembly jig and the packaging substrate can be made smaller than the dimension of the sum of the thickness of the semiconductor chip and the thickness of the melted solder by allowing a part of the bottom surface of the chip positioning piece to become always, or substantially always, in contact with the upper surface of the packaging substrate owing to the weight of the chip positioning jig itself. As a consequence, the semiconductor chip does not slip aside out of the opening of the chip positioning piece. Therefore, the semiconductor chip can be positioned accurately on the packaging substrate.

Bonding structure, bonding material, and bonding method

Device and method for bonding substrates

A device for bonding of one bond side of a first substrate to one bond side of a second substrate, the device having one module group with a common working space which can be closed especially gastight to the environment, at least one bond module is connected in a sealed manner to the working space, and a movement apparatus for moving the first and second substrate in the working space. The module group has a reduction module which is connected, in a sealed manner to the working space for reducing the bond sides.

Diffusion soldering preform with varying surface profile

A method of soldering includes providing a substrate having a first metal joining surface, providing a semiconductor die having a second metal joining surface, providing a solder preform having a first interface surface and a second interface surface, arranging the solder preform between the substrate and the semiconductor die such that the first interface surface faces the first metal joining surface and such that the second interface surface faces the second metal joining surface, and performing a mechanical pressure-free diffusion soldering process that forms a soldered joint between the substrate and the semiconductor die by melting the solder preform and forming intermetallic phases in the solder. One or both of the first interface surface and the second interface surface has a varying surface profile that creates voids between the solder preform and one or both of the substrate and the semiconductor die before the melting of the solder preform.

Low profile high temperature double sided flip chip power packaging

A wire bondless, double flip chipped discrete power package including a base plate for structural support, heat spreading, and thermal connection, power substrate for electrical interconnection and isolation, lead frames for external connections, an upper substrate for topside electrical interconnection, and injection molded housing for mounting, isolation, and protection.

Engagement copper thickener, conjugant and semiconductor device without pressurization

本发明涉及一种无加压接合用铜糊料，其是包含金属粒子和分散介质的无加压接合用铜糊料，其中，金属粒子包含体积平均粒径为0.01μm以上且0.8μm以下的亚微米铜粒子和体积平均粒径为2.0μm以上且50μm以下的微米铜粒子，分散介质包含具有300℃以上的沸点的溶剂，且具有300℃以上的沸点的溶剂的含量以无加压接合用铜糊料的总质量为基准，为2质量％以上。

Semiconductor device having curved bonding leads and method of forming the same

Copper paste for joining, method for producing joined body, and method for producing semiconductor device

SEMICONDUCTOR MODULE

Die Erfindung betrifft ein Verfahren zur Herstellung eines Elektronikmoduls. Hierzu wird eine Baugruppe (99), die einen Schaltungsträger (3) mit einem ersten metallischen Oberflächenabschnitt (311) aufweist, einen ersten Fügepartner (1), der mittels einer ersten Verbindungsschicht (41) mit dem ersten metallischen Oberflächenabschnitt (311) stoffschlüssig verbunden ist, und einen zweiten metallischen Oberflächenabschnitt (111; 312). Bei einer Wärmebehandlung wird der zweite metallische Oberflächenabschnitt (111; 312) ununterbrochen auf Temperaturen gehalten, die höher sind als eine Wärmebehandlungsmindesttemperatur von wenigstens 300°C. Außerdem wird ein zweiter Fügepartner (2) bereitgestellt. Zwischen dem zweiten Fügepartner (2) und der Baugruppe (99) wird eine feste Verbindung hergestellt, indem der zweite Fügepartner (2) nach Abschluss der Wärmebehandlung an dem zweiten Oberflächenabschnitt (111; 312) stoffschlüssig mit der Baugruppe (99) verbunden wird. The invention relates to a method for producing an electronic module. For this purpose, an assembly (99) having a circuit carrier (3) with a first metallic surface portion (311), a first joining partner (1), which by means of a first connection layer (41) with the first metallic surface portion (311) is materially connected , and a second metallic surface portion (111; 312). In a heat treatment, the second metallic surface portion (111; 312) is continuously maintained at temperatures higher than a heat treatment minimum temperature of at least 300 ° C. In addition, a second joint partner (2) is provided. Between the second joining partner (2) and the assembly (99), a firm connection is established by the second joint partner (2) after completion of the heat treatment at the second surface portion (111, 312) is integrally connected to the assembly (99).

Sinter-bonding composition, sinter-bonding sheet, and dicing tape with sinter-bonding sheet

【課題】高密度の焼結層による焼結接合を低負荷条件で実現するのに適した焼結接合用組成物、焼結接合用シート、および、焼結接合用シート付きのダイシングテープを提供する。【解決手段】本発明の焼結接合用組成物は、導電性金属含有の焼結性粒子を含む。この焼結性粒子の平均粒径は２μｍ以下であり、且つ、当該焼結性粒子における粒径１００ｎｍ以下の粒子の割合は８０質量％以上である。本発明の焼結接合用シート１０は、このような焼結接合用組成物のなす粘着層を備える。本発明の焼結接合用シート付きダイシングテープＸは、このような焼結接合用シート１０およびダイシングテープ２０を備える。ダイシングテープ２０は、基材２１と粘着剤層２２とを含む積層構造を有し、焼結接合用シート１０はダイシングテープ２０の粘着剤層２２上に位置する。【選択図】図５

SUBSTRATE FOR POWER MODULE WITH Ag UNDERLAYER AND POWER MODULE

This substrate for a power module with an Ag underlayer is provided with a circuit layer formed on one surface of an insulation layer, and an Ag underlayer formed on the circuit layer. The substrate for the power module with the Ag underlayer is characterized in that the Ag underlayer comprises a glass layer formed on the circuit layer side, and an Ag layer superposed on the glass layer, and regarding a Raman spectrum obtained by Raman spectroscopy after causing incident light to enter the Ag underlayer from a surface on the opposite side to the glass layer of the Ag layer, I A /I B is 1.1 or more where I A is the highest value of intensity in a wavenumber range of 3000-4000 cm -1 , and I B is the highest value of intensity in a wavenumber range of 450-550 cm -1 .

Method for bonding metal bodies and bonding structure for metal bodies

Semiconductor device bonding material

Provided is a semiconductor device wherein an internal bonding section does not melt at the time of substrate mounting by means of filling the hole portions of a porous metal body having a mesh structure with an Sn or Sn-based solder alloy and using a bonding material obtained by covering the surface thereof for internal bonding of the semiconductor device.

Conductor is welded to aluminum metallization

一种将导体焊接到铝金属化物的方法包括：用替代金属氧化物层或替代金属合金氧化物层替代所述铝金属化物上的铝氧化物层。然后，至少部分地还原所述替代金属氧化物层中的或所述替代金属合金氧化物层中的替代金属氧化物。使用焊料材料将所述导体焊接到所述铝金属化物。

Copper paste for joining, method for producing joined body, and method for producing semiconductor device

Provided is copper paste for joining including metal particles, and a dispersion medium. The metal particles include sub-micro copper particles having a volume-average particle size of 0.12 µm to 0.8 µm, and micro copper particles having a volume-average particle size of 2 µm to 50 µm, a sum of the amount of the sub-micro copper particles contained and the amount of the micro copper particles contained is 80% by mass or greater on the basis of a total mass of the metal particles, and the amount of the sub-micro copper particles contained is 30% by mass to 90% by mass on the basis of a sum of a mass of the sub-micro copper particles and a mass of the micro copper particles.

Heat bonding sheet and dicing tape with heat bonding sheet

【課題】接合対象物の位置ずれを抑制しつつ焼結接合を実現するのに適した加熱接合用シート、および、そのような加熱接合用シートを伴うダイシングテープを、提供する。【解決手段】本発明の加熱接合用シート（１０）は、導電性金属含有の焼結性粒子を含む粘着層（１１）を備え、７０℃、０.５ＭＰａ、および１秒間の圧着条件にて粘着層（１１）が５ｍｍ角のサイズで圧着された銀平面に対する当該粘着層（１１）の７０℃でのせん断接着力が０.１ＭＰａ以上である。本発明の加熱接合用シート付きダイシングテープは、基材および粘着剤層を含む積層構造を有するダイシングテープと、粘着剤層上の加熱接合用シート（１０）とを備える。【選択図】図１

Engagement metal thickener, conjugant and its manufacturing method and semiconductor device and its manufacturing method

本发明的接合用金属糊料含有金属粒子和碳数为1～20的直链状或支链状的一元脂肪族醇，金属粒子含有体积平均粒径为0.12～0.8μm的亚微米铜粒子。

Semiconductor device member, method of manufacturing semiconductor device, and semiconductor device member

Solder joint

信頼性の高いはんだ接合部を提供する。Ｓｎを主成分とし、Ａｇ及び／またはＳｂ及び／またはＣｕをさらに含むはんだ材が溶融されたはんだ接合層と、前記はんだ接合層と接する面にＮｉ−Ｐ−Ｃｕめっき層を備える被接合体とを含むはんだ接合部であって、前記Ｎｉ−Ｐ−Ｃｕめっき層が、Ｎｉを主成分とし、０．５質量％以上であって、８質量％以下のＣｕと、３質量％以上であって、１０質量％以下のＰとを含み、前記Ｎｉ−Ｐ−Ｃｕめっき層が、前記はんだ接合層との界面に微結晶層を有し、前記微結晶層が、ＮｉＣｕＰ三元合金の微結晶を含む相と、（Ｎｉ，Ｃｕ）３Ｐの微結晶を含む相と、Ｎｉ３Ｐの微結晶を含む相とを備える、はんだ接合部。 Provide a highly reliable solder joint. A solder joint layer in which a solder material containing Sn as a main component and further containing Ag and / or Sb and / or Cu is melted, and a bonded body having a Ni—P—Cu plating layer on a surface in contact with the solder joint layer. The Ni-P-Cu plating layer contains Ni as a main component, and has 0.5% by mass or more, 8% by mass or less of Cu, and 3% by mass or more. The Ni—P—Cu plating layer contains 10% by mass or less of P and has a microcrystal layer at the interface with the solder bonding layer, and the microcrystal layer is a microcrystal of NiCuP ternary alloy. A solder joint including a phase containing, a phase containing microcrystals of (Ni, Cu) 3P, and a phase containing microcrystals of Ni3P.

접합용 도전성 조성물 및 이것을 사용한 접합 구조및 그 제조 방법

접합용 도전성 조성물은, 구리 분말과 카르복실산이 혼합되어 이루어진다. 상기 카르복실산은 그 구조 중에 분지 탄소쇄를 갖는다. 구리 분말은, 주사형 전자 현미경에 의해 측정한 입도 분포 중 1㎛ 미만의 영역에 있어서의 누적 체적 50용량％의 체적 누적 입경 D 50 이 0.11㎛ 이상 1㎛ 미만의 제1 구리 입자와, 주사형 전자 현미경에 의해 측정한 입도 분포 중 1㎛ 이상의 영역에 있어서의 누적 체적 50용량％의 체적 누적 입경 D 50 이 1㎛ 이상 10㎛ 이하의 제2 구리 입자를 포함한다. 카르복실산의 함유량이, 상기 구리 분말 100질량부에 대하여 6질량부 이상 24질량부 이하이다.