Method for the wafer-level integration of shape memory alloy wires

The present invention relates to a method to attach a shape memory alloy wire to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. The present invention also relates to a device comprising a shape memory alloy wire attached to a substrate, where the wire is mechanically attached into a 3D structure on the substrate.

METHOD FOR THE WAFER-LEVEL INTEGRATION OF SHAPE MEMORY ALLOY WIRES

The present invention relates to a method to attach a shape memory alloy wire to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. The present invention also relates to a device comprising a shape memory alloy wire attached to a substrate, where the wire is mechanically attached into a 3D structure on the substrate.

For shape memory alloy wire wafer-level integrated method

ASSEMBLY Of a MICROELECTRONIC CHIP HAS GROOVE WITH a TELEGRAPHIC ELEMENT IN THE FORM OF TORON AND PROCESS Of ASSEMBLY

L'assemblage comporte au moins une puce microélectronique avec un élément filaire (5), ladite puce comporte deux faces principales (1, 2) parallèles et des faces latérales (3a, 3b), au moins l'une des faces latérales (3a,3b) comporte une rainure (4) longitudinale d'encastrement de l'élément filaire (5). L'élément filaire (5) est un toron comportant au moins deux fils électriquement conducteurs recouverts d'isolant et la puce comporte, dans la rainure (4) au moins un plot (9) électriquement conducteur, ledit plot (9) étant en contact électrique avec une zone dénudée (12) d'un seul des fils électriquement conducteurs du toron.

ASSEMBLY Of a MICROELECTRONIC CHIP HAS GROOVE WITH a TELEGRAPHIC ELEMENT IN THE FORM OF TORON AND PROCESS Of ASSEMBLY

Semiconductor Device and Method of Making a Semiconductor Package with Graphene for Die Attach

A semiconductor device has a substrate with a die pad. A conductive material is disposed on the die pad. The conductive material includes a plurality of graphene-coated metal balls in a matrix. A semiconductor die is disposed on the conductive material. The conductive material is sintered using an infrared laser. A bond wire is formed between the semiconductor die and substrate. An encapsulant is deposited over the semiconductor die and bond wire.

WIRE POSITIONING AND MECHANICAL ATTACHMENT FOR A RADIO-FREQUENCY IDENTIFICATION DEVICE

An antenna terminal positioning structure for a radio-frequency identification device having terminal pads mounted to one of its surface is obtained providing a wall assembly mounted to the device surface, the wall assembly having at least one wall surface extending from the device surface so as to be aligned with a target area on the electrical pad. The target is sufficiently large to receive the antenna terminal. An appropriate positioning of the antenna terminal on the pad is obtained by abutting the antenna terminal against the at least one wall surface. A mechanical attachment is activated between the antenna terminal and the positioning structure using a well-known process such as thermo-compression, ultra-violet (UV) or Laser soldering, mono or bi-components gluing etc., depending of the material of the positioning structure. The present positioning structure and attachment process are also applicable in other micro-electronic fields such as micro-sensors and micro- electronic machines ...

INCLUSION OF CHIP ELEMENTS IN A SHEATHED WIRE

A method for producing a sheathed wire comprises the following steps: axially advancing a core (20) through a sheathing zone (32); wrapping a sheathing fiber (24) around the core in the sheathing zone; and providing a series of microelectronic chip elements (10), each of which has a wire section (12), in the sheathing zone (32) in such a way that the sheathing fiber that wraps around the core also wraps around a chip element and the wire section thereof to form a sheathed wire which includes spaced-apart chip elements.

Multi-chip stack structure and method for fabricating the same

A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire ...

WIRE POSITIONING AND MECHANICAL ATTACHMENT FOR A RADIO-FREQUENCY IDENTIFICATION DEVICE

형상기억합금 와이어의 웨이퍼 레벨 집적하는 방법

... 본 발명은 기판에 형상기억합금 와이어를 접합하는 방법에 관한 것으로, 상기 와이어는 기판에 3D 구조로 기계적으로 접합한다. 본 발명은 또한 형상기억합금 와이어가 접합된 기판을 포함하는 장치에 관한 것으로, 상기 와이어는 기판에 3D 구조로 기계적으로 접합한다.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

To improve the reliability of a semiconductor device. 110-. (canceled)11. A method of manufacturing a semiconductor device , the method comprising:(a) preparing a semiconductor substrate which includes a plurality of wiring layers and a pad formed on an uppermost wiring layer of the plurality of wiring layers;(b) forming a surface protection film which includes an opening on the pad and is made of an inorganic insulating film;(c) forming a rewiring, which is electrically connected to the pad via the opening, on the surface protection film;(d) forming a pad electrode on the rewiring; and(e) forming a ball at a tip end of a wire, and connecting the ball to the pad electrode while applying ultrasonic vibration to the ball in a first direction,wherein the rewiring includes a pad electrode mounting portion on which the pad electrode is mounted, a connection portion which is connected to the pad, and an extended wiring portion that couples the pad electrode mounting portion and the connection portion, andthe pad electrode mounting portion has a rectangular shape with long sides and short sides.12. The method of manufacturing the semiconductor device according to claim 11 ,wherein the first direction is a direction along the long side.13. The method of manufacturing the semiconductor device according to claim 12 ,wherein the pad electrode covers a front surface of the pad electrode mounting portion, and extends to a side wall of the pad electrode mounting portion.14. The method of manufacturing the semiconductor device according to claim 11 ,wherein the first direction is a direction along the short side.15. The method of manufacturing the semiconductor device according to claim 11 ,wherein the pad electrode mounting portion includes a fin portion which extends from the long side or the short side to an outer side of the pad electrode mounting portion. The present application claims priority from Japanese Patent Application No. 2015-029409 filed on Feb. 18, 2015, the ...

METHOD OF FABRICATING AN INTEGRATED CIRCUIT CHIP AND INTEGRATED CIRCUIT CHIP

METHOD FOR FABRICATING MULTI-CHIP STACK STRUCTURE

A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire ...

Method for the wafer-level integration of shape memory alloy wires

The present invention relates to a method to attach a shape memory alloy wire to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. The present invention also relates to a device comprising a shape memory alloy wire attached to a substrate, where the wire is mechanically attached into a 3D structure on the substrate.

Adhesive sheet, adhesive sheet with dicing sheet, laminated sheet and method of manufacturing semiconductor device

To provide an adhesive sheet capable of reducing vibration of a semiconductor chip and reducing tip crack and connection defects between a wire and a pad. There is provided an adhesive sheet having tensile storage elastic modulus at 130 DEG C of 1 to 20 MPa and tan[delta] at 130 DEG C or 0.1 to 0.3.

Assembly of a microelectronic chip having a groove with a wire element in the form of a strand, and method for assembly

Assembly of at least one microelectronic chip with a wire element, the chip comprising a groove for embedment of the wire element. The wire element is a strand with a longitudinal axis substantially parallel to the axis of the groove, comprising at least two electrically conducting wires covered with insulator. The chip comprises at least one electrically conducting bump in the groove, this bump being in electric contact with a stripped area of a single one of the electrically conducting wires of the strand.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

The semiconductor device includes a plurality of wiring layers formed on a semiconductor substrate, a pad (9a) formed on an uppermost wiring layer (9) of the plurality of wiring layers (5,7,9), a surface protection film (10) which includes an opening (10a) on the pad (9a) and is made of an inorganic insulating film, a rewiring (12) formed on the surface protection film (10); a pad electrode (13) formed on the rewiring, and a wire (20) connected to the pad electrode (13). The rewiring (12) includes a pad electrode mounting portion (121) on which the pad electrode (13) is mounted, a connection portion which is connected to the pad (9a), and an extended wiring portion which couples the pad electrode mounting portion (121) and the connection portion, and the pad electrode mounting portion (121) has a rectangular shape when seen in a plan view.

Verfahren zum Auflöten eines ersten Lötpartners auf einen zweiten Lötpartner unter Verwendung von Abstandhaltern

Die Erfindung betrifft ein Verfahren zum Auflöten eines ersten Lötpartners (2) auf eine Montagefläche (3t) eines zweiten Lötpartners (3). Der erste Lötpartner (2) weist eine Oberseite (2t) und eine der Oberseite (2t) entgegengesetzte Unterseite (2b) auf. Bei dem Verfahren wird ein Lot (5) zwischen der Montagefläche (3t) und der Unterseite (2b) derart angeordnet und aufgeschmolzen, dass zu einem ersten Zeitpunkt der erste Lötpartner (2) an einer ersten Stelle (S1) der Unterseite (2b) an einem Abstandhalter (41) anliegt, der erste Lötpartner (2) an einer zweiten Stelle (S2) der Unterseite (2b) an einem Abstandhalter (42) anliegt; und eine dritte Stelle (S3) der Unterseite (2b) des ersten Lötpartners (2) von der Montagefläche (3t) einen ersten Abstand (d1) aufweist. Ab einem dem ersten Zeitpunkt folgenden zweiten Zeitpunkt werden der erste Lötpartner (2) und der zweite Lötpartners (3) derart aneinandergepresst, dass die dritte Stelle (S3) der Unterseite (2b) des ersten Lötpartners (2) von ...

PROCEEDED Of ASSEMBLY Of AT LEAST a CHIP WITH a FABRIC INCLUDING a DEVICE CHIP HAS

INCORPORATION Of ELEMENTS HAS CHIP IN a WIRE LAPS

METHOD OF FABRICATING AN INTEGRATED CIRCUIT CHIP AND INTEGRATED CIRCUIT CHIP

PROCEEDED Of ASSEMBLY Of AT LEAST a CHIP WITH a FABRIC INCLUDING a DEVICE CHIP HAS

L'invention concerne un procédé d'assemblage d'un dispositif sur deux fils tendus sensiblement parallèles. Le dispositif comprend une puce électronique (8) et deux rainures (4a, 4b) sensiblement parallèles ouvertes sur des côtés opposés du dispositif. L'écartement des rainures correspond à l'écartement des fils. Le dispositif présente une forme pénétrante le long d'un axe perpendiculaire au plan des rainures, ayant une base au niveau des rainures et un sommet (1) de dimension inférieure à l'écartement des fils. Le procédé comprend les étapes consistant à placer le sommet (1) du dispositif entre les deux fils ; à déplacer le dispositif entre les deux fils, d'où il résulte que les fils sont écartés par la forme pénétrante du dispositif ; et à continuer le déplacement du dispositif jusqu'à ce que les fils pénètrent dans les rainures en revenant vers leur écartement initial.

INCORPORATION Of ELEMENTS HAS CHIP IN a WIRE LAPS

Un procédé de réalisation d'un fil guipé, comprend les étapes suivantes : faire défiler axialement une âme (20) par une zone de guipage (32) ; enrouler une fibre de gainage (24) autour de l'âme au niveau, de la zone de guipage ; et présenter, au niveau de la zone de guipage (32), un élément à puce microélectronique (10) muni d'un tronçon de fil (12), de sorte que la fibre de gainage en cours d'enroulement autour de l'âme s'enroule également autour de l'élément à puce et son tronçon de fil.

CHIP-ON-LEAD PACKAGE AND METHOD OF FORMING

In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads. The one major surface is electrically connected to the first lead, and electrically isolated from the second lead. The other major surface where active device are formed may be electrically connected to the second lead.

Doppelseitiges Kühltyp-Leistungsmodul und Herstellungsverfahren dafür

Die Offenbarung betrifft ein doppelseitiges Kühltyp-Leistungsmodul und ein Herstellungsverfahren dafür. Das doppelseitige Kühltyp-Leistungsmodul umfasst ein Paar von Halbleiterchips, die zwischen einem oberen Substrat und einem unteren Substrat angeordnet sind. Das doppelseitige Kühltyp-Leistungsmodul umfasst Ausgangsanschlusszuleitungen, die konfiguriert sind, um auf einer unteren Oberfläche des oberen Substrats angeordnet und jeweils mit dem Paar von Halbleiterchips verbunden zu sein; eine Plusanschlusszuleitung, die konfiguriert ist, um auf einer Seite einer oberen Oberfläche des unteren Substrats angeordnet zu sein, um mit irgendeinem Halbleiterchip, gewählt aus dem Paar von Halbleiterchips, verbunden zu sein; und eine Minusanschlusszuleitung, die konfiguriert ist, um auf der anderen Seite der oberen Oberfläche des unteren Substrats angeordnet zu sein, um mit dem anderen Halbleiterchip des Paars von Halbleiterchips verbunden zu sein.

Method for the wafer-level integration of shape memory alloy wires

The present invention relates to a method to attach a shape memory alloy wire to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. The present invention also relates to a device comprising a shape memory alloy wire attached to a substrate, where the wire is mechanically attached into a 3D structure on the substrate.

METHOD FOR THE WAFER-LEVEL INTEGRATION OF SHAPE MEMORY ALLOY WIRES

The present invention relates to a method to attach a shape memory alloy wire to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. The present invention also relates to a device comprising a shape memory alloy wire attached to a substrate, where the wire is mechanically attached into a 3D structure on the substrate.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

The present invention is to improve reliability of a semiconductor device. The semiconductor device (1) includes a plurality of wiring layers (5, 7, 9) formed on a semiconductor substrate (1P), a pad (9a) formed on an uppermost wiring layer of the wiring layers (5, 7, 9), a surface protection film (10) which includes an opening on the pad and is made of an inorganic insulating film, a rewiring (12) formed on the surface protection film (10), a pad electrode (13) formed on the rewiring (12), and a wire (20) connected to the pad electrode (13). The rewiring (12) includes a pad electrode mounting portion on which the pad electrode (13) is mounted, a connection portion which is connected to the pad, and an extended wiring portion which connects the pad electrode mounting portion and the connection portion, and the pad electrode mounting portion (13) is in a rectangular shape when viewed from a plane. COPYRIGHT KIPO 2016 (1) Semiconductor device (Semiconductor chip) (10) Surface protection film ...

METHOD FOR THE WAFER-LEVEL INTEGRATION OF SHAPE MEMORY ALLOY WIRES

The present invention relates to a method to attach a shape memory alloy wire to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. The present invention also relates to a device comprising a shape memory alloy wire attached to a substrate, where the wire is mechanically attached into a 3D structure on the substrate.

Grown carbon nanotube die attach structures, articles, devices, and processes for making them

An article of manufacture includes a semiconductor die (110) having an integrated circuit (105) on a first side of the die (110), a diffusion barrier (125) on a second side of the die (110) opposite the first side, a mat of carbon nanotubes (112) rooted to the diffusion barrier (125), a die attach adhesive (115) forming an integral mass with the mat (112) of the carbon nanotubes, and a die pad (120) adhering to the die attach adhesive and (115) and the mat (112) of carbon nanotubes for at least some thermal transfer between the die (110) and the die pad (120) via the carbon nanotubes (112). Other articles, integrated circuit devices, structures, and processes of manufacture, and assembly processes are also disclosed.

Leistungswandlungsvorrichtung und Verfahren zum Herstellen derselben

Die vorliegende Erfindung betrifft eine Leistungswandlungsvorrichtung (10) sowie ein Verfahren zu deren Herstellung. Ein Leiterrahmen (35) wird auf eine leitende Schicht (26) und eine Verteilerschiene (23) gesetzt. Der Leiterrahmen (35) weist Löcher auf, die zuvor in gegenüber liegende Enden desselben geformt wurden, und Teile eines Lötmaterials oder Lötmaterialteile (36, 37) werden in die Löcher eingefügt. Die Lötmaterialteile (36, 37) werden dann durch ein mit Ultraschall vibrierendes Werkzeug vibriert, wodurch die Lötmaterialteile (36, 37) geschmolzen werden, ohne eine hohe Temperatur aufzuweisen. Der Leiterrahmen (35) wird dadurch an die leitende Schicht (26) und die Verteilerschiene (23) gebondet. Ein Halbleiter-Element (22) und die Verteilerschiene (23) werden durch einen weiteren Leiterrahmen (31) und den Leiterrahmen (35) verbunden. Die Verbindungsstruktur ist dabei derart, dass der Leiterrahmen (35), der durch Ultraschall-Bonden oder andere Bond-Verfahren zu bonden ist, nicht in ...

The armor of the chip component

Kompakter Klasse-F-Chip und Drahtanpassungstopolgie

Eine Verstärkerschaltung enthält einen RF-Eingangsport, einen RF-Ausgangsport, einen Referenzpotentialport und einen RF-Verstärker, der einen Eingangsanschluss und einen ersten Ausgangsanschluss aufweist. Ein Ausgangsimpedanzanpassungsnetzwerk koppelt den ersten Ausgangsanschluss elektrisch mit dem RF-Ausgangsport. Eine erste Induktivität ist elektrisch zwischen den ersten Ausgangsanschluss und den RF-Ausgangsport in Reihe geschaltet, ein erster LC-Resonator ist elektrisch direkt zwischen den ersten Ausgangsanschluss und den Referenzpotentialport geschaltet, und ein zweiter LC-Resonator ist elektrisch direkt zwischen den ersten Ausgangsanschluss und den Referenzpotentialport geschaltet. Der erste LC-Resonator ist dazu ausgebildet, eine Ausgangskapazität des RF-Verstärkers bei einer dritten Frequenz des RF-Signals auszugleichen. Der zweite LC-Resonator ist dazu ausgebildet, eine Harmonische zweiter Ordnung des RF-Signals auszugleichen.

Verfahren zum Auflöten eines ersten Lötpartners auf einen zweiten Lötpartner unter Verwendung von Abstandhaltern

Verfahren zum Auflöten eines ersten Lötpartners (2) auf eine Montagefläche (3t) eines zweiten Lötpartners (3), wobei der erste Lötpartner (2) eine Oberseite (2t) und eine der Oberseite (2t) entgegengesetzte Unterseite (2b) aufweist, und wobei das Verfahren aufweist: Anordnen eines Lots (5) zwischen der Montagefläche (3t) und der Unterseite (2b) und Aufschmelzen des Lots (5) derart, dass zu einem ersten Zeitpunkt – der erste Lötpartner (2) an einer ersten Stelle (S1) der Unterseite (2b) an einem Abstandhalter (41) anliegt; – der erste Lötpartner (2) an einer zweiten Stelle (S2) der Unterseite (2b) an einem Abstandhalter (42) anliegt; – eine dritte Stelle (S3) der Unterseite (2b) des ersten Lötpartners (2) von der Montagefläche (3t) einen ersten Abstand (d1) aufweist; Aneinanderpressen des ersten Lötpartners (2) und des zweiten Lötpartners (3) derart, dass ab einem dem ersten Zeitpunkt folgenden zweiten Zeitpunkt die dritte Stelle (S3) der Unterseite (2b) des ersten Lötpartners (2) von der ...

METHOD FOR THE WAFER INTEGRATION OF SHAPE MEMORY ALLOY WIRES

Inclusion of chip elements in a sheathed wire

A method for forming a sheathed wire includes the steps of: axially advancing a core through a sheathing zone; wrapping a sheathing fiber around the core in the sheathing zone; and providing, in the sheathing zone, a series of microelectronic chip elements each provided with a wire section, in such a way that the sheathing fiber that wraps around the core also wraps around a chip element and the wire section thereof to form a sheathed wire incorporating spaced-apart chip elements.

WIRE POSITIONING AND MECHANICAL ATTACHMENT FOR A RADIO-FREQUENCY IDENTIFICATION DEVICE

An antenna terminal positioning structure for a radio-frequency identification device having terminal pads mounted to one of its surface is obtained providing a wall assembly mounted to the device surface, the wall assembly having at least one wall surface extending from the device surface so as to be aligned with a target area on the electrical pad. The target is sufficiently large to receive the antenna terminal. An appropriate positioning of the antenna terminal on the pad is obtained by abutting the antenna terminal against the at least one wall surface. A mechanical attachment is activated between the antenna terminal and the positioning structure using a well-known process such as thermo-compression, ultra-violet (UV) or Laser soldering, mono or bi-components gluing etc., depending of the material of the positioning structure. The present positioning structure and attachment process are also applicable in other micro-electronic fields such as micro-sensors and micro-electronic machines ...

INCLUSION OF CHIP ELEMENTS IN A SHEATHED WIRE

WIRE POSITIONING AND MECHANICAL ATTACHMENT FOR A RADIO-FREQUENCY IDENTIFICATION DEVICE

An antenna terminal positioning structure for a radio-frequency identification device having terminal pads mounted to one of its surface is obtained providing a wall assembly mounted to the device surface, the wall assembly having at least one wall surface extending from the device surface so as to be aligned with a target area on the electrical pad. The target is sufficiently large to receive the antenna terminal. An appropriate positioning of the antenna terminal on the pad is obtained by abutting the antenna terminal against the at least one wall surface. A mechanical attachment is activated between the antenna terminal and the positioning structure using a well-known process such as thermo-compression, ultra-violet (UV) or Laser soldering, mono or bi-components gluing etc., depending of the material of the positioning structure. The present positioning structure and attachment process are also applicable in other micro-electronic fields such as micro-sensors and micro-electronic machines ...

Integrated circuits having copper bonding structures with silicon carbon nitride passivation layers thereon and methods for fabricating same

Integrated circuits having copper bonding structures with silicon carbon nitride passivation layers and methods for making the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a copper bonding structure having a contact surface. The copper bonding structure overlies the substrate. A passivation layer formed of silicon carbon nitride is disposed on the contact surface.

Multiple chips stack structure and method for fabricating the same

POWER CONVERSION APPARATUS AND METHOD FOR MANUFACTURING THE SAME

A second lead frame is set onto a conductive layer and a busbar. The second lead frame has holes previously formed at opposite ends thereof, and pieces of solder material or solder pieces are inserted into the holes. Then, the solder pieces are vibrated by an ultrasonically vibrating tool, whereby the solder pieces are melted without having a high temperature. The second lead frame is thus bonded to the conductive layer and the busbar. A semiconductor element and the busbar are connected by a first lead frame and the second lead frame. The connection structure thereof is such that the second lead frame to be bonded by ultrasonic bonding or other bonding methods is not directly in contact with the semiconductor element, which eliminates the risk of damage to the semiconductor element.

System having semiconductor die mounted in die-receiving area having different shape than die

Electronic systems utilizing a plurality of integrated circuit packages having at least some large gaps between edges of a semiconductor die and the inner ends of package conductors defining a die-receiving area, one or more bond wire support structure are disposed in the gap, thereby causing a long bond wire to behave as two or more shorter bond wires. The bond wires are tacked to a top surface of the support structure by various alternative means. Alternatively, a "jumper" structure having conductive traces of graduated length can be disposed in the die-receiving area between the die and the edges of the die-receiving area, providing an intermediate connection between the die and the leads of the package, thereby permitting short bond wires to be used in lieu of long bond wires.

ASSEMBLY OF A GROOVED MICROELECTRONIC CHIP WITH A TOROIDAL WIRE ELEMENT AND METHOD OF ASSEMBLING IT

The invention relates to an assembly of at least one microelectronic chip with a wire element (5), the chip having a groove (4) in which the wire element is embedded. The wire element (5) is a torus of longitudinal axis substantially parallel to the axis of the groove, comprising at least two electrically conducting wires (5a, 5b, 5c) coated with an insulator. The chip includes at least one electrically conducting stud (9) in the groove (4), this stud being in electrical contact with a stripped region of only one of the electrically conducting wires of the torus.

Semiconductor device

METHOD FOR THE WAFER-LEVEL INTEGRATION OF SHAPE MEMORY ALLOY WIRES

VERFAHREN ZUR STEUERUNG DER ENERGIE BEI ULTRASCHALLDRAHTBONDVORGAENGEN

Chip-on-lead package and method of forming

In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads. The one major surface is electrically connected to the first lead, and electrically isolated from the second lead. The other major surface where active device are formed may be electrically connected to the second lead.

溝を有する超小型電子チップとストランドの形をしたワイヤ要素との組立体及び組立方法

METHOD FOR ASSEMBLING AT LEAST ONE CHIP USING A FABRIC, AND FABRIC INCLUDING A CHIP DEVICE

The invention relates to a method for assembling a device on two substantially parallel, extended threads (18a, 18b). The device includes an electronic chip and two substantially parallel, open grooves (4a, 4b) on opposite sides of the device. The spacing of the grooves corresponds to the spacing of the threads. The device has a shape penetrating along an axis perpendicular to the plane of the grooves, said shape having a base on the grooves and a top (1) that is smaller than the spacing of the threads. The method includes the steps that involve: placing the top (1) of the device between both threads; moving the device between both threads, thus causing the threads to be spaced apart by the penetrating shape of the device; and continuing the movement of the device until the threads penetrate into the grooves while returning to the initial spacing thereof.

ASSEMBLY OF A MICROELECTRONIC CHIP HAVING A GROOVE WITH A WIRE ELEMENT IN THE FORM OF A STRAND, AND METHOD FOR ASSEMBLY

Assembly of at least one microelectronic chip with a wire element, the chip comprising a groove for embedment of the wire element. The wire element is a strand with a longitudinal axis substantially parallel to the axis of the groove, comprising at least two electrically conducting wires covered with insulator. The chip comprises at least one electrically conducting bump in the groove, this bump being in electric contact with a stripped area of a single one of the electrically conducting wires of the strand.

Compact class-F chip and wire matching topology

An amplifier circuit includes an RF input port, an RF output port, a reference potential port, and an RF amplifier having an input terminal and a first output terminal. An output impedance matching network electrically couples the first output terminal to the RF output port. A first inductor is electrically connected in series between the first output terminal and the RF output port, a first LC resonator is directly electrically connected between the first output terminal and the reference potential port, and a second LC resonator is directly electrically connected between the first output terminal and the reference potential port. The first LC resonator is configured to compensate for an output capacitance of the RF amplifier at a center frequency of the RF signal. The second LC resonator is configured to compensate for a second order harmonic of the RF signal.

CONTACT ASSEMBLY FOR AN ELECTRONIC COMPONENT, AND METHOD FOR PRODUCING AN ELECTRONIC COMPONENT

A contact assembly for an electronic component includes a wiring substrate having an upper face, a lower face and at least one contact connection surface on the upper face. At least one bonding strip is provided for connection to the at least one contact connection surface. The at least one contact connection surface is disposed on at least one metal-filled recess in the volume of the wiring substrate. A semiconductor component, an electronic component and a method for producing an electronic component are also provided.

METHOD FOR ASSEMBLING AT LEAST ONE CHIP USING A FABRIC, AND FABRIC INCLUDING A CHIP DEVICE

Method for assembling at least one chip using a fabric, and fabric including a chip device

A method for assembling a device on two substantially parallel taut threads. The device includes an electronic chip and two substantially parallel grooves open on opposite sides of the device. The distance separating the grooves corresponds to the distance separating the threads. The device presents a penetrating shape along an axis perpendicular to the plane of the grooves, having a base at the level of the grooves and an apex of smaller size than the distance separating the threads. The method includes the steps consisting in placing the apex of the device between the two threads; in moving the device between the two threads resulting in the threads being separated from one another by the penetrating shape of the device; and in continuing movement of the device until the threads penetrate into the grooves reverting to their initial separation distance.

Multiple chips stack structure and method for fabricating the same

Multiple chips stack structure and a method for fabricating the same are provided. A method of fabricating is provided that has placing a group of first chips on a chip carrier by using a step pattern, placing a second chip on a top of the group of the first chips, electric connecting the group of the fist chips and the second chip to the chip carrier with wires, using Film Over Wire (FOW) to stack a third chip with an isolated layer on the on the first and the second chips, covering a part of ends of the wires on the first chip on the top of the group of the first chips and at least part of the second chip with the isolated layer, and electric connecting the third chip to the chip carrier with wires so that to avoid conventional technique that a second chip's plan size is far smaller than a first chop and the second chip is directly mounted on the first chip to increase height of entire structure and problem of wiring process difficultly.

Inclusion of chip elements in a sheathed wire

A method for producing a sheathed wire comprises the following steps: axially advancing a core (20) through a sheathing zone (32); wrapping a sheathing fiber (24) around the core in the sheathing zone; and providing a series of microelectronic chip elements (10), each of which has a wire section (12), in the sheathing zone (32) in such a way that the sheathing fiber that wraps around the core also wraps around a chip element and the wire section thereof to form a sheathed wire which includes spaced-apart chip elements.

Double-side cooling type power module and producing method thereof

Disclosed herein are a double-side cooling type power module and a producing method thereof. The double-side cooling type power module includes a pair of semiconductor chips disposed between an upper substrate and a lower substrate. The double-side cooling type power module includes output terminal leads configured to be disposed on a lower surface of the upper substrate and each connected to the pair of semiconductor chips, respectively; a plus terminal lead configured to be disposed at one side of an upper surface of the lower substrate to be connected to any one semiconductor chip selected from the pair of semiconductor chips; and a minus terminal lead configured to be disposed at the other side of the upper surface of the lower substrate to be connected to the other semiconductor chip of the pair of semiconductor chips.

Wire positioning and mechanical attachment for a radio-frequency indentification device

An antenna terminal positioning structure for a radio-frequency identification device having terminal pads mounted to one of its surface is obtained providing a wall assembly mounted to the device surface, the wall assembly having at least one wall surface extending from the device surface so as to be aligned with a target area on the electrical pad. The target is sufficiently large to receive the antenna terminal. An appropriate positioning of the antenna terminal on the pad is obtained by abutting the antenna terminal against the at least one wall surface. A mechanical attachment is activated between the antenna terminal and the positioning structure using a well-known process such as thermo-compression, ultra-violet (UV) or Laser soldering, mono or bi-components gluing etc., depending of the material of the positioning structure. The present positioning structure and attachment process are also applicable in other micro-electronic fields such as micro-sensors and micro-electronic machines ...

Method for assembling at least one chip using fabric, and fabric including chip device

Method for the wafer-level integration of shape memory alloy wires

The present invention relates to a method to attach a shape memory alloy wire to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. The present invention also relates to a device comprising a shape memory alloy wire attached to a substrate, where the wire is mechanically attached into a 3D structure on the substrate.

Chip-on-lead package and method of forming

In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads. The one major surface is electrically connected to the first lead, and electrically isolated from the second lead. The other major surface where active device are formed may be electrically connected to the second lead.

Method for fabricating multi-chip stack structure

A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire ...

ASSEMBLY OF A GROOVED MICROELECTRONIC CHIP WITH A TOROIDAL WIRE ELEMENT AND METHOD OF ASSEMBLING IT

Method for assembling at least one chip using fabric, and fabric including chip device

METHOD FOR THE WAFER-LEVEL INTEGRATION OF SHAPE MEMORY ALLOY WIRES

MULTI-CHIP STACK STRUCTURE AND METHOD FOR FABRICATING THE SAME

A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire ...

Wire positioning and mechanical attachment for a radio-frequency indentification device

An antenna terminal positioning structure for a radio-frequency identification device having terminal pads mounted to one of its surface is obtained providing a wall assembly mounted to the device surface, the wall assembly having at least one wall surface extending from the device surface so as to be aligned with a target area on the electrical pad. The target is sufficiently large to receive the antenna terminal. An appropriate positioning of the antenna terminal on the pad is obtained by abutting the antenna terminal against the at least one wall surface. A mechanical attachment is activated between the antenna terminal and the positioning structure using a well-known process such as thermo-compression, ultra-violet (UV) or Laser soldering, mono or bi-components gluing etc., depending of the material of the positioning structure. The present positioning structure and attachment process are also applicable in other micro-electronic fields such as micro-sensors and micro-electronic machines ...

Assembly of a grooved microelectronic chip with a toroidal wire element and method of assembling it

INTEGRATED CIRCUITS HAVING COPPER BONDING STRUCTURES WITH SILICON CARBON NITRIDE PASSIVATION LAYERS THEREON AND METHODS FOR FABRICATING SAME

Integrated circuits having copper bonding structures with silicon carbon nitride passivation layers and methods for making the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a copper bonding structure having a contact surface. The copper bonding structure overlies the substrate. A passivation layer formed of silicon carbon nitride is disposed on the contact surface. 1. A integrated circuit comprising:a substrate;a copper bond pad having a contact surface, the copper bond pad overlying the substrate;a passivation layer comprising silicon carbon nitride disposed on the contact surface; anda conductive element bonded to the copper bond pad through the passivation layer with a weld.2. The integrated circuit of claim 1 , wherein the passivation layer has a thickness of from about 3 to about 15 nanometers (nm).3. The integrated circuit of claim 2 , wherein the passivation layer has a thickness of from about 5 to about 8 nm.4. The integrated circuit of claim 1 , wherein the copper bond pad comprises pure copper claim 1 , doped copper claim 1 , or a copper alloy.5. The integrated circuit of claim 4 , wherein the doped copper comprises at least 90 weight percent (wt %) copper based on a total weight of the bond pad.6. The integrated circuit of claim 5 , wherein the doped copper comprises aluminum claim 5 , manganese claim 5 , gold or a combination thereof.7. The integrated circuit of claim 4 , wherein the copper alloy comprises at least 55 wt % copper based on a total weight of the copper bond pad.8. The integrated circuit of claim 7 , wherein the copper alloy comprises aluminum claim 7 , gold claim 7 , or a combination thereof.9. The integrated circuit of claim 1 , wherein the conductive element is bonded to the copper bond pad through the passivation layer with a ball bond forming the weld.10. The integrated circuit of claim 9 , wherein the conductive element is a wire.11. The integrated circuit of claim 1 , wherein the ...

Semiconductor device and method of manufacturing the same

METHOD FOR ASSEMBLING AT LEAST ONE CHIP USING A FABRIC, AND FABRIC INCLUDING A CHIP DEVICE

A method for assembling a device on two substantially parallel taut threads. The device includes an electronic chip and two substantially parallel grooves open on opposite sides of the device. The distance separating the grooves corresponds to the distance separating the threads. The device presents a penetrating shape along an axis perpendicular to the plane of the grooves, having a base at the level of the grooves and an apex of smaller size than the distance separating the threads. The method includes the steps consisting in placing the apex of the device between the two threads; in moving the device between the two threads resulting in the threads being separated from one another by the penetrating shape of the device; and in continuing movement of the device until the threads penetrate into the grooves reverting to their initial separation distance.

被覆されたワイヤの中へのチップ素子の組み込み

BONDING TOOL, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE

A bonding tool for bonding two conductive plates in contact with each other by pressing the bonding tool against the two conductive plates while vibrating a bonding end portion thereof in a direction parallel to the conductive plates. The bonding end portion of the bonding tool includes a bonding base having an end surface, the end surface having a protrusion area that has two sides facing and parallel to each other in a first direction that is parallel to the end surface, a plurality of protrusions provided in the protrusion area of the end surface, and a suppression portion provided on the end surface along the two sides of the protrusion area. The bonding end portion is configured to vibrate in the first direction.

織物を使用して少なくとも１つのチップを組み込むための方法およびチップ装置を備える織物

Assembly of a grooved microelectronic chip with a toroidal wire element and method of assembling it

The present invention relates to an assembly of at least one microelectronic chip with a wire element (5), the chip having a groove (4) in which the wire element is embedded. The wire element (5) is a torus of longitudinal axis substantially parallel to the axis of the groove, comprising at least two electrically conducting wires (5a, 5b, 5c) coated with an insulator. The chip includes at least one electrically conducting stud (9) in the groove (4), this stud being in electrical contact with a stripped region of only one of the electrically conducting wires of the torus.

Method for Producing a Metal Layer on a Substrate and Device

A method produces a metal layer on a semiconductor substrate. A metal layer is produced on the semiconductor substrate by depositing metal particles. The metal particles include cores made of a first metal material and shells surrounding the cores. The shells are made of a second metal material that is resistant to oxidation.

Semiconductor device including cladded base plate

A semiconductor device includes a semiconductor chip coupled to a substrate and a base plate coupled to the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure.

Resin-encapsulated semiconductor device and method of manufacturing the same

A resin-encapsulated semiconductor device includes: a semiconductor element mounted on a die pad portion; a plurality of lead portions disposed so that distal end parts thereof are opposed to the die pad portion; a metal thin wire for connecting an electrode of the semiconductor element to the lead portion; and an encapsulating resin for partially encapsulating those components. A bottom surface part of the die pad portion, and a bottom surface part, an outer surface part, and an upper end part of the lead portion are exposed from the encapsulating resin. A plated layer is formed on the exposed lead bottom surface part and the exposed lead upper end part.

LEADFRAME PACKAGE WITH STABLE EXTENDED LEADS

Embodiments of the present disclosure are directed to leadframes having the cantilevered extension that includes an integral support on the end of the lead nearest the die pad. A support integral to the leadframe allows the support to be built to the proper height to support the cantilevered lead in each package and reduces or eliminates the upward, downward, and side to side deflections caused or allowed by supports built-in to the tooling of the manufacturing equipment. Also, by building the support into the leadframe, the leadframes may be pretaped prior to the die attach and wire bonding steps of the manufacturing process. 1. A semiconductor package , comprising:a die pad having a die attach surface;a semiconductor die coupled to the die attach surface of the die pad;a plurality of leads spaced apart from at least one side of the die pad, the plurality of leads having first ends and second ends, the first ends being nearer the die pad than the second ends;lands at the second ends of the plurality of leads;cantilevered beams extending from the lands and forming the first ends of the leads, each of the cantilevered beams having a first surface and a second surface opposite the first surface;encapsulation material located over the semiconductor die and portions of the leads, including the first surfaces and portions of the second surfaces of the cantilevered beams; andat least one cavity in the encapsulation material that exposes portions of the second surfaces of the leads to an environment outside the semiconductor package.2. The semiconductor package of claim 1 , further comprising a conductive wire coupling the semiconductor die to the first surface of one of the cantilevered beams claim 1 , the at least one cavity being formed at the first ends of the leads.3. The semiconductor package of wherein the at least one cavity is a trench exposing the portions of the second surfaces of the plurality of leads.4. The semiconductor package of wherein the at least one ...

INTEGRATED CIRCUIT PACKAGE STACK

Apparatuses, methods and systems associated with integrated circuit (IC) package design are disclosed herein. An IC package stack may include a first IC package and a second IC package. The first IC package may include a first die and a first redistribution layer that communicatively couples contacts on the first side of the first IC package to the first die and to contacts on a second side of the first IC package, the second side opposite to the first side. The second IC package may be mounted to the second side of the first IC package. The second IC package may include a second die and a second redistribution layer that communicatively couples contacts on a side of the second IC package to the second die, the contacts of the second IC package communicatively coupled to the contacts on the second side of the first IC package. 1. An integrated circuit (IC) package stack , comprising: a first die;', 'a first redistribution layer that communicatively couples contacts on the first side of the first IC package to the first die and to contacts on a second side of the first IC package, the second side opposite to the first side;', 'a first set of vias that communicatively couples the contacts on the first side of the first IC package to the first redistribution layer; and', 'a second set of vias that communicatively couples the first redistribution layer to the contacts on the second side of the first IC package, wherein the first set of vias are formed within a substrate of the first IC package and the second set of vias are formed within a molded layer of the first IC package; and, 'a first IC package, a first side of the first IC package to be mounted to a circuit board, the first IC package includes a second die;', 'a second redistribution layer that communicatively couples contacts on a side of the second IC package to the second die, the contacts of the second IC package communicatively coupled to the contacts on the second side of the first IC package., 'a second ...

LEAD-FREE SOLDERING METHOD AND SOLDERED ARTICLE

In a soldering method for Ag-containing lead-free solders to be soldered to an Ag-containing member, void generation is prevented and solder wettability is improved. The soldering method for Ag-containing lead-free solders of the present invention is a soldering method for Ag-containing lead-free solders includes a first step of bringing a lead-free solder having a composition that contains Ag that a relation between a concentration C (mass %) of Ag contained in an Sn—Ag-based lead-free solder before soldering of a mass M(g) and an elution amount B(g) of Ag contained in the Ag-containing member becomes 1.0 mass %≦(M×C+B)×100/(M+B)≦4.6 mass % and that the balance consists of Sn and unavoidable impurities into contact with the Ag-containing member, a second step of heating and melting the lead-free solder, and a third step of cooling the lead-free solder. 1. A soldering method for Ag-containing lead-free solders to be soldered to an Ag-containing member comprising: {'br': None, '1.0 mass %≦(M×C+B)×100/(M+B)≦4.6 mass %'}, 'a first step of bringing a lead-free solder into contact with the Ag-containing member, the lead-free solder having a composition consisting of Ag and the balance of Sn and unavoidable impurities, which satisfies a relation between a concentration C (mass %) of Ag contained in an Sn—Ag based lead-free solder before soldering of a mass M(g) and an elution amount B(g) of Ag contained in the Ag-containing member being as followsa second step of heating and melting the lead-free solder; anda third step of cooling the lead-free solder.2. The soldering method for Ag-containing lead-free solders according to claim 1 , whereinthe composition of the lead-free solder in the first step is configured by a multiple eutectic system that a precipitation strengthening element that is not more than 0.1 mass % in solubility limit concentration has been added to a Sn—Ag eutectic system, andthe lead-free solder in the third step has a composition that a total mass of Ag ...

POWER MODULE WITH THE INTEGRATION OF CONTROL CIRCUIT

The present disclosure provides a power module with the integration of a control circuit at least, including: a power substrate; a power device mounted on the power substrate; and at least one control substrate which supports the control circuit, is electrically connected with the power substrate and disposed at an angle of inclination on a surface of the power substrate on which the power device is mounted; wherein the angle of inclination is greater than or equal to 45 degrees and smaller than or equal to 135 degrees. In the power module provided by the present disclosure, only the power substrate as well as the connections between the control substrate and the power substrate occupies the footprint area of the power module, and thus the horizontal footprint area of the power module is effectively reduced and thereby the power density of the power module is increased. 1. A power module with the integration of a control circuit , comprising:a power substrate;a power device mounted on the power substrate; andat least one control substrate which supports the control circuit, is electrically connected with the power substrate and disposed at an angle of inclination on a surface of the power substrate on which the power device is mounted;wherein the angle of inclination is greater than or equal to 45 degrees and smaller than or equal to 135 degrees.2. The power module according to claim 1 , wherein the power substrate comprises at least one conductive wiring layer on which the power device is disposed.3. The power module according to claim 1 , wherein the at least one control substrate comprises at least one conductive wiring layer and at least one insulation layer claim 1 , and a control device in the control circuit is disposed on the at least one conductive wiring layer.4. The power module according to claim 3 , wherein the at least one control substrate comprises two conductive wiring layers disposed on both sides of the at least one insulation layer claim 3 , ...

Radio frequency shielding cavity package

A radio-frequency shielding cavity package is set forth along with a method of manufacturing thereof. According to one embodiment, the radio-frequency shielding cavity package comprises a metallic leadframe and plastic molded body. The leadframe has a plurality of contact pads extending from top to bottom surfaces thereof, at least one contact pad on the top surface being surrounded by metal for shielding the contact pad from external electric fields. A plated inner ring surrounds a die attach pad on the leadframe. The die attach pad receives a semiconductor die adapted to be wire bonded to the inner ring and plurality of contact pads. A plated outer ring defines a ground plane circumscribing the perimeter of the leadframe. A cap is connected to the ground plane for enclosing and protecting the wire bonded semiconductor device die and providing electrical grounding thereof.

METHOD FOR ASSEMBLING A MICROELECTRONIC CHIP ELEMENT ON A WIRE ELEMENT, AND INSTALLATION ENABLING ASSEMBLY TO BE PERFORMED

Method for assembling includes: providing a system to transfer wire element from wire element supply device to wire element storage device; stretching wire element between supply and storage devices by tensioning; providing an individualized reservoir and separated chip elements, each including a connection terminal including a top with free access facing in which chip element is not present; transporting the chip element from reservoir to an assembly area between supply and storage devices in which wire element is tightly stretched in assembly area; fixing electrically conducting wire element to chip element connection terminal in assembly area; and adding electrically insulating material on chip element after latter has been fixed to wire element forming a cover, the addition of material being performed on surface of chip element including connection terminal fixed to wire element to cover at least the connection terminal and portion of wire element at fixing point of latter. 115-. (canceled)16. A method for assembling a microelectronic chip element on an electrically conducting wire element , comprising the following steps:providing a transfer system of the wire element from a wire element supply device to a storage device of said wire element,stretching of the wire element between the supply device and the storage device by a tensioning device,providing a reservoir of individualized and separated chip elements, each chip element comprising a connection terminal, the connection terminal of each chip element comprising a top with free access facing which no part of the chip element is present,transporting a chip element from the reservoir to an assembly area located between the supply device and storage device in such a way that the wire element is tightly stretched in said assembly area,fixing the electrically conducting wire element to the connection terminal of the chip element in the assembly area,performing addition of electrically insulating material on the ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device can reduce the number of bonding wires. The semiconductor device includes two or more semiconductor elements each of which has electrodes on a first main surface and a second main surface, an electrode plate that has one surface which is bonded to electrodes on the first main surfaces of the semiconductor elements, with a first bonding material layer interposed therebetween, and extends over the electrodes on the first main surfaces of the two or more semiconductor elements, and a conductive plate that includes a first lead terminal and a semiconductor element bonding portion which is bonded to electrodes on the second main surfaces of the semiconductor elements. A second bonding material layer is interposed therebetween, and is connected to the electrodes on the second main surfaces of the two or more semiconductor elements. 1. A semiconductor device comprising:two or more semiconductor elements each of which has electrodes on a first main surface and a second main surface;an electrode plate that has one surface which is bonded to the first main surfaces of the two or more semiconductor elements, with a first bonding material layer interposed therebetween;a conductive plate that includes a first lead terminal and a semiconductor element bonding portion which is bonded to the second main surfaces of the two or more semiconductor elements, with a second bonding material layer interposed therebetween; anda second lead terminal that is connected to another surface of the electrode plate by a bonding wire.2. The semiconductor device according to claim 1 ,wherein the semiconductor element bonding portion of the conductive plate, the second bonding material layer, the semiconductor elements, the first bonding material layer, the electrode plate, and the bonding wire are sealed by a molding resin.3. The semiconductor device according to claim 1 ,wherein a space which is surrounded by the semiconductor elements, the electrode plate, and the conductive ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A method for fabricating a semiconductor device includes providing a semiconductor die, arranging an electrical connector over the semiconductor die, the electrical connector including a conductive core, an absorbing feature arranged on a first side of the conductive core, and a solder layer arranged on a second side of the conductive core, opposite the first side and facing the semiconductor die, and soldering the electrical connector onto the semiconductor die by heating the solder layer with a laser, wherein the laser irradiates the absorbing feature and absorbed energy is transferred from the absorbing feature through the conductive core to the solder layer. 1. A method for fabricating a semiconductor device , the method comprising:providing a semiconductor die;arranging an electrical connector over the semiconductor die, the electrical connector comprising a conductive core, an absorbing feature arranged on a first side of the conductive core, and a solder layer arranged on a second side of the conductive core, opposite the first side and facing the semiconductor die; andsoldering the electrical connector onto the semiconductor die by heating the solder layer with a laser,wherein the laser irradiates the absorbing feature and absorbed energy is transferred from the absorbing feature through the conductive core to the solder layer.2. The method of claim 1 , wherein the material of the solder layer has a melting point that is lower than a melting point of the material of the conductive core claim 1 , and wherein the absorbed energy is sufficient to melt the material of the solder layer but insufficient to melt the material of the conductive core.3. The method of claim 1 , wherein an absorptance for the laser beam of the absorbing feature is higher than an absorptance for the laser beam of the conductive core.4. The method of claim 1 , wherein the absorbing feature comprises an absorbing layer or an antireflection layer claim 1 , and wherein the absorbing layer or ...

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME

A semiconductor device includes, an alloy layer sandwiched between a first Ag layer formed on a mounting board or circuit board and a second Ag layer formed on a semiconductor element, wherein the alloy layer contains an intermetallic compound of AgSn formed by Ag components of the first Ag layer and the second Ag layer and Sn, and wherein a plurality of wires containing Ag are arranged extended from an outside-facing periphery of the alloy layer. 1. A semiconductor device in which a semiconductor element is bonded to a mounting board , said semiconductor device comprising:an alloy layer sandwiched between a first Ag layer formed on the mounting board and a second Ag layer formed on the semiconductor element;{'sub': '3', 'wherein the alloy layer contains an intermetallic compound of AgSn formed by Ag components of the first Ag layer and the second Ag layer and Sn, and a plurality of wires containing Ag are arranged as being extended from an outside-facing periphery of the alloy layer.'}2. The semiconductor device of claim 1 , wherein the wires are arranged as being extended in the same direction.3. The semiconductor device of claim 1 , wherein the wires are arranged as being extended radially from the outside-facing periphery of the alloy layer.4. The semiconductor device of claim 1 , wherein claim 1 , in the wires claim 1 , as a material other than Ag claim 1 , there is added at least one of Pd claim 1 , Ni claim 1 , Cu claim 1 , Fe claim 1 , Au claim 1 , Pt claim 1 , Al claim 1 , Sn claim 1 , Sb claim 1 , Ti and P.5. The semiconductor device of claim 1 , wherein the semiconductor element is formed of a wide bandgap semiconductor material.6. (canceled)7. A semiconductor device fabrication method of fabricating a semiconductor device in which a semiconductor element is bonded to a mounting board claim 1 , said semiconductor device fabrication method comprising:a wire structure forming step of forming a wire structure in which a plurality of wires containing Ag are ...

METHOD FOR FABRICATING MULTI-CHIP STACK STRUCTURE

A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficultly. 1. A method for fabricating a multi-chip stack structure , comprising:disposing a first chip group comprising a plurality of first chips on a chip carrier in a step-like manner, disposing a second chip on the first chip on top of the first chip group, wherein the first and second chips are electrically connected to the chip carrier through bonding wires;stacking a third chip on the first chip group and the second chip with an insulative film provided therebetween, the insulative film covering part of the ends of the bonding wire of the first chip on the top of the first chip group and at least part of the second chip; andelectrically connecting the third chip with the chip carrier through bonding wires.2. The method of claim 1 , wherein planar size of the second chip is smaller than that of the first chip.3. The method of claim 1 , wherein the first and third chips are memory chips claim 1 , and the second chip is a controller ...

CHIP ARRANGEMENT AND METHOD FOR FORMING A CONTACT CONNECTION

The invention relates to a chip arrangement () and to a method for forming a contact connection () between a chip (), in particular a power transistor or the like, and a conductor material track (), the conductor material track being formed on a non-conductive substrate (), the chip being arranged on the substrate or on a conductor material track (), a silver paste () or a copper paste being applied to each of a chip contact surface () of the chip and the conductor material track (), a contact conductor () being immersed into the silver paste or the copper paste on the chip contact surface and into the silver paste or the copper paste on the conductor material track, a solvent contained in the silver paste or the copper paste being at least partially vaporized by heating and the contact connection being formed by sintering the silver paste or the copper paste by means of laser energy. 1. A method for forming a contact connection between a chip and a conductor material track , the conductor material track being formed on a non-conductive substrate , the chip being arranged on the substrate or on another conductor material track ,comprising the steps ofapplying a silver paste or a copper paste to each of a chip contact surface of the chip and the conductor material track, immersing a contact conductor into the silver paste or the copper paste on the chip contact surface and into the silver paste or the copper paste on the conductor material track, heating the silver paste or the copper paste to at least partially vaporize a solvent contained in the silver paste or the copper paste and forming the contact connection by sintering the silver paste or the copper paste with laser energy.2. The method according to claim 1 ,whereina stranded wire is used as a contact conductor.3. The method according to claim 2 ,whereinthe stranded wire is at least partially infiltrated by the silver paste or the copper paste.4. The method according to claim 2 ,whereinonly one stranded wire ...

INTELLIGENT POWER MODULE AND MANUFACTURING METHOD THEREOF

An intelligent power module and a manufacturing method thereof are provided. The intelligent power module includes a radiator, an insulating layer, a circuit wiring, a circuit component and a metal wire. At least part of a lower surface of the radiator is defined as a heat dissipating area, the heat dissipating area is provided with a heat dissipating corrugation, the insulating layer is provided to an upper surface of the radiator, the circuit wiring is provided to the insulating layer, and the circuit component is provided to the circuit wiring and is connected to the circuit wiring via the metal wire. 1. An intelligent power module comprising:a radiator, at least part of a lower surface of the radiator defining a heat dissipating area, the heat dissipating area being provided with a heat dissipating corrugation;an insulating layer provided to an upper surface of the radiator;a circuit wiring provided to the insulating layer; anda circuit component provided to the circuit wiring and connected to the circuit wiring via a metal wire.2. The intelligent power module according to claim 1 , wherein the radiator is configured as a paper radiator having wet-type carbon composite material function or the radiator is configured as a paper radiator made from an insulating material capable of withstanding temperature of above 350° C.3. The intelligent power module according to claim 1 , wherein a plurality of heat dissipating corrugations are provided claim 1 , the plurality of heat dissipating corrugations are spaced apart from each other or the plurality of heat dissipating corrugations are arranged continuously.4. The intelligent power module according to claim 1 , wherein a distance between an outer edge of the heat dissipating corrugation and an outer edge of the lower surface of the radiator is more than 1 mm.5. The intelligent power module according to claim 1 , to wherein the heat dissipating area protrudes downwards to form a boss and the heat dissipating corrugation ...

UNPACKED STRUCTURE FOR POWER DEVICE OF RADIO FREQUENCY POWER AMPLIFICATION MODULE AND ASSEMBLY METHOD THEREFOR

A power device without a package structure in a radio frequency power amplifier module and an assembly method for a radio frequency power amplifier module are provided. The radio frequency power amplification module includes the power device, a heat dissipating plate and a printed circuit board. The power device includes a carrier flange, a plurality of electronic elements and bond-wires, and the electronic elements are adhered to the carrier flange, the power device and the printed circuit board are fixed on the heat dissipating plate, the electronic elements of the power device are connected with each other through the bond-wires, and the electronic elements are directly connected to the printed circuit board through the bond-wires. The electronic elements include at least one passive device, a decoupling capacitor is disposed on the printed circuit board, and the decoupling capacitor is connected to the passive device through the bond-wires. 1. A power device without a package structure in a radio frequency power amplifier module , wherein the radio frequency power amplifier module comprises the power device , a heat dissipating plate and a printed circuit board ,wherein the printed circuit board has an opening and the printed circuit board with the opening is fixed on the heat dissipating plate,the power device comprises a carrier flange, a plurality of electronic elements and bond-wires, the electronic elements are adhered to the carrier flange, and the carrier flange adhered with the electronic elements is embedded into the opening of the printed circuit board and fixed on the heat dissipating plate,the electronic elements of the power device are connected with each other through the bond-wires, the electronic elements are directly connected to the printed circuit board through the bond-wires, and the electronic elements comprise at least one passive device; anda decoupling capacitor is disposed on the printed circuit board, and the decoupling capacitor is ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

Disclosed is a semiconductor device in which, when two adjacent semiconductor chips are coupled with bonding wires, a short circuit between the adjacent bonding wires can be suppressed. A first bonding wire, a second bonding wire, a third bonding wire, and a fourth bonding wire are lined up in this order along a first side. When viewed from a direction perpendicular to a chip mounting part, a maximum of the space between the first bonding wire and the second bonding wire is larger than that of the space between the second bonding wire and the third bonding wire. Further, a maximum of the space between the second bonding wire and the third bonding wire is larger than that of the space between the third bonding wire and the fourth bonding wire. 1. A semiconductor device comprising:a first semiconductor chip that is a rectangle having a first side, a second side facing the first side, a third side, and a fourth side;a second semiconductor chip that is a rectangle having a fifth side, a sixth side facing the fifth side, a seventh side, and an eighth side;a chip mounting part, over the same surface of which the first semiconductor chip and the second semiconductor chip are mounted; anda plurality of bonding wires that couple the first semiconductor chip to the second semiconductor chip,wherein the first side of the first semiconductor chip faces the fifth side of the second semiconductor chip,wherein the first semiconductor chip has a plurality of first electrode pads arranged along the first side,wherein the second semiconductor chip has a plurality of second electrode pads arranged along the fifth side,wherein, of the bonding wires, a first bonding wire, a second bonding wire, a third bonding wire, and a fourth bonding wire are lined up in this order along the first side,wherein, when viewed from a direction perpendicular to the chip mounting part, a maximum of a space between the first bonding wire and the second bonding wire is larger than that of a space between the ...

SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SOLDERING SUPPORT JIG

A semiconductor device manufacturing method includes: applying solder to an arrangement area of a substrate, the substrate having a connection area to which a wiring member is to be directly connected, the connection area neighboring the arrangement area; arranging a component on the arrangement area via the solder; and soldering the component to the arrangement area by heating the solder while covering the connection area. A soldering support jig includes a columnar covering member having a covering surface at a bottom of the columnar covering member. 1. A semiconductor device manufacturing method comprising:applying solder to an arrangement area of a substrate, the substrate having a connection area to which a wiring member is to be directly connected, the connection area neighboring the arrangement area;arranging a component on the arrangement area via the solder; andsoldering the component to the arrangement area by heating the solder while covering the connection area.2. The semiconductor device manufacturing method according to claim 1 , whereinthe soldering is performed by heating the solder while covering the connection area using a soldering support jig arranged on the substrate so that a covering surface of the soldering support jig covers the connection area,the soldering support jig includes a columnar covering member, andthe covering surface is at a bottom of the columnar covering member.3. The semiconductor device manufacturing method according to claim 1 , further comprising claim 1 , after the soldering claim 1 , directly bonding the wiring member to the connection area.4. The semiconductor device manufacturing method according to claim 2 , wherein the arranging the component includes:arranging a plate-shaped positioning jig on the substrate, the positioning jig having a lower opening formed in a principal surface of the positioning jig, the lower opening corresponding to the arrangement area; andarranging the component on the arrangement area, based ...

Straight wirebonding of silicon dies

A method including stacking a number of silicon dice such that one or more edges of the dice are in vertical alignment, where the one or more edges include a number of connection pads. The method also includes positioning a connecting wire on a substantially perpendicular axis to the one or more edges. The connecting wire includes a number of solder blocks formed thereon. The solder blocks are spaced at intervals associated with a distance between a first set of aligned connection pads on the dice. The connecting wire is positioned such that the solder blocks are in contact with the first set of aligned connection pads. The method also includes applying heat to cause the solder blocks to reflow and physically and electrically couple the connecting wire to the connection pads.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes: an interposer mounted on an upper surface of a printed board; a first semiconductor element mounted on an upper surface of the interposer; a second semiconductor element mounted on the upper surface of the printed board and performing conversion between an optical signal and an electrical signal; and a bonding wire connecting a first pad and a second pad, the first pad being provided on the upper surface of the interposer, the second pad being provided on an upper surface of the second semiconductor element, the first semiconductor element lowers a speed of an electrical signal input from the second semiconductor element and outputs the electrical signal to the printed board, and increases a speed of an electrical signal and outputs the electrical signal to the second semiconductor element via the interposer and the bonding wire. 1. A semiconductor device comprising:a printed board;an interposer mounted on an upper surface of the printed board;a first semiconductor element mounted on an upper surface of the interposer;a second semiconductor element that is mounted on the upper surface of the printed board, is adjacent to the interposer, and performs conversion between an optical signal and an electrical signal; anda bonding wire that connects a first pad and a second pad, the first pad being provided on the upper surface of the interposer, the second pad being provided on an upper surface of the second semiconductor element,wherein the first semiconductor element lowers a speed of an electrical signal input from the second semiconductor element via the bonding wire and the interposer and outputs the electrical signal to the printed board, and increases a speed of an electrical signal input from the printed board and outputs the electrical signal to the second semiconductor element via the interposer and the bonding wire.2. The semiconductor device according to claim 1 , whereinthe first pad is provided at an edge of the upper surface ...

LEADFRAME PACKAGE WITH STABLE EXTENDED LEADS

Embodiments of the present disclosure are directed to leadframes having the cantilevered extension that includes an integral support on the end of the lead nearest the die pad. A support integral to the leadframe allows the support to be built to the proper height to support the cantilevered lead in each package and reduces or eliminates the upward, downward, and side to side deflections caused or allowed by supports built-in to the tooling of the manufacturing equipment. Also, by building the support into the leadframe, the leadframes may be pretaped prior to the die attach and wire bonding steps of the manufacturing process. 1. A method of forming a semiconductor package , the method comprising:attaching a semiconductor die to surfaces of a die pads;electrically coupling the semiconductor die to a plurality of leads, the plurality of leads located near and spaced apart from at least one side of the die pad, the plurality of leads having lands at a second end of the lead and a wire bonding surface at a first end of the lead and integral extensions that support each of the first ends of the leads, the first ends being nearer the die pad than the second ends;encapsulating the semiconductor die; andremoving the integral extensions to form cavities beneath the first ends of the leads.2. The method of claim 1 , further comprising sealing the cavities beneath the first ends.3. The method of claim 1 , further comprising sealing the cavities beneath the first ends with epoxy.4. The method of claim 1 , further comprising sealing the cavities beneath the first ends with silicone.5. The method of claim 1 , further comprising sealing the cavities beneath the first ends with a sealing structure that extends a first distance from a bottom surface of the lands.6. The method of claim 1 , further comprising coupling a printed circuit board to the lands with solder.7. The method of wherein a sealing structure contacts the printed circuit board.8. The method of wherein solder has a ...

Semiconductor Module and Method for Manufacturing the Same

There is provided a semiconductor module and a method for manufacturing the same which make it possible to joint the electrode of the bare-chip transistor and the wiring pattern on the substrate by solder mounting operation, in the same process of solder mounting operation for mounting the bare-chip transistor or other surface mounting devices on the wiring patterns on the substrate. A semiconductor module includes: a plurality of wiring patterns formed on an insulating layer; a bare-chip transistor mounted on one wiring pattern out of the plurality of wiring patterns via a solder; and a copper connector constituted of a copper plate for jointing an electrode formed on a top surface of the bare-chip transistor and another wiring pattern out of the plurality of wiring patterns via a solder. 19-. (canceled)10. A semiconductor module comprising:a substrate made of metal;an insulating layer formed on the substrate;a plurality of wiring patterns formed on the insulating layer;a bare-chip transistor mounted on one wiring pattern out of the plurality of wiring patterns via a solder; anda copper connector constituted of a copper plate for jointing an electrode formed on a top surface of the bare-chip transistor and another wiring pattern out of the plurality of wiring patterns via a solder, whereinthe bare-chip transistor is a bare-chip FET having a source electrode and a gate electrode formed on a top surface thereof,the copper connector includes a source electrode copper connector and a gate electrode copper connector,the source electrode of the bare-chip FET and the another wiring pattern out of the plurality of wiring patterns are jointed by the source electrode copper connector via a solder,the gate electrode of the bare-chip FET and a further another wiring pattern out of the plurality of wiring patterns is jointed by the gate electrode copper connector via a solder,the gate electrode copper connector falls into one type, and the source electrode copper connector ...

Chip package, method of forming a chip package and method of forming an electrical contact

In various embodiments, a method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.

Package with roughened encapsulated surface for promoting adhesion

A package comprising at least one electronic chip, a first heat removal body thermally coupled to a first main surface of the at least one electronic chip and configured for removing thermal energy from the at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, and part of the first heat removal body, wherein at least part of a surface of the first heat removal body is roughened.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Reliability of a semiconductor device is improved. 1. A method of manufacturing a semiconductor device , the method comprising the steps of:(a) preparing a semiconductor chip having a pad electrode made of first copper, on a main surface of the semiconductor chip;(b) preparing a base material having a chip mounting portion and a lead;(c) after the step (b), mounting the semiconductor chip in the chip mounting portion; and(d) after the step (c), coupling the pad electrode and the lead by using a wire which is made of second copper and has a ball portion and a wire portion,wherein the step (d) includes the steps of(d-1) exposing the wire and the pad electrode to a reducing gas atmosphere, forming a first hydroxyl layer on a surface of the ball portion, and forming a second hydroxyl layer on a surface of the pad electrode,(d-2) a first bonding step of joining the ball portion to the pad electrode through the first hydroxyl layer and the second hydroxyl layer, and(d-3) after the first bonding step, joining the ball portion to the pad electrode by performing a heat treatment on the semiconductor chip and the base material.2. The method of manufacturing a semiconductor device according to claim 1 ,wherein the reducing gas atmosphere contains nitrogen and hydrogen.3. The method of manufacturing a semiconductor device according to claim 1 ,wherein the second hydroxyl layer is formed on a surface of an oxidized layer formed on a surface of the pad electrode.4. The method of manufacturing a semiconductor device according to claim 3 ,wherein after the step (d-2), a first bonding layer foamed by first hydrogen bond and first ionic bond is formed between the ball portion and the pad electrode.5. The method of manufacturing a semiconductor device according to claim 4 ,wherein the step (d-2) is performed in 130° C.-250° C.6. The method of manufacturing a semiconductor device according to claim 4 ,wherein the first ionic bond included in the first bonding layer is formed of a first ...

Laser-Induced Forming and Transfer of Shaped Metallic Interconnects

A method of forming and transferring shaped metallic interconnects, comprising providing a donor substrate comprising an array of metallic interconnects, using a laser system to prepare the metallic interconnects, forming shaped metallic interconnects, and transferring the shaped metallic interconnect to an electrical device. An electronic device made from the method of providing a donor ribbon, wherein the donor ribbon comprises an array of metal structures and a release layer on a donor substrate, providing a stencil to the metal structures on the donor substrate, applying a laser pulse through the donor substrate to the metal structures, and directing the metal structures to an electronic device. 1. A method of forming and transferring shaped metallic interconnects , comprising:providing a donor substrate comprising an array of metallic interconnects;using a laser system to prepare the metallic interconnects;forming shaped metallic interconnects; andtransferring the shaped metallic interconnect to an electrical device.2. The method of forming and transferring shaped metallic interconnects of claim 1 , further comprising the steps of:delivering laser pulses to the metallic interconnects on the donor substrate; andutilizing two independent translation stages to allow the movement of the donor substrate with respect to the receive substrate for alignment and focusing.3. The method of forming and transferring shaped metallic interconnects of claim 1 , wherein the step of providing a donor substrate comprising an array of metallic interconnects further includes the steps of:forming an adhesion/release layer on the donor substrate;wherein the adhesion/release layer comprises a material with high UV absorption and wherein the material softens or melts above room temperature;placing a metal foil on the adhesion/release layer;bonding the metal foil to the adhesion/release layer; andpatterning the metal foil by machining or etching.4. The method of forming and transferring ...

Method for fabricating an electronic device

The method for fabricating a device includes the following successive steps: providing a first substrate made from silicon of (100), (110) or (111) orientation, from a material of III-IV type or from a material of II-VI type, provided with at least one salient metal pad, and providing a second substrate; fixing the first substrate with the second substrate, the at least one metal pad forming a blocking means preventing movement beyond a threshold position; and performing an anneal of the metal pad so as to melt the metal pad and eliminate the blocking means.

Semiconductor device

An object of the present invention is to stabilize and strengthen the strength of a bonding part between a metal electrode on a semiconductor chip and metal wiring connected thereto using a simple structure. Provided is a semiconductor device including a metal layer 130 on a surface of a metal electrode 120 formed on a semiconductor chip 110 , the metal layer 130 consisting of a metal or an alloy different from a constituent metal of the metal electrode 120 , metal wiring 140 is connected to the metal layer 130 via a bonding part 150 , wherein the constituent metal of the metal layer 130 is a metal or an alloy different from the constituent metal of the metal electrode 120 , and the bonding part 150 has an alloy region harder than the metal wiring 140.

INK PRINTED WIRE BONDING

An integrated circuit package with improved reliability and methods for creating the same are disclosed. More specifically, integrated circuit packages are created using one or more sacrificial layers that provide support for ink printed wires prior to package processing, but are removed during package processing. Once each of the sacrificial layers is removed, molding compound is placed around each ink printed wire, which may have a substantially rectangular cross section that can vary in dimension along a length of a given wire. While substantially surrounding each wire in and of itself improves reliability, removing non-conductive paste, fillets, or other adhesive materials also minimizes adhesion issues between the molding compound and those materials, which increases the bond of the molding compound to the package and its components. The net result is a more reliable integrated circuit package that is less susceptible to internal cracking and wire damage. 1. A device , comprising:a package substrate;a plurality of contact pads on the package substrate;a first die coupled to the package substrate;a first plurality of ink printed wires, the first plurality of ink printed wires electrically coupled between the plurality of contact pads and the first die, at least one of the first plurality of ink printed wires having a first width adjacent to the first die and a second width adjacent to the respective one of the plurality of contact pads, the first width being different than the second width.2. The device of wherein the first width is smaller than the second width.3. The device of wherein the first die includes a plurality of pillars claim 1 , the first plurality of ink printed wires being coupled between the plurality of pillars and the plurality of contact pads.4. The device of wherein at least one of the first plurality of ink printed wires is coupled to a top and side surface of one of the plurality of pillars.5. The device of claim 1 , further comprising a ...

SiC SEMICONDUCTOR DEVICE

An SiC semiconductor device includes an SiC chip having a first main surface at one side and a second main surface at another side, a first main surface electrode including a first Al layer and formed on the first main surface, a pad electrode formed on the first main surface electrode and to be connected to a lead wire, and a second main surface electrode including a second Al layer and formed on the second main surface. 1. An SiC semiconductor device comprising:an SiC chip having a first main surface at one side and a second main surface at another side;a first main surface electrode including a first Al layer and formed on the first main surface;a pad electrode formed on the first main surface electrode and to be connected to a lead wire; anda second main surface electrode including a second Al layer and formed on the second main surface.2. The SiC semiconductor device according to claim 1 , further comprising:an insulating layer covering the first main surface electrode on the first main surface and having a pad opening exposing a portion of the first main surface electrode; andwherein the pad electrode is formed on the first main surface electrode inside the pad opening.3. The SiC semiconductor device according to claim 2 , whereinthe SiC chip has a side surface connecting the first main surface and the second main surface andthe insulating layer has a peripheral edge formed at an interval from the side surface on the first main surface.4. The SiC semiconductor device according to or claim 2 , wherein the insulating layer includes a resin layer.5. The SiC semiconductor device according to claim 1 , wherein the pad electrode includes a metal material differing from the first main surface electrode.6. The SiC semiconductor device according to claim 1 , wherein the pad electrode includes at least one among an Ni layer claim 1 , a Pd layer claim 1 , and an Au layer.7. The SiC semiconductor device according to claim 1 , wherein the pad electrode includes an Ni layer ...

Semiconductor sensor chips

Semiconductor sensor chips are provided. In some embodiments, a semiconductor sensor chip can include at least one wire bond pad on one side thereof, at least one bond pad on another, opposite side thereof, and at least one through-silicon via (TSV) extending therebetween and electrically connected to the bond pads on opposite sides of the chip. Each of the bond pads can have a wire attached thereto. In some embodiments, a semiconductor sensor chip can include a pressure sensor, a substrate, and a resistor in a well that provides p-n junction isolation from a body of the substrate. In some embodiments, a semiconductor sensor chip can include a plurality of wire bonds pads with a wire soldered to each of the bond pads. Each of the wires can be soldered with a longitudinal length thereof soldered to its associated bond pad.

Semiconductor packages with an intermetallic layer

A method of forming a semiconductor package. Implementations include forming on a die backside an intermediate metal layer having multiple sublayers, each including a metal selected from the group consisting of titanium, nickel, copper, silver, and combinations thereof. A tin layer is deposited onto the intermediate metal layer and is then reflowed with a silver layer of a substrate to form an intermetallic layer having a melting temperature above 260 degrees Celsius and including an intermetallic consisting of silver and tin and/or an intermetallic consisting of copper and tin. Another method of forming a semiconductor package includes forming a bump on each of a plurality of exposed pads of a top side of a die, each exposed pad surrounded by a passivation layer, each bump including an intermediate metal layer as described above and a tin layer coupled to the intermediate metal layer is reflowed to form an intermetallic layer.

SEMICONDUCTOR POWER MODULE USING DISCRETE SEMICONDUCTOR COMPONENTS

An electronic power module is disclosed. The module includes a baseplate and a plurality of internally isolated discrete electronic devices mounted to the baseplate such that their electrical leads are oriented away from the baseplate. Electrical leads may be coupled to a printed circuit board (PCB). Other features disclosed include a thermal interface material and an application-specific heat sink. The assembly may be overmolded via injection molding or potted using an encapsulant. Example electronic devices include thyristors, diodes, and transistors. 1. An electronic power module comprising:a baseplate; anda plurality of internally isolated discrete electronic devices mounted to the baseplate;wherein each of the plurality of internally isolated discrete electronic devices includes electrical leads oriented away from the baseplate.2. The electronic power module of further comprising:a thermal interface material disposed between the plurality of internally isolated discrete electronic devices and the baseplate.3. The electronic power module of wherein:the thermal interface material comprises beryllium oxide, aluminum nitride, zinc oxide, or silicon dioxide.4. The electronic power module of wherein:the baseplate comprises copper.5. The electronic power module of wherein:the electrical leads are coupled to a printed circuit board (PCB).6. The electronic power module of wherein:the electrical leads are coupled to the PCB by soldering.7. The electronic power module of wherein:the baseplate is coupled to at least one heat sink.8. The electronic power module of wherein:the plurality of internally isolated discrete electronic devices and the baseplate are overmolded via injection molding.9. The electronic power module of wherein:the plurality of internally isolated discrete electronic devices and the baseplate are potted using an encapsulant.10. The electronic power module of wherein:each discrete electronic device is either a thyristor, a diode, or a transistor.11. A ...

RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A resin-encapsulated semiconductor device is manufactured by mounting semiconductor elements on respective die pad portions of a frame. Electrodes on the surface of the semiconductor elements are wire bonded to lead portions of the frame. The die pad portions, semiconductor elements and lead portions are encapsulated with resin, leaving a bottom surface part of the lead portions exposed. The lead portions are partially cut by a rotary blade from an upper side of the resin to form concave parts in the lead portions, which are wet-etched to form exposed lead upper end parts. A plated layer is formed on the lead upper end parts and the lead bottom surface parts. The remaining parts of the lead portions with the plated layer are cut to separate the resin-encapsulated semiconductor device into individual pieces. 1. A method of manufacturing a resin-encapsulated semiconductor device , comprising:preparing one of a frame and an electroformed substrate, including a plurality of units each including a die pad portion and a plurality of lead portions disposed opposite to the die pad portion;mounting a semiconductor element on each of the die pad portions of the one of the frame and the electroformed substrate, and connecting the plurality of lead portions and electrodes on a surface of the semiconductor element to each other via a metal thin wire;encapsulating the die pad portions, the semiconductor elements, and the plurality of lead portions with an encapsulating resin so that a bottom surface part of each of the plurality of lead portions is exposed;performing lead pre-cutting by cutting a cutting region of each of the plurality of lead portions by a rotary blade from an upper surface side of the encapsulating resin, the cutting region corresponding to a boundary between the plurality of units of the one of the frame and the electroformed substrate after the resin-encapsulation, thereby forming a concave part at the cutting region while leaving a part of the each of the ...

SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SOLDERING SUPPORT JIG

A semiconductor device manufacturing method includes: applying solder to an arrangement area of a substrate, the substrate having a connection area to which a wiring member is to be directly connected, the connection area neighboring the arrangement area; arranging a component on the arrangement area via the solder; and soldering the component to the arrangement area by heating the solder while covering the connection area. A soldering support jig includes a columnar covering member having a covering surface at a bottom of the columnar covering member. 1. A semiconductor device manufacturing method comprising:applying solder to an arrangement area of a substrate, the substrate having a connection area to which a wiring member is to be directly connected, the connection area neighboring the arrangement area;arranging a component on the arrangement area via the solder; andsoldering the component to the arrangement area by heating the solder while covering the connection area.2. The semiconductor device manufacturing method according to claim 1 , whereinthe soldering is performed by heating the solder while covering the connection area using a soldering support jig arranged on the substrate so that a covering surface of the soldering support jig covers the connection area,the soldering support jig includes a columnar covering member, andthe covering surface is at a bottom of the columnar covering member.3. The semiconductor device manufacturing method according to claim 1 , further comprising claim 1 , after the soldering claim 1 , directly bonding the wiring member to the connection area.4. The semiconductor device manufacturing method according to claim 2 , wherein the arranging the component includes:arranging a plate-shaped positioning jig on the substrate, the positioning jig having a lower opening formed in a principal surface of the positioning jig, the lower opening corresponding to the arrangement area; andarranging the component on the arrangement area, based ...

Integrated wire bonder and 3d measurement system with defect rejection

An apparatus comprises a wire bonder system including a wire bonding device, a measuring device and a rejection device. The wire bonding device is configured to attach wire bond type electrical interconnect to an electronic assembly. A wire bond is formed between a first semiconductor device and a second electronic device to form at least a portion of the electronic assembly. The measuring device is configured to perform a three dimensional measurement associated with a wire bond, and the rejection device is configured to identify an electronic assembly for rejection according to the three dimensional wire bond measurement.

SEMICONDUCTOR MODULE COMPRISING A SEMICONDUCTOR AND COMPRISING A SHAPED METAL BODY THAT IS ELECTRICALLY CONTACTED BY THE SEMICONDUCTOR

Semiconductor module including a semiconductor and including a shaped metal body that is electrically contacted by the semiconductor, for forming a contact surface for an electrical conductor, wherein the shaped metal body is bent or folded. A method is also described for establishing electrical contacting of an electrical conductor on a semiconductor, said method including the steps of: fastening a bent or folded shaped metal body of a constant thickness to the semiconductor by means of a first fastening method and then fastening the electrical conductor to the shaped metal body by means of a second fastening method. 1. A semiconductor module comprising a semiconductor and comprising a shaped metal body that is electrically contacted by the semiconductor , for forming a contact surface for an electrical conductor ,whereinthe shaped metal body is bent or folded.2. The semiconductor module according to claim 1 , wherein the shaped metal body is bent multiple times or folded multiple times.3. The semiconductor module according to claim 1 , wherein the shaped metal body is corrugated.4. The semiconductor module according to claim 1 , wherein the shaped metal body consists of aluminum (Al) or copper (Cu).5. The semiconductor module according to claim 1 , wherein the shaped metal body is connected to the semiconductor by means of sintering.6. The semiconductor module according to claim 1 , wherein the shaped metal body is connected to the semiconductor by means of adhesive bonding.7. The semiconductor module according to claim 1 , wherein the shaped metal body is connected to the semiconductor by means of soldering.8. The semiconductor module according to claim 1 , wherein the shaped metal body is connected to the semiconductor by means of nanowires.9. The semiconductor module according to claim 1 , wherein the electrical conductor is a lead frame or a ribbon.10. The semiconductor module according to claim 1 , wherein the semiconductor is produced from silicon carbide ( ...

Power module package and method for manufacturing the same

Disclosed relates to a power module package and a method for manufacturing the same. The power module package includes a lower substrate on which a pattern is formed, a power semiconductor element and a ribbon which are separated apart from each other at a predetermined distance to be mounted on an upper surface of the lower substrate, a first spacer attached to an upper portion of the power semiconductor element via a first adhesive layer, a second spacer attached to an upper portion of the ribbon via a second adhesive layer, and an upper substrate attached to an upper portion of each of the first and second spacers via a third adhesive layer.

Method and apparatus for multi-chip structure semiconductor package

A packaged semiconductor device may include a leadframe and a die carrier mounted to the leadframe. The die carrier is formed from an electrically and thermally conductive material. A die is mounted to a surface of the die carrier with die attach material having a melting point in excess of 240° C. A method may include providing the die carrier, melting the die attach material at a temperature in excess of 240° C. to attach the die to the surface of the die carrier to form a sub-assembly, attaching the sub-assembly to a leadframe, electrically interconnecting the die and the leadframe, and enclosing at least portions of the die and the leadframe to form a packaged device.

DIE-TO-DIE INDUCTIVE COMMUNICATION DEVICES AND METHODS

Embodiments of inductive communication devices include first and second IC die and an inductive coupling substrate. The first IC die has a first coil. The inductive coupling substrate has a second coil and a first signal communication interface (e.g., a third coil or a contact). The second IC die has a second signal communication interface (e.g., a fourth coil or a contact). The first IC die and the inductive coupling substrate are arranged so that the first and second coils are aligned across a gap between the first IC die and the inductive coupling substrate. A dielectric component is positioned within the gap between the first and second coils to galvanically isolate the first IC die and the inductive coupling substrate. During operation, signals are conveyed between the first and second IC die through inductive coupling between the coils and communication through the signal communication interfaces. 1. A device comprising:a first integrated circuit (IC) die that includes a first coil proximate to a first surface of the first IC die, and a plurality of first bond pads, wherein the plurality of first bond pads are electrically coupled to the first coil;an inductive coupling substrate that includes a second coil and a first signal communication interface, wherein the second coil is proximate to a first surface of the inductive coupling substrate, and the second coil is electrically coupled to the first signal communication interface;a second IC die that includes a second signal communication interface and a plurality of second bond pads, wherein the second signal communication interface is electrically coupled to the plurality of second bond pads, and whereinthe first IC die, the second IC die, and the inductive coupling substrate are arranged within the device so that the first surface of the inductive coupling substrate faces the first surface of the first IC die and a first surface of the second IC die, the first coil and the second coil are aligned with each ...

Chip-on-lead package and method of forming

In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads. The one major surface is electrically connected to the first lead, and electrically isolated from the second lead. The other major surface where active device are formed may be electrically connected to the second lead.

SYSTEM AND METHOD FOR ROUTING SIGNALS IN COMPLEX QUANTUM SYSTEMS

Embodiments of the present invention disclose a computer system having a plurality of quantum circuits arranged in a two-dimensional plane-like structure, the quantum circuits comprising qubits and busses (i.e., qubit-qubit interconnects), and a method of formation therefor. A quantum computer system comprises a plurality of quantum circuits arranged in a two-dimensional pattern. At least one interior quantum circuit, not along the perimeter of the two-dimensional plane of the plurality of quantum circuits, contains a bottom chip, a device layer, a top chip, and a routing layer. A signal wire connects the device layer to the routing layer, wherein the signal wire breaks the two dimensional plane, for example, the signal wire extends into a different plane. 1. (canceled)2. A quantum computer system comprising:a plurality of quantum circuits arranged in a two-dimensional layout; andwherein the plurality of quantum circuits includes at least one interior quantum circuit that is not along a perimeter of the two-dimensional layout, wherein the at least one interior quantum circuit comprises a plurality of layers, a top layer of the plurality of layers including a through hole to a bottom layer of the plurality of layers; anda signal wire positioned at least partially within the through hole and connecting the bottom layer to the top layer.3. The quantum computer system of claim 2 , wherein the bottom layer of the plurality of layers comprises a bottom chip having a device layer and the top layer of the plurality of layers comprises a top chip having a routing layer; andwherein the signal wire communicatively connects the device layer of the bottom chip to the routing layer of the top chip, and wherein the signal wire is not parallel to a plane of the two dimensional layout.4. The quantum computer system of claim 3 , wherein the through hole is formed by reactive ion etching or by laser milling.5. The quantum computer system of claim 4 , wherein the through hole has a ...

Micro-coaxial wire bonding

A method includes attaching a micro-coaxial wire to electrical contacts in a substrate, the micro-coaxial wire including a core wire, a bonded section, and a shield layer, the electrical contacts including a first electrical contact and a second electrical contact. Attaching the micro-coaxial wire to the electrical contacts includes connecting a core wire of the micro-coaxial wire to the first electrical contact including forming a bonded section by bonding the core wire to the first electrical contact, and then depositing solder onto the bonded section of the core wire.

METHOD AND DEVICE FOR ESTABLISHING A WIRE CONNECTION AS WELL AS A COMPONENT ARRANGEMENT HAVING A WIRE CONNECTION

A method and a device for establishing a wire connection between a first contact surface and at least one further contact surface. A contact end of a wire is positioned in a contact position relative to the first contact surface with a wire guiding tool. Subsequently, a mechanical, electrically conductive connection is established between the first contact surface and the contact end with a first solder material connection, and subsequently the wire guiding tool is moved to the further contact surface thus forming a wire section and establishing a further mechanical, electrically conductive connection between the wire section end and the further contact surface with a further solder material connection. 1. A method for establishing a wire connection between a first contact surface and at least one further contact surface , in which a contact end of a wire is positioned in a contact position relative to the first contact surface by means of a wire guiding tool and a contact area , which is formed between the first contact surface and the contact end , is subsequently wetted using an at least partially fused first solder material amount formed from a solder material molded piece in order to establish a first solder material connection in such manner that a mechanical , electrically conductive connection is formed between the first contact surface and the contact end ,the wire guiding tool is subsequently moved to the further contact surface in such a manner that a contact area is formed between a wire section end of a wire section, which is formed between the first contact surface and the further contact surface by means of the movement of the wire guiding tool, and the further contact surface,and the second contact area is subsequently wetted using an at least partially fused second solder material amount formed from a solder material molded piece in order to establish at least one further solder material connection in such a manner that a mechanical electrically ...

Semiconductor component with chip for the high-frequency range

The invention relates to a semiconductor component with a chip, especially with a high-frequency switching circuit. The semiconductor component further comprises a metal body on the chip and a supplementary circuit board. The supplementary circuit board is provided on an underside facing away from the metal body for connection with a printed-circuit board by means of reflow soldering. 1. A semiconductor component , comprisinga metal body on at least one chip and a supplementary circuit board,wherein the supplementary circuit board is provided on an underside facing away from the metal body for connection with a printed-circuit board by operations including soldering.2. The semiconductor component according to claim 1 ,wherein the supplementary circuit board at least partially surrounds the chip in the form of a frame.3. The semiconductor component according to claim 1 ,wherein the supplementary circuit board is fitted on the underside with at least one semiconductor element.4. The semiconductor component according to claim 1 ,wherein the supplementary circuit board provides at least one connecting tab for the electrical connection of the component to the printed-circuit board.5. The semiconductor component according to claim 4 ,wherein the connecting tab is movable in an elastic manner perpendicular to a printed-circuit board surface.6. The semiconductor component according to claim 4 ,wherein the metal body exposes the connecting tab by a structure including a recess.7. The semiconductor component according to claim 4 ,wherein the connecting tab comprises a plated insulating material.8. The semiconductor component according to claim 4 ,wherein the connecting tab provides on the underside at least one reflow soldering position for signal routing between component and printed-circuit board and/or at least one reflow soldering position for the ground connection between component and printed-circuit board.9. The semiconductor component according to claim 8 ,wherein the ...

Compact Class-F Chip and Wire Matching Topology

An amplifier circuit includes an RF input port, an RF output port, a reference potential port, and an RF amplifier having an input terminal and a first output terminal. An output impedance matching network electrically couples the first output terminal to the RF output port. A first inductor is electrically connected in series between the first output terminal and the RF output port, a first LC resonator is directly electrically connected between the first output terminal and the reference potential port, and a second LC resonator is directly electrically connected between the first output terminal and the reference potential port. The first LC resonator is configured to compensate for an output capacitance of the RF amplifier at a center frequency of the RF signal. The second LC resonator is configured to compensate for a second order harmonic of the RF signal.

ATTACHING PASSIVE COMPONENTS TO A SEMICONDUCTOR PACKAGE

Embodiments of the present disclosure provide a method comprising forming an electrically conductive structure on a surface of a semiconductor die, attaching the semiconductor die to a substrate, forming a molding compound to encapsulate the semiconductor die, forming an opening in the molding compound, the opening to at least partially expose the electrically conductive structure, and electrically coupling a passive component to the electrically conductive structure through the opening in the molding compound. Other embodiments may be described and/or claimed. 1. A method comprising:forming (i) a first electrically conductive structure formed on an active surface of the semiconductor die and (ii) a second electrically conductive structure formed on the active surface of the semiconductor die, and wherein the first electrically conductive structure provides (i) a power connection for the semiconductor die, or (ii) a ground connection for the semiconductor die;attaching the semiconductor die to a substrate;forming a single molding compound disposed to substantially encapsulate both the substrate and the semiconductor die, including substantially encapsulating the active surface of the semiconductor die, wherein the molding compound has a channel formed in the molding compound;forming an opening in the molding compound, wherein the channel (i) extends from the active surface of the semiconductor die to the opening on the molding compound and (ii) at least partially includes the second electrically conductive structure formed on the active surface of the semiconductor die;attaching a passive component to the molding compound at least partly over the opening on the exterior surface of the molding compound; andelectrically coupling the passive component to the active surface of the semiconductor die via the second electrically conductive structure through the channel in the molding compound.2. The method of claim 1 , wherein the second electrically conductive structure ...

Leadframe area array packaging technology

Embodiments of the present invention are directed to leadframe area array packaging technology for fabricating an area array of I/O contacts. A manufactured package includes a polymer material substrate, an interconnect layer positioned on top of the polymer material substrate, a die coupled to the interconnect layer via wire bonds or conductive pillars, and a molding compound encapsulating the die, the interconnect layer and the wire bonds or conductive pillars. The polymer material is typically formed on a carrier before assembly and is not removed to act as the substrate of the manufactured package. The polymer material substrate has a plurality of through holes that exposes the interconnect layer at predetermined locations and enables solder ball mounting or solder printing directly to the interconnect layer. In some embodiments, the semiconductor package includes a relief channel in the polymer material substrate to improve the reliability performance of the manufactured package.

FLEXIBLY-WRAPPED INTEGRATED CIRCUIT DIE

Embodiments of a flexibly-wrapped integrated circuit die device and a method for mounting a flexibly-wrapped integrated circuit die to a substrate are disclosed. In some embodiments, the flexibly-wrapped integrated circuit die device includes a substrate and a flexible integrated circuit die coupled to the substrate in a substantially vertical orientation with reference to a surface of the substrate. 1. An integrated circuit die device comprising:a substrate; anda curved integrated circuit die coupled to the substrate in a substantially vertical orientation with reference to a surface of the substrate.2. The integrated circuit die device of wherein the curved integrated circuit die comprises a segmented substrate material comprising a plurality of linked segments.3. The integrated circuit die device of wherein the curved integrated circuit die comprises an active side and an inactive side.4. The integrated circuit die device of wherein the active side comprises additional electronic circuitry with reference to the inactive side.5. The integrated circuit die device of and further comprising bonding wires coupling electronic circuitry on the curved integrated circuit die to circuitry on the substrate.6. The integrated circuit die device of and further comprising at least one integrated circuit die coupled to the substrate in a substantially horizontal orientation with reference to the curved integrated circuit die claim 1 , wherein the curved integrated circuit die wraps around at least a portion of the periphery of the at least one integrated circuit die.7. The integrated circuit die device of wherein electronic circuitry on the curved integrated circuit die is coupled to the at least one integrated circuit die with one or more bonding wires.8. The integrated circuit die device of wherein the curved integrated circuit die is coupled to the substrate in a circular pattern around the periphery of the at least one integrated circuit die.9. The integrated circuit die ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A method of manufacturing a semiconductor device including: bonding a wire constituted of copper on an electrode pad provided on a surface of a semiconductor substrate, wherein the electrode pad includes a hard metal layer harder than the wire as a surface layer of the electrode pad, a recess is provided in a surface of the hard metal layer, the wire before the bonding includes a linear portion and a ball portion provided at a distal end of the linear portion and having a diameter larger than a diameter of the linear portion, and the ball portion is bonded in the recess in the bonding. 1. A method of manufacturing a semiconductor device , the method comprising:bonding a wire constituted of copper on an electrode pad provided on a surface of a semiconductor substrate,whereinthe electrode pad comprises a hard metal layer harder than the wire as a surface layer of the electrode pad,a recess is provided in a surface of the hard metal layer,the wire before the bonding comprises a linear portion and a ball portion provided at a distal end of the linear portion and having a diameter larger than a diameter of the linear portion, andthe ball portion is bonded in the recess in the bonding.2. The method of claim 1 , whereinthe recess comprises a bottom surface and a lateral surface, andthe ball portion is brought into contact with the bottom surface and the lateral surface in the bonding.3. The method of claim 1 , wherein a width of the recess is narrower than the diameter of the ball portion before the bonding.4. The method of claim 1 , wherein an inner volume of the recess is larger than a half of a volume of the ball portion before the bonding.5. The method of claim 1 , whereinthe electrode pad comprises a soft metal layer interposed between the hard metal layer and the semiconductor substrate, andthe soft metal layer is softer than the wire.6. A semiconductor device claim 1 , comprising:a semiconductor substrate;an electrode pad provided on a surface of the semiconductor ...

Abstracted NAND Logic In Stacks

A microelectronic package may include a substrate having first and second surfaces each extending in first and second directions, a NAND wafer having a memory storage array, a bitline driver chiplet configured to function as a bitline driver, and a wordline driver chiplet configured to function as a wordline driver. The NAND wafer may be coupled to the first surface of the substrate, and the bitline and wordline driver chiplets may each be mounted to a front surface of the NAND wafer. The NAND wafer may have element contacts electrically connected with conductive structure of the substrate. The bitline and wordline driver chiplets may be elongated along the first and second directions, respectively. Front surfaces of the bitline driver chiplet and the wordline driver chiplet may be arranged in a single common plane and may be entirely contained within an outer periphery of the front surface of the NAND wafer.

Laser-Induced Forming and Transfer of Shaped Metallic Interconnects

A method of forming and transferring shaped metallic interconnects, comprising providing a donor substrate comprising an array of metallic interconnects, using a laser system to prepare the metallic interconnects, forming shaped metallic interconnects, and transferring the shaped metallic interconnect to an electrical device. An electronic device made from the method of providing a donor ribbon, wherein the donor ribbon comprises an array of metal structures and a release layer on a donor substrate, providing a stencil to the metal structures on the donor substrate, applying a laser pulse through the donor substrate to the metal structures, and directing the metal structures to an electronic device. 1. A method of forming and transferring shaped metallic interconnects , comprising:providing a donor substrate comprising an array of metallic interconnects;using a laser system to prepare the metallic interconnects;forming shaped metallic interconnects; andtransferring the shaped metallic interconnect to an electrical device.2. The method of forming and transferring shaped metallic interconnects of claim 1 , further including the step of:laser bending the shaped metallic interconnect and then transferring the shaped metallic interconnect onto a receiving substrate or device.3. The method of forming and transferring shaped metallic interconnects of claim 1 , further comprising the steps of:delivering laser pulses to the metallic interconnects on the donor substrate; andutilizing two independent translation stages to allow the movement of the donor substrate with respect to the receive substrate for alignment and focusing.4. The method of forming and transferring shaped metallic interconnects of claim 2 , wherein the laser fluence during bending of the shaped metallic interconnects is 1.1 J/cmfor 12.5 μm thick interconnects.5. The method of forming and transferring shaped metallic interconnects of claim 1 , wherein the step of providing a donor substrate comprising an ...

Method For Producing Wire Bond Connection And Arrangement For Implementing The Method

Method for producing wire bond connections between an electronic component or a module and a substrate with energy input into a bonding wire by an ultrasonic transducer, wherein during the energy input for forming a first wire bond connection, at least one bonding parameter characterizing the instantaneous state of the bonding wire is measured in dependence on time, the curve shape of the time dependence is differentiated by means of predetermined comparative criteria or curves into three curve sections and hereby the temporal course of the method into three phases, to be specific, a cleaning, a fusion and a tempering phase, and the energy fed into the ultrasonic transducer and/or the bonding force exerted on the bonding wire and/or the duration of the energy input into at least one partial section of at least the cleaning and the fusion phase, in particular each of the cleaning, fusion and tempering phases is/are controlled independent of the measurement result in quasi real time during the formation of the first wire bond connection or during the subsequent formation of a second wire bond connection of the same type in dependence on the curve shape in the associated curve section in a phase-specific manner. 1. Method for producing wire bond connections between an electronic component or a module and a substrate with energy input into a bonding wire by an ultrasonicduring the energy input for forming a first wire bond connection, at least one bonding parameter characterizing the instantaneous state of the bonding wire is measured in dependence on time, the curve shape of the time dependence is differentiated by means of predetermined comparative criteria or curves into three curve sections and hereby the temporal course of the method into three phases, to be specific, a cleaning, a fusion and a tempering phase, andthe energy fed into the ultrasonic transducer and/or the bonding force exerted on the bonding wire and/or the duration of the energy input into at least ...

SEMICONDUCTOR PACKAGING METHOD AND SEMICONDUCTOR PACKAGE DEVICE

The present disclosure provides a semiconductor packaging method and a semiconductor package device. The semiconductor packaging method includes providing a chip, where the chip includes a chip substrate having a front surface and a back surface, where the front surface includes a photosensitive region; soldering pads disposed at the front surface of the chip substrate surrounding the photosensitive region; a metal part formed on a side of each soldering pad facing away from the chip substrate; and a transparent protective layer formed on the front surface of the chip substrate, where a first end of the metal part is exposed by protruding over a surface of the transparent protective layer. The method further includes electrically connecting the first end of the metal part to a circuit board using a conductive connection part, such that the chip is electrically connected to the circuit board. 1. A semiconductor packaging method , comprising: a chip substrate having a front surface and a back surface, wherein the front surface includes a photosensitive region;', 'soldering pads disposed at the front surface of the chip substrate surrounding the photosensitive region;', 'a metal part formed on a side of each soldering pad facing away from the chip substrate; and', 'a transparent protective layer formed on the front surface of the chip substrate, wherein a first end of the metal part is exposed by protruding over a surface of the transparent protective layer; and, 'providing a chip, wherein the chip includeselectrically connecting the first end of the metal part to a circuit board using a conductive connection part, such that the chip is electrically connected to the circuit board.2. The method according to claim 1 , wherein providing the chip includes:providing a wafer, wherein the wafer includes a plurality of chip substrates arranged in a matrix and separated by dicing grooves between adjacent chip substrates, and the soldering pads are formed at the front surface of ...

WIRE-BONDING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Provided is a wire-bonding apparatus () including: a capillary () through which a wire () is inserted; a nonsticking determination circuit () configured to apply a predetermined electrical signal between a bonding target and the wire () in a clamped state and to determine whether or not the wire () and the bonding target is sticking as well as whether or not the wire () is disconnected based on a response of the application of the predetermined electrical signal; an annular projecting length detection ring () disposed coaxially with the capillary (); and a projecting length determination circuit () configured to determine whether or not a projecting length of a wire tail projecting from the tip of the capillary () is appropriate based on detection on whether or not power is conductive when a predetermined inspection voltage is applied between the wire () and the projecting length detection ring () as well as a presence of a discharge spark when a predetermined inspection high voltage is applied between the wire () and the projecting length detection ring (). 1. A wire bonding apparatus comprising:a capillary through which a wire is inserted;an annular wire projecting length detection ring disposed coaxially with the capillary; anda projecting length determination unit configured to determine whether or not a projecting length of the wire projecting from a tip of the capillary is appropriate based on detection on whether or not power is conductive when a predetermined inspection voltage is applied between the wire and the wire projecting length detection ring.2. The wire bonding apparatus according to claim 1 , Wherein a predetermined inspection high voltage is applied between the wire and the wire projecting length detection ring to detect a presence of a discharge spark claim 1 , if the power has been detected to be non-conductive when the predetermined inspection voltage is applied between the wire and the wire projecting length detection ring.3. The wire bonding ...

Semiconductor Device and Method of Manufacturing the Same

To improve the reliability of a semiconductor device. 1. A semiconductor device comprising:a semiconductor substrate;a plurality of wiring layers formed on the semiconductor substrate;a pad formed on an uppermost wiring layer of the plurality of wiring layers;a surface protection film which includes an opening on the pad and is made of an inorganic insulating film;a rewiring formed on the surface protection film; anda pad electrode which is formed on the rewiring, and is a region for connection with a wire,wherein the rewiring includes a pad electrode mounting portion on which the pad electrode is mounted, a connection portion which is connected to the pad, and an extended wiring portion which couples the pad electrode mounting portion and the connection portion, andthe pad electrode mounting portion has a rectangular shape when seen in a plan view.2. The semiconductor device according to claim 1 ,wherein the pad electrode covers an entire upper surface and a side surface of the pad electrode mounting portion.3. The semiconductor device according to claim 1 ,wherein a film thickness of the rewiring is five or more times a film thickness of the uppermost wiring layer on which the pad is formed.4. The semiconductor device according to claim 3 ,wherein the rewiring is made of a copper film.5. The semiconductor device according to claim 1 ,wherein the pad electrode mounting portion has two short sides and two long sides,the extended wiring portion is connected to one side of the two short sides, anda wiring width of the extended wiring portion is smaller than a length of the short side.6. The semiconductor device according to claim 5 ,wherein a first fin portion is connected to the other side of the two short sides, andthe first fin portion extends to an outer side of the pad electrode mounting portion.7. The semiconductor device according to claim 6 ,wherein the wire is formed on the pad electrode, andthe wire extends from the pad electrode mounting portion toward the ...

Electronic Device By Laser-Induced Forming and Transfer of Shaped Metallic Interconnects

An electronic device made from the method of providing a donor substrate comprising an array of metallic interconnects, using a laser system to prepare the metallic interconnects, forming shaped metallic interconnects, laser bending the shaped metallic interconnects; and transferring the shaped metallic interconnects onto a receiving substrate or device. 1. An electronic device made from the method of providing a donor ribbon , wherein the donor ribbon comprises an array of metal structures and a release layer on a donor substrate , providing a stencil to the metal structures on the donor substrate , applying a laser pulse through the donor substrate to the metal structures , laser bending the shaped metallic interconnect; and transferring the shaped metallic interconnect onto a receiving substrate or device.2. The electronic device of wherein the method further comprises the steps of delivering laser pulses to the metallic interconnects on the donor substrate; and utilizing two independent translation stages to allow the movement of the donor substrate with respect to the receive substrate for alignment and focusing.3. The electronic device of wherein the laser fluence during bending of the shaped metallic interconnects is 1.1 J/cmfor 12.5 μm thick interconnects and wherein the laser bending of the shaped metallic interconnect comprises the steps of placing a stencil over the metallic interconnects and firing the laser through the donor substrate into open regions of the stencil.4. The electronic device of wherein the step of providing a donor substrate comprising an array of metallic interconnects further includes the steps of dissolving a low temperature wax in toluene and forming a solution; spin coating the solution at room temperature and forming a wax layer; placing a copper foil over the wax layer; bonding the copper foil to the wax layer by heating and pressing at about 80° C.; applying a photoresist to the copper foil; exposing and developing the ...

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, AND POSITIONING JIG

A semiconductor device has a plurality of small-sized semiconductor chips disposed between an insulated circuit board having a conductive pattern and a terminal. The semiconductor device exhibits a high accuracy in positioning the semiconductor chips. The semiconductor device includes an insulated circuit board having a conductive pattern, a first semiconductor chip with a rectangular shape connected to the conductive pattern through a first joining material, a second semiconductor chip with a rectangular shape, disposed on the conductive pattern separated from the first semiconductor chip and connected to the conductive pattern through a second joining material, and a terminal disposed above the first semiconductor chip and the second semiconductor chip, connected to the first semiconductor chip through a third joining material, and connected to the second semiconductor chip through a fourth joining material. The terminal has a through-hole above a place between the first semiconductor chip and the second semiconductor chip. 1. A semiconductor device comprising:an insulated circuit board having a conductive pattern;a first semiconductor chip with a rectangular shape connected through a first joining material to the conductive pattern;a second semiconductor chip with a rectangular shape disposed on the conductive pattern separated from the first semiconductor chip and connected through a second joining material to the conductive pattern;a terminal disposed above the first semiconductor chip and the second semiconductor chip, connected to the first semiconductor chip through a third joining material, and connected to the second semiconductor chip through a fourth joining material, the terminal having a through-hole above a place between the first semiconductor chip and the second semiconductor chip.2. The semiconductor device according to claim 1 , wherein a gap between a side of the first semiconductor chip and a side of the second semiconductor chip claim 1 , the ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A soldering portion () and a Ni plating mark () are simultaneously forming by plating on a wiring pattern () of an insulating substrate (). A semiconductor chip () is mounted on the insulating substrate (). A position of the insulating substrate () is recognized by the Ni plating mark () and a wire () is bonded to the semiconductor chip (). An electrode () is joined to the soldering portion () by solder (). The insulating substrate (), the semiconductor chip (), the wire (), and the electrode () are encapsulated in an encapsulation material (). 1. A method of manufacturing a semiconductor device comprising:simultaneously forming a soldering portion and a mark by plating on a wiring pattern of an insulating substrate;mounting a semiconductor chip on the insulating substrate;recognizing a position of the insulating substrate by the mark and bonding a wire to the semiconductor chip;joining an electrode to the soldering portion by solder; andencapsulating the insulating substrate, the semiconductor chip, the wire, and the electrode in an encapsulation material.2. A method of manufacturing a semiconductor device comprising:forming a soldering portion on a wiring pattern of an insulating substrate;simultaneously forming a protective film covering a periphery of the wiring pattern and a mark provided on the wiring pattern by solder resist;mounting a semiconductor chip on the insulating substrate;recognizing a position of the insulating substrate by the mark and bonding a wire to the semiconductor chip;joining an electrode to the soldering portion by solder; andencapsulating the insulating substrate, the semiconductor chip, the wire, and the electrode in an encapsulation material.3. A method of manufacturing a semiconductor device comprising:forming a soldering portion on a wiring pattern of an insulating substrate;forming a protective film, which is formed of a solder resist and has a first opening disposed on the soldering portion and a second opening disposed on a ...

Packaged electronic device with split die pad in robust package substrate

In a described example, an apparatus includes a package substrate with a split die pad having a slot between a die mount portion and a wire bonding portion; a first end of the wire bonding portion coupled to the die mount portion at one end of the slot; a second end of the wire bonding portion coupled to a first lead on the package substrate. At least one semiconductor die is mounted on the die mount portion; a first end of a first wire bond is bonded to a first bond pad on the at least one semiconductor die; a second end of the first wire bond is bonded to the wire bonding portion; and mold compound covers the at least one semiconductor die, the die mount portion, the wire bonding portion, and fills the slot.

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device that includes an insulated circuit board having a conductive pattern, a first semiconductor chip with a rectangular shape connected through a first joining material to the conductive pattern, a second semiconductor chip with a rectangular shape disposed on the conductive pattern separated from the first semiconductor chip and connected through a second joining material to the conductive pattern, a terminal disposed above the semiconductor chips, respectively connected to the first and second semiconductor chips through third and fourth joining materials, the terminal having a through-hole above a place between the first and second semiconductor chips, the method including a positioning step in which the first and second semiconductor chips are respectively positioned at at least three positioning places, and at least one of the positioning places is positioned with a positioning member inserted into the through-hole. 1. A method of manufacturing a semiconductor device that comprises: an insulated circuit board having a conductive pattern; a first semiconductor chip with a rectangular shape connected through a first joining material to the conductive pattern; a second semiconductor chip with a rectangular shape disposed on the conductive pattern separated from the first semiconductor chip and connected through a second joining material to the conductive pattern; a terminal disposed above the first semiconductor chip and the second semiconductor chip , connected to the first semiconductor chip through a third joining material , and connected to the second semiconductor chip through a fourth joining material; the terminal having a through-hole above a place between the first semiconductor chip and the second semiconductor chip ,the method comprising a positioning step in whichthe first semiconductor chip is positioned at at least three positioning places,the second semiconductor chip is positioned at at least three ...

SEMICONDUCTOR MODULE PACKAGE AND METHOD OF MANUFACTURING THE SAME

There is provided a semiconductor module package including: a base substrate formed by mounting one or more first semiconductor devices thereon; a lead frame formed on a top surface of the first semiconductor device and having an inlet formed to inject a solder paste; and spaces inserted between the first semiconductor device and the lead frame to form a separation space, wherein the solder paste is filled in the separation space. 1. A semiconductor module package comprising:a base substrate formed by mounting one or more first semiconductor devices thereon;a lead frame formed on a top surface of the first semiconductor device and having an inlet formed to inject a solder paste; andspaces inserted between the first semiconductor device and the lead frame to form a separation space,wherein the solder paste is filled in the separation space.2. The semiconductor module package of claim 1 , wherein the lead frame includes:an inlet injecting the solder paste; anda through via formed in a lower end portion of the inlet and allowing the solder paste to flow out.3. The semiconductor module package of claim 2 , wherein the lead frame is formed by being bent to correspond to top surfaces of one or more of the first semiconductor devices and is formed so that a second semiconductor device is inserted into the inlet.4. The semiconductor module package of claim 2 , wherein the spaces are formed along an outer peripheral surface of the through via and are formed to have the same height.5. The semiconductor module package of claim 4 , wherein the space is made of a material having adhesion on both surfaces thereof.6. The semiconductor module package of claim 3 , wherein the space is formed to be removable.7. The semiconductor module package of claim 3 , wherein the space is formed integrally with the lead frame and has an adhesive formed on a lower end portion thereof.8. The semiconductor module package of claim 1 , wherein the lead frame and the space have an adjusting member ...

POWER SEMICONDUCTOR DEVICE

A power semiconductor device is provided. The power semiconductor device includes a leadframe, which includes a first chip carrier part and at least one second chip carrier part, which are fitted at a distance from one another and are in each case electrically conductive, at least one first power semiconductor component applied on the first chip carrier part, at least one second power semiconductor component applied on the second chip carrier part, external contacts in the form of external leads, and a capacitor. The capacitor is mounted on two adjacent external leads. 1. A power semiconductor device , comprising:a leadframe, which comprises a first chip carrier part and at least one second chip carrier part, which are fitted at a distance from one another and are in each case electrically conductive,at least one first power semiconductor component applied on the first chip carrier part,at least one second power semiconductor component applied on the second chip carrier part, external contacts in the form of external leads, anda capacitor,wherein the capacitor is mounted on two adjacent external leads.2. The power semiconductor device of claim 1 ,wherein the two adjacent external leads comprise soldering connections for connecting the capacitor.3. The power semiconductor device of claim 1 , further comprising:bonding wires configured to electrically connect contact areas on active top sides of the first power semiconductor component and of the second power semiconductor component and contact areas on the external leads.4. The power semiconductor device of claim 3 ,wherein the soldering connections differ from the contact areas on the external leads.5. The power semiconductor device of claim 1 ,wherein the external leads in each case comprise a first part, on which the contact areas are arranged and which lies in the same horizontal plane as the first chip carrier part and the second chip carrier part, a signal lead, which is oriented parallel to the first part and ...

Semiconductor packages with an intermetallic layer

A method of forming a semiconductor package. Implementations include forming on a die backside an intermediate metal layer having multiple sublayers, each including a metal selected from the group consisting of titanium, nickel, copper, silver, and combinations thereof. A tin layer is deposited onto the intermediate metal layer and is then reflowed with a silver layer of a substrate to form an intermetallic layer having a melting temperature above 260 degrees Celsius and including an intermetallic consisting of silver and tin and/or an intermetallic consisting of copper and tin. Another method of forming a semiconductor package includes forming a bump on each of a plurality of exposed pads of a top side of a die, each exposed pad surrounded by a passivation layer, each bump including an intermediate metal layer as described above and a tin layer coupled to the intermediate metal layer is reflowed to form an intermetallic layer.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE

A resin casing is insert-molded while clamp protrusions of clamp portions formed in bonding portions of lead terminals are put between an upper mold and a lower mold. An insulating substrate which has a wiring pattern mounted with semiconductor elements is fitted into an opening portion of the resin casing and adhesively bonded to the resin casing. Electric connection between the semiconductor elements and the bonding portions of the lead terminals and between the wiring pattern on the insulating substrate and the bonding portions of the lead terminals is made by bonding wires. Thus, it is possible to provide a method for manufacturing a semiconductor device and the semiconductor device, in which stress applied to lead terminals of a lead frame formed by insert molding can be suppressed, and wire bonding properties and reliability can be improved even when the thickness of each of the lead terminals is reduced. 1. A method for manufacturing a semiconductor device including a semiconductor element received in an annular resin casing which has an opening portion and which is molded integrally with lead terminals by insert molding using at least two molds , the method comprising:an insert molding step of placing clamp portions, which have clamp protrusions and which are formed in bonding portions of the lead terminals, on one of the molds to protrude the clamp portions into the opening portion, and insert-molding the resin casing while putting the clamp protrusions between the one mold and another mold;a substrate mounting step of fitting an insulating substrate, which has a wiring pattern mounted with the semiconductor element, into the opening portion of the insert-molded resin casing and adhesively bonding the insulating substrate and the resin casing to each other; anda wire bonding step of making electric connection between the semiconductor element and one of the bonding portions of the lead terminals and/or between the wiring pattern on the insulating substrate ...

BENDABLE AND STRETCHABLE ELECTRONIC DEVICES AND METHODS

Generally discussed herein are systems and methods that can include a stretchable and bendable device. According to an example a method can include (1) depositing a first elastomer material on a panel, (2) laminating trace material on the elastomer material, (3) processing the trace material to pattern the trace material into one or more traces and one or more bond pads, (4) attaching a die to the one or more bond pads, or (5) depositing a second elastomer material on and around the one or more traces, the bonds pads, and the die to encapsulate the one or more traces and the one or more bond pads in the first and second elastomer materials. 125.-. (canceled)26. A method of making a stretchable and bendable apparatus comprising:depositing a first elastomer material on a panel;laminating trace material on the elastomer material;processing the trace material to pattern the trace material into one or more traces and one or more bond pads;attaching a die to the one or more bond pads; anddepositing a second elastomer material on and around the one or more traces, the bonds pads, and the die to encapsulate the one or more traces and the one or more bond pads in the first and second elastomer materials.27. The method of claim 26 , wherein processing the trace material includes processing the trace material so as to form a trace with a thickness of less than about 500 nanometers.28. The method of claim 27 , further comprising:situating a first trace encapsulation material on the first elastomer material before laminating the trace material on the first elastomer material; andselectively removing portions of the first trace encapsulation material to pattern the first trace encapsulation material.29. The method of claim 28 , further comprising:situating a second trace encapsulation material on the one or more traces; andselectively removing portions of the second trace encapsulation material.30. The method of claim 26 , further comprising:releasing the first elastomer material ...

STRUCTURE AND METHOD FOR STABILIZING LEADS IN WIRE-BONDED SEMICONDUCTOR DEVICES

A semiconductor device having a leadframe including a pad () surrounded by elongated leads () spaced from the pad by a gap () and extending to a frame, the pad and the leads having a first thickness () and a first and an opposite and parallel second surface; the leads having a first portion () of first thickness near the gap and a second portion () of first thickness near the frame, and a zone () of reduced second thickness () between the first and second portions; the second surface (a) of the first lead portions is coplanar with the second surface (a) of the second portions. A semiconductor chip () with a terminal is attached the pad. A metallic wire connection () from the terminal to an adjacent lead includes a stitch bond () attached to the first surface of the lead. 1. A leadframe comprising:a metallic pad surrounded by a plurality of leads, each of the plurality of leads including a first surface and an opposite second surface, the first surface being adapted to connect a bond wire:wherein each of the plurality of leads including a first portion, a second portion and a third portion, wherein the first portion includes a first section with a first thickness and a second section with a second thickness, the second portion includes the second thickness, and the third portion includes the first thickness.2. The leadframe of claim 1 , wherein the metallic pad and the plurality of leads include a base metal selected from a group consisting of copper claim 1 , copper alloys claim 1 , aluminum claim 1 , aluminum alloys claim 1 , iron-nickel alloys claim 1 , and Kovar.3. The leadframe of claim 2 , wherein the first surface includes a layer of nickel plated on the base metal and a layer of palladium plated on the nickel layer claim 2 , and a layer of gold plated on the palladium layer.4. A semiconductor device comprising:a metallic pad; anda semiconductor chip, attached to the metallic pad, and electrically connected to a first surface of each of a plurality of leads, ...

Module Comprising a Semiconductor Chip

A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a material on the basis of Cu is attached to the first terminal contact surface, and a second bond element is attached to the second terminal contact surface. The second bond element is made of a material different from the material of the first bond element or is made of a type of bond element different from the type of the first bond element.

Semiconductor die package and method of assembling same

A semiconductor die package is assembled from a lead frame having lead fingers with a bonding end adjacent a die flag, and an elongate region extending away from the die flag. A semiconductor die is mounted on the die flag and electrodes of the semiconductor die are electrically connected to the bonding ends with bond wires. Each elongate region is bent into an external connector lead with mounting feet. The elongate region of each of the lead fingers protrudes from a housing formed from a mold compound. The mold compound extends from the housing to provide insulated support fingers molded to the external connector leads.

SYSTEMS AND METHODS FOR MULTIPLE BALL BOND STRUCTURES

A method for forming a semiconductor device includes forming a first ball bond on a first contact pad, in which the first ball bond has a first wire segment of a bonding wire extending from the ball bond; forming a mid-span ball in the first wire segment at a first distance from the ball bond; and after the forming the mid-span ball, attaching the mid-span ball to a second contact pad to form a second ball bond. 1. A method for forming a semiconductor device , the method comprising:forming a first ball bond on a first contact pad, the first ball bond having a first wire segment of a bonding wire extending from the ball bond;forming a mid-span ball in the first wire segment at a first distance from the ball bond; andafter the forming the mid-span ball, attaching the mid-span ball to a second contact pad to form a second ball bond.2. The method of claim 1 , wherein the forming the mid-span ball is performed while the first ball bond is attached to the first contact pad.3. The method of claim 1 , further comprising;detaching the bonding wire from the second ball bond;4. The method of claim 1 , wherein after the attaching the mid-span ball to the second contact pad claim 1 , a second wire segment of the bonding wire extends from the second ball bond.5. The method of claim 4 , further comprising:forming a second mid-span ball in the second wire segment at a second distance from the second ball bond; andattaching the second mid-span ball to a third contact pad.6. The method of claim 4 , further comprising:forming a stitch bond with the second wire segment to a third contact pad.7. The method of claim 1 , wherein the first contact pad is on a semiconductor die and the second contact pad is on a package substrate.8. The method of claim 1 , wherein the first contact pad is on a first semiconductor die and the second contact pad is on a second semiconductor die.9. The method of claim 1 , wherein the forming the mid-span ball comprises:using an electronic-flame-off (EFO) wand ...

SIGNAL ROUTING IN COMPLEX QUANTUM SYSTEMS

Embodiments of the present invention disclose a computer system having a plurality of quantum circuits arranged in a two-dimensional plane-like structure, the quantum circuits comprising qubits and busses (i.e., qubit-qubit interconnects), and a method of formation therefor. A quantum computer system comprises a plurality of quantum circuits arranged in a two-dimensional pattern. At least one interior quantum circuit, not along the perimeter of the two-dimensional plane of the plurality of quantum circuits, contains a bottom chip, a device layer, a top chip, and a routing layer. A signal wire connects the device layer to the routing layer, wherein the signal wire breaks the two dimensional plane, for example, the signal wire extends into a different plane. 1. A method comprising:forming a plurality of quantum circuits arranged in a two-dimensional layout, wherein the plurality of quantum circuits comprises at least one interior quantum circuit that is not along a perimeter of the two-dimensional layout, the at least one interior quantum circuit comprises a plurality of layers, wherein a top layer of the plurality of layers comprises a through hole to a bottom layer of the plurality of layers; andforming a signal wire at least partially within the through hole to connect the bottom layer to the top layer.2. The method of claim 1 , wherein the bottom layer of the plurality of layers comprises a bottom chip having a device layer and the top layer of the plurality of layers comprises a top chip having a routing layer; andwherein the signal wire communicatively connects the device layer of the bottom chip to the routing layer of the top chip, and wherein the signal wire is not parallel to a plane of the two dimensional layout.3. The method of claim 1 , wherein the through hole is formed by reactive ion etching or by laser milling.4. The method of claim 1 , wherein the through hole has a diameter less than or equal to 1000 μm.5. The method of claim 2 , wherein the at ...

FABRICATION METHOD OF SEMICONDUCTOR DEVICE, EVALUATION METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

A fabrication method of a semiconductor device that includes trench gate structures each having a gate electrode extending in a depth-direction of an element, where first trench gate structures contribute to controlling the element and second trench gate structures do not contribute. The fabrication method includes forming the trench gate structures on a front face of a semiconductor substrate; forming on the front face, an electrode pad connected to the gate electrode of at least one trench gate structure; executing screening by applying a predetermined voltage between the electrode pad and an electrode portion having a potential other than a gate potential, to apply the predetermined voltage to gate insulator films in contact with each gate electrode connected to the electrode pad; and forming the second trench gate structures having the gate electrodes connected to the electrode pad, by short-circuiting the electrode portion to the electrode pad after executing screening. 1. A fabrication method of a semiconductor device that includes a plurality of trench gate structures each having a gate electrode extending in a depth direction of an element , the plurality of trench gate structures including first trench gate structures respectively contributing to control of the element and second trench gate structures respectively not contributing to the control of the element , the fabrication method of a semiconductor device comprising:forming the plurality of trench gate structures on a front face of a semiconductor substrate;forming on the front face of the semiconductor substrate, an electrode pad connected to the gate electrode of at least one of the trench gate structures among the plurality of trench gate structures;executing screening by applying a predetermined voltage between the electrode pad and an electrode portion having a potential other than a gate potential, to apply the predetermined voltage to gate insulator films in contact with each gate electrode ...

Electronic module comprising fluid cooling channel and method of manufacturing the same

Various embodiments provide an electronic module comprising a interposer comprising a fluid channel formed in an electrically isolating material and an electrically conductive structured layer; at least one electronic chip attached to the electrically conductive layer and in thermal contact to the fluid channel; and a molded encapsulation formed at least partially around the at least one electronic chip, wherein the electrically conductive structured layer is directly formed on the electrically isolating material. 1. An electronic module comprising:an interposer comprising a fluid channel formed in an electrically isolating material and an electrically conductive structured layer;at least one electronic chip attached to the electrically conductive layer and in thermal contact to the fluid channel; anda molded encapsulation formed at least partially around the at least one electronic chip,wherein the electrically conductive structured layer is directly formed on the electrically isolating material.2. The electronic module according to claim 1 , wherein the interposer comprises a ceramic material.3. The electronic module according to claim 2 , wherein the ceramic material is sintered.4. The electronic module according to claim 2 , wherein the electrically conductive structured layer comprises a metal and is sintered together with the ceramic material.5. The electronic module according to claim 1 , further comprising a further electronic chip claim 1 , wherein the at least one electronic chip is arranged on a first main surface of the interposer and the further electronic chip is arranged on a second main surface of the interposer.6. The electronic module according to claim 1 , wherein the at least one electronic chip is attached to the electrically conductive structure layer by a sintering process.7. The electronic module according to claim 1 , further comprising an external electrical contact connected to the electrically conductive structured layer and being ...

SEMICONDUCTOR DEVICE WITH STEP PORTION HAVING SHEAR SURFACES

A semiconductor device includes a source electrode pad formed to a front surface of a semiconductor chip and a metal clip (metal plate) to which a lead is electrically connected. The metal clip includes a chip-connecting portion electrically connected to the source electrode pad via a conductive bonding material, a lead-connecting portion electrically connected to the lead via a conductive bonding material, and an intermediate portion positioned between the chip-connecting portion and the lead-connecting portion. Further, between the intermediate portion and the chip-connecting portion, a step portion, which has shear surfaces disposed to face each other, is provided interposing a joining portion. 1. A method of manufacturing a semiconductor device comprising the steps of:(a) preparing a lead frame including a chip-mounting portion having a chip-mounting surface, a first lead disposed to be separated from the chip-mounting portion, a second lead disposed to separate the chip-mounting portion and the first lead;(b) mounting a semiconductor chip having a front surface to which a first electrode and a second electrode are formed and a back surface to which a third electrode is formed and positioned on the opposite to the front surface to the chip-mounting portion via a first conductive bonding material;(c) electrically connecting the second electrode and the second lead via a metal plate having a chip-connecting portion, a lead-connecting portion, and an intermediate portion positioned between the chip-connecting portion and the lead-connecting portion;(d) electrically connecting the first electrode and the first lead via a wire; and(e) sealing the semiconductor chip, the metal plate, and the wire by a resin such that the first lead, the second lead, and the chip-mounting portion are partly exposed, in a plan view, the chip-mounting portion, the intermediate portion, and the lead-connecting portion disposed in this order from the second electrode of the semiconductor ...

METHODS FOR CONNECTING INTER-LAYER CONDUCTORS AND COMPONENTS IN 3D STRUCTURES

Systems and methods for creating interlayer mechanical or electrical attachments or connections using filaments within a three-dimensional structure, structural component, or structural electronic, electromagnetic, or electromechanical component/device. 1. A method for connecting inter-layer conductors and components in a 3D structure , said method comprising:providing a layer of a substrate material of a 3D structure; andembedding a portion of a filament within said layer of said substrate material wherein a portion of said substrate material in a flowable state is displaced by said portion of said filament and does not substantially protrude above a top surface of said layer.2. The method of wherein said portion of said filament is substantially flush with said top surface of said layer.3. The method of wherein said substrate material of said 3D structure comprises a polymer or a composite structure and wherein said substrate material is rendered with a 3D printer.4. The method of wherein said portion of said filament is embedded with a thermal wire embedding technique or a non-thermal embedding technique.5. The method of further comprising configuring an inter-layer connection between said layer and another layer in an additive manufacturing process.6. The method of wherein inter-layer connection is configured in a shape of a hole.7. The method of wherein said hole is configured in a shape of a keyhole that permits a wire to be grabbed from a lower level and brought to a next layer to provide said inter-layer connection.8. The method of wherein said inter-layer connection is formed in a shape of a spiral that allows a longer piece of wire to be pulled out to achieve a via and a second layer wire capable of being embedded at a higher level.9. The method of further comprising configuring a wire at said layer that is exposed by a hole sufficiently large to push a second wire on a next level down to be connected together by a joining method or allowed to make contact ...

METHODS OF MANUFACTURING AND OPERATING DIE-TO-DIE INDUCTIVE COMMUNICATION DEVICES

Embodiments of inductive communication devices include first and second IC die and an inductive coupling substrate. The first IC die has a first coil. The inductive coupling substrate has a second coil and a first signal communication interface (e.g., a third coil or a contact). The second IC die has a second signal communication interface (e.g., a fourth coil or a contact). The first IC die and the inductive coupling substrate are arranged so that the first and second coils are aligned across a gap between the first IC die and the inductive coupling substrate. A dielectric component is positioned within the gap between the first and second coils to galvanically isolate the first IC die and the inductive coupling substrate. During operation, signals are conveyed between the first and second IC die through inductive coupling between the coils and communication through the signal communication interfaces.

SEMICONDUCTOR DEVICE WITH ENCAPSULATED LEAD FRAME CONTACT AREA AND RELATED METHODS

A semiconductor device may include an IC, and lead frame contact areas adjacent the IC. Each lead frame contact area may have a lead opening. The semiconductor device may include bond wires, each bond wire coupling a respective lead frame contact area with the IC. The semiconductor device may include encapsulation material surrounding the IC, the lead frame contact areas, and the bond wires, and leads. Each lead may extend through a respective lead opening and outwardly from the encapsulation material. 1. A semiconductor device comprising:at least one integrated circuit (IC);a plurality of lead frame contact areas adjacent said at least one IC, each lead frame contact area having a lead opening therein;a plurality of bond wires, each bond wire coupling a respective lead frame contact area with said at least one IC;encapsulation material surrounding said at least one IC, said plurality of lead frame contact areas, and said plurality of bond wires; anda plurality of leads, each lead extending through a respective lead opening and outwardly from said encapsulation material.2. The semiconductor device of further comprising a plurality of solder joints claim 1 , each solder joint attaching a respective lead within a corresponding lead opening.3. The semiconductor device of wherein each of said lead openings comprises a lead through-opening extending through a corresponding lead frame contact area; and wherein each of said solder joints fills a corresponding lead through-opening.4. The semiconductor device of wherein each of said solder joints is laterally spaced outwardly from a respective bond wire.5. The semiconductor device of wherein each of said solder joints has a ball shape.6. The semiconductor device of further comprising at least one IC die pad below said at least one IC.7. The semiconductor device of further comprising an adhesive layer between said at least one IC and said at least one IC die pad.8. The semiconductor device of wherein each lead frame contact ...

FLIP CHIP ASSEMBLY AND PROCESS WITH SINTERING MATERIAL ON METAL BUMPS

A method is disclosed of fabricating a microelectronic package comprising a substrate overlying the front face of a microelectronic element. A plurality of metal bumps project from conductive elements of the substrate towards the microelectronic element, the metal bumps having first ends extending from the conductive elements, second ends remote from the conductive elements, and lateral surfaces extending between the first and second ends. The metal bumps can be wire bonds having first and second ends attached to a same conductive pad of the substrate. A conductive matrix material contacts at least portions of the lateral surfaces of respective ones of the metal bumps and joins the metal bumps with contacts of the microelectronic element. 1. (canceled)2. (canceled)3. A method of fabricating an interconnection element , comprising:applying a conductive matrix material to respective lateral surfaces of wire bonds projecting above conductive pads of a substrate, the lateral surface of each wire bond extending between first and second opposite ends of each wire bond, the first and second ends attached directly to a conductive pad of the plurality of conductive pads at first and second attachment locations spaced apart from one another, the conductive matrix material comprising a mixture of metals having substantially different melting-points and a non-metallic material,wherein the wire bonds projecting above the conductive pads of the substrate with the conductive matrix material thereon are configured to be joined with respective contacts of an external component by sintering the conductive matrix material to form joints of the sintered conductive matrix material which have an open cell foam-like structure interspersed with at least one of a polymer or voids.4. The method as claimed in claim 3 , wherein the conductive matrix material is applied to the wire bonds so as to extend within at least one opening of the substrate.5. The method as claimed in claim 3 , wherein ...

COATED WIRE FOR BONDING APPLICATIONS

The invention is related to a bonding wire which contains a core having a surface and a coating layer which is at least partially superimposed over the surface of the core. The core contains a core main component selected from copper and silver. The coating layer contains a coating component selected from palladium, platinum, gold, rhodium, ruthenium, osmium and iridium in an amount of at least 10% and further contains the core main component in an amount of at least 10%. 121.-. (canceled)22. A bonding wire comprising a core having a surface and a coating layer which is at least partially superimposed over the surface of the core , wherein the core comprises a core main component selected from the group consisting of copper and silver; and wherein the coating layer comprises a coating component selected from the group consisting of palladium , platinum , gold , rhodium , ruthenium , osmium and iridium in an amount of at least 10% and further comprises the core main component in an amount of at least 10%.23. The wire according to claim 22 , wherein an outer range of the coating layer extends from a depth of 0.1% of a wire diameter to a depth of 0.25% of the wire diameter claim 22 , and wherein the amount of the core main component and the amount of the coating component are present in the outer range.24. The wire according to claim 23 , wherein the amount of the core main component in the outer range is between 30% and 70%.25. The wire according to claim 23 , wherein the amount of the coating component decreases within the outer range toward an inside of the wire.26. The wire according to claim 25 , wherein a difference of the amount of the coating component at a radially inner border of the outer range and the amount of the coating component at a radially outer border of the outer range is not more than 30%.27. The wire according to claim 22 , wherein a main component of the wire changes at least two times starting from an outside of the wire up to a depth of 0.25% ...

METHOD FOR JOINING A MICORELECTRONIC CHIP TO A WIRE ELEMENT

A method for joining a microelectronic chip to at least one wire element comprises: a first step of applying a cover to a first face of the microelectronic chip, the cover being configured to form, with the first face, at least one temporary side groove; a step of inserting the wire element into the temporary groove; a step of attaching the wire element to the microelectronic chip; and a step of removing the cover from the microelectronic chip. 1. A method of assembling a microelectronic chip on at least one wire element , comprising:applying a cover to a first face of the microelectronic chip, the cover being configured to form, with the first face, at least one temporary lateral groove;inserting the at least one wire element into the temporary groove;fixing the at least one wire element to the microelectronic chip; andremoving the cover from the microelectronic chip.2. The method of claim 1 , wherein the cover has a contact face and at least one shoulder claim 1 , the method further comprising applying the contact face to the first face of the microelectronic chip to form the temporary lateral groove with the first face.3. The method of claim 3 , wherein the first face of the microelectronic chip has at least one shoulder to form the temporary lateral groove with a contact face of the cover.4. The method of claim 3 , wherein applying the cover to the first face of the microelectronic chip comprises maintaining contact between the contact face of the cover and the first face by vacuum.5. The method of claim 4 , wherein inserting the at least one wire element into the temporary groove comprises inserting a longitudinal portion of the at least one wire element at least partially into the temporary lateral groove.6. The method of claim 5 , further comprising applying a holder to a second face of the microelectronic chip at least while inserting the at least one wire element into the temporary groove.7. The method of claim 6 , further comprising providing at least one ...

SURFACE FINISH FOR WIREBONDING

The present disclosure provides embodiments of package devices and methods for making package devices for a semiconductor die. One embodiment includes a die mounting structure having a finished bond pad that includes a copper bond pad and a cobalt-containing layer over a top surface of the copper bond pad, and a wire bond structure that is bonded to a top surface of the cobalt-containing layer of the finished bond pad, where cobalt-containing material of the cobalt-containing layer is located between a bottom surface of the wire bond structure and the top surface of the copper bond pad such that the cobalt-containing material is present under a center portion of the wire bond structure. 1. A package device for a semiconductor die comprising:a package substrate having a finished bond pad that comprises a copper bond pad and a cobalt-containing layer over a top surface of the copper bond pad; and 'cobalt-containing material of the cobalt-containing layer is located between a bottom surface of the wire bond structure and the top surface of the copper bond pad such that the cobalt-containing material is present under a center portion of the wire bond structure.', 'a wire bond structure bonded to a top surface of the cobalt-containing layer of the finished bond pad, wherein'}2. The package device of claim 1 , further comprising:a finished ball pad on the package substrate, the finished ball pad comprising a copper ball pad and the cobalt-containing layer over a top surface of the copper ball pad; anda solder ball bonded to a top surface of the cobalt-containing layer of the finished ball pad for a ball grid array (BGA) connection.3. The package device of claim 1 , wherein the package substrate comprises at least one of a ceramic substrate claim 1 , an organic substrate claim 1 , an epoxy substrate claim 1 , an FR-4 substrate claim 1 , an FR-5 substrate claim 1 , a BT substrate claim 1 , and polyimide substrate.4. The package device of claim 1 , wherein the wire bond ...

Method for inserting a wire into a groove of a semiconductor chip, and piece of equipment for implementing such a method

A method for inserting a wire into a longitudinal groove of a semiconductor chip for the assembly thereof, the groove containing a pad made of a bonding material having a set melting point, the method comprises: in a positioning step, placing a longitudinal section of the wire along the groove, in forced abutment against the pad; and, in an insertion step, exposing a zone containing at least one portion of the pad to a processing temperature higher than the melting point of the bonding material and for a sufficient time to make the pad at least partially melt, and causing the wire to be inserted into the groove. The present disclosure also relates to a piece of equipment allowing the insertion method to be implemented.

Semiconductor package with a cavity in a die pad for reducing voids in the solder

A semiconductor package having an aperture in a die pad and solder in the aperture coplanar with a surface of the package is disclosed. The package includes a die pad, a plurality of leads, and a semiconductor die coupled to the die pad with a die attach material. A cavity or aperture is formed through the die pad to expose a portion of the die attach material. Multiple solder reflows are performed to reduce the presence of voids in the die attach material. In a first solder reflow, the voids of trapped gas that form when attaching the die to the die pad are released. Then, in a second solder reflow, solder is added to the aperture coplanar with a surface of the die pad. The additional solder can be the same material as the die attach material or a different material.

Apparatus, system, and method for wireless connection in integrated circuit packages

Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.

Procédé d'assemblage d'une puce microélectronique sur un élement filaire

L'invention concerne un procédé d'assemblage d'une puce microélectronique (1) sur au moins un élément filaire (7a, 7b). Le procédé d'assemblage comprend : • Une première étape d'application d'un capot (5) sur une première face de la puce microélectronique (1), le capot 10 (5) étant configuré pour former avec la première face (11) au moins une rainure temporaire latérale; • Une étape d'insertion de l'élément filaire (7a,7b) dans la rainure temporaire; • Une étape de fixation de l'élément filaire (7a,7b) 15 sur la puce microélectronique (1); • Une étape de retrait du capot (5) de la puce microélectronique (1).

Discrete flexible interconnects for modules of integrated circuits

Flexible interconnects, flexible integrated circuit systems and devices, and methods of making and using flexible integrated circuitry are presented herein. A flexible integrated circuit system is disclosed which includes first and second discrete devices that are electrically connected by a discrete flexible interconnect. The first discrete devices includes a first flexible multi-layer integrated circuit (IC) package with a first electrical connection pad on an outer surface thereof. The second discrete device includes a second flexible multi-layer integrated circuit (IC) package with a second electrical connection pad on an outer surface thereof. The discrete flexible interconnect is attached to and electrically connects the first electrical connection pad of the first discrete device to the second electrical connection pad of the second discrete device.

A semiconductor packages and manufacturing method for it

본 발명은 반도체패키지와 그 제조방법에 관한 것이다. The present invention relates to a semiconductor package and a method of manufacturing the same. 종래의 CSP 기술은 낱개로 절단 가공된 반도체칩에 회로기판을 부착하는 기술을 통해 거의 칩과 같은 크기로 반도체패키지를 제조할 수는 있지만, 초소형 크기의 낱개로 절단된 반도체칩(1)에 회로기판(2)을 붙이고 볼(3)을 부착해야 하는 등 그 제조공정이 복잡하고 정밀성이 요구되는 제조상의 문제점을 안고 있었다. In the conventional CSP technology, a semiconductor package can be manufactured in almost the same size as a chip through a technique of attaching a circuit board to a single cut semiconductor chip, but a circuit is formed in a single cut semiconductor chip 1 having a small size. The manufacturing process is complicated and the precision is required, such as attaching the board | substrate 2 and attaching the ball 3, and the like. 본 발명에서는 상기와 같은 종래의 갖는 제반문제점을 해결하기 위하여 반도체칩(10)과 그 크기가 완전히 동일한 CSP 반도체패키지를 제공하고, 나아가 CSP 반도체패키지의 제조공정을 단순화하여 제조원가를 절감할 수 있도록 한 것이다. The present invention provides a CSP semiconductor package that is exactly the same size as the semiconductor chip 10 in order to solve the above conventional problems, and further simplify the manufacturing process of the CSP semiconductor package to reduce the manufacturing cost will be.

半导体器件及其制造方法

半导体器件及其制造方法，提高半导体器件的可靠性。在引线框架(LF)设有一对悬吊部(HL)，并且夹具(CLP)由主体部(BDU)和一对延伸部(EXU)构成，以此为前提，一对延伸部(EXU)搭载于一对悬吊部(HL)上而被支承。由此，夹具(CLP)被搭载于引线(LD1)上(1点)和一对悬吊部(HL)上(2点)，夹具(CLP)被这些部件3点支承。

Semiconductor device and method of manufacturing the same

본 발명은, 반도체 장치의 신뢰성을 향상시키는 것을 과제로 한다. 리드 프레임 LF에 한 쌍의 현수부 HL이 설치되며, 또한 클립 CLP가 본체부 BDU와 한 쌍의 연장부 EXU로 구성되어 있는 것을 전제로 하여, 한 쌍의 연장부 EXU가 한 쌍의 현수부 HL 위에 탑재되고 지지되어 있는 점에 있다. 이에 의해, 클립 CLP는, 리드 LD1 위(1점)와 한 쌍의 현수부 HL 위(2점)에 탑재됨으로써, 클립 CLP는, 이 3점에 의해 지지되어 있게 된다.

Wire bonding apparatus and method for producing semiconductor device

打线装置(10)具备：毛细管(28)，其供导线(30)通插；未连判断电路(36)，其向接合对象物与处于夹紧状态的导线(30)之间施加既定的电信号，且依据其的回应来判断接合对象物与导线(30)之间的未连及导线(30)是否切断；圆环状的突出长度检测环40，其与毛细管(28)同轴地配置；及突出长度判断电路(38)，其根据向突出长度检测环(40)与导线(30)之间施加既定的检查电压时的导通的有无的检测以及向其间施加既定的检查高电压时的放电火花的有无的检测，来判断自毛细管(28)之前端突出的导线尾部的突出长度是否适当。

Wire bonding apparatus and method for producing semiconductor device

와이어 본딩 장치(10)는 와이어(30)를 삽입통과시키는 캐필러리(28)와, 본딩 대상물과 클램프 상태의 와이어(30) 사이에 소정의 전기 신호를 인가하고, 그 응답 에 기초하여 본딩 대상물과 와이어(30) 사이의 불착과 와이어(30)가 절단된 것인지 아닌지를 판정하는 불착 판정 회로(36)와, 캐필러리(28)와 동축에 배치되는 둥근 고리 형상의 돌출길이 검출 링(40)과, 돌출길이 검출 링(40)과 와이어(30) 사이에 소정의 검사 전압을 인가했을 때의 도통의 유무의 검출 및 그 사이에 소정의 검사 고전압을 인가 했을 때의 방전 스파크의 유무의 검출에 기초하여, 캐필러리(28)의 선단으로부터 돌출하는 와이어 테일의 돌출길이의 적절/부적절을 판정하는 돌출길이 판정 회로(38)를 구비한다. The wire bonding apparatus 10 includes a capillary 28 for inserting the wire 30 and a wire 30 for applying a predetermined electric signal between the object to be bonded and the clamped wire 30, A determination circuit 36 for determining whether or not the wire 30 is disconnected from the wire 30 and whether or not the wire 30 has been cut off, and a rounded protruding length detection ring 40 The detection of the presence or absence of conduction when a predetermined inspection voltage is applied between the protruding length detecting ring 40 and the wire 30 and the detection of the presence or absence of a discharge spark when a predetermined inspection high voltage is applied therebetween And a protrusion length determination circuit 38 that determines the proper / improper length of the protrusion of the wire tail protruding from the tip end of the capillary 28. [

Flexibly wrapped crystal of integrated circuit

Использование: для создания интегральной схемы. Сущность изобретения заключается в том, что устройство на основе гибко оборачиваемого кристалла интегральной схемы содержит подложку и гибкий кристалл интегральной схемы, соединенный с подложкой по существу в вертикальной ориентации относительно поверхности подложки. Технический результат: обеспечение возможности улучшенного теплоотведения и сохранения компактности. 4 н. и 21 з.п. ф-лы, 8 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 2 642 170 C2 (51) МПК H01L 23/12 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ (52) СПК H01L 23/12 (2006.01) (21)(22) Заявка: 2016119458, 19.12.2013 (24) Дата начала отсчета срока действия патента: Дата регистрации: 24.01.2018 (73) Патентообладатель(и): ИНТЕЛ КОРПОРЕЙШН (US) (43) Дата публикации заявки: 23.11.2017 Бюл. № 33 (56) Список документов, цитированных в отчете о поиске: US 20110057284 A1, 10.03.2011. US (45) Опубликовано: 24.01.2018 Бюл. № 3 2011281407 A1, 17.11.2011. US 2010112774 A1, 06.05.2010. JP 2001284564 A, 12.10.2001. (85) Дата начала рассмотрения заявки PCT на национальной фазе: 19.05.2016 (86) Заявка PCT: 2 6 4 2 1 7 0 Приоритет(ы): (22) Дата подачи заявки: 19.12.2013 R U 19.12.2013 (72) Автор(ы): АЛЬБЕРС Свен (DE), СКИННЕР Майкл (US), БАРТ Ганс-Йоахим (DE), БАУМГАРТНЕР Петер (DE), ГОСНЕР Харальд (DE) WO 2015/094259 (25.06.2015) Адрес для переписки: 109012, Москва, ул. Ильинка, 5/2, ООО "Союзпатент" (54) ГИБКО ОБОРАЧИВАЕМЫЙ КРИСТАЛЛ ИНТЕГРАЛЬНОЙ СХЕМЫ (57) Реферат: Использование: для создания интегральной вертикальной ориентации относительно схемы. Сущность изобретения заключается в том, поверхности подложки. Технический результат: что устройство на основе гибко оборачиваемого обеспечение возможности улучшенного кристалла интегральной схемы содержит теплоотведения и сохранения компактности. 4 н. подложку и гибкий кристалл интегральной схемы, и 21 з.п. ф-лы, 8 ил. соединенный с подложкой по существу в R U 2 6 4 2 1 7 0 (87 ...

Method for manufacturing antenna part

本发明提供一种天线元件的制造方法，该制造方法简单且造价低廉。具体而言，天线元件(10)是经过下述工序将线圈部件(11)和半导体基板(12)相连接而制成，即，在线圈部件(11)的连接端部(11a)与焊料层(14)相接触的状态下，相对于半导体基板(12)对线圈部件(11)进行布线的工序；通过对焊料层(14)加热使其熔化，能够将连接端部(11a)的一部分插入焊料层(14)，继而通过焊料层(14)将焊盘(12a)与线圈部件(11)电性连接的工序。

Component or bond connection unit fixing method for use in circuit arrangement e.g. semiconductor arrangement, involves applying force on contact surface, such that component or connection units is fixed to surface with reaction forces

The method involves positioning a component (7) or bond connection units (3, 4) on a contact surface (2) by using a positioning unit e.g. capillary, where the contact surface is formed by a layer with a reactive material embedded between two soldering layers. A force is applied on the contact surface in such a manner that the reactive material e.g. aluminum, nickel or magnesium, in the layer of the contact surface is ignited and the component or the connection units is fixed to the contact surface with reaction forces produced by the ignition. An independent claim is also included for a circuit arrangement comprising a substrate and a component.

Method for producing semiconductor chips and method for producing a via in a semiconductor substrate

Verfahren zum Herstellen von Halbleiterchips, wobei das Verfahren umfasst: Bereitstellen eines Halbleiter-Wafers; Ausbilden einer Metallschicht auf dem Halbleiter-Wafer durch Plasmaabscheidung von bereits hergestellten Metallpartikeln auf dem Halbleiter-Wafer, wobei die Metallpartikel aus Kupfer und/oder Aluminium hergestellte Kerne und die Kerne umgebende Schalen umfassen, wobei die Schalen aus Silber, Gold, Palladium, Titan, Tantal und/oder Niob hergestellt sind; und Zersägen des Halbleiter-Wafers, wodurch die Halbleiterchips getrennt werden. A method of manufacturing semiconductor chips, the method comprising: Providing a semiconductor wafer; Forming a metal layer on the semiconductor wafer by plasma deposition of already produced metal particles on the semiconductor wafer, the metal particles comprising cores made of copper and / or aluminum and shells surrounding the cores, the shells of silver, gold, palladium, titanium, Tantalum and / or niobium are made; and Sawing the semiconductor wafer, thereby separating the semiconductor chips.

Manufacturing method of semiconductor module

本発明は、低温かつ短時間の接合を可能とし、また、はんだ接合媒体を用いることなく接合を行うことにより、より信頼性の高い接合部を得ることが可能な、半導体モジュールの製造方法を提供する。 回路基板上の第１回路電極と、半導体素子の裏面側素子電極とを接合する第１接合工程と、前記半導体素子の表面側素子電極と、リードフレームの一端とを接合する第２接合工程と、前記リードフレームの他端と、回路基板上に形成された第２回路電極とを接合する第３接合工程とを含み、接続されるべき１対の導電部の一方に、低融点金属層を形成した後に加熱加圧し、前記低融点金属層を前記１対の導電部中に固液拡散させることによって、導電部を接合する。 The present invention provides a method for manufacturing a semiconductor module that enables low-temperature and short-time bonding, and that a bonding portion with higher reliability can be obtained by bonding without using a solder bonding medium. To do. A first joining step for joining the first circuit electrode on the circuit board and the back-side element electrode of the semiconductor element; a second joining step for joining the top-side element electrode of the semiconductor element and one end of the lead frame; A third joining step for joining the other end of the lead frame and a second circuit electrode formed on the circuit board, and a low melting point metal layer is formed on one of the pair of conductive parts to be connected. After the formation, the conductive parts are joined by heating and pressurizing and solid-liquid diffusion of the low melting point metal layer into the pair of conductive parts.