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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 2386. Отображено 100.
02-02-2012 дата публикации

Method and electrostatic transfer stamp for transferring semiconductor dice using electrostatic transfer printing techniques

Номер: US20120027557A1
Автор: Ian Ashdown, Ingo Speier
Принадлежит: Cooledge Lighting Inc

A transfer stamp that can be charged with a spatial pattern of electrostatic charge for picking up selected semiconductor dice from a host substrate and transferring them to a target substrate. The stamp may be bulk charged and then selectively discharged using irradiation through a patterned mask. The technique may also be used to electrostatically transfer selected semiconductor dice from a host substrate to a target substrate.

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Номер записи: 1
25-10-2012 дата публикации

Method for disposing a component

Номер: US20120269971A1
Автор: Hidekazu Arase
Принадлежит: Panasonic Corp

Provided is a method for disposing a component on a substrate ( 100 ), the method comprising steps of: a step (a) of preparing the substrate ( 100 ), a first liquid, and a component-dispersing liquid; a step (b) of applying the first liquid to the substrate ( 100 ) along the +X direction continuously to dispose the first liquid on hydrophilic lines ( 112 ) and hydrophilic body regions ( 111 ) along the +X direction alternately; a step (c) of bringing the component-dispersing liquid in contact with the first liquid disposed on the hydrophilic region ( 111 ); and a step (d) of removing the first liquid and the second liquid from the substrate ( 100 ) to dispose the component on the hydrophilic region ( 111 ).

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Номер записи: 2
25-04-2013 дата публикации

Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die

Номер: US20130099378A1
Автор: HanGil Shin, HeeJo Chi, NamJu Cho
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

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Номер записи: 3
02-05-2013 дата публикации

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

Номер: US20130105989A1
Автор: Reza A. Pagaila, Seng Guan Chow, Seung Uk Yoon
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

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Номер записи: 4
06-06-2013 дата публикации

Packaging Process Tools and Systems, and Packaging Methods for Semiconductor Devices

Номер: US20130143361A1
Автор: Chih-Wei Lin, Chun-Cheng Lin, Chung-Shi Liu, Kuei-Wei Huang, Ming-Da Cheng, Wei-Hung Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.

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Номер записи: 5
27-06-2013 дата публикации

Light Emitting Diode (LED) Using Three-Dimensional Gallium Nitride (GaN) Pillar Structures with Planar Surfaces

Номер: US20130161584A1
Автор: Changqing Zhan, Mark Albert Crowder, Paul J. Schuele
Принадлежит: Individual

A method is provided for fabricating a light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. The method forms a plurality of GaN pillar structures, each with an n-doped GaN (n-GaN) pillar and planar sidewalls perpendicular to the c-plane, formed in either an m-plane or a-plane family. A multiple quantum well (MQW) layer is formed overlying the n-GaN pillar sidewalls, and a layer of p-doped GaN (p-GaN) is formed overlying the MQW layer. The plurality of GaN pillar structures are deposited on a first substrate, with the n-doped GaN pillar sidewalls aligned parallel to a top surface of the first substrate. A first end of each GaN pillar structure is connected to a first metal layer. The second end of each GaN pillar structure is etched to expose the n-GaN pillar second end and connected to a second metal layer.

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Номер записи: 6
10-10-2013 дата публикации

Semiconductor Package and Method of Manufacturing the Same

Номер: US20130264706A1
Автор: Dong-Hyeon Jang, Ho-geon Song, Sung-Jun IM, Teak-Hoon LEE, Won-Keun Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the first cutting groove; and forming a second cutting groove having a second kerf width that is less than the first kerf width, in the molding layer, so as to separate the molding layer into individual molding layers covering one of the plurality of first semiconductor chips and corresponding one of the plurality of second semiconductor chips.

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Номер записи: 7
27-03-2014 дата публикации

Package process and package structure

Номер: US20140087519A1
Автор: Chi-Chih Shen, Jen-Chuan Chen, Tommy Pan
Принадлежит: Advanced Semiconductor Engineering Inc

A package process is provided. An adhesive layer is disposed on a carrier board and then plural first semiconductor devices are disposed on the adhesive layer. A first molding compound formed on the carrier board covers the sidewalls of the first semiconductor devices and fills the gaps between the first semiconductor devices so as to form a chip array board constructed by the first semiconductor devices and the first molding compound. Next, plural second semiconductor devices are flip-chip bonded to the first semiconductor devices respectively. Then, a second molding compound formed on the chip array board at least covers the sidewalls of the second semiconductor devices and fills the gaps between the second semiconductor devices. Subsequently, the chip array board is separated from the adhesive layer. Then, the first and the second molding compound are cut along the gaps between the second semiconductor devices.

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Номер записи: 8
04-01-2018 дата публикации

Apparatus and methods for micro-transfer-printing

Номер: US20180001614A1
Автор: Christopher Bower, David Gomez, David Kneeburg, Matthew Meitl, Salvatore Bonafede
Принадлежит: X Celeprint Ltd

In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed.

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Номер записи: 9
13-01-2022 дата публикации

Wet alignment method for micro-semiconductor chip and display transfer structure

Номер: US20220013400A1
Автор: Junsik Hwang, Kyungwook Hwang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A wet alignment method for a micro-semiconductor chip and a display transfer structure are provided. The wet alignment method for a micro-semiconductor chip includes: supplying a liquid to a transfer substrate including a plurality of grooves; supplying the micro-semiconductor chip onto the transfer substrate; scanning the transfer substrate by using an absorber capable of absorbing the liquid. According to the wet alignment method, the micro-semiconductor chip may be transferred onto a large area.

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Номер записи: 10
04-01-2018 дата публикации

SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF

Номер: US20180005987A1
Автор: Hiner David, Huemoeller Ronald, KELLY MICHAEL
Принадлежит:

A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a connect die that routes electrical signals between a plurality of other semiconductor die. 1. A method of making an electronic device , the method comprising:receiving a first portion of a signal redistribution structure;forming a first functional die interconnection structure on the signal redistribution structure;forming a second functional die interconnection structure on the signal redistribution structure;coupling a back side of a connect die to the signal redistribution structure, the connect die comprising a first connect die interconnection structure coupled to a front side of the connect die and a second connect die interconnection structure coupled to the front side of the connect die;coupling a first interconnection structure of a first functional die to the first functional die interconnection structure; andcoupling a second interconnection structure of the first functional die to the first connect die interconnection structure.2. The method of claim 1 , wherein:said receiving the first portion of the signal redistribution structure comprises receiving the first portion of the signal distribution structure on a carrier; andthe method further comprises removing the carrier.3. The method of claim 1 , comprising:coupling a third interconnection structure of a second functional die to the second functional die interconnection structure; andcoupling a fourth interconnection structure of the second functional die to the second connect die interconnection structure.4. The method of claim 2 , comprising after said removing the carrier claim 2 , adding at least one dielectric layer and at least one conductive layer to the signal redistribution structure.5. The method of claim 1 , comprising before said coupling the first and ...

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Номер записи: 11
07-01-2021 дата публикации

CHIP FRONT SURFACE TOUCHLESS FLIP CHIP BONDERS

Номер: US20210005572A1
Автор: Li Dong, Liu Zongrong, Ma Ying, Yi Ge
Принадлежит:

A piece of chip-to-wafer and chip-to-chip bonding equipment, which has innovative designs enabling chip(s) from either a diamagnetic carrier or a diced wafer to expose the chip back side surface for pickup, is invented. The designs either use a levitation technology, or air dynamic, or a novel mechanical design to fulfill the chip front surfaces touchless requirement to avoid the chip surface contamination. The invented chip bonder is particularly useful for bonding applications which require using chips with zero tolerance of particle and/or contamination on the chip front surfaces or bonding surfaces. 1. A chip bonder—a piece of equipment for chip-to-wafer and chip-to-chip bonding , comprises at least:A chip supply/pickup station with a method to enable either a pickup/flip tool or a bonding head to access the backside surface of a chip, without touching the chip's front surface, either from a chip carrier or a diced wafer on a dicing tape;A chip bonding station with a bonding head.2. The system of claim 1 , wherein said chip bonder further comprises a flipped chip sitting station claim 1 , on which said chip is either picked claim 1 , flipped then placed by said pickup/flip tool; or from which said chip is picked by said bonding head.3. The system of claim 1 , wherein said chip bonder further comprises a surface activation station using an ion plasma technology to activate the bonding surface of said chip.4. The system of claim 1 , wherein said chip carrier is an accessory of said chip bonder and is made by a piece of specially treated and shaped diamagnetic material being capable of carrying and floating said chip in a magnetic field to expose said chip's bottom surface for pickup.5. The system of claim 1 , wherein said chip from said diced wafer is charged from the chip backside through said dicing tape then is levitated to expose the chip bottom surface for pickup in an electrical field via electrostatic levitation.6. The system of claim 1 , wherein said chip ...

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Номер записи: 12
07-01-2021 дата публикации

ULTRA-SMALL LED ELECTRODE ASSEMBLY AND METHOD FOR PREPARING SAME

Номер: US20210005596A1
Автор: DO Young Rag, SUNG Yeon Goog
Принадлежит:

Provided is a method of manufacturing a ultra-small light-emitting diode (LED) electrode assembly, the method including preparing a base substrate, forming an electrode line including a first electrode and a second electrode on the base substrate, positioning a guide member having a plurality of slit portions therein on the base substrate, and inserting ultra-small LED devices into the plurality of slit portions of the guide member. 114-. (canceled)15. A display device comprising:a substrate;a first electrode on the substrate and extending in a first direction; a second electrode spaced from the first electrode in a second direction and extending in the first direction;a bank on the first electrode and the second electrode and comprising a plurality of openings overlapping with at least a portion of the first electrode and the second electrode; anda plurality of LED devices in the openings, the LED devices extending in a direction,wherein the direction in which an LED device from among the plurality of LED devices is extended is at an angle with respect to the first direction in which the first electrode and the second electrode are extended.16. The display device of claim 15 , wherein the direction in which the LED device is extended is perpendicular to the first direction.17. The display device of claim 15 , wherein the first electrode and the second electrode are at a same plane.18. The display device of claim 15 , wherein the openings are arranged in parallel to each other.19. The display device of claim 18 , wherein the plurality of LED devices is on the first electrode and the second electrode.20. The display device of claim 19 , wherein the plurality of LED devices is arranged along the first direction.21. The display device of claim 18 , wherein a first length of the openings measured in the first direction is different from a second length of the openings measured in the second direction.22. The display device of claim 21 , wherein the second length of the ...

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Номер записи: 13
02-01-2020 дата публикации

Supporting InFO Packages to Reduce Warpage

Номер: US20200006251A1
Автор: Chen Hsien-Wei, Chen Jie, CHEN Ying-Ju
Принадлежит:

A method includes encapsulating a first device die and a second device die in an encapsulating material, forming redistribution lines over and electrically coupling to the first device die and the second device die, and bonding a bridge die over the redistribution lines to form a package, with the package including the first device die, the second device die, and the bridge die. The bridge die electrically inter-couples the first device die and the second device die. The first device die, the second device die, and the bridge die are supported with a dummy support die. 18.-. (canceled)9. A method comprising:encapsulating a first device die and a second device die in an encapsulating material;forming redistribution lines over the first device die and the second device die;forming electrical connectors overlying and electrically coupling to the first device die and the second device die through the redistribution lines;performing a singulation on the encapsulating material, wherein the first device die and the second device die are sawed into a package; andattaching the package to a dummy support die, wherein the dummy support die extends beyond edges of the package in each of four lateral directions.1011-. (canceled)12. The method of further comprising bonding a bridge die to the package claim 9 , wherein the bridge die is on an opposite side of the redistribution lines than the first device die and the second device die.13. The method of claim 12 , wherein the dummy support die is bonded to have a first portion overlapped by the first device die claim 12 , and a second portion overlapped by the second device die.1420.-. (canceled)21. A method comprising: a first device die;', 'a second device die;', 'an encapsulating material encapsulating the first device die and the second device die therein, wherein opposite sides of the adhesive film are in physical contact with the encapsulating material and the blank die; and', 'a plurality of redistribution lines over and ...

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Номер записи: 14
03-01-2019 дата публикации

Release Film as Isolation Film in Package

Номер: US20190006199A1
Автор: Chih-Wei Wu, Hsien-Ju Tsou, Jing-Cheng Lin, Pu Wang, Szu-Wei Lu, Ying-Ching Shih
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method includes forming a release film over a carrier, forming a metal post on the release film, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, decomposing a first portion of the release film to separate a second portion of the release film from the carrier, and forming an opening in the release film to expose the metal post.

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Номер записи: 15
02-01-2020 дата публикации

PACKAGING PROCESS AND MANUFACTURING METHOD

Номер: US20200006286A1
Автор: Chen Jiun-Ting, Lu Szu-Wei, Shih Ying-Ching, Wu Chih-Wei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A manufacturing method and a packaging process are provided. A package having a first die and a second die is provided. A circuit substrate having a first warpage level is provided. The package is mounted onto the circuit substrate and then heated under an elevated temperature to bond the package to the circuit substrate. The package heated under the elevated temperature is warped with a second warpage level, and the first warpage level is substantially in conformity with the second warpage level. 1. A bonding process , comprising:providing a circuit substrate on a fixture, wherein the circuit substrate has a mounting surface and mounting portions formed on the mounting surface;performing a substrate padding process;mounting a package onto the mounting surface of the circuit substrate, wherein the package has a bottom surface and connectors formed on the bottom surface of the package; andperforming a reflow process and bonding the connectors of the package to the mounting portions of the circuit substrate.2. The process according to claim 1 , wherein performing a substrate padding process includes placing a spacer underneath the circuit substrate and between the circuit substrate and the fixture to bend the circuit substrate and turn the mounting surface into a first warped surface.3. The process according to claim 2 , wherein the package includes at least one first die and a plurality of second dies claim 2 , and placing a spacer includes placing at least one spacer beneath the circuit substrate at a position corresponding to a position of the at least one first die of the package.4. The process according to claim 3 , wherein a vertical projection of the at least one spacer is partially overlapped with a vertical projection of the at least one first die.5. The process according to claim 3 , wherein a vertical projection of the at least one spacer is fully overlapped with a vertical projection of the at least one first die.6. The process according to claim 3 , ...

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Номер записи: 16
03-01-2019 дата публикации

FAN-OUT PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

Номер: US20190006314A1
Автор: Chuang Po-Yao, Fang Tzu-Jui, Jeng Shin-Puu, Lin Yi-Jou, Liu Hsien-Wen
Принадлежит:

Package structures and methods for forming the same are provided. A package structure includes a semiconductor die. The semiconductor die includes a passivation layer over a semiconductor substrate. The semiconductor die also includes a conductive pad in the passivation layer. The passivation layer partially exposes a top surface of the conductive pad. The package structure also includes an encapsulation layer surrounding the semiconductor die. The package structure further includes a dielectric layer covering the semiconductor die and the encapsulation layer. In addition, the package structure includes a redistribution layer covering the dielectric layer. The redistribution layer extends in the dielectric layer to be physically connected to the top surface of the conductive pad. 1. A package structure , comprising:a semiconductor die, comprising:a passivation layer over a semiconductor substrate; anda conductive pad in the passivation layer, wherein the passivation layer partially exposes a top surface of the conductive pad;an encapsulation layer surrounding the semiconductor die;a conductive pillar surrounded by the encapsulation layer and protruding from the encapsulation layer;a dielectric layer covering the semiconductor die and the encapsulation layer; anda redistribution layer covering the dielectric layer, wherein the redistribution layer extends in the dielectric layer to be physically connected to the top surface of the conductive pad.2. The package structure as claimed in claim 1 , wherein the dielectric layer adjoins the conductive pad claim 1 , the passivation layer and the encapsulation layer.3. (canceled)4. The package structure as claimed in claim 1 , wherein the dielectric layer extends in the passivation layer claim 1 , and the top surface of the conductive pad is partially exposed by the dielectric layer.5. (canceled)6. The package structure as claimed in claim 1 ,wherein the redistribution layer is in contact with the conductive pillar and the ...

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Номер записи: 17
27-01-2022 дата публикации

Single-Shot Encapsulation

Номер: US20220028813A1
Автор: Clark Jonathan, Ho Kok Khoon, MacLeod John
Принадлежит: SEMTECH CORPORATION

A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps. 1. A method of making a semiconductor device , comprising:providing a semiconductor wafer;forming a plurality of pillar bumps over the wafer;singulating the semiconductor wafer into a plurality of semiconductor die; anddepositing an encapsulant over the semiconductor die with the pillar bumps exposed from the encapsulant.2. The method of claim 1 , wherein the pillar bumps include solder caps.3. The method of claim 2 , wherein the solder caps include lead-free solder.4. The method of claim 1 , further including transfer-mounting the semiconductor die prior to depositing the encapsulant.5. The method of claim 1 , further including singulating the semiconductor die through the encapsulant.6. The method of claim 5 , further including singulating the semiconductor die with a plurality of semiconductor die packaged together.7. A method of making a semiconductor device claim 5 , comprising:providing a semiconductor die;forming a pillar bump over the semiconductor die;forming a solder cap over the pillar bump; anddepositing an encapsulant over the semiconductor die, pillar bump, and solder cap.8. The method of claim 7 , wherein a surface of the encapsulant is coplanar with a surface of the solder cap.9. The method of claim 7 , further including disposing the semiconductor die over a substrate after depositing the encapsulant claim 7 , wherein the encapsulant contacts the substrate.10. The method of claim 9 , further including reflowing the ...

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Номер записи: 18
11-01-2018 дата публикации

Electronic package and manufacturing method thereof

Номер: US20180012774A1
Автор: Dyi-chung Hu
Принадлежит: Individual

An electronic package including a middle patterned conductive layer, a first redistribution circuitry disposed on a first surface of the middle patterned conductive layer and a second redistribution circuitry disposed on a second surface of the middle patterned conductive layer is provided. The middle patterned conductive layer has a plurality of middle conductive pads. The first redistribution circuitry includes a first patterned conductive layer having a plurality of first conductive elements. Each of the first conductive elements has a first conductive pad and a first conductive via that form a T-shaped section. The second redistribution circuitry includes a second patterned conductive layer having a plurality of second conductive elements. Each of the second conductive elements has a second conductive pad and a second conductive via that form an inversed T-shaped section.

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Номер записи: 19
10-01-2019 дата публикации

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20190013214A1
Автор: Chang Chien Shang-Yu, HSU Hung-Hsin, LIN Han-Wen, LIN Nan-Chun
Принадлежит: POWERTECH TECHNOLOGY INC.

A manufacturing method of a package structure is described. The method includes at least the following steps. A carrier is provided. A semiconductor die and a sacrificial structure are disposed on the carrier. The semiconductor die is electrically connected to the bonding pads on the sacrificial structure through a plurality of conductive wires. As encapsulant is formed on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires. The carrier is debonded, and at least a portion of the sacrificial structure is removed through a thinning process. A redistribution layer is formed on the semiconductor die and the encapsulant. The redistribution layer is electrically connected to the semiconductor die through the conductive wires. 1. A manufacturing method of a package structure , comprising:providing a carrier,disposing a semiconductor die and at least one sacrificial structure on the carrier;electrically connecting the semiconductor die to bonding pads on the sacrificial structure through a plurality of conductive wires;forming an encapsulant on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires;debonding the carrier,removing at least a portion of the sacrificial structure through a thinning process; andforming a redistribution layer on the semiconductor die and the encapsulant, the redistribution layer is electrically connected to the semiconductor die through the conductive wires.2. The manufacturing method of a package structure according to claim 1 , wherein the sacrificial structure is disposed on the carrier claim 1 , and the semiconductor die is disposed on the sacrificial structure.3. The manufacturing method of a package structure according to claim 2 , wherein a width of the sacrificial structure is greater than a width of the semiconductor die.4. The manufacturing method of a package structure according to claim 2 , wherein the redistribution layer is formed on the ...

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Номер записи: 20
14-01-2021 дата публикации

PIXEL STRUCTURE, DISPLAY APPARATUS INCLUDING THE PIXEL STRUCTURE, AND METHOD OF MANUFACTURING THE PIXEL STRUCTURE

Номер: US20210013190A1
Автор: CHO Chio, CHO Hyunmin, HONG Sungjin, IM Hyundeok, KANG Jonghyuk, Kim Daehyun, LEE Jooyeol
Принадлежит:

A pixel structure of a display apparatus includes an electrode line, at least one ultra small light-emitting diode, and a connection electrode. The electrode line includes a second electrode separated from a first electrode and at a same level as the first electrode on a base substrate. The at least one ultra small light-emitting diode is on the base substrate and has a length less than a distance between the first and second electrodes. A connection electrode includes a first contact electrode connecting the first electrode to the ultra small light-emitting diode and a second contact electrode connecting the second electrode to the ultra small light-emitting diode. 1. A pixel structure of a display apparatus , the pixel structure comprising:a guide structure on a base substrate and having a first region and a second region extending from the first region, wherein the guide structure comprises a first electrode and a second electrode that extend along the second region and are separated from each other to define the second region;a plurality of light-emitting diodes in the second region, wherein a distance between a side of the first electrode and a side of the second electrode facing the side of the first electrode is greater than a length of the light-emitting diodes; anda dam structure that blocks an end of the second region,wherein the pixel structure comprises first and second contact electrodes contacting the light-emitting diodes, and connecting the light-emitting diodes to the first and second electrodes.2. The pixel structure as claimed in claim 1 , wherein a length of each of the light-emitting diodes is less than a width of the second region.3. The pixel structure as claimed in claim 1 , wherein each of the first electrode and the second electrode has a thickness greater than a thickness of the light-emitting diodes.4. The pixel structure as claimed in claim 1 , wherein the first electrode includes a first upper surface being separated by a first distance ...

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Номер записи: 21
09-01-2020 дата публикации

Supporting InFO Packages to Reduce Warpage

Номер: US20200013733A1
Автор: Chen Hsien-Wei, Chen Jie, CHEN Ying-Ju
Принадлежит:

A method includes encapsulating a first device die and a second device die in an encapsulating material, forming redistribution lines over and electrically coupling to the first device die and the second device die, and bonding a bridge die over the redistribution lines to form a package, with the package including the first device die, the second device die, and the bridge die. The bridge die electrically inter-couples the first device die and the second device die. The first device die, the second device die, and the bridge die are supported with a dummy support die. 1. A package comprising:a first device die;a second device die;a first encapsulating material encapsulating the first device die and the second device die therein;a plurality of redistribution lines over and electrically coupling to the first device die and the second device die;a bridge die over and bonded to the redistribution lines, wherein the bridge die electrically intercouples the first device die and the second device die; anda dummy support die underlying and attached to the first device die and the second device die.2. The package of claim 1 , wherein the bridge die comprises:a first portion overlapping the first device die; anda second portion overlapping the second device die.3. The package of claim 1 , wherein the bridge die comprises a substrate and an interconnect structure on the substrate claim 1 , and the bridge die is free from active devices and passive devices therein.4. The package of further comprising a first die-attach film and a second die-attach film attaching the first device die and the second device die claim 1 , respectively claim 1 , to the dummy support die.5. The package of further comprising a continuous adhesive film comprising:a first portion between and contacting the first die-attach film and the dummy support die; anda second portion between and contacting the second die-attach film and the dummy support die.6. The package of claim 4 , wherein the dummy support ...

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Номер записи: 22
14-01-2021 дата публикации

Method for replacing or patching element of display device

Номер: US20210015011A1
Автор: Li-Yi Chen
Принадлежит: Mikro Mesa Technology Co Ltd

A method for replacing an element of a display device includes: forming a structure with a first liquid layer between a first micro device and a conductive pad of a substrate in which the first micro device is gripped by a capillary force produced by the first liquid layer; evaporating the first liquid layer such that the first micro device is bound to the substrate; determining if the first micro device is malfunctioned or misplaced; removing the first micro device when the first micro device is malfunctioned or misplaced; forming an another structure with a second liquid layer between a second micro device and the conductive pad of the substrate in which the second micro device is gripped by a capillary force produced by the second liquid layer; and evaporating the second liquid layer such that the second micro device is bound to the substrate.

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Номер записи: 23
21-01-2016 дата публикации

Apparatus and methods for micro-transfer-printing

Номер: US20160020120A1
Автор: Christopher Bower, David Gomez, David Kneeburg, Matthew Meitl, Salvatore Bonafede
Принадлежит: X Celeprint Ltd

In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed.

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Номер записи: 24
19-01-2017 дата публикации

Semiconductor Device and Method of Forming EMI Shielding Layer with Conductive Material Around Semiconductor Die

Номер: US20170018507A1
Автор: Carson Flynn, Pagaila Reza A., Yoon Seung Uk
Принадлежит: STATS ChipPAC Pte. Ltd.

A semiconductor device has a plurality of first semiconductor die mounted over an interface layer formed over a temporary carrier. An encapsulant is deposited over the first die and carrier. A flat shielding layer is formed over the encapsulant. A channel is formed through the shielding layer and encapsulant down to the interface layer. A conductive material is deposited in the channel and electrically connected to the shielding layer. The interface layer and carrier are removed. An interconnect structure is formed over conductive material, encapsulant, and first die. The conductive material is electrically connected through the interconnect structure to a ground point. The conductive material is singulated to separate the first die. A second semiconductor die can be mounted over the first die such that the shielding layer covers the second die and the conductive material surrounds the second die or the first and second die. 1. A method of making a semiconductor device , comprising:providing a first semiconductor die;depositing an encapsulant around the first semiconductor die;forming a shielding layer over the first semiconductor die;forming a channel through the encapsulant around the first semiconductor die;depositing a conductive material in the channel around the first semiconductor die and electrically connected to the shielding layer; andforming an interconnect structure over the conductive material, encapsulant, and first semiconductor die, wherein the interconnect structure is electrically connected to the conductive material.2. The method of claim 1 , wherein the conductive material extends into the interconnect structure.3. The method of claim 1 , wherein the conductive material terminates at a boundary between the encapsulant and interconnect structure.4. The method of claim 1 , further including providing side-by-side first semiconductor die each covered by the shielding layer and surrounded by the conductive material.5. The method of claim 1 , further ...

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Номер записи: 25
21-01-2021 дата публикации

METHOD FOR MANUFACTURING ELECTRONIC DEVICE

Номер: US20210020461A1
Автор: IGARASHI Kouji, KINOSHITA Jin, KURIHARA Hiroyoshi, Miura Toru
Принадлежит: Mitsui Chemicals Tohcello, Inc.

The method for manufacturing an electronic device includes at least: a step of preparing a structure provided with an adhesive film provided with a base material layer, an adhesive resin layer (A) provided on a first surface side of the base material layer and for temporarily fixing an electronic component, and an adhesive resin layer (B) provided on a second surface side of the base material layer and in which an adhesive force is decreased by an external stimulus, an electronic component attached to the adhesive resin layer (A) of the adhesive film, and a support substrate attached to the adhesive resin layer (B) of the adhesive film; at least one step selected from a step of decreasing water content in the adhesive film and a step of decreasing water content in the structure; and a step of sealing the electronic component with a sealing material. 1. A method for manufacturing an electronic device , comprising at least:{'b': '1', 'claim-text': [ a base material layer;', 'an adhesive resin layer (A) for temporarily fixing an electronic component, which is provided on a first surface side of the base material layer; and', 'an adhesive resin layer (B) in which an adhesive force is decreased by an external stimulus, which is provided on a second surface side of the base material layer;, 'an adhesive film having, 'an electronic component attached to the adhesive resin layer (A) of the adhesive film; and', 'a support substrate attached to the adhesive resin layer (B) of the adhesive film;, 'a step () of preparing a structure having{'b': 2', '2', '1', '2', '2, 'at least one step () selected from a step (-) of decreasing water content in the adhesive film and a step (-) of decreasing water content in the structure; and'}{'b': '3', 'a step () of sealing the electronic component with a sealing material.'}2. The method for manufacturing an electronic device according to claim 1 ,{'b': 2', '2', '1, 'wherein the step () includes the step (-) of decreasing the water content in ...

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Номер записи: 26
21-01-2021 дата публикации

MULTI-LAYER TETHERS FOR MICRO-TRANSFER PRINTING

Номер: US20210020491A1
Автор: Bower Christopher Andrew, Trindade António José Marques
Принадлежит:

A micro-device structure comprises a source substrate comprising sacrificial portions laterally spaced apart by anchors. Each sacrificial portion is exposed through an opening. A micro-device is disposed on each sacrificial portion and laterally attached to an anchor by a multi-layer tether. In certain embodiments, a micro-device structure is constructed by providing the source substrate, disposing micro-devices on each sacrificial portion, depositing a first tether layer over at least a portion of the source substrate and the micro-device, depositing a second tether layer over the first tether layer, and patterning the first tether layer and the second tether layer to form (i) a multi-layer tether for each of the micro-devices such that the multi-layer tether laterally attaches the micro-device to one of the anchors, and (ii) an opening exposing each of the sacrificial portions. 117-. (canceled)18. A method of making a micro-device structure , comprising:providing a source substrate comprising sacrificial portions spaced apart by anchors;disposing micro-devices in association with the source substrate such that each of the micro-devices is disposed exclusively on, in, or over one of the sacrificial portions;depositing a first tether layer over at least a portion of the source substrate and the micro-devices;depositing a second tether layer over the first tether layer, the first tether layer thicker than the second tether layer; andpatterning the first tether layer and the second tether layer to form (i) a corresponding multi-layer tether for each of the micro-devices such that the corresponding multi-layer tether laterally attaches the micro-device to one of the anchors, and (ii) an opening exposing each of the sacrificial portions,wherein after the patterning (i) the first tether layer extends over at least a portion of each of the micro-devices, (ii) the second tether layer extends over at least a portion of each of the micro-devices, or (iii) the first tether ...

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Номер записи: 27
21-01-2021 дата публикации

SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20210020533A1
Автор: Lu Wen-Long
Принадлежит: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

A semiconductor device package includes an electronic component, an encapsulation layer encapsulating the electronic component, and a passivation layer stacking with the encapsulation layer. The passivation layer has a first surface facing the encapsulation layer, a second surface opposite to the first surface, and a first sidewall connecting the first surface and the second surface. The first sidewall inclines with respect to the second surface, and a first projection width of the encapsulation layer is greater than a second projection width of the passivation layer. 1. A semiconductor device package , comprising:an electronic component;an encapsulation layer encapsulating the electronic component; anda passivation layer stacking with the encapsulation layer, wherein the passivation layer has a first surface facing the encapsulation layer, a second surface opposite to the first surface, and a first sidewall connecting the first surface and the second surface, the first sidewall inclining with respect to the second surface, wherein a first projection width of the encapsulation layer is greater than a second projection width of the passivation layer.2. The semiconductor device package of claim 1 , wherein the second surface is smaller than the first surface.3. The semiconductor device package of claim 1 , wherein the encapsulation layer has a third surface facing the passivation layer claim 1 , a fourth surface opposite to the third surface claim 1 , and a second sidewall connecting the third surface and the fourth surface.4. The semiconductor device package of claim 3 , wherein the encapsulation layer hangs over the passivation layer.5. The semiconductor device package of claim 3 , wherein a surface roughness of the second sidewall of the encapsulation layer is larger than a surface roughness of the first sidewall of the passivation layer.6. The semiconductor device package of claim 3 , wherein the third surface is larger than the fourth surface.7. The semiconductor ...

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Номер записи: 28
21-01-2021 дата публикации

SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF

Номер: US20210020605A1
Автор: Do Won Chul, Hiner David, Huemoeller Ronald, KELLY MICHAEL, Khim Jin Young, Lee Sang Hyoun, Mok In Su
Принадлежит:

A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a connect die that routes electrical signals between a plurality of other semiconductor die. 1. An electronic device comprising:a signal redistribution structure (SRS) comprising a top SRS side, a bottom SRS side, and a plurality of lateral SRS sides, where the signal redistribution structure is coreless;a lower electronic component (LEC) comprising a top LEC side, a bottom LEC side, and a plurality of lateral LEC sides, where the top LEC side is coupled to the bottom SRS side;a vertical interconnect structure coupled to the bottom SRS side at a position that is laterally offset from the lower electronic component;an LEC interconnect structure that is coupled to the top LEC side and to the bottom SRS side, such that the lower electronic component is electrically coupled to the signal redistribution structure through at least the LEC interconnect structure;a semiconductor die comprising a top die side, a bottom die side, and a plurality of lateral die sides;a first die interconnect structure coupled to the top SRS side and to the bottom die side, such that the semiconductor die is electrically coupled to the vertical interconnect structure; anda second die interconnect structure coupled to the top SRS side and to the bottom die side, such that the semiconductor die is electrically coupled to the lower electronic component.2. The electronic device of claim 1 , wherein:the semiconductor die is electrically coupled to the vertical interconnect structure through at least the first die interconnect structure and the signal redistribution structure; andthe semiconductor die is electrically coupled to the lower electronic component through at least the second die interconnect structure, the signal redistribution structure, and the LEC ...

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Номер записи: 29
10-02-2022 дата публикации

Method for Manufacturing Display Device and Display Device Manufacturing Apparatus

Номер: US20220045039A1
Автор: Kusunoki Koji, Nonaka Taiki, TSUKAMOTO Yosuke, Yamazaki Shunpei, Yoshizumi Kensuke
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

To reduce the manufacturing cost of a display device using a micro LED as a display element. To manufacture a display device using a micro LED as a display element in a high yield. Employed is a method for manufacturing a display device, including: forming a plurality of transistors in a matrix over a substrate (), forming conductors () electrically connected to the transistors over the substrate (), and forming a plurality of light-emitting elements () in a matrix over a film (). Each of the light-emitting elements () includes electrodes () on one surface and the other surface is in contact with the film (). The conductors () and the electrodes () are opposed to each other. An extrusion mechanism () is pushed out from the film () side to the substrate () side so that the conductors () and the electrodes () are in contact with each other, whereby the conductors () and the electrodes () are electrically connected to each other. 1. A method for manufacturing a display device , comprising:forming a first plurality of transistors in a matrix over a substrate,forming a conductor electrically connected to the first plurality of transistors over the substrate after forming the first plurality of transistors;forming a first plurality of light-emitting elements comprising an electrode in a matrix over a first film;arranging the substrate and the first film so that the conductor and the electrode face each other:electrically connecting the conductor and the electrode by pushing out the one of the first plurality of light-emitting elements after arranging the substrate and the first film,wherein one of the first plurality of light-emitting elements includes the electrode on one surface and is in contact with the first film on the other surface.2. The method for manufacturing a display device claim 1 , according to claim 1 , further comprising:after electrically connecting the conductor and the electrode, applying an ultrasonic wave to the conductor and the electrode, whereby ...

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Номер записи: 30
24-01-2019 дата публикации

SEMICONDCUTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20190027452A1
Автор: Chen Chen-Shien, Chen Ching-Hui, Huang Hon-Lin, KU Chin-Yu, KUO Chien-Hung, WANG CHAO-YI, Yang Cheng-Lung
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor device and a manufacturing method for the semiconductor device are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump a spacer and surrounds the bump and disposed between the etching stop layer and the bump. 17-. (canceled)8. A manufacturing method for a semiconductor device , comprising:forming an etching stop layer over a first dielectric layer, wherein the first dielectric layer is formed over a conductive structure;forming a sacrificial layer over the etching stop layer, wherein an opening passes through the sacrificial layer and the etching stop layer to expose a portion of the conductive structure;forming a spacer on a sidewall of the opening;after forming the spacer, forming a bump in the opening to electrically connect the conductive structure, wherein the spacer is disposed between the etching stop layer and the bump; andafter forming the bump, removing a portion of the spacer on the sidewall of the opening.9. The method as claimed in claim 8 , wherein the spacer is formed over the first dielectric layer between the etching stop layer and the bump.10. The method as claimed in claim 8 , wherein forming the bump and the spacer comprises:forming a spacer layer on the sidewall and a bottom of the opening;removing the spacer layer on the bottom of the opening, to expose the conductive structure and form the spacer;forming the bump in the opening, wherein the spacer on the sidewall of the opening surrounds the bump; andremoving the portion of the spacer on the sidewall of the opening.11. The method as claimed in claim 8 , further comprising forming a second dielectric layer over a portion of the first dielectric layer ...

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Номер записи: 31
23-01-2020 дата публикации

Device and method for contactlessly transferring at least partly ferromagnetic electronic components from a carrier to a substrate

Номер: US20200027764A1
Автор: Hans-Peter Monser, Sigmund Niklas
Принадлежит: Muehlbauer GmbH and Co KG

The device and method according to the invention are used to transfer an electronic ferromagnetic component from a carrier to a substrate using a magnetic assembly. The magnetic assembly is designed and arranged to aid in the correct positioning of the at least partly ferromagnetic electronic component on the substrate. The magnetic field generated by the magnetic assembly produces a magnetic force oriented from the carrier towards the substrate, said magnetic force aiding the transfer of the component from the carrier to the substrate such that a significantly increased positioning accuracy of the component is achieved compared to a transfer without said magnetic force.

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Номер записи: 32
23-01-2020 дата публикации

PACKAGING STRUCTURE AND FORMING METHOD THEREOF

Номер: US20200027857A1
Автор: Shi Lei
Принадлежит:

Packaging structure and method of forming a packaging structure are provided. A substrate is provided, and an adhesive layer is formed on the substrate. An improvement layer is formed on the adhesive layer. The improvement layer contains openings exposing surface portions of the adhesive layer at bottoms of the openings. A plurality of chips is provided and includes functional surfaces. The plurality of chips is mounted on the substrate such that the functional surfaces are bonded to the adhesive layer at the bottoms of the openings. 1. A method of forming a packaging structure , comprising:providing a substrate;forming an adhesive layer on the substrate;forming an improvement layer on the adhesive layer, wherein the improvement layer contains openings there-in, exposing surface portions of the adhesive layer at bottoms of the openings;providing a plurality of chips, wherein the plurality of chips includes functional surfaces; andmounting the plurality of chips on the substrate such that the functional surfaces are bonded to the adhesive layer at the bottoms of the openings.2. The method according to claim 1 , wherein the substrate is made of a material including glass claim 1 , ceramic claim 1 , metal claim 1 , or polymer.3. The method according to claim 1 , wherein the plurality of chips has a top surface higher than the improvement layer.4. The method according to claim 3 , wherein the plurality of chips has a thickness in a range of approximately 20 micrometers to 100 micrometers.5. The method according to claim 3 , wherein the openings have a depth in a range of approximately 10 micrometers to 50 micrometers.6. The method according to claim 1 , wherein the adhesive layer includes an ultraviolet adhesive claim 1 , an acrylic pressure sensitive adhesive claim 1 , or an epoxy pressure sensitive adhesive.7. The method according to claim 1 , wherein forming the improvement layer includes:forming an improvement film on the adhesive layer; andforming openings in the ...

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Номер записи: 33
23-01-2020 дата публикации

Packaging structure and forming method thereof

Номер: US20200027858A1
Автор: Lei Shi
Принадлежит: Tongfu Microelectronics Co Ltd

Packaging structure and method for forming a packaging structure are provided. A bonding layer is formed on the substrate. An improvement layer is formed on the bonding layer. The improvement layer contains openings exposing surface portions of the bonding layer at bottoms of the openings. Chips are provided and include functional surfaces. The chips are mounted on the substrate by bonding the functional surfaces of the chips to the bonding layer through the openings. Top surfaces of the chips are lower than or flush with a top surface of the improvement layer.

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Номер записи: 34
23-01-2020 дата публикации

PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF

Номер: US20200027859A1
Автор: Shi Lei
Принадлежит:

The present disclosure provides a package structure and its packaging method. The packaging method includes: providing a bonding layer on a substrate; forming an improvement layer on the bonding layer, where the improvement layer has openings, and bottoms of the openings expose a surface of the bonding layer; providing chips, each including a non-functional surface; and mounting the chips by attaching the non-functional surface to the bonding layer at the bottoms of the openings. 1. A fabrication method of a package structure , comprising:providing a bonding layer on a substrate;forming an improvement layer on the bonding layer, wherein the improvement layer has openings, and bottoms of the openings expose a surface of the bonding layer;providing chips, each including a non-functional surface; andmounting the chips by attaching the non-functional surfaces to the bonding layer at the bottoms of the openings.2. The fabrication method according to claim 1 , wherein:each chip includes a functional surface opposing to the non-functional surface; andthe functional surface of the chip is lower than or equal to a top surface of the improvement layer; or the functional surface of the chip is higher than a top surface of the improvement layer.3. The fabrication method according to claim 1 , wherein:the bonding layer includes an ultraviolet adhesive, an acrylic acid pressure sensitive adhesive or an epoxy resin pressure sensitive adhesive.4. The fabrication method according to claim 1 , wherein forming the improvement layer and the openings includes:forming an improvement film on the surface of the bonding layer; andexposing and developing the improvement film to form the improvement layer having the openings.5. The fabrication method according to claim 4 , wherein:a material of the improvement film includes a photoresist.6. The fabrication method according to claim 2 , after mounting the chips claim 2 , further including:forming an encapsulation layer on the top surface of ...

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Номер записи: 35
01-02-2018 дата публикации

Microperturbation Assembly System and Method

Номер: US20180029038A1
Автор: Kenji Sasaki, Paul J. Schuele, Shu-Han Yu
Принадлежит: eLux Inc

Microperturbation fluidic assembly systems and methods are provided for the fabrication of emissive panels. The method provides an emissive substrate with a top surface patterned to form an array of wells. A liquid suspension is formed over the emissive substrate top surface, comprising a first liquid and emissive elements. Using an array of micropores, a perturbation medium, which optionally includes emissive elements, is injected into the liquid suspension. The perturbation medium may be the first liquid, a second liquid, or a gas. A laminar flow is created in the liquid suspension along the top surface of the emissive substrate in response to the perturbation medium, and emissive elements are captured in the wells. The ejection of the perturbation medium can also be used to control the thickness of the liquid suspension overlying the top surface of the emissive substrate.

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Номер записи: 36
31-01-2019 дата публикации

PACKAGE DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20190035715A1
Автор: CHOU Hsueh-Hsuan, FAN Chia-Chieh, Lin Yi-Hung, Sung Li-Wei, WANG Cheng-Chi, Wang Kuan-Jen
Принадлежит:

The present disclosure provides a package device including a conductive pad, a protecting block, and a redistribution layer. The protecting block is disposed on the conductive pad. The redistribution layer is disposed on the protecting block, and the conductive pad is electrically connected to the redistribution layer through the protecting block. 1. A package device , comprising:a conductive pad;a protecting block, disposed on the conductive pad; anda redistribution layer, disposed on the protecting block, and the conductive pad being electrically connected to the redistribution layer through the protecting block.2. The package device according to claim 1 , wherein the conductive pad is directly in contact with the protecting block.3. The package device according to claim 1 , wherein the protecting block covers the conductive pad in a top view direction of the package device.4. The package device according to claim 1 , wherein the conductive pad and the protecting block are formed of a same material.5. The package device according to claim 1 , wherein the protecting block comprises a conductive material.6. The package device according to claim 1 , wherein the conductive pad and the protecting block have different thicknesses.7. The package device according to claim 1 , further comprising an electronic device claim 1 , disposed on the redistribution layer claim 1 , wherein the conductive pad is electrically connected to the electronic device through the protecting block and the redistribution layer.8. The package device according to claim 7 , wherein the redistribution layer comprises at least one dielectric layer and at least one patterned conductive layer claim 7 , and the conductive pad is electrically connected to the electronic device through the at least one patterned conductive layer.9. The package device according to claim 7 , further comprising an encapsulation layer disposed between the electronic device and the redistribution layer.10. The package device ...

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Номер записи: 37
31-01-2019 дата публикации

METHOD OF FABRICATING SEMICONDUCTOR PACKAGE

Номер: US20190035756A1
Автор: KIM Jongyoun, LEE SEOKHYUN, Lee SeokWon, MIN Youn Ji, Suk Kyoung Lim
Принадлежит:

A method of fabricating a semiconductor package including, forming a preliminary first insulating layer including a first opening, curing the preliminary first insulating layer to form a first insulating layer, forming a preliminary second insulating layer on the first insulating layer at least partially filling the first opening. The method includes forming a second opening in the preliminary second insulating layer at least partially overlapping the first opening. A sidewall of the first opening is at least partially exposed during forming the second opening. The preliminary second insulating layer is cured to form a second insulating layer. A barrier metal layer is formed along the sidewall of the first opening and along a sidewall of the second opening. A redistribution conductive pattern is formed on the barrier metal layer. A planarization process is performed to at least partially expose the second insulating layer. 1. A method of fabricating a semiconductor package , the method comprising:forming a preliminary first insulating layer including a first opening;curing the preliminary first insulating layer to form a first insulating layer;forming a preliminary second insulating layer on the first insulating layer, the preliminary second insulating layer at least partially filling the first opening;forming a second opening in the preliminary second insulating layer, the second opening at least partially overlapping the first opening, wherein a sidewall of the first opening is at least partially exposed during forming the second opening;curing the preliminary second insulating layer to form a second insulating layer;forming a barrier metal layer along the sidewall of the first opening and along a sidewall of the second opening;forming a redistribution conductive pattern on the barrier metal layer; andperforming a planarization process to at least partially expose the second insulating layer.2. The method of claim 1 , wherein claim 1 , after performing the ...

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Номер записи: 38
30-01-2020 дата публикации

Adhesive substrate, transfer device having adhesive substrate, and method for producing adhesive substrate

Номер: US20200035627A1
Автор: Hiroyuki Iguchi, Toshio Shiobara, Tsutomu Kashiwagi
Принадлежит: Shin Etsu Chemical Co Ltd

An adhesive substrate includes a support base member and an adhesive layer provided on the support base member. The support base member contains electroconductive particles and an insulating resin, and has a recessed and projected pattern with two or more projected portions on one surface or both surfaces of the support base member. The adhesive layer is provided at least on upper surfaces of the projected portions in the recessed and projected pattern of the support base member. The adhesive layer on the upper surfaces of the projected portions has an upper surface with a curved surface. Thus, the present invention provides an adhesive substrate capable of selectively picking up and quickly transferring large amounts of fine chips and particles, a method for producing the adhesive substrate, and a transfer device.

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Номер записи: 39
09-02-2017 дата публикации

Roll-to-roll fabricated light sheet and encapsulated semiconductor device

Номер: US20170038055A1
Автор: John J. Daniels
Принадлежит: Articulated Technologies LLC

A bottom electrically conductive surface is disposed on the top surface of a substrate and a top electrically conductive surface disposed on the bottom surface of a superstrate. A bare die electronic device is disposed with at least one of its top conductor in direct electrical communication with the bottom electrically conductive surface and/or its bottom conductor in direct electrical communication with the top conductive surface. A non-conductive adhesive secures the substrate to the superstrate so that the bare die electronic device is retained in direct electrical communication. The non-conductive adhesive has a melting point temperature at least greater than a minimum operating temperature of the operating temperature range of the bare die, so that the non-conductive adhesive does not melt and flow thereby preventing a separation or degradation of the direct electrical connection of the bare die electronic device.

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Номер записи: 40
11-02-2016 дата публикации

Batch Process for Connecting Chips to a Carrier

Номер: US20160043054A1
Автор: Fischer Rupert, HEINRICH Alexander, Mahler Joachim, Roesl Konrad, Strobel Peter
Принадлежит:

Methods for connecting chips to a chip carrier are disclosed. In some embodiments the method for connecting a plurality of chips to a chip carrier includes placing first chips on a transfer carrier, placing second chips on the transfer carrier, placing the transfer carrier with the first and second chips on the chip carrier and forming connections between the first chips and the chip carrier and the second chips and the chip carrier. 1. A method for connecting a plurality of chips to a chip carrier , the method comprising:placing first chips on a transfer carrier;placing second chips on the transfer carrier, wherein the first chips are different from the second chips;placing the transfer carrier with the first and second chips on the chip carrier; andafter placing the transfer carrier on the chip carrier, forming connections between the first chips and the chip carrier and the second chips and the chip carrier.2. The method according to claim 1 , wherein forming the connections comprises forming first connections for the first chips using an electrically insulating connection medium and forming second connections for the second chips using an electrically conductive connection medium.3. The method according to claim 1 , wherein forming the connections comprises forming first connections for the first chips applying a first electrically conductive connection medium and forming second connections for the second chips applying a second electrically conductive connection medium.4. The method according to claim 3 , wherein the first electrically conductive connection medium and the second electrically conductive connection medium are the same.5. The method according to claim 1 , wherein forming the connections comprises forming first connections for the first chips applying a first electrically insulating connection medium and forming second connections for the second chips applying a second electrically insulating connection medium.6. The method according to claim 1 , ...

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Номер записи: 41
24-02-2022 дата публикации

Carrier Assisted Substrate Method of Manufacturing an Electronic Device and Electronic Device Produced Thereby

Номер: US20220059387A1
Автор: Kweon Young Do, St. Amand Roger
Принадлежит:

An electronic device structure and a method for making an electronic device. As non-limiting examples, various aspects of this disclosure provide a method of manufacturing an electronic device that comprises the utilization of a carrier assisted substrate, and an electronic device manufactured thereby. 120-. (canceled)21. A method of manufacturing an electronic component , the method comprising:forming a redistribution structure (RDS) comprising a top redistribution structure (RDS) side, a bottom redistribution structure (RDS) side, and a lateral redistribution structure (RDS) side, where the redistribution structure (RDS) comprises at least one dielectric material and at least one conductive material;forming a bottom solder resist (SR) material on the bottom redistribution structure (RDS) side and comprising a top solder resist (SR) side, a bottom solder resist (SR) side, and a lateral solder resist (SR) side, where the bottom solder resist (SR) material comprises a bottom solder resist (SR) aperture that exposes a respective portion of the bottom redistribution structure (RDS) side through the bottom solder resist (SR) material; andforming a carrier on the bottom solder resist (SR) side, where a portion of the carrier is positioned in the bottom solder resist (SR) aperture.22. The method of claim 21 , where said forming the redistribution structure (RDS) comprises forming pads at the top redistribution structure (RDS) side for attaching a semiconductor die to the redistribution structure (RDS).23. The method of claim 21 , where said forming the carrier comprises:forming a carrier material; andafter said forming the carrier material, removing a portion of the carrier material.24. The method of claim 23 , wherein said removing the portion of the carrier material comprises grinding the portion of the carrier material.25. The method of claim 21 , wherein said forming the redistribution structure (RDS) comprises forming under bump metallization at the bottom ...

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Номер записи: 42
15-02-2018 дата публикации

Molding for large panel fan-out package

Номер: US20180047651A1
Автор: Ming Tsung SHEN, Po-Wei LU, Shao-An CHEN, Yu-Tzu PENG
Принадлежит: Advanced Semiconductor Engineering Inc

The present disclosure relates to wafer level packages including one or more semiconductor dies and a method of manufacturing the same. A method comprises: providing a carrier having a predetermined area, disposing a semiconductor device on the predetermined area, and forming a sacrificial wall on a periphery of the predetermined area.

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Номер записи: 43
15-02-2018 дата публикации

Single-Shot Encapsulation

Номер: US20180047688A1
Автор: John MacLeod, Jonathan Clark, Kok Khoon Ho
Принадлежит: Semtech Corp

A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps.

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Номер записи: 44
14-02-2019 дата публикации

INTEGRATED FAN-OUT PACKAGE AND METHOD FOR FABRICATING THE SAME

Номер: US20190051604A1
Автор: Yee Kuo-Chung, Yu Chen-Hua, Yu Chun-Hui
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

An integrated fan-out package includes an integrated circuit, a plurality of semiconductor devices, a first redistribution circuit structure, and an insulating encapsulation. The integrated circuit has an active surface and a rear surface opposite to the active surface. The semiconductor devices are electrically connected the integrated circuit. The first redistribution circuit structure is disposed between the integrated circuit and the semiconductor devices. The first redistribution circuit structure is electrically connected to the integrated circuit and the semiconductor devices respectively. The first redistribution circuit structure has a first surface, a second surface opposite to the first surface, and lateral sides between the first surface and the second surface. The insulating encapsulation encapsulates the integrated circuit and the semiconductor devices and covers the first surface and the second surface of the first redistribution circuit structure. Furthermore, methods for fabricating the integrated fan-out package are also provided. 1. An integrated fan-out package , comprising:an integrated circuit having an active surface and a rear surface opposite to the active surface;a plurality of semiconductor devices electrically connected the integrated circuit, wherein the plurality of semiconductor devices are arranged in a side-by-side manner from a top view of the integrated fan-out package;a first redistribution circuit structure disposed between the integrated circuit and the semiconductor devices and electrically connected to the integrated circuit and the semiconductor devices respectively, wherein the first redistribution circuit structure has a first surface, a second surface opposite to the first surface and lateral sides between the first surface and the second surface;a die-attach film disposed between the rear surface of the integrated circuit and the first surface of the first redistribution circuit structure; andan insulating encapsulation ...

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Номер записи: 45
22-02-2018 дата публикации

Pre-bumped redistribution layer structure and semiconductor package incorporating such pre-bumped redistribution layer structure

Номер: US20180053665A1
Автор: Che-Hung KUO, Che-Ya Chou, Nan-Cheng Chen
Принадлежит: MediaTek Inc

A pre-bumped redistribution layer (RDL) structure is disclosed. The pre-bumped RDL structure includes at least a dielectric layer, a first metal layer on the first surface, a second metal layer on the second surface, and a via layer electrically connecting the first metal layer and the second metal layer. At least a bump pad is formed in the first metal layer. A bump is disposed on the bump pad. The bump comprises a copper layer with its lower end directly jointed to a top surface of the bump pad.

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Номер записи: 46
22-02-2018 дата публикации

METHOD OF MASS TRANSFERRING ELECTRONIC DEVICE

Номер: US20180053742A1
Автор: Huang Jing-En, Huang Yi-Ru, Lan Yan-Ting, Ting Shao-Ying
Принадлежит: GENESIS PHOTONICS INC.

A method of mass transferring electronic devices includes following steps. A wafer is provided. The wafer includes a substrate and a plurality of electronic devices. The electronic devices are arranged in a matrix on a surface of the substrate. The wafer is attached to a temporary fixing film. The wafer is cut so that the wafer is divided into a plurality of blocks. Each of the blocks includes at least a part of the electronic devices and a sub-substrate. The temporary fixing film is stretched so that the blocks on the temporary fixing film are separated from each other as the temporary fixing film is stretched. At least a part of the blocks is selected as a predetermined bonding portion, and each of the blocks in the predetermined bonding portion is transferred to a carrying substrate in sequence, so that the electronic devices in the predetermined bonding portion arc bonded to the carrying substrate. The sub-substrates of the blocks are removed. Another method of mass transferring electronic devices is also provided. 1. A method of mass transferring electronic devices , comprising:providing a wafer comprising a substrate and a plurality of electronic devices, the electronic devices being arranged in a matrix on a surface of the substrate;attaching the wafer to a temporary fixing film;cutting the wafer so that the wafer is divided into a plurality of blocks, each of the blocks comprising at least a part of the electronic devices and a sub-substrate;stretching the temporary fixing film so that the blocks on the temporary fixing film arc separated from each other as the temporary fixing film is stretched;selecting at least a part of the blocks as a predetermined bonding portion, and transferring each of the blocks in the predetermined bonding portion to a carrying substrate in sequence, so that the electronic devices in the predetermined bonding portion are bonded to the carrying substrate; andremoving the sub-substrates of the blocks in sequence.2. The method of ...

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Номер записи: 47
25-02-2021 дата публикации

SEMICONDUCTOR PACKAGE

Номер: US20210057344A1
Автор: KIM Jongyoun
Принадлежит:

A semiconductor package includes a redistribution layer, a semiconductor chip on the redistribution layer, and a molding layer covering a sidewall of the semiconductor chip and a top surface and a sidewall of the redistribution layer. The sidewall of the redistribution layer is inclined with respect to a bottom surface of the redistribution layer, and a sidewall of the molding layer is spaced apart from the sidewall of the redistribution layer. 1. A semiconductor package comprising:a redistribution layer;a semiconductor chip on the redistribution layer; anda molding layer covering a sidewall of the semiconductor chip and a top surface and a sidewall of the redistribution layer,wherein the sidewall of the redistribution layer is inclined with respect to a bottom surface of the redistribution layer, andwherein a sidewall of the molding layer is spaced apart from the sidewall of the redistribution layer.2. The semiconductor package of claim 1 , wherein a distance between the sidewall of the molding layer and the sidewall of the redistribution layer increases in an upward vertical direction.3. The semiconductor package of claim 1 , wherein an angle between the sidewall of the redistribution layer and the bottom surface of the redistribution layer is an acute angle.4. The semiconductor package of claim 3 , wherein the angle between the sidewall of the redistribution layer and the bottom surface of the redistribution layer is equal to or greater than 45 degrees and less than 90 degrees.5. The semiconductor package of claim 1 , wherein a bottom surface of an edge portion of the molding layer is coplanar with the bottom surface of the redistribution layer.6. The semiconductor package of claim 1 , wherein a surface roughness of the sidewall of the redistribution layer is less than a surface roughness of the sidewall of the molding layer.7. The semiconductor package of claim 1 , wherein the redistribution layer comprises a plurality of sidewalls claim 1 , andwherein the ...

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Номер записи: 48
25-02-2021 дата публикации

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Номер: US20210057346A1
Автор: Chen Chien-Hsun, CHEN Wei-Ting, Huang Shih-Ya, Tsai Chung-Hao, WANG Chuei-Tang, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor package includes dies, a redistribution structure, a conductive structure and connectors. The conductive plate is electrically connected to contact pads of at least two dies and is disposed on redistribution structure. The conductive structure includes a conductive plate and a solder cover, and the conductive structure extend over the at least two dies. The connectors are disposed on the redistribution structure, and at least one connector includes a conductive pillar. The conductive plate is at same level height as conductive pillar. The vertical projection of the conductive plate falls on spans of the at least two dies. 1. A semiconductor package , comprising:dies, disposed side by side, each die including a contact pad;a redistribution structure, disposed on the dies and electrically connecting the dies;a conductive structure, electrically connected to the contact pads of at least two dies of the dies, disposed on the redistribution structure, and extending over the at least two dies, wherein the conductive structure includes a conductive plate; andconnectors disposed on the redistribution structure, and at least one connector comprises a conductive pillar,wherein the conductive plate is at a same level height as the conductive pillar, and a vertical projection of the conductive plate falls on spans of the at least two dies.2. The semiconductor package of claim 1 , further comprising a solder cover disposed on the conductive plate.3. The semiconductor package of claim 2 , wherein a pattern of the solder cover matches a pattern of the conductive plate4. The semiconductor package of claim 1 , wherein the conductive plate and the conductive pillar are made of the same material.5. The semiconductor package of claim 1 , wherein the at least one connector further includes an under-bump seed layer and a solder bump claim 1 , and the under-bump seed layer claim 1 , the conductive pillar and the solder bump are sequentially stacked.6. The semiconductor ...

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Номер записи: 49
13-02-2020 дата публикации

High Speed Handling of Ultra-Small Chips by Selective Laser Bonding and Debonding

Номер: US20200051948A1
Автор: Budd Russell, Chen Qianwen, Dang Bing, Hung Li-Wen, Knickerbocker John, Nah Jae-Woong, Wen Bo
Принадлежит:

Techniques for high speed handling of ultra-small chips (e.g., micro-chips) by selective laser bonding and/or debonding are provided. In one aspect, a method includes: providing a first wafer including chips bonded to a surface thereof; contacting the first wafer with a second wafer, the second wafer including a substrate bonded to a surface thereof, wherein the contacting aligns individual chips with bonding sites on the substrate; and debonding the individual chips from the first wafer using a debonding laser having a small spot size of about 0.5 μm to about 100 μm, and ranges therebetween. A system is also provided that has digital cameras, a motorized XYZ-axis stage, and a computer control system configured to i) control a spot size of the at least one laser source and ii) adjust a positioning of the sample to align individual chips with a target area of the laser. 1. A system , comprising:at least one optical scannerat least one laser source optically connected to the at least one optical scanner, wherein the at least one laser source is configured to produce one or more of a bonding laser and a debonding laser;digital cameras optically connected to the at least one optical scanner;a motorized XYZ-axis stage;a sample on the motorized XYZ-axis stage, wherein the sample comprises a first wafer having chips bonded to a surface thereof in contact with a second wafer having a substrate bonded to a surface thereof; anda computer control system configured to i) control the at least one laser source, ii) read image information from the digital cameras to calculate alignment position; and iii) adjust a position of the motorized XYZ-axis stage to align individual chips with a target area of the at least one laser source.2. The system of claim 1 , wherein the at least one laser source comprises:a debonding laser source located on a first side of the sample; anda bonding laser source located on a second side of the sample opposite the first side.3. The system of claim 2 , ...

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Номер записи: 50
10-03-2022 дата публикации

DICING DIE ATTACH FILM, AND SEMICONDUCTOR PACKAGE USING THE SAME AND METHOD OF PRODUCING SEMICONDUCTOR PACKAGE

Номер: US20220077101A1
Автор: Morita Minoru
Принадлежит: FURUKAWA ELECTRIC CO., LTD.

A dicing die attach film, including an adhesive layer and a temporary-adhesive layer, the adhesive layer and the temporary-adhesive layer being laminated, 2. The dicing die attach film according to claim 1 , wherein when the adhesive layer is heated at a temperature elevation rate of 5° C./min from 25° C. claim 1 , an elastic modulus G′ before curing in a range of 25 to 80° C. is 10 kPa or more.3. The dicing die attach film according to claim 1 , wherein when the adhesive layer is heated at a temperature elevation rate of 5° C./min from 25° C. claim 1 , a melt viscosity at 120° C. is in a range of 500 to 10 claim 1 ,000 Pa·s.4. The dicing die attach film according to claim 1 , wherein the temporary-adhesive layer is energy ray-curable.5. A method of producing a semiconductor package claim 1 , comprising the steps of:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'a first step of thermocompression bonding the dicing die attach film according to to a back surface of a semiconductor wafer in which at least one semiconductor circuit is formed on a surface so that the adhesive layer is in contact with the back surface of the semiconductor wafer;'}a second step of dicing the semiconductor wafer and the adhesive layer simultaneously to obtain a semiconductor chip with an adhesive layer, the semiconductor chip with an adhesive layer including the semiconductor chip and the adhesive layer on the temporary-adhesive layer;a third step of removing the temporary-adhesive layer from the adhesive layer and thermocompression bonding the semiconductor chip with an adhesive layer and a wiring board via the adhesive layer; anda fourth step of thermally curing the adhesive layer.6. A semiconductor package wherein a semiconductor chip and a wiring board claim 1 , or semiconductor chips are bonded with a thermally curable component of the adhesive layer of the dicing die attach film according to . This application is a Continuation of PCT International Application No. PCT/JP2020/ ...

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Номер записи: 51
10-03-2022 дата публикации

Fan-out wafer-level packaging structure and method packaging the same

Номер: US20220077107A1
Автор: Hailin Zhao
Принадлежит: SJ Semiconductor Jiangyin Corp

The present disclosure provides a fan-out wafer-level packaging structure and a method for packaging the same. The structure includes: two or more semiconductor chips with a bonding pad, the semiconductor chips are arranged in a fan-out wafer array, and each of the semiconductor chips has an initial position, respectively; a plastic packaging layer, covering surfaces of the semiconductor chips and between the semiconductor chips, each of the semiconductor chips has an offset position, respectively, and the offset position has an offset distance relative to the initial position; a redistribution layer formed on the semiconductor chips, to realize interconnection between the semiconductor chips, the redistribution layer includes at least one first redistribution layer, the first redistribution layer is formed on a surface of the semiconductor chips and is aligned and in contact with the bonding pad of the semiconductor chips; and a metal bump formed on the redistribution layer.

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Номер записи: 52
10-03-2022 дата публикации

SHIFT CONTROL METHOD IN MANUFACTURE OF SEMICONDUCTOR DEVICE

Номер: US20220077108A1
Автор: Shih Ying-Ching, Tsou Hsien-Ju, Wu Chih-Wei
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A shift control method in manufacture of semiconductor device includes at least the following step. A plurality of semiconductor dies is encapsulated with an insulating encapsulation over a carrier, where at least portions of the plurality of semiconductor dies are shifted after encapsulating. A lithographic pattern is formed at least on the plurality of semiconductor die, where forming the lithographic pattern includes compensating for a shift in a position of the portions of the plurality of semiconductor dies. 1. A shift control method in manufacture of semiconductor device , comprising:encapsulating a plurality of semiconductor dies with an insulating encapsulation over a carrier, wherein at least portions of the plurality of semiconductor dies are shifted after encapsulating; andforming a lithographic pattern at least on the plurality of semiconductor die, wherein forming the lithographic pattern comprises compensating for a shift in a position of the portions of the plurality of semiconductor dies.2. The shift control method in manufacture of semiconductor device of claim 1 , further comprising:measuring the shift in the position of the portions of the plurality of semiconductor dies to result in a measuring result before forming the lithographic pattern; andfeeding back the measuring result to a lithographic tool utilized to form the lithographic pattern.3. The shift control method in manufacture of semiconductor device of claim 2 , wherein measuring the shift in the position of the portions of the plurality of semiconductor dies comprises:setting a reference coordinate to map the portions of the plurality of semiconductor dies, wherein an origin of the reference coordinate is aligned with one of the portions of the plurality of semiconductor dies.4. The shift control method in manufacture of semiconductor device of claim 1 , wherein an overlay offset is between a first target of one of the plurality of semiconductor dies and a second target of the one of the ...

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Номер записи: 53
01-03-2018 дата публикации

SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME

Номер: US20180061776A1
Автор: CHIANG Yuan-Feng, LU Po-Wei, YANG Peng
Принадлежит: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

A semiconductor device package comprises a semiconductor device, a first encapsulant surrounding the semiconductor device, a second encapsulant covering the semiconductor device and the first encapsulant, and a redistribution layer extending through the second encapsulant and electrically connected to the semiconductor device. 1. A semiconductor device package , comprising:a semiconductor device;a first encapsulant surrounding the semiconductor device;a second encapsulant covering the semiconductor device and the first encapsulant; anda redistribution layer extending through the second encapsulant and electrically connected to the semiconductor device.2. The semiconductor device package of claim 1 , wherein the second encapsulant is a planarization layer.3. The semiconductor device package of claim 1 , wherein the first encapsulant surrounds the second encapsulant.4. The semiconductor device package of claim 1 , wherein the redistribution layer is surrounded by the second encapsulant.5. The semiconductor device package of claim 1 , wherein a height of the first encapsulant is higher than a height of the semiconductor device.6. The semiconductor device package of claim 1 , wherein the first encapsulant comprises a tapered sidewall.7. The semiconductor device package of claim 6 , wherein the first encapsulant further comprises a first surface claim 6 , and wherein the semiconductor device is disposed directly on the first surface.8. The semiconductor device package of claim 6 , wherein the tapered sidewall of the first encapsulant surrounds the semiconductor device claim 6 , and forms an obtuse angle with a bottom surface of the semiconductor device.9. The semiconductor device package of claim 1 , wherein the first encapsulant comprises a first surface and a second surface substantially perpendicular to the first surface claim 1 , and wherein a roughness of the first surface is greater than a roughness of the second surface.10. The semiconductor device package of ...

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Номер записи: 54
01-03-2018 дата публикации

Semiconductor package and method for manufacturing the same

Номер: US20180061805A1
Автор: Chun-Jun ZHUANG, Hsu-Nan FANG
Принадлежит: Advanced Semiconductor Engineering Inc

A semiconductor package structure includes at least one semiconductor die, at least one conductive pillar, an encapsulant and a circuit structure. The semiconductor die has an active surface. The conductive pillar is disposed adjacent to the active surface of the semiconductor die. The encapsulant covers the semiconductor die and the conductive pillar. The encapsulant defines at least one groove adjacent to and surrounding the conductive pillar. The circuit structure is electrically connected to the conductive pillar.

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Номер записи: 55
01-03-2018 дата публикации

Semiconductor Device and Method of Forming SIP with Electrical Component Terminals Extending Out from Encapsulant

Номер: US20180061806A1
Автор: Jung JinHee, Kim OhHan, Yoon Insang
Принадлежит: STATS ChipPAC Pte. Ltd.

A semiconductor device has a carrier with an adhesive layer formed over the carrier. Alignment marks are provided for picking and placing the electrical component on the carrier or adhesive layer. An electrical component is disposed on the adhesive layer by pressing terminals of the electrical component into the adhesive layer. The electrical component can be a semiconductor die, discrete component, electronic module, and semiconductor package. A leadframe is disposed over the adhesive layer. A shielding layer is formed over the electrical component. An encapsulant is deposited over the electrical component. The carrier and adhesive layer are removed so that the terminals of the electrical component extend out from the encapsulant for electrical interconnect. A substrate includes a plurality of conductive traces. The semiconductor device is disposed on the substrate with the terminals of the electrical component in contact with the conductive traces. 1. A method of making a semiconductor device , comprising:providing a carrier;forming an adhesive layer over the carrier;disposing an electrical component on the adhesive layer by pressing terminals of the electrical component into the adhesive layer;depositing an encapsulant over the electrical component; andremoving the carrier to leave the terminals of the electrical component extending out from the encapsulant for electrical interconnect.2. The method of claim 1 , further including disposing a leadframe over the carrier or adhesive layer.3. The method of claim 1 , wherein the electrical component is selected from the group consisting of a semiconductor die claim 1 , discrete component claim 1 , electronic module claim 1 , and semiconductor package.4. The method of claim 1 , further including providing alignment marks for positioning the electrical component on the carrier or adhesive layer.5. The method of claim 1 , further including forming a shielding layer over the electrical component.6. The method of claim 1 , ...

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Номер записи: 56
04-03-2021 дата публикации

MICRO LED DISPLAY AND METHOD FOR MANUFACTURING THE SAME

Номер: US20210066243A1
Автор: KOO Jamyeong, Lee Byunghoon, Lee Changjoon, Min Sungyong
Принадлежит:

A method for manufacturing a micro light emitting diode (LED) display is provided. The method includes a first operation of applying a light-to-heat conversion layer to a first surface of a carrier substrate, a second operation of forming a first adhesive layer on the light-to-heat conversion layer a third operation of aligning a plurality of micro LED chips on the first adhesive layer, a fourth operation of positioning the plurality of micro LED chips above a circuit board at a first distance, a fifth operation of radiating a laser to the plurality of micro LED chips, and a sixth operation of causing the first adhesive layer to be deformed by the light-to-heat conversion layer, so that the plurality of micro LED chips are detached from the first adhesive layer to be attached to the circuit board. Various other embodiments are possible. 1. A method for manufacturing a micro light emitting diode (LED) display , the method comprising:a first operation of applying a light-to-heat conversion layer to a first surface of a carrier substrate;a second operation of forming a first adhesive layer on the light-to-heat conversion layer;a third operation of aligning a plurality of micro LED chips on the first adhesive layer;a fourth operation of positioning the plurality of micro LED chips above a circuit board at a first distance;a fifth operation of radiating a laser to the plurality of micro LED chips; anda sixth operation of causing the first adhesive layer to be deformed by the light-to-heat conversion layer, so that the plurality of micro LED chips are detached from the first adhesive layer to be attached to the circuit board.2. The method of claim 1 , wherein the light-to-heat conversion layer converts light energy into heat energy to cause deformation of the first adhesive layer to which each of the micro LED chips is attached.3. The method of claim 2 , wherein a deformed part of the first adhesive layer has a downward convex shape.4. The method of claim 1 , a conductive ...

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Номер записи: 57
17-03-2022 дата публикации

Semiconductor device package and a method of manufacturing the same

Номер: US20220084958A1
Автор: Peng Yang, Po-Wei LU, Yuan-Feng CHIANG
Принадлежит: Advanced Semiconductor Engineering Inc

A semiconductor device package comprises a semiconductor device, a first encapsulant surrounding the semiconductor device, a second encapsulant covering the semiconductor device and the first encapsulant, and a redistribution layer extending through the second encapsulant and electrically connected to the semiconductor device.

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Номер записи: 58
28-02-2019 дата публикации

Transferring device and transferring method of micro light emitting diode

Номер: US20190067510A1
Автор: Fenli ZHAO
Принадлежит: Shenzhen China Star Optoelectronics Technology Co Ltd

Provided are a transferring device and a transferring method of a micro light emitting diode. During the transferring process of the micro light emitting diode, the state of the magnetorheological fluid is controlled to achieve the physical connection of the micro light emitting diode and the transferring head to increase the acting force between the micro light emitting diode and the transferring head, thereby preventing damage during the transfer process of the micro light emitting diode for reducing the difficulty of transferring the light emitting diode. Moreover, with the simple electromagnetic device to control the connection and separation of the micro light emitting diode and the transferring head, the transferring operation of the micro light emitting diode is simplified to promote the transferring efficiency of the micro light emitting diode.

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Номер записи: 59
28-02-2019 дата публикации

SEMICONDUCTOR DEVICE AND MOUTING STRUCTURE OF SEMICONDUCTOR DEVICE

Номер: US20190067560A1
Автор: KIGOSHI Satohiro, MASAKI Takaaki, MIZUTA Shinsei
Принадлежит:

The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor element, a plurality of terminals, and a sealing resin. The semiconductor element has a front surface and a back surface. The front surface and the back surface face in opposite directions to each other in a thickness direction of the semiconductor element. The plurality of terminals are disposed at a distance from the semiconductor element and are electrically connected to the front surface. The sealing resin has a first surface facing in a same direction as the direction in which the front surface faces. Each of the plurality of terminals has a main surface exposed from the first surface. 120-. (canceled)21. A semiconductor device comprising:a semiconductor element;a first conductive member electrically connected to and spaced apart from the semiconductor element;a second conductive member electrically connected to the semiconductor element and spaced apart from the semiconductor element and the first conductive member; anda resin member covering the semiconductor element, at least a part of the first conductive member and at least a part of the second conductive member,wherein the resin member comprises a first surface, a second surface, a third surface and a fourth surface, the first surface and the second surface being disposed to face away from each other in a first direction, the third surface and the fourth surface being disposed to face away from each other in a second direction perpendicular to the first direction,the first conductive member comprises a first end portion, a second end portion, a third end portion and a fourth end portion, the first end portion being exposed from the first surface of the resin member, the second end portion being exposed from the second surface of the resin member, the third end portion being exposed from the third surface of the resin member, the fourth end portion being smaller in size measured in the first direction ...

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Номер записи: 60
11-03-2021 дата публикации

Methods and systems for manufacturing semiconductor devices

Номер: US20210074671A1
Автор: Benjamin L. McClain, Bret K. Street, Mark E. Tuttle, Wei Zhou
Принадлежит: Micron Technology Inc

A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.

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Номер записи: 61
07-03-2019 дата публикации

ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF

Номер: US20190074195A1
Автор: Hu Dyi-Chung
Принадлежит:

A method for manufacturing an electronic package includes: forming a middle patterned conductive layer having a first surface, a second surface opposite to the first surface, and a plurality of middle conductive pads; forming a first redistribution circuitry on the first surface, wherein the first redistribution circuitry includes a first patterned conductive layer having a plurality of first conductive elements, each first conductive element has a first conductive via and pad that form a T-shaped section, and each first conductive via connects the corresponding middle conductive pad and is tapering; and forming a second redistribution circuitry on the second surface, wherein the second redistribution circuitry includes a second patterned conductive layer having a plurality of second conductive elements, each second conductive element has a second conductive via and pad that form an inversed T-shaped section, and each second conductive via connects the corresponding middle conductive pad and is tapering. 1. A method for manufacturing an electronic package , comprising:forming a middle patterned conductive layer, wherein the middle patterned conductive layer has a first surface, a second surface opposite to the first surface, and a plurality of middle conductive pads;forming a first redistribution circuitry on the first surface of the middle patterned conductive layer, wherein the first redistribution circuitry comprising a first patterned conductive layer, the first patterned conductive layer has a plurality of first conductive elements, each of the first conductive elements has a first conductive pad and a first conductive via that form a T-shaped section, and each of the first conductive vias connects the corresponding middle conductive pad and is tapering facing towards the corresponding middle conductive pad; andforming a second redistribution circuitry on the second surface of the middle patterned conductive layer, wherein the second redistribution circuitry ...

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Номер записи: 62
07-03-2019 дата публикации

Target substrate with micro semiconductor structures

Номер: US20190074206A1
Автор: Hsien-Te Chen
Принадлежит: Ultra Display Technology Corp

A target substrate with micro semiconductor structures is manufactured by following steps of: attaching a pre-adhesive layer on a target substrate; patterning the adhesive layer to form a plurality of micro contact protrusions; and using the target substrate to perform a selective batch pickup procedure to pick up a plurality of micro semiconductor structures so as to form the target substrate with micro semiconductor structures.

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Номер записи: 63
05-03-2020 дата публикации

Integrated circuit (ic) device with multi-die integration

Номер: US20200075566A1
Автор: Stephen L. Morein
Принадлежит: Synaptics Inc

A method for manufacturing an integrated circuit (IC) device. A first IC wafer is diced to obtain a first superdie including a plurality of first die. A second IC wafer is diced to obtain a second superdie including a plurality of second die. The first superdie and the second superdie are placed on an interposer substrate to form at least part of a composite IC wafer, wherein each of the first die is aligned with a respective one of the second die in the composite IC wafer. The composite IC wafer is diced to obtain a plurality of IC devices, where each of the IC devices includes a respective one of the first die and the second die with which it is aligned.

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Номер записи: 64
18-03-2021 дата публикации

SHIFT CONTROL METHOD IN MANUFACTURE OF SEMICONDUCTOR DEVICE

Номер: US20210082870A1
Автор: Shih Ying-Ching, Tsou Hsien-Ju, Wu Chih-Wei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A shift control method in manufacture of semiconductor device includes at least the following step. An overlay offset of a first target of a semiconductor die and a second target of the semiconductor die is determined, where the second target is disposed on the first target. The semiconductor die is placed over a carrier, where placing the semiconductor die includes feeding back the overlay offset to result in a positional control of the semiconductor die. The semiconductor die is post processed to form a semiconductor device. Other shift control methods in manufacture of semiconductor device are also provided. 1. A shift control method in manufacture of semiconductor device , comprising:determining an overlay offset of a first target of a semiconductor die and a second target of the semiconductor die, wherein the second target is disposed on the first target;placing the semiconductor die over a carrier, wherein placing the semiconductor die comprises feeding back the overlay offset to result in a positional control of the semiconductor die; andpost processing the semiconductor die to form a semiconductor device.2. The shift control method in manufacture of semiconductor device of claim 1 , wherein determining the overlay offset of the first target and the second target is performed before singulating the semiconductor die from a semiconductor wafer.3. The shift control method in manufacture of semiconductor device of claim 1 , whereinthe first target is a conductive pad of the semiconductor die and the second target is a conductive connector of the semiconductor die electrically connected to the conductive pad, anddetermining the overlay offset of the first target and the second target comprises calculating a difference of relative position between the conductive connector and the conductive pad relative to a reference mark on the semiconductor die.4. The shift control method in manufacture of semiconductor device of claim 1 , wherein the overlay offset indicates a ...

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Номер записи: 65
31-03-2022 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE INCLUDING A FIRST SUB-PACKAGE STACKED ATOP A SECOND SUB-PACKAGE

Номер: US20220102328A1
Автор: Shih Shing-Yih
Принадлежит:

A semiconductor package includes a first sub-package and a second sub-package. The first sub-package is stacked atop the second sub-package. Each of the first sub-package and the second sub-package includes at least two first semiconductor dies, a second semiconductor die, a plurality of molding pieces, a bond-pad layer, a plurality of redistribution layers (RDLs) and a plurality of bumps. The bumps of the first sub-package are attached to the bond-pad layer of the second sub-package. 1. A method of manufacturing a semiconductor package , comprising:forming a first sub-package and a second sub-package, wherein forming each of the first and the second sub-package comprising following steps:(a) disposing at least two first semiconductor dies and a second semiconductor die disposed in between thereof on a first supporting substrate, wherein each of the first semiconductor dies comprises a plurality of through silicon vias (TSVs) substantially vertical to the first supporting substrate and each having a first end connecting to the first supporting substrate and a second end embedded in the first semiconductor die;(b) forming a molding layer covering the first supporting substrate, the first semiconductor dies and the second semiconductor die;(c) thinning the molding layer, the first semiconductor dies and the second semiconductor die, wherein the second ends of the TSVs are exposed from the first semiconductor dies, wherein upper surfaces of the TSVs, upper surfaces of the thinned molding layer, upper surfaces of the thinned first semiconductor dies and an upper surface of the thinned second semiconductor die are coplanar;(d) forming a bond-pad layer over the upper surfaces of the TSVs and the upper surface of the thinned second semiconductor die;(e) removing the first supporting substrate from lower surfaces of the TSVs, lower surfaces of the molding layer, lower surfaces of the first semiconductor dies and a lower surface of the second semiconductor die; and(f) ...

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Номер записи: 66
25-03-2021 дата публикации

METHODS AND SYSTEMS FOR MANUFACTURING SEMICONDUCTOR DEVICES

Номер: US20210091037A1
Автор: MCCLAIN BENJAMIN L., Street Bret K., Tuttle Mark E., Zhou Wei
Принадлежит:

A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process. 1. A method of manufacturing a semiconductor device , the method comprising:positioning a stopper wall on a wafer substrate between a first stage of a semiconductor bonding apparatus and a second stage of the semiconductor bonding apparatus, the first stage having a first pressing surface, and the second stage having a second pressing surface facing the first pressing surface of the first stage, wherein the stopper wall and the wafer substrate have a combined height measured from the second pressing surface in a direction normal to the first pressing surface, wherein the stopper wall at least partially surrounds a stack of semiconductor dies, wherein the semiconductor dies are positioned between the wafer substrate and the first stage of the semiconductor bonding apparatus, and wherein the stack of semiconductor dies has an unpressed stack height measured from the second pressing surface in a direction normal to the first pressing surface; andmoving one or both of the first and second stages of the semiconductor bonding apparatus toward each other until the first pressing ...

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Номер записи: 67
05-05-2022 дата публикации

Selective micro device transfer to receiver substrate

Номер: US20220139856A1
Автор: Ehsanollah Fathi, Gholamreza Chaji
Принадлежит: Vuereal Inc

A method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. Micro devices being attached to a donor substrate with a donor force. The donor substrate and receiver substrate are aligned and brought together so that selected micro devices meet corresponding contact pads. A receiver force is generated to hold selected micro devices to the contact pads on the receiver substrate. The donor force is weakened and the substrates are moved apart leaving selected micro devices on the receiver substrate. Several methods of generating the receiver force are disclosed, including adhesive, mechanical and electrostatic techniques.

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Номер записи: 68
05-05-2022 дата публикации

SELECTIVE MICRO DEVICE TRANSFER TO RECEIVER SUBSTRATE

Номер: US20220139857A1
Автор: Chaji Gholamreza, Fathi Ehsanollah
Принадлежит: VueReal Inc.

A method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. Micro devices being attached to a donor substrate with a donor force. The donor substrate and receiver substrate are aligned and brought together so that selected micro devices meet corresponding contact pads. A receiver force is generated to hold selected micro devices to the contact pads on the receiver substrate. The donor force is weakened and the substrates are moved apart leaving selected micro devices on the receiver substrate. Several methods of generating the receiver force are disclosed, including adhesive, mechanical and electrostatic techniques.

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Номер записи: 69
05-05-2022 дата публикации

METHOD AND SYSTEM FOR MANUFACTURING A SEMICONDUCTOR PACKAGE STRUCTURE

Номер: US20220139872A1
Автор: HONG Jheng-Yu, Hsu Chih-Hsiang, LEE PO-CHUN, LIU Che-Ting, LU Yu-Ting
Принадлежит: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

A method and a system for manufacturing a semiconductor package structure are provided. The method includes: (a) providing a package body including at least one semiconductor device encapsulated in an encapsulant; (b) providing a flattening force to the package body; (c) thinning the package body after (b); (d) attaching a film to the package body; and (e) releasing the flattening force after (d).

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Номер записи: 70
05-05-2022 дата публикации

Electronic device and manufacturing method thereof

Номер: US20220140185A1
Автор: Chun-Hsien Lin
Принадлежит: Innolux Corp

An electronic device is provided, the electronic device includes a driving substrate, the driving substrate includes a plurality of circular grooves and a plurality of rectangular grooves, a plurality of disc-shaped light-emitting units, at least one disc-shaped light-emitting unit is disposed in at least one circular groove, and the at least one disc-shaped light-emitting unit includes an alignment element positioned on a top surface of the at least one disc-shaped light-emitting unit, a diameter of the at least one disc-shaped light-emitting unit is defined as R, a diameter of the alignment element is defined as r, a width of at least one rectangular groove among the rectangular grooves is defined as w, and a height of the at least one rectangular groove is defined as H, and the at least one disc-shaped light-emitting unit and the at least one rectangular groove satisfy the condition of (R+r)/2>(w2+H2)1/2.

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Номер записи: 71
05-04-2018 дата публикации

METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE AND ELECTRONIC DEVICE

Номер: US20180096984A1
Автор: Pompl Stefan, Schmenn Andre, Sojka Damian, UMMINGER Katharina
Принадлежит:

A method for manufacturing an electronic device includes: providing a semiconductor carrier including first and second vertically integrated electronic structures laterally spaced apart from each other, an electrical connection layer disposed over a first side of the semiconductor carrier and electrically connecting the first and second vertically integrated electronic structures with each other; mounting the semiconductor carrier on a support carrier with the first side of the semiconductor carrier facing the support carrier; thinning the semiconductor carrier from a second side opposite the first side; and removing material of the semiconductor carrier in a separation region between the first and second vertically integrated electronic structures to separate a first semiconductor region of the first vertically integrated electronic structure from a second semiconductor region of the second vertically integrated electronic structure with the first and second vertically integrated electronic structures remaining electrically connected with each other via the electrical connection layer. 1. A method for manufacturing an electronic device , the method comprising:providing a semiconductor carrier, the semiconductor carrier comprising a first vertically integrated electronic structure and a second vertically integrated electronic structure laterally spaced apart from each other, an electrical connection layer disposed over a first side of the semiconductor carrier and electrically connecting the first vertically integrated electronic structure and the second vertically integrated electronic structure with each other;mounting the semiconductor carrier on a support carrier with the first side of the semiconductor carrier facing the support carrier;thinning the semiconductor carrier from a second side of the semiconductor carrier opposite the first side of the semiconductor carrier; andremoving material of the semiconductor carrier in a separation region between the first ...

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Номер записи: 72
28-03-2019 дата публикации

Method of Manufacturing a Release Film as Isolation Film in Package

Номер: US20190096700A1
Автор: Lin Jing-Cheng, Lu Szu-Wei, Shih Ying-Ching, Tsou Hsien-Ju, WANG Pu, Wu Chih-Wei
Принадлежит:

A method includes forming a release film over a carrier, forming a metal post on the release film, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, decomposing a first portion of the release film to separate a second portion of the release film from the carrier, and forming an opening in the release film to expose the metal post. 1. A package of integrated circuits , the package comprising:an encapsulating material;a through-via penetrating through the encapsulating material;a Light-To-Heat-Conversion (LTHC) coating material contacting the through-via and the encapsulating material; anda conductive feature penetrating through the LTHC coating material.2. The package of claim 1 , wherein the LTHC coating material is configured to decompose under heat of a light.3. The package of claim 1 , wherein the conductive feature comprises a solder region.4. The package of further comprising:a device die; anda die-attach film adhering the device die to the LTHC coating material, wherein the device die and the die-attach film are encapsulated by the encapsulating material.5. The package of claim 1 , wherein the LTHC coating material comprises a polymer and carbon black particles.6. The package of claim 5 , wherein the polymer comprises acrylic.7. The package of claim 5 , wherein the LTHC coating material further comprises silicon filler.8. The package of claim 1 , wherein the LTHC coating material comprises a surface having marks with a shape of parallel strips.9. The package of claim 1 , wherein the LTHC coating material comprises a first plurality of portions and a second plurality of portions allocated in an alternating layout claim 1 , wherein the first plurality of portions are thinner than the second plurality of portions.10. A package comprising:a device die;a die-attach film;a Light-To-Heat- ...

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Номер записи: 73
28-03-2019 дата публикации

SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME

Номер: US20190096816A1
Автор: Chen Chin-Liang, HO KUAN-LIN, LIANG Yu-Min, Yu Chi-Yang
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor packages and methods of forming the same are disclosed. The semiconductor package includes a plurality of chips, a first molding compound, a first redistribution structure, a second molding compound and a second redistribution structure. The first molding compound encapsulates the chips. The first redistribution structure is disposed over the plurality of chips and the first molding compound. The second molding compound surrounds the first molding compound. The second redistribution structure is disposed over the first redistribution structure, the first molding compound and the second molding compound. 1. A semiconductor package , comprising:a plurality of chips, wherein one of the plurality of chips comprises a protection layer;a first molding compound, encapsulating the plurality of chips, and a material of the protection layer is different from a material of the first molding compound;a first redistribution structure, disposed over the plurality of chips and the first molding compound, wherein the first redistribution structure is in contact with the protection layer;a second molding compound, surrounding the first molding compound, wherein the second molding compound covers the first redistribution structure; anda second redistribution structure, disposed over the first redistribution structure, the first molding compound and the second molding compound.2. The semiconductor package of claim 1 , wherein the second molding compound is directly contact with the first molding compound claim 1 , and an interface is formed between the first molding compound and the second molding compound.3. The semiconductor package of claim 1 , wherein the second molding compound is not disposed between the plurality of chips.4. The semiconductor package of claim 1 , wherein the first redistribution structure comprises a plurality of connecting pads claim 1 , and the plurality of connecting pads is directly contact with the second redistribution structure.5. The ...

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Номер записи: 74
28-03-2019 дата публикации

INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF

Номер: US20190096840A1
Автор: Ang Ai-Tee, Chen Shing-Chao, Hsieh Ching-Hua, Lin Chih-Wei, Lin Ching-Yao
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

An integrated fan-out package includes a first and second dies, an encapsulant, and a redistribution structure. The first and second dies respectively has an active surface, a rear surface opposite to the active surface, and conductive posts on the active surface. The first and second dies are different types of dies. The active and rear surfaces of the first die are respectively levelled with the active and rear surfaces of the second die. Top surfaces of the conductive posts of the first and second dies are levelled. The conductive posts of the first and second dies are wrapped by same material. The encapsulant encapsulates sidewalls of the first and second dies. A first surface of the encapsulant is levelled with the active surfaces. The second surface of the encapsulant is levelled with the rear surfaces. The redistribution structure is disposed over the first die, the second die, and the encapsulant. 15-. (canceled)6. A manufacturing method of an integrated fan-out package , comprising:providing a carrier having an adhesive layer formed thereon;providing a first die and a second die on the adhesive layer, wherein a height of the first die is different from a height of the second die, the first die has first conductive posts and the second die has second conductive posts, the first conductive posts have substantially a same height, and the second conductive posts have substantially a same height;pressing the first die and the second die against the adhesive layer to make the active surfaces of the first die and the second die be in direct contact with the adhesive layer and the first and second conductive posts be submerged into the adhesive layer;curing the adhesive layer;forming an encapsulant to encapsulate the first die and the second die;removing the carrier from the adhesive layer;reducing heights of the first and second conductive posts and removing at least a portion of the adhesive layer such that the first and second conductive posts are laterally ...

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Номер записи: 75
28-03-2019 дата публикации

Micro device transfer head heater assembly and method of transferring a micro device

Номер: US20190096846A1
Автор: Andreas Bibl, Hsin-Hua Hu, Hung-fai Stephen Law, John A. Higginson
Принадлежит: Apple Inc

A method of transferring a micro device and an array of micro devices are disclosed. A carrier substrate carrying a micro device connected to a bonding layer is heated to a temperature below a liquidus temperature of the bonding layer, and a transfer head is heated to a temperature above the liquidus temperature of the bonding layer. Upon contacting the micro device with the transfer head, the heat from the transfer head transfers into the bonding layer to at least partially melt the bonding layer. A voltage applied to the transfer head creates a grip force which picks up the micro device from the carrier substrate.

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Номер записи: 76
26-03-2020 дата публикации

Ir assisted fan-out wafer level packaging using silicon handler

Номер: US20200098638A1
Автор: Bing Dang, Jeffrey D. Gelorme, John U. Knickerbocker
Принадлежит: International Business Machines Corp

A support structure for use in fan-out wafer level packaging is provided that includes, a silicon handler wafer having a first surface and a second surface opposite the first surface, a release layer is located above the first surface of the silicon handler wafer, and a layer selected from the group consisting of an adhesive layer and a redistribution layer is located on a surface of the release layer. After building-up a fan-out wafer level package on the support structure, infrared radiation is employed to remove (via laser ablation) the release layer, and thus remove the silicon handler wafer from the fan-out wafer level package.

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Номер записи: 77
04-04-2019 дата публикации

STACKED SEMICONDUCTOR PACKAGE ASSEMBLIES INCLUDING DOUBLE SIDED REDISTRIBUTION LAYERS

Номер: US20190103386A1
Автор: CHEN William T., Huang Chih-Yi, Hung Chih-Pin, HUNT JOHN RICHARD, Wang Chen-Chao
Принадлежит: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module. 1. A semiconductor device package comprising:a bottom electronic device having an active surface;an interposer module including a plurality of conductive vias;a top electronic device having an active surface and disposed above the bottom electronic device and above the interposer module; anda double sided redistribution layer (RDL) structure disposed between the bottom electronic device and the top electronic device, the active surface of the bottom electronic device facing toward the double sided RDL structure, the active surface of the top electronic device facing toward the double sided RDL structure, the double sided RDL structure electrically connecting the active surface of the bottom electronic device to the active surface of the top electronic device, the double sided RDL structure electrically connecting the active surface of the top electronic device to the interposer module.2. The semiconductor device package of claim 1 , further comprising:a second RDL structure disposed below the bottom electronic device and below the ...

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Номер записи: 78
21-04-2016 дата публикации

METHOD OF FORMING A CHIP ASSEMBLY AND CHIP ASSEMBLY

Номер: US20160111395A1
Автор: HEINRICH Alexander
Принадлежит:

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier. 1. A method of forming a chip assembly , the method comprising:forming a plurality of cavities in a carrier;arranging a die attach liquid in each of the cavities;arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier;evaporating the die attach liquid; andafter the evaporating the die attach liquid, fixing the plurality of chips to the carrier.2. The method of claim 1 , further comprising:holding the plurality of chips, by a holding force, in respective positions in which they are arranged.3. The method of claim 2 ,wherein the holding force is provided by the die attach liquid.4. The method of claim 1 ,wherein the evaporating of the die attach liquid comprises heating the chip assembly.5. The method of claim 1 ,wherein the die attach liquid evaporates essentially completely.6. The method of claim 1 ,wherein the die attach liquid comprises an organofluorine compound.7. The method of claim 1 ,wherein the die attach liquid comprises a hydrofluoroether.8. The method of claim 1 ,wherein the die attach liquid comprises an alcohol or secondary alcohol9. The method of claim 1 ,wherein the fixing the plurality of chips to the carrier comprises heating the chip assembly.10. The method of claim 1 ,wherein the fixing the plurality of chips to ...

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Номер записи: 79
21-04-2016 дата публикации

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

Номер: US20160111410A1
Автор: Byung Tai Do, Linda Pei Ee CHUA, Reza A. Pagaila, Seng Guan Chow, Seung Uk Yoon
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

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Номер записи: 80
21-04-2016 дата публикации

Method for transferring light-emitting elements onto a package substrate

Номер: US20160111605A1
Автор: Tzu-Yang Lin, Yu-Chu Li, Yu-Hung Lai
Принадлежит: PlayNitride Inc

A method for transferring light-emitting elements onto a package substrate includes: providing a light-emitting unit including a supporting substrate and a plurality of light-emitting elements, each of the light-emitting elements being removably connected to the supporting substrate and having a surface opposite to the supporting substrate; disposing the light-emitting unit spacingly above a package substrate in such a manner that the surface of each of the light-emitting elements faces the package substrate; and disconnecting the light-emitting elements from the supporting substrate to allow the light-emitting elements to fall onto the package substrate by gravity, so as to connect the light-emitting elements with the package substrate in a non-contact transferring method.

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Номер записи: 81
02-06-2022 дата публикации

Adsorption device, transferring system having same, and transferring method using same

Номер: US20220172970A1
Автор: Hirohisa Tanaka, Po-Liang Chen, Yasunori Shimada, Yung-Fu Lin
Принадлежит: Century Technology Shenzhen Corp Ltd

A transferring method includes providing an adsorption device, using the adsorption device to attract and hold a plurality of light emitting diodes (LEDs), providing a target substrate with a plurality of spots of anisotropic conductive adhesive on a surface of the target substrate; moving the adsorption device or the target substrate wherein each of the plurality of LEDs adsorbed by the adsorption device becomes in contact with one of the plurality of spots of anisotropic conductive adhesive; and curing the plurality of spots of anisotropic conductive adhesive on the target substrate and moving away the adsorption device.

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Номер записи: 82
19-04-2018 дата публикации

FULLY MOLDED MINIATURIZED SEMICONDUCTOR MODULE

Номер: US20180108606A1
Автор: Olson Timothy L., Scanlan Christopher M.
Принадлежит:

A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imageable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT). 1. A semiconductor module , comprising: a semiconductor die comprising contact pads,', 'conductive pillars coupled to the contact pads and extending to the planar surface, and', 'an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion;, 'a fully molded base portion comprising a planar surface that further comprisesa build-up interconnect structure comprising a routing layer disposed over the fully molded base portion;a photo-imageable solder mask material disposed over the routing layer and comprising openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars; anda SMD component electrically coupled to the SMD land pads with surface mount technology (SMT).2. The semiconductor module of claim 1 , wherein the photo-imageable solder mask comprises at least one of epoxy solder resist claim 1 , ...

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Номер записи: 83
19-04-2018 дата публикации

APPARATUSES AND METHODS FOR FORMING DIE STACKS

Номер: US20180108645A1
Автор: Koopmans Michel
Принадлежит: MICRON TECHNOLOGY, INC.

Apparatuses and methods for forming die stacks are disclosed herein. An example method includes dispensing a temporary adhesive onto a substrate, placing a base die onto the temporary adhesive, curing the temporary adhesive, forming a die stack that includes the base die, activating a release layer disposed on the substrate, wherein the release layer is between the substrate and the temporary adhesive, removing the die stack from the substrate, and removing the temporary adhesive from the die stack. 1. A method comprising:temporarily adhering a base die onto a release layer of a process substrate;stacking a plurality of die on the base die; andremoving the process substrate from the base die.2. The method of claim 1 , wherein removing the process substrate from the base die comprises separating the release layer of the process substrate from the base die.3. The method of claim 2 , wherein separating the release layer of the process substrate from the base die comprises exposing the release layer to a laser emission.4. The method of claim 3 , wherein the laser emission corresponds to an emission in the UV claim 3 , visible claim 3 , or infrared range of the electromagnetic spectrum.5. The method of claim 2 , wherein separating the release layer of the process substrate from the base die comprises exposing the release layer to radiation.6. The method of claim 5 , wherein the process substrate is transparent to radiation exposed to the temporary adhesive.7. The method of claim 1 , further comprising:placing the process substrate over an opening of a process carrier.8. The method of claim 1 , wherein the base die comprises a logic die and the plurality of die comprises a plurality of memory die.9. A method claim 1 , comprising:dicing a process substrate including a release layer;activating the release layer disposed on the process substrate to release a die stack from the process substrate; andremoving the process substrate from the die stack.10. The method of wherein ...

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Номер записи: 84
02-04-2020 дата публикации

METHOD FOR MANUFACTURING A CHIP PACKAGE

Номер: US20200105714A1
Автор: Lai Chien-Chih, LIN Hung-Wen
Принадлежит:

A method for manufacturing chip package is disclosed. The method includes providing a wafer having an upper surface and a lower surface opposite thereto, in which the wafer comprises a plurality of conductive pads disposed on the upper surface; dicing the upper surface of the wafer to form a plurality of trenches; forming a patterned photoresist layer on the upper surface and in the trenches; forming a plurality of conductive bumps disposed correspondingly on the conductive pads; thinning the wafer from the lower surface toward the upper surface, such that the patterned photoresist layer in the trenches is exposed from the lower surface; forming an insulating layer under the lower surface; and dicing the patterned photoresist layer and the insulating layer along each trench to form a plurality of chip packages. 1. A method of manufacturing chip package , comprising steps of:providing a wafer having an upper surface and a lower surface opposite thereto, wherein the wafer comprises a plurality of conductive pads disposed on the upper surface;dicing the upper surface of the wafer to form a plurality of trenches;forming a patterned photoresist layer on the upper surface and in the trenches;forming a plurality of conductive bumps disposed correspondingly on the conductive pads;thinning the wafer from the lower surface toward the upper surface, such that the patterned photoresist layer in the trenches is exposed from the lower surface;forming an insulating layer under the lower surface; anddicing the patterned photoresist layer and the insulating layer along each trench to form a plurality of chip packages.2. The method of claim 1 , after the step of forming the conductive bumps claim 1 , further comprising forming a surface treatment layer on the conductive bumps.3. The method of claim 1 , after the step of forming the conductive bumps and before the step of thinning the wafer claim 1 , further comprising:forming an adhesive layer covering the patterned photoresist layer ...

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Номер записи: 85
26-04-2018 дата публикации

METHOD FOR SIMULTANEOUSLY BONDING MULTIPLE CHIPS OF DIFFERENT HEIGHTS ON FLEXIBLE SUBSTRATES USING ANISOTROPIC CONDUCTIVE FILM OR PASTE

Номер: US20180114772A1
Автор: Krusor Brent S., Mei Ping
Принадлежит: PALO ALTO RESEARCH CENTER INCORPORATED

The present application provides methods, systems and devices for simultaneously bonding multiple semiconductor chips of different height profiles on a flexible substrate. 1. A method for substantially simultaneously bonding multiple semiconductor chips of different height profiles on a flexible substrate comprising:providing a flexible substrate with printed conductive traces;placing an anisotropic conductive adhesive (ACA) over at least portions of the printed conductive traces of the flexible substrate, the ACA including a thermosetting adhesive and conductive spherical elements;tacking the ACA in place by application of heat and pressure for a predetermined time by use of a heat generating mechanism and a pressure generating mechanism;positioning and orientating a first side of each of multiple semiconductor chips to align with selected locations of the printed conductive traces of the flexible substrate lying under the ACA by use of a positioning and orienting mechanism, wherein at least one of the multiple semiconductor chips has a height profile different from at least one other one of the multiple semiconductor chips;curing the thermosetting adhesive of the ACA by applying heat and pressure by use of a curing mechanism, wherein the pressure is applied to a second side of each of the multiple semiconductor chips, the applying of the pressure pressing and deforming the conductive spherical elements of the ACA, wherein electrical contact is made between the semiconductor chips and at least portions of the printed conductive traces.2. The method according to wherein the application of pressure occurs on a second side of each of the multiple semiconductor chips opposite the first side of each of the multiple semiconductor chips.3. The method according to wherein applying the pressure includes using a pressure applying device having a deformable bonding head to provide the application of pressure to the second side of each of the multiple semiconductor chips claim ...

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Номер записи: 86
26-04-2018 дата публикации

SEMICONDUCTOR LASER DEVICE, PHOTOELECTRIC CONVERTER, AND OPTICAL INFORMATION PROCESSING UNIT

Номер: US20180115138A1
Автор: Ootorii Hiizu
Принадлежит:

A semiconductor laser device that enables flip-chip assembly by having an embedding section around a mesa section, and that has an improved emission lifetime, as well as a photoelectric converter and an optical information processing unit each having such a semiconductor laser device. The semiconductor laser device includes: a mesa section including an active layer, and having a first electrode on a top surface; an embedding section covering the mesa section, and having a first connection aperture that reaches the first electrode; and a first wiring provided on the embedding section overlaying the first connection aperture, the first wiring being electrically connected to the first electrode through the first connection aperture. 110.-. (canceled)11. A surface emitting semiconductor device comprising:a semiconductor structure having a mesa structure, the semiconductor structure comprising an active layer and a DBR layer;a first electrode on a top surface of the mesa structure;a first insulating film on a side surface and the top surface of the mesa structure, and having a first aperture;a second insulating film on the side surface and the top surface of the mesa structure, the first insulating film being between the mesa structure and the second insulating film, the second insulating film having a second aperture;a first wiring on the second insulating film, the first wiring (a) having a length along a first direction equal to or longer than a radius of the mesa structure along the first direction, (b) being in the first aperture and the second aperture, (c) extending across opposite sides of the second aperture along the first direction in a first cross section, and (d) being electrically connected to the mesa structure through the first aperture and the second aperture; anda second wiring including:(e) a first portion electrically connected to the semiconductor structure at a first contact region and (f) a second portion electrically connected to the semiconductor ...

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Номер записи: 87
09-06-2022 дата публикации

Method for Forming Chip Packages and a Chip Package

Номер: US20220181295A1
Автор: Li Weiping
Принадлежит:

The present application provides a method for forming a chip package and a chip package. The method comprises mounting at least one chipset including at least first and second chips on a carrier with front surface of the chips face away from the carrier; attaching an interconnection device to the front surfaces of the first and second chips to enable electrically connections between the chips; forming a molded encapsulation layer whereby the first chip, the second chip and the interconnection device are embedded or partially embedded in the molded encapsulation layer; thinning one side of the molded encapsulation layer away from the carrier to expose first bumps on the first and second chips; forming second bumps on a surface of one side of the molded encapsulation layer where the first bumps are exposed; and removing the carrier. Thus, a flexible, efficient and low-cost packaging scheme is provided for multi-chip connection. 1. A method of forming a chip package , comprising:providing a carrier and at least one chipset, wherein each chipset comprises at least a first chip and a second chip, wherein front surfaces of the first chip and the second chip are provided with first bumps;mounting the first chip and the second chip in each chipset on the surface of the carrier with the front surfaces of the first chip and the second chip facing away from the carrier;attaching an interconnect device to the front surfaces of the first and second chips to enable the first chip in each chipset to be electrically connected to the second chip through the interconnect device;forming a molded encapsulation layer, wherein the first chip, the second chip and the interconnection device are embedded or partially embedded in the molded encapsulation layer;thinning one side of the molded encapsulation layer facing away from the carrier to expose some of the first bumps of the first chip and the second chip;forming second bumps on a surface of one side of the molded encapsulation layer ...

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Номер записи: 88
09-06-2022 дата публикации

Method for Forming Chip Packages and a Chip Package

Номер: US20220181296A1
Автор: Li Weiping
Принадлежит:

The present application provides a method for forming chip packages and a chip package. The method comprises arranging a plurality of interconnect devices at intervals on a surface of a carrier and assembling a plurality of chipsets over the interconnect devices. Each chipset comprises at least two chips electrically connected through an interconnect device. A front surface of each chip facing the carrier is provided with a plurality of first bumps. The method further comprises forming a molded package layer whereby the plurality of chipsets and the plurality of interconnect devices are embedded in the molded package layer; removing the carrier and thinning the molded package layer to expose the first bumps; forming second bumps on the surface on one side of the molded package layer where the first bumps are exposed; and dicing the molded package layer to obtain a plurality of package units. Thus, a flexible and low-cost packaging scheme is provided for multi-chip interconnection. 1. A method of forming a package , comprising:arranging a plurality of interconnect devices at intervals on a surface of a carrier, each interconnect device having a first side facing away from the carrier;assembling a plurality of chipsets over the plurality of interconnect devices, wherein each chipset includes at least two chips that are jointed by a corresponding interconnect device on the first side of the corresponding interconnect device whereby the at least two chips are electrically interconnected through the corresponding interconnect device, and wherein a front surface of each chip in each chipset faces the carrier and is provided with a plurality of first bumps;forming a molded package layer around the plurality of chipsets, wherein the plurality of chipsets and the plurality of interconnect devices are embedded in the molded package layer;removing the carrier and thinning the molded package layer to expose some of the plurality of first bumps;forming a second bump on the ...

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Номер записи: 89
09-06-2022 дата публикации

Chip Interconnecting Method, Interconnect Device and Method for Forming Chip Packages

Номер: US20220181297A1
Автор: Weiping Li
Принадлежит: Yibu Semiconductor Co Ltd

The present disclosure provides a chip interconnecting method, an interconnect device and a method for forming a chip interconnection package. The method comprises arranging at least one chipset on a carrier, each chipset including at least a first chip and a second chip. A contact surface (or diameter) of each of the first bumps is smaller than that of any of the second bumps. The method further comprises attaching an interconnect device to the first chip and the second chip, the interconnect device including first pads for bonding to corresponding bumps on the first chip and second pads for bonding to corresponding bumps on the second chip. Attaching the interconnect device includes aligning the plurality of first pads with the corresponding bumps on the first chip whereby the plurality of second pads are self-aligned for bonding to the plurality of second bumps.

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Номер записи: 90
18-04-2019 дата публикации

SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF

Номер: US20190115319A1
Автор: Hiner David, Huemoeller Ronald, KELLY MICHAEL
Принадлежит:

A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a connect die that routes electrical signals between a plurality of other semiconductor die. 1. An electronic device comprising:a first signal redistribution structure;a first vertical interconnection structure on a first side of the first signal redistribution structure;a connect die comprising a back side and a front side, wherein the back side is facing and is coupled to the first side of the first signal redistribution structure;a first connect die interconnection structure coupled to the front side of the connect die;a second signal redistribution structure on the first vertical interconnection structure and on the first connect die interconnection structure; and a first interconnection structure coupled to the second signal redistribution structure, such that the first interconnection structure of the first electronic component is electrically coupled to the first vertical interconnection structure through at least the second signal redistribution structure; and', 'a second interconnection structure coupled to the second signal redistribution structure, such that the second interconnection structure of the first electronic component is electrically coupled to the first connect die interconnection structure through at least the second signal redistribution structure., 'a first electronic component comprising2. The electronic device of claim 1 , comprising:a second vertical interconnection structure on the first side of the first signal redistribution structure;a second connect die interconnection structure coupled to the front side of the connect die, wherein the second connect die interconnection structure is electrically coupled to the first connect die interconnection structure; and a first interconnection structure ...

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Номер записи: 91
09-04-2020 дата публикации

Semiconductor package

Номер: US20200111763A1
Автор: Ji-Hoon Kim, Ji-Seok HONG
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor package includes: a lower semiconductor chip including a first semiconductor substrate, which includes a first semiconductor device on an active surface thereof and a protrusion defined by a recess region on an inactive surface thereof opposite to the active surface, a plurality of external connecting pads on a bottom surface of the first semiconductor substrate, and a plurality of through-electrodes electrically connected to the plurality of external connecting pads; and at least one upper semiconductor chip stacked on the protrusion of the lower semiconductor chip and electrically connected to the plurality of through-electrodes, the at least one upper semiconductor chip including a second semiconductor substrate which includes a second semiconductor device on an active surface thereof.

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Номер записи: 92
09-04-2020 дата публикации

LIGHT EMITTING DEVICE

Номер: US20200111932A1
Автор: IWAKURA Daisuke, KURAMOTO Masafumi
Принадлежит: NICHIA CORPORATION

A light emitting element includes a light emitting element having a first face on which a first electrode and a second electrode are provided. A wavelength converting material covers a whole of the light emitting element except for the first face such that a surface of the wavelength converting material and the first face constitute a substantially flat plane. A first electrically conductive material is provided on the first face and the surface of the wavelength converting material to be electrically connected to the first electrode. A second electrically conductive material is provided on the first face and the surface of the wavelength converting material to be electrically connected to the second electrode. An insulating member is disposed on the first electrically conductive material, the second electrically conductive material, and the first face between the first electrode and the second electrode. 1. A light emitting device comprising:a light emitting element having a first face on which a first electrode and a second electrode are provided;a wavelength converting material covering a whole of the light emitting element except for the first face such that a surface of the wavelength converting material and the first face constitute a substantially flat plane;a first electrically conductive material provided on the first face and the surface of the wavelength converting material to be electrically connected to the first electrode;a second electrically conductive material provided on the first face and the surface of the wavelength converting material to be electrically connected to the second electrode; andan insulating member disposed on the first electrically conductive material, the second electrically conductive material, and the first face between the first electrode and the second electrode.2. The light emitting device according to claim 1 , wherein the substantially flat plane has a level difference between the first face and the surface of the waveform ...

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Номер записи: 93
13-05-2021 дата публикации

Batch Diffusion Soldering and Electronic Devices Produced by Batch Diffusion Soldering

Номер: US20210143123A1
Автор: HEINRICH Alexander, Roesl Konrad, Trunov Kirill, Unrau Arthur
Принадлежит:

A method of batch soldering includes: forming a soldered joint between a metal region of a first semiconductor die and a metal region of a substrate using a solder preform via a soldering process which does not apply pressure directly to the first semiconductor die, the solder preform having a maximum thickness of 30 μm and a lower melting point than the metal regions; setting a soldering temperature of the soldering process so that the solder preform melts and fully reacts with the metal region of the first semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the preform melting point and the soldering temperature; and soldering a second semiconductor die to the same or different metal region of the substrate, without applying pressure directly to the second semiconductor die. 1. A method of batch soldering , comprising:forming a first soldered joint between a metal region of a first semiconductor die and a first metal region of a substrate using a first solder preform via a soldering process which does not apply pressure directly to the first semiconductor die, the first solder preform having a maximum thickness of 30 μm and a lower melting point than both the metal region of the first semiconductor die and the first metal region of the substrate;setting a soldering temperature of the soldering process so that the first solder preform melts and fully reacts with the metal region of the first semiconductor die and the first metal region of the substrate to form one or more intermetallic phases throughout the entire first soldered joint, each of the one or more intermetallic phases having a melting point above the melting point of the preform and the soldering temperature; andsoldering a second semiconductor die to the first or different metal region of the substrate, without applying pressure directly to the second semiconductor ...

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Номер записи: 94
24-07-2014 дата публикации

Semiconductor laser device, photoelectric converter, and optical information processing unit

Номер: US20140203196A1
Автор: Hiizu Ootorii
Принадлежит: Sony Corp

A semiconductor laser device that enables flip-chip assembly by having an embedding section around a mesa section, and that has an improved emission lifetime, as well as a photoelectric converter and an optical information processing unit each having such a semiconductor laser device. The semiconductor laser device includes: a mesa section including an active layer, and having a first electrode on a top surface; an embedding section covering the mesa section, and having a first connection aperture that reaches the first electrode; and a first wiring provided on the embedding section overlaying the first connection aperture, the first wiring being electrically connected to the first electrode through the first connection aperture.

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Номер записи: 95
25-04-2019 дата публикации

PRINTING MODULE, PRINTING METHOD AND SYSTEM OF FORMING A PRINTED STRUCTURE

Номер: US20190123015A1
Автор: CHENG Li-Hui, Lin Jing-Cheng, PAN CHIH-CHIEN, Tsai Po-Hao
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A printing module, printing method and system of forming a printed structure are provided. The printing module includes a first printing dispenser operable to dispense a first material, a second printing dispenser operable to dispense a second material, a first curing unit, a second curing unit and a third curing unit. The first, the second and the third curing units each is operable to irradiate a light capable of curing the first and second materials and are alternately arranged with the first and second printing dispensers along a line. The first and second printing dispensers and the first, second and third curing units are simultaneously movable along the line. During the second curing unit and one of the first curing unit and the third curing unit are operable to irradiate the light, the other of the first curing unit and the third curing unit is off. 1. A printing module , comprising:a first printing dispenser operable to dispense a first material;a second printing dispenser operable to dispense a second material; anda first curing unit, a second curing unit and a third curing unit each being operable to irradiate a light capable of curing the first and second materials, wherein the first, second and third curing units are alternately arranged with the first and second printing dispensers along a line, the first printing dispenser is sandwiched between the first and second curing units, and the second printing dispenser is sandwiched between the second and third curing units,wherein the first and second printing dispensers and the first, second and third curing units are simultaneously movable along the line, andwherein during the second curing unit and one of the first curing unit and the third curing unit are operable to irradiate the light, the other of the first curing unit and the third curing unit is off.2. The printing module of claim 1 , wherein when the printing module moves in a first direction along the line claim 1 , the first curing unit is off ...

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Номер записи: 96
01-09-2022 дата публикации

WAFER LEVEL CHIP SCALE SEMICONDUCTOR PACKAGE

Номер: US20220278076A1
Автор: Bobde Madhur, Chen Bo, Wang Long-Ching, Xue Yan Xun
Принадлежит: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

A wafer level chip scale semiconductor package comprises a device semiconductor layer, a backside metallization layer, a film laminate layer, and a metal layer. The device semiconductor layer comprises a plurality of metal electrodes disposed on a front surface of the device semiconductor. Each side surface of the backside metallization layer is coplanar with a corresponding side surface of the device semiconductor layer. Each side surface of the metal layer is coplanar with a corresponding side surface of the film laminate layer. A surface area of a back surface of the backside metallization layer is smaller than a surface area of a front surface of the metal layer. 1. A wafer level chip scale semiconductor package comprising:a device semiconductor layer comprising a plurality of metal electrodes disposed on a front surface of the device semiconductor;a backside metallization layer attached to a back surface of the device semiconductor layer; anda metal layer attached through a film laminate layer to the backside metallization layer;wherein each side surface of the backside metallization layer is coplanar with a corresponding side surface of the device semiconductor layer;wherein each side surface of the metal layer is coplanar with a corresponding side surface of the film laminate layer; andwherein a surface area of a back surface of the backside metallization layer is smaller than a surface area of a front surface of the metal layer.2. The wafer level chip scale semiconductor package of further comprising:a marking film coating layer overlaying the metal layer.3. The wafer level chip scale semiconductor package of claim 2 ,wherein each side surface of the metal layer is coplanar with a corresponding side surface of the marking film coating layer.4. The wafer level chip scale semiconductor package of claim 3 ,wherein the surface area of the front surface of the metal layer extends beyond all edges of the device semiconductor layer. This Patent Application is a ...

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Номер записи: 97
02-05-2019 дата публикации

Micro-led display panel and manufacturing method thereof

Номер: US20190131282A1
Автор: Pei-Hsin Chen, Yi-Ching Chen, Ying-Tsang Liu, Yu-Chu Li
Принадлежит: PlayNitride Inc

A micro-LED display panel including a substrate, an anisotropic conductive film, and a plurality of micro-LEDs is provided. The anisotropic conductive film is disposed on the substrate. The micro-LEDs and the anisotropic conductive film are disposed at the same side of the substrate, and the micro-LEDs are electrically connected to the substrate through the anisotropic conductive film. Each of the micro-LEDs includes an epitaxial layer and an electrode layer electrically connected to the epitaxial layer, and the electrode layers comprises a first electrode and a second electrode which are located between the substrate and the corresponding epitaxial layer. A ratio of a thickness of each of the electrode layers to a thickness of the corresponding epitaxial layer ranges from 0.1 to 0.5, and a gap between the first electrode and the second electrode of each of the micro-LEDs is in a range of 1 μm to 30 μm.

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Номер записи: 98
23-04-2020 дата публикации

MANUFACTURING METHOD OF PACKAGE STRUCTURE

Номер: US20200126815A1
Автор: Chang Chien Shang-Yu, HSU Hung-Hsin, LIN Han-Wen, LIN Nan-Chun
Принадлежит: POWERTECH TECHNOLOGY INC.

A manufacturing method of a package structure is described. The method includes at least the following steps. A carrier is provided. A semiconductor die and a sacrificial structure are disposed on the carrier. The semiconductor die is electrically connected to the bonding pads on the sacrificial structure through a plurality of conductive wires. As encapsulant is formed on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires. The carrier is debonded, and at least a portion of the sacrificial structure is removed through a thinning process. A redistribution layer is formed on the semiconductor die and the encapsulant. The redistribution layer is electrically connected to the semiconductor die through the conductive wires. 1. A manufacturing method of a package structure , comprising:providing a carrier;disposing a semiconductor die and at least one sacrificial structure on the carrier, wherein a plurality of bonding pads are disposed on the sacrificial;electrically connecting the semiconductor die to the bonding pads on the sacrificial structure through a plurality of conductive wires;forming an encapsulant on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires;debonding the carrier;removing at least a portion of the sacrificial structure through a thinning process; andforming a redistribution layer on the semiconductor die and the encapsulant, the redistribution layer is electrically connected to the semiconductor die through the conductive wires.2. The manufacturing method of a package structure according to claim 1 , wherein the thinning process further comprises removing a portion of the encapsulant.3. The manufacturing method of a package structure according to claim 2 , wherein the thinning process further comprises completely removing the sacrificial structure.4. The manufacturing method of a package structure according to claim 3 , wherein the thinning process ...

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Номер записи: 99
23-04-2020 дата публикации

LED MODULE AND METHOD FOR FABRICATING THE SAME

Номер: US20200126957A1
Автор: CHOI Jinwon, Han Sol, HER Jimin, KIM Daewon, KIM Jinmo, LEE Kyujin, Shin Younghwan, YOO Taekyung
Принадлежит: LUMENS CO., LTD.

Disclosed is a method for fabricating an LED module. The method includes: constructing a chip-on-carrier including a chip retainer having a horizontal bonding plane and a plurality of LED chips in which electrode pads are bonded to the bonding plane of the chip retainer; and transferring the plurality of LED chips in a predetermined arrangement from the chip retainer to a substrate by transfer printing. The transfer printing includes: primarily section-wise exposing a transfer tape to reduce the adhesive strength of the transfer tape such that bonding areas are formed at predetermined intervals on the transfer tape; and pressurizing the transfer tape against the LED chips on the chip retainer to attach the LED chips to the corresponding bonding areas of the transfer tape and detaching the electrode pads of the LED chips from the chip retainer to pick up the chips. 1. A micro-LED display module comprising;a substrate;a plurality of electrode patterns arranged in a matrix on the substrate, each of the plurality of electrode patterns comprising a first individual electrode pad, a second individual electrode pad, a third individual electrode pad, and a common electrode pad; and a first LED chip bonded to the first individual electrode pad and the common electrode pad;', 'a second LED chip bonded to the second individual electrode pad and the common electrode pad; and', 'a third LED chip bonded to the third individual electrode pad and the common electrode pad,, 'a plurality of groups of LED chips arranged in the matrix on the substrate, each of the plurality of groups of LED chips comprisingwherein the first LED chip, the second LED chip, and the third LED chip have substantially the same height from the substrate.2. The micro-LED display module according to claim 1 , wherein the first LED chip claim 1 , the second LED chip claim 1 , and the third LED chip are arranged with a substantially same interval in a lengthwise direction.3. The micro-LED display module according ...

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Номер записи: 100