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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 8119. Отображено 100.

01-03-2012 дата публикации

Bumpless build-up layer package with pre-stacked microelectronic devices

Номер: US20120049382A1

Автор: Pramod Malatkar

Принадлежит: Intel Corp

The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

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Номер записи: 1

12-04-2012 дата публикации

Semiconductor device and test system for the semiconductor device

Номер: US20120086003A1

Автор: Sung-Kyu Park

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor package including a stress mitigation unit that mitigates stress to the semiconductor chip. The semiconductor package includes a substrate, a semiconductor chip on the substrate, an encapsulation member formed on the substrate and covering the first semiconductor chip, and the stress mitigation unit mitigating stress from a circumference of the first semiconductor chip to the first semiconductor chip. The stress mitigation unit includes at least one groove formed in the encapsulation member.

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Номер записи: 2

24-05-2012 дата публикации

Semiconductor device and method of forming the same

Номер: US20120126402A1

Автор: Keiyo Kusanagi, Koichi Hatakeyama, Mitsuhisa Watanabe

Принадлежит: Elpida Memory Inc

A semiconductor device includes a wiring board; a stack of semiconductor chips disposed over the wiring board, each of the semiconductor chip comprising via electrodes, the semiconductor chips being electrically coupled through the via electrodes to each other, the semiconductor chips being electrically coupled through the via electrodes to the wiring board; a first seal that seals the stack of semiconductor chips; and a second seal that covers the first seal. The first seal is smaller in elastic modulus than the second seal.

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Номер записи: 3

21-06-2012 дата публикации

Packaged semiconductor chips with array

Номер: US20120153443A1

Автор: Andrey Grinman, Charles Rosenstein, David Ovrutsky, Vage Oganesian

Принадлежит: Tessera LLC

A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.

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Номер записи: 4

02-08-2012 дата публикации

Semiconductor device and method of fabricating the same

Номер: US20120193779A1

Автор: Chung-Sun Lee, Hyun-jung SONG, Jung-Hwan Kim, Sun-pil Youn, Tae-Hong Min

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip. The molding material may be on outer side surfaces of the homogeneous integral underfill material above the upper surface of the first chip, wherein, in view of a first cross sectional profile, the molding material is separated from sidewalls of the second chip by the homogeneous integral underfill material such that the molding material does not contact sidewalls of the second chip.

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Номер записи: 5

13-09-2012 дата публикации

Semiconductor device and manufacturing method of the same

Номер: US20120228762A1

Автор: Hiroshi Watabe, Masatoshi Fukuda

Принадлежит: Toshiba Corp

A semiconductor device, includes: a wiring substrate, a stacked body mounted on the wiring substrate, an underfill layer filled into gaps between respective semiconductor chips of the stacked body; and a molding body made up of a molding resin covered and formed at outside of the stacked body and so on. The underfill layer is made up of a cured product of a resin material containing an amine-based curing agent, and the cured product has a Tg of 65° C. or more and 100° C. or less.

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Номер записи: 6

06-12-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120306100A1

Автор: Teruaki Chino

Принадлежит: Shinko Electric Industries Co Ltd

A method of manufacturing a semiconductor device, includes temporarily fixing a semiconductor chip to a supporting member to direct a connection electrode toward the supporting member side, forming an insulating layer for preventing resin-permeation covering the semiconductor chip, on the supporting member and the semiconductor chip, forming a resin substrate sealing a periphery and a back surface side of the semiconductor chip, on the insulating layer, and removing the supporting member to expose the connection electrode of the semiconductor chip. A build-up wiring is connected directly to the connection electrode of the semiconductor chip.

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Номер записи: 7

24-01-2013 дата публикации

Semiconductor packages and methods of forming the same

Номер: US20130020720A1

Автор: Chul-Yong JANG, JONGHO LEE, Taehoon Kim, Young Lyong Kim

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.

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Номер записи: 8

31-01-2013 дата публикации

Semiconductor device

Номер: US20130026652A1

Автор: Seiya Fujii

Принадлежит: Elpida Memory Inc

A semiconductor device which has a plurality of semiconductor chips stacked on a substrate. The semiconductor device includes semiconductor chip 2 , semiconductor chip 3 a stacked on substrate 4 together with semiconductor chip 2 , and having a foot print larger than semiconductor chip 2 , through electrode 22 extending through semiconductor chip 2 only in a central portion of semiconductor chip 2 , through electrode 32 extending through semiconductor chip 3 a at a position facing to through electrode 22 , and conduction bump 7 b arranged between through electrode 22 and through electrode 32 , and conductively connecting through electrode 22 with through electrode 32.

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Номер записи: 9

07-02-2013 дата публикации

Stackable integrated circuit package system

Номер: US20130032954A1

Автор: Hun Teak Lee, Soo Jung Park, Tae Keun Lee

Принадлежит: Stats Chippac Pte Ltd

A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed.

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Номер записи: 10

28-02-2013 дата публикации

Semiconductor Device and Method of Manufacturing a Semiconductor Device Including Grinding Steps

Номер: US20130049205A1

Автор: David O'Sullivan, Klaus Reingruber, Thorsten Meyer

Принадлежит: Intel Mobile Communications GmbH

A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.

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Номер записи: 11

07-03-2013 дата публикации

System in package and method of fabricating same

Номер: US20130056880A1

Автор: Chien-Hsiun Lee, Tsung-Ding Wang

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An assembly has at least one integrated circuit (IC) die fixed in a medium. The assembly has a redistribution layer over the IC die. The redistribution layer has conductors connecting first pads on active faces of the IC die to second pads at an exposed surface of the assembly. A die unit is provided over the IC die. The die unit has a bottom die interconnected to a package substrate. Respective portions of the redistribution layer corresponding to each of the at least one IC die partially underlie the bottom die, and extend beyond the bottom die. The package substrate has contacts connected to the ones of the second pads corresponding to the at least one IC die.

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Номер записи: 12

28-03-2013 дата публикации

Integrated circuit packaging system with encapsulation and method of manufacture thereof

Номер: US20130075927A1

Автор: HanGil Shin, HeeJo Chi, NamJu Cho

Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base integrated circuit on the base substrate; forming a base encapsulation, having a base encapsulation top side, on the base substrate and around the base integrated circuit; forming a base conductive via, having a base via head, through the base encapsulation and attached to the base substrate adjacent to the base integrated circuit, the base via head exposed from and coplanar with the base encapsulation top side; mounting an interposer structure over the base encapsulation with the interposer structure connected to the base via head; and forming an upper encapsulation on the base encapsulation top side and partially surrounding the interposer structure with a side of the interposer structure facing away from the base encapsulation exposed.

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Номер записи: 13

28-03-2013 дата публикации

Integrated circuit and method of making

Номер: US20130075928A1

Автор: Abram Castro, Bernardo Gallegos

Принадлежит: Texas Instruments Inc

Circuits and methods of fabricating circuits are disclosed herein. An embodiment of the circuit includes a die having a side, wherein a connection point is located on the side. A dielectric layer having a first side, a second side, and at least one via extending between the first side and the second side, is located proximate the side of the die. The via is electrically connected to the connection point. A conductive layer is located adjacent the second side of the first dielectric layer, wherein at least a portion of the conductive layer is electrically connected to the via.

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Номер записи: 14

28-03-2013 дата публикации

Multi-chip semiconductor package and method of fabricating the same

Номер: US20130078763A1

Автор: Jong-Gi Lee, Kwang-Yong Lee, Min-Ho Lee

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A first semiconductor chip having a first projection electrode formed on an upper surface thereof is prepared. A second semiconductor chip having a second projection electrode is mounted on the first semiconductor chip to expose the first projection electrode. An insulating film is formed between the first projection electrode and the second projection electrode. A groove is formed in the insulating film. An interconnection configured to fill an inside of the groove and connected to the first projection electrode and the second projection electrode is formed.

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Номер записи: 15

11-04-2013 дата публикации

Radiation-shielded semiconductor device

Номер: US20130087895A1

Автор: Chih-Chin Liao, Hem Takiar, Suresh Kumar UPADHYAYULA

Принадлежит: SanDisk Technologies LLC

A semiconductor device is disclosed including an electromagnetic radiation shield. The device may include a substrate having a shield ring defined in a conductance pattern on a surface of the substrate. One or more semiconductor die may be affixed and electrically coupled to the substrate. The one or more semiconductor die may then be encapsulated in molding compound. Thereafter, a metal may be plated around the molding compound and onto the shield ring to form an EMI/RFI shield for the device.

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Номер записи: 16

11-04-2013 дата публикации

Methods of Packaging Semiconductor Devices and Structures Thereof

Номер: US20130087916A1

Автор: Jing-Cheng Lin, Jui-Pin Hung, Tsan-Hua Tung, Yi-Hang Lin

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

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Номер записи: 17

25-04-2013 дата публикации

Semiconductor device and fabrication method therefore

Номер: US20130100318A1

Автор: Junji Tanaka, Kouichi Meguro, Masanori Onodera

Принадлежит: SPANSION LLC

Various embodiments of the present invention include a semiconductor device and a fabrication method therefore, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefore, in which downsizing and cost reduction can be realized.

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Номер записи: 18

16-05-2013 дата публикации

Microelectro mechanical system encapsulation scheme

Номер: US20130119493A1

Автор: Bruce C. S. CHOU, Chen-Chih Fan

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A microelectro mechanical system (MEMS) assembly includes a carrier and a MEMS device disposed over the carrier. A buffer layer is disposed over the MEMS device. The Young's modulus of the buffer layer is less than that of the MEMS device.

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Номер записи: 19

23-05-2013 дата публикации

Semiconductor device and manufacturing method therefor

Номер: US20130127050A1

Автор: Takehiko Maeda, Yuichi Miyagawa

Принадлежит: Renesas Electronics Corp

A semiconductor device includes a substrate having a main surface and a back surface opposite to the main surface, a first semiconductor chip having an upper surface and a lower surface opposite to the first surface with a side surface provided therebetween, the first semiconductor chip being mounted on the main surface of the substrate, a plurality of bumps provided between the main surface of the substrate and the lower surface of the first semiconductor chip, a second semiconductor chip having an upper surface and a lower surface opposite to the first surface with a side surface provided therebetween, the second semiconductor chip being mounted on the upper surface of the first semiconductor chip such that the side surface of the second semiconductor chip is positioned outward from the side surface of the first semiconductor chip.

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Номер записи: 20

04-07-2013 дата публикации

Semiconductor device having a through-substrate via

Номер: US20130168850A1

Автор: Arkadii V. Samoilov, Larry Y. Wang, Tyler Parent

Принадлежит: Maxim Integrated Products Inc

Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop.

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Номер записи: 21

15-08-2013 дата публикации

Complex Semiconductor Packages and Methods of Fabricating the Same

Номер: US20130207253A1

Автор: Gwi-gyeon Yang, Seung-won Lim

Принадлежит: Fairchild Korea Semiconductor Ltd

Disclosed are complex semiconductor packages, each including a large power module package which includes a small semiconductor package, and methods of manufacturing the complex semiconductor packages. An exemplary complex semiconductor package includes a first package including: a first packaging substrate; a plurality of first semiconductor chips disposed on the first packaging substrate; and a first sealing member covering the first semiconductor chips on the first packaging substrate; and at least one second package separated from the first packaging substrate, disposed in the first sealing member, and including second semiconductor chips.

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Номер записи: 22

12-09-2013 дата публикации

Semiconductor Packages and Methods of Forming The Same

Номер: US20130234283A1

Автор: Andrew Roberts, Martin Standing

Принадлежит: INFINEON TECHNOLOGIES AG

In one embodiment, a method of fabricating a semiconductor package includes forming a first plurality of die openings on a laminate substrate. The laminate substrate has a front side and an opposite back side. A plurality of first dies is placed within the first plurality of die openings. An integrated spacer is formed around each die of the plurality of first dies. The integrated spacer is disposed in gaps between the laminate substrate and an outer sidewall of each die of the plurality of first dies. The integrated spacer holds the die within the laminate substrate by partially extending over a portion of a top surface of each die of the plurality of first dies. Front side contacts are formed over the front side of the laminate substrate.

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Номер записи: 23

12-09-2013 дата публикации

Flip-chip packaging techniques and configurations

Номер: US20130234344A1

Автор: Frank J. Juskey, Paul D. Bantz, Robert C. Hartmann

Принадлежит: Triquint Semiconductor Inc

Embodiments of the present disclosure flip-chip packaging techniques and configurations. An apparatus may include a package substrate having a plurality of pads formed on the package substrate, the plurality of pads being configured to receive a corresponding plurality of interconnect structures formed on a die and a fluxing underfill material disposed on the package substrate, the fluxing underfill material comprising a fluxing agent configured to facilitate formation of solder bonds between individual interconnect structures of the plurality of interconnect structures and individual pads of the plurality of pads and an epoxy material configured to harden during formation of the solder bonds to mechanically strengthen the solder bonds. Other embodiments may also be described and/or claimed.

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Номер записи: 24

03-10-2013 дата публикации

Semiconductor module

Номер: US20130256865A1

Автор: Akihiro UMEKI, Yoichi Hiruta

Принадлежит: Individual

In the semiconductor module comprising a package substrate, a first semiconductor package, and a semiconductor bare chip, such problems as the occurrence of a wire short caused by warpage of the first semiconductor package and non-filling and the like at the time of resin sealing can be solved. A semiconductor module 10 , having: a semiconductor package 6 , which is obtained by mounting and resin-sealing a semiconductor bare chip on a first package substrate; a semiconductor bare chip 2 ; and a second package substrate 12 , the semiconductor module being characterized in that the semiconductor package 6 is mounted on the second package substrate 12 and the semiconductor bare chip 2 is mounted on the semiconductor package 6.

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Номер записи: 25

17-10-2013 дата публикации

Tape for processing wafer, method for manufacturing tape for processing wafer, and method for manufacturing semiconductor device

Номер: US20130273718A1

Автор: Kouhei Taniguchi, Kouji Komorida, Michio Mashino, Rie Katou, Shinya Katou, Takayuki Matsuzaki, Tatsuya Sakuta

Принадлежит: Hitachi Chemical Co Ltd

In a wafer processing tape, circular or tongue-shaped notched parts facing the center of an adhesive layer, as seen in a plan view, are formed so as to correspond to a pasting region to a wafer ring to a depth that reaches a release substrate from the side of a base material film. Due to the formation of the notched parts, when a peeling force acts on the wafer processing tape, portions of a tacky material layer and the base material film which are more outward than the notched parts are peeled off first, and a portion that is more inward than the notched parts remains on the wafer ring in a protruding state. Accordingly, a peeling strength between the wafer processing tape and the wafer ring can be increased and the wafer processing tape can be suppressed from being peeled off from the wafer ring during processes.

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Номер записи: 26

14-11-2013 дата публикации

Plated terminals with routing interconnections semiconductor device

Номер: US20130299979A1

Автор: Saravuth Sirinorakul

Принадлежит: UTAC Thai Ltd

A semiconductor package includes terminals, each having an exposed surface that is flush with a bottom surface of the semiconductor package, and a layer of interconnection routings disposed within the semiconductor package. At least one interconnection routing is electrically coupled with a terminal and extends planarly therefrom. The semiconductor package also includes at least one die coupled with the layer of interconnection routings. In some embodiments, the semiconductor package also includes one or more additional intermediary layers. Each intermediary layer includes a via layer and an associated routing layer. The associated routing layer includes associated routings. At least one associated routing is electrically coupled with a terminal and extends planarly therefrom. Each via layer couples two routing layers. The semiconductor package also includes a locking mechanism for fastening a package compound with the interconnection routings and the terminals.

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Номер записи: 27

02-01-2014 дата публикации

Package with Passive Devices and Method of Forming the Same

Номер: US20140001635A1

Автор: Der-Chyang Yeh, Li-Hsien HUANG, Shuo-Mao Chen

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar.

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Номер записи: 28

23-01-2014 дата публикации

Embedded integrated circuit package and method for manufacturing an embedded integrated circuit package

Номер: US20140021638A1

Автор: Edward Fuergut, Georg Meyer-Berg, Joachim Mahler, Khalil Hosseini

Принадлежит: INFINEON TECHNOLOGIES AG

A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects.

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Номер записи: 29

27-02-2014 дата публикации

COMPOUND BARRIER LAYER, METHOD FOR FORMING THE SAME AND PACKAGE STRUCTURE USING THE SAME

Номер: US20140054803A1

Автор: Chen Chun-Ting, Lai Li-Wen, Lin Kun-Wei, WANG Teng-Yen

Принадлежит: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

An embodiment of the invention provides a compound barrier layer, including: a first barrier layer disposed on a substrate; and a second barrier layer disposed on the first barrier layer, wherein the first barrier layer and second barrier layer both include a plurality of alternately arranged inorganic material regions and organo-silicon material regions and the inorganic material regions and the organo-silicon material regions of the first barrier layer and second barrier layer are alternatively stacked vertically. 1. A compound barrier layer , comprisinga first barrier layer disposed on a substrate; anda second barrier layer disposed on the first barrier layer, wherein the first barrier layer and second barrier layer both comprise a plurality of alternately arranged inorganic material regions and organo-silicon material regions, wherein the inorganic material regions of the first barrier layer and the organo-silicon material regions of the second barrier layer are alternatively stacked vertically, and the inorganic material regions of the second barrier layer and the organo-silicon material regions of the first barrier layer are alternatively stacked vertically.2. The compound barrier layer as claimed in claim 1 , wherein the organo-silicon material regions of the first barrier layer and the second barrier layer are connected to each other to form a continuous structure claim 1 , and the inorganic material regions of the first barrier layer and the second barrier layer are disconnected with each other to form a discontinuous structure.3. The compound barrier layer as claimed in claim 1 , wherein the organic material regions comprise compounds having an Si—C bond or Si—O—C bond.4. The compound barrier layer as claimed in claim 1 , wherein the inorganic material regions comprise aluminum oxide (AlO) claim 1 , silicon oxide claim 1 , silicon oxynitride claim 1 , silicon nitride claim 1 , silicon-carbon-oxy-nitride claim 1 , or combinations thereof.5. A package ...

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Номер записи: 30

06-03-2014 дата публикации

Methods and Apparatus for Package on Package Structures

Номер: US20140061932A1

Автор: Chung-Shi Liu, Meng-Tse Chen, Ming-Da Cheng, Tao-Hua Lee, Wei-Yu Chen, Xi-Hong Chen, Yi-Da Tsai

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A package-on-package (“PoP”) structure and a method of forming are provided. The PoP structure may be formed by forming a first set of electrical connections on a first substrate. A first material may be applied to the first set of electrical connections. A second substrate may be provided having a second set of electrical connections formed thereon. The first set of electrical connections of the first substrate having the epoxy flux applied may be contacted to the second electrical connections of the second substrate. A reflow process may be performed to electrically connect the first substrate to the second substrate. The epoxy flux applied to the first electrical connections of the first substrate may prohibit electrical bridges or shorts from forming during the reflow process.

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Номер записи: 31

06-03-2014 дата публикации

Semiconductor Device and Method of Forming Thick Encapsulant for Stiffness with Recesses for Stress Relief in FO-WLCSP

Номер: US20140061944A1

Автор: Caparas Jose Alvin, Chen Kang, Lin Yaojian, Omandam Glenn

Принадлежит: STATS CHIPPAC, LTD.

A semiconductor device has a semiconductor die mounted to a carrier. A first encapsulant is deposited over the semiconductor die and carrier. A stiffening support member can be disposed over the carrier around the semiconductor die. A plurality of channels or recesses is formed in the first encapsulant. The recesses can be formed by removing a portion of the first encapsulant. Alternatively, the recesses are formed in a chase mold having a plurality of extended surfaces. A second encapsulant can be deposited into the recesses of the first encapsulant. The carrier is removed and an interconnect structure is formed over the semiconductor die and first encapsulant. The thickness of the first encapsulant provides sufficient stiffness to reduce warpage while the recesses provide stress relief during formation of the interconnect structure. A portion of the first encapsulant and recesses are removed to reduce thickness of the semiconductor device. 1. A method of making a semiconductor device , comprising:providing a first semiconductor die;depositing an encapsulant over the semiconductor die;forming a recess in the encapsulant;forming an interconnect structure over the semiconductor die; andremoving a first portion of the encapsulant.2. The method of claim 1 , wherein forming the recess further includes removing a second portion of the encapsulant while leaving the first portion of the encapsulant.3. The method of claim 1 , further including:disposing a support structure within the recess prior to forming the interconnect structure; andremoving the support structure after forming the interconnect structure.4. The method of claim 1 , further including forming the recess over the first semiconductor die and outside a footprint of the semiconductor die.5. The method of claim 1 , further including:providing a second semiconductor die; andforming the recess over the first and second semiconductor die.6. The method of claim 1 , further including disposing a support member ...

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Номер записи: 32

27-03-2014 дата публикации

Package process and package structure

Номер: US20140087519A1

Автор: Chi-Chih Shen, Jen-Chuan Chen, Tommy Pan

Принадлежит: Advanced Semiconductor Engineering Inc

A package process is provided. An adhesive layer is disposed on a carrier board and then plural first semiconductor devices are disposed on the adhesive layer. A first molding compound formed on the carrier board covers the sidewalls of the first semiconductor devices and fills the gaps between the first semiconductor devices so as to form a chip array board constructed by the first semiconductor devices and the first molding compound. Next, plural second semiconductor devices are flip-chip bonded to the first semiconductor devices respectively. Then, a second molding compound formed on the chip array board at least covers the sidewalls of the second semiconductor devices and fills the gaps between the second semiconductor devices. Subsequently, the chip array board is separated from the adhesive layer. Then, the first and the second molding compound are cut along the gaps between the second semiconductor devices.

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Номер записи: 33

06-01-2022 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20220005779A1

Автор: NIWA Keiichi

Принадлежит:

A semiconductor device includes a wiring board; a first semiconductor chip including a first surface, a second surface, and a connection bump on the first surface, the first semiconductor chip coupled to the wiring board through the connection bump; a resin layer covering the connection bump between the first semiconductor chip and the wiring board, an upper surface of the resin layer parallel to the second surface of the first semiconductor chip; and a second semiconductor chip including a third surface, a fourth surface, and an adhesive layer on the third surface, the second semiconductor chip adhering to the second surface of the first semiconductor chip and the upper surface of the resin layer through the adhesive layer. The upper surface of the resin layer projects outside a portion of at least an outer edge of the second semiconductor chip when viewed from the top. 1. A semiconductor device comprising:a wiring board;a first semiconductor chip including a first surface, a second surface opposite to the first surface, and a connection bump on the first surface, the first semiconductor chip coupled to the wiring board through the connection bump;a resin layer covering the connection bump between the first semiconductor chip and the wiring board, an upper surface of the resin layer substantially parallel to the second surface of the first semiconductor chip; anda second semiconductor chip including a third surface, a fourth surface opposite to the third surface, and an adhesive layer on the third surface, the second semiconductor chip adhering to the second surface of the first semiconductor chip and the upper surface of the resin layer through the adhesive layer,wherein the upper surface of the resin layer projects outside a portion of at least an outer edge of the second semiconductor chip when viewed from the top.2. The semiconductor device according to claim 1 ,wherein a spacer is not provided between the second semiconductor chip and the wiring board.3. The ...

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Номер записи: 34

05-01-2017 дата публикации

CHEMICAL SENSOR PACKAGE FOR HIGHLY PRESSURED ENVIRONMENT

Номер: US20170003247A1

Автор: Chan Yuen Sing, Chidambaram Vivek, Hwang How Yuan, Lee Jong Bum, Wai Eva Leong Ching, Woo Daniel Rhee Min

Принадлежит:

A package for a chemical sensor including an encapsulation and a pressure balancing structure is disclosed. The encapsulation encapsulates a chemical sensor and has a hole for exposing a chemical sensitive part of the chemical sensor. The pressure balancing structure balances pressure applied to the chemical sensor at the chemical sensitive part. 1. A method for packaging a chemical sensor comprising:encapsulating a chemical sensor by a encapsulation;providing a hole for exposing a chemical sensitive part of the chemical sensor; andproviding a pressure balancing structure for balancing pressure applied to the chemical sensor at the chemical sensitive part.2. The method in accordance with claim 1 , wherein the pressure balancing structure is a pressure balancing hole for applying counter pressure to the chemical sensor at the opposite side of the chemical sensitive part claim 1 , the method further comprising providing Redistribution Layer (RDL) on the chemical sensor for moving a wiring outside of the encapsulation away from the opposite side of the chemical sensitive part.3. The method in accordance with claim 1 , wherein the pressure balancing structure is a pressure balancing supporting structure for applying counter pressure to the chemical sensor at the opposite side of the chemical sensitive part claim 1 , the method further comprising providing Redistribution Layer (RDL) on the chemical sensor for moving a wiring outside of the encapsulation away from the opposite side of the chemical sensitive part.4. The method in accordance with claim 1 , further comprising providing Through Mold Via (TMV) interconnection for connecting the chemical sensor to the wiring outside of the encapsulation.5. The method in accordance with claim 1 , wherein the package is fabricated through fan-out wafer level packaging (FO-WLP) processes.6. The method in accordance with claim 1 , further comprising coating the encapsulation by a hydrophobic conformal coating. This patent ...

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Номер записи: 35

05-01-2017 дата публикации

Electronic device and method of manufacturing the same

Номер: US20170005025A1

Автор: FROEHLER Ulrich, GRAWERT Felix, KATZMAIER Ernst, KIRCHNER Uwe, MENTE Rene, Otremba Ralf, SCHLOEGL Andreas, Wahl Uwe

Принадлежит:

Various embodiments provide an electronic device, wherein the electronic device comprises a mounting surface configured to mount the electronic device to an external structure and having a first size; a backside electrode having a second size and having arranged thereon a die electrically connected to the backside electrode; wherein the first size is at least three times the second size. 1. An electronic device comprising:a mounting surface configured to mount the electronic device to an external structure and having a first size;a backside electrode having a second size and having arranged thereon a die electrically connected to the backside electrode;wherein the first size is at least three times the second size.2. The electronic device according to claim 1 , wherein the first size is at least five times the second size.3. The electronic device according to claim 1 , further comprising an encapsulation encapsulating at least partially the electronic device.4. The electronic device according to claim 3 , wherein the encapsulation is formed by an encapsulation material at least partially forming the backside of the electronic device.5. The electronic device according to claim 3 , wherein the encapsulation comprises a plurality of encapsulation materials claim 3 , wherein a first encapsulation material covers the backside of the backside electrode and a second encapsulation material covers a frontside of the electronic device.6. The electronic device according to claim 5 , wherein the first encapsulation material has a different dielectric constant than the second encapsulation material.7. The electronic device according to claim 5 , wherein the first encapsulation material has a different specific heat conductivity than the second encapsulation material.8. The electronic device according to claim 1 , wherein the mounting surface and the backside surface partially overlap in area.9. An electronic module comprising{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'an ...

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Номер записи: 36

05-01-2017 дата публикации

Semiconductor Package System and Method

Номер: US20170005049A1

Автор: Cheng Ming-Da, Huang Hui-Min, Lin Chih-Wei, Liu Chung-Shi, Tsai Tsai-Tsung, Yu Chen-Hua

Принадлежит:

A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die. 1. A semiconductor device comprising:a semiconductor die with a first sidewall;a first protective layer over the semiconductor die, wherein a second sidewall of the first protective layer is recessed from the first sidewall of the semiconductor die;an opening through the first protective layer;an encapsulant covering the first sidewall and the second sidewall, wherein the encapsulant has a top surface that is planar with the first protective layer; anda conductive material filling the opening and extending over the encapsulant.2. The semiconductor device of claim 1 , further comprising a second protective layer over the conductive material.3. The semiconductor device of claim 2 , further comprising an underbump metallization extending through the second protective layer to make electrical contact with the conductive material.4. The semiconductor device of claim 2 , wherein the second protective layer has a third sidewall aligned with a fourth sidewall of the encapsulant.5. The semiconductor device of claim 1 , further comprising a through via extending through the encapsulant and in electrical connection with the conductive material.6. The semiconductor device of claim 1 , wherein the conductive material is in physical contact with the encapsulant.7. The semiconductor device of claim 6 , wherein the conductive material is copper.8. A semiconductor device comprising:a protective material overlying a first surface of a semiconductor die, the protective material having a second surface facing away from the first surface;an encapsulant encapsulating the ...

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Номер записи: 37

05-01-2017 дата публикации

Method of manufacturing a semiconductor package

Номер: US20170005070A1

Автор: Do Won Chul, Hiner David Jon, Huemoeller Ronald, Kelly Michael G., LEE Ji Hun, Park Doo Hyun

Принадлежит:

Methods for a semiconductor device package formed in a chip-on-wafer last process using thin film adhesives are disclosed and may include bonding a first carrier to a first surface of an interposer in wafer form, forming conductive bumps on a second surface of the interposer, bonding a second carrier to the conductive bumps utilizing a film adhesive, removing the first carrier from the interposer, bonding a semiconductor die to the first surface of the interposer, and encapsulating the die and the first surface of the interposer in an encapsulant material. The second carrier and the film adhesive may be removed from the conductive bumps utilizing a slide-off process. The interposer and encapsulant may be diced into a plurality of interposer and die structures. One of the die and interposer structures may be bonded to a substrate. The die may be bonded to the interposer utilizing a mass reflow process. 120-. (canceled)21. A method of manufacturing a semiconductor package , the method comprising:receiving an interposer on a support structure, the interposer comprising an interposer back side that comprises a plurality of interposer back side interconnection structures;attaching a back side carrier to the interposer back side;removing the support structure from the interposer;attaching a semiconductor die to a front side of the interposer;encapsulating at least a portion of the interposer and at least a portion of the semiconductor die in an encapsulating material; andattaching a front side carrier to the encapsulating material and removing the back side carrier.22. The method of claim 21 , wherein said attaching the back side carrier to the interposer back side comprises utilizing an adhesive layer to bond the back side carrier to the interposer back side.23. The method of claim 22 , wherein each of the interposer back side interconnection structures comprises an under-bump metal that is at least partially embedded in the adhesive layer.24. The method of claim 21 , ...

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Номер записи: 38

13-01-2022 дата публикации

PACKAGE STRUCTURES HAVING UNDERFILLS

Номер: US20220013496A1

Автор: KANG Unbyoung, Lee Jongho, Lee TeakHoon, PARK Jinwoo

Принадлежит:

A package structure includes a lower substrate, substrate connection terminals on the lower substrate, a semiconductor package on the substrate connection terminals, the semiconductor package including a package substrate and a first encapsulant covering the package substrate, first underfills between the lower substrate and the semiconductor package, the first underfills covering corner portions of the semiconductor package, as viewed in a plan view, and covering at least one of the substrate connection terminals, and a second underfill between the lower substrate and the semiconductor package, the second underfill covering a side surface of the semiconductor package in a plan view. 1. A package structure , comprising:a lower substrate;substrate connection terminals on the lower substrate;a semiconductor package on the substrate connection terminals, the semiconductor package including a package substrate and a first encapsulant covering the package substrate;first underfills between the lower substrate and the semiconductor package, the first underfills covering corner portions of the semiconductor package, respectively, as viewed in a plan view, and covering at least one of the substrate connection terminals; anda second underfill between the lower substrate and the semiconductor package, the second underfill covering a side surface of the semiconductor package in the plan view.2. The package structure as claimed in claim 1 , wherein each of the first underfills includes:an inner portion overlapping the semiconductor package in a vertical direction, the inner portion covering the substrate connection terminals; andan outer portion not overlapping the semiconductor package in the vertical direction.3. The package structure as claimed in claim 2 , wherein the outer portion covers side surfaces of the package substrate and the first encapsulant.4. The package structure as claimed in claim 3 , wherein a height of a portion of the semiconductor package covered by the ...

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Номер записи: 39

07-01-2016 дата публикации

SYSTEM-IN-PACKAGE

Номер: US20160005726A1

Автор: Chen Nan-Cheng, Chou Che-Ya

Принадлежит:

A system-in-package includes a package carrier; a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier, wherein a plurality of contact pads are situated on the die face; a second semiconductor die mounted on the package carrier and adjacent to the first semiconductor die; a rewiring laminate structure between the first semiconductor die and the package carrier, the rewiring laminate structure comprising a re-routed metal layer, wherein at least a portion of the re-routed metal layer projects beyond the die edge; and a plurality of copper pillar bumps arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier. 1. A system-in-package , comprising:a package carrier;a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier, wherein a plurality of contact pads are situated on the die face;a second semiconductor die mounted on the package carrier adjacent to the first semiconductor die;a rewiring laminate structure between the first semiconductor die and the package carrier, the rewiring laminate structure comprising a re-routed metal layer, wherein at least a portion of the re-routed metal layer projects beyond the die edge; anda plurality of copper pillars arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier.2. The system-in-package according to further comprising an underfill between the rewiring laminate structure and the package carrier.3. The system-in-package according to wherein the package carrier is a substrate comprising two metal wiring layers disposed on the chip side and on an opposite side of the package carrier respectively.4. The system-in-package according to wherein the two metal wiring layers are electrically interconnected to ...

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Номер записи: 40

07-01-2016 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20160005727A1

Автор: OGAWA Kenta, YAMAMACHI Shintaro

Принадлежит:

This invention can reduce heat that is generated in a first semiconductor chip and transfers to a second semiconductor chip through through-silicon vias. The first semiconductor chip has the first through-silicon vias. Each of the first through-silicon vias is arranged on any of grid points arranged in m rows and n columns (m>n). The first semiconductor chip also has a first circuit formation area. A first circuit is formed in the first circuit formation area. The first circuit performs signal processing while communicating with the second semiconductor chip. In plan view, the first circuit formation area does not overlap with a through-silicon via area that is defined by coupling the outermost grid points arranged in m rows and n columns. In plan view, some of connection terminals are located between the first circuit formation area and the through-silicon via area. 19-. (canceled)10. A semiconductor device comprising:a wiring board including a first surface over which an electrode pad is formed;a first semiconductor chip including a second surface over which a first connection terminal is formed, a third surface opposite to the second surface, a through-silicon via, and a first circuit; anda second semiconductor chip including a fourth surface over which a bump electrode is formed;wherein the first semiconductor chip is mounted over the wiring board such that the second surface of the first semiconductor chip faces the first surface of the wiring board,wherein the second semiconductor chip is mounted over the first semiconductor chip such that the fourth surface of the second semiconductor chip faces the third surface of the first semiconductor chip,wherein the first connection terminal of the first semiconductor chip is electrically coupled with the electrode pad of the wiring board,wherein the through-silicon via of the first semiconductor chip is electrically coupled with the bump electrode of the second semiconductor chip,wherein the first circuit of the first ...

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Номер записи: 41

07-01-2016 дата публикации

Methods of Forming Structures

Номер: US20160005966A1

Автор: Hyun Sik Kim, Irina V. Vasilyeva, Kyle B. Campbell, Kyuchul Chong

Принадлежит: Micron Technology Inc

Some embodiments include methods of forming structures. Spaced-apart features are formed which contain temperature-sensitive material. Liners are formed along sidewalls of the features under conditions which do not expose the temperature-sensitive material to a temperature exceeding 300° C. The liners extend along the temperature-sensitive material and narrow gaps between the spaced-apart features. The narrowed gaps are filled with flowable material which is cured under conditions that do not expose the temperature-sensitive material to a temperature exceeding 300° C. In some embodiments, the features contain memory cell regions over select device regions. The memory cell regions include first chalcogenide and the select device regions include second chalcogenide. The liners extend along and directly against the first and second chalcogenides.

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Номер записи: 42

02-01-2020 дата публикации

Semiconductor module

Номер: US20200006170A1

Автор: Takashi NUNOKAWA, Takayuki Takano, Yuichi Sasajima

Принадлежит: TAIYO YUDEN CO LTD

A semiconductor module includes: a dielectric film that has a first surface and a second surface opposed to the first surface; a plurality of circuit parts mounted on the first surface; an electrode layer that is disposed on the second surface and includes a plurality of electrode portions to be electrically connected to the plurality of circuit parts, at least a part of the plurality of electrode portions including a base that is long in one axis direction; a rigid member that is disposed on the first surface, includes, at least one shaft portion, and faces the base with the dielectric layer sandwiched therebetween, the at least one shaft axis extending along the one axis direction; and a sealing layer that is provided on the first surface and covers the plurality of circuit parts and the rigid member.

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Номер записи: 43

02-01-2020 дата публикации

MULTI-LAYER SOLUTION BASED DEPOSITION OF DIELECTRICS FOR ADVANCED SUBSTRATE ARCHITECTURES

Номер: US20200006180A1

Автор: ALUR Amruthavalli, ALUR Siddharth, BROWN ANDREW, PARK Ji Yong, Xu Cheng

Принадлежит:

Embodiments include an electronic package and methods of forming an electronic package. In an embodiment, the electronic package comprises a substrate, and a plurality of conductive features formed over the substrate. In an embodiment, a bilayer build-up layer is formed over the plurality of conductive features. In an embodiment, the bilayer build-up layer comprises a first dielectric layer and a second dielectric layer. In an embodiment, a surface of the first dielectric layer comprises depressions. In an embodiment, the second dielectric layer is disposed in the depressions of the surface of the first dielectric layer. 1. An electronic package , comprising:a substrate;a plurality of conductive features formed over the substrate; and a first dielectric layer, wherein a surface of the first dielectric layer comprises depressions; and', 'a second dielectric layer in the depressions of the surface of the first dielectric layer., 'a bilayer build-up layer formed over the plurality of conductive features, wherein the bilayer build-up layer comprises2. The electronic package of claim 1 , wherein depressions in the first dielectric layer are located between the conductive features formed over the substrate.3. The electronic package of claim 1 , wherein the second dielectric layer completely fills the depressions of the first dielectric layer.4. The electronic package of claim 1 , wherein a depth of the depressions are approximately 10 microns or less.5. The electronic package of claim 4 , wherein the depth of the depressions are approximately 5 microns or less.6. The electronic package of claim 1 , wherein a surface of the second dielectric has a C4 area thickness variation (CTV) of 10 microns or less.7. The electronic package of claim 1 , wherein the second dielectric is a spun on dielectric.8. The electronic package of claim 7 , wherein the first dielectric comprises filler particles.9. The electronic package of claim 1 , further comprising a plurality of bilayer build- ...

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Номер записи: 44

02-01-2020 дата публикации

Underfill Structure for Semiconductor Packages and Methods of Forming the Same

Номер: US20200006181A1

Автор: CHEN Yu-Wei, Huang Kuan-Yu, Kuo Li-Chung, Lee Long Hua, Lin Jing-Cheng, Lu Szu-Wei, Shih Ying-Ching

Принадлежит:

A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE. 1. A device comprising: an integrated circuit die;', 'an interposer bonded to the integrated circuit die by a plurality of die connectors; and', 'an encapsulant surrounding the integrated circuit die;, 'a package comprisinga package substrate bonded to the interposer by a plurality of conductive connectors;a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); anda second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.2. The device of claim 1 , wherein the first underfill tapers from the package toward the package substrate.3. The device of claim 2 , wherein the second underfill tapers from the package substrate toward the package.4. The device of claim 1 , wherein the first underfill and the second underfill taper from the package substrate toward the package.5. The device of claim 1 , wherein the first underfill is in contact with the interposer and spaced apart from the encapsulant.6. The device of claim 1 , wherein the second underfill is in contact with the package and spaced apart from the conductive connectors.7. The device of claim 1 , wherein the first underfill has a ...

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Номер записи: 45

02-01-2020 дата публикации

RF DEVICES WITH ENHANCED PERFORMANCE AND METHODS OF FORMING THE SAME

Номер: US20200006193A1

Автор: Carroll Michael, Costa Julio C.

Принадлежит:

The present disclosure relates to a radio frequency device that includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion, first bump structures, a first mold compound, and a second mold compound. The FEOL portion includes an active layer, a contact layer, and isolation sections. Herein, the active layer and the isolation sections reside over the contact layer, and the active layer is surrounded by the isolation sections. The BEOL portion is formed underneath the FEOL portion, and the first bump structures and the first mold compound are formed underneath the BEOL portion. Each first bump structure is partially encapsulated by the first mold compound, and electrically coupled to the FEOL portion via connecting layers within the BEOL portion. The second mold compound resides over the active layer without a silicon material, which has a resistivity between 5 Ohm-cm and 30000 Ohm-cm, in between. 1. An apparatus comprising: the BEOL portion comprises a plurality of connecting layers;', 'the FEOL portion comprises an active layer, a contact layer, and isolation sections;', 'the active layer and the isolation sections reside over the contact layer, and the isolation sections surround the active layer;', 'the active layer does not extend vertically beyond the isolation sections;, 'a device region including a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion residing over the BEOL portion, whereina plurality of first bump structures formed at a bottom surface of the BEOL portion, wherein the plurality of first bump structures is electrically coupled to the FEOL portion via the plurality of connecting layers;a first mold compound formed over the bottom surface of the BEOL portion and partially encapsulating each of the plurality of first bump structures, wherein a bottom portion of each of the plurality of first bump structures is not covered by the first mold compound; anda second mold compound residing over ...

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Номер записи: 46

02-01-2020 дата публикации

SEMICONDUCTOR PACKAGES

Номер: US20200006196A1

Автор: Lin Jing-Cheng, Lu Szu-Wei

Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor packages are provided. One of the semiconductor package includes a semiconductor die, a thermal conductive pattern, an encapsulant and a thermal conductive layer. The thermal conductive pattern is disposed aside the semiconductor die. The encapsulant encapsulates the semiconductor die and the thermal conductive pattern. The thermal conductive layer covers a rear surface of the semiconductor die, wherein the thermal conductive pattern is thermally coupled to the semiconductor die through the thermal conductive layer and electrically insulated from the semiconductor die. 1. A semiconductor package , comprising:a semiconductor die;a thermal conductive pattern aside the semiconductor die;an encapsulant, encapsulating the semiconductor die and the thermal conductive pattern; anda thermal conductive layer covering a rear surface of the semiconductor die, wherein the thermal conductive pattern is thermally coupled to the semiconductor die through the thermal conductive layer and electrically insulated from the semiconductor die.2. The semiconductor package as claimed in claim 1 , further comprising a semiconductor device stacked over and electrically connected to the semiconductor die.3. The semiconductor package as claimed in claim 1 , wherein the thermal conductive pattern comprises a plurality of discrete through vias.4. The semiconductor package as claimed in claim 3 , wherein the plurality of discrete through vias are arranged along at least one ring-shaped path surrounding the semiconductor die.5. The semiconductor package as claimed in claim 1 , wherein the thermal conductive pattern comprises a ring-shaped structure surrounding the semiconductor die.6. The semiconductor package as claimed in claim 1 , wherein the thermal conductive pattern comprises a plurality of discrete wall-shaped structures.7. The semiconductor package as claimed in claim 1 , further comprising a redistribution circuit structure disposed over an active surface of the ...

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Номер записи: 47

02-01-2020 дата публикации

CHIP PACKAGE AND METHOD OF FABRICATING THE SAME

Номер: US20200006219A1

Автор: Chen Guan-Yu, HUANG Li-Hsien, SU An-Jhih, Yeh Der-Chyang, Yeh Ming-Shih

Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A chip package including an integrated circuit component, a thermal conductive layer, an insulating encapsulant and a redistribution circuit structure is provided. The integrated circuit component includes an amorphous semiconductor portion located at a back surface thereof. The thermal conductive layer covers the amorphous semiconductor portion of the integrated circuit component, wherein thermal conductivity of the thermal conductive layer is greater than or substantially equal to 10 W/mK. The insulating encapsulant laterally encapsulates the integrated circuit component and the thermal conductive layer. The redistribution circuit structure is disposed on the insulating encapsulant and the integrated circuit component, wherein the redistribution circuit structure is electrically connected to the integrated circuit component. 1. A method of fabricating a chip package , the method comprising:attaching an integrated circuit component on a carrier through a first thermal paste, wherein thermal conductivity of the first thermal paste ranges from about 10 W/mK to about 250 W/mK;forming an insulating encapsulant to encapsulate the integrated circuit component attached on the carrier; andforming a redistribution circuit structure on the insulating encapsulant and the integrated circuit component, wherein the redistribution circuit structure is electrically connected to the integrated circuit component.2. The method as claimed in further comprising:forming a plurality of conductive through vias on the carrier before forming the insulating encapsulant such that the conductive through vias are encapsulated by the insulating encapsulant,wherein the conductive through vias are electrically connected to the integrated circuit component through the redistribution circuit structure after forming the redistribution circuit structure.3. The method as claimed in further comprising:after forming the redistribution circuit structure, de-bonding the first thermal paste and the ...

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Номер записи: 48

02-01-2020 дата публикации

Mixing Organic Materials into Hybrid Packages

Номер: US20200006254A1

Автор: Chen Hsien-Wei, Chen Ming-Fa, Hu Chih-Chia, Yu Chen-Hua

Принадлежит:

A method includes forming an interposer, which includes a semiconductor substrate, and an interconnect structure over the semiconductor substrate. The method further includes bonding a device die to the interposer, so that a first metal pad in the interposer is bonded to a second metal pad in the device die, and a first surface dielectric layer in the interposer is bonded to a second surface dielectric layer in the device die. The method further includes encapsulating the device die in an encapsulating material, forming conductive features over and electrically coupling to the device die, and removing the semiconductor substrate. A part of the interposer, the device die, and portions of the conductive features in combination form a package. 1. A package comprising: an interposer;', 'a device die underlying and bonded to the interposer;', 'a first encapsulating material encapsulating the device die therein, wherein the first encapsulating material is overlapped by a portion of the interposer;, 'a device package comprisinga second encapsulating material encapsulating the device package therein;at least one dielectric layer overlapping the second encapsulating material and the device package; andconductive features in the at least one dielectric layer, wherein the conductive features are electrically coupled to the device die through the interposer.2. The package of claim 1 , wherein a first metal pad in the interposer is bonded to a second metal pad in the device die claim 1 , and a first surface dielectric layer in the interposer is bonded to a second surface dielectric layer in the device die.3. The package of further comprising a supporting substrate underlying a semiconductor substrate of the device die.4. The package of further comprising an additional dielectric layer on the supporting substrate claim 3 , wherein the additional dielectric layer is bonded to the semiconductor substrate of the device die.5. The package of claim 4 , wherein the additional ...

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Номер записи: 49

03-01-2019 дата публикации

METHOD FOR PACKAGING CHIP AND CHIP PACKAGE STRUCTURE

Номер: US20190006196A1

Автор: QU Lianjie

Принадлежит:

A method for packaging a chip, including: forming a release layer on a first panel-level substrate, and forming redistribution layers respectively on predetermined regions on the release layer, the redistribution layers located in different regions being insulated from each other, and forming a first dielectric layer during the process of forming the redistribution layers; connecting a chip and a pillar connected to the chip to the redistribution layer formed in the predetermined region through a solder cap on the pillar; packaging the chip to form an encapsulation layer; and removing the first panel-level substrate and the release layer, and forming a solder ball on one side of the redistribution layer. 1. A method for packaging a chip , comprising:forming a release layer on a first panel-level substrate, and forming redistribution layers respectively on predetermined regions on the release layer, the redistribution layers located in different predetermined regions being insulated from each other, and forming a first dielectric layer during the process of forming the redistribution layers;connecting a chip and a pillar connected to the chip to the redistribution layer formed in the predetermined region through a solder cap on the pillar;packaging the chip to form an encapsulation layer; andremoving the first panel-level substrate and the release layer, and forming a solder ball on one side of the redistribution layer.2. The method for packaging a chip according to claim 1 , wherein before connecting a chip and a pillar connected to the chip to the redistribution layer formed in the predetermined region through a solder cap on the pillar claim 1 , the method for packaging the chip further comprises:fixing a plurality of wafers to a second panel-level substrate, the wafer comprises a plurality of chips;forming a pillar and a solder cap on a side of each chip away from the second panel-level substrate;forming a second dielectric layer, the second dielectric layer ...

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Номер записи: 50

03-01-2019 дата публикации

SEMICONDUCTOR PACKAGE AND METHOD MANUFACTURING THE SAME

Номер: US20190006257A1

Автор: Hsu Feng-Cheng, Jeng Shin-Puu

Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor package including at least one integrated circuit component, a glue material, an insulating encapsulation, and a redistribution circuit structure is provided. The glue material encapsulates the at least one integrated circuit component and has a first surface and a second surface opposite to the first surface, wherein the at least one integrated circuit component is exposed by the first surface of the glue material, and an area of the first surface is smaller than an area of the second surface. The insulating encapsulation encapsulates the glue material, wherein an interface is between the glue material and the insulating encapsulation. The redistribution circuit structure is disposed on the at last one integrated circuit component, the glue material and the insulating encapsulation, wherein the redistribution circuit structure is electrically connected to the at least one integrated circuit component. 1. A semiconductor package , comprising:at least one integrated circuit component having an active surface;a glue material, encapsulating the at least one integrated circuit component and having a first surface and a second surface opposite to the first surface, wherein the at least one integrated circuit component is exposed by the first surface of the glue material, and an area of the first surface is smaller than an area of the second surface;an insulating encapsulation, encapsulating the glue material, wherein an interface is between the glue material and the insulating encapsulation; anda redistribution circuit structure disposed on the at least one integrated circuit component, the glue material and the insulating encapsulation, wherein the redistribution circuit structure is electrically connected to the at least one integrated circuit component,wherein the active surface of the at least one integrated circuit component faces toward the first surface of the glue material.2. The semiconductor package as claimed in claim 1 , wherein an included ...

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Номер записи: 51

03-01-2019 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR MODULE AND SEMICONDUCTOR MODULE

Номер: US20190006258A1

Автор: BANDO KOJI, MUTO Kuniharu

Принадлежит:

Reliability of a semiconductor module is improved. In a resin mold step of assembly of a semiconductor module, an IGBT chip, a diode chip, a control chip, a part of each of chip mounting portions are resin molded so that a back surface of each of the chip mounting portions is exposed from a back surface of a sealing body. After the resin molding, an insulating layer is bonded to the back surface of the sealing body so as to cover each back surface (exposed portion) of the chip mounting portions, and then, a TIM layer is bonded to an insulating layer. Here, a region of the TIM layer in a plan view is included in a region of the insulating layer. 1. A method of manufacturing a semiconductor module comprising the steps of:(a) preparing a first semiconductor chip including a first power transistor therein and having a first surface formed with a first terminal electrically connected to the first power transistor and a second surface opposite to the first surface, the second surface being formed with a second terminal electrically connected to the first power transistor;(b) preparing a second semiconductor chip including a second power transistor therein and having a first surface formed with a third terminal electrically connected to the second power transistor and a second surface opposite to the first surface, the second surface being formed with a fourth terminal electrically connected to the second power transistor;(c) after the step (a), mounting the first semiconductor chip through a first conductive bonding material on a first chip mounting portion having a first surface and a second surface opposite to the first surface so that the first surface of the first chip mounting portion and the second surface of the first semiconductor chip face each other;(d) after the step (b), mounting the second semiconductor chip through a second conductive bonding material on a second chip mounting portion having a first surface and a second surface opposite to the first surface ...

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Номер записи: 52

03-01-2019 дата публикации

Integrated Circuit Packages and Methods of Forming Same

Номер: US20190006354A1

Автор: Hung-Jui Kuo, Ming-Che Ho, Yi-Wen WU

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An integrated circuit package and a method of forming the same are provided. A method includes attaching a first side of an integrated circuit die to a carrier. An encapsulant is formed over and around the integrated circuit die. The encapsulant is patterned to form a first opening laterally spaced apart from the integrated circuit die and a second opening over the integrated circuit die. The first opening extends through the encapsulant. The second opening exposes a second side of the integrated circuit die. The first side of the integrated circuit die is opposite the second side of the integrated circuit die. A conductive material is simultaneously deposited in the first opening and the second opening.

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Номер записи: 53

08-01-2015 дата публикации

SEMICONDUCTOR PACKAGES

Номер: US20150008594A1

Автор: Chen Meng-Tse, Chen Wei-yu, Chen Xi-Hong, Cheng Ming-Da, Lee Tao-Hua, Liu Chung-Shi, Tsai Yi-Da

Принадлежит:

A semiconductor package may include a first substrate, a second substrate facing the first substrate, a plurality of first electrical connections disposed between the first substrate and the second substrate, and a first material disposed between the first substrate and the second substrate. The plurality of first electrical connections may electrically couple the first substrate and the second substrate to each other. The first material may surround each of the plurality of first electrical connections, and a width of the first material proximal the first substrate may be smaller than a width of the first material proximal the second substrate. 1. A semiconductor package comprising: a first encapsulant formed over the first side of the first substrate; and', 'a first plurality of electrical features formed at the second side of the first substrate;, 'a first substrate having a first side and a second side opposite the first side, the first substrate comprisinga second substrate having a first side and a second side opposite the first side, the second substrate comprising a second plurality of electrical features formed on the first side of the second substrate;a plurality of first electrical connections coupled between the first plurality of electrical features and the second plurality of electrical features;a second encapsulant disposed over the first side of the second substrate, the second encapsulant positioned between each of the plurality of first electrical connections; anda first material disposed over the second encapsulant, the first material positioned between each of the plurality of first electrical connections, wherein the first material is separated from the second side of the first substrate.2. The semiconductor package of claim 1 , further comprising:a third encapsulant disposed between the second encapsulant and the second side of the first substrate.3. The semiconductor package of claim 2 , wherein the third encapsulant comprises a molding ...

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Номер записи: 54

20-01-2022 дата публикации

SEMICONDUCTOR PACKAGE AND PACKAGE-ON-PACKAGE INCLUDING THE SAME

Номер: US20220020676A1

Автор: YU Bongken

Принадлежит:

A semiconductor package that includes a support wiring structure. A semiconductor chip is on the support wiring structure. A cover wiring structure is on the semiconductor chip. A plurality of connection structures penetrates a filling member and electrically connects the support wiring structure to the cover wiring structure. The filling member fills a space between the support wiring structure and the cover wiring structure. The filling member surrounds the plurality of connection structures and the semiconductor chip and includes a plurality of fillers. A partial portion of the plurality of fillers includes cutting fillers having a flat surface that extends along a vertical level that is a reference level. 1. A semiconductor package comprising:a support wiring structure;a semiconductor chip on the support wiring structure;a cover wiring structure on the semiconductor chip;a plurality of connection structures penetrating a filling member and configured to electrically connect the support wiring structure to the cover wiring structure; andthe filling member fills a space between the support wiring structure and the cover wiring structure, the filling member surrounding the plurality of connection structures and the semiconductor chip and including a plurality of fillers;wherein a partial portion of the plurality of fillers includes cutting fillers having a flat surface that extends along a vertical level that is a reference level.2. The semiconductor package of claim 1 , wherein the flat surface of the cutting filler is an upper surface of the cutting filler claim 1 , and a remaining portion of the cutting filler extends below the reference level.3. The semiconductor package of claim 1 , wherein an upper surface of the semiconductor chip is positioned at the reference level.4. The semiconductor package of claim 3 , wherein each of the plurality of connection structures has an entasis shape and a maximum horizontal width of the plurality of connection structures is ...

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Номер записи: 55

27-01-2022 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE

Номер: US20220028769A1

Автор: ZIGLIOLI Federico Giovanni

Принадлежит: STMICROELECTRONICS S.R.L.

A semiconductor chip is mounted on a leadframe. A first portion of an insulating package for the semiconductor chip is formed from laser direct structuring (LDS) material molded onto the semiconductor chip. A conductive formation (provided by laser-drilling the LDS material and plating) extends between the outer surface of the first portion of insulating package and the semiconductor chip. An electrically conductive clip is applied onto the outer surface of the first portion of the insulating package, with the electrically conductive clip electrically coupled to the conductive formation and the leadframe. A second portion of the insulating package is made from package molding material (epoxy compound) molded onto the electrically conductive clip and applied onto the outer surface of the first portion of the insulating package. 1. A semiconductor device , comprising:a leadframe having at least one semiconductor chip mounted thereon;at least one portion of an insulating package over the at least one semiconductor chip on the leadframe, said at least one portion made of a laser direct structuring material molding on the at least one semiconductor chip, the at least one portion of the insulating package having an outer surface;at least one electrically conductive formation extending between an outer surface of the at least one portion of the insulating package and the at least one semiconductor chip; andan electrically conductive clip applied onto the outer surface of the at least one portion of the insulating package, the electrically conductive clip electrically coupled to the at least one electrically conductive formation and electrically coupled to the leadframe, with the at least one semiconductor chip located intermediate the leadframe and the electrically conductive clip.2. The semiconductor device of claim 1 , comprising at least one further portion of the insulating package over the at least one semiconductor chip claim 1 , the at least one further portion ...

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Номер записи: 56

12-01-2017 дата публикации

Semiconductor Device and Method of Depositing Encapsulant Along Sides and Surface Edge of Semiconductor Die in Embedded WLCSP

Номер: US20170011936A1

Автор: Lin Yaojian, Marimuthu Pandi C., Wirtz Heinz-Peter, Yoon Seung Wook

Принадлежит: STATS ChipPAC Pte. Ltd.

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface. 1. A method of making a semiconductor device , comprising:providing a substrate;disposing a semiconductor die over the substrate;depositing a first encapsulant over the substrate and semiconductor die; andsingulating the first encapsulant.2. The method of claim 1 , further including:depositing a second encapsulant over the semiconductor die; andsingulating the second encapsulant and substrate prior to depositing the first encapsulant.3. The method of claim 2 , further including depositing the second encapsulant between the semiconductor die and substrate.4. The method of claim 1 , further including removing a portion of the first encapsulant to form a recess in the first encapsulant adjacent to the substrate prior to singulating the first encapsulant.5. The method of claim 4 , further including removing the portion of the first encapsulant using laser direct ablation (LDA).6. The method of claim 1 , further including depositing a mold underfill between the semiconductor die and substrate.7. The method of claim 1 , further including disposing an interconnect ...

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Номер записи: 57

14-01-2016 дата публикации

PHOTOCOUPLER

Номер: US20160013113A1

Автор: Ikedo Yuichi, MURANAKA Tetsuya

Принадлежит:

A photocoupler includes: a light emitting element; a light receiving element; an inner resin layer; and an outer resin layer. The light emitting element is driven by an input electrical signal. The light receiving element is configured to convert emission light of the light emitting element into an electrical signal. The inner resin layer includes a base resin and a curing agent. The base resin contains isocyanuric acid having an epoxy group. The curing agent contains an acid anhydride having an acid anhydride group. The inner resin layer covers the light emitting element and the light receiving element. Then outer resin layer encloses the inner resin layer and configured to block the emission light. Carbon atomic concentration increases and oxygen atomic concentration decreases with distance in depth direction of the inner resin layer from an interface. 1. A semiconductor device comprising:a semiconductor element;a first resin layer including a base resin and a curing agent, and covering the semiconductor element; anda second resin layer covering the first resin layer, wherein the first resin layer has a region, and carbon atomic concentration of the region increases and oxygen atomic concentration of the region decreases with distance in depth direction of the first resin layer from an interface between the first resin layer and the second resin layer.2. The device according to claim 1 , wherein the base resin contains isocyanuric acid having an epoxy group claim 1 , and the curing agent contains an acid anhydride having an acid anhydride group.3. The device according to claim 2 , whereinthe first resin layer and the second resin layer each include an inorganic filler containing silicon, andthe inorganic filler of the inner resin layer is exposed at the interface.4. The device according to claim 3 , whereinthe first resin layer is blended with a first inorganic filler at a first blending ratio of 60 weight % or more and 85 weight % or less,the second resin layer ...

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Номер записи: 58

11-01-2018 дата публикации

Circuit Package

Номер: US20180012816A1

Автор: Chen Chien-Hua, Cumbie Michael W, Farrar Stephen

Принадлежит: Hewlett-Packard Development Company, L.P.

A circuit package comprises a circuit device in a first epoxy mold compound and a second epoxy mold compound of different compositions. 1. A circuit package , comprisinga packaging,a circuit device in the packaging, whereinthe packaging comprises a first epoxy mold compound with a first CTE and a second epoxy mold compound with a second CTE higher than the first CTE, the second epoxy mold compound being disposed adjacent to the circuit device.2. The circuit package of claim 1 , whereinthe second epoxy mold compound extends in the same plane as the circuit device, andthe first epoxy mold compound extends under the second epoxy mold compound and under the circuit device.3. The circuit package of comprising an array of circuit devices.4. The circuit package of wherein the first epoxy mold compound has a higher weight percentage of fillers than the second epoxy mold compound.5. The circuit package of wherein a weight percentage of fillers in the epoxy mold compounds increases in at least one direction away from the circuit device.6. The circuit package of wherein a total volume of the second epoxy mold compound is less than a total volume of the first epoxy mold compound.7. The circuit package of wherein the circuit device includes fluid channels claim 1 , and the packaging comprises fluid holes that open into the fluid channels.8. A method of compression molding claim 1 , comprisingdepositing at least two epoxy mold compounds of different compositions over a cavity,heating the compounds,depositing a circuit device in at least one of the epoxy mold compounds, andcooling the circuit device and the epoxy mold compounds.9. The method of wherein a second epoxy mold compound has a higher CTE than a first epoxy mold compound.10. The method of comprising depositing a relatively thin layer of the second epoxy mold compound over a relatively thick layer of the first epoxy mold compound11. The method of wherein the circuit device is disposed in the same layer as the second epoxy ...

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Номер записи: 59

11-01-2018 дата публикации

Semiconductor Device and Method of Forming PoP Semiconductor Device with RDL Over Top Package

Номер: US20180012857A1

Автор: Yaojian Lin

Принадлежит: Stats Chippac Pte Ltd

A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.

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Номер записи: 60

11-01-2018 дата публикации

Chip-On-Wafer Package and Method of Forming Same

Номер: US20180012862A1

Автор: Chen Ming-Fa, Yeh Sung-Feng, Yu Chen-Hua

Принадлежит:

A method includes bonding a die to a substrate, where the substrate has a first redistribution structure, the die has a second redistribution structure, and the first redistribution structure is bonded to the second redistribution structure. A first isolation material is formed over the substrate and around the die. A first conductive via is formed, extending from a first surface of the substrate, where the first surface is opposite the second redistribution structure, the first conductive via contacting a first conductive element in the second redistribution structure. Forming the first conductive via includes patterning an opening in the substrate, extending the opening to expose the first conductive element, where extending the opening includes using a portion of a second conductive element in the first redistribution structure as an etch mask, and filling the opening with a conductive material. 1. A method comprising:bonding a die to a substrate, the substrate having a first redistribution structure disposed at a first surface of the substrate, the die having a second redistribution structure, the first redistribution structure being bonded to the second redistribution structure;forming a first isolation material over the substrate and around the die;patterning an opening in a second surface of the substrate, the second surface being opposite the substrate from the first surface;extending the opening to expose a first conductive element in the second redistribution structure, wherein extending the opening comprises using a second conductive element in the first redistribution structure as an etch mask; andfilling the opening with a conductive material, the conductive material contacting the first conductive element.2. The method of claim 1 , further comprising:after extending the opening, forming an isolation layer in the opening; andetching the isolation layer to form sidewall spacers on sidewalls of the opening.3. The method of claim 2 , wherein the sidewall ...

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Номер записи: 61

15-01-2015 дата публикации

Microelectronic packages and methods for the fabrication thereof

Номер: US20150014855A1

Автор: Douglas G. Mitchell, Weng Foong Yap

Принадлежит: Individual

Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method comprises encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body. The outer molded body has a portion, which circumscribes the core redistribution layer. One or more topside redistribution layers are produced over the core redistribution layer. A contact array is formed over the topside redistribution layer and electrically coupled to the first semiconductor die encapsulated in the outer molded body through the topside redistribution layers and the core redistribution layers.

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Номер записи: 62

10-01-2019 дата публикации

Wafer-level packaging for enhanced performance

Номер: US20190013254A1

Автор: Jon Chadwick, Julio C. Costa, Merrill Albert Hatcher, JR., Peter V. Wright

Принадлежит: Qorvo US Inc

The present disclosure relates to a mold module that includes a device layer, a number of first bump structures, a first mold compound, a stop layer, and a second mold compound. The device layer includes a number of input/output (I/O) contacts at a top surface of the device layer. Each first bump structure is formed over the device layer and electronically coupled to a corresponding I/O contact. The first mold compound resides over the device layer, and a portion of each first bump structure is exposed through the first mold compound. The stop layer is formed underneath the device layer. The second mold compound resides underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.

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Номер записи: 63

10-01-2019 дата публикации

WAFER-LEVEL PACKAGING FOR ENHANCED PERFORMANCE

Номер: US20190013255A1

Автор: Chadwick Jon, Costa Julio C., Hatcher, JR. Merrill Albert, Wright Peter V.

Принадлежит:

The present disclosure relates to a wafer-level packaging process. According to an exemplary process, a precursor wafer that includes a device layer with a number of input/output (I/O) contacts, a number of bump structures over the device layer, the stop layer underneath the device layer, and a silicon handle layer underneath the stop layer is provided. Herein, each bump structure is electronically coupled to a corresponding I/O contact. A first mold compound is then applied over the device layer to encapsulate each bump structure. Next, the silicon handle layer is removed substantially. A second mold compound is applied to an exposed surface from which the silicon handle layer was removed. Finally, the first mold compound is thinned down to expose a portion of each bump structure. 1. A method comprising: the device layer has a plurality of input/output (I/O) contacts at a top surface of the device layer;', 'the plurality of first bump structures are formed over the device layer, wherein each of the plurality of first bump structures is electronically coupled to a corresponding I/O contact;', 'the stop layer resides underneath the device layer; and', 'the silicon handle layer resides underneath the stop layer, such that the stop layer separates the device layer from the silicon handle layer;, 'providing a precursor wafer that includes a silicon handle layer, a stop layer, a device layer, and a plurality of first bump structures, whereinapplying a first mold compound over the device layer to encapsulate each of the plurality of first bump structures;removing substantially the silicon handle layer;applying a second mold compound to an exposed surface from which the silicon handle layer was removed; andthinning down the first mold compound to provide a mold wafer, wherein a portion of each of the plurality of first bump structures is exposed.2. The method of wherein removing substantially the silicon handle layer is provided by one of a group consisting of chemical ...

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Номер записи: 64

10-01-2019 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20190013256A1

Автор: Kim Jin Su, KO Young Gwan, Lee Han Ul

Принадлежит:

A semiconductor device includes: a chip having an active surface having connection pads disposed thereon; an encapsulant encapsulating at least portions of the chip; a connection member disposed on the active surface of the chip and including a redistribution layer electrically connected to the connection pads; a passivation layer disposed on the connection member; and an under bump metallurgy (UBM) layer at least partially embedded in the passivation layer and electrically connected to the redistribution layer of the connection member. The UBM layer includes a UBM pad partially embedded in the passivation layer and a UVM via penetrating through a portion of the passivation layer and electrically connecting the redistribution layer of the connection member and the UBM pad to each other. A portion of a side surface of the UBM pad is exposed through an opening formed in the passivation layer and the opening surrounds the UBM pad. 1. An interposer comprising:a passivation layer;a first redistribution layer (RDL) disposed on the passivation layer;under bump metallurgy (UBM) pads at least partially embedded in the passivation layer;UBM vias penetrating through a portion of the passivation layer and electrically connecting the first RDL and the UBM pads to each other; anda resin layer disposed on a lower surface of the passivation layer and having openings,wherein each opening exposes at least a portion of a lower surface of respective UBM pad, andwherein a width of an upper surface of each UBM via in contact with the redistribution layer is greater than that of a lower surface thereof in contact with the respective UBM pad.2. The interposer of claim 1 , further comprising:first connection terminals disposed on the openings,wherein each first connection terminal is connected to the exposed lower surface of the respective UBM pad.3. The interposer of claim 1 , further comprising:an insulating layer disposed on an upper surface of the passivation layer; anda second RDL ...

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Номер записи: 65

10-01-2019 дата публикации

SEMICONDUCTOR PACKAGES

Номер: US20190013299A1

Автор: Lee Sang-Won

Принадлежит:

Provided is a semiconductor package having high electric reliability. The semiconductor package includes a lower sub-semiconductor package including a lower semiconductor chip and a lower mold layer on the lower semiconductor chip and having a mold via hole, an upper sub-semiconductor package including an upper semiconductor chip, a filling layer that is between the lower sub-semiconductor package and the upper sub-semiconductor package, a connection via in the mold via hole that penetrates the lower mold layer and the filling layer and electrically connects the lower sub-semiconductor package to the upper sub-semiconductor package. The filling layer includes an extending part of the filling layer that extends into the mold via hole of the filling layer from a portion having a higher level than a top surface of the lower mold layer. 1. A semiconductor package comprising:a lower sub-semiconductor package comprising a lower semiconductor chip, a lower mold layer on the lower semiconductor chip, and a mold via hole;an upper sub-semiconductor package comprising an upper semiconductor chip;a filling layer that is between the lower sub-semiconductor package and the upper sub-semiconductor package; anda connection via in the mold via hole that penetrates the lower mold layer and the filling layer, and electrically connects the lower sub-semiconductor package to the upper sub-semiconductor package,wherein the filling layer comprises an extending part that extends into the mold via hole from a portion of the filling layer having a higher level than a top surface of the lower mold layer.2. The semiconductor package of claim 1 , further comprising:an electromagnetic wave shielding member on a side surface of the lower sub-semiconductor package, a side surface of the filling layer, and/or side and/or top surfaces of the upper sub-semiconductor package.3. The semiconductor package of claim 2 , wherein the filling layer comprises a protruding part that protrudes farther than the ...

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Номер записи: 66

10-01-2019 дата публикации

FAN-OUT SEMICONDUCTOR PACKAGE MODULE

Номер: US20190013300A1

Автор: BAEK Yong Ho, Gong Jung Chul, HUR Young Sik, JUNG Joo Hwan, KIM Han

Принадлежит:

A fan-out semiconductor package module includes: a core member having a first through hole and a second through hole; a semiconductor chip disposed in the first through hole, and having an active surface and an inactive surface opposite the active surface, the active surface having a connection pad disposed thereon; at least one first passive component disposed in the second through hole; a first encapsulant encapsulating the core member encapsulating at least a portion of each of the core member and the at least one first passive component; a second encapsulant encapsulating at least a portion of the inactive surface of the semiconductor chip; and a connection member disposed on the core member, the active surface of the semiconductor chip, and the at least one first passive component, and including a redistribution layer electrically connected to the connection pad and the at least one first passive component. 1. A fan-out semiconductor package module comprising:a core member having a first through hole and a second through hole spaced from each other;a semiconductor chip disposed in the first through hole, the semiconductor chip having an active surface and an inactive surface opposite the active surface, the active surface having a connection pad disposed thereon;at least one first passive component disposed in the second through hole;a first encapsulant encapsulating at least a portion of each of the core member and the at least one first passive component, the first encapsulant filling at least a portion of the second through hole;a second encapsulant encapsulating at least a portion of the inactive surface of the semiconductor chip, the second encapsulant filling at least a portion of the first through hole; anda connection member disposed on the core member, the active surface of the semiconductor chip, and the at least one first passive component, the connection member including a redistribution layer electrically connected to the connection pad and the at ...

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Номер записи: 67

14-01-2021 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING DEVICE AND CIRCUIT

Номер: US20210013134A1

Автор: DERAI Michele, ZIGLIOLI Federico Giovanni

Принадлежит:

A method of manufacturing semiconductor devices such as integrated circuits comprises: providing one or more semiconductor chips having first and second opposed surfaces, coupling the semiconductor chip or chips with a support substrate with the second surface towards the support substrate, embedding the semiconductor chip or chips coupled with the support substrate in electrically-insulating packaging material by providing in the packaging material electrically-conductive passageways. The electrically-conductive passageways comprise: electrically-conductive chip passageways towards the first surface of the at least one semiconductor chip, and/or electrically-conductive substrate passageways towards the support substrate. 1. A method , comprising:coupling a semiconductor chip to a support;molding a first layer of LDS material over the semiconductor chip and the support substrate;using a laser, forming first and second through openings in the first layer of LDS material, wherein the first through opening is at a bond pad of the semiconductor chip and the second through opening is at a contact of the support;filling the first and second through openings with conductive material;forming a conductive line on a surface of the first layer of LDS material, the conductive line being coupled to the conductive material in the first and second through openings; andmolding a second layer of LDS material over the conductive material in the first and second through openings and the conductive line.2. The method of claim 1 , wherein the conductive line is sloped.3. The method of claim 1 , further comprising using the laser to form a third through opening in the second layer of LDS material claim 1 , filling the third through opening with a conductive material claim 1 , the conductive material in the third through opening is coupled to the conductive line.4. The method of claim 1 , wherein the semiconductor chip is a first semiconductor chip claim 1 , the method further comprising ...

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Номер записи: 68

14-01-2021 дата публикации

SEMICONDUCTOR PACKAGE

Номер: US20210013181A1

Автор: HAN Sanguk, JO Chajea, KIM Hyoeun, SEO Sunkyoung

Принадлежит:

A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode. 1. A semiconductor package comprising:a lower semiconductor package; andan upper semiconductor package disposed on the lower semiconductor package,wherein the lower semiconductor package includes:a circuit substrate;a first semiconductor device disposed on the circuit substrate and including a first through electrode;a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode;a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device;a second molding member covering a sidewall of the first molding member; andan upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode, andwherein the upper semiconductor package includes:a third semiconductor device; anda connection terminal electrically connected to the third semiconductor device and the upper redistribution layer.2. The semiconductor package according to claim 1 , wherein a material of the first molding member is different from a material of the second molding member claim 1 , andthe first molding member contacts the second molding member.3. The semiconductor ...

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Номер записи: 69

09-01-2020 дата публикации

THERMALLY CONDUCTIVE STRUCTURE FOR HEAT DISSIPATION IN SEMICONDUCTOR PACKAGES

Номер: US20200013636A1

Автор: Kuo Ying-Hao, Tseng Chun-Hao, Yee Kuo-Chung

Принадлежит:

A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate. An insulating barrier layer is deposited above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer. A thermally conductive layer is formed over the insulating barrier layer to at least partially encapsulate the at least one chip. 1. A method of forming a semiconductor package , comprising:providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate;depositing an insulating barrier layer above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer;forming a thermally conductive layer over the insulating barrier layer to at least partially encapsulate the at least one chip; andattaching a heat sink to the thermally conductive layer, wherein the heat sink is attached to the thermally conductive layer by a thermal interface material (TIM).2. The method of claim 1 , wherein the thermal interface material has a lower surface that is spaced apart from an upper surface of the insulating barrier layer by the thermally conductive layer.3. The method of claim 1 , wherein the at least one chip includes a first chip having a first chip height and a second chip having a second chip height claim 1 , the first and second chip heights being measured perpendicular to the upper surface of the substrate and the first chip height being greater than the second chip height.4. The method of claim 3 , wherein the thermally conductive layer has a planar upper surface that extends over an entirety of the upper surface of the substrate claim 3 , and wherein the thermally conductive layer has a first thickness over the first chip and a second thickness over the second chip claim 3 , the first and second thicknesses being measured perpendicular to the upper surface ...

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Номер записи: 70

09-01-2020 дата публикации

SEMICONDUCTOR PACKAGE

Номер: US20200013727A1

Автор: Kim Hyung Joon, Lee Sang Jong, SEO Yoon Seok

Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor package includes: a frame having first and second through-holes spaced apart from each other; passive components disposed in the first through-hole; a semiconductor chip disposed in the second through-hole and having an active surface on which connection pads are disposed and an inactive surface opposing the active surface; a first encapsulant covering at least portions of the passive components and filling at least portions of the first through-hole; a second encapsulant covering at least portions of the semiconductor chip and filling at least portions of the second through-hole; and a connection structure disposed on the frame, the passive components, and the active surface of the semiconductor chip and including wiring layers electrically connected to the passive components and the connection pads of the semiconductor chip. The second encapsulant has a higher electromagnetic wave absorption rate than that of the first encapsulant. 1. A semiconductor package comprising:a frame including first and second through-holes spaced apart from each other;passive components disposed in the first through-hole;a semiconductor chip disposed in the second through-hole and having an active surface on which connection pads are disposed and an inactive surface opposing the active surface;a first encapsulant covering at least portions of the passive components and filling at least portions of the first through-hole;a second encapsulant covering at least portions of the semiconductor chip and filling at least portions of the second through-hole; anda connection structure disposed on the frame, the passive components, and the active surface of the semiconductor chip and including wiring layers electrically connected to the passive components and the connection pads of the semiconductor chip,wherein the second encapsulant has a higher electromagnetic wave absorption rate than that of the first encapsulant.2. The semiconductor package of claim 1 , wherein the second ...

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Номер записи: 71

09-01-2020 дата публикации

SEMICONDUCTOR PACKAGE STRUCTURE WITH ANTENNA

Номер: US20200013735A1

Автор: Chi Yen-Yao, HSU Wen-Sung, Kao Yeh-Chun, LIN Tzu-Hung, LIU Nai-Wei, Yeh Shih-Huang

Принадлежит: MEDIATEK INC.

A semiconductor package structure is provided. The semiconductor package structure includes a first redistribution layer (RDL) structure formed on a non-active surface of a semiconductor die. A second RDL structure is formed on and electrically coupled to an active surface of the semiconductor die. A ground layer is formed in the first RDL structure. A first molding compound layer is formed on the first RDL structure. A first antenna includes a first antenna element formed in the second RDL structure and a second antenna element formed on the first molding compound layer. Each of the first antenna element and the second antenna element has a first portion overlapping the semiconductor die as viewed from a top-view perspective. 1. A semiconductor package structure , comprising:a semiconductor die;a first redistribution layer (RDL) structure formed on a non-active surface of the semiconductor die;a second RDL structure formed on and electrically coupled to an active surface of the semiconductor die;a ground layer formed in the first RDL structure;a first molding compound layer formed on the first RDL structure; and a first antenna element formed in the second RDL structure; and', 'a second antenna element formed on the first molding compound layer,', 'wherein each of the first antenna element and the second antenna element has a first portion overlapping the semiconductor die as viewed from a top-view perspective., 'a first antenna, comprising2. The semiconductor package structure as claimed in claim 1 , wherein each of the first antenna element and the second antenna element has a second portion adjoining the first portion claim 1 , and wherein the ground layer has a through-opening overlapping the second portion as viewed from a top-view perspective.3. The semiconductor package structure as claimed in claim 1 , further comprising:a second molding compound layer surrounding the semiconductor die;a through via structure formed in the second molding compound layer and ...

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Номер записи: 72

09-01-2020 дата публикации

Semiconductor device with thin redistribution layers

Номер: US20200013739A1

Автор: Do Hyung Kim, Dong Hoon Lee, Seung Chul Han

Принадлежит: Amkor Technology Singapore Holding Pte Ltd

A semiconductor device with thin redistribution layers is disclosed and may include forming a first redistribution layer on a dummy substrate, electrically coupling a semiconductor die to the first redistribution layer, and forming a first encapsulant layer on the redistribution layer and around the semiconductor die. The dummy substrate may be removed thereby exposing a second surface of the first redistribution layer. A dummy film may be temporarily affixed to the exposed second surface of the redistribution layer and a second encapsulant layer may be formed on the exposed top surface of the semiconductor die, a top surface and side edges of the first encapsulant layer, and side edges of the first redistribution layer. The dummy film may be removed to again expose the second surface of the first redistribution layer, and a second redistribution layer may be formed on the first redistribution layer and on the second encapsulant layer.

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Номер записи: 73

09-01-2020 дата публикации

Semiconductor Package

Номер: US20200013743A1

Автор: BAEK Yong Ho, HUR Young Sik, KIM Doo Il, So Won Wook

Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor package includes a semiconductor chip including a body, a connection pad, a passivation film, a first connection bump disposed, and a first coating layer; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure including an insulating layer, a redistribution layer, and a connection via. The first connection bump includes a low melting point metal, the redistribution layer and the connection via include a conductive material, and the low melting point metal has a melting point lower than a melting point of the conductive material. 1. A semiconductor package , comprising:a semiconductor chip including a body having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, a passivation film disposed on the active surface of the body and covering at least a portion of the connection pad, a first connection bump disposed on the passivation film and electrically connected to the connection pad, and a first coating layer disposed on the passivation film and covering at least a portion of a side surface of the first connection bump;an encapsulant covering at least a portion of the semiconductor chip; anda connection structure including an insulating layer disposed on the first coating layer of the semiconductor chip, a redistribution layer disposed on the insulating layer, and a connection via passing through the insulating layer and electrically connecting the first connection bump to the redistribution layer,wherein the first connection bump includes a low melting point metal,the redistribution layer and the connection via include a conductive material, andthe low melting point metal has a melting point lower than a melting point of the conductive material.2. The semiconductor package of claim 1 , wherein the low melting point metal includes a solder claim 1 , andthe conductive material includes copper (Cu).3. The semiconductor package of claim 1 , wherein a ...

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Номер записи: 74

09-01-2020 дата публикации

METHOD OF MANUFACTURING 3DIC STRUCTURE

Номер: US20200013746A1

Автор: Chen Hsien-Wei, Chen Ming-Fa, Yeh Sung-Feng

Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A method of manufacturing a 3DIC structure includes the following processes. A die is bonded to a wafer. A first dielectric layer is formed on the wafer and laterally aside the die. A second dielectric material layer is formed on the die and the first dielectric layer. A portion of the second dielectric material layer over a non-edge region of the wafer is selectively removed to form a protruding portion over an edge region of the wafer. The second dielectric material layer is planarized to form a second dielectric layer on the first dielectric layer and the die. A bonding film is formed on the second dielectric layer. A carrier is bonded to the wafer through the bonding film. 1. A method of manufacturing a 3DIC structure , comprising:bonding a die to a wafer;forming a first dielectric layer on the wafer and laterally aside the die;forming a second dielectric material layer on the die and the first dielectric layer;selectively removing a portion of the second dielectric material layer over a non-edge region of the wafer to form a protruding portion over an edge region of the wafer; andplanarizing the second dielectric material layer to form a second dielectric layer on the first dielectric layer and the die.2. The method of claim 1 , where the selectively removing the portion of the second dielectric material layer comprises:forming a mask layer on the second dielectric material layer;pattering the mask layer to form a patterned mask layer having an opening, wherein the patterned mask layer covers the second dielectric material layer on the edge region of the wafer, and the opening exposes the portion of the second dielectric material layer over the non-edge region of the wafer;etching the portion of the second dielectric material layer exposed by the opening, wherein the second dielectric material layer covered by the patterned mask layer form the protruding portion; andremoving the patterned mask layer.3. The method of claim 1 , wherein the planarizing the second ...

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Номер записи: 75

09-01-2020 дата публикации

CHIP PACKAGE AND METHOD OF FORMING A CHIP PACKAGE WITH A METAL CONTACT STRUCTURE AND PROTECTIVE LAYER, AND METHOD OF FORMING AN ELECTRICAL CONTACT

Номер: US20200013749A1

Автор: Bauer Michael, Dangelmaier Jochen, ENGL Reimund, Gatterbauer Johann, HILLE Frank, HUETTINGER Michael, KANERT Werner, Koerner Heinrich, Mahler Joachim, RUEHLE Brigitte, Santos Rodriguez Francisco Javier, Vellei Antonio

Принадлежит:

In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure. 1. A method of forming an electrical contact , comprising:arranging an intermediate layer on the metal surface;arranging a metal contact structure over or on a metal surface; andplating a metal layer on the metal surface and on the metal contact structure, thereby fixing the metal contact structure to the metal surface and forming an electrical contact between the metal contact structure and the metal surface or strengthening or thickening an existing electrical contact between the metal contact structure and the metal surface.2. The method of claim 1 , further comprising:before plating the metal layer on the metal surface and on the metal contact structure, treating the metal surface and the metal contact structure by a process involving wet chemistry, dry chemistry, and/or a plasma in order to prepare a surface of the metal surface and of the metal contact structure for the plating.3. The method of claim 1 , wherein the metal contact structure claim 1 , the metal surface and/or a metallization material comprises or consists of copper.4. The method of claim 1 , wherein the metal contact structure may contain or consist of the same metal as the metal surface.5. The method of claim 3 , wherein the metallization comprises a galvanic deposit or an electroless deposit.6. The method of ...

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Номер записи: 76

19-01-2017 дата публикации

Die Packages and Methods of Manufacture Thereof

Номер: US20170018476A1

Автор: WANG Chuei-Tang, Yu Chen-Hua

Принадлежит:

Die packages and method of manufacturing the same are disclosed. In an embodiment, a method of manufacturing a die package may include forming an encapsulated via structure including at least one via, a polymer layer encapsulating the at least one via, and a first molding compound encapsulating the polymer layer; placing the encapsulated via structure and a first die stack over a carrier, the at least one via having a first end proximal the carrier and a second end distal the carrier; encapsulating the first die stack and the encapsulated via structure in a second molding compound; and forming a first redistribution layer (RDL) over the second molding compound, the first RDL electrically connecting the at least one via. 1. A device , comprising:an encapsulated via structure comprising at least one via, a polymer layer encapsulating the at least one via, and a first molding compound encapsulating the polymer layer;a first die stack adjacent the encapsulated via structure and having a topmost surface substantially level with a topmost surface of the encapsulated via structure;a second molding compound encapsulating the first die stack and the encapsulated via structure; anda first redistribution layer (RDL) over the second molding compound, the first RDL electrically connected to the at least one via.2. The device of claim 1 , further comprising a plurality of first conductive pillars disposed between a first surface of the first die stack and the first RDL claim 1 , the plurality of first conductive pillars electrically coupled to the first die stack.3. The device of claim 1 , wherein the first die stack is laterally separated from the encapsulated via structure.4. The device of claim 1 , further comprising a second RDL underlying the first die stack claim 1 , the second RDL electrically connected to the at least one via.5. The device of claim 4 , further comprising a plurality of connectors underlying the second RDL.6. The device of claim 1 , further comprising a ...

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Номер записи: 77

21-01-2016 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20160020181A1

Автор: CHAN WEN-HSIN, HSIEH CHEN-CHIH, Shih Chao-Wen, Tsai Hao-Yi, YU Tsung-Yuan

Принадлежит:

A semiconductor device includes a substrate defined with a seal ring region and a circuit region, the substrate includes a seal ring structure and an integrated circuit structure, the seal ring structure is disposed in the seal ring region and includes a plurality of stacked conductive layers interconnected by a plurality of via layers, the integrated circuit structure is disposed in the circuit region and includes an active or a passive device; a metal pad disposed over the seal ring region and contacted with the seal ring structure; a passivation layer disposed over the substrate and covering the metal pad; a polymeric layer disposed over the passivation layer and the circuit region; and a molding disposed over the passivation layer and the polymeric layer, wherein the seal ring structure is covered by the molding.

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Номер записи: 78

19-01-2017 дата публикации

Electronic component device

Номер: US20170018533A1

Автор: Shota MIKI

Принадлежит: Shinko Electric Industries Co Ltd

An electronic component device includes a first electronic component, a second electronic component disposed on and connected to the first electronic component, a first underfill resin filled between the first electronic component and the second electronic component, the first underfill resin having a base part arranged around the second electronic component and a convex portion formed on an upper surface of the base part, a third electronic component disposed on and connected to the second electronic component with being in contact with the convex portion of the base part at a peripheral edge portion thereof, and a second underfill resin filled between the second electronic component and the third electronic component.

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Номер записи: 79

03-02-2022 дата публикации

Packaged Semiconductor Device Including Liquid-Cooled Lid and Methods of Forming the Same

Номер: US20220037231A1

Автор: Hsiao Sheng-Tsung, Shao Tung-Liang, Tung Chih-Hang, Wang Jen Yu, Wu Chung-Jung

Принадлежит:

Semiconductor devices including lids having liquid-cooled channels and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first integrated circuit die; a lid coupled to the first integrated circuit die, the lid including a plurality of channels in a surface of the lid opposite the first integrated circuit die; a cooling cover coupled to the lid opposite the first integrated circuit die; and a heat transfer unit coupled to the cooling cover through a pipe fitting, the heat transfer unit being configured to supply a liquid coolant to the plurality of channels through the cooling cover. 1. A semiconductor device comprising:a first integrated circuit die;a lid coupled to the first integrated circuit die, the lid comprising a plurality of channels in a surface of the lid opposite the first integrated circuit die;a cooling cover coupled to the lid opposite the first integrated circuit die; anda heat transfer unit coupled to the cooling cover through a pipe fitting, wherein the heat transfer unit is configured to supply a liquid coolant to the plurality of channels through the cooling cover.2. The semiconductor device of claim 1 , wherein the lid is coupled to the first integrated circuit die by dielectric-to-dielectric bonds.3. The semiconductor device of claim 1 , further comprising an encapsulant laterally surrounding the first integrated circuit die claim 1 , wherein the lid is coupled to the encapsulant by dielectric-to-dielectric bonds.4. The semiconductor device of claim 1 , further comprising an encapsulant laterally surrounding the first integrated circuit die claim 1 , wherein a width of the lid is equal to a width of the first integrated circuit die.5. The semiconductor device of claim 1 , further comprising an encapsulant laterally surrounding the first integrated circuit die claim 1 , wherein a width of the lid is equal to a width of the cooling cover and greater than a width of the encapsulant.6. The semiconductor ...

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Номер записи: 80

03-02-2022 дата публикации

Semiconductor device package and method of manufacturing the same

Номер: US20220037244A1

Автор: Li-Hua TAI, Wen-Pin Huang

Принадлежит: Advanced Semiconductor Engineering Inc

The present disclosure provides a semiconductor device package. The semiconductor device package includes a first substrate and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface of the first substrate. The second substrate has a first surface facing the first substrate and a second surface opposite to the first surface of the second substrate. The semiconductor device package also includes a first electronic component disposed on the first surface of the second substrate and electrically connected to the first surface of the second substrate. The semiconductor device package also includes a first encapsulant and a second encapsulant between the first substrate and the second substrate. The first encapsulant is different from the second encapsulant. A method of manufacturing a semiconductor device package is also disclosed.

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Номер записи: 81

03-02-2022 дата публикации

FLEXIBLE CIRCUITS ON SOFT SUBSTRATES

Номер: US20220037278A1

Автор: MAHAJAN Ankit, Meyers Kara A., Niccum Kayla C., Pekurovsky Mikhail L., PITERA Gino L., Rowe David J., Shah Saagar A., Taylor Daniel B.

Принадлежит:

An article includes a solid circuit die on a first major surface of a substrate, wherein the solid circuit die includes an arrangement of contact pads, and wherein at least a portion of the contact pads in the arrangement of contact pads are at least partially exposed on the first major surface of the substrate to provide an arrangement of exposed contact pads; a guide layer including an arrangement of microchannels, wherein the guide layer contacts the first major surface of the substrate such that at least some microchannels in the arrangement of microchannels overlie the at least some exposed contact pads in the arrangement of exposed contact pads; and a conductive particle-containing liquid in at least some of the microchannels. Other articles and methods of manufacturing the articles are described. 1. An article , comprising:a solid circuit die on a first major surface of a substrate, wherein the solid circuit die comprises an arrangement of contact pads, and wherein at least a portion of the contact pads in the arrangement of contact pads are at least partially exposed on the first major surface of the substrate to provide an arrangement of exposed contact pads;a guide layer comprising an arrangement of microchannels, wherein the guide layer contacts the first major surface of the substrate such that at least some microchannels in the arrangement of microchannels overlie the at least some exposed contact pads in the arrangement of exposed contact pads; anda conductive particle-containing liquid in at least some of the microchannels.2. The article of claim 1 , wherein the solid circuit die is at least partially embedded in the first major surface of the substrate.3. The article of claim 1 , wherein the solid circuit die is embedded in the first major surface of the substrate.4. The article of claim 1 , wherein the substrate comprises a flexible polymeric material.5. The article of claim 1 , wherein the guide layer comprises a layer of a polymeric material and a ...

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Номер записи: 82

18-01-2018 дата публикации

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20180019175A1

Автор: Appelt Bernd Karl, ESSIG Kay Stefan

Принадлежит: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

A semiconductor package device includes a first die having a first surface and a second surface opposite to the first surface, and a first adhesive layer disposed on the first surface of the first die. The semiconductor package device further includes an encapsulant layer encapsulating the first die and the first adhesive layer, and a first conductive via disposed in the first adhesive layer and electrically connected to the first die. 1. A semiconductor package device , comprising:a first die, having a first surface and a second surface opposite to the first surface;a first adhesive layer disposed on the first surface of the first die;an encapsulant layer encapsulating the first die and the first adhesive layer; anda first conductive via disposed in the first adhesive layer and electrically connected to the first die.2. The semiconductor package device of claim 1 , further comprising a first conductive layer disposed on the second surface of the first die and covering substantially the entire second surface of the first die claim 1 , wherein the first conductive layer has a first surface and a second surface opposite to the first surface and exposed from the encapsulant layer claim 1 , the first surface of the first conductive layer directly contacts the second surface of the first die and the second surface of the first conductive layer is substantially coplanar with a first surface of the encapsulant layer.3. The semiconductor package device of claim 2 , further comprising a second conductive via disposed in the first die claim 2 , wherein the second conductive via is electrically connected to the first conductive layer and the first conductive via.4. The semiconductor package device of claim 1 , further comprising a first conductive layer disposed on the encapsulant layer claim 1 , wherein the conductive layer covers substantially an entire surface of the encapsulant layer.5. The semiconductor package device of claim 4 , further comprising:a patterned conductive ...

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Номер записи: 83

18-01-2018 дата публикации

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

Номер: US20180019191A1

Автор: Katkar Rajesh, Uzoh Cyprian Emeka

Принадлежит: INVENSAS CORPORATION

A solder connection may be surrounded by a solder locking layer () and may be recessed in a hole () in that layer. The recess may be obtained by evaporating a vaporizable portion () of the solder connection. Other features are also provided. 1. A manufacturing method comprising: one or more first components each of which comprises solder and a material sublimatable or vaporizable when the solder is melted; and', 'a first layer comprising a top surface and one or more holes in the top surface, each hole containing at least a segment of a corresponding first component;, 'obtaining a first structure comprisingheating each first component to sublimate or vaporize at least part of each sublimatable or vaporizable material and provide an electrically conductive connection at a location of each first component;wherein in the heating operation at least part of each first component recedes down from the top surface to provide or increase a recess in each hole at the top surface.2. The method of wherein each hole is a through-hole.3. The method of wherein each hole's sidewall is a dielectric sidewall.4. The method of wherein the first layer is dielectric.5. The method of wherein the first layer is formed by molding.6. The method of further comprising:obtaining a second structure with one or more protruding conductive posts; andinserting each conductive post into a corresponding recess provided or increased in the heating operation, and forming a solder bond in each recess between the corresponding conductive post and the corresponding electrically conductive connection.7. The method of wherein before the heating operation claim 1 , at least a segment of each first component either:comprises of a solder core coated with the sublimatable or vaporizable material; orconsists of the sublimatable or vaporizable material.8. The method of wherein in obtaining the first structure claim 7 , the one or more first components are formed before the first layer.9. The method of wherein in ...

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Номер записи: 84

18-01-2018 дата публикации

Semiconductor package device and method of manufacturing the same

Номер: US20180019221A1

Автор: Bernd Karl Appelt, Chi-Tsung Chiu, Kay Stefan ESSIG

Принадлежит: Advanced Semiconductor Engineering Inc

A semiconductor package device includes a first die, an adhesive layer, and an encapsulant layer. The first die comprises a first electrode at a first surface of the first die and a second electrode at a second surface of the first die opposite to the first surface of the first die. The adhesive layer is disposed on the first surface of the first die. The encapsulant layer encapsulates the first die and the adhesive layer, wherein substantially an entire surface of the second electrode is exposed from the encapsulant layer.

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Номер записи: 85

22-01-2015 дата публикации

Substrate for semiconductor package and process for manufacturing

Номер: US20150021766A1

Автор: Chun-Che Lee, Sheng-Ming Wang, Tien-Szu Chen

Принадлежит: Advanced Semiconductor Engineering Inc

A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.

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Номер записи: 86

17-01-2019 дата публикации

Semiconductor device and optical coupling device

Номер: US20190019784A1

Автор: Naoya Takai

Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor device includes a first semiconductor element having a first surface, a second semiconductor element having a lower surface bonded to the first surface of the first semiconductor element, a gel-like silicone that covers an upper surface of the second semiconductor element, and a resin portion that covers the gel-like silicone and the first surface of the first semiconductor element.

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Номер записи: 87

21-01-2021 дата публикации

SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20210020533A1

Автор: Lu Wen-Long

Принадлежит: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

A semiconductor device package includes an electronic component, an encapsulation layer encapsulating the electronic component, and a passivation layer stacking with the encapsulation layer. The passivation layer has a first surface facing the encapsulation layer, a second surface opposite to the first surface, and a first sidewall connecting the first surface and the second surface. The first sidewall inclines with respect to the second surface, and a first projection width of the encapsulation layer is greater than a second projection width of the passivation layer. 1. A semiconductor device package , comprising:an electronic component;an encapsulation layer encapsulating the electronic component; anda passivation layer stacking with the encapsulation layer, wherein the passivation layer has a first surface facing the encapsulation layer, a second surface opposite to the first surface, and a first sidewall connecting the first surface and the second surface, the first sidewall inclining with respect to the second surface, wherein a first projection width of the encapsulation layer is greater than a second projection width of the passivation layer.2. The semiconductor device package of claim 1 , wherein the second surface is smaller than the first surface.3. The semiconductor device package of claim 1 , wherein the encapsulation layer has a third surface facing the passivation layer claim 1 , a fourth surface opposite to the third surface claim 1 , and a second sidewall connecting the third surface and the fourth surface.4. The semiconductor device package of claim 3 , wherein the encapsulation layer hangs over the passivation layer.5. The semiconductor device package of claim 3 , wherein a surface roughness of the second sidewall of the encapsulation layer is larger than a surface roughness of the first sidewall of the passivation layer.6. The semiconductor device package of claim 3 , wherein the third surface is larger than the fourth surface.7. The semiconductor ...

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Номер записи: 88

21-01-2021 дата публикации

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20210020594A1

Автор: CHEN Cheng Yuan, Chiu Chi-Tsung, HSIEH Hui-Ying, LEE Hui Hua

Принадлежит: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

A semiconductor package structure includes a base material, at least one semiconductor chip, an encapsulant, a depression structure, a redistribution layer and at least one conductive via. The semiconductor chip is disposed on the base material. The encapsulant is disposed on the base material and covers the at least one semiconductor chip. The encapsulant has an outer side surface. The depression structure is disposed adjacent to and exposed from of the outer side surface the encapsulant. The redistribution layer is disposed on the encapsulant. The conductive via is disposed in the encapsulant and electrically connects the semiconductor chip and the redistribution layer. 1. A semiconductor package structure , comprising:a base material;at least one semiconductor chip disposed on the base material;an encapsulant disposed on the base material and covering the at least one semiconductor chip;a redistribution layer disposed on the encapsulant and having an outer side surface;a wetting layer disposed on the outer side surface of the redistribution layer; andat least one conductive via disposed in the encapsulant and electrically connecting the at least one semiconductor chip and the redistribution layer.2. The semiconductor package structure of claim 1 , wherein the base material is a lead frame or an organic substrate.3. The semiconductor package structure of claim 1 , wherein the base material defines a cavity claim 1 , and the at least one semiconductor chip is disposed in the cavity.4. The semiconductor package structure of claim 1 , wherein the at least one semiconductor chip has an active surface and a backside surface opposite to the active surface claim 1 , the backside surface of the at least one semiconductor chip is attached to the base material claim 1 , the active surface of the at least one semiconductor chip faces the redistribution layer claim 1 , and the at least one conductive via is electrically connected to the active surface of the at least one ...

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Номер записи: 89

21-01-2021 дата публикации

SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF

Номер: US20210020605A1

Автор: Do Won Chul, Hiner David, Huemoeller Ronald, KELLY MICHAEL, Khim Jin Young, Lee Sang Hyoun, Mok In Su

Принадлежит:

A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a connect die that routes electrical signals between a plurality of other semiconductor die. 1. An electronic device comprising:a signal redistribution structure (SRS) comprising a top SRS side, a bottom SRS side, and a plurality of lateral SRS sides, where the signal redistribution structure is coreless;a lower electronic component (LEC) comprising a top LEC side, a bottom LEC side, and a plurality of lateral LEC sides, where the top LEC side is coupled to the bottom SRS side;a vertical interconnect structure coupled to the bottom SRS side at a position that is laterally offset from the lower electronic component;an LEC interconnect structure that is coupled to the top LEC side and to the bottom SRS side, such that the lower electronic component is electrically coupled to the signal redistribution structure through at least the LEC interconnect structure;a semiconductor die comprising a top die side, a bottom die side, and a plurality of lateral die sides;a first die interconnect structure coupled to the top SRS side and to the bottom die side, such that the semiconductor die is electrically coupled to the vertical interconnect structure; anda second die interconnect structure coupled to the top SRS side and to the bottom die side, such that the semiconductor die is electrically coupled to the lower electronic component.2. The electronic device of claim 1 , wherein:the semiconductor die is electrically coupled to the vertical interconnect structure through at least the first die interconnect structure and the signal redistribution structure; andthe semiconductor die is electrically coupled to the lower electronic component through at least the second die interconnect structure, the signal redistribution structure, and the LEC ...

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Номер записи: 90

26-01-2017 дата публикации

RESIN-ENCAPSULATD SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20170025320A1

Автор: Kimura Noriyuki

Принадлежит:

A first resin encapsulated body () and a second resin encapsulated body () are stacked to form a resin-encapsulated semiconductor device. The first resin encapsulated body () includes: a first semiconductor element (); an external terminal (); inner wiring (); and a first resin () for covering those components, at least a rear surface of the external terminal (), a rear surface of the semiconductor element (), and a surface of the inner wiring () are exposed from the first resin (). The second resin encapsulated body () includes: a second semiconductor element () having an electrode pad formed on a surface thereof; a second resin () for covering the second semiconductor element; and a metal body connected to the electrode pad, and is partly exposed from the second resin. The inner wiring and the metal body are electrically connected to each other. 1. A method of manufacturing a resin-encapsulated semiconductor device including a first resin encapsulated body and a second resin encapsulated body , the method comprising:forming a plurality of inner wiring lines on one main surface of a substrate;forming an external terminal on a part of a surface of at least one inner wiring line of the plurality of inner wiring lines on a side opposite to the substrate;connecting electrically a first semiconductor element and the plurality of inner wiring lines to each other;encapsulating, in a first resin, the one main surface side of the substrate on which the plurality of inner wiring lines, the external terminal, and the first semiconductor element are arranged;grinding a surface of the first resin opposite to a surface on which the first resin is in contact with the substrate, to thereby expose a rear surface of the external terminal and a surface of the first semiconductor element opposite to a face side thereof;opening another main surface of the substrate except for edge portions thereof, to thereby expose the plurality of inner wiring lines and the first resin;connecting ...

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Номер записи: 91

26-01-2017 дата публикации

LOCALIZED STRAIN RELIEF FOR AN INTEGRATED CIRCUIT

Номер: US20170025497A1

Автор: "OCONNOR Denis M.", "ODONNELL John Jude", FITZGERALD Padraig L., KIERSE Oliver J., Poucher Patrick F.M.

Принадлежит:

An integrated circuit may include a semiconductor die having a trench formed in a surface of the semiconductor die. One or more circuit components may be formed on the surface of the semiconductor die. The trench can extend into the semiconductor die next to at least one circuit component. The trench may surround the circuit component partially or wholly. The trench may be filled with a material having a lower bulk modulus than the semiconductor die in which the trench is formed. 1. (canceled)2. An integrated circuit comprising:a semiconductor die;one or more circuit components formed in a surface of the semiconductor die;a protective layer deposited over the one or more circuit components in the semiconductor die;a cap disposed over the one or more circuit components to protect the one or more circuit components, the cap being bonded to the protective layer; andan encapsulating material disposed over the cap and the protective layer.3. The integrated circuit of claim 2 , wherein the protective layer comprises an oxide layer deposited over the one or more circuit components.4. The integrated circuit of claim 2 , wherein the one or more circuit components comprises a transistor.5. The integrated circuit of claim 2 , wherein the one or more circuit components experiences electrical drift when subjected to mechanical strains.6. The integrated circuit of claim 2 , further comprising at least one trench formed in a surface of the semiconductor die claim 2 , the at least one trench disposed adjacent the one or more circuit components.7. The integrated circuit of claim 6 , wherein a space in the at least one trench is filled with a gas.8. The integrated circuit of claim 6 , wherein the at least one trench at least partially surrounds one or more of the circuit components.9. The integrated circuit of claim 6 , wherein the at least one trench extends into the semiconductor die such that a bottom of the at least one trench extends below at least one circuit component next to ...

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Номер записи: 92

25-01-2018 дата публикации

Integrated Circuit Packages and Methods for Forming the Same

Номер: US20180025959A1

Автор: Chen Hsien-Wei, Kuo Yian-Liang, Lu Wen-Hsiung, TSAI Tsung-Fu, TU Chia-Wei

Принадлежит:

A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies. 1. A chip comprising:a substrate;a metal pad over the substrate;a passivation layer having a portion over the metal pad;a polymer layer over the passivation layer, wherein the polymer layer extends to an edge of the chip, and a first edge of the polymer layer forms a part of the edge of the chip;an electrical connector; and a first horizontal surface substantially perpendicular to the edge of the chip; and', 'a slant sidewall surface, wherein the first horizontal surface is connected to a first end of the slant sidewall surface, and the slant sidewall surface is neither perpendicular to nor parallel to the edge of the chip., 'a molding compound encircling a portion of the electrical connector, wherein a lower portion of the electrical connector is in the molding compound, and wherein the molding compound comprises a surface comprising2. The chip of further comprising a second horizontal surface substantially perpendicular to the edge of the chip claim 1 , wherein the second horizontal surface is connected to a second end of the slant sidewall surface claim 1 , and the first horizontal surface claim 1 , the slant sidewall surface claim 1 , and the second horizontal surface form a step.3. The chip of claim 1 , wherein the first horizontal surface extends to the electrical connector.4. The chip of further comprising:a plurality of dielectric layers underlying the metal pad; anda seal ring proximal edges of the chip, wherein the seal ring extends into the plurality of dielectric layers.5. The chip of claim 4 , wherein the molding compound comprises:first portions on opposite sides of electrical connector, ...

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Номер записи: 93

25-01-2018 дата публикации

3D Semiconductor Package Interposer with Die Cavity

Номер: US20180026008A1

Автор: Chen Kim Hong, Hou Shang-Yun, Huang Szu-Po, Hung Wensen, Jeng Shin-Puu

Принадлежит:

Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects. 1. A device , comprising:a substrate having a top surface;an interposer over the top surface of the substrate, the interposer being connected to the substrate by first interconnects;a first integrated circuit die connected to a first side of the interposer by first connectors;a second integrated circuit die connected to a second side of the interposer opposite the first side by second connectors, the second integrated circuit die having a smaller footprint than the interposer; anda fan-out structure disposed over a top surface of the interposer and extending beyond outermost edges of the interposer, wherein the fan-out structure is electrically connected to second interconnects, the second interconnects in contact with the top surface of the substrate.2. The device of claim 1 , further comprising third connectors connecting the fan-out structure to the second integrated circuit die.3. The device of claim 1 , further comprising a cavity in the top surface of the substrate claim 1 , wherein the first integrated circuit die extends into the cavity.4. The device of claim 1 , further comprising:a first molding compound on sidewalls of the interposer, the first interconnects, and the second interconnects; anda second molding compound on the first molding compound, the fan-out structure, and the second integrated circuit die.5. The device of claim 1 , ...

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Номер записи: 94

10-02-2022 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Номер: US20220045037A1

Автор: Ki Won Myoung, LEE IL BOK, Lee Won Geol, Mok In Su

Принадлежит: Amkor Technology Singapore Holding Pte. Ltd.

In one example, a semiconductor device comprises a base assembly comprising a first substrate, a first device on a top surface of the first substrate, and a first encapsulant on the top surface of the first substrate and bounding a side surface of the first device. The semiconductor device further comprises a conductive pillar on the first substrate and in the first molding compound, wherein the conductive pillar comprises a non-conductive pillar core and a conductive pillar shell on the pillar core. 1. (canceled)2. A semiconductor device , comprising: a first substrate,', 'a first device on a top surface of the first substrate, and', 'a first encapsulant on the top surface of the first substrate and bounding a side surface of the first device; and', 'a conductive pillar on the first substrate and in the first encapsulant;, 'a base assembly comprising'} the conductive pillar comprises a non-conductive pillar core and a conductive pillar shell on the non-conductive pillar core; and', 'the non-conductive pillar core does not extend above a top side of the first encapsulant., 'wherein3. The semiconductor device of claim 2 , further comprising a conductor on a top end of the non-conductive pillar core.4. The semiconductor device of claim 3 , wherein the conductor and the conductive pillar shell comprise the same material.5. The semiconductor device of claim 3 , wherein the conductor comprises a portion of the conductive pillar shell.6. The semiconductor device of claim 2 , wherein a top end of the non-conductive pillar core is below a top side of the first encapsulant.7. The semiconductor device of claim 2 , wherein:a top end of the conductive pillar shell is exposed from the first encapsulant; anda top end of the non-conductive pillar core is covered by the top end of the conductive pillar shell.8. The semiconductor device of claim 2 , further comprising:a top assembly comprisinga second substrate,a second device on a top surface of the second substrate, anda second ...

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Номер записи: 95

24-01-2019 дата публикации

FAN-OUT SEMICONDUCTOR PACKAGE AND PACKAGE SUBSTRATE COMPRISING THE SAME

Номер: US20190027419A1

Автор: Jung Hyun Chul, Lee Chang Bo, Oh Joon Seok, YEO Jeong Ho

Принадлежит:

A fan-out semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the inactive surface of the semiconductor chip; a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip; a reinforcing plate disposed on the encapsulant and having a first surface facing the inactive surface of the semiconductor chip and a second surface opposing the first surface; and rigid patterns formed on at least one of the first surface and the second surface of the reinforcing plate. 1. A fan-out semiconductor package comprising:a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;an encapsulant encapsulating at least portions of the inactive surface of the semiconductor chip;a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip;a reinforcing plate disposed on the encapsulant and having a first surface facing the inactive surface of the semiconductor chip and a second surface opposing the first surface; andrigid patterns disposed on at least one of the first surface and the second surface of the reinforcing plate.2. The fan-out semiconductor package of claim 1 , wherein the reinforcing plate has an elastic modulus greater than that of the encapsulant.3. The fan-out semiconductor package of claim 1 , wherein the reinforcing plate includes a glass fiber claim 1 , an inorganic filler claim 1 , and an insulating resin.4. The fan-out semiconductor package of claim 3 , further comprising a resin layer disposed on the second surface of the reinforcing plate claim 3 ,wherein the resin layer includes ...

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Номер записи: 96

24-01-2019 дата публикации

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20190027449A1

Автор: Chang Shou-Zen, CHUANG NAN-CHIN, Shih Chao-Wen, Wan Albert

Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A package structure includes at least one die, an antenna element, and at least one through interlayer via. The antenna element is located on the at least one die. The at least one through interlayer via is located between the antenna element and the at least one die, wherein the antenna element is electrically connected to the at least one die through the at least one through interlayer via. 1. A package structure , comprising:a molding compound;an antenna element molded in the molding compound;at least one die located on the molding compound;a redistribution layer located between the at least one die and the molding compound, wherein the redistribution layer includes a ground plane portion and a location of the antenna element is overlapped with a location of the ground plane portion in a vertical projection on the redistribution layer; andconductive elements connected to a first side of the redistribution layer, wherein the at least one die is connected to the first side of the redistribution layer, and positioning locations of the conductive elements are aside of a positioning location of the at least one die in the vertical projection.2. The package structure of claim 1 , further comprising at least one through interlayer via encapsulated in the molding compound claim 1 , wherein the at least one through interlayer via is connected to the antenna element and the antenna element is electrically connected to the at least one die through the redistribution layer and the at least one through interlayer via.3. The package structure of claim 1 , wherein the location of the antenna element is overlapped with a location of the at least one die in the vertical projection.4. The package structure of claim 1 , wherein the redistribution layer is located between the conductive elements and the antenna element.5. The package structure of claim 1 , further comprising a protective layer located on the molding compound and covering the antenna element.6. A package structure ...

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Номер записи: 97

24-01-2019 дата публикации

System on Integrated Chips and Methods of Forming Same

Номер: US20190027465A1

Автор: Chen Ming-Fa, Yeh Sung-Feng, Yu Chen-Hua

Принадлежит:

An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die. 1. A package comprising:a first semiconductor die;a second semiconductor die bonded to the first semiconductor die, wherein a first dielectric layer of the first semiconductor die is directly bonded to a second dielectric layer of the second semiconductor die;a third semiconductor die bonded to the first semiconductor die, wherein the first dielectric layer of the first semiconductor die is directly bonded to a third dielectrics layer of the third semiconductor die;a first isolation material disposed around the second semiconductor die and the third semiconductor die, wherein the second semiconductor die is physically separated from the third semiconductor die by the first isolation material; anda redistribution structure electrically connected to the first semiconductor die, the second semiconductor die, and the third semiconductor die.2. The package of claim 1 , wherein the redistribution structure is disposed on an opposing side of the first semiconductor die as the second semiconductor die and the third semiconductor die.3. The package of claim 1 , wherein the redistribution structure is electrically connected to the second semiconductor die by a conductive via extending through a second isolation material claim 1 , and wherein the first semiconductor die is physically separated from the conductive via by the second isolation material.4. The package of claim 3 , wherein the second ...

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Номер записи: 98

23-01-2020 дата публикации

PLATING INTERCONNECT FOR SILICON CHIP

Номер: US20200027737A1

Автор: JR. Antonio Rosario, Malado Jerard Canuto, Taloban

Принадлежит:

A system, method, and silicon chip package for providing connections between a die of a silicon chip package and external leads of the silicon chip package is disclosed. The connections are formed using a pre-mold etched with a trace pattern. The trace pattern provides rigid traces that connect the die with the external leads.

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Номер записи: 99

28-01-2021 дата публикации

Integrated Circuit Package and Method of Forming Same

Номер: US20210028081A1

Автор: Lu Szu-Wei, Shih Ying-Ching, Wu Chih-Wei, Yu Chen-Hua

Принадлежит:

An integrated circuit package and a method of forming the same are provided. A method includes stacking a plurality of integrated circuit dies on a wafer to form a die stack. A bonding process is performed on the die stack. The bonding process mechanically and electrically connects adjacent integrated circuit dies of the die stack to each other. A dam structure is formed over the wafer. The dam structure surrounds the die stack. A first encapsulant is formed over the wafer and between the die stack and the dam structure. The first encapsulant fills gaps between the adjacent integrated circuit dies of the die stack. A second encapsulant is formed over the wafer. The second encapsulant surrounds the die stack, the first encapsulant and the dam structure. 1. A package comprising:a substrate;a dam structure attached to the substrate, the dam structure being an annular structure;a die stack extending through the dam structure and attached to the substrate, a topmost surface of the die stack being above a topmost surface of the dam structure; anda first encapsulant surrounding the die stack and extending through the dam structure.2. The package of claim 1 , wherein the first encapsulant is in physical contact with an inner sidewall and the topmost surface of the dam structure.3. The package of claim 1 , wherein the first encapsulant has a sloped sidewall.4. The package of claim 1 , further comprising a second encapsulant surrounding the die stack claim 1 , the first encapsulant and the dam structure claim 1 , wherein the topmost surface of the die stack is level with a topmost surface of the second encapsulant.5. The package of claim 4 , wherein the second encapsulant is in physical contact with an outer sidewall and the topmost surface of the dam structure.6. The package of claim 4 , wherein the second encapsulant has a sloped sidewall.7. The package of claim 4 , wherein the first encapsulant and the second encapsulant comprise different materials.8. A package comprising ...

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Номер записи: 100