CORE-SHELL PARTICLES FOR MAGNETIC PACKAGING

A package substrate may include a build-up layer. The build-up layer may include a dielectric material and one or more microspheres. The one or more microspheres may include a magnetic core that includes a first material that is a first oxidation-resistant material. Further, the one or more microspheres may include a shell to encapsulate the core, and the shell may include a second material that is a second oxidation-resistant material. The package substrate may further include a metal layer coupled with the build-up layer. 1. A package substrate , comprising: a dielectric material; and', 'one or more microspheres, wherein the one or more microspheres include a magnetic core that includes a first material that is a first oxidation-resistant material,, 'a build-up layer comprisingwherein the one or more microspheres include a shell to encapsulate the core, andwherein the shell includes a second material that is a second oxidation-resistant material; anda metal layer coupled with the build-up layer.2. The package substrate of claim 1 , wherein the first material is cobalt-tantalum-zirconium claim 1 , neodymium-iron-carbon claim 1 , or cobalt-iron-carbon.3. The package substrate of claim 1 , wherein the first material is iron claim 1 , cobalt claim 1 , or nickel.4. The package substrate of claim 1 , wherein the first material is a polymer that includes iron claim 1 , and wherein the polymer is a polyimide claim 1 , polyester claim 1 , polyphenol claim 1 , or poly cyclic-olefin.5. The package substrate of claim 1 , wherein the second material is copper claim 1 , silver claim 1 , gold claim 1 , platinum claim 1 , palladium claim 1 , titanium claim 1 , or chromium.6. The package substrate of claim 1 , wherein the build-up layer further comprises silica filler material.7. The package substrate of claim 1 , wherein the metal layer is copper claim 1 , tungsten claim 1 , or aluminum.8. A build-up layer claim 1 , comprising:a dielectric material; andone or more microspheres, ...

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME

A semiconductor device includes a base and a conductive layer to form a composite substrate. The conductive layer covers a surface of the base. The semiconductor device also includes a dielectric layer covering the conductive layer. The conductive layer is disposed between the dielectric layer and the base. The semiconductor device further includes a GaN-containing composite layer, a gate electrode disposed over the GaN-containing composite layer, a source electrode and a drain electrode disposed on the GaN-containing composite layer. The source electrode and the drain electrode are disposed at two opposite sides of the gate electrode. In addition, a method for manufacturing the semiconductor device with a composite substrate is provided. 1. A semiconductor device , comprising:a composite substrate comprising a base and a conductive layer, wherein the conductive layer continuously contacts and covers a surface of the base;a dielectric layer covering the conductive layer, wherein the conductive layer is disposed between the dielectric layer and the base;a GaN-containing composite layer disposed on the composite substrate;a gate electrode disposed on the GaN-containing composite layer;a source electrode and a drain electrode disposed on the GaN-containing composite layer and at two opposite sides of the gate electrode.2. The semiconductor device as claimed in claim 1 , wherein the conductive layer comprises a metal claim 1 , an alloy claim 1 , a metal nitride claim 1 , polysilicon or a combination thereof.3. The semiconductor device as claimed in claim 1 , wherein the conductive layer comprises Ti claim 1 , Ta claim 1 , W claim 1 , Nb claim 1 , Mo claim 1 , V claim 1 , an alloy or a nitride comprising a metal thereof.4. The semiconductor device as claimed in claim 1 , wherein the conductive layer comprises Ti claim 1 , Ta claim 1 , W claim 1 , Nb claim 1 , Mo claim 1 , V claim 1 , TaAl claim 1 , TiW claim 1 , TiN claim 1 , TaN claim 1 , TiAlN claim 1 , TaAlN claim 1 , ...

Component structure, power module and power module assembly structure

The present disclosure relates to a component structure, a power module and a power module assembly structure having the component structure. The component structure comprises: a first bus bar, having one end extending to a first plane to form a first connecting terminal; a second bus bar, comprising a front portion of the second bus bar and a rear portion of the second bus bar, wherein the front portion of the second bus bar is laminated in parallel with the first bus bar, and the rear portion of the second bus bar is extended to a second plane to form a second connecting terminal; and an external circuit comprising a third bus bar, wherein the third bus bar is settled in parallel with the rear portion of the second bus bar, to reduce a parasitic inductance between the first connecting terminal and the second connecting terminal.

Hybrid bonding structures, semiconductor devices having the same, and methods of manufacturing the semiconductor devices

Provided are a hybrid bonding structure, a solder paste composition, a semiconductor device, and a method of manufacturing the semiconductor device. The hybrid bonding structure includes a solder ball and a solder paste bonded to the solder ball. The solder paste includes a transient liquid phase. The transient liquid phase includes a core and a shell on a surface of the core. A melting point of the shell may be lower than a melting point of the core. The core and the shell are configured to form an intermetallic compound in response to the transient liquid phase at least partially being at a temperature that is within a temperature range of about 20° C. to about 190° C.

ELEMENT MODULE

An element module includes a cooler, a plurality of elements, and a conductive member. The cooler includes a first element disposition portion and a second element disposition portion which are provided on both sides in a predetermined direction. The plurality of elements are disposed in each of the first element disposition portion and the second element disposition portion. The conductive member is disposed in a space portion of the cooler. The space portion penetrates the cooler between the plurality of elements in each of the first element disposition portion and the second element disposition portion. The space portion allows the first element disposition portion and the second element disposition portion to communicate with each other. The conductive member is connected to the element of the first element disposition portion and the element of the second element disposition portion. 13-. (canceled)4. An element module , comprising:a cooler including a first element disposition portion and a second element disposition portion which are provided on both sides in a predetermined direction, and including at least one refrigerant storage portion configured to internally store a refrigerant between the first element disposition portion and the second element disposition portion;a plurality of elements disposed in each of the first element disposition portion and the second element disposition portion, and including transistors;a conductive member disposed in a space portion through which the first element disposition portion and the second element disposition portion are allowed to communicate with each other by penetrating the cooler between the plurality of elements in each of the first element disposition portion and the second element disposition portion, and connected to the element of the first element disposition portion and the element of the second element disposition portion;a plurality of conductor plates disposed on a side opposite to each facing side of ...

TERMINAL PLATE AND SEMICONDUCTOR DEVICE

Provided is a terminal plate according to an embodiment including: a first plate portion for being connected to a first semiconductor element; a second plate portion for being connected to a second semiconductor element; a third plate portion provided above the first plate portion and the second plate portion; a first connecting portion provided between the first plate portion and the third plate portion and connecting the first plate portion and the third plate portion; a second connecting portion provided between the second plate portion and the third plate portion and connecting the second plate portion and the third plate portion; a fourth plate portion provided above the first plate portion and the second plate portion and provided on the opposite side of the third plate portion with interposing the first and second plate portions; a third connecting portion provided between the first plate portion and the fourth plate portion and connecting the first plate portion and the fourth plate portion; a fourth connecting portion provided between the second plate portion and the fourth plate portion and connecting the second plate portion and the fourth plate portion; and a fifth plate portion provided above the fourth plate portion, the fifth plate portion connected to the fourth plate portion, and the fifth plate portion having a hole. 1. A terminal plate comprising:a first plate portion for being connected to a first semiconductor element;a second plate portion for being connected to a second semiconductor element;a third plate portion provided above the first plate portion and the second plate portion;a first connecting portion provided between the first plate portion and the third plate portion and connecting the first plate portion and the third plate portion;a second connecting portion provided between the second plate portion and the third plate portion and connecting the second plate portion and the third plate portion;a fourth plate portion provided above the ...

Semiconductor device

A semiconductor device may include a first conductor plate on which a first semiconductor element, a second semiconductor element and a first circuit board are disposed, and a plurality of first signal terminals. A size of the second semiconductor is smaller than a size of the first semiconductor element. In a plan view along a direction perpendicular to the first conductor plate, the plurality of first signal terminals is located in a first direction with respect to the first semiconductor element. The second semiconductor element and the first circuit board are located between the plurality of first signal terminals and the first semiconductor element and are arranged along a second direction that is perpendicular to the first direction. A signal pad of the first semiconductor element is connected to a corresponding one of the plurality of first signal terminals via a signal transmission path of the first circuit board.

Microelectronic device including fiber-containing build-up layers

Described are microelectronic devices including a substrate formed with multiple build-up layers, and having at least one build-up layer formed of a fiber-containing material. A substrate can include a buildup layers surrounding an embedded die, or outward of the build-up layer surrounding the embedded die that includes a fiber-containing dielectric. Multiple build-up layers located inward from a layer formed of a fiber-containing dielectric will be formed of a fiber-free dielectric.

SEMICONDUCTOR DEVICE

A semiconductor device is provided, including: a bottom portion having a pad formed of a conductive material; a lid portion covering at least a part of the bottom portion; and a first terminal portion and a second terminal portion which are provided in parallel with each other, are fixed to the lid portion, and each contact a corresponding pad, wherein: the first terminal portion is provided with a first plate-shaped portion; the second terminal portion is provided with a second plate-shaped portion; and each of the first plate-shaped portion and the second plate-shaped portion has a principal surface in a direction facing the pad and is flexible in a direction toward the pad. 1. A semiconductor device comprising:a bottom portion having a pad formed of a conductive material;a lid portion covering at least a part of the bottom portion;a first terminal portion and a second terminal portion which are provided in parallel with each other, are fixed to the lid portion, and each contact a corresponding pad;a plurality of main terminals which form a current path of a large current flowing in a power device; and the plurality of control terminal are the first terminal portion and the second terminal portion;', 'the first terminal portion is provided with a first plate-shaped portion and the second terminal portion is provided with a second plate-shaped portion; and', 'each of the first plate-shaped portion and the second plate-shaped portion has a principal surface in a direction facing the pad and is flexible in a direction toward the pad., 'a plurality of control terminals, each of which has a shape of a plate whose width is smaller than each of the plurality of main terminals, wherein2. The semiconductor device according to claim 1 , wherein the first plate-shaped portion and the second plate-shaped portion are provided in parallel with each other.3. The semiconductor device according to claim 2 , wherein the principal surface of each of the first plate-shaped portion ...

Semiconductor Device Comprising a Can Housing a Semiconductor Die which is Embedded by an Encapsulant

A semiconductor device includes a conductive can include a flat portion and at least one peripheral rim portion extending from an edge of the flat portion, a semiconductor die comprising a first main face and a second main face opposite to the first main face, a first contact pad disposed on the first main face and a second contact pad disposed on the second main face, wherein the first contact pad is electrically connected to the flat portion of the can, an electrical interconnector connected with the second contact pad, and an encapsulant disposed under the semiconductor die so as to surround the electrical interconnector, wherein an external surface of the electrical interconnector is recessed from an external surface of the encapsulant. 1. A semiconductor device , comprisinga conductive can comprising a flat portion and at least one peripheral rim portion extending from an edge of the flat portion;a semiconductor die comprising a first main face and a second main face opposite to the first main face, a first contact pad disposed on the first main face and a second contact pad disposed on the second main face, wherein the first contact pad is electrically connected to the flat portion of the can;an electrical interconnector connected with the second contact pad; andan encapsulant disposed under the semiconductor die so as to surround the electrical interconnector, whereinan external surface of the electrical interconnector is recessed from an external surface of the encapsulant.2. The semiconductor device according to claim 1 , wherein the encapsulant is disposed so as to fill a space between the semiconductor die and the flat portion and the rim of the can.3. The semiconductor device according to claim 1 , whereina top surface of the can is exposed by or not covered by the encapsulant.4. The semiconductor device according to claim 1 , whereina height of the electrical interconnector is in a range of 40% to 80% of a height of the encapsulant, wherein the height ...

SEMICONDUCTOR DEVICE

A semiconductor device includes an assembly configured such that a plurality of semiconductor modules is connected by a component. Each of the plurality of semiconductor modules includes a semiconductor element including a front-surface electrode fixing a front-surface electrode plate and a back-surface electrode fixing a back-surface electrode plate, wherein the component is either of a first component and a second component. The first component being configured to connect adjacent semiconductor modules to each other such that a front-surface electrode plate of one of the adjacent semiconductor modules is connected to a back-surface electrode plate of the other one of the adjacent semiconductor modules. The second component is configured to connect adjacent semiconductor modules such that respective front-surface electrode plates are connected and respective back-surface electrode plates are connected. The semiconductor modules are connected by the first component or the second component. 1. A semiconductor device comprising:an assembly configured such that a plurality of semiconductor modules is connected by a connection component, the assembly being sealed with a molding resin, wherein: a semiconductor element including a front-surface electrode and a back-surface electrode,', 'a front-surface electrode plate fixed to the front-surface electrode, and', 'a back-surface electrode plate fixed to the back-surface electrode;, 'each of the plurality of semiconductor modules includes'}the connection component is either of a first connection component and a second connection component, the first connection component being configured to connect adjacent semiconductor modules to each other such that a front-surface electrode plate of one of the adjacent semiconductor modules is connected to a back-surface electrode plate of the other one of the adjacent semiconductor modules, the second connection component being configured to connect adjacent semiconductor modules to each ...

PACKAGING OF A SEMICONDUCTOR DEVICE WITH PHASE-CHANGE MATERIAL FOR THERMAL PERFORMANCE

A semiconductor device comprises a generally planar semiconductor chip. The semiconductor chip comprises a first side and second side opposite the first side. The first side is associated with a source conductive pad. The second side is associated with a drain conductive pad. A gate pad overlies a portion of the first side. A source terminal comprises a metallic strip assembly with a series of pocket chambers spaced apart from each other and partially filled with a phase-change material filling. A drain terminal is spaced apart from the source terminal by a dielectric layer. The source terminal is bonded to the source conductive pad via a bonding interface material. 1. A semiconductor device comprising:a generally planar semiconductor chip comprising a first side and second side opposite the first side, the first side associated with a source conductive pad, the second side associated with a drain conductive pad; a gate pad overlying a portion of the first side;a source terminal comprising a metallic strip assembly with a series of pocket chambers spaced apart from each other and partially filled with a phase-change material filling;a drain terminal spaced apart from the source terminal by a dielectric layer; andthe source terminal bonded to the source conductive pad via a bonding interface material.2. The semiconductor device according to wherein the drain terminal further comprises a metallic strip assembly with a series of pocket chambers spaced apart from each other and partially filled with a phase-change material filling.3. The semiconductor device according to wherein the series of pocket chambers of the drain terminal are substantially oval or substantially spherical and wherein the phase-change material filling comprises a refrigerant.4. The semiconductor device according to wherein the series of pocket chambers of the source terminal are substantially oval or substantially spherical and wherein the phase-change material filling comprises a refrigerant.5. ...

MANUFACTURING A MODULE WITH SOLDER BODY HAVING ELEVATED EDGE

A method of manufacturing a module is disclosed. In one example, the method comprises providing at least one solder body with a base portion and an elevated edge extending along at least part of a circumference of the base portion. At least one carrier, on which at least one electronic component is mounted, is placed in the at least one solder body so that the at least one carrier is positioned on the base portion and is spatially confined by the elevated edge. 1. A method of manufacturing a module , wherein the method comprises:providing at least one solder body with a base portion and an elevated edge extending along at least part of a circumference of the base portion; andplacing at least one carrier, on which at least one electronic component is mounted, in the at least one solder body so that the at least one carrier is positioned on the base portion and is spatially confined by the elevated edge.2. The method according to claim 1 , wherein the method comprisesproviding a plurality of solder bodies each with a base portion and an elevated edge extending along at least part of a circumference of the respective base portion; andplacing each of a plurality of carriers, wherein at least one electronic component is mounted on each of the carriers, in an assigned one of the solder bodies so that each of the carriers is positioned on a respective base portion and is spatially confined by a respective elevated edge.3. The method according to claim 1 , wherein the method comprises connecting the at least one solder body with the at least one carrier by soldering.4. The method according to claim 1 , wherein the method comprises placing the at least one solder body on a support body.5. The method according to claim 4 , wherein the method comprises placing claim 4 , and in particular pre-fixing claim 4 , the at least one solder body on the support body before placing the at least one carrier in the at least one solder body.6. The method according to claim 4 , wherein the ...

Method for producing a substrate plate, substrate plate, method for producing a semiconductor module and semiconductor module

One aspect relates to a method for producing a substrate plate for a large-area semiconductor element, particularly for a thyristor wafer or a diode. At least one first layer made from a first material, with a first coefficient of expansion, and at least one second layer made from a second material of low expandability, with a second coefficient of expansion, which is smaller than the first coefficient of expansion, are bonded to one another by means of a low-temperature sintering method at a bonding temperature of 150° C.-300° C. At least one first bonding layer made from a bonding material is formed between the first layer and the second layer and the bonding temperature substantially corresponds to the mounting temperature during the bonding of the substrate plate produced with at least one large-area semiconductor element.

Power semiconductor device

Provided is a power semiconductor device which is able to have improved connection reliability between a wiring line and an electrode of a power semiconductor element in comparison to conventional power semiconductor devices. This power semiconductor device is provided with: a semiconductor element; an insulating substrate having an electrode layer to which the semiconductor element is bonded; an external wiring line which is solder bonded to an upper surface electrode of the semiconductor element and has an end portion for external connection, said end portion being bent toward the upper surface; and a frame member which is affixed to the electrode layer of the insulating substrate. The frame member has a fitting portion that is fitted with the end portion for external connection; and the external wiring line has at least two projected portions that protrude toward the semiconductor element.

COMPOSITE ASSEMBLY OF THREE STACKED JOINING PARTNERS

A composite assembly of three stacked joining partners, and a corresponding method. The three stacked joining partners are materially bonded to one another by an upper solder layer and a lower solder layer. An upper joining partner and a lower joining partner are fixed in their height and have a specified distance from one another. The upper solder layer is fashioned from a first solder agent, having a first melt temperature, between the upper joining partner and a middle joining partner. The second solder layer is fashioned from a second solder agent, having a higher, second melt temperature, between the middle joining partner and the lower joining partner. The upper joining partner has an upwardly open solder compensating opening filled with the first solder agent, from which, to fill the gap between the upper joining partner and the middle joining partner, the first solder agent subsequently flows into the gap. 110-. (canceled)11. A composite assembly , comprising:three stacked joining partners materially bonded to one another by an upper solder layer and by a lower solder layer, an upper joining partner of the joining partners and a lower joining partner of the joining partners being fixed in their height and having a specified distance from one another, the upper solder layer is fashioned from a first solder agent having a first melt temperature, and is situated between the upper joining partner and a middle joining partner of the joining partners, and the second solder layer is fashioned from a second solder agent, having a higher, second melt temperature relative to the first melt temperature, and is situated between the middle joining partner and the lower joining partner, wherein the upper joining partner has an upwardly open solder compensating opening filled with the first solder agent, from which, in order to fill a gap between the upper joining partner and the middle joining partner, the first solder agent subsequently flows into the gap.12. The ...

Method of manufacturing light emitting element mounting base member, method of manufacturing light emitting device using the light emitting element mounting base member, light emitting element mounting base member, and light emitting device using the light emitting element mounting base member

A method of manufacturing a light emitting element mounting base member includes: providing a first insulating member in a plate shaped having at least one recess portion or at least one through-hole; disposing in the recess portion or in the through-hole a light blocking resin and a plurality of core members each equipped with a second insulating member having light reflectivity on each surface of a plurality of electrical conductor cores; and exposing at least one of the surface of the electrical conductor cores from the second insulating members by removing each part of at least one of the second insulating members.

Method of manufacturing light emitting element mounting base member, method of manufacturing light emitting device using the light emitting element mounting base member, light emitting element mounting base member, and light emitting device using the light emitting element mounting base member

A method of manufacturing a light emitting element mounting base member includes: providing a first insulating member in a plate shaped having at least one recess portion or at least one through-hole; disposing in the recess portion or in the through-hole a light blocking resin and a plurality of core members each equipped with a second insulating member having light reflectivity on each surface of a plurality of electrical conductor cores; and exposing at least one of the surface of the electrical conductor cores from the second insulating members by removing each part of at least one of the second insulating members.

Semiconductor device

According to one embodiment, a semiconductor device includes at least a package substrate, an external electrode, a mounting substrate, and a mounting electrode. A signal connection point of the external electrode is provided at an end portion in a longitudinal direction of the external electrode. A signal connection point of the mounting electrode is provided at an end portion of the mounting electrode. The end portion of the mounting electrode is opposite to the signal connection point of the external electrode facing to the mounting electrode in the longitudinal direction.

Package structure and communications device

A package structure is disclosed, the package structure includes a substrate, a chip, a bonding layer, and a coating. A plurality of grooves are disposed on the substrate. Silver bonding materials are disposed in the grooves and on a surface of the substrate, to form the bonding layer. The chip is connected to the substrate by using the bonding layer. The grooves are symmetrically arranged along a first and a second axis that are perpendicular to each other, a vertical projection of the chip on the substrate is centrosymmetric about the first and the second axis, and the vertical projection of the chip on the substrate covers a partial area of an outer-ring groove which faces a periphery of the chip. The coating covers a surface that is of the bonding layer and not in contact with the substrate or the chip, used to prevent migration of silver ions.

Component structure, power module and power module assembly structure

The present disclosure relates to a component structure, a power module and a power module assembly structure having the component structure. The component structure comprises: a first bus bar, having one end extending to a first plane to form a first connecting terminal; a second bus bar, comprising a front portion of the second bus bar and a rear portion of the second bus bar, wherein the front portion of the second bus bar is laminated in parallel with the first bus bar, and the rear portion of the second bus bar is extended to a second plane to form a second connecting terminal; and an external circuit comprising a third bus bar, wherein the third bus bar is settled in parallel with the rear portion of the second bus bar, to reduce a parasitic inductance between the first connecting terminal and the second connecting terminal.

Power Semiconductor Arrangement Having a Stack of Connection Plates

A power semiconductor arrangement includes a plurality of half-bridges arranged in parallel alongside one another by way of a longer longitudinal side of the half-bridges. An input load current terminal, an output load current terminal and a phase terminal are arranged on a top side of each of the half-bridges, the input load current terminals and the output load current terminals being arranged on an imaginary line that runs orthogonal to the longer longitudinal side of the half-bridges. First connection plates are connected to respective ones of the output load current terminals, and second connection plates are connected to respective ones of the input load current terminals. The first connection plates are arranged above the second connection plates. The first and the second connection plates are arranged in parallel with one another and electrically insulated from one another. 1. A power semiconductor arrangement , comprising:a plurality of power semiconductor switching elements arranged in a row and interconnected in parallel, each power semiconductor switching element having one load current terminal for load current input and one load current terminal for load current output, each of the load current terminals of the same load current direction from load current input and load current output being arranged on a common imaginary line;a connection plate for each current load direction and configured to provide a joint electrical contact-connection and fasten all the load current terminals of the same load current direction from load current input and load current output, the connection plates being arranged in a manner electrically insulated from one another, spaced apart from one another and stacked in a stacking direction, each connection plate extending away from an in-feed edge via the associated load current terminals and contacting the load current terminals to provide a contact-connection up to an end edge opposite the in-feed edge along a first ...

SEMICONDUCTOR DEVICE

There is a problem that the reliability of insulation is lowered. A length L from a center P of a conductor layer to a peripheral edge portion of an insulating member is formed to be longer than a length L from the center P of the conductor layer to a peripheral edge portion of a protruding portion of a base member . In other words, a base end surface of the peripheral edge portion of the protruding portion is located on an inner side with respect to an insulating member end surface of the peripheral edge portion of the insulating member . Further, the insulating member end surface of the insulating member and a conductor layer end surface of the conductor layer form an end surface at the same position. Since the base end surface of the peripheral edge portion of the protruding portion is located on the inner side with respect to the insulating member end surface of the peripheral edge portion of the insulating member in this manner, an insulation distance can be secured. 1. A semiconductor device comprising:a semiconductor element;a conductor plate connected to the semiconductor element;a metal-made base member facing the conductor plate and constituting an exterior of the semiconductor device; andan insulating member arranged between the conductor plate and the base member, whereinthe insulating member is constituted to have a conductor layer sandwiched between a first insulating layer and a second insulating layer, forms a capacitance circuit between the first insulating layer and the conductor plate, and forms a capacitance circuit between the second insulating layer and the base member,the base member has a protruding portion formed in a contact portion between the insulating member and the base member, the protruding portion protruding toward the insulating member, anda length from a center of the conductor layer to a peripheral edge portion of the insulating member including the conductor layer is formed to be longer than a length from the center of the ...

THERMAL AND ELECTRICALLY CONDUCTIVE STRESS RELIEF INTERMEDIATE ELEMENT FOR A SEMICONDUCTIVE DEVICE

Liquid Crystal Display Device

본 발명은 TCP 또는 FPC 등의 본딩을 하는 필름 뿐만 아니라, 상기 TCP 또는 FPC 필름에 대응되어 본딩이 이루어지는 구조물, 즉, PCB와 액정 패널, PCB의 소오스 구동부와 게이트 구동부에 각각 테스트 포인트를 삽입함으로써, 본딩 완료 후 불량 발생시 장치를 해체하지 않고 이상이 일어난 부위를 판별하여 이상이 발생된 부위에 대한 리페어를 진행할 수 있는 액정 표시 장치에 관한 것으로, 도전성 필름을 이용하여 액정 패널과 PCB를 본딩하는 액정 표시 장치에 있어서, 상기 본딩이 이루어지는 각 구조물마다 테스트 포인트가 형성됨을 특징으로 한다. According to the present invention, as well as a film for bonding such as TCP or FPC, the test point is inserted into a structure in which bonding is performed corresponding to the TCP or FPC film, that is, a PCB, a liquid crystal panel, and a source driver and a gate driver of the PCB, The present invention relates to a liquid crystal display device capable of repairing a portion where an abnormality occurs by disassembling the device without disassembling the device after completion of the bonding. A liquid crystal display which bonds a liquid crystal panel and a PCB using a conductive film. In the apparatus, characterized in that the test point is formed for each structure of the bonding. COF(Chip On Film), TCP(Tape Carrier Package), TP(Test Point) Chip On Film (COF), Tape Carrier Package (TCP), Test Point (TP)

Without stitch module

本发明涉及一种无针脚模块，包括基板，所述基板设有第一表面、第二表面、及连接于所述第一表面与所述第二表面之间的侧面；所述侧面与所述第一表面之间所成的角度为钝角；所述基板上对应所述侧面间隔开设有凹槽，所述凹槽的内壁上均镀有导电层；所述第一表面上对应所述凹槽的一端周缘处印制有第一焊盘，所述第二表面上对应所述凹槽的另一端周缘处印制有第二焊盘，所述第一焊盘与所述第二焊盘均连接所述导电层。上述无针脚模块，结构简单，设计合理，将侧面与第一表面呈倾斜设置，且侧面与第一表面之间所成角度为钝角，使得第一焊盘与导电层的连接处的厚度减小，能有效减少阻抗不连续程度，同时，还在侧面设置凹槽，可提高爬锡效果。

Semiconductor devices

本发明涉及一种半导体器件。在半导体器件的性能方面实现了改进。所述半导体器件包括具有上面(第一面)、与所述上面相反的下面(第二面)以及位于所述上面与所述下面之间并且使半导体芯片被安装在其上方的多个侧面的金属板。所述金属板的一部分被从密封所述半导体芯片的密封体暴露。已暴露部分被金属膜覆盖。所述金属板的所述侧面包括被所述密封体覆盖的第一侧面以及被设置为与所述第一侧面相反并且从所述密封体暴露的侧面(第二侧面)。在所述金属板的所述上面与所述侧面之间，插入有相对于所述上面和所述侧面中的每一个倾斜并且被所述金属膜覆盖的倾斜面。

Package device comprising a capacitor disposed on the opposite side of the die relative to the substrate

일 실시 예에 따른 패키지 장치(300)는, 기판(310); 상기 기판(310)의 일면에 배치되는 복수 개의 상부 랜드(311); 상기 복수 개의 상부 랜드(311)에 배치되는 복수 개의 상부 솔더 볼(331); 상기 복수 개의 상부 솔더 볼(331)에 연결되는 다이(320); 상기 기판(310)의 타면에 배치되는 복수 개의 하부 랜드(312); 상기 복수 개의 하부 랜드(312) 중 일부의 하부 랜드에 배치되는 복수 개의 하부 솔더 볼(332); 및 상기 복수 개의 하부 랜드(312) 중 상기 하부 솔더 볼이 배치되지 않은 하부 랜드에 연결되고, 상기 다이(320)의 반대편에 마련되고, 상기 하부 솔더 볼(332)의 높이 보다 큰 높이를 갖는 캐패시터(340)를 포함할 수 있다.

CONSTRAINT ADAPTER FOR SEMICONDUCTOR DEVICE

HEAT AND ELECTRIC CONDUCTING BASE FOR RECEIVING SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING THE SAME

BASE PRESENTANT UNE BONNE CARACTERISTIQUE D'ADAPTATION AUX DIFFERENTS COEFFICIENTS DE DILATATION THERMIQUE. ELLE COMPREND: -UN CORPS 12 CONSTITUE D'UN PREMIER MATERIAU PRESENTANT UN PREMIER COEFFICIENT DE DILATATION THERMIQUE; -UNE SURFACE DE RECEPTION D'ELEMENT 12 SUR LE CORPS; ET -UN TREILLIS 14 EN MATERIAU MODIFICATEUR DE COEFFICIENT DE DILATATION THERMIQUE NOYE DANS LE CORPS A L'ENDROIT DE LA SURFACE DE RECEPTION D'ELEMENT DE FACON A MODIFIER LE COEFFICIENT DE DILATATION THERMIQUE DU CORPS A CET ENDROIT ET LUI CONFERER UNE VALEUR PLUS PROCHE DU COEFFICIENT DE DILATATION THERMIQUE DE L'ELEMENT SEMI-CONDUCTEUR QUE DE CELUI DES PARTIES RESTANTES DU CORPS. APPLICATION AUX SEMI-CONDUCTEURS DE PUISSANCE.

Semiconductor device

ANISOTROPIC CONDUCTIVE FILM FOR MICROCONNECTICS

The device includes hardened conductor solids (52) with a matrix of fused end materials (44,54) formed in a polymer material, to form a microconnector matrix. The formation steps consist of depositing a fusible material layer, followed by a polymer. The fusible material layer and polymer are re-heated to form a fused structure. An extra layer is then formed, and photolithography carried out to form a hole structure. Conductor material is then added to the holes, and the material heated to form the outer hole fused section, and peel away the lower outer level.

CONDUCTIVE BASE OF HEAT AND ELECTRICITY FOR RECEIVING A SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREOF

Information handling system

An information handling system which includes as part thereof a circuitized substrate comprising a first layer comprised of a dielectric material including a resin material including a predetermined quantity of particles therein and not including continuous fibers, semi-continuous fibers or the like as part thereof, and at least one circuitized layer positioned on the dielectric first layer.

Making method of photo hardening resin with anisotropic electric ball and bonding method of flat display using photo hardening resin of anaerobic

본 발명은 이방성 도전볼을 포함하는 혐기성의 광경화 접착제의 제조방법과 혐기성의 광경화접착제를 이용한 평판디스플레이의 회로접속방법에 관한 것으로서, 접착제 삽입홈(1a)이 형성된 금형플레이트(31)를 준비하는 단계와, 상기 금형플레이트(31)에 혐기성의 광경화 접착제(32)를 올려놓는 단계와, 상기 금형플레이트(31) 상에서 혐기성의 광경화 접착제(32)가 금형플레이트(31)의 접착제 삽입홈(31a)에 각각 삽입되어 이방성 도전볼(33)이 그 안에 포함되도록 하는 단계와, 상기 이방성 도전볼(33)이 포함되어 있는 혐기성의 광경화 접착제(32)를 무정전 실리콘패드(34)에 붙이는 단계로 이루어져, 상기 제조방법에 의해 제조된 이방성 도전볼을 포함하는 혐기성의 광경화 접착제를 회로접속장치에 사용하여 회로를 접속하는 회로접속방법에 관한 것이다. The present invention relates to a method of manufacturing an anaerobic photocurable adhesive including an anisotropic conductive ball and a circuit connecting method of a flat panel display using an anaerobic photocurable adhesive, wherein a mold plate 31 having an adhesive insertion groove 1a is prepared. And placing the anaerobic photocurable adhesive 32 on the mold plate 31, and the anaerobic photocurable adhesive 32 on the mold plate 31 is inserted into the adhesive of the mold plate 31. Inserting each of the anisotropic conductive balls 33 therein, and attaching the anaerobic photocurable adhesive 32 including the anisotropic conductive balls 33 to the uninterruptible silicon pad 34. It relates to a circuit connection method comprising a step, and connecting the circuit using an anaerobic photocurable adhesive comprising an anisotropic conductive ball produced by the manufacturing method in a circuit connection device. 이방성 도전볼, 혐기성, 광경화 접착제, 금형플레이트, 무정전 실리콘패드, 코팅 블레이드 Anisotropic Conductive Ball, Anaerobic, Photo Curing Adhesive, Mold Plate, Uninterruptible Silicon Pad, Coating Blade

Microelectronic assemblies including z-axis conductive films

An assembly of two or more microelectronic parts, wherein electrical and/or thermal interconnection between the parts is achieved by means of multiple, discrete, conductive nanoscopic fibrils (15) or tubules (15) fixed within the pores of an insulating film (16). Such a film is said to have anisotropic electrical conductivity, i.e., Z-axis conductivity, with little or no conductivity in the other directions.

A kind of encapsulating structure and its method for packing of multi-chip lamination

本发明涉及一种多芯片叠层的封装结构及其封装方法，仅使用一个联结片设置于HS芯片的源极和LS芯片的漏极上实现其电性连接，导电损耗和开关损耗减小，且热耗散效率则得到增强。IC芯片绝缘地连接在联结片上，从而可以叠放到HS芯片及LS芯片所在平面的上方，以有效减少封装后的器件尺寸。本发明中可以将第一、第二载片台的底面暴露在塑封体外；还有多种方法，进一步将联结片上不连接IC芯片的一部分表面暴露在塑封体外；或者在联结片上进一步连接散热板，并使该散热板的一部分表面暴露在塑封体外；或者将散热板插入到塑封体预留的缺口中以接触联结片帮助散热。

Power semiconductor assembly having a stack of connection panels with improved geometry for common electrical contacting of a plurality of identical power semiconductor switching elements

Component structure, power module and power module assembly structure

The present disclosure relates to a component structure, a power module and a power module assembly structure having the component structure. The component structure comprises: a first bus bar, having one end extending to a first plane to form a first connecting terminal; a second bus bar, comprising a front portion of the second bus bar and a rear portion of the second bus bar, wherein the front portion of the second bus bar is laminated in parallel with the first bus bar, and the rear portion of the second bus bar is extended to a second plane to form a second connecting terminal; and an external circuit comprising a third bus bar, wherein the third bus bar is settled in parallel with the rear portion of the second bus bar, to reduce a parasitic inductance between the first connecting terminal and the second connecting terminal.

Expansion constrained die stack

Structures and techniques for mounting semiconductor dies are disclosed. In one embodiment, the invention includes a stack of printed wiring board assemblies that are connected via interconnection components. At least one of the printed wiring board assemblies includes an interposer substrate having a constraining layer that includes carbon.

Printed circuit board and method of manufacturing semiconductor package using the same

Provided is a printed circuit board having a structure that can prevent the generation of cracks around a rectangular hole and a method of manufacturing a printed circuit board for a semiconductor package. The printed circuit board includes a base substrate in which at least one window slit is formed, a plurality of circuit patterns formed at least on a side surface of the base substrate, a protective layer formed on the base substrate and the circuit patterns, and a crack preventive layer that is formed along at least a portion of edges of the window slit and is not formed at least on the circuit patterns.

Plate type member for semiconductor device package and package

A plate type member of a Cu--W and/or Mo alloy can be bonded to a ceramic member or the like to form a semiconductor device package without problems, because the degree of warping of the plate type member during a heating step in its fabrication is suppressed. In the plate type member consisting of a Cu--W and/or Mo alloy, including a small amount of alkaline earth metal impurity the difference between alkaline earth metal contents in upper and lower halves of the member along the thickness direction is not more than 10 ppm, or delete "an alkaline earth" preferably not more than 5 ppm relative to the content of W and/or Mo. This plate type member is manufactured by reducing the alkaline earth metal content in W and/or Mo raw material powder, or standing a skeleton vertically upright on a refractory plate for carryiing out Cu infiltration, and performing homogeneous heating and cooling replace during the manufacturing thereby preventing maldistribution of the alkaline earth metal.

PROTECTIVE BUFFER

Aluminum-silicon carbide composite and processing method thereof

Structures including electronic devices and semiconductor devices

Method of manufacture of material for semiconductor substrate, material for semiconductor substrate, and package for semiconductor

A material for semiconductor substrate is composed substantially of tungsten and/or molybdenum mixed with 5-30 wt.% copper, 0.002-0.07 wt.% phosphorus, 0.1-0.5 wt.% one or two kinds selected from among cobalt, nickel, and iron. The material is manufactured by mixing together tungsten powder and/or molybdenum powder of 1 µm in particle size, copper powder of 7 µm in particle size, and small amounts of an iron-group metal and phosphorus or phosphorus compound, molding the mixture at a pressure of 1.0 ton/cm 2 , and then, sintering the molded body at a temperature which allows solid and liquid to coexist below the melting point of copper.

Uses of uniaxially electrically conductive articles

Polymer (preferably polyimide) sheets (10) with laser ablated through-holes plated with metal (20) are used for making electrical connections to specified microcircuits, espe­cially unbumped microchips and Tape Automated Bonding (TAB) articles. Bonding with different melting-point materials at opposite ends of the plated holes is disclosed. Preferred polyimides are those derived from polymerisation of 4,4'-biphenyldianhydride and (4,4'-diaminobiphenyl, or 4,4'-diaminobiphenylether, or phenylenediamine, preferably p-phenylenediamine).

Chip package and method of fabricating the same

본 발명은, 제1 단자가 형성된 제1 면과, 상기 제1 면과 대향하며 제2 단자가 형성된 제2 면을 포함하며 상기 제1 및 제2 면 상에는 각각 도전층이 형성된 칩과, 상기 칩의 제2 면에 배치되며 상기 제2 단자와 연결되는 도전성 비아홀이 형성된 기판을 포함하는 칩 패키지를 제공한다. 또한, 본 발명은 새로운 칩 패키지 제조방법과 상기 칩 패키지를 포함하는 어셈블리를 제공할 수도 있다. According to the present invention, a chip including a first surface having a first terminal formed thereon, a second surface facing the first surface and having a second terminal formed thereon, and having a conductive layer formed on the first and second surfaces, respectively, The chip package includes a substrate disposed on a second surface of the substrate and having a conductive via hole connected to the second terminal. The present invention may also provide a new chip package manufacturing method and an assembly including the chip package. 본 발명의 칩 패키지에 따르면, 종래에 사용되었던 와이어본딩과 별도의 도전성 랜드를 형성할 필요가 없어, 패키지 크기를 감소시킬 수 있을 뿐만 아니라, 그 제조공정도 간소화시킬 수 있다는 잇점이 있다. According to the chip package of the present invention, there is no need to form a conductive land separate from the wire bonding used in the related art, so that the package size can be reduced and the manufacturing process can be simplified.

Composite assembly of three stacked joining partners

A composite assembly of three stacked joining partners, and a corresponding method. The three stacked joining partners are materially bonded to one another by an upper solder layer and a lower solder layer. An upper joining partner and a lower joining partner are fixed in their height and have a specified distance from one another. The upper solder layer is fashioned from a first solder agent, having a first melt temperature, between the upper joining partner and a middle joining partner. The second solder layer is fashioned from a second solder agent, having a higher, second melt temperature, between the middle joining partner and the lower joining partner. The upper joining partner has an upwardly open solder compensating opening filled with the first solder agent, from which, to fill the gap between the upper joining partner and the middle joining partner, the first solder agent subsequently flows into the gap.

Low moisture absorptive circuitized substrate, method of making same, electrical assembly utilizing same, and information handling system utilizing same

A circuitized substrate comprising a first layer comprised of a dielectric material including a low moisture absorptive polymer resin in combination with a nodular fluoropolymer web encased within the resin, the resulting dielectric layer formed from this combination not including continuous or semi-continuous fibers as part thereof. The substrate further includes at least one circuitized layer positioned on the dielectric first layer. An electrical assembly and a method of making the substrate are also provided, as is an information handling system (e.g., computer) incorporating the circuitized substrate of the invention as part thereof.

Anisotropic film conductor for microconnections

The device includes hardened conductor solids (52) with a matrix of fused end materials (44,54) formed in a polymer material, to form a microconnector matrix. The formation steps consist of depositing a fusible material layer, followed by a polymer. The fusible material layer and polymer are re-heated to form a fused structure. An extra layer is then formed, and photolithography carried out to form a hole structure. Conductor material is then added to the holes, and the material heated to form the outer hole fused section, and peel away the lower outer level.

COMPOSITE MATERIAL WITH LOW COEFFICIENT OF THERMAL EXPANSION AND GOOD THERMAL CONDUCTIVITY

L'INVENTION CONCERNE UN MATERIAU COMPOSITE, ET NOTAMMENT UN MATERIAU POUR UNE PLAQUETTE QUI EST DISPOSEE DANS UN DISPOSITIF SEMI-CONDUCTEUR ENTRE UNE PASTILLE DE MATIERE SEMI-CONDUCTRICE ET UN ELEMENT FAIT D'UNE MATIERE DONT LE COEFFICIENT DE DILATATION THERMIQUE EST BEAUCOUP PLUS ELEVE QUE CELUI DE LA MATIERE SEMI-CONDUCTRICE, NOTAMMENT UN ELEMENT DE CONNEXION EN CUIVRE OU EN ALUMINIUM POUR LE COURANT ELECTRIQUE A L'ENTREE OU A LA SORTIE DU DISPOSITIF SEMI-CONDUCTEUR. CE MATERIAU COMPOSITE SE COMPOSE D'UNE MATRICE 22 D'UN ALLIAGE D'ENVIRON 64 EN POIDS DE FER ET D'ENVIRON 36 EN POIDS DE NICKEL OU D'UN AUTRE ALLIAGE CONTENANT DU FER ET DU NICKEL ET AYANT UN COEFFICIENT DE DILATATION THERMIQUE DE 3.10K AU MAXIMUM DANS LES LIMITES DE LA GAMME DE TEMPERATURE DE 20C A 100C, AINSI QUE DE VEINES 23 DE CUIVRE QUI S'ETENDENT DANS UNE DIRECTION DANS LA MATRICE ET SONT REPARTIES DANS CETTE DERNIERE, LE CUIVRE ET L'ALLIAGE ETANT UNIS METALLURGIQUEMENT PAR UNE COUCHE LIMITE CONTENANT DU CUIVRE ET L'ALLIAGE ET AYANT UNE EPAISSEUR DE 5MICRONS AU MAXIMUM. THE INVENTION RELATES TO A COMPOSITE MATERIAL, AND IN PARTICULAR TO A MATERIAL FOR A PLATE WHICH IS ARRANGED IN A SEMICONDUCTOR DEVICE BETWEEN A PELLET OF SEMICONDUCTOR MATERIAL AND AN ELEMENT MADE FROM A MATERIAL WHOSE THERMAL EXPANSION COEFFICIENT IS GREATER. THAN THAT OF SEMI-CONDUCTIVE MATERIAL, IN PARTICULAR A COPPER OR ALUMINUM CONNECTION ELEMENT FOR ELECTRIC CURRENT AT THE INPUT OR OUTPUT OF THE SEMI-CONDUCTIVE DEVICE. THIS COMPOSITE MATERIAL CONSISTS OF A MATRIX 22 OF AN ALLOY OF APPROXIMATELY 64 IN IRON WEIGHT AND ABOUT 36 IN WEIGHT OF NICKEL OR ANY OTHER ALLOY CONTAINING IRON AND NICKEL AND HAVING A COEFFICIENT OF THERMAL EXPANSION OF 3.10K AT MAXIMUM WITHIN THE LIMITS OF THE 20C TO 100C TEMPERATURE RANGE, AS WELL AS 23 COPPER VEINS THAT EXTEND IN A DIRECTION INTO THE MATRIX AND ARE DISTRIBUTED THROUGHOUT THE LATTER, THE COPPER AND THE ALLOY BEING UNITED METALLURGICALLY BY A ...

Semiconductor device and semiconductor device packaging system

Low moisture absorptive circuitized substrate with reduced thermal expansion, method of making same, electrical assembly utilizing same, and information handling system utilizing same

Process for the bubble-free bonding of a large-area semiconductor component to a substrate by soldering

Semiconductor device

This semiconductor device is provided with a bottom part having pads formed from a conductive material, a lid covering at least part of the bottom part, and a first terminal unit and a second terminal unit disposed in parallel, fixed to the lid and each contacting a corresponding pad, wherein a first plate-shape unit is provided on the first terminal unit, a second plate-shape unit is provided on the second terminal unit, and the first plate-shape unit and the second plate-shape unit each has a primary surface facing in the direction opposite of a pad, and is flexible in the direction towards the pads.

Electronic Package

외부 접속은 제 1 비등방성 도체 부재(13), 상부면에 제 1 도체 패턴(29)을 갖는 제 1 평탄 절연부재(14), 제 2 비등방성 도체 부재(15) 및, 상부면에 제 2 도체 패턴(30)을 갖는 제 2 평탄 절연 부재(17)를 전자 장치 위에 연속적으로 제공함으로써, 도체 패드(12)의 어레이를 상부면에 갖는 전자 장치에 형성된다. 상기 두개의 평탄 절연 부재는 대향면 사이로 관통하여 연장하는 전도 바이어스(25, 26)의 어레이를 포함한다. 제 1 비등방성 도체 부재(13) 및, 제 1 평탄 절연부재(14)를 통해 연장하는 전도 바이어스(25)의 제 1 어레이는 전자 장치 상의 도체 패드(12)의 제 1 다수를 외부 접속이 형성되어 있는 도체 패드 주변 어레이를 포함하는 제 1 도체 패턴(29)에 상호 접속시킨다. 전자 장치 상의 도체 패드의 제 2 다수를 제 2 도체 패턴(30)에 상호 접속시키기 위해, 수단은 제 2 비등방성 도체 부재(15), 제 2 평탄 절연 부재(17)를 관통하여 연장하는 전도 바이어스(26)의 제 2 어레이, 전도 바이어스(25)의 제 1 어레이 및, 제 1 비등방성 도체 부재(13)를 포함한다. The external connection is the first anisotropic conductor member 13, the first flat insulating member 14 having the first conductor pattern 29 on the upper surface, the second anisotropic conductor member 15, and the second on the upper surface. By continuously providing the second flat insulating member 17 having the conductor pattern 30 on the electronic device, it is formed in the electronic device having the array of the conductor pads 12 on the upper surface. The two flat insulating members comprise an array of conduction biases 25, 26 extending therebetween. The first anisotropic conductor member 13 and the first array of conduction biases 25 extending through the first flat insulation member 14 form an external connection with a first plurality of conductor pads 12 on the electronic device. The first conductor pattern 29 including the conductor pad peripheral array is interconnected. To interconnect the second plurality of conductor pads on the electronic device to the second conductor pattern 30, the means extends through the second anisotropic conductor member 15, the second flat insulating member 17. A second array of 26, a first array of conduction biases 25, and a first anisotropic conductor member 13 are included.

Printed circuit board and method of manufacturing semiconductor package using the same

本发明提供了一种其结构能防止在矩形孔周围产生裂纹的印刷电路板以及制造用于半导体封装的印刷电路板的方法。该印刷电路板包括其中形成有至少一个窗口狭缝的基部衬底、多个形成于基部衬底至少一个侧面上的电路图案、形成于基部衬底和电路图案上的保护层、以及沿着窗口狭缝的至少一部分边缘形成的并且至少不形成于电路图案上的防裂纹层。

Component structure, power module and power module assembly structure

"COMPOSITE MATERIAL"

Information handling system including a circuitized substrate having a dielectric layer without continuous fibers

An information handling system which includes as part thereof a circuitized substrate comprising a first layer comprised of a dielectric material including a resin material including a predetermined quantity of particles therein and not including continuous fibers, semi-continuous fibers or the like as part thereof, and at least one circuitized layer positioned on the dielectric first layer.

Metal tab for chip assembly

A semiconductor die having a metal tab connected thereto. The metal tab includes at least one slot on at least one side of the metal tab, wherein the at least one slot i) creates an opening between at least two portions of the metal tab and ii) exposes the semiconductor die in relation to the metal tab. The semiconductor die can be a silicon (Si) die and the metal tab can be a copper (Cu) tab, where the at least one slot includes at least four slots corresponding to each of at least four sides of the metal, and wherein with respect to each of the at least four sides, each corresponding slot i) creates an opening between at least two portions of the Cu metal tab and ii) exposes the Si semiconductor die in relation to the Cu metal tab.

Circuitized substrate

A circuitized substrate comprising a first layer comprised of a dielectric material including a resin material including a predetermined quantity of particles therein and not including continuous fibers, semi-continuous fibers or the like as part thereof, and at least one circuitized layer positioned on the dielectric first layer. An electrical assembly and a method of making the substrate is also provided, as is a circuitized structure including the circuitized substrate in combination with other circuitized substrates having lesser dense thru-hole patterns. An information handling system incorporating the circuitized substrate of the invention as part thereof is also provided.

Heat removal assembly for semiconductor power module

本发明涉及一种用于半导体功率模块的排热组件(20)，该排热组件具有三个堆叠的接合配对件(24、26、28)，以及涉及一种具有至少一个排热组件(20)的相应半导体功率模块和一种用于连接排热组件(20)的三个接合配对件(24、26、28)的层堆叠的方法，这些接合配对件(24、26、28)通过第一焊料层(22A)和第二焊料层(22B)材料配合地相互连接。在此，第一焊料层(22A)形成在导电的第一接合配对件(24)和电绝缘的中间接合配对件(26)之间，并且第二焊料层(22B)形成在电绝缘的中间接合配对件(26)和导电的第二接合配对件(28)之间，其中第一接合配对件(24)是待排热的第一导体迹线(24A)，在第一导体迹线上施加有第一电压电势，其中第二接合配对件(28)是用作散热器的第二导体迹线(28A)，在第二导体迹线上施加有与第一电压电势不同的第二电压电势，并且其中中间接合配对件(26)是电绝缘的中间层(26A)，该中间层在第一接合配对件(24)和第二接合配对件(28)之间形成电绝缘的散热路径。

High-frequency chip packages

A microelectronic package is provided in which a first chip(10) having active elements, e.g. amplifying elements(16), and passive elements(14), e.g. resistors, capacitors and inductors, is mounted in electrical communication with a microelectronic element(12) having conductive patterns(18) opposing a front face of the first chip. Absorptive material patterns(26) are disposed between the conductive patterns(18) of the microelectronic element(12) and at least some of the passive elements(14) while leaving at least some of the active elements(16) exposed so as to attenuate radio frequency energy propagated by wave between the passive devices(14) and conductive patterns(18) of the microelectronic element(12).

Electronic device and manufacturing method thereof

本申请公开一种电子设备，包括背板电路，间隔设置于背板电路上的多个导电粘接件，分别设置于多个导电粘接件上的多个电子元件，其中，背板电路与多个电子元件通过多个导电粘接件分别电连接。本申请还进一步公开了一种用于制造前述电子设备的制作方法。

chip assemblies

Eine Chipbaugruppe kann ein Gehäusesubstrat beinhalten, das einen oder mehrere Pins beinhaltet. Die Chipbaugruppe kann auch ein oder mehrere Pads beinhalten. Das eine oder die mehreren Pads können elektrisch mit dem einen oder den mehreren Pins gekoppelt sein. Außerdem kann die Chipbaugruppe eine Platine beinhalten, die ein oder mehrere Platinenpads beinhaltet. Ferner kann die Chipbaugruppe eine anisotrope Schicht beinhalten. Die anisotrope Schicht kann zwischen der Platine und dem einen oder den mehreren Pads und zwischen der Platine und einem Teil des Gehäusesubstrats positioniert sein. Außerdem kann die anisotrope Schicht die Platine mechanisch mit dem einen oder den mehreren Pads und dem Teil des Gehäusesubstrats koppeln. Ferner kann die anisotrope Schicht das eine oder die mehreren Pads elektrisch mit dem einen oder den mehreren Platinenpads koppeln. A chip assembly may include a packaging substrate that includes one or more pins. The chip assembly can also include one or more pads. The one or more pads can be electrically coupled to the one or more pins. In addition, the chip assembly may include a circuit board that includes one or more circuit board pads. Furthermore, the chip assembly may include an anisotropic layer. The anisotropic layer may be positioned between the circuit board and the one or more pads and between the circuit board and a portion of the package substrate. Additionally, the anisotropic layer may mechanically couple the circuit board to the one or more pads and the portion of the package substrate. Further, the anisotropic layer may electrically couple the one or more pads to the one or more board pads.

Method of manufacturing semiconductor substrate material, semiconductor substrate material and semiconductor package

Semiconductor device and packaging method thereof

本申请实施例公开了一种半导体器件的封装方法及半导体器件。本申请实施例提供的技术方案，通过采用接合工具将所述铜箔分别与所述芯片以及所述引线管脚进行压合以使得铜箔产生塑性变形，最终使得铜箔与芯片以及引线管脚之间扩散结合形成铜‑铜结合，通过上述压合的方式来替代原有的通过焊接材料来将铜箔与芯片、引线管脚结合的方式。由于在进行铜箔与芯片及引线框架结合时无需进行焊锡以及清除焊锡操作，进而提高了半导体器件的实际产能，以及提升封装工艺的稳定性；并且由于铜箔与引线框架的表面铜层直接结合可以实现双面散热的效果，进一步提高了半导体器件的散热能力。

Power semiconductor device with pressure contact

In the case of power semiconductor elements having pressure contact, contact surfaces which have different coefficients of thermal expansion lie on top of one another. This can lead to welding of the contact surfaces due to friction. Friction is kept at a low level by providing the contact surfaces (4, 6) with a layer (7, 8) which consists of an amorphous carbon-metal compound. The latter has a lower coefficient of friction with small resistivity. <IMAGE>

Microelectronic assembly including Z-axis conductive film

(57)【要約】 ２個以上のマイクロ電子部品の組立体であって、部品間の電気的及び／又は熱的相互接続が、絶縁フィルム（１６）の穴に固定した複数個の個別伝導性ナノ寸法小繊維（１５）又は小管（１５）により達成される。このようなフィルムは異方性電気伝導度、すなわちＺ軸伝導度を有すると言い、他の方向にはほとんど又は全く伝導度を有さない。

Stacked structure having matrix-fibered composite layers and a metal layer

Herein disclosed is a stacked or laminated structure which is rigidly integrated by sandwiching a metal layer between a first matrix-fiber composite layer prepared to have as a whole a thermal expansion coefficient and a second matrix-fiber layer prepared to have as a whole another thermal expansion coefficient different from that of the first matrix-fiber composite layer. The intervening metal layer acts as a buffer for the first and second matrix-fiber composite layers. The stacked structure according to the present invention can by used as the chip carrier of a semiconductor device, for example.

Microdisplay module with reduced size

公开了一种具有减小尺寸的微显示器模块(21)。常规模块(例如，LCOS型)要求封装基板(23)的较大区域进行容纳并且将平坦柔性电路连接器(32)连接到它们。与LCOS芯片和封装基板处于同一平面中的来自模块的连接或凸起附加地占据了模块外部的显著空间。在具有有限空间的显示系统中，可能没有足够的间隙，从而可能导致组件故障以及复杂的组装和测试。在所公开的模块中，柔性连接器(32)被连接到封装基板(23)的后侧。通过穿过基板(23)的通孔(29)来促成前侧上的连接器(32)与模块焊盘(28)之间的电连接。连接器可以围绕封装基板的边缘弯曲以提供改进的间隙。

Semiconductor device and method for its manufacture

Heat extraction assembly for a semiconductor power module

The invention relates to a heat extraction assembly (20) for a semiconductor power module, comprising three stacked joint partners (24, 26, 28) integrally bonded together by a first soulder layer (22A) and by a second soulder layer (22B), and a corresponding semiconductor power module comprising at least one of these heat extraction assemblies (20) and a method for bonding a layer stack consisting of three joining partners (24, 26, 28) in such a heat extraction assembly (20). The first soulder layer (22A) is formed between a first, electroconducting joining partner (24) and a central, electrically insulating joining partner (26), and the second soulder layer (22B) is formed between the central, electrically insulating joining partner (26) and a second, electroconducting joining partner (28), wherein the first joining partner (24) is a first conducting track (24A) from which heat is to be extracted and to which a first voltage potential is applied, the second joining partner (28) is a second conducting track (28A) that acts as a heat sink and to which a second voltage potential different from the first voltage potential is applied, and the central joining partner (26) is an electrically insulating intermediate layer (26A) that forms an electrically insulated heat-dissipation path between the first joining partner (24) and the second joining partner (28).

Multi-chip laminated packaging structure and packaging method thereof

本发明涉及一种多芯片叠层的封装结构及其封装方法，仅使用一个联结片设置于HS芯片的源极和LS芯片的漏极上实现其电性连接，导电损耗和开关损耗减小，且热耗散效率则得到增强。IC芯片绝缘地连接在联结片上，从而可以叠放到HS芯片及LS芯片所在平面的上方，以有效减少封装后的器件尺寸。本发明中可以将第一、第二载片台的底面暴露在塑封体外；还有多种方法，进一步将联结片上不连接IC芯片的一部分表面暴露在塑封体外；或者在联结片上进一步连接散热板，并使该散热板的一部分表面暴露在塑封体外；或者将散热板插入到塑封体预留的缺口中以接触联结片帮助散热。

Forming Method of Cu to Cu Flip Chip Interconnection and Cu to Cu Flip Chip Interconnection Thereby

본 발명은, (가) 제1 피접합체의 UBM(under bump metallurgy)이나 패드(pad) 상에 구리를 전해도금하여 구리 필라를 형성하는 단계; (나) 상기 구리 필라의 상부 표면에 습식 증착을 통해 물리적으로 결합된 구리 나노 입자 군집체 층을 제조하는 단계; 및 (다) 상기 제1 피접합체 상에 형성된 구리 나노 입자 군집체층을 제2 피접합체 상의 패드에 정렬 위치시켜, 대기 분위기에서 상기 제1 피접합체 및 제2 피접합체 중 적어도 하나를 가압하면서 250℃ 내지 350℃로 가열 소결하여, 상기 제1 피접합체 및 제2 피접합체 접점부를 고상 소결접합시킴으로써 구리-구리 플립칩 인터커넥션부를 형성하는 단계;를 포함하며, 상기 구리 나노 입자 군집체 층은, i) 구리 나노 노듈을 가지는 구리 입자 군집체(aggregate) 층, ii) 구리 나노 노듈을 가지는 구리 프랙탈 군집체 층 및 iii) 구리 나노 노듈을 가지는 구리 산호 군집체 층으로 이루어진 군에서 하나 이상 선택되는 것을 특징으로 하는 구리-구리 플립칩 인터커넥션 형성 방법 및 이에 의해 형성된 구리-구리 플립칩 인터커넥션 형성부에 관한 것이다. The present invention is (A) forming a copper pillar by electroplating copper on an under bump metallurgy (UBM) or a pad of the first to-be-attached body; (B) preparing a copper nanoparticle aggregate layer physically bonded to the upper surface of the copper pillar through wet deposition; and (C) aligning the copper nanoparticle aggregate layer formed on the first to-be-joined body on the pad on the second to-be-adhered body, and pressurizing at least one of the said first to-be-joined body and the second to-be-joined body in an atmospheric atmosphere at 250 degreeC to forming a copper-copper flip-chip interconnection portion by heating and sintering at 350° C. to solid-state sintering the first and second to-be-joined contact portions; The copper nanoparticle aggregate layer, At least one selected from the group consisting of i) a copper particle aggregate layer having copper nanonodules, ii) a copper fractal aggregate layer having copper nanonodules, and iii) a copper coral aggregate layer having copper nanonodules It relates to a copper-copper flip-chip interconnection forming method characterized in that and a copper-copper flip-chip interconnection forming part formed thereby.

Microelectronic assemblies including z-axis conductive films

With the microdisplay module for reducing size

公开了一种具有减小尺寸的微显示器模块(21)。常规模块(例如，LCOS型)要求封装基板(23)的较大区域进行容纳并且将平坦柔性电路连接器(32)连接到它们。与LCOS芯片和封装基板处于同一平面中的来自模块的连接或凸起附加地占据了模块外部的显著空间。在具有有限空间的显示系统中，可能没有足够的间隙，从而可能导致组件故障以及复杂的组装和测试。在所公开的模块中，柔性连接器(32)被连接到封装基板(23)的后侧。通过穿过基板(23)的通孔(29)来促成前侧上的连接器(32)与模块焊盘(28)之间的电连接。连接器可以围绕封装基板的边缘弯曲以提供改进的间隙。

Display device

A display device includes a wire substrate including a wire unit for driving the display device, an integrated circuit chip mounted at the wire substrate, and a pad unit extended from the wire unit to be disposed between the wire substrate and the integrated circuit chip. The pad unit is connected to the integrated circuit chip. The pad unit includes a first conductive layer extended from the wire unit, and a second conductive layer disposed on the first conductive layer. The hardness of the second conductive layer is less than the hardness of the first conductive layer.

Chip package and method of manufacturing the same

Semiconductor device

An object is to provide a semiconductor device capable of reducing inductance between a high potential terminal and a low potential terminal while achieving downsizing of the semiconductor device. A semiconductor device includes: the insulating substrate; the circuit pattern including a low potential circuit pattern and a high potential circuit pattern provided on a region adjacent to the low potential circuit pattern; a plurality of semiconductor chips mounted on the circuit pattern; a low potential terminal having one end portion connected to the low potential circuit pattern; and a high potential terminal having one end portion connected to the high potential circuit pattern, wherein the high potential terminal and the low potential terminal include electrode parts and constituting parallel flat plates vertically disposed in parallel to each other and extending on a side of the low potential circuit pattern and electrode parts and protruding from the insulating substrate.

Chip package and method of manufacturing the same

Dual-side cooling semiconductor packages and related methods

A dual-side cooling (DSC) semiconductor package includes a first metal-insulator-metal (MIM) substrate having a first insulator layer, first metallic layer, and second metallic layer. A second MIM substrate includes a second insulator layer, third metallic layer, and fourth metallic layer. The third metallic layer includes a first portion having a first contact area and a second portion, electrically isolated from the first portion, having a second contact area. A semiconductor die is coupled with the second metallic layer and is directly coupled with the third metallic layer through one or more solders, sintered layers, electrically conductive tapes, solderable top metal (STM) layers, and/or under bump metal (UBM) layers. The first contact area is electrically coupled with a first electrical contact of the die and the second contact area is electrically coupled with a second electrical contact of the die. The first and fourth metallic layers are exposed through an encapsulant.

Chip package and its producing method

(57)【要約】 【課題】 本発明は、第１端子が形成された第１面及び 第２端子が形成された前記第１面に対向する第２面を含 み、前記第１及び第２面上には夫々導電層を成すチップ と、前記チップの第２面に配置され前記第２端子と連結 された導電性バイアホールを設けた基板とを含んだチッ プパッケージを提供し、さらに、本発明は新たなチップ パッケージの製造方法と前記チップパッケージを含むア センブリーを提供する。 【解決手段】 第１端子が形成された第１面と、第２端 子が形成され前記第１面と対向する第２面と、前記第１ 面と第２面の間に形成された側面とを含み、前記第１及 び第２面上には夫々導電層が形成されたチップ、及び、 前記チップの第２面に配置され、前記第２端子と連結さ れる導電性バイアホールが形成された基板を含むチップ パッケージ。

Ein halbleiterbauelement mit einer dose, in der ein halbleiterdie untergebracht ist, der von einer einkapselung eingebettet ist

Halbleiterbauelement (10), welches aufweisteine leitende Dose (11) mit einem flachen Abschnitt (11A) und mindestens einem peripheren Randabschnitt (11B), der sich von einem Rand des flachen Abschnitts (11A) aus erstreckt;einen Halbleiterdie (12) mit einer ersten Hauptfläche und einer zweiten Hauptfläche gegenüber der ersten Hauptfläche, einem ersten Kontaktpad (12A), das auf der ersten Hauptfläche angeordnet ist, und einem zweiten Kontaktpad (12B), das auf der zweiten Hauptfläche angeordnet ist, wobei das erste Kontaktpad (12A) elektrisch mit dem flachen Abschnitt (11A) der Dose (11) verbunden ist;einen säulenartigen elektrischen Zwischenverbinder (13), der mit dem zweiten Kontaktpad (12A) verbunden ist; undeine Einkapselung (14), die unter dem Halbleiterdie (12) so angeordnet ist, dass sie den elektrischen Zwischenverbinder (13) umgibt, wobei eine Außenfläche des elektrischen Zwischenverbinders (13) gegenüber einer Außenfläche der Einkapselung (14) zurückgesetzt ist, wobeider elektrische Zwischenverbinder (13) aus einer Kupfersäule besteht, und wobeider elektrische Zwischenverbinder (13) und die Einkapselung (14) nach außen freigelegt sind, und wobeikein Lot auf der Außenfläche des elektrischen Zwischenverbinders (13) vorhanden ist.

Busbar with dielectric coating

An apparatus includes a busbar and a heat-generating electronic device mounted on a first side of the busbar, the heat-generating electronic device being electrically and thermally coupled to the first side of the busbar. The busbar includes an array of non-planar physical structures on a second side of the busbar opposite the first side of the busbar. The apparatus includes a dielectric coating on the array of non-planar physical structures, the dielectric coating defining a non-planar dielectric surface on the second side of the busbar.

Lighting apparatus using organic light-emitting diode and method of fabricating the same

A lighting apparatus using an organic light-emitting diode and a method of fabricating the same are characterized in that an organic emissive material and a conductive film used as a cathode are deposited on the entire surface of a substrate, and then an organic emissive layer in a lighting area and contact areas becomes separated (disconnected or cut) by laser ablation, simultaneously with the formation of a contact hole for contact with an anode. Next, cathode contact and encapsulation processes are performed using an adhesive containing conductive particles and a metal film. This simplifies the fabrication process of the lighting apparatus without using an open mask (metal mask), which is a complicated tool, thus making it useful especially in roll-to-roll manufacturing.

Package device including capacitor disposed on opposite side of die relative to substrate

A package device is provided. The package device includes a substrate, a plurality of upper lands disposed on one surface of the substrate, a plurality of upper solder balls disposed on the plurality of upper lands, a die connected to the plurality of upper solder balls, a plurality of lower lands disposed on the other surface of the substrate, a plurality of lower solder balls disposed on some of the plurality of lower lands, and a capacitor connected to the lower lands on which the plurality of lower solder balls are not disposed among the plurality of lower lands, provided on an opposite side of the die, and including a height greater than the height of the plurality of lower solder balls.

Package apparatus comprising capacitor disposed opposite die based on substrate

A package device includes a substrate, a plurality of upper lands disposed on one surface of the substrate, a plurality of upper solder balls disposed on the plurality of upper lands, a die connected to the plurality of upper solder balls, a plurality of lower lands disposed on the other surface of the substrate, a plurality of lower solder balls disposed on some of the plurality of lower lands, and a capacitor connected to the lower lands on which the lower solder balls are not disposed among the plurality of lower lands, provided on an opposite side of the die, and including a height greater than the height of the lower solder ball.

半導体モジュール

【課題】低温でのオン抵抗の増大及びターンオフサージ電圧の増大を抑制した、小型で安価な半導体モジュールを得ること。【解決手段】半導体スイッチング素子と、半導体スイッチング素子の第一面及び第一面とは反対側の第二面の一方または双方に設けられ、半導体スイッチング素子の主たる材料の線膨張係数よりも大きい線膨張係数を有し、厚みが半導体スイッチング素子よりも厚い応力印加部と、を備え、応力印加部は、温度変化に伴った応力印加部の熱収縮または熱膨張により、半導体スイッチング素子に圧縮応力または引張応力を生じさせ、半導体スイッチング素子は、圧縮応力又は引張応力の大きさが増加するに従って、半導体スイッチング素子がオンになる閾値電圧が低下する。【選択図】図２

双芯片二极管模块

本发明涉及一种双芯片二极管模块，包括第一导电体、第二导电体、第一芯片、第二芯片、第一塑封体与第二塑封体；在第一导电体的头端与第二导电体的尾端之间设有第一芯片，在第一芯片的外部设有第一塑封体，在第一导电体的尾端与第二导电体的头端之间设有第二芯片，在第二芯片的外部设有第二塑封体。本发明采用双芯片分流的方式降低芯片正向工作时的功耗，同样的电流输入功耗可以降低一半。本发明中，单个芯片的散热面积更大，芯片分开布局减少了互相热量的影响，在一定程度上提升了接线盒额定电流。本发明中，芯片与导电体直接连接减少了中间连接，减少了热传导的距离，散热更快。

元件模块

实施方式的元件模块具备：冷却器、多个元件以及导电部件。冷却器具有设于规定方向的两侧的第一元件配置部以及第二元件配置部。多个元件分别配置于第一元件配置部以及第二元件配置部。导电部件配置于冷却器的空间部。空间部在第一元件配置部以及第二元件配置部各自的多个元件之间贯通冷却器。空间部使第一元件配置部以及第二元件配置部连通。导电部件与第一元件配置部的元件和第二元件配置部的元件连接。

Semiconductor device comprising a can housing a semiconductor die which is embedded by an encapsulant

A semiconductor device includes a conductive can include a flat portion and at least one peripheral rim portion extending from an edge of the flat portion, a semiconductor die comprising a first main face and a second main face opposite to the first main face, a first contact pad disposed on the first main face and a second contact pad disposed on the second main face, wherein the first contact pad is electrically connected to the flat portion of the can, an electrical interconnector connected with the second contact pad, and an encapsulant disposed under the semiconductor die so as to surround the electrical interconnector, wherein an external surface of the electrical interconnector is recessed from an external surface of the encapsulant.

一种减少ipm模块注塑溢料的方法和dbc基板

本发明公开了一种减少IPM模块注塑溢料的方法和DBC基板，该方法改变DBC基板上孤岛设计，使DBC基板在注塑工艺中受力平衡；并且，在DBC基板背面的DBC背面铜层设计“楔形”台面结构，形成注塑料在DBC基板背面流速的缓冲台，在DBC基板不平情况下，减小注塑料向DBC基板背面外溢的溢料。本发明通过改变DBC设计思路，来减少溢料的方法来替代激光去毛刺工艺，提高生产效率，降低生产成本与工艺投入。

Flächiges teil für halbleitergehäuse

Packaging structure and communication device

Embodiments of the present invention disclose a package structure and a communications device. The package structure includes a substrate, a chip, a bonding layer, and a coating. A plurality of grooves are disposed on the substrate. Silver bonding materials are disposed in the plurality of grooves and on a surface of the substrate, to form the bonding layer. The chip is connected to the substrate by using the bonding layer. The plurality of grooves are symmetrically arranged along a first axis of symmetry and a second axis of symmetry that are perpendicular to each other, a vertical projection of the chip on the substrate is centrosymmetric about the first axis of symmetry and the second axis of symmetry, a groove in the plurality of grooves that faces a periphery of the chip is an outer-ring groove, and the vertical projection of the chip on the substrate covers a partial area of the outer-ring groove. The coating covers a surface that is of the bonding layer and that is not in contact with the substrate or the chip, and is used to prevent migration of silver ions in the bonding layer. The package structure provided in the embodiments of the present invention has an advantage of low thermal resistance and good heat dissipation efficiency, thereby prolonging a service life of a power amplifier.

estrutura de pacote e dispositivo de comunicações

Modalidades desta presente invenção revelam uma estrutura de pacote e um dispositivo de comunicações. A estrutura de pacote inclui um substrato, um chip, uma camada de ligação, e um revestimento. Uma pluralidade de ranhuras são dispostas no substrato. Materiais de ligação de prata são dispostos na pluralidade de ranhuras e em uma superfície do substrato, para formar a camada de ligação. O chip é conectado ao substrato usando-se a camada de ligação. A pluralidade de ranhuras são simetricamente dispostas ao longo de um primeiro eixo de simetria e de um segundo eixo de simetria que são perpendiculares entre si, uma projeção vertical do chip no substrato é centrossimétrica em torno do primeiro eixo de simetria e do segundo eixo de simetria, uma ranhura na pluralidade de ranhuras que está voltada para uma periferia do chip é uma ranhura de anel externo, e a projeção vertical do chip no substrato cobre uma área parcial da ranhura de anel externo. O revestimento cobre uma superfície que é da camada de ligação e que não está em contato com o substrato ou com o chip, e é usado para impedir a migração de íons de prata na camada de ligação. A estrutura da pacote fornecida nas modalidades da presente invenção tem uma vantagem de baixa resistência térmica e boa eficiência de dissipação de calor, prolongando assim a vida útil de um amplificador de potência.

Semiconductor device

According to one embodiment, a semiconductor device includes at least a package substrate, an external electrode, a mounting substrate, and a mounting electrode. A signal connection point of the external electrode is provided at an end portion in a longitudinal direction of the external electrode. A signal connection point of the mounting electrode is provided at an end portion of the mounting electrode. The end portion of the mounting electrode is opposite to the signal connection point of the external electrode facing to the mounting electrode in the longitudinal direction.