СПОСОБ И УСТРОЙСТВО ДЛЯ ОЧИСТКИ, РАЗДЕЛЕНИЯ, МОДИФИКАЦИИ И/ИЛИ ИММОБИЛИЗАЦИИ ХИМИЧЕСКИХ ИЛИ БИОЛОГИЧЕСКИХ ОБЪЕКТОВ, НАХОДЯЩИХСЯ В ТЕКУЧЕЙ СРЕДЕ, И ОПОРА ИЗ МИКРОПРОВОЛОКИ

... 1. Устройство для очистки, разделения, модификации и/или иммобилизации химических или биологических объектов, находящихся в текучей среде, посредством связывания химического или биологического объекта с функциональным покрытием или лигандами, находящимися на поверхности опор из микропроволоки при отсутствии воздействия магнитного поля, создаемого между опорами из микропроволоки и частицами, находящимися в текучей среде, на разделение названных частиц, которое содержит по меньшей мере одну опору из микропроволоки, закрепленную своими концами и имеющую многослойную структуру, состоящую из центрального стержня и по меньшей мере одного покрывающего слоя и пригодную для связывания химических или биологических объектов, при этом поверхность микропроволоки модифицирована путем присоединения лигандов или нанесением на нее функционального покрытия. ! 2. Устройство по п.1, в котором центральный стержень и покрывающие слои выполнены из материала, выбранного из группы, включающей стеклянный, металлический ...

Halbleiteranordnung mit Metallplatte

ELEKTRONISCHES BAUELEMENTGEHÄUSE

Die Technologie eines elektronischen Bauelementgehäuses ist offenbart. Ein elektronisches Bauelementgehäuse gemäß der vorliegenden Offenbarung kann ein Gehäusesubstrat, eine elektronische Komponente, eine Formmasse, die die elektronische Komponente einkapselt, und eine Redistributionsschicht umfassen, die derart angeordnet ist, dass die Formmasse zwischen dem Gehäusesubstrat und der Redistributionsschicht ist. Die Redistributionsschicht und das Gehäusesubstrat können elektrisch gekoppelt sein. Außerdem können die Redistributionsschicht und die elektronische Komponente elektrisch gekoppelt sein, um die elektronische Komponente und das Gehäusesubstrat elektrisch zu koppeln. Zugeordnete Systeme und Verfahren sind auch offenbart.

Leistungsmodul

Ein Leistungsmodul ist so aufgebaut, dass ein Leistungsvorrichtungschip (5) innerhalb eines äußeren Gehäuses (1) angeordnet ist und eine Elektrode des Leistungsvorrichtungschips (5) mit einer externen Elektrode (10a) verbunden ist, die in dem äußeren Gehäuse (1) integriert ist. Das Leistungsmodul enthält: einen Wärmeverteiler (3), der in dem äußeren Gehäuse (1) befestigt ist, den Leistungsvorrichtungschip (5), der mit Lot auf den Wärmeverteiler (3) gebondet ist, einen isolierenden Damm (4), der auf dem Wärmeverteiler (3) so gebildet ist, dass er den Leistungsvorrichtungschip (5) umgibt, und eine interne Hauptelektrode (7), deren eines Ende mit Lot auf die Elektrode des Leistungsvorrichtungschips (5) gebondet ist und deren anderes Ende an einer oberen Oberfläche des Dammes befestigt ist. Die externe Elektrode (10a) und das andere Ende der internen Hauptelektrode (7) sind durch Drahtbonden elektrisch miteinander verbunden.

Halbleitermodul

Es wird eine Technik zur Verbesserung der Kühlkapazität eines Halbleitermoduls, welches Pin-Bonding verwendet, vorgesehen. Das Halbleitermodul enthält: einen Pin (4), der mit einem Halbleiterelement (1) verbunden ist; ein Pin-Verdrahtungssubstrat (5), das einen zweiten Metallfilm (5c) und einen ersten Metallfilm (5b) auf der oberen bzw. unteren Oberfläche hat, wobei der erste Metallfilm (5b) und der zweite Metallfilm (5c) mit dem Pin (4) elektrisch verbunden sind; Lot (3c), das den Pin (4) und das Halbleiterelement (1) verbindet; ein DCB-Substrat (2), das einen dritten Metallfilm (2b) und einen vierten Metallfilm (2c) auf der oberen bzw. unteren Oberfläche hat, wobei der dritte Metallfilm (2b) an eine untere Oberfläche des Halbleiterelements (1) gebondet ist; und einen ersten Kühler (6), der mit dem vierten Metallfilm (2c) verbunden ist. Das Verhältnis (H/T) einer Höhe (H) des Lots zu einem Abstand (T) von dem Halbleiterelement (1) zu dem ersten Metallfilm (5b) ist gleich oder größer als ...

Packungen für drahtlose Signalübertragung mit integrierter Antennengruppe

Antennenpackungsstrukturen werden bereitgestellt, um Packungen für drahtlose Signalübertragung zu implementieren. Eine Antennenpackung enthält zum Beispiel ein mehrschichtiges Packungssubstrat, eine ebene Antennengruppe, Antennenspeiseleitungen und Widerstandsübertragungsleitungen. Die ebene Antennengruppe beinhaltet eine Gruppe von aktiven Antennenelementen und künstliche Antennenelemente, die die Gruppe von aktiven Antennenelementen umgeben. Jedes aktive Antennenelement ist mit einer entsprechenden Antennenspeiseleitung verbunden, und jedes künstliche Antennenelement ist mit einer entsprechenden Widerstandsübertragungsleitung verbunden. Jede Widerstandsübertragungsleitung verläuft durch das mehrschichtige Packungssubstrat und endet in derselben Metallisierungsschicht des mehrschichtigen Packungssubstrats.

Leistungsmodul

Das Leistungsmodul weist mindestens ein elektrisches Bauteil mit einer Kontaktfläche auf, wobei welchem das elektrische Bauteil mittels der Kontaktfläche an mindestens ein mit offenporigem Material gebildetes Kontaktstück des Leistungsmoduls elektrisch kontaktiert ist und das zumindest eine elektrische Bauteil und das zumindest eine Kontaktstück, zumindest in Richtungen der flächigen Erstreckungen der mindestens einen Kontaktfläche, relativ zueinander zumindest formschlüssig festgelegt sind.

Optoelektronisches Bauelement und Verfahren zur Herstellung von optoelektronischen Halbleiterbauelementen

Es wird ein optoelektronisches Halbleiterbauelement (1) mit einem Träger (5) und einem Halbleiterkörper (2) angegeben, wobei der Halbleiterkörper an dem Träger befestigt ist und eine Halbleiterschichtenfolge mit einem zum Erzeugen und/oder zum Empfangen von Strahlung vorgesehenen aktiven Bereich (20), einer ersten Halbleiterschicht (21) und einer zweiten Halbleiterschicht (22) aufweist. Der aktive Bereich ist zwischen der ersten Halbleiterschicht und der zweiten Halbleiterschicht angeordnet. Der Träger ist elektrisch leitfähig und in einen ersten Trägerkörper (51) und einen zweiten Trägerkörper (52) unterteilt, wobei der erste Trägerkörper und der zweite Trägerkörper voneinander elektrisch isoliert sind. Der erste Trägerkörper weist auf der dem Halbleiterkörper abgewandten Seite einen ersten externen Kontakt (61) des Halbleiterbauelements auf, wobei der erste Kontakt über den ersten Trägerkörper mit der ersten Halbleiterschicht elektrisch leitend verbunden ist. Der zweite Trägerkörper weist ...

PARALLELEBENENSUBSTRAT

Halbleitervorrichtung

Eine Halbleitervorrichtung kann ein erstes isoliertes Substrat, einen ersten Halbleiterchip sowie einen zweiten Halbleiterchip, die auf dem ersten isolierten Substrat angeordnet sind, ein zweites isoliertes Substrat, das zu dem ersten isolierten Substrat gegenüberliegend ist, wobei der erste Halbleiterchip dazwischen angeordnet ist, und ein drittes isoliertes Substrat umfassen, das zu dem ersten isolierten Substrat gegenüberliegend ist, wobei der zweite Halbleiterchip dazwischen angeordnet ist, und Seite an Seite mit dem zweiten isolierten Substrat angeordnet ist.

Miniaturisiertes SMD-Diodenpaket und Herstellungsverfahren dafür

Miniaturisiertes SMD-Diodenpaket (10), umfassend:einen Diodenchip (30a, 30b, 30c) mit einer TVS-Diode, einer Schottkydiode, einer Schaltdiode, einer Zenerdiode oder einer Gleichrichterdiode, der eine Bodenfläche aufweist, die mit einer positiven Elektrode (31) und einer negativen Elektrode (31) versehen ist;eine Bodenleiterplatte (50) aus einer Keramikplatte, einer Kunststoffplatte, einer Verbundplatte oder einer wärmeableitenden Platte;zwei Schaltkreiselektroden (56a, 56b), die separat auf der Bodenleiterplatte (50) aufgebracht sind und elektrisch mit der jeweiligen positiven Elektrode und negativen Elektrode (31) an der Bodenfläche des Diodenchips (30a, 30b, 30c) verbunden sind;eine Kapselung (75) aus einem Keramikmaterial oder einem Kunststoffmaterial zur Bildung einer integrierten Struktur mit der Bodenleiterplatte (50), um den Diodenchip (30a, 30b, 30c) und die zwei Schaltkreiselektroden (56a, 56b) zu kapseln, derart dass sich jeweils ein Ende der zwei Schaltkreiselektroden (56a, 56b ...

Leistungshalbleitermodul und Verfahren zur Herstellung eines Leistungshalbleitermoduls

Ein Leistungshalbleitermodul kann einen Träger, einen Leistungshalbleiterchip, der so über dem Träger angeordnet ist, dass eine erste Hauptseite des Leistungshalbleiterchips dem Träger zugewandt ist, einen Kontaktclip, der so über dem Leistungshalbleiterchip angeordnet ist, dass eine zweite, der ersten Hauptseite gegenüberliegende Hauptseite des Leistungshalbleiterchips; dem Kontaktclip zugewandt ist, und ein zwischen der zweiten Hauptseite und dem Kontaktclip angeordnetes Abstandshalterelement umfassen, wobei eine erste Lötverbindung die zweite Hauptseite und das Abstandshalterelement verbindet und wobei eine zweite Lötverbindung das Abstandshalterelement und den Kontaktclip verbindet.

HALBLEITER-BAUELEMENT UND VERFAHREN ZU DESSEN HERSTELLUNG

Ein Verfahren weist die folgenden Schritte auf: Herstellen einer Vorrichtungsstruktur, wobei das Herstellen der Vorrichtungsstruktur das Herstellen einer ersten Umverteilungsstruktur über und in elektrischer Verbindung mit einer Halbleitervorrichtung und das Herstellen eines Formmaterials um die erste Umverteilungsstruktur und die Halbleitervorrichtung umfasst; Herstellen einer zweiten Umverteilungsstruktur über dem Formmaterial und der ersten Umverteilungsstruktur, wobei die zweite Umverteilungsstruktur mit der ersten Umverteilungsstruktur elektrisch verbunden ist; Befestigen einer Verbindungsstruktur an der zweiten Umverteilungsstruktur, wobei die Verbindungsstruktur ein Kernsubstrat aufweist und mit der zweiten Umverteilungsstruktur elektrisch verbunden ist; und Abscheiden eines Unterfüllungsmaterials auf Seitenwänden der Verbindungsstruktur und zwischen der zweiten Umverteilungsstruktur und der Verbindungsstruktur.

Electrical assembly comprises cooler structure and electrical component on metal-ceramic substrate having electrical module, where electrical module comprises two metal-ceramic substrates

Electrical assembly comprises cooler structure and an electrical component (6) on a metal-ceramic substrate (4,5) having electrical module. The electrical module comprises two metal-ceramic substrates, where each substrate includes a ceramic layer (7,10), which are provided with partially structured metal plating (9,12). An active cooler (2,3) and an electrical component are also provided between two metal-ceramic substrates, which are thermally connected.

Input/output architecture for mounted processors, and methods of using same

Microelectronic package and method of manufacturing same

Optoelectronic module package

Nput/output architechture for mounted processors, and methods of using same

Method of achieving a functional electronic textile

VERFAHREN ZUM BEFESTIGEN EINER MIT LEITERSPUREN VERSEHENEN ISOLIERENDEN FOLIE AN STROMLEITERN AUF EINEM SUBSTRAT.

SINGLE-CHIP MODULE INTEGRATED CIRCUITS

平行平面式基板

... 一种具有多个介电材料和导电材料交替的大致平面层的微电子基板，还具有第一平面和第二表面，其中介电材料和导电材料层在第一和第二表面间基本上垂直地延伸。 ...

Electrical interconnection device for connecting power supply electricity with at least one electronic component and related electronic system

An electrical interconnection device includes a first terminal, a second terminal, an insulation substrate, a first conduction layer and a current conduction loop. The insulation substrate includes parallel top and bottom surfaces. The first conduction layer is set to contact with the top surface, and includes a bonding pad and current traces for connecting the electronic components. The first conduction layer forms a first current conduction plane. The current conduction loop is arranged between the first terminal and the second terminal, includes the traces and has an inductance. The device includes a component for reducing loop inductance. The component comprises a second conduction layer and an electrical connection piece. The second conduction layer is set to contact with the bottom surface. The second layer forms with a second conduction plane parallel to the first plane. The electrical connection piece is between the two planes. The first terminal is connected to the first plane ...

Provided for the semiconductor chip are connected with each other intermediary substrate method and apparatus

LSI circuit chip package with carrier and underlying substrate

La présente invention concerne un ensemble à dispositif électronique comprenant une puce à circuit intégré à grande échelle (LSI) ayant des parties centrale (4a) et périphérique (4b). Un circuit et des bornes sont formés dans les parties centrale (4a) et périphérique (4b), respectivement. Un substrat porteur est fixé à la partie centrale de la puce LSI. Le substrat porteur (3) a des parties centrale (4a) et périphérique (4b). Des gouttes et des bornes font prévues dans les parties centrale (4a) et périphérique (4b), respectivement du substrat porteur (3). Des fils connectent les bornes de la puce LSI et du substrat porteur (3). Le substrat porteur (3) est monté sur un substrat par l'intermédiaire des gouttes. Le coefficient de dilatation thermique est compris entre ceux de la puce LSI et du substrat.

ELECTRONIC DEVICE HAVING AN INTEGRATED PASSIVE COMPONENTS

MICROWAVE PACKAGE WITH REDUCED SPACE IN SURFACE AND MOUNTAIN SUCH A CASING ON A CIRCUIT.

SUPPORT FOR ELECTRIC COMPONENT AND ELECTRIC DEVICE INCLUDING/UNDERSTANDING LESUPPORT AND THE COMPONENT

Ce support (12) comprend une partie métallique (PM) conductrice destinée à être chauffée pour l'assemblage du composant électrique (22) sur la partie métallique (PM). Il comprend également une partie en matériau synthétique (PS), jointive avec la partie métallique (PM), assurant la cohésion du support (12). Cette partie en matériau synthétique (PS) comprend une masse de basse température de fusion (14) et une masse de haute température de fusion (16), intercalée entre la masse de basse température de fusion (14) et la partie métallique (PM). Plus particulièrement, la masse de haute température de fusion (16) est réalisée dans un matériau ayant une température de fusion supérieure à la température de fusion de la masse de basse température de fusion (14).

LSI electronic circuit support assembly

Assemblage de dispositifs électroniques comprenant un boîtier de support de bande (1) supportant un circuit LSI (2) et ayant des trous traversants (8) disposés bidimensionnellement dans un film et connectés électriquement au circuit LSI par un motif de câblage, et un substrat isolant (3) ayant des broches d'entrée/sortie (4) connectées à des pastilles (9) fournies sur un substrat de montage (6), s'étendant dans et en contact avec les trous (8). Le boîtier de support de bande peut être fabriqué de façon aussi peu coûteuse que le boîtier TBGA de l'état de l'art, à un coût inférieur à celui d'un câblage similaire utilisant un substrat stratifié céramique. La constante diélectrique et d'autres facteurs du matériau du substrat isolant (3) n'ont pas à être pris en compte, et on peut utiliser le matériau le moins coûteux.

TRANSMISSION DEVICE RF INTEGRATED ELECTROMAGNETIC WAVE REFLECTOR

Dispositif de transmission RF (100) comprenant au moins : - un substrat (102) comportant des première et deuxième faces (104, 106) opposées l'une de l'autre ; - un premier circuit électronique de transmission RF (108) disposé sur et/ou dans le substrat ; - une première antenne (112a) disposée du côté de la première face du substrat, espacée de la première face du substrat et reliée électriquement au premier circuit électronique de transmission RF ; - un premier réflecteur d'ondes électromagnétiques couplé à la première antenne et comprenant : - une première surface à haute impédance (114a) comportant au moins plusieurs premiers éléments électriquement conducteurs (118) formant une première structure périodique et disposés sur la première face du substrat en regard de la première antenne ; - un premier plan de masse électriquement conducteur (116a) disposé au moins partiellement en regard de la première antenne.

PROCESS FOR MANUFACTURING HOUSINGS FOR ROBUST BE PLOTTED ON A MULTILAYER PRINTED CIRCUIT

L'invention concerne un procédé de fabrication collective de boîtiers BGA destinés à être reportés sur un panneau de PCB d'au moins 4 couches. A partir d'un panneau PCB à une couche dit panneau PCB fin, comportant sur une face verso des billes de connexion sans plomb qui ont une température de fusion Tl, et des plots d'interconnexion sans plomb sur une face recto, le procédé comporte les étapes de : - apport de métal sur chaque plot du panneau PCB fin, ce métal ayant une température de fusion supérieure à Tl d'au moins 200°C, - report de boîtiers BGA munis de billes de connexion sans plomb sur la face recto du panneau PCB fin, pour que les billes des boîtiers coïncident avec les plots munis de leur apport de métal et fusion des billes au métal pour dissoudre le métal dans les billes, la température de fusion de ces nouvelles billes étant supérieure à Tl d'au moins 30°C, - dépôt d'une résine d'enrobage des boîtiers BGA, la résine remplissant le volume compris entre le boîtier et le PCB fin ...

Semiconductor package film having reinforcement material and display module applying them

SIDE BRAZE PACKAGE

Multilayer Wiring Substrate

반도체 패키지 및 반도체 패키지 모듈

... 범프를 통하여 회로 기판과 연결되는 반도체 패키지가 제공된다. 본 발명의 일 실시예에 따른 반도체 패키지는, 복수개의 접속 패드가 노출되도록 형성된 반도체 칩; 상기 각 접속 패드 상에 형성되며, 제1 필라부 및 상기 제1 필라부 상측에 형성되는 제1 솔더부를 포함하는 연결용 범프들; 상기 접속 패드 주변에서 상기 접속 패드의 상부 표면 보다 높은 위치에 형성되며, 솔더 유도부가 형성되어 있는 제2 필라부 및 상기 제2 필라부 상측에 형성되는 제2 솔더부를 포함하는 지지용 범프들;을 포함한다.

이중 랜드를 갖는 반도체패키지 및 관련된 장치

... 이중 랜드(dual land)를 갖는 반도체패키지를 제공한다. 상기 반도체패키지는 다수의 내부 패드들을 갖는 기판을 구비한다. 반도체 칩이 상기 기판에 부착된다. 상기 반도체 칩은 상기 내부 패드들에 전기적으로 접속된다. 상기 기판에 형성되고 상기 내부 패드들에 전기적으로 접속된 다수의 랜드들을 제공한다. 상기 기판에 형성된 적어도 하나의 우회배선을 제공한다. 상기 우회배선은 제 1 랜드 및 제 2 랜드에 접속된다. 상기 제 1 랜드는 상기 랜드들 중 선택된 하나이고, 상기 제 2 랜드는 상기 랜드들 중 선택된 다른 하나이다. 상기 제 1 랜드 및 상기 제 2 랜드는 상기 랜드들 사이의 평균거리보다 3배 이상 떨어진다.

SEMICONDUCTOR PACKAGE, CAPABLE OF SHIELDING AN ELECTROMAGNETIC WAVE

PURPOSE: A semiconductor package is provided to reduce an impedance of a whole semiconductor package by shielding an electromagnetic wave. CONSTITUTION: A semiconductor package includes a printed circuit board, a semiconductor chip(106), a first metal wire(110), a metal plate(108), a second metal wire(112), and an encapsulation agent(116). The printed circuit board has an electrode terminal on a side. The semiconductor chip is arranged on a plane of the printed circuit board. The first metal wire couples a bonding pad of the semiconductor bonding pad to the electrode terminal of the printed circuit board electrically. The metal plate is arranged on an upper part of the semiconductor chip. The second metal wire connects the metal plate to the electrode terminal of the printed circuit board electrically. The encapsulation agent encapsulates a plane of the printed circuit board having the metal plate and the first and second metal wires. © KIPO 2008 ...

TAPE SUBSTRATE FOR A TAPE PACKAGE HAVING A REINFORCEMENT LAYER WITH GUIDE HOLE, ESPECIALLY FOR HAVING THE GUIDE HOLE GREATER THAN SPROCKET HOLE

PURPOSE: A tape substrate for a tape package having a reinforcement layer is provided to prevent a guide pin from being mechanically contacted with the reinforcement layer by contacting the guide pin with a base film portion, on which a sprocket hole is formed. CONSTITUTION: A tape substrate includes a base film(210), a wiring pattern, and a reinforcement layer(230). Sprocket holes are formed along both boundary regions of the base film. The sprocket holes are apart from each other by a constant distance. The wiring pattern is formed on at least one surface of the base film between the sprocket holes. The reinforcement layer is formed on a boundary region of a lower surface of the base film. Guide holes are formed on the metallic reinforcement layer, such that the guide holes correspond to the sprocket holes. © KIPO 2007 ...

METHOD FOR MANUFACTURING ELECTRONIC-COMPONENT BUILT-IN BOARD, RELATED TO HIGHER-DENSITY MOUNTING OF ELECTRONIC PARTS INCLUDING SEMICONDUCTOR ELEMENTS

PURPOSE: A method for manufacturing an electronic-component built-in board is provided to facilitate the manufacturing by forming a resin layer between two wiring circuit boards on which electronic components are mounted wherein the electronic-component mounted faces are faced to each other, and compression-bonding the resin layer and the boards. CONSTITUTION: A process for producing a circuit board(7) having built-in electronic parts, which comprises the steps of disposing two wiring circuit boards(2) having an electronic part(1) mounted thereon respectively so that the electronic-part-mounting sides of the respective circuit boards face each other; disposing a resin layer(3) between the circuit boards; and press-bonding the resin layer to the circuit boards. © KIPO 2006 ...

LANDSIDE STIFFENING CAPACITORS TO ENABLE ULTRATHIN AND OTHER LOW-Z PRODUCTS

Embodiments of systems, devices, and methods to minimize warping of ultrathin IC packaged products are generally described in the present invention. In some embodiments, an apparatus comprises an IC mounted on a package substrate and a capacitive stiffener subassembly mounted on the package substrate. The capacitive stiffener subassembly comprises a plurality of capacitive elements electrically connected to contact points of the IC. COPYRIGHT KIPO 2016 ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME BY PROVIDING STACKED MEMBER BETWEEN SUBSTRATES

PURPOSE: A semiconductor device and a method for fabricating the same are provided to prevent particles or dust from trespassing in a device between a pair of substrates and suppress deterioration of the device. CONSTITUTION: A semiconductor device comprises a transistor over a first substrate, a first insulation layer formed on the transistor, a conductive layer(52) electrically connected to a source or a drain of the transistor through an opening formed in the first insulation layer, a second insulation layer formed on the conductive layer, and a second substrate provided on the second insulation layer. A thickness of each of first and second substrates is 100 micrometers or less. At least one of the first substrate and the second substrate is a glass substrate. At least one of a sealing material and a spacer is provided between the first substrate and the second substrate. © KIPO 2007 ...

SEMICONDUCTOR DEVICE

An objective of the present invention is to improve the performance of a semiconductor device. A high-speed transmission path (SGP1) of a semiconductor device (PKG1) includes a connection portion (CP1) for electrically connecting a semiconductor chip (10) and an interposer (40); a connection portion (CP2) for connecting the interposer (40) and a wiring substrate (30); and an external terminal portion (CP3) formed on the lower surface (3b) of the wiring substrate (30). In addition, the high-speed transmission path (SGP1) includes a transmission portion (TP1) installed in the interposer (40) and electrically connecting the connection portion (CP1) and the connection portion (CP2), and a transmission portion (TP2) installed on the wiring substrate (30) and electrically connecting the connection portion (CP2) and the external terminal portion (CP3). Moreover, in the high-speed transmission path (SGP1), one end portion thereof is connected to a branch portion (BR1) in the middle of the transmission ...

Package on package structure

A package on package structure including a first package structure, a plurality of bumps and a second package structure is provided. The first package structure includes a carrier, a chip, a heat spreader and an encapsulant. The chip is disposed on the carrier and electrically connected to the carrier through a plurality of conductive wires. The heat spreader includes a supporting portion and a plurality of connecting portion. The heat spreader has a circuit layer formed thereon. The supporting portion is located on the chip and the connecting portions are located respectively at two opposite sides of the supporting portion. The head spreader covers the chip and the conductive wires and is electrically connected to the carrier through the circuit layer on the connecting portion. The encapsulant encapsulates the chip, the conductive wires, a portion of the heat spreader and a portion of the carrier. The second package structure is disposed on the first package structure and is electrically ...

Semiconductor package and method for manufacturing the same

A semiconductor package includes a semiconductor chip, a first substrate layer and a second substrate layer. The semiconductor chip has an active surface and a plurality of pads disposed on the active surface. The first substrate layer is formed on the active surface of the semiconductor chip and has a plurality of first contacts electrically connected to the pads of the semiconductor chip. The second substrate layer is substantially smaller than the first substrate layer, is formed on the first substrate layer, and has a plurality of second contacts electrically connected to the first contacts of the first substrate layer.

Solid state device miniaturization

One or more example embodiments of miniaturized electric devices are disclosed. In some example embodiments, the electric device includes a first thin substrate layer and a second thin substrate layer positioned above the first thin substrate layer. The electric device further includes one or more components electrically coupled to the first thin substrate layer. An overmold compound is deposited covering the one or more components between the first thin substrate and the second thin substrate. The electric device further includes one or more through mold vias that electrically and communicatively connect the first thin substrate layer and the second thin substrate layer.

Method for forming the package structure

A method for forming the package structure is provided. The method includes forming a die structure over a first surface of a first substrate, and forming a plurality of electrical connectors below a second surface of the first substrate. The method also includes forming a first protruding structure below the second surface of the first substrate, and the electrical connectors are surrounded by the first protruding structure. The method further includes forming a second protruding structure over a second substrate, and bonding the first substrate to the second substrate. The electrical connectors are surrounded by the second protruding structure, and the first protruding structure does not overlap with the second protruding structure.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING SUPPORTING LAYER OVERSEMICONDUCTOR DIE IN THIN FAN-OUTWAFER LEVEL CHIP SCALE PACKAGE

Package and package method thereof

A method includes bonding an antenna substrate to a redistribution structure. The antenna substrate has a first part of a first antenna, and the redistribution structure has a second part of the first antenna. The method further includes encapsulating the antenna substrate in an encapsulant, and bonding a package component to the redistribution structure. The redistribution structure includes a third part of a second antenna, and the package component includes a fourth part of the second antenna.

Manufacturing method of package-on-package structure

Component embedded package carrier and manufacturing method thereof

ELECTRONIC SYSTEM PROVIDED WITH A PLURALITY OF INTERCONNECTED ELECTRONIC FUNCTIONS

ELECTRONIC SYSTEM PROVIDED WITH A PLURALITY OF INTERCONNECTED ELECTRONIC FUNCTIONS Electronic system provided with a plurality of interconnected electronic functions. - The electronic system (1) includes a connection ring (2) comprising a plurality of alternately conductive and insulating superposed layers, the superposed conductive layers (C) being linked to one another by electrical links (5) forming an interconnect network, said connection ring (2) comprising an inner cavity (3), the electronic system (1) also including a plurality of electronic functions (4A, 4B) that are arranged inside the inner cavity (3) of said connection ring (2) over a plurality of levels (N1, N2), with at least one electronic function (4A, 4B) per level (N1, N2), each of said electronic functions (4A, 4B) being linked to the connection ring (2) at the level of the inner face (2A) of the latter. [Figure 1] ...

Wire bonding structure and method that eliminates special wire bondable finish and reduces bonding pitch on substrates

Package stucture with embedded capacitor and applications thereof

Integrated circuit packaging system with post type interconnector and method of manufacture thereof

WIRE BOND INTERCONNECTION

A wire bond interconnection between a die pad and a bond finger includes a support pedestal at a bond site of the lead finger, a ball bond on the die pad, and a stitch bond on the support pedestal, in which a width of the lead finger at the bond site is less than a diameter of the support pedestal. Also, a semiconductor package including a die mounted onto and electrically connected by a plurality of wire bonds to a substrate, in which each of the wire bonds includes a wire ball bonded to a pad on the die and stitch bonded to a support pedestal on a bond site on a lead finger, and in which the width of the lead finger at the bond site is less than the diameter of the support pedestal. Also, such a package in which the package substrate includes a two-tier substrate, each tier including a plurality of lead fingers having a lead finger bond pitch about twice the die pad pitch, the lead fingers of the first tier and the second tier having a staggered arrangement. In some embodiments the support ...

STACKABLE MOLDED MICROELECTRONIC PACKAGES WITH AREA ARRAY UNIT CONNECTORS

A microelectronic package (290) having a (substrate 230), a microelectronic element (170), e.g., a chip, and terminals (240) can have conductive elements (238) electrically connected with element contacts of the chip and contacts of the substrate. Conductive elements can be electrically insulated from one another for simultaneously carrying different electric potentials. An encapsulant (201) can overlie the first surface (136) of the substrate and at least a portion of a face (672) of the microelectronic element remote from the substrate, and may have a major surface (200) above the microelectronic element. A plurality of package contacts (120, 220, 408, 410, 427) can overlie a face (672) of the microelectronic element remote from the substrate. The package contacts, e.g., conductive masses (410), substantially rigid posts (120, 220), can be electrically interconnected with terminals (240) of the substrate (230), such as through the conductive elements. The package contacts can have top ...

MULTI CHIP MODULE AND FABRICATION METHOD THEROF

A multi chip module and a fabrication method thereof are provided. The multi chip module includes: a plate; a substrate adhered to the plate, and having a chip and a signal pattern formed thereat; and a stopper formed at the plate, and defining a region where the substrate is adhered. The method includes: providing a plate connected with a lead, and having a region defined by a stopper; adhering a substrate having a chip and a signal pattern, to the region defined by the stopper on the plate; and wire bonding the signal pattern with the lead.

SUBSTRATE WITH BUILT-IN CHIP AND METHOD FOR MANUFACTURING SUBSTRATE WITH BUILT-IN CHIP

A method for manufacturing a substrate having a built-in chip is provided with a first step of mounting a semiconductor chip on a first substrate whereupon a first wiring is formed, and a second step of bonding a second substrate whereupon a second wiring is formed with the first substrate. In the second step, the semiconductor chip is sealed between the first substrate and the second substrate, the first wiring is electrically connected with the second wiring, and a multilayer wiring connected with the semiconductor chip is formed.

MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES

Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die.

METHOD FOR MANUFACTURING ELECTRONIC DEVICES AND ELECTRONIC DEVICES THEREOF

In some embodiments, a method of manufacturing electronic devices including providing a carrier substrate having a first side, a second side, and a first adhesive at the first side; providing a first flexible substrate; and bonding the first flexible substrate to the first side of the carrier substrate. The first adhesive bonds the first flexible substrate to the first side of the carrier substrate. The carrier substrate comprises a mechanism configured to compensate for a deformation of the carrier substrate. Other embodiments are disclosed.

IMPROVED BONDING ARRANGEMENT AND METHOD FOR LTCC CIRCUITRY

An LTCC (low temperature cofired ceramic) structure which has conductors to which leads are to be bonded for connection to external circuitry. The conductors include additives to promote adhesion to the ceramic layer. The presence of these additives degrade bonding performance. For better bondability of the leads, a pure conductor metal layer, devoid of the additives is placed on the conductors in areas where leads are to be bonded. This pure conductor metal layer may be cofired with the stack of ceramic layers or may be post fired after stack firing.

CAPACITOR AND METHOD FOR PRODUCING SAME

Disclosed is a capacitor producing method wherein a dielectric film composed of a barium titanate-based ceramic material is formed on a metal foil by an improved aerosol deposition method; a first via conductor and a second via conductor, which are connected to the metal foil, are embedded in the dielectric film; a first electrode pattern connected to the first via conductor is formed on the dielectric film; and the metal foil is patterned to form a second electrode pattern connected to the second via conductor.

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTERPOSER AND METHOD OF MANUFACTURE THEREOF

A method of manufacture of an integrated circuit packaging system includes: mounting a device over an integrated circuit having a through via; attaching an interposer, having an opening, and the integrated circuit with the device within the opening; and forming an encapsulation at least partially covering the integrated circuit and the interposer facing the integrated circuit.

Semiconductor device, chip module, and semiconductor module

Provided is a semiconductor device having a surface layer power supply path in a surface layer wiring layer, on which a chip module is mounted, of a main substrate that has a plurality of wiring layers and through holes, the surface layer power supply path supplying power to a semiconductor chip via an inner peripheral-side power supply terminal group and an outer peripheral-side power supply terminal group. The surface layer power supply path overlaps the inner peripheral-side power supply terminal group and the outer peripheral-side power supply terminal group as seen in the orthogonal direction, and is formed continuously so as to extend in a direction from a position at which the surface layer power supply path is connected to the inner peripheral-side power supply terminal group toward the outer peripheral side of the main substrate.

MOUNTING BOARD, METHOD FOR MANUFACTURING MOUNTING BOARD, AND SEMICONDUCTOR MODULE

To reduce connection defects between a circuit substrate provided on a core substrate and a circuit to be mounted thereon, thereby improving reliability as a multilayered device mounting substrate. The device mounting substrate includes: a first circuit substrate composed of a substrate, an insulating layer formed on this substrate, and a first conductive layer (including conductive parts) formed on this insulating layer; and a second circuit substrate mounted on the first circuit substrate, being composed of a base, a second conductive layer (including conductive parts) formed on the bottom of the base, and a third conductive layer (including conductive parts) formed on the top of the base. Here, the first and second circuit substrates are bonded by pressure so that the first and second conductive parts are laminated and embedded together into the insulating layer. The first and second conductive parts form connecting areas in the insulating layer, thereby connecting the first and second ...

Tape stiffener and semiconductor device component assemblies including same

Stiffeners for tapes, films, or other connective structures that are configured to be secured to a semiconductor device component, such as a semiconductor die or substrate, by tape-automated bonding processes. The stiffeners are fabricated by stereolithographic processes and may include one layer or two or more superimposed, contiguous, mutually adhered layers. The stiffeners are configured to prevent torsional flexion or bending of the connective structure to which they are to be secured. The stiffeners may include apertures through which intermediate conductive elements or other structures secured to the connective structure may be exposed or protrude. Stiffeners that reinforce sprocket or indexing holes in a connective structure are also disclosed. The stereolithographic method of fabricating the stiffeners may include use of a machine vision system with at least one camera operably associated with a computer that controls the stereolithographic application of material so that the system ...

Ceramic multilayer circuit board and semiconductor module

A ceramic multilayer circuit board comprising ceramic layers and wiring conductor layers laminated alternately, in which the ceramic layer has a thermal expansion coefficient lower than that of the wiring conductor and not lower than one half of that of the conductor layer and is formed from a glass which softens at a temperature not higher than the melting point of the wiring conductor layer; a semiconductor module having a high reliability in its solder joint part comprising said ceramic multilayer circuit board mounted with a ceramic carrier substrate being mounted with a semiconductor device, said board being able to use a silver or copper conductor having a good electro-conductivity; and an amorphous glass powder for said ceramic multilayer circuit board.

Method of planarizing a curved substrate and resulting structure

According to the present invention a technique for providing a planarized substrate with dendritic connections of solder balls, especially a multi-layer ceramic substrate is provided. In the case where the substrate has a raised central portion on the top surface on which are disposed top surface metallurgy pads, a layer of conformable photoimagable material is placed over the top surface. The photoimagable material is exposed and developed in a pattern corresponding to the pattern of the top surface metallurgy pads to form vias in the photoimagable material. Copper is plated in the vias in contact with the top surface metallurgy pads. The exposed surface of the photoimagable surface is then planarized, preferably by mechanical polishing to form a flat planar surface, with the ends of the vias exposed. Dendritic connector pads are then grown on the exposed ends of the vias to which solder ball connections of an I/C chip are releasably connected.

Semiconductor package and manufacture thereof

The present invention relates to a semiconductor package which is loaded with a plurality of high-performance integrated circuits for high-performance systems such as super computers and large-sized computers. According to the invention, the packaging density of the semiconductor is doubled by stacking upper and lower members and forming substrates loaded with a plurality of chips in a multistep structure so that the size of computers can be minimized and heat emission efficiency can be improved by forming heat sinks in a fin-pin shape.

Semiconductor device and package wiring substrate with matrix pattern external terminals for transmitting a differential signal

A semiconductor device or semiconductor device package for transmitting a plurality of differential signals, the reliability of which hardly deteriorates. The semiconductor device is an area array semiconductor device in which a plurality of lands (external terminals) including a plurality of lands for transmitting a plurality of differential signals are arrayed in a matrix pattern in the back surface of a wiring substrate. Some of the lands are located in the outermost periphery of the matrix pattern. Some others of the lands are located inward of the outermost periphery of the matrix pattern and in rows next to the outermost periphery. The spacing between lands in a second region between the lands located in the rows next to the outermost periphery and the side surface of the wiring substrate is larger than in a first region in the outermost periphery.

PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF

A package structure including a redistribution circuit structure, a wiring substrate, an insulating encapsulation, a buffer layer, a semiconductor device and a stiffener ring is provided. The redistribution circuit structure includes a first surface and a second surface opposite to the first surface. The wiring substrate is disposed on the first surface of the redistribution circuit structure. The insulating encapsulation is disposed on the first surface of the redistribution circuit structure and laterally encapsulating the wiring substrate. The buffer layer is disposed over the second surface of the redistribution circuit structure. The semiconductor device is disposed on the buffer layer, and the semiconductor device is electrically connected to the wiring substrate through the redistribution circuit structure. The stiffener ring is adhered with the buffer layer by an adhesive. 1. A package structure , comprising:a redistribution circuit structure comprising a first surface and a second surface opposite to the first surface;a wiring substrate disposed on the first surface of the redistribution circuit structure;an insulating encapsulation disposed on the first surface of the redistribution circuit structure and laterally encapsulating the wiring substrate;a buffer layer disposed over the second surface of the redistribution circuit structure;a semiconductor device disposed on the buffer layer, and the semiconductor device being electrically connected to the wiring substrate through the redistribution circuit structure; anda stiffener ring adhered with the buffer layer by an adhesive.2. The package structure as claimed in further comprising a barrier layer disposed on the second surface of the redistribution circuit structure claim 1 , wherein the barrier layer is disposed between the buffer layer and the redistribution circuit structure.3. The package structure as claimed in further comprising:first conductive terminals disposed between the redistribution circuit ...

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package includes: a first package including a first semiconductor chip; a second package under the first package, the second package including a second semiconductor chip; and a first interposer package between the first package and the second package, the first interposer package including: a power management integrated circuit (PMIC) configured to supply power to the first package and the second package; a core member having a through-hole in which the PMIC is disposed; a first redistribution layer on the core member, and electrically connected to the first package; a second redistribution layer under the core member, and electrically connected to the second package; core vias penetrating the core member, and electrically connecting the first redistribution layer with the second redistribution layer; and a first signal path electrically connecting the first package with the second package.

Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

CIRCUIT BOARD FOR PERIPHERAL CIRCUITS OF HIGH-CAPACITY MODULES, AND A HIGH-CAPACITY MODULE INCLUDING A PERIPHERAL CIRCUIT USING THE CIRCUIT BOARD

... [Summary] [Subject] The present invention has an objective to provide a circuit board for a peripheral circuit which can transmit outside heat which generates from a high exothermic element, such as a power semiconductor element, while attaining reduction in size and weight, reduction in serge, and reduction in a loss, in high-capacity modules including power modules, such as an inverter. [Solution Means] In a high-capacity module, by laminating a peripheral circuit using a ceramic circuit board with electrode(s) constituted by thick conductor and embedded therein on a highly exothermic element, overheating of the module is prevented by effective heat dissipation via the circuit board while attaining reduction in size and weight, reduction in serge, and reduction in a loss in the module.

Radio frequency module and communication device

A radio frequency module includes: a multilayer substrate that includes a plurality of insulator layers; an amplifying circuit that is provided on the multilayer substrate and amplifies a radio frequency signal; a power supply circuit that is provided on the multilayer substrate and supplies power to the amplifying circuit; a ground conductor that is a first conductor pattern having a ground potential and used in the amplifying circuit; and a ground conductor that is a second conductor pattern having a ground potential and used in the power supply circuit. The ground conductors are physically separated from each other and provided in internal layers of the multilayer substrate.

Semiconductor package devices including interposer openings for heat transfer member

A semiconductor package device includes a lower package, an interposer disposed on the lower package and including a ground layer and at least one opening, and an upper package on the interposer. The lower package includes a first package substrate, a first semiconductor chip on the first package substrate, and a first molding compound layer on the first package substrate. The upper package includes a second package substrate and at least one upper semiconductor chip on the second package substrate. A heat transfer member includes a first portion disposed between the interposer and the upper package, a second portion disposed in the at least one opening of the interposer, and a third portion disposed between the interposer and the lower package.

Semiconductor package and fabrication method thereof

A semiconductor package is provided, which includes: a first semiconductor device having a first top surface and a first bottom surface opposite to the first top surface; a plurality of conductive balls formed on the first top surface of the first semiconductor device; a second semiconductor device having a second top surface and a second bottom surface opposite to the second top surface; and a plurality of conductive posts formed on the second bottom surface of the second semiconductor device and correspondingly bonded to the conductive balls for electrically connecting the first semiconductor device and the second semiconductor device, wherein the conductive posts have a height less than 300 um. Therefore, the present invention can easily control the height of the semiconductor package and is applicable to semiconductor packages having fine-pitch conductive balls.

CONNECTOR INTERFACE FOR PROCESSOR PACKAGING

An apparatus is provided which comprises: a processor substrate extended away from a processor die, wherein the processor substrate has at least one signal interface which is connectable to a connector; and an interposer coupled to the processor substrate and a motherboard. Described is an apparatus which comprises: a processor substrate extended away from a processor die, wherein the processor substrate has at least one signal interface; and a motherboard coupled to the processor substrate, wherein the motherboard is configured to have a hole which is large enough to place a connector at least partially in it to couple with the at least one signal interface.

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

A semiconductor device includes a rectangular lower semiconductor element; a plurality of external electrodes located in a pattern on the lower semiconductor element along sides thereof; a plurality of internal electrodes electrically connected to the plurality of external electrodes via a plurality of line patterns respectively and located on the lower semiconductor element in a pattern; dams provided in such a pattern that each of the dams encloses one or at least two external electrodes among the plurality of external electrodes; an upper semiconductor element mounted on the lower semiconductor element such that a plurality of terminals on the upper semiconductor element are electrically connected to the plurality of internal electrodes respectively; and a resin potted to flow to a space between the lower semiconductor element and the upper semiconductor element.

Circuit assemblies with multiple interposer substrates, and methods of fabrication

A combined interposer (120) includes multiple constituent interposers (120.i), each with its own substrate (120.iS) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (120R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (120R.B). The constituent interposer substrates (120.iS) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided.

Vertical modular stiffeners for stacked multi-device packages

Disclosed embodiments include a stacked multi-chip package that includes two semiconductor package substrates that are spaced apart by a vertical-device stiffener. The vertical-device stiffener provides both connection space for at least one vertical semiconductive device and at least one vertical radio-frequency device, as well as stiffness and form-factor reduction.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a first substrate; a second substrate, disposed over the first substrate; a die, disposed over the second substrate; a via, extending through the second substrate and electrically connecting to the die; a redistribution layer (RDL) disposed between the first substrate and the second substrate, including a dielectric layer, a first conductive structure electrically connecting to the via, and a second conductive structure surrounding the first conductive structure, wherein the second conductive structure extends along an edge of the dielectric layer and penetrates through the dielectric layer; and a first underfill material, disposed between the first substrate and the RDL, wherein one end of the second conductive structure exposed through the dielectric layer is entirely in contact with the first underfill material.

Chip-last embedded interconnect structures

The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.

Making electrical components in handle wafers of integrated circuit packages

A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.

INFORMATION HANDLING SYSTEM INTERPOSER ENABLING SPECIALTY PROCESSOR INTEGRATED CIRCUIT IN STANDARD SOCKETS

An information handling system (IHS) has a circuit board assembly with a dual-sided interposer substrate that is inserted between a baseboard and a processor integrated circuit having a second pattern of electrical contacts. The dual interposer substrate formed of a stack of printed circuit boards (PCBs) provides communication channels between a first coupling pad on the baseboard that has a first pattern of electrical contacts and a second coupling pad on top of the dual interposer substrate that provides the second pattern of electrical contacts. The second pattern receives another type of processor integrated circuit than a type supported by the first pattern. Stacked vias formed through the stack of PCBs electrically connect respective electrical contacts of the first and second coupling pads to form a corresponding communication channel. One or more grounded vias mitigate signal integrity (SI) anomalies on the communication channels.

INTEGRATED FAN-OUT PACKAGES AND METHODS OF FORMING THE SAME

Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.

Package structure and manufacturing method thereof

A package structure including a first chip, a second chip, a dielectric body, a third chip, an encapsulant, a first conductive terminal, and a circuit layer is provided. The dielectric body covers the first chip and the second chip. The third chip is disposed on the dielectric body such that a third active surface thereof faces a first active surface of the first chip or a second active surface of the second chip. The encapsulant covers the third chip. The first conductive terminal is disposed on the dielectric body and is opposite to the third chip. The circuit layer includes a first circuit portion and a second circuit portion. The first circuit portion penetrates the dielectric body. The first chip, the second chip, or the third chip is electrically connected to the first conductive terminal through the first circuit portion. The second circuit portion is embedded in the dielectric body.

MICROELECTRONIC ASSEMBLIES HAVING AN INTEGRATED CAPACITOR

Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

Modular printed circuit board electrical integrity and uses

Modular printed circuit board (PCB) structures and methods of producing them are described herein. In some embodiments, a PCB structure may include a first PCB module including first structures on one or more layers of the first PCB module. The PCB structure may further include a second PCB module including second structures on one or more layers of the second PCB module. The PCB structure may additionally include a middle layer between the first PCB module and the second PCB module. The middle layer electrically coupling, without connectors, one or more of the first structures aligned with one or more of the second structures.

High density interconnection using fanout interposer chiplet

Multiple component package structures are described in which an interposer chiplet is integrated to provide fine routing between components. In an embodiment, the interposer chiplet and a plurality of conductive vias are encapsulated in an encapsulation layer. A first plurality of terminals of the first and second components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals of first and second components may be in electrical connection with the interposer chiplet.

SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

A semiconductor package may include a first substrate, a second substrate at least partially surrounding the first substrate, the first substrate disposed in an opening penetrating the second substrate, and a semiconductor chip on the first substrate. The first substrate may be spaced apart from the second substrate in the opening, and a thickness of the first substrate may be less than a thickness of the second substrate.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a redistribution structure, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first under-bump metallization (UBM) pattern covered by a first dielectric layer, and the first UBM pattern includes a surface substantially leveled with a surface of the first dielectric layer. The circuit substrate is electrically coupled to the redistribution structure through a conductive joint disposed on the surface of the first UBM pattern. The insulating encapsulation is disposed on the redistribution structure to cover the circuit substrate.

Method for fabricating glass substrate package

A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors.

Porous alumina templates for electronic packages

Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.

Semiconductor module, bonding jig, and manufacturing method of semiconductor module

A semiconductor module includes an image pickup device on which a bump is disposed, and a flexible wiring board having a flexible resin as a base and including a wire having a bonding electrode at a distal end portion solder-bonded to the bump, in which the bonding electrode is pressed against the bump by bending/deformation of the wiring board caused by application of heat to a solder bonding temperature.

Power module having at least one power semiconductor

A power module includes a substrate having a first layer and a second layer which are connected to one another and arranged above one another. The first layer includes a first dielectric material having a metallization arranged on a side facing the second layer and the second layer includes a second dielectric material having a metallization arranged on a side facing away from the metallization of the first dielectric material. A power semiconductor having a first contact area and a second contact area opposite the first contact area is connected to the metallization of the first dielectric material via the first contact area and arranged in a first recess of the second layer. A metallic first encapsulation encapsulates the power semiconductor in a fluid-tight manner, with the second contact area of the power semiconductor being electrically conductively connected to the metallization of the second dielectric material via the first encapsulation.

Semiconducting device that includes wirebonds

Some embodiments relate to a semiconducting device that includes a substrate, a die and an interconnect device. The die and interconnect device are attached to an upper surface of the substrate. The semiconducting device further includes a first wire that is bonded to the substrate and to the interconnect device and a second wire that is bonded to the interconnect device and to the die. Other example embodiments include a stack of dice that has a bottom die attached to the upper surface of the substrate and a top die stacked onto the other dice in the stack of dice. The interconnect device is attached to an upper surface of any die in the stack of dice such that a first wire is bonded to the substrate and to the interconnect device and a second wire is bonded to the interconnect device and to the top die.

Semiconductor structure and manufacturing method thereof

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a first under-bump metallization (UBM) pattern, a first conductive via, and a first dielectric layer laterally covering the first UBM pattern and the first conductive via. Entireties of a top surface and a bottom surface of the first UBM pattern are substantially planar. The first conductive via landing on the top surface of the first UBM pattern includes a vertical sidewall and a top surface connected to the vertical sidewall, and a planarized mark is on the top surface of the first conductive via. A bottom surface of the first dielectric layer is substantially flush with the bottom surface of the first UBM, and a top surface of the first dielectric layer is substantially flush with the top surface of the first conductive via.

Power Module with Press-Fit Contacts

A method of forming a semiconductor device includes providing a power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, mounting one or more semiconductor dies on a portion of the structured metallization layer, forming an encapsulant body of electrically insulating material that covers the power electronics carrier and encapsulates the one or more semiconductor dies, securing a press-fit connector to the power electronics carrier with a base portion of the press-fit connector being disposed within an opening in the encapsulant body and with an interfacing end of the press-fit connector being electrically accessible from outside the encapsulant body.

INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING A CAPACITOR-EMBEDDED, REDISTRIBUTION LAYER (RDL) SUBSTRATE FOR INTERFACING AN IC CHIP(S) TO A PACKAGE SUBSTRATE, AND RELATED METHODS

Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate and related fabrication methods. The embedded capacitor can be coupled to a power distribution network (PDN) to provide decoupling capacitance to reduce current-resistance (IR) drop. The RDL substrate is disposed between the IC chip(s) and the package substrate to minimize distance between the embedded capacitor(s) and the IC chip(s) to reduce the parasitic inductance in the PDN, thus reducing PDN noise. With the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections between the package substrate and the IC chip(s). In this regard, the RDL substrate includes an outer RDL layer adjacent to the IC chip(s) to support small pitch metal interconnects as well as provide fan-out capability. This provides enhanced connectivity compatibility with higher-density die interconnect IC chips while also supporting a closer located ...

Semiconductor chip device with polymeric filler trench

A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

Methods of fabricating package stack structure and method of mounting package stack structure on system board

A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

Integrated circuit packaging system with interposer interconnections and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; forming an encapsulation covering the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and leaves a surface of the routing structure exposed from the encapsulation, and a portion of the vertical interconnect exposed from the encapsulation above the surface of the routing structure; mounting a first-external-package-component to the routing structure; and forming a first-external-package-encapsulation covering the first-external-package-component.

Semiconductor assembly and semiconductor package including a solder channel

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Wiring Substrate, Imaging Device and Imaging Device Module

A imaging device includes a first insulating substrate having a through hole, a connection electrode and a first wiring conductor, a second insulating substrate having outside terminals and a second wiring conductor, and an imaging element including a light-receiving portion arranged at a center portion on an upper surface thereof and a connection terminal arranged at an outer peripheral portion thereof, at least one of the lower surface of the first insulating substrate and the upper surface of the second insulating substrate including a recess portion, the through hole being located on an inner side thereof, the imaging element being arranged below the first insulating substrate such that the light-receiving portion is located within the through hole, the connection terminal being electrically connected to the connection electrode, the imaging element being accommodated inside the recess portion, outer peripheral portions of the first insulating substrate and the second insulating substrate being electrically connected to each other.

Semiconductor package module

There is provided a semiconductor package module capable of minimizing a thickness of the module in spite of including an electronic element having a large size. The semiconductor package module includes: a semiconductor package having a shield formed on an outer surface and a side thereof and at least one receiving part provided in a lower surface thereof, the receiving part having a groove shape; and a main substrate having at least one large element and the semiconductor package mounted on one surface thereof, wherein the large element is received in the receiving part of the semiconductor package and is mounted on the main substrate.

Thermal Power Plane for Integrated Circuits

A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Semiconductor package and semiconductor system including the same

Provided are a semiconductor package and a semiconductor system including the semiconductor package. The semiconductor package includes a semiconductor device and an interconnect structure electrically connected to the semiconductor device and delivering a signal from the semiconductor device, wherein the interconnect structure includes an anodized insulation region and an interconnect adjacent to and defined by the anodized insulation region.

Microelectronic package and method of manufacturing same

A microelectronic package includes a substrate ( 110, 210 ), an interposer ( 120, 220 ) having a first surface ( 121 ) and an opposing second surface ( 122 ), a microelectronic die ( 130, 230 ) attached to the substrate, and a mold compound ( 140 ) over the substrate. The interposer is electrically connected to the substrate using a wirebond ( 150 ). The first surface of the interposer is physically connected to the substrate with an adhesive ( 160 ), and the second surface has an electrically conductive contact ( 126 ) formed therein. The mold compound completely encapsulates the wirebond and partially encapsulates the interposer such that the electrically conductive contact in the second surface of the interposer remains uncovered by the mold compound.

Chip-last embedded interconnect structures and methods of making the same

The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.

Multilayer resin sheet and method for producing the same, method for producing cured multilayer resin sheet, and highly thermally conductive resin sheet laminate and method for producing the same

A multilayer resin sheet is constituted by including a resin layer containing an epoxy resin having a mesogenic skeleton, a curing agent and an inorganic filler, and an insulating adhesive layer formed on at least either of the surfaces of the resin layer. A cured multilayer resin sheet originated from the multilayer resin sheet has high thermal conductivity, good insulation and adhesive strength, and, further, superior thermal shock resistance, and is suitable as an electric insulating material to be used for an electric or electronic device.

Semiconductor device

A semiconductor device includes a first semiconductor chip provided with a first semiconductor element including a plurality of element electrodes; and a first substrate having an element mounting surface on which the first semiconductor chip is mounted. The first substrate includes a plurality of first electrodes, each formed on the element mounting surface; a plurality of first interconnects connected to the first electrodes; a plurality of second electrodes formed on a surface opposite to the element mounting surface; a plurality of second interconnects connected to the second electrodes; a plurality of through-hole interconnects penetrating the first substrate and connecting the first interconnects to the second interconnects; and a third semiconductor element. The first side of the first substrate is shorter than the first side of the first semiconductor chip.

Electronic module

An electronic module. One embodiment includes a carrier. A first transistor is attached to the carrier. A second transistor is attached to the carrier. A first connection element includes a first planar region. The first connection element electrically connects the first transistor to the carrier. A second connection element includes a second planar region. The second connection element electrically connects the second transistor to the carrier. In one embodiment, a distance between the first planar region and the second planar region is smaller than 100 μm.

Module substrate, module-substrate manufacturing method, and terminal connection substrate

In a module substrate, a plurality of terminal connection substrates each including an insulator and a plurality of columnar terminal electrodes arranged on a single lateral surface or both lateral surfaces of the insulator is mounted on a single side of a composite substrate such that at least one of the terminal connection substrates extends over a border between a plurality of neighboring module substrates. The composite substrate, in which the plurality of terminal connection substrates is mounted on the single side and a plurality of electronic components is mounted on at least the single side, is divided at a location where the module substrates are to be cut from the composite substrate.

Fabrication method of packaging substrate having through-holed interposer embedded therein

A packaging substrate having a through-holed interposer embedded therein and a fabrication method of the packaging substrate are provided, where the packaging substrate includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer.

Method Of Manufacturing Package-On-Package (Pop)

A method of manufacturing package-on-packages (POPs) includes: forming a plurality of internal connection members that are separated from each other on a first circuit substrate; forming a first package by attaching a plurality of first chips between the internal connection members on the first circuit substrate; forming a second package by attaching a plurality of second chips that are separated from each other on a second circuit substrate; electrically connecting the first circuit substrate and the second circuit substrate by stacking the internal connection members onto the second circuit substrate; forming an encapsulant to encapsulate the first package and the second package; and forming the POPs in which the first chips and the second chips are respectively formed by cutting the first circuit substrate, the second circuit substrate, and the encapsulant.

Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Semiconductor Package with a Bridge Interposer

There are disclosed herein various implementations of semiconductor packages including a bridge interposer. One exemplary implementation includes a first active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The semiconductor package also includes a second active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The second portion of the first active die and the second portion of the second active die include solder balls mounted on a package substrate, and are configured to communicate electrical signals to the package substrate utilizing the solder balls and without utilizing through-semiconductor vias (TSVs).

Semiconductor Interposer Having a Cavity for Intra-Interposer Die

A semiconductor package may include a substrate, and a semiconductor interposer having a cavity and a plurality of through semiconductor vias. The semiconductor interposer is situated over the substrate. An intra-interposer die is disposed within the cavity of the semiconductor interposer. A thermally conductive adhesive is disposed within the cavity and contacts the intra-interposer die. Additionally, a top die is situated over the semiconductor interposer. In one implementation, the semiconductor interposer is a silicon interposer. In another implementation, the semiconductor interposer is flip-chip mounted to the substrate such that the intra-interposer die disposed within the cavity faces the substrate. In yet another implementation, the cavity in the semiconductor interposer may extend from a top surface of the semiconductor interposer to a bottom surface of the semiconductor interposer and a thermal interface material may be disposed between the intra-interposer die and the substrate.

Package-on-package type semiconductor packages and methods for fabricating the same

A method of forming a semiconductor package may include providing a first package including a first semiconductor chip mounted on a first package substrate having a via-hole and molded by a first mold layer, providing a second package including a second semiconductor chip mounted on a second package substrate having a connection pad and molded by a second mold layer, stacking the first package on the second package to vertically align the via-hole with the connection pad, forming a through-hole penetrating the first and second packages and exposing the connection pad, and forming an electrical connection part in the through-hole. The electrical connection part may electrically connect the first package and the second package to each other.

Stacked module

A stacked module includes a first multilayer substrate including an opening having a stepwise wall face, and a first transmission line including a first grounding conductor layer, a second multilayer substrate supported on a stepped portion of the stepwise wall face and including a second transmission line including a second grounding conductor layer, a first chip mounted on a bottom of the opening and coupled to a third transmission line provided on the first multilayer substrate, and a second chip mounted on the front face of the second multilayer substrate and coupled to the second transmission line. A face to which the second grounding conductor layer or a fourth grounding conductor layer coupled thereto is exposed is joined to the stepped portion to which the first grounding conductor layer or a third grounding conductor layer coupled thereto is exposed, and the first and second grounding conductor layers are coupled.

Reliable Area Joints for Power Semiconductors

A power semiconductor module includes an electrically insulating substrate, copper metallization disposed on a first side of the substrate and patterned into a die attach region and a plurality of contact regions, and a semiconductor die attached to the die attach region. The die includes an active device region and one or more copper die metallization layers disposed above the active device region. The active device region is disposed closer to the copper metallization than the one or more copper die metallization layers. The copper die metallization layer spaced furthest from the active device region has a contact area extending over a majority of a side of the die facing away from the substrate. The module further includes a copper interconnect metallization connected to the contact area of the die via an aluminum-free area joint and to a first one of the contact regions of the copper metallization.

Direct bonded copper substrate and power semiconductor module

Disclosed are a DBC substrate and a power semiconductor module having improved thermal reliability by directly forming a via in a substrate of a semiconductor device used mainly as a power device such as a silicon device, a silicon carbide (SiC) device, and a gallium nitride (GaN) device. The power semiconductor module includes: a DBC substrate including a ceramic base material defining a via, a lower copper layer connected to a bottom surface of the ceramic base material, and an upper copper layer connected to a top surface of the ceramic base material; a power semiconductor device stacked on the upper copper layer of the DBC substrate; and a heat dissipating device connected to the lower copper layer of the DBC substrate, and dissipating heat, generated by the operation of the power semiconductor device, through the via.

Interface Substrate with Interposer

An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided.

Method of manufacturing semiconductor device

In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.

WIRING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers, a plurality of circuit layers in contact with the dielectric layers, and a plurality of dam portions in contact with the dielectric layers. The dam portions are stacked on and contact one another. The conductive through via extends through the dam portions. 1. A wiring structure , comprising:a conductive structure including a plurality of dielectric layers, a plurality of circuit layers in contact with the dielectric layers, and a plurality of dam portions in contact with the dielectric layers, wherein the dam portions are stacked on and contact one another; andat least one conductive through via extending through the dam portions;wherein each of the dam portions includes a main portion and an extending portion, the main portion extends through a dielectric layers, the extending portion is disposed on a surface of the dielectric layer, and a width of the main portion gradually increases toward the extending portion.2. The wiring structure of claim 1 , wherein the dam portions and the circuit layers are formed concurrently.3. The wiring structure of claim 1 , wherein each of the dam portions defines a through hole claim 1 , and the at least one conductive through via is disposed in the through holes of the dam portions.4. The wiring structure of claim 1 , wherein each of the dam portions is in a substantially closed ring shape.5. (canceled)6. The wiring structure of claim 1 , wherein each of the dam portions defines a through hole claim 1 , and the extending portion includes an inner extending portion extending inwardly toward the through hole claim 1 , and an outer extending portion extending opposite to the inner extending portion.7. The wiring structure of claim 1 , wherein each of the dam portions includes a seed layer and a conductive material disposed on the seed layer claim 1 , and the seed layer is ...

METHOD FOR FABRICATING ELECTRONIC PACKAGE

An electronic package and a method for fabricating the same are provided. Two packaging modules are stacked on each other. An area that an electronic package occupies a mother board is reduced during a subsequent process of fabricating an electronic product. Therefore, the electronic product has a reduced size. 18-. (canceled)9. A method for fabricating an electronic package , comprising:providing a first carrying structure having a first surface and a second surface opposing the first surface, with at least one first electronic component disposed on the first surface and electrically connected to the first carrying structure, and a plurality of conductors disposed on the second surface and electrically connected to the first carrying structure;stacking on the first surface of the first carrying structure via at least one conductive element a second carrying structure provided with a functional electronic component; andforming a packaging layer between the first carrying structure and the second carrying structure, allowing the packaging layer to pack the first electronic component, the functional electronic component and the conductive element.10. The method of claim 9 , wherein the functional electronic component is electrically connected to the second carrying structure and electrically connects the conductive element to the first carrying structure and the second carrying structure.11. The method of claim 10 , wherein the conductive element is disposed on the second carrying structure claim 10 , and then the conductive element is bonded onto the first carrying structure.12. The method of claim 10 , wherein the conductive element is disposed on the first surface of the first carrying structure claim 10 , and then the second carrying structure is bonded onto the conductive element.13. The method of claim 10 , further comprising disposing at least one second electronic component on the second surface of the first carrying structure claim 10 , and electrically ...

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

In one example, a semiconductor device comprises a first base substrate comprising a first base conductive structure, a first encapsulant contacting a lateral side of the first base substrate, a redistribution structure (RDS) substrate over the base substrate and comprising an RDS conductive structure coupled with the first base conductive structure, a first electronic component over the RDS substrate and over a first component terminal coupled with the RDS conductive structure, and a second encapsulant over the RDS substrate and contacting a lateral side of the first electronic component. Other examples and related methods are also disclosed herein. 1. A semiconductor device , comprising:a first base substrate comprising a first base conductive structure;a first encapsulant contacting a lateral side of the first base substrate;a redistribution structure (RDS) substrate over the base substrate and comprising an RDS conductive structure coupled with the first base conductive structure;a first electronic component over the RDS substrate and over a first component terminal coupled with the RDS conductive structure; anda second encapsulant over the RDS substrate and contacting a lateral side of the first electronic component.2. The semiconductor device of claim 1 , wherein:the first encapsulant further contacts a top side of the first base substrate.3. The semiconductor device of claim 1 , wherein the first base substrate comprises:a base dielectric structure; andan embedded component in the base dielectric structure.4. The semiconductor device of claim 1 , wherein the first base substrate comprises a coreless substrate.5. The semiconductor device of claim 1 , further comprising:a second electronic component over the RDS substrate and over a second component terminal coupled with the RDS conductive structure.6. The semiconductor device of claim 5 , further comprising:a second base substrate laterally adjacent to the first base substrate and comprising a second base ...

Semiconductor device

A semiconductor device includes a supporting plate including a first surface, a second surface opposite to the first surface, and a through hole extending from the first surface to the second surface; and a semiconductor unit fixed to the first surface. The semiconductor unit includes an insulating plate, a circuit plate fixed to a front surface of the insulating plate, a semiconductor chip fixed to the circuit plate, and a protruding metal block fixed to a rear surface of the insulating plate and penetrating through the through hole to extend to the second surface.

CIRCUIT BOARD AND ELECTRONIC DEVICE

A circuit board includes a metal circuit plate, a metallic heat diffusing plate disposed below the metal circuit plate and having an upper surface and a lower surface, a metallic heat dissipating plate below the heat diffusing plate, an insulating substrate disposed between the metal circuit plate and the heat diffusing plate, and an insulating substrate disposed between the heat diffusing plate and the heat dissipating plate. A grain diameter of metal grains contained in the heat diffusing plate decreases from each of the upper surface and the lower surface of the heat diffusing plate toward a center portion of the heat diffusing plate in a thickness direction. 1. A circuit board comprising:a metal circuit plate;a metallic heat diffusing plate below the metal circuit plate;a metallic heat dissipating plate below the heat diffusing plate;a first insulating substrate disposed between the metal circuit plate and the heat diffusing plate and comprising an upper surface bonded to a lower surface of the metal circuit plate and a lower surface bonded to an upper surface of the heat diffusing plate; anda second insulating substrate disposed between the heat diffusing plate and the heat dissipating plate and comprising an upper surface bonded to a lower surface of the heat diffusing plate and a lower surface bonded to an upper surface of the heat dissipating plate,wherein a grain diameter of metal grains contained in the heat diffusing plate decreases from each of the upper surface and the lower surface of the heat diffusing plate toward a center portion of the heat diffusing plate in a thickness direction.2. A circuit board comprising:a metal circuit plate;a plurality of metallic heat diffusing plates disposed below the metal circuit plate and arranged in an up-down direction;a metallic heat dissipating plate below the plurality of heat diffusing plates;a first insulating substrate disposed between the metal circuit plate and an uppermost heat diffusing plate of the ...

Semiconductor Package and Method

In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over a Temporary Substrate

A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a first interconnect structure over the substrate;disposing a first semiconductor die over the first interconnect structure;disposing the substrate over a carrier with the first semiconductor die oriented away from the carrier;depositing an encapsulant over the carrier, substrate, and first semiconductor die;forming a second interconnect structure over the encapsulant and semiconductor die; andremoving the substrate to expose the first interconnect structure after forming the second interconnect structure.2. The method of claim 1 , further including forming a conductive column over the first interconnect structure.3. The method of claim 2 , wherein the conductive column extends from the first interconnect structure to the second interconnect structure ...

MICROELECTRONIC DEVICE INTERCONNECT STRUCTURE

A microelectronic device is formed including two or more structures physically and electrically engaged with one another through coupling of conductive features on the two structures. The conductive features may be configured to be tolerant of bump thickness variation in either of the structures. Such bump thickness variation tolerance can result from a contact structure on a first structure including a protrusion configured to extend in the direction of the second structure and to engage a deformable material on that second structure. 1. A microelectronic device , comprising:a first interconnect structure comprising first multiple contact structures on a first surface; a respective first portion with a first lateral dimension proximate a dielectric structure of the second interconnect structure, and', 'a protrusion extending from the respective first portion in a direction toward the first interconnect structure, the protrusion having a second portion with a second lateral dimension less than the first lateral dimension of the first portion of the contact structure; and, 'a second interconnect structure comprising second multiple contact structures on a second surface in positions to be coupled to respective first multiple contact structures, the second multiple contact structures each having,'}a deformable material establishing electrical and mechanical contact between the first multiple contact structures of the first interconnect structure and respective second multiple contact structures of the second interconnect structure.2. The microelectronic device of claim 1 , wherein a first plurality of the second multiple contact structures each include a bond pad having a planar contact surface forming the first portion claim 1 , and wherein the protrusion extends relative to the planar contact surface.3. The microelectronic device of claim 1 , wherein the first multiple contact structures comprise:a first plurality of contact structures, each of a first lateral ...

VEHICLE-USE ALTERNATING CURRENT GENERATOR REGULATOR

A vehicle-use alternating current generator regulator includes an IC regulator wherein an IC chip is sealed with resin and a lead terminal for external connection protrudes from a sealing resin, and a regulator holder having a lead opposing portion that encloses an IC regulator mounting portion in which the IC regulator is mounted. A configuration is such that the lead terminal has a lead protruding portion protruding from a contact with the regulator holder, and the IC regulator is positioned by the lead protruding portion being fitted into the lead opposing portion of the regulator holder. 1. A vehicle-use alternating current generator regulator , comprising:an IC regulator wherein an IC chip that configures a voltage control circuit of the vehicle-use alternating current generator is sealed with resin, and a lead terminal for external connection protrudes from a sealing resin; anda regulator holder having an IC regulator mounting portion in which the IC regulator is mounted and a lead opposing portion, provided on a periphery of the IC regulator mounting portion, opposing the lead terminal, whereinthe lead terminal has a lead protruding portion protruding from a contact with the regulator holder, and the IC regulator is positioned by the lead protruding portion being fitted into the lead opposing portion of the regulator holder.2. The vehicle-use alternating current generator regulator according to claim 1 , whereina plurality of the lead terminal extending linearly from the sealing resin are disposed in parallel with respect to one IC regulator, andthe lead terminal of the plurality of lead terminals to be positioned in the lead opposing portion is formed to be longer than the other lead terminals by an amount equivalent to the lead protruding portion.3. The vehicle-use alternating current generator regulator according to claim 1 , whereina plurality of the lead terminal to be positioned in the lead opposing portion are disposed with respect to one IC regulator. ...

MICROELECTRONIC DEVICES DESIGNED WITH MODULAR SUBSTRATES HAVING INTEGRATED FUSES

Embodiments of the invention include a microelectronic device that includes a plurality of organic dielectric layers, a cavity formed in at least one organic dielectric layer of the plurality of organic dielectric layers and a modular structure having first and second ports and a conductive member that is formed within the cavity. The conductive member provides modularity by being capable of connecting the first and second ports and also disconnecting the first and second ports. 1. A microelectronic device comprising:a plurality of organic dielectric layers;a cavity formed in at least one organic dielectric layer of the plurality of organic dielectric layers; anda modular structure having first and second ports and a first conductive member that is formed within the cavity, the first conductive member provides modularity by being capable of connecting the first and second ports and also disconnecting the first and second ports, wherein the first and second ports are embedded in the plurality of organic dielectric layers.2. The microelectronic device of claim 1 , wherein the cavity is formed by removing the at least one organic dielectric in proximity to the first conductive member to release the first conductive member.3. The microelectronic device of claim 1 , wherein the first conductive member disconnects the first and second ports when a threshold voltage is applied between the first and second ports to cause the first conductive member to heat up to a melting point of the first conductive member.4. The microelectronic device of claim 1 , wherein the modular structure further comprises a third port claim 1 , a second conductive member claim 1 , and a third conductive member with the second conductive member being coupled to the second and third ports while the third conductive member is coupled to the first and third ports.5. The microelectronic device of claim 4 , wherein the second conductive member provides modularity by being capable of connecting the second ...

DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME

Disclosed herein are a display device with a reduced bezel area and a method for fabricating the same. A wiring electrode disposed on a substrate is electrically connected to a connection electrode disposed on an inclined surface of a circuit board in contact with the substrate, and the connection electrode is electrically connected to a circuit wiring disposed on the circuit board. Therefore, an inactive area such as a pad portion for connecting the substrate with the circuit board is not required, such that the bezel area can be reduced. 1. A display device comprising:a substrate with light-emitting elements and wiring electrodes for supplying driving signals and current thereto;a circuit board disposed on the substrate and covering a part of the wiring electrodes, a plurality of circuit wirings being disposed on a first surface of the circuit board; anda plurality of connection electrodes respectively connecting the wiring electrodes to the circuit wirings,wherein the circuit board has an inclined surface and the connection electrodes extend on the inclined surface to the first surface of the circuit board.2. The display device of claim 1 , wherein the inclined surface is disposed between the first surface and the substrate and/or wherein the first surface extends in parallel to the substrate.3. The display device of claim 1 , further comprising: a buffer layer at the inclined surface of the circuit board for compensating a step difference between the circuit board and the substrate.4. The display device of claim 3 , wherein the buffer layer has a tapered shape with an inclination angle with respect to the substrate corresponding to that of the inclined surface of the circuit board.5. The display device of claim 1 , wherein a reflective layer is disposed between the circuit board and the substrate.6. The display device of claim 1 , wherein the connection electrodes and/or at least one dummy electrode extend from the substrate on the inclined surface to the first ...

Integrated Circuit Packages and Methods of Forming Same

An integrated circuit package and a method of forming the same are provided. A method includes attaching a first side of an integrated circuit die to a carrier. An encapsulant is formed over and around the integrated circuit die. The encapsulant is patterned to form a first opening laterally spaced apart from the integrated circuit die and a second opening over the integrated circuit die. The first opening extends through the encapsulant. The second opening exposes a second side of the integrated circuit die. The first side of the integrated circuit die is opposite the second side of the integrated circuit die. A conductive material is simultaneously deposited in the first opening and the second opening.

ACTIVE HEATSINK LID

An active device lid for a device base. The device lid includes a heatsink proximate to a circuit assembly and configured to remove heat generated by the device base, the circuit assembly configured to generate an operating signal voltage for the device base, and a connector configured to connect the circuit assembly to the device base, where the device base is configured to connect to a device mounting substrate on a substrate side of the device base, and where the circuit assembly is configured to be at least partially located on an opposing side of the device base, the opposing side opposing the substrate side. 1. A device lid for a device base , the device lid comprising:a heatsink proximate to a circuit assembly and configured to remove heat generated by the device base;the circuit assembly configured to generate an operating signal voltage for the device base; anda connector configured to connect the circuit assembly to the device base,wherein the device base is configured to connect to a device mounting substrate on a substrate side of the device base, andwherein the circuit assembly is configured to be at least partially located on an opposing side of the device base, the opposing side opposing the substrate side.2. The device lid of claim 1 ,wherein the heatsink comprises a first portion for collecting the heat from the device base and a second portion for releasing the heat into an ambient space,wherein the circuit assembly is interposed between the first portion and the second portion of the heatsink.3. The device lid of claim 2 ,wherein the heatsink penetrates an opening in the circuit assembly to connect to the device base.4. The device lid of claim 3 , further comprising:an input connector configured to receive a system signal voltage, wherein the system signal voltage is used by the circuit assembly to generate the operating signal voltage; andan output connector configured to provide the operating signal voltage to the device base,wherein the input ...

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Disclosed is a semiconductor package comprising a lower substrate including a conductive line; a first semiconductor chip on the lower substrate; an under-fill layer between the first semiconductor chip and the lower substrate, the under-fill layer including a central part below the first semiconductor chip and an edge part isolated from direct contact with the central part in a first direction parallel to a top surface of the lower substrate, and a recess region between the central part and the edge part. The recess region may be defined by a sidewall of the central part, a sidewall of the edge part, and a top surface of the conductive line in the lower substrate. 110.-. (canceled)11. A semiconductor package , comprising:a lower substrate including a conductive line;a first semiconductor chip on the lower substrate; a central part below the first semiconductor chip, and', 'an edge part isolated from direct contact with the central part in a first direction parallel to a top surface of the lower substrate; and, 'an under-fill layer between the first semiconductor chip and the lower substrate, the under-fill layer including'}a recess region between the central part and the edge part, the recess region defined by a sidewall of the central part, a sidewall of the edge part, and a portion of a top surface of the conductive line.12. The semiconductor package of claim 11 , whereinthe central part of the under-fill layer fills a space between the lower substrate and the first semiconductor chip, andthe recess region of the under-fill layer is adjacent to a side of the first semiconductor chip.13. The semiconductor package of claim 11 , wherein a width in the first direction of the recess region is less than a width in the first direction of the conductive line.14. The semiconductor package of claim 11 , wherein a width in the first direction of the recess region is in a range of 10 μm to 500 μm.15. The semiconductor package of claim 11 , whereina height of the sidewall of ...

SEMICONDUCTOR PACKAGE AND PACKAGE-ON-PACKAGE INCLUDING THE SAME

A semiconductor package that includes a support wiring structure. A semiconductor chip is on the support wiring structure. A cover wiring structure is on the semiconductor chip. A plurality of connection structures penetrates a filling member and electrically connects the support wiring structure to the cover wiring structure. The filling member fills a space between the support wiring structure and the cover wiring structure. The filling member surrounds the plurality of connection structures and the semiconductor chip and includes a plurality of fillers. A partial portion of the plurality of fillers includes cutting fillers having a flat surface that extends along a vertical level that is a reference level. 1. A semiconductor package comprising:a support wiring structure;a semiconductor chip on the support wiring structure;a cover wiring structure on the semiconductor chip;a plurality of connection structures penetrating a filling member and configured to electrically connect the support wiring structure to the cover wiring structure; andthe filling member fills a space between the support wiring structure and the cover wiring structure, the filling member surrounding the plurality of connection structures and the semiconductor chip and including a plurality of fillers;wherein a partial portion of the plurality of fillers includes cutting fillers having a flat surface that extends along a vertical level that is a reference level.2. The semiconductor package of claim 1 , wherein the flat surface of the cutting filler is an upper surface of the cutting filler claim 1 , and a remaining portion of the cutting filler extends below the reference level.3. The semiconductor package of claim 1 , wherein an upper surface of the semiconductor chip is positioned at the reference level.4. The semiconductor package of claim 3 , wherein each of the plurality of connection structures has an entasis shape and a maximum horizontal width of the plurality of connection structures is ...

ELECTRONIC PACKAGE AND METHOD FOR MANUFACTURING THE SAME

The present disclosure provides an electronic package and method of manufacturing the same. The electronic package includes an electronic device including a first carrier and a first electronic component disposed on the first carrier, a second carrier adjacent to the first carrier of the electronic device, and a conductive layer at least partially covering the electronic device, and separating the electronic device from the second carrier. 1. An electronic package , comprising:an electronic device comprising a first carrier and a first electronic component disposed on the first carrier;a second carrier adjacent to the first carrier of the electronic device; anda conductive layer at least partially covering the electronic device, and separating the electronic device from the second carrier.2. The electronic package according to claim 1 , further comprising a first substrate disposed under the first carrier and the second carrier claim 1 , wherein the first carrier and the second carrier are electrically connected to the first substrate.3. The electronic package according to claim 2 , further comprising a second electronic component disposed on the second carrier claim 2 , wherein the second electronic component is electrically connected to the electronic device by an electrical element electrically connected to the first substrate through a gap between the first carrier and the second carrier.4. The electronic package according to claim 3 , wherein the first carrier and the second carrier are portions of a second substrate.5. The electronic package according to claim 1 , further comprising a connect portion connecting the first carrier to the second carrier to form a second substrate.6. The electronic package according to claim 5 , further comprising a second electronic component disposed on the second carrier claim 5 , and the second electronic component is electrically connected to the electronic device through the second carrier and the connect portion.7. The ...

POWER MODULE WITH THE INTEGRATION OF CONTROL CIRCUIT

The present disclosure provides a power module with the integration of a control circuit at least, including: a power substrate; a power device mounted on the power substrate; and at least one control substrate which supports the control circuit, is electrically connected with the power substrate and disposed at an angle of inclination on a surface of the power substrate on which the power device is mounted; wherein the angle of inclination is greater than or equal to 45 degrees and smaller than or equal to 135 degrees. In the power module provided by the present disclosure, only the power substrate as well as the connections between the control substrate and the power substrate occupies the footprint area of the power module, and thus the horizontal footprint area of the power module is effectively reduced and thereby the power density of the power module is increased. 1. A power module with the integration of a control circuit , comprising:a power substrate;a power device mounted on the power substrate; andat least one control substrate which supports the control circuit, is electrically connected with the power substrate and disposed at an angle of inclination on a surface of the power substrate on which the power device is mounted;wherein the angle of inclination is greater than or equal to 45 degrees and smaller than or equal to 135 degrees.2. The power module according to claim 1 , wherein the power substrate comprises at least one conductive wiring layer on which the power device is disposed.3. The power module according to claim 1 , wherein the at least one control substrate comprises at least one conductive wiring layer and at least one insulation layer claim 1 , and a control device in the control circuit is disposed on the at least one conductive wiring layer.4. The power module according to claim 3 , wherein the at least one control substrate comprises two conductive wiring layers disposed on both sides of the at least one insulation layer claim 3 , ...

Compound carrier board structure of flip-chip chip-scale package and manufacturing method thereof

A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate having a flip region with a through-opening and bonding to a Non-conductive Film to bond to a carrier board in order to form a compound carrier board structure. Therefore, when a die is planted in the film region of the carrier board structure, the carrier board is able to susceptible to different stresses during a package process. The baseplate uses the low Thermal Expansion Coefficient material to avoid warpage problems caused by the thermal expansion of the carrier board resulting from the thermal stresses. The carrier board is able to disperse conduction of thermal stresses by the baseplate in order to strengthen cooling effect of the compound carrier board structure. Thus, the present invention achieves miniaturization and heat strengthening and enhances the mechanical strength.

Semiconductor package with dual sides of metal routing

A method includes forming a redistribution structure over a carrier, the redistribution structure having conductive features on a surface of the redistribution structure distal the carrier; forming a conductive pillar over the surface of the redistribution structure; attaching a die to the surface of the redistribution structure adjacent to the conductive pillar, where die connectors of the die are electrically coupled to the conductive features of the redistribution structure; and attaching a pre-made substrate to the conductive pillar through a conductive joint, where the conductive joint is on the conductive pillar and comprises a different material from the conductive pillar, where the conductive joint and the conductive pillar electrically couple the redistribution structure to the pre-made substrate.

INTEGRATED FAN-OUT PACKAGES AND METHODS OF FORMING THE SAME

Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip. 1. An integrated fan-out package , comprising:a first semiconductor chip comprising a heat dissipation layer on a first surface thereof;a plurality of thermal vias above the first semiconductor chip and in physical contact with the heat dissipation layer;an encapsulation layer encapsulating the plurality of thermal through integrated fan-out vias; anda redistribution layer structure at the first side of the first semiconductor chip and thermally connected to the plurality of thermal vias,wherein the plurality of thermal vias are arranged near a hot spot of a semiconductor chip.2. The integrated fan-out package of claim 1 , wherein the heat dissipation layer completely covers the first surface of the first semiconductor chip.3. The integrated fan-out package of claim 1 , wherein the heat dissipation layer comprises Al claim 1 , Cu claim 1 , Ni claim 1 , Co claim 1 , Ti claim 1 , W claim 1 , silicon carbide claim 1 , aluminum nitride claim 1 , graphite or a combination thereof.4. The integrated fan-out package of claim 1 , wherein the heat dissipation layer covering at least 30 percent of a first surface of the first semiconductor chip.5. The integrated fan-out package of claim 1 , further comprising:a second semiconductor chip ...

INTERPOSER AND CIRCUIT SUBSTRATE

An interposer includes an insulating plate including insulating layers and having first, second, third and fourth surfaces such that the second surface is on the opposite side of the first surface, the third surface is perpendicular to the first surface, the fourth surface is on the opposite side of the third surface, and the insulating layers are laminated on the third surface, and conductor layers formed in the insulating plate such that each conductor layer is interposed between adjacent insulating layers and includes straight conductors having first electrodes exposed from the first surface and second electrodes exposed from the second surface, respectively. The insulating layers include second insulating layers each sandwiched by adjacent conductor layers such that each second insulating layer integrally has an inter-conductor-layer insulating layer portion formed between the adjacent conductor layers and inter-conductor insulating layer portions formed between adjacent straight conductors in a respective conductor layer. 1. An interposer , comprising:an insulating plate comprising a plurality of insulating layers and having a first surface, a second surface, a third surface and a fourth surface such that the second surface is on an opposite side of the first surface, the third surface is perpendicular to the first surface, the fourth surface is on an opposite side of the third surface, and the plurality of insulating layers is laminated on the third surface; anda plurality of conductor layers formed in the insulating plate such that each of the conductor layers is interposed between adjacent insulating layers and comprises a plurality of straight conductors having a plurality of first electrode portions exposed from the first surface at one ends and a plurality of second electrode portions exposed from the second surface at opposite ends, respectively,wherein the plurality of insulating layers includes a plurality of second insulating layers each sandwiched by ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a first circuit board having a first chip and a second chip mounted on a first base, the second chip having a greater height from the first base than that of the first chip; and a second circuit board having a third chip and a fourth chip mounted on a second base, the fourth chip having a greater height from the second base than that of the third chip, the second circuit board being disposed overlapping with the first base such that the second base faces the first chip, and the second base not contacting the second chip. 1. A semiconductor device comprising:a first circuit board having a first chip and a second chip mounted on a first base, with the second chip having a greater height from the first base than that of the first chip; anda second circuit board having a third chip and a fourth chip mounted on a second base, the fourth chip having a greater height from the second base than that of the third chip, with the second circuit board disposed overlapping with the first circuit board such that the second base faces the first chip, and the second base not contacting the second chip.2. The semiconductor device of claim 1 , wherein the second base is narrower in width than the first base and does not contact the second chip.3. The semiconductor device of claim 2 , wherein:the first base further includes a protrusion protruding further toward an outer-side than the second base in plan view; andthe second chip is mounted on the protrusion.4. The semiconductor device of claim 1 , wherein:the second chip is housed in a housing hole that penetrates the second base such that the second base does not contact the second chip.5. The semiconductor device of claim 1 , further comprising a connecting member that is disposed between the first base and the second base claim 1 , and that electrically connects the first base and the second base.6. The semiconductor device of claim 5 , wherein the connecting member is disposed at a position ...

ELECTRONIC DEVICE MODULE AND METHOD OF MANUFACTURING THE SAME

In one general aspect, an electronic device module includes a first board, a first device mounted on a first surface of the first board, a second board disposed below the first board, and a plurality of second devices disposed between the first board and the second board, wherein a surface of each second device the plurality of second devices is bonded to a second surface of the first board and another surface of each of the second devices is bonded to the second board. 1. An electronic device module comprising:a first board;a first device mounted on a first surface of the first board;a second board disposed below the first board; anda plurality of second devices disposed between the first board and the second board, wherein a surface of each second device of the plurality of second devices is bonded to a second surface of the first board and another surface of each of the second devices is bonded to the second board.2. The electronic device module of claim 1 , further comprising a plurality of external connection terminal disposed on a lower surface of the second board.3. The electronic device module of claim 1 , wherein connection terminals are formed on the surfaces of each second device of the plurality of second devices and the plurality of second devices are bonded to the first and second boards through the connection terminals.4. The electronic device module of claim 3 , wherein the first and second boards are electrically connected to each other through the connection terminals of the plurality of second devices.5. The electronic device module of claim 3 , wherein the plurality of second devices include an electronic component having a hexahedral shape claim 3 , and each of the second devices have the same or similar thickness as each other.6. The electronic device module of claim 3 , wherein the second device comprises at least one electronic component and at least one dummy device.7. The electronic device module of claim 1 , further comprising an ...

Semiconductor device package and method of manufacturing the same

The present disclosure provides a semiconductor device package. The semiconductor device package includes a first substrate and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface of the first substrate. The second substrate has a first surface facing the first substrate and a second surface opposite to the first surface of the second substrate. The semiconductor device package also includes a first electronic component disposed on the first surface of the second substrate and electrically connected to the first surface of the second substrate. The semiconductor device package also includes a first encapsulant and a second encapsulant between the first substrate and the second substrate. The first encapsulant is different from the second encapsulant. A method of manufacturing a semiconductor device package is also disclosed.

INTEGRATED SUBSTRATE STRUCTURE, ELECTRONIC ASSEMBLY, AND MANUFACTURING METHOD THEREOF

An integrated substrate, an electronic assembly, and manufacturing methods thereof are provided. The integrated substrate structure includes a coarse redistribution structure, fine redistribution segments, and conductive connectors. The coarse redistribution structure includes a coarse dielectric layer and a coarse circuitry embedded therein. The fine redistribution segments disposed over the coarse redistribution structure and disposed side by side and apart from one another. The respective fine redistribution segment includes a fine dielectric layer thinner than the coarse dielectric layer, and a fine circuitry embedded in the fine dielectric layer. The fine circuitry includes a dimension and a pitch finer than those of the coarse circuitry, and a layout density of the fine circuitry is denser than that of the coarse circuitry. The conductive connectors are interposed between the coarse redistribution structure and the fine redistribution segments, and the coarse circuitry is electrically coupled to the fine circuitry through the conductive connectors. 1. An integrated substrate structure for coupling a fine-pitched chip , comprising:a coarse redistribution structure comprising a coarse dielectric layer and a coarse circuitry embedded in the coarse dielectric layer; a fine dielectric layer being thinner than the coarse dielectric layer; and', 'a fine circuitry embedded in the fine dielectric layer, the fine circuitry comprising a dimension and a pitch finer than those of the coarse circuitry of the coarse redistribution structure, and a layout density of the fine circuitry being denser than a layout density of the coarse circuitry; and, 'a plurality of fine redistribution segments disposed over the coarse redistribution structure and coupled to the fine-pitched chip, the plurality of fine redistribution segments being disposed side by side and spatially apart from one another, each of the plurality of fine redistribution segments comprisinga plurality of ...

Packaged circuit structure and method for manufacturing the same

A package circuit structure includes a metal board including a first surface and a second surface, a plurality of embedded components, an insulating layer, and two antenna circuit boards. At least one first groove is recessed from the first surface. At least one second groove is recessed from the second surface. The first groove and the second groove are spaced with each other along a first direction perpendicular to a thickness direction of the metal board. Each embedded component is mounted in the first groove or the second groove. The insulating layer covers the first surface and the second surface and fills the first groove and the second groove. The antenna circuit boards are respectively stacked on two opposite sides of the insulating layer. Each antenna circuit board includes at least one antenna and at least one ground wiring. The metal board is electrically connected to each ground wiring.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a substrate, a conductive layer, a first surface mount device (SMD) and a bonding wire. The substrate has a t top surface. The first conductive layer is formed on the top surface and has a first conductive element and a first pad separated from each other. The first SMD is mounted on the first pad, overlapping with but electrically isolated from the first conductive element. The first bonding wire electrically connects the first SMD with the first conductive layer. 1. A semiconductor package , comprising:a substrate having a top surface;a conductive layer formed on the top surface and having a first conductive element and a first pad separated from each other;a surface mount device (SMD) mounted on the first pad, overlapping with and electrically isolated from the first conductive element; anda bonding wire electrically connect the SMD with the first conductive layer.2. The semiconductor package according to claim 1 , wherein the SMD comprises a first electrode and a second electrode; the bonding wire electrically connects the first electrode with a second conductive element of the conductive layer; and the second conductive element is separated from the first pad.3. The semiconductor package according to claim 1 , further comprising a solder resistance layer covering a portion of the conductive layer and allowing the SMD mounted thereon.4. The semiconductor package according to claim 2 , wherein the second electrode is mounted on and electrically connected to the first pad through a conductive paste layer; and the first electrode is mounted on and electrically isolated from a second pad of the first conductive layer through a solder resistance layer.5. The semiconductor package according to claim 4 , wherein the second pad is separated from the first conductive element and the second conductive element.6. A semiconductor package claim 4 , comprising:a first substrate having a first top surface;a first conductive layer formed on the ...

SUBSTRATE-EMBEDDED SUBSTRATE

A chip package substrate and methods for fabricating the chip package substrate. An exemplary chip package substrate generally includes a first substrate and a second substrate embedded in the first substrate and having a plurality of layered traces embedded therein. 1. A chip package substrate comprising:a first substrate; anda second substrate embedded in the first substrate and having a plurality of layered traces embedded therein, wherein the second substrate is a coreless embedded trace substrate and wherein the plurality of layered traces are embedded in a pre-impregnated dielectric material of the second substrate.2. The chip package substrate of claim 1 , wherein the first substrate and the second substrate are coupled through one or more micro-vias.3. The chip package substrate of claim 1 , wherein the first substrate comprises at least one of a core dielectric material or a substrate material having at least two layers.4. (canceled)5. The chip package substrate of claim 1 , wherein the first substrate has a thickness in a range of 150 to 400 μm.6. The chip package substrate of claim 3 , wherein the first substrate comprises a copper-clad laminate.7. The chip package substrate of claim 1 , wherein the second substrate comprises three or four layers of embedded traces.8. The chip package substrate of claim 1 , further comprising an insulation layer arranged below the first and second substrates claim 1 , wherein the insulation layer comprises an insulating buildup film.9. The chip package substrate of claim 8 , further comprising a layer of solder resist arranged below the insulation layer and having trenches for exposing traces coupled to the second substrate for coupling to an electronic component.10. The chip package substrate of claim 1 , further comprising a layer of solder resist arranged above the first and second substrates and having one or more trenches for exposing traces coupled to the second substrate for coupling to an electronic component.11. ...

Substrate with embedded stacked through-silicon via die

A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.

Bonding Package Components Through Plating

A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

INTERPOSER FRAME AND METHOD OF MANUFACTURING THE SAME

Some embodiments relate to a package. The package includes a first substrate, a second substrate, and an interposer frame between the first and second substrates. The first substrate has a first connection pad disposed on a first face thereof, and the second substrate has a second connection pad disposed on a second face thereof. The interposer frame is arranged between the first and second faces and generally separates the first substrate from the second substrate. The interposer frame includes a plurality of through substrate holes (TSHs) which pass entirely through the interposer frame. A TSH is aligned with the first and second connection pads, and solder extends through the TSH to electrically connect the first connection pad to the second connection pad. 1. A package comprising:a first substrate comprising a first plurality of connectors; an interposer substrate having a plurality of through substrate holes (TSHs) which are aligned with the first plurality of connectors, respectively, and having an opening whose width is greater than a width of each TSH of the plurality of TSHs, wherein the interposer substrate is made of a base material and at least one additive and the at least one additive adjusts a strength and a coefficient of thermal expansion of the interposer substrate; and', 'a conductive layer lining sidewalls of each TSH of the plurality of TSHs, the conductive layer filling less than an entirety of each TSH;, 'an interposer frame arranged over the first substrate, the interposer frame comprisinga semiconductor die arranged in the opening in the interposer substrate; anda second substrate arranged over the interposer frame and electrically connected to the first plurality of connectors, wherein a conductive structure extends through at least one TSH of the plurality of TSHs to electrically connect the second substrate to a connector of the first plurality of connectors.2. The package of claim 1 , wherein the conductive structure includes solder to ...

Wafer-level stack chip package and method of manufacturing the same

A semiconductor product in the form of a stack chip package and a method of manufacturing the same, where a plurality of semiconductor chips are stacked one on another so as to enable the exchange of electrical signals between the semiconductor chips, and where a conductive layer is included for inputting and outputting signals to and from individual chips. A stack chip package having a compact size may, for example, be manufactured by stacking, on a first semiconductor chip, a second semiconductor chip having a smaller surface area by means of interconnection structures so as to enable the exchange of electrical signals between the first and second semiconductor chips, and by using a conductive layer for inputting and outputting signals to and from individual semiconductor chips, in lieu of a thick substrate. Furthermore, heat dissipation effects can be enhanced by the addition of a heat dissipation unit.

Z-AXIS GUARDBANDING USING VERTICAL GROUND CONDUCTORS FOR CROSSTALK MITIGATION

In one embodiment, an interposer may include a top surface, a bottom surface, a ground plane disposed between the top surface and bottom surface, an array of top contacts on the top surface, a corresponding array of bottom contacts on the bottom surface, a plurality of through connections between corresponding top and bottom contacts, and a plurality of ground conductors interspersed with the plurality of through connections. The array of top contacts may be configured to interface with a first component above the interposer. The array of bottom contacts may be configured to interface with a second component beneath the interposer. The ground conductors may extend orthogonally through, and be electrically connected to, the ground plane. 1. An interposer comprising:a top surface;a bottom surface;a ground plane disposed between the top surface and bottom surface;an array of top contacts on the top surface configured to interface with a first component above the interposer,a corresponding array of bottom contacts on the bottom surface configured to interface with a second component beneath the interposer,a plurality of through connections between corresponding top and bottom contacts;a plurality of signal traces, each respective signal trace configured to allow an electrical signal traveling through a respective through connection to be tested at a location near the edge of the interposer; anda plurality of ground conductors interspersed with the plurality of through connections, wherein the ground conductors extend orthogonally through, and are electrically connected to, the ground plane.2. The interposer of claim 1 , wherein the plurality of through connections is arranged in rows of through connections claim 1 , wherein the plurality of ground conductors is arranged in rows claim 1 , and wherein the rows of ground conductors are disposed between the rows of through connections.3. The interposer of claim 2 , wherein a first row of through connections is flanked on ...

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A package structure includes a semiconductor die, a redistribution circuit structure, and a metallization element. The semiconductor die has an active side and an opposite side opposite to the active side. The redistribution circuit structure is disposed on the active side and is electrically coupled to the semiconductor die. The metallization element has a plate portion and a branch portion connecting to the plate portion, wherein the metallization element is electrically isolated to the semiconductor die, and the plate portion of the metallization element is in contact with the opposite side. 1. A package structure , comprising:a semiconductor die, having an active side and an opposite side opposite to the active side;a redistribution circuit structure, disposed on the active side and electrically coupled to the semiconductor die; anda metallization element, having a plate portion and a branch portion connecting to the plate portion, wherein the metallization element is electrically isolated to the semiconductor die, and the plate portion of the metallization element is in contact with the opposite side.2. The package structure of claim 1 , wherein the plate portion of the metallization element is in physical contact with the opposite side of the semiconductor die.3. The package structure of claim 1 , wherein the plate portion of the metallization element is sandwiched between the semiconductor die and the branch portion.4. The package structure of claim 1 , wherein the metallization element is thermally coupled to the semiconductor die.5. The package structure of claim 1 , further comprising:an insulating encapsulation, laterally encapsulating the semiconductor die and sandwiched between the redistribution circuit structure and the metallization element; andconductive terminals, disposed on and electrically connected to the redistribution circuit structure, wherein the redistribution circuit structure is sandwiched between the conductive terminals and the ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes an insulated circuit board having conductor layers arranged away from each other and bonding materials each provided on the conductor layers; a wiring board having an opposing surface facing the conductor layers and through holes each corresponding to a position of each bonding material; hollow members each having a cylindrical portion and a flanged portion at one end of the cylindrical portion and having a cavity in common with the cylindrical portion, ok cylindrical portions press-fitted into the through holes, and other ends of the cylindrical portions bonded to the conductor layers by the bonding materials; and external connection terminals each inserted into the cavity of each hollow member and bonded to the conductor layers. Each cylindrical portion is inserted into each through hole such that each flanged portion contacts with an upper surface opposed to the opposing surface of the wiring board. 1. A semiconductor device comprising:an insulated circuit board including conductor layers arranged away from each other and a plurality of bonding materials each provided on the conductor layers;a wiring board including an opposing surface facing the conductor layers and including a plurality of through holes each corresponding to a position of each of the plurality of bonding materials;a plurality of hollow members including a cylindrical portion and a flanged portion provided at one end of the cylindrical portion and having a cavity in common with the cylindrical portion, the cylindrical portions each being press-fitted into each of the plurality of through holes, and other ends of the cylindrical portions being bonded to the conductor layers by the plurality of bonding materials; anda plurality of external connection terminals each inserted into the cavity of each of the plurality of hollow members and bonded to the conductor layers,wherein the cylindrical portions each are inserted into the each of the plurality of through holes ...

SEMICONDUCTOR DEVICE

A semiconductor device implements upper and lower arms for three phases by a plurality of semiconductor chips, an insulated circuit board, and a printed board, the printed board includes: a plurality of upper relay pattern layers arranged on one main surface of an insulating layer; an upper common pattern layer arranged on the one main surface of the insulating layer; a plurality of lower relay pattern layers arranged to be opposed to the upper relay pattern layers on another main surface opposite to the one main surface of the insulating layer; and a lower common pattern layer arranged to be opposed to the upper common pattern layer on the other main surface of the insulating layer, and control wires electrically connected to the semiconductor chips are partly provided in regions between the upper relay pattern layers and the upper common pattern layer. 1. A semiconductor device comprising:a plurality of semiconductor chips each having a control electrode;an insulated circuit board in which the plural semiconductor chips are mounted on one main surface;a printed board arranged to be opposed to the one main surface of the insulated circuit board; anda plurality of control wires each electrically connected to one of the control electrodes,wherein upper and lower arms for three phases are implemented by the semiconductor chips, the insulated circuit board, and the printed board, an insulating layer;', 'a plurality of upper relay pattern layers arranged on one main surface of the insulating layer;', 'an upper common pattern layer arranged parallel to the upper relay pattern layers on the one main surface of the insulating layer;', 'a plurality of lower relay pattern layers arranged to be opposed to the upper relay pattern layers on another main surface opposite to the one main surface of the insulating layer and individually having a potential equal to that of the corresponding upper relay pattern layers; and', 'a lower common pattern layer arranged to parallel to the ...

METHODS AND APPARATUS FOR PROVIDING AN INTERPOSER FOR INTERCONNECTING SEMICONDUCTOR CHIPS

Methods and apparatus are provide for an interposer for interconnecting one or more semiconductor chips with an organic substrate in a semiconductor package, the interposer including: a first glass substrate having first and second opposing major surfaces, the first glass substrate having a first coefficient of thermal expansion (CTE1); a second glass substrate having first and second opposing major surfaces, the second glass substrate having a second coefficient of thermal expansion (CTE2); and an interface disposed between the first and second glass substrates and joining the second major surface of the first glass substrate to the first major surface of the second glass substrate, where CTE1 is less than CTE2, the first major surface of the first glass substrate operates to engage the one or more semiconductor chips, and the second major surface of the second glass substrate operates to engage the organic substrate. 1. An interposer for interconnecting one or more semiconductor chips with a substrate in a semiconductor package , the interposer comprising:a first glass substrate having first and second opposing major surfaces, the first glass substrate having a first coefficient of thermal expansion (CTE1);a second glass substrate having first and second opposing major surfaces, the second glass substrate having a second coefficient of thermal expansion (CTE2);an interface disposed between the first and second glass substrates and joining the second major surface of the first glass substrate to the first major surface of the second glass substrate; andat least one via extending from the first major surface of the first glass substrate to the second major surface of the second glass substrate,wherein CTE1 is less than CTE2, the first major surface of the first glass substrate operates to engage the one or more semiconductor chips, and the second major surface of the second glass substrate operates to engage the substrate.2. The interposer of claim 1 , wherein 1≦ ...

CHIP PACKAGE STRUCTURE

A chip package structure including a molding compound, a carrier board, a chip, a plurality of conductive pillars and a circuit board is provided. The carrier board includes a substrate and a redistribution layer. The substrate has a first surface and a second surface. The redistribution layer is disposed on the first surface. The chip and the conductive pillars are disposed on the redistribution layer. The molding compound covers the chip, the conductive pillars, and the redistribution layer. The circuit board is connected with the carrier board, wherein the circuit board is disposed on the molding compound, such that the chip is located between the substrate and the circuit board, and the chip and the redistribution layer are electrically connected with the circuit board through the conductive pillars. Heat generated by the chip is transmitted through the substrate from the first surface to the second surface to dissipate. 1. A chip package structure , comprising:at least one carrier board comprising a substrate and a redistribution layer, wherein the substrate has a first surface and a second surface opposite to each other, and the redistribution layer is disposed on the first surface of the substrate;at least one chip disposed on the redistribution layer;at least one conductive pillar disposed on the redistribution layer, wherein the at least one conductive pillar is located at a periphery of the at least one chip;at least one molding compound disposed on the redistribution layer and covering the at least one chip, the at least one conductive pillar, and the redistribution layer, wherein the at least one conductive pillar passes through the at least one molding compound; anda circuit board disposed on the at least one molding compound, wherein the circuit board is connected with the at least one carrier board through the at least one conductive pillar, such that the at least one chip is located between the substrate and the circuit board, and the at least one ...

SEMICONDUCTOR MODULE, BONDING JIG, AND MANUFACTURING METHOD OF SEMICONDUCTOR MODULE

A semiconductor module includes an image pickup device on which a bump is disposed, and a flexible wiring board having a flexible resin as a base and including a wire having a bonding electrode at a distal end portion solder-bonded to the bump, in which the bonding electrode is pressed against the bump by bending/deformation of the wiring board caused by application of heat to a solder bonding temperature. 1. A semiconductor module comprising:a semiconductor device on which a first electrode is disposed; anda flexible wiring board including a wire having a second electrode at a distal end portion solder-bonded to the first electrode, whereinthe wiring board includes a laminate substrate in which a plurality of substrates with different thermal expansion coefficients are laminated, andthe second electrode is pressed against the first electrode by bending/deformation of the wiring board caused by application of heat to a solder bonding temperature and by a difference in the thermal expansion coefficients of the plurality of substrates.2. The semiconductor module according to claim 1 , whereinthe laminate substrate is a laminate of a first substrate and a second substrate with different thermal expansion coefficients, andthe first substrate to which the second electrode is bonded has a smaller thermal expansion coefficient than the second substrate.3. The semiconductor module according to claim 1 , wherein the plurality of substrates are made of resin.4. The semiconductor module according to claim 1 , whereinthe first electrode is a solder bump, andthe second electrode is a protruding electrode of metal that does not melt at the solder bonding temperature.5. The semiconductor module according to claim 1 , wherein the first electrode is disposed on a main surface of the semiconductor device.6. The semiconductor module according to claim 1 , wherein the first electrode is disposed on a tapered side surface of the semiconductor device.7. A bonding jig used for heating and ...

Multichip module, on board computer, sensor interface substrate, and the multichip module manufacturing method

A multichip module includes a plurality of semiconductor substrates and a plurality of surface mounting parts. The plurality of semiconductor substrates each have a wiring line region which contains a wiring line to pierce from one of the surfaces to the other surface. A plurality of surface mounting parts are mounted on either of the plurality of surface mounting parts. The plurality of semiconductor substrates are stacked to form a multilayer structure. The first surface mounting part as at least one of the plurality of surface mounting parts is arranged in an inside region of the multilayer structure.

SEMICONDUCTOR MODULE

A semiconductor module includes a printed circuit board having an insulating plate, first and fourth wiring layers disposed on a principal surface of the insulating plate, second and third wiring layers disposed on another surface opposite to the principal surface, a first via disposed in the insulating plate and electrically and mechanically connected to the first and third wiring layers, and a second via disposed in the insulating plate and electrically and mechanically connected to the second and fourth wiring layers; a first insulating substrate disposed with a first circuit plate; a second insulating substrate disposed with a second circuit plate; a first semiconductor chip; a second semiconductor chip; a first heat release member fixed between the third wiring layer and the third circuit plate; and a second heat release member fixed between the fourth wiring layer and the first circuit plate. 1. A semiconductor module , comprising: an insulating plate,', 'a first wiring layer and a fourth wiring layer disposed on a principal surface of the insulating plate,', 'a second wiring layer and a third wiring layer disposed on a surface opposite to the principal surface,', 'a first via disposed in the insulating plate, and electrically and mechanically connected to the first wiring layer and third wiring layer, and', 'a second via disposed in the insulating plate, and electrically and mechanically connected to the second wiring layer and the fourth wiring layer;, 'a printed circuit board having'}a first insulating substrate disposed facing the first wiring layer, and having a first circuit plate on a surface facing the first wiring layer and the fourth wiring layer;a second insulating substrate disposed facing the second wiring layer, and having a second circuit plate facing the second wiring layer and a third circuit plate facing the third wiring layer;a first semiconductor chip sandwiched between the first wiring layer and the first circuit plate, and having a ...

SEMICONDUCTOR DEVICE

A semiconductor device with enhanced performance. The semiconductor device has a high speed transmission path which includes a first coupling part to couple a semiconductor chip and an interposer electrically, a second coupling part to couple the interposer and a wiring substrate, and an external terminal formed on the bottom surface of the wiring substrate. The high speed transmission path includes a first transmission part located in the interposer to couple the first and second coupling parts electrically and a second transmission part located in the wiring substrate to couple the second coupling part and the external terminal electrically. The high speed transmission path is coupled with a correction circuit in which one edge is coupled with a branching part located midway in the second transmission part and the other edge is coupled with a capacitative element, and the capacitative element is formed in the interposer. 1. A semiconductor device comprising:a first substrate having a first front surface and a first back surface opposite to the first front surface;a second substrate having a second front surface and a second back surface opposite to the second front surface and being mounted over the first substrate with the first front surface of the first substrate facing the second back surface; anda first semiconductor component mounted over the second front surface of the second substrate and coupled with a first signal transmission path,the first signal transmission path comprising:a first coupling part to couple the first semiconductor component and the second substrate electrically;a second coupling part to couple the second substrate and the first substrate;a first external terminal formed on the first back surface of the first substrate;a first transmission part located in the second substrate to couple the first coupling part and the second coupling part electrically; anda second transmission part located in the first substrate to couple the second ...

3D Semiconductor Package Interposer with Die Cavity

Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects. 1. A device , comprising:a substrate having a top surface;an interposer over the top surface of the substrate, the interposer being connected to the substrate by first interconnects;a first integrated circuit die connected to a first side of the interposer by first connectors;a second integrated circuit die connected to a second side of the interposer opposite the first side by second connectors, the second integrated circuit die having a smaller footprint than the interposer; anda fan-out structure disposed over a top surface of the interposer and extending beyond outermost edges of the interposer, wherein the fan-out structure is electrically connected to second interconnects, the second interconnects in contact with the top surface of the substrate.2. The device of claim 1 , further comprising third connectors connecting the fan-out structure to the second integrated circuit die.3. The device of claim 1 , further comprising a cavity in the top surface of the substrate claim 1 , wherein the first integrated circuit die extends into the cavity.4. The device of claim 1 , further comprising:a first molding compound on sidewalls of the interposer, the first interconnects, and the second interconnects; anda second molding compound on the first molding compound, the fan-out structure, and the second integrated circuit die.5. The device of claim 1 , ...

SEMICONDUCTOR DEVICES INCLUDING POWER CONNECTION LINES

A semiconductor chip includes a first core region including a first core and a first power line configured to provide a first voltage to the first core, a second core region including a second core and a second power line configured to provide the first voltage to the second core, a cache region between the first core region and the second core region, the cache region including a cache and a third power line providing a second voltage to the cache, and arranged between the first core region and the second core region; and a first power connection line connecting the first power line to the second power line and arranged in the cache region. 1. A semiconductor chip , comprising:a first core region including a first core and a first power line configured to provide a first voltage to the first core;a second core region including a second core and a second power line configured to provide the first voltage to the second core;a cache region between the first core region and the second core region, the cache region including a cache and a third power line configured to provide a second voltage to the cache; anda first power connection line in the cache region, the first power connection line connecting the first power line to the second power line.2. The semiconductor chip of claim 1 , whereinthe cache region includes a plurality of line layers that are stacked, andthe first power connection line is on a first line layer that is different from a separate line layer on which the third power line is located.3. The semiconductor chip of claim 1 , whereinthe first core region, the second core region, and the cache region include a plurality of line layers that are stacked, andthe first power connection line is on a same line layer as a line layer on which the first power line and the second power line are located.4. The semiconductor chip of claim 1 , whereinthe first core region, the cache region, and the second core region are aligned in a first direction,the ...

METHOD FOR FABRICATING GLASS SUBSTRATE PACKAGE

A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors. 1. A chip packaging structure comprising:a glass substrate having a first surface and a second surface opposed to said first surface, wherein said first surface is parallel to said second surface, multiple metal conductors extending through said glass substrate beginning at said first surface and ending at said second surface, wherein one of said metal conductors comprises a cross-section surface parallel to said first surface, wherein said cross-section surface comprises a first edge, a second edge opposite to and substantially parallel with said first edge, a third edge and a fourth edge opposite to said third edge, wherein said first edge has a first length is greater than that of said third and fourth edges, wherein said second edge has a second length is greater than that of said third and fourth edges, wherein said metal conductors comprises a first sidewall, a second sidewall opposite to and substantially parallel with said first sidewall, a third sidewall and a fourth sidewall opposite to said third sidewall;a first metal connection structure is on said first surface, wherein said first metal connection structure comprises a first dielectric layer on said first surface, wherein a ...

Flexible package-to-socket interposer

A flexible interposer for the attachment of a microelectronic package to a microelectronic socket, wherein a first portion of the flexible substrate may be positioned between the microelectronic package and the microelectronic socket, and a second portion of the flexible interposer may extend from between the microelectronic package and the microelectronic socket to electrically contact an external component. In one embodiment, the external component may be a microelectronic substrate and the microelectronic socket may be attached to the microelectronic substrate.

Method for Producing Power Semiconductor Module Arrangement

A method for producing a power semiconductor module arrangement having a base plate and a contact element configured to, when the base plate is arranged in a housing, provide an electrical connection between an inside and an outside of the housing, includes: connecting an electrically insulating first layer to the base plate; and connecting the contact element to the first layer. Connecting the first layer to the base plate includes forming a third layer on the base plate or on the first layer and mounting the first layer on the base plate such that the third layer attaches the first layer to the base plate. Connecting the contact element to the first layer includes forming a second layer on the first layer or on the contact element and mounting the contact element on the first layer such that the second layer attaches the contact element to the first layer.

Interposer with flexible portion

To address the issue of shrinking volume that can be allocated for electrical components, a system can use an interposer with a flexible portion. A first portion of the interposer can electrically connect to a top side of a motherboard. A flexible portion of the interposer, adjacent to the first portion, can wrap around an edge of the motherboard. A peripheral portion of the interposer, adjacent to the flexible portion, can electrically connect to a bottom side of the motherboard. The peripheral portion can be flexible or rigid. The interposer can define a cavity that extends through the first portion of the interposer. A chip package can electrically connect to the first portion of the interposer. The chip package can be coupled to at least one electrical component that extends into the cavity when the chip package is connected to the interposer.

Fan-Out Wafer Level Package Structure

A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the carrier and around the vias, and the ends of the vias and mounts on the die exposed. The vias may be in via chips with one or more dielectric layers separating the vias. The via chips may be formed separately from the carrier. The dielectric layer of the via chips may separate the vias from, and comprise a material different than, the molded substrate. An RDL having RDL contact pads and conductive lines may be formed on the molded substrate. A second structure having at least one die may be mounted on the opposite side of the molded substrate, the die on the second structure in electrical communication with at least one RDL contact pad. 1. An package comprising:a planar first surface, the planar first surface comprising a first external contact of a first die, a molding compound, and a via located within a via die, wherein the via extends from a first side of the via die to a second side of the via die, wherein the via has a straight sidewall as it extends from the first side to the second side; anda redistribution layer over the molding compound, the first via, and the first die.2. The package of claim 1 , wherein the planar first surface further comprises a second die.3. The package of claim 1 , wherein the via is in contact with a dielectric material different from the molding compound.4. The package of claim 1 , wherein the first die comprises first die mounts.5. The package of claim 4 , wherein the first die mounts comprise pins.6. The package of claim 1 , further comprising a wide I/O DRAM chip connected to the via.7. A package comprising:a first die embedded within a molding compound;a first via extending from a first side of the molding compound to a second side of the molding compound, the first via having straight sidewalls from a first side of the first via to a second side of the first via;a first ...

STACK PACKAGES

A stack package may include a first substrate package, a second substrate package, an interposer and at least one semiconductor chip. The first substrate package may include a plurality of first pads isolated from direct contact with each other by a first pitch. The second substrate package may be under the first substrate package. The second substrate package may include a plurality of second pads isolated from direct contact with each other by a second pitch. The second pitch may be different from the first pitch. The interposer may be above the first substrate package. The interposer may include a plurality of third pads isolated from direct contact with each other by a third pitch. The semiconductor chip may be arranged above the interposer. 1. A stack package , comprising:a first substrate package including a plurality of first pads isolated from direct contact with each other by a first pitch;a second substrate package under the first substrate package, the second substrate package including a plurality of second pads isolated from direct contact with each other by a second pitch, the second pitch being different from the first pitch;an interposer above the first substrate package, the interposer including a plurality of third pads isolated from direct contact with each other by a third pitch; andat least one first semiconductor chip above the interposer.2. The stack package of claim 1 , wherein the first pitch is narrower than the second pitch.3. (canceled)4. The stack package of claim 1 , wherein the first pitch is substantially the same as the third pitch.5. The stack package of claim 1 , wherein an area of the first substrate package is smaller than an area of the second substrate package and greater than an area of the interposer.6. The stack package of claim 1 , wherein the first substrate package comprises:a first insulation substrate, wherein the plurality of first pads are on an upper surface of the first insulation substrate;a plurality of first ...

PRINTED CIRCUIT BOARD INCLUDING SUB-CIRCUIT BOARD

A printed circuit board includes: a core member including a through-hole; a sub-circuit board disposed in the through-hole; a first insulating layer disposed on opposing surfaces of the core member and opposing surfaces of the sub-circuit board; and an insulating material disposed between an inner wall of the through-hole and the sub-circuit board. 1. A printed circuit board , comprising:a core member comprising a through-hole;a sub-circuit board disposed in the through-hole;a first insulating layer disposed on the core member and the sub-circuit board; and first circuit patterns having a first pitch and disposed to overlap the core member in a thickness direction, and', 'second circuit patterns having a second pitch and disposed to overlap the sub-circuit board in the thickness direction,, 'an outer circuit layer disposed on the first insulating layer, and comprising'}wherein the first pitch is larger than the second pitch.2. The printed circuit board of claim 1 , wherein the first and second circuit patterns are disposed on a same level.3. The printed circuit board of claim 1 , wherein the sub-circuit board comprises an inner circuit layer and a second insulating layer.4. The printed circuit board of claim 3 , further comprising an insulating material disposed between an inner wall of the through hole and the sub-circuit board claim 3 ,wherein the insulating material is made of a material different from a material of the second insulating layer.5. The printed circuit board of claim 4 , wherein the insulating material is filled with a material of the first insulating layer.6. The printed circuit board of claim 1 , wherein the first insulating layer further comprises a fabric stiffener.7. The printed circuit board of claim 1 , wherein the sub-circuit board comprises a coreless structure.8. The printed circuit board of claim 1 , wherein the sub-circuit board comprises a reinforcing layer comprising a fabric stiffener.9. The printed circuit board of claim 1 , wherein ...

Method For Mounting An Electrical Component In Which A Hood Is Used, And A Hood That Is Suitable For Use In This Method

A method for mounting an electrical component on a substrate is disclosed. According to the method, joining is simplified using a cover, or hood, that includes a contact structure on an inner side of the hood, wherein when the hood is mounted, the contact structure is joined to the underlying structure at different joining levels simultaneously using an additional material. Moreover, a joining pressure, e.g., for diffusion or sintered bonds for electrical contacts, can be applied using such a hood. 1. A method for mounting an electrical component on a substrate , wherein the component has a bottom side facing toward the substrate and a top side situated opposite said bottom side , the method comprising:mounting the component onto the substrate,forming a cover including integrated conductor paths that define a contacting structure, the cover laterally traverses the component,', 'first contact surfaces of the contacting structure laterally outside the component contact the substrate at a first joining level defined at the mounting side of the substrate, and', 'electrical contact is generated between second contact surfaces of the contacting structure and the component at a second joining level defined at the top side of the component, the second joining level being different than the first joining level., 'mounting the cover onto a mounting side of the substrate and onto the top side of the component mounted on the substrate, such that2. The method of claim 1 , comprising claim 1 , after mounting the component to the substrate and mounting the cover onto the substrate and the component claim 1 , performing a temperature or pressure based joining process to complete joining connections between the cover and the component at the first joining level and between the cover and the substrate at the second joining level.3. The method of claim 1 , comprising mounting a rear side of the substrate claim 1 , opposite the mounting side claim 1 , to a component part at a third ...

Semiconductor package and method of manufacturing the same

A semiconductor package includes a first substrate, a pattern layer disposed on the first substrate, a first chip member disposed on a surface of the first substrate, lead frames mounted on the first substrate surrounding the first chip member, and a first encapsulation layer disposed on the first substrate, encapsulating the first chip member and the lead frame, wherein upper end portions of the lead frame and the first encapsulation layer are removed, and lead frame columns are exposed through the first encapsulation layer.

PACKAGING STRUCTURE

A packaging structure includes a first substrate including a first metal terminal and a first protruding resin portion formed at a first surface; a second substrate including a second metal terminal and a second protruding resin portion formed at a second surface, the second metal terminal being made of the same kind of metal as the first metal terminal; and a sealing portion filled between the first surface of the first substrate and the second surface of the second substrate, the first metal terminal and the second metal terminal being directly bonded with each other, the first protruding resin portion and the second protruding resin portion being directly bonded with each other, each of the first protruding resin portion and the second protruding resin portion being made of a resin material that does not include fillers, and the sealing portion being made of a resin material including fillers. 1. A packaging structure comprising:a first substrate including a first metal terminal and a first protruding resin portion formed at a first surface of the first substrate;a second substrate including a second metal terminal and a second protruding resin portion formed at a second surface of the second substrate, the second metal terminal being made of the same kind of metal as the first metal terminal,the second substrate being provided on the first substrate such that the second surface of the second substrate faces the first surface of the first substrate; anda sealing portion filled between the first surface of the first substrate and the second surface of the second substrate,the first metal terminal and the second metal terminal being directly bonded with each other,the first protruding resin portion and the second protruding resin portion being directly bonded with each other,each of the first protruding resin portion and the second protruding resin portion being made of a resin material that does not include fillers, andthe sealing portion being made of a resin ...

Method Of Making A Sensor Package With Cooling Feature

A sensor device includes a first substrate of semiconductor material having opposing first and second surfaces, photodetectors configured to receive light impinging on the first surface, and first contact pads each exposed at both the first and second surfaces and electrically coupled to at least one of the photodetectors. A second substrate comprises opposing first and second surfaces, electrical circuits, a second contact pads each disposed at the first surface of the second substrate and electrically coupled to at least one of the electrical circuits, and a plurality of cooling channels formed as first trenches extending into the second surface of the second substrate but not reaching the first surface of the second substrate. The first substrate second surface is mounted to the second substrate first surface such that each of the first contact pads is electrically coupled to at least one of the second contact pads. 1. A method of forming a sensor device , comprising: opposing first and second surfaces,', 'a plurality of photodetectors configured to receive light impinging on the first surface, and', 'a plurality of first contact pads each extending between the first and second surfaces and electrically coupled to at least one of the plurality of photodetectors;, 'providing a first substrate of semiconductor material that comprises opposing first and second surfaces,', 'electrical circuits,', 'a plurality of second contact pads each disposed at the first surface of the second substrate and electrically coupled to at least one of the electrical circuits,, 'providing a second substrate that comprisesmounting the second surface of the first substrate to the first surface of the second substrate such that each of the first contact pads is electrically coupled to at least one of the second contact pads; andforming a plurality of cooling channels as first trenches into the second surface of the second substrate but not reaching the first surface of the second substrate ...

Semiconductor Package System and Method

A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die. 1. A semiconductor device comprising:a semiconductor die, the semiconductor die comprising a first side, a second side opposite the first side, and a first sidewall extending between the first side and the second side;a protective layer over the semiconductor die, the protective layer comprising a second sidewall;vias extending through the protective layer; andan encapsulant encapsulating the semiconductor die, the encapsulant in physical contact with the first side, the first sidewall, and a first portion of the second sidewall, wherein a second portion of the second sidewall is not in physical contact with the encapsulant.2. The semiconductor device of claim 1 , further comprising a redistribution layer in electrical connection with at least one of the vias claim 1 , the redistribution layer extending over the encapsulant.3. The semiconductor device of claim 2 , wherein the redistribution layer is in physical contact with the encapsulant.4. The semiconductor device of claim 2 , further comprising a passivation layer between the encapsulant and the redistribution layer.5. The semiconductor device of claim 2 , further comprising a through via extending through the encapsulant.6. The semiconductor device of claim 2 , further comprising a second protective layer over the redistribution layer.7. The semiconductor device of claim 6 , further comprising an underbump metallization extending through the second protective layer.814.-. (canceled)15. A method of manufacturing a semiconductor device claim 6 , the method comprising:forming a first protective ...

SEMICONDUCTOR TSV DEVICE PACKAGE FOR CIRCUIT BOARD CONNECTION

An electronic device includes a circuit board and a semiconductor device package. The semiconductor device package includes a laminate layer. The semiconductor device package includes a semiconductor die having an active side, an inactive side opposite the active side, and through-silicon vias (TSVs) conductively connecting the active side to the inactive side and conductively connecting the semiconductor die to one of the laminate layer and the circuit board. The semiconductor device package includes a laminate layer having a side attached to the active side or the inactive side semiconductor die. The semiconductor device package includes solder balls at the side of the laminate layer attached to the semiconductor die, around the semiconductor die, and attached to the circuit board. 1. A method comprising:preparing a semiconductor die having an active side, an inactive side opposite the active side, and a plurality of through-silicon vias (TSVs) conductively connecting the active side to the inactive side;attaching a laminate layer to the semiconductor die; andattaching a circuit board to the semiconductor die.2. The method of claim 1 , wherein the laminate layer is attached to the semiconductor die before the circuit board is attached to the semiconductor die claim 1 ,wherein attaching the laminate layer to the semiconductor die comprises employing a plurality of solder bumps to attach a side of the laminate layer to the active side of the semiconductor die, employing a plurality of solder balls at the side of the laminate layer attached to the semiconductor die, around the semiconductor die, to attach laminate layer to the circuit board; and', 'employing solder paste to attach the circuit board to the inactive side of the semiconductor at which the TSVs are exposed., 'and wherein attaching the circuit board to the semiconductor die includes attaching the circuit board to the laminate layer and comprises3. The method of claim 1 , wherein the laminate layer is ...

SELF-SHIELDED DIE HAVING ELECTROMAGNETIC SHIELDING ON DIE SURFACES

A self-shielded die includes a substrate, an electronic device attached to the substrate, one or more electrical pads disposed on a bottom surface of the substrate, and an electromagnetic interference (EMI) shield formed of at least one electrically conductive material and connected to ground. At least one of the one or more electrical pads is electrically connected to the electronic device. The EMI shield includes a top shield layer, disposed directly on and substantially completely covering a top surface of the substrate opposite the bottom surface of the substrate, and side shield layers substantially completely covering all sides of the substrate, extending between the top surface of the substrate and the bottom surface of the substrate. 1. A self-shielded die , comprising:a hybrid substrate comprising a base semiconductor substrate and a lid semiconductor substrate, bonded to the base semiconductor substrate;an electronic device attached to the base semiconductor substrate in a cavity pre-formed between the base and lid semiconductor substrates;one or more electrical pads disposed on a bottom surface of the base semiconductor substrate, at least one of the one or more electrical pads being electrically connected to the electronic device; andan electromagnetic interference (EMI) shield formed of at least one electrically conductive material and connected to ground, the EMI shield comprising a top shield layer, disposed directly on and substantially completely covering a top surface of the hybrid substrate opposite the bottom surface of the hybrid substrate, and side shield layers substantially completely covering all sides of the hybrid substrate, extending between the top surface of the hybrid substrate and the bottom surface of the hybrid substrate.2. The self-shielded die of claim 1 , wherein the EMI shield effectively forms a Faraday cage around the electronic device.3. The self-shielded die of claim 1 , wherein at least a portion of the at least one ...

STRUCTURES AND METHODS FOR PROVIDING ELECTRICAL ISOLATION IN SEMICONDUCTOR DEVICES

Semiconductor package structures and methods of forming the same are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon. 17-. (canceled)8. A method of forming a semiconductor structure , the method comprising:forming a plurality of semiconductor chips, each of the semiconductor chips comprising a substrate with one or more transistors or integrated circuits formed thereon;forming, on a top surface of each of the plurality of semiconductor chips, first solder bumps having a first pitch;flipping the plurality of semiconductor chips having the first solder bumps formed thereon;bonding the flipped plurality of semiconductor chips to a first side of an interposer through the first solder bumps; andbonding the interposer to a printed circuit board (PCB) or package substrate through second solder bumps disposed on a second side of the interposer, the second solder bumps having a second pitch that is greater than the first pitch.9. The method of claim 8 , wherein the flip-chip bonding of the semiconductor chips to the first side of the interposer comprises:bonding the plurality of semiconductor chips to the first side of the interposer in an arrangement that includes air gaps or insulating passivation material separating adjacent semiconductor chips, the air gaps or insulating passivation material providing electrical isolation between the adjacent chips.10. The method of claim 8 , wherein the flip-chip bonding of the semiconductor chips to the first side of the interposer ...

Packaging stacked substrates and an integrated circuit die using a lid and a stiffening structure

An electronic device disposed in a package that includes: an interposer, fan-out interconnect (FOI), and a lid. The interposer having first size and first surface upon which die terminals (DTs) are disposed and are configured to electrically couple to integrated circuit die (IC), and second surface upon which substrate terminals (STs) are disposed and are configured to electrically couple to substrate. The IC has second size smaller than the first size, and the IC is mounted on the first surface in electrical contact with the DTs, the interposer is mounted on third surface, and the package substrate has third size, larger than the first size. The FOI establishes electrical interconnection between DTs and STs, the DTs have first pitch size and the STs have second pitch size, larger than first pitch size. The lid has first section, configured to abut fourth surface, and second section, mounted on the third surface.

ELECTRONIC DEVICE MODULE AND MANUFACTURING METHOD THEREOF

An electronic device module includes a first board including a first side and a second side facing in opposite directions, the first side of the first board being configured to have a first electronic device mounted thereon; a second board adhered to the second side of the first board, and including a device accommodating portion that is a space formed by removing a central portion of the second board; a second electronic device disposed in the device accommodating portion and mounted on the second side of the first board so that the second electronic device is adjacent to an internal edge side of the second board defining a boundary of the device accommodating portion; and a bonding layer disposed in a gap between the first board and the second board and extending into a gap between the second side of the first board and the second electronic device, the bonding layer bonding the second board and the second electronic device to the first board. 1. An electronic device module comprising:a first board comprising a first side and a second side facing in opposite directions, the first side of the first board being configured to have a first electronic device mounted thereon;a second board adhered to the second side of the first board, and comprising a device accommodating portion that is a space formed by removing a central portion of the second board;a second electronic device disposed in the device accommodating portion and mounted on the second side of the first board so that the second electronic device is adjacent to an internal edge side of the second board defining a boundary of the device accommodating portion; anda bonding layer disposed in a gap between the first board and the second board and extending into a gap between the second side of the first board and the second electronic device, the bonding layer bonding the second board and the second electronic device to the first board.2. The electronic device module of claim 1 , further comprising an insulating ...

High-frequency component and high-frequency module including the same

In a method for mounting a filter circuit component to obtain desired frequency characteristics of the filter circuit component without receiving the influence of a parasitic inductance and a parasitic capacitance, and to increase the packing density of components, since the ground terminal of the filter circuit component connected to the mounting electrode is connected to the ground electrode through the via conductors at the shortest distance, the occurrence of an unnecessary parasitic inductance and an unnecessary parasitic capacitance is prevented. The filter circuit component is mounted on the high-frequency component to obtain the desired frequency characteristics of the filter circuit component without the influence of a parasitic inductance and a parasitic capacitance. Since the component is located in a space surrounded by the inner peripheral surface of the supporting frame body, the packing density of components is increased.

Component Carrier With a Bypass Capacitance Comprising Dielectric Film Structure

There is provided a component carrier comprising: (a) a stack of at least one electrically conductive layer structure and at least one electrically insulating layer structure; and (b) a bypass capacitance structure formed on an/or within the stack. The bypass capacitance structure comprises an electrically conductive film structure having a rough surface, a dielectric film structure formed on the rough surface, and a further electrically conductive film structure formed on the dielectric film structure. 4. The component carrier as set forth in claim 1 , wherein the dielectric film structure comprises a thickness which is in the range between 10 nm and 2000 nm claim 1 , in particular lower than 1000 nm.5. The component carrier as set forth in claim 1 , wherein the dielectric film structure comprises a material having a dielectric constant which is in the range between 3 and 1000.6. The component carrier as set forth in claim 1 , wherein the dielectric film structure comprises a material selected from a group consisting of diamond-like carbon claim 1 , aluminum oxide claim 1 , silicon nitride claim 1 , silicon oxide claim 1 , neodymium oxide claim 1 , hafnium oxide claim 1 , zirconium oxide claim 1 , or a combination of these materials. This application claims the benefit of the filing date of Chinese Patent Application No. 2016106190757 filed 29 Jul. 2016, the disclosure of which is hereby incorporated herein by reference.Embodiments of the invention generally relate to the technical field of component carriers onto which electronic components can be placed in order to form an electronic assembly. In particular, embodiments of the invention relate to a component carrier comprising a bypass capacitor.High-speed digital circuits typically present serious challenges related to the design of a power supply. For example, numerous logic gates are rapidly turned on and off and short surges of current are continuously drawn from an electrically conductive layer being ...

WAFER-SCALE POWER DELIVERY

A method is provided to supply power to wafer-scale ICs. The method includes receiving a wafer containing ICs placed on the top of the wafer. The wafer has through-silicon vias to provide power from the bottom to the ICs. The method also includes a printed circuit board, which has power rails in a pattern on the top of the printed circuit board, where the rails provide voltage and ground. The method continues with placing metal solder spheres between the bottom of the wafer and the top of the printed circuit board, where the spheres provide connections between the two, and where the spheres are free to move and operate as mechanical springs to resist clamping forces. The method also includes applying clamping pressure to the structure to establish connections by compressing the spheres, where no soldering is required. 1. A method of fabricating a logic/wiring assembly , the method comprising:receiving a printed circuit board that includes a plurality of power rails;receiving a lower silicon-based wafer including an integrated circuit formed thereon;arranging a first plurality of electrically conductive solder spheres, with a predetermined size and pitch, between a bottom surface of the lower silicon-based wafer and a top surface of the printed circuit board such that first plurality of electrically conductive solder spheres are free to move and operate as mechanical springs to resist clamping forces; andapplying clamping force to the structure to establish electrical connections between the wafer and the printed circuit board by compressing the plurality of electrically conductive solder spheres such that no metallurgical bonding or soldering is required,wherein the first plurality of electrically conductive solder spheres establish electrical connections between the wafer and the printed circuit board while the lower silicon-based wafer excludes an organic laminate layer.2. The method of claim 1 , further comprising:receiving an upper silicon-based wafer including ...

ANTENNA MODULE AND METHOD OF MANUFACTURING THE SAME

An antenna module includes: an integrated circuit (IC) configured to generate a radio frequency (RF) signal; and a substrate including an antenna portion providing a first surface of the substrate, and a circuit pattern portion providing a second surface of the substrate. The antenna portion includes first antenna members configured to transmit the RF signal, cavities corresponding to the first antenna members, through vias respectively disposed in the cavities and respectively electrically connected to the first antenna members, and a plating member disposed in at least one cavity among the cavities. The circuit pattern portion includes a circuit pattern and an insulating layer forming, for each of the through vias, an electrical connection path to the IC. 1. An antenna module , comprising:an integrated circuit (IC) configured to generate a radio frequency (RF) signal; and wherein the antenna portion comprises first antenna members configured to transmit the RF signal, cavities corresponding to the first antenna members, through vias respectively disposed in the cavities and respectively electrically connected to the first antenna members, and a plating member disposed in at least one cavity among the cavities, and', 'wherein the circuit pattern portion comprises a circuit pattern and an insulating layer forming, for each of the through vias, an electrical connection path to the IC., 'a substrate comprising an antenna portion providing a first surface of the substrate, and a circuit pattern portion providing a second surface of the substrate,'}2. The antenna module of claim 1 , whereinthe antenna portion further comprises an insulating member at least partially two-dimensionally surrounding each of the cavities, anda thickness of the insulating member is greater than a thickness of the insulating layer.3. The antenna module of claim 2 , wherein the through vias form linear connections between the circuit pattern portion and corresponding first antenna members among ...

Radio frequency module and communication device

A radio frequency module includes: a multilayer substrate that includes a plurality of insulator layers; an amplifying circuit that is provided on the multilayer substrate and amplifies a radio frequency signal; a power supply circuit that is provided on the multilayer substrate and supplies power to the amplifying circuit; a ground conductor that is a first conductor pattern having a ground potential and used in the amplifying circuit; and a ground conductor that is a second conductor pattern having a ground potential and used in the power supply circuit. The ground conductors are physically separated from each other and provided in internal layers of the multilayer substrate.

ELECTRONIC DEVICE

According to one embodiment, the interconnect layer includes a fourth conductive member and a fifth conductive member. The fourth conductive member is provided between the first region of the first chip and the third region of the second chip. The fourth conductive member connects the first conductive member of the first chip and the second conductive member of the second chip. The fifth conductive member is provided between the second region of the first chip and the fifth region of the third chip. The fifth conductive member connects the first conductive member of the first chip and the third conductive member of the third chip. The first chip is provided between the first terminal and the second terminal. 118.-. (canceled)19. An electronic device , comprising:two or more first chips, each first chip including a interconnect member; andthree or more chips including at least one second chip and at least one third chip, the second chip including a second conductive member, the third chip including a third conductive member,the second conductive member of the second chip being electrically connected to the third conductive member of the third chip via the interconnect member of one first chip.20. The device according to claim 19 , wherein the first chip includes a memory element.21. The device according to claim 19 , wherein the second chip includes a logic element.22. The device according to claim 19 , wherein the third chip includes a memory element.23. The device according to claim 19 , wherein the second chip includes a logic element claim 19 , and the third chip includes a memory element.24. The device according to claim 19 , further comprising a resin portion covering the second chip and the third chip.25. The device according to claim 19 , further comprising an interconnect layer provided between the first chip and the second chip claim 19 , and between the first chip and the third chip claim 19 , the interconnect layer being electrically connected to the ...

Package structure and antenna device using the same

An antenna device is provided. The antenna device includes a first substrate and a second substrate facing the first substrate. The first substrate includes an inner surface and an outer surface opposite the inner surface of the first substrate. The second substrate includes an inner surface and an outer surface opposite the inner surface of the second substrate. The antenna device also includes a die disposed between the first substrate and the second substrate, a redistribution layer disposed between the die and the inner surface of the second substrate, and an antenna unit electrically connected to the die via the redistribution layer. The antenna unit is arranged on at least one of the inner surface of the first substrate, the outer surface of the first substrate, the inner surface of the second substrate and the outer surface of the second substrate.

Semiconductor device package and method for manufacturing the same

A semiconductor device package includes a conductive layer, a first conductive pillar, a circuit layer and a second conductive pillar. The conductive layer has a first surface. The first conductive pillar is disposed on the first surface of the conductive layer. The circuit layer is disposed over the conductive layer. The circuit layer has a first surface facing the conductive layer. The second conductive pillar is disposed on the first surface of the circuit layer. The first conductive pillar is physically spaced apart from the second conductive pillar and electrically connected to the second conductive pillar.

Semiconductor package

A semiconductor package includes a substrate, a semiconductor die, a dummy die, a conductive layer, at least one first conductive wire, and at least one second conductive wire. The semiconductor die is disposed on the substrate. The dummy die is disposed on the semiconductor die. The conductive layer is disposed on the dummy die. The first conductive wire electrically connects the semiconductor die to a signal source. The second conductive wire electrically connects the conductive layer to a ground reference.

PACKAGE STRUCTURE

A package structure includes a redistribution layer having an upper surface and a lower surface opposite to each other, in which the redistribution layer has at least one recess on its lower surface, an electronic element disposed on the upper surface of the redistribution layer, at least one first conductive ball disposed on the at least one recess of the redistribution layer, in which a portion of the at least one first conductive ball is filled into the at least one recess, and a plurality of second conductive balls disposed on the lower surface of the redistribution layer. The height of the first conductive ball is larger than the height of each of the second conductive balls in a direction perpendicular to the lower surface of the redistribution layer. 1. A package structure , comprising:a redistribution layer comprising an upper surface and a lower surface opposite to each other, wherein the lower surface of the redistribution layer has at least one first recess;an electronic element disposed on the upper surface of the redistribution layer;at least one first conductive ball disposed on the at least one first recess of the redistribution layer, wherein a part of the at least one first conductive ball is filled into the at least one first recess; anda plurality of second conductive balls disposed on the lower surface of the redistribution layer;wherein in a direction perpendicular to the lower surface of the redistribution layer, a height of the at least one first conductive ball is larger than a height of each of the second conductive balls.2. The package structure of claim 1 , wherein the electronic element comprises a chip.3. The package structure of claim 1 , wherein the at least one first recess is disposed along an edge of the electronic element in the direction.4. The package structure of claim 3 , wherein the at least one first recess is overlapped with the edge of the electronic element in the direction.5. The package structure of claim 3 , wherein the ...

ANTENNA MODULE AND ELECTRONIC SYSTEM INCLUDING THE SAME

An antenna module includes an antenna substrate, a fan-out package and first electrical connection structures. The antenna substrate includes a pattern layer including antenna and ground patterns, and a feeding layer under the pattern layer including a feeding network that supplies power to the antenna patterns. The fan-out package is under the antenna substrate and includes a semiconductor chip driving the antenna substrate, an encapsulant encapsulating some of the semiconductor chip, a first redistribution layer on the semiconductor chip electrically connecting the semiconductor chip with the antenna substrate, and a second redistribution layer under the semiconductor chip electrically connecting the semiconductor chip with external devices. The first electrical connection structures are between and electrically connect the antenna substrate and the fan-out package. A logic layer including logic patterns electrically connecting the pattern layer with the feeding layer in the antenna substrate in the first redistribution layer in the fan-out package. 1. An antenna module comprising: a pattern layer including a plurality of antenna patterns and a plurality of ground patterns; and', 'a feeding layer under the pattern layer and including a feeding network configured to supply power to the plurality of antenna patterns;, 'an antenna substrate comprising'} a semiconductor chip configured to drive the antenna substrate;', 'an encapsulant encapsulating at least portions of the semiconductor chip;', 'a first redistribution layer on the semiconductor chip and electrically connecting the semiconductor chip with the antenna substrate; and', 'a second redistribution layer under the semiconductor chip and electrically connecting the semiconductor chip with an external printed circuit board; and, 'a fan-out package under the antenna substrate, the fan-out package comprising'}a plurality of first electrical connection structures between the antenna substrate and the fan-out ...

ELECTRONIC PACKAGE AND METHOD OF FABRICATING THE SAME

A met of fabricating an electronic package is provided, g: providing a carrier body haying a first surface formed with a plurality of recessed portions, and a second surface opposing the first surface and interconnecting with the recessed portions; forming on the first surface of the carrier body an electronic structure that has a plurality of conductive elements received in the recessed portions correspondingly; and removing a portion of the carrier body, with the conductive elements exposed from the second surface of the carrier body. Therefore, the carrier body is retained, and the fabrication cost is reduced since no temporary material is required. The present invention further provides the electronic package thus fabricated. 1. An electronic package , comprising:a carrier body having a first surface formed with a plurality of recessed portions, and a second surface opposing the first surface and interconnecting with the recessed portions;an electronic structure formed on the first surface of the carrier body; and{'sup': '-', 'a plurality of conductive elements formed on the electronic structure, received in the recessed portions conespondingly, and exposed from the second surface of the carrier body.'}2. The electronic package of claim 1 , wherein the carrier body is a semiconductor board.3. The electronic package of claim 1 , wherein the electronic structure comprises at least one interposer having the conductive elements and an electronic element formed on the interposer.4. The electronic package of claim 3 , wherein the electronic structure further comprises an insulating layer that encapsulates the interposer and the electronic element.5. The electronic package of claim 1 , wherein the conductive elements are secured to the recessed portions via a bonding material.6. The electronic package of claim 1 , wherein the conductive elements have surfaces flush with the second surface of the carrier body.7. The electronic package of claim 1 , further comprising a ...