ИНТЕГРИРОВАННАЯ ОБРАБОТКА И ГЕНЕРИРОВАНИЕ ЭЛЕКТРОЭНЕРГИИ НА КРИСТАЛЛЕ

Изобретение относится к области электротехники, а именно к обрабатывающему устройству с собственным источником питания, и содержит обрабатывающее устройство и электрический генератор, которые имеют физическую, электрическую и тепловую связь между собой. Электрический генератор представляет собой топливный элемент, который может быть изготовлен из материалов на основе кремния, способных также поддерживать функционирование схем обработки. Тепловая связь между электрическим генератором и обрабатывающим устройством может включать в себя термоэлектрик, который генерирует электрическую энергию на основе разности температур или потребляет электрическую энергию для создания разности температур. Тепловая связь между электрическим генератором и обрабатывающим устройством содержит тепловую связь между топливом, доставляемым электрическому генератору. Вычислительное устройство с обрабатывающими устройствами с собственным источником питания также включает в себя устройство аккумулирования энергии для ...

МНОЖЕСТВО ЭЛЕМЕНТОВ ПИТАНИЯ В УСТРОЙСТВАХ С НАЛОЖЕННЫМИ ДРУГ НА ДРУГА ИНТЕГРИРОВАННЫМИ КОМПОНЕНТАМИ

Изобретение относится к офтальмологическому устройству, такому как контактная линза. В настоящем изобретении предложено устройство с наложенными друг на друга интегрированными компонентами с множеством элементов питания, содержащее первый слой, содержащий первую поверхность, и второй слой, содержащий вторую поверхность, причем по меньшей мере часть первой поверхности лежит поверх по меньшей мере части второй поверхности, по меньшей мере одно электрическое соединение между электрическим контактом на первой поверхности и электрическим контактом на второй поверхности, по меньшей мере один электрический транзистор, причем электрический транзистор(ы) содержится внутри устройства с наложенными друг на друга интегрированными компонентами, по меньшей мере первый и второй отдельные элементы питания, причем отдельные элементы питания содержатся в любом или обоих из первого и второго слоев, и схему внутренней диагностики, содержащую сенсорный элемент, выполненный с возможностью обнаруживать ток, протекающий ...

Semiconductor module, has bonding wire bonded at load terminal and connected with upper contact piece, and explosion protection unit arranged between load terminals and upper contact piece and embedded in bonding wire at specific length

The module (100) has an electrically conductive lower contact piece (31) and an electrically conductive upper contact piece (32) spaced in a vertical direction (v). Multiple semiconductor chips comprise load terminals. One of the load terminals is electrical conductively connected with the lower contact piece. A bonding wire (4) is bonded at the load terminal and connected with the upper contact piece. An explosion protection unit is arranged between the load terminals and the upper contact piece and embedded in the bonding wire over 80% or 90% of length. The semiconductor chips are designed as unipolar and bipolar transistors such as IGBTs and MOSFETs. The bonding wire is designed as a flat small strip.

Bauelement mit empfindlichen Bauelementstrukturen und Verfahren zur Herstellung

Elektrisches Bauelement,- mit einem Substrat, das ein Material mit pyroelektrischen oder piezoelektrischen Eigenschaften umfasst- mit auf der Oberfläche des Substrats angeordneten elektrischen Leiterbahnen (LB) und zumindest drei elektrisch leitenden Bauelementstrukturen (BS1, BS2, BS3), die gegenüber einer Spannung empfindlich oder durch einen elektrischen Überschlag gefährdet sind,- bei dem in einer Vorstufe des Bauelements die zumindest drei Bauelementstrukturen (BS1, BS2, BS3) jeweils über zumindest eine der elektrischen Leiterbahnen (LB) mit einer von zumindest drei elektrischen Anschlussflächen (AF1, AF2, AF3), die von außen zugänglich sind, verbunden sind- bei dem je zwei der Anschlussflächen mittels einer der zumindest zwei Shuntleitungen (SL1, SL2) kurzgeschlossen sind, wobei jede der zumindest zwei Shuntleitungen (SLi, SL2) mindestens einen Abschnitt mit verringertem Querschnitt gegenüber den elektrischen Leiterbahnen aufweist.

Nichtlinearer Widerstand

Halbleitervorrichtung

Zuverlässige physikalisch nicht klonbare Funktion für die Berechtigungsprüfung einer Einheit

Die vorliegende Offenbarung bezieht sich auf eine sichere Einheit mit einer physikalisch nicht klonbaren Funktion sowie auf Verfahren zum Herstellen einer derartigen sicheren Einheit. Die Einheit beinhaltet ein Substrat und wenigstens eine High-k/Metall-Gate-Einheit, die auf dem Substrat ausgebildet ist. Die wenigstens eine High-k/Metall-Gate-Einheit repräsentiert die physikalisch nicht klonbare Funktion. In einigen Fällen kann die wenigstens eine High-k/Metall-Gate-Einheit einer Variabilitäts-Verbesserung unterworfen werden. In einigen Fällen kann die sichere Einheit einen Messkreis zum Messen einer Eigenschaft der wenigstens einen High-k/Metall-Gate-Einheit beinhalten.

Integrierte Schaltung mit im Wesentlichen durch das Substrat verlaufenden Isolationsbereichen

... raben-Isolationsbereiche enthält. Das Substrat trägt eine Vorrichtung. Die Graben-Isolationsbereiche sind konfiguriert, um die Vorrichtung seitlich zu isolieren. Die Graben-Isolationsbereiche erstrecken sich im Wesentlichen durch das Substrat.

ZELLMONTIERTE MONOLITHISCHE INTEGRIERTE SCHALTUNG

Diese Offenbarung stellt eine zellmontierte monolithische integrierte Schaltung bereit. Ein Batteriesystem weist Folgendes auf: eine Batteriezelle, die einen Becher beinhaltet, und ein keramisches Substrat, das eine gemusterte metallisierte Fläche beinhaltet und über einen wärmeleitfähigen Klebstoff an dem Becher montiert ist. Das Batteriesystem weist zudem eine monolithische integrierte Schaltung auf, die Daten über die Zelle misst und überträgt und derart an der gemusterten metallisierten Fläche montiert ist, dass das keramische Substrat und die monolithische integrierte Schaltung elektrisch voneinander isoliert sind.

Field plates on two opposed surfaces of double-based bidirectional bipolar transisstor:devices, methods, and systems

Bicmos process for counter doped collecter

In a BICMOS circuit the bipolar transistor base region is formed in an n-type well serving as the collector of the transistor. Boron ions are implanted at two different energy levels to form the base region (26) and to counter dope the well to form a region (34) below the base region which is more lightly doped than the remainder of the well. The ion implantation counter doping the well may comprise two energy levels. Such counter doping reduces the electric field at the collector base junction and reduces collector base capacitance. ...

Ultra high speed signal transmission/reception

An interconnect for transmitting an electric signal between electronic devices includes a first coupling element electromagnetically coupled to, and immediately juxtaposed to, a second coupling element The first coupling element is mounted on and is electrically connected to a first electronic device having a first integrated circuit. The second coupling element may be mounted on and electrically connected to the first electronic device, and electrically connected to an interconnect n a second electronic device, or the second coupling element may be mounted on and electrically connected to the second electronic device.

Leakage measurement of through silicon vias

A leakage measurement structure for through substrate vias which includes a semiconductor substrate; a plurality of through substrate vias in the semiconductor substrate extending substantially through the semiconductor substrate; and a leakage measurement structure located in the semiconductor substrate. The leakage measurement structure includes a plurality of substrate contacts extending into the semiconductor substrate; a plurality of sensing circuits connected to the plurality of through substrate vias and to the plurality of the substrate contacts, the plurality of sensing circuits providing a plurality of outputs indicative of current leakage from the plurality of through substrate vias; a built-in self test (BIST) engine to step through testing of the plurality of through substrate vias; and a memory coupled to the BIST engine to receive the outputs from the plurality of sensing circuits. Also included is a method of testing a semiconductor substrate.

A process for dyeing polyolefine or polyvinylidene chloride filaments

Polyolefine or polyvinylidene chloride filaments are dyed with a monoazo dyestuff, the aromatic nucleus or nuclei of which is or are substituted by one or more straight- or branched-aliphatic side-chains with at least seven carbon atoms. The dye may be applied from aqueous suspension, or may be produced in situ by applying, separately and successively, the diazotized amine and the coupling component and then effecting coupling on the fibre. The dyestuffs employed in the examples are: (1) p-cetyl-aniline --> p-nonyl phenol, formed on the fibre; (2) p-amino-octyl-benzene --> b -naphthol, applied from aqueous suspension; (3) p-cetyl-aniline --> p-cetyl-phenol, applied from aqueous suspension; and (4) p-octadecyl-aniline --> b -naphthol, applied from aqueous suspension.

CIRCUIT TO THE PROTECTION OF POWER SEMICONDUCTORS AGAINST OVER HEAD ENDINGS

SEMICONDUCTOR DEVICE WITH GAS CELL AND PROCEDURE FOR YOUR PRODUCTION

Methods and apparatus to form electronic circuitry on ophthalmic devices

This invention discloses an energized Ophthalmic Device with incorporated low energy consuming modes. In some embodiments, media inserts with incorporated low energy consuming modes are described.

Method and apparatus for integrated-battery devices

A thin multichip module

PLANAR STRUCTURE FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES WITH GAPS IN GLASSY LAYER OVER HIGH FIELD REGIONS

IR-699 PLANAR STRUCTURE FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES WITH GAPS IN GLASSY LAYER OVER HIGH FIELD REGIONS Two gaps are placed in the reflowed phosphorusdoped silicon-dioxide material overcoating of a planar high voltage semiconductor device to prevent polarization of the reflowed silox. The invention is applicable to any device using a polarizable glassy coating which will be exposed to a high electric field extending along its surface and is shown applied to a high voltage diode, a high voltage MOSFET and a high voltage TRIMOS-type device which is a semiconductor switching device using spaced MOS transistors having a common drain region.

AN ARRANGEMENT RELATED TO A GAS SENSOR

The present invention concerns a gas-sensor related arrangement ("A") and more specifically an arrangement which, for its function, utilizes a first (1) light-generating means, a second (2) light-receiving means, and a third (3) means for forming and defining an optical measuring distance between said first and second means through a gas sample, as well as a control unit (20, 123), with associated calculating circuits (30, 125). More specifically, a unit ("E1 ") is to be allotted to a plurality of first electric connector devices or means (4, 4a, 4b), said connector devices being adapted and distributed along a first surface portion (5) of said unit for an electric connecting possibility to other electric connector devices or means ((4), (4a), (4b)) related to a carrier ("B1 "), such as a printed circuit card or board, for said unit. Said first (1) and second (2) means are to be closely related to each other within a "discrete unit" ("EI ") as a first (1a) and a second (2a) surface section ...

Verfahren zum Bestimmen von mechanischen Spannungswerten an Werkstoffen.

Dreiachsiges Lenkgestell für Fahrzeuge, insbesondere für Strassenbahnwagen.

Kristalldetektor für hochfrequente Schwingungen.

Elément redresseur

Laufzeitröhre mit wenigstens einem toroidförmigen Hohlraumresonator.

Elektrischer Kondensator und Verfahren zu dessen Herstellung.

Halbleiteranordnung und Verfahren zur Herstellung derselben

Verfahren zur Herstellung einer mehrlagigen mikroelektronischen Schaltung

Transistor

Steuerbare Halbleiteranordnung

Procédé de fabrication d'un composant semiconducteur

Steuerbare bistabile Halbleiteranordnung

Halbleiterbauelement

Transistor

Thyristor

Halbleiter-Schalteinrichtung

Thyristor

BATTERY-SUPPORTED INTEGRATED LOGIC ELEMENT.

SEMICONDUCTOR COMPONENT FOR HIGH TENSION.

Electronic circuit and camera

SEMICONDUCTOR DEVICES

Assembly of transistor

Device of semiconductors réglabels

Dispositif pour protéger les semi-conducteurs de puissance contre les amorçages gâchette en l'air.

Dispositif pour protéger les semi-conducteurs de puissance contre les amorçages gâchette en l'air. Un condensateur C et au besoin une résistance R sont montés entre un point de raccordement A, situé en amont du semi-conducteur de puissance Tc dans le sens du passage du courant, du circuit de courant de charge, et la gâchette S du semi-conducteur de puissance.

LIKE STRUCTURE FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES

Compensating network of temperature for semiconductor

Semiconductor Memory Apparatus

PACKAGE TREATMENT APPARATUS

DEVICE FOR MANUFACTURING SUBSTRATE AND CONTROL MODULE USED FOR SAME

The present invention provides a device for manufacturing a substrate capable of flexibly changing a communication method without replacement of a control module at once and an input/output control module and a communication control module used for the same. The device comprises: a host computer; manufacturing equipment monitored by the host computer; and the control module connected between the manufacturing equipment and the host computer. The control module includes: the input/output control module connected to the manufacturing equipment, and controlling an input/output signal of the manufacturing equipment; and the communication control module which is connected between the input/output control module and the host computer, and is detached from the input/output control module when network communication of the host computer changes. COPYRIGHT KIPO 2017 ...

CARRIER FOR A TEST CAPABLE OF SECURING THE POSITION ACCURACY OF A TERMINAL

PURPOSE: A carrier for a test is provided to prevent a contact failure by preventing a base film from being located on the outer side of an electronic component. CONSTITUTION: A carrier for a test includes a base film(40) and a cover film(70). The base film includes a bump(44) in contact with an electrode of a die(90). The cover film overlaps with the base film. The die is received between the base film and the cover film. The base film includes a first region(40a) with a first thickness and a second region(40b) with a second thickness. The second thickness is thinner than the first thickness. The second region faces a part of an edge(92) of the die. COPYRIGHT KIPO 2013 ...

ENERGIZED OPHTHALMIC LENS INCLUDING STACKED INTEGRATED COMPONENTS

Styrbar halvledaranordning av PNPN-typ

Integrated circuit, double seal ring for integrated circuit and manufacturing method thereof

Chip scale ball grid array for integrated circuit package

A chip scale ball grid array for integrated circuit packaging having a nonpolymer layer or support structure positioned between a semiconductor die and a substrate. The nonpolymer support structure acts to increase circuit reliability by reducing thermal stress effects and/or by reducing or eliminating formation of voids in an integrated circuit package. A nonpolymer support structure may be a material, such as copper foil, having sufficient rigidity to allow processing of chip scale package in strip format.

METHOD FOR PRODUCING ELECTRONIC COMPONENT, ELECTRONIC COMPONENT, AND CHIP ASSEMBLY

The present invention has: a cutting step (step S11) for obtaining a pre-pattern-formation chip (10) by cutting a wafer (1); and a polishing step (step S12) for collecting the plurality of obtained chips (10) and barrel polishing the cut surface (10A) of each chip. The present invention further has an arranging step (step S13) for arranging each of the polished plurality of chips (10B) in a manner so that the obverse (10C) of each of the chips (10B) faces upwards (M1). The present invention further has an adhering step (step S14) for forming a chip assembly (20) by adhering the cut surfaces (10A) of the arranged chips (10B) together by means of an adhesive (30). The present invention has: a pattern forming step (step S16) for forming a circuit pattern (15) on each chip (10B) of the chip assembly (20); and a melting step (step S17) for melting the adhesive (30) of the chip assembly (20) to break apart the post-pattern-formation chips (10E).

BATTERY-MOUNTED INTEGRATED CIRCUIT DEVICE

A battery-mounted integrated circuit device is disclosed wherein an integrated circuit and a solid battery are formed on the same substrate. In this battery-mounted integrated circuit device, a first diffusion layer containing N-type impurities is formed in the semiconductor substrate in a region lying between the region where the solid battery is mounted and the region where the integrated circuit is mounted, and a second diffusion layer containing N-type impurities is formed in the semiconductor substrate in a region below the region where the solid battery is mounted. The first diffusion layer and the second diffusion layer overlap each other.

Package alignment structure and method of forming same

An embodiment is a semiconductor device comprising a first bond pad on a first substrate, the first bond pad having a first center line through a center of the first bond pad and orthogonal to a top surface of the first substrate, and a first conductive connector on a second substrate, the first conductive connector having a second center line through a center of the first conductive connector and orthogonal to a top surface of the second substrate, the second substrate over the first substrate with the top surface of the first substrate facing the top surface of the second substrate. The semiconductor device further comprises a first alignment component adjacent the first bond pad on the first substrate, the first alignment component configured to align the first center line with the second center line.

Semiconductor device and method for manufacturing the same

In manufacturing a semiconductor memory, a gate oxide film, a polysilicon film and a WSi film are laminated on the major surface of a semiconductor wafer corresponding to both an element region on which a semiconductor chip is to be formed and a dicing region serving as a dicing line. These laminated films are patterned to form a projected dummy pattern having substantially the same wiring structure as that of a gate electrode portion of a selective transistor. The dummy pattern is formed between element isolation regions along a dicing direction at the same time when the gate electrode portion is formed. The dummy pattern prevents stress caused by dicing from being concentrated on an insulation film in the dicing region, thereby minimizing a crack waste. Consequently, in the semiconductor memory, a malfunction due to a large crack waste caused by the dicing, can be avoided.

Micro- or nano-electronic component comprising a power source and means for protecting the power source

The component comprises a sealed cavity wherein the unprotected power source formed by a micro-battery or a micro-supercapacitance is deposited. Any penetration of the ambient atmosphere into the sealed cavity causes destruction of the power source by oxidation, thereby making the component inoperative. The cavity can be in a vacuum or filled with an inert gas. A pressure sensor can be fitted inside the cavity and detect a pressure variation inside the cavity to make the component inoperative when the pressure variation exceeds a predetermined threshold. The cavity can be closed by a cover or filled with a filling material consisting of silicone resin, thermosetting resin, polymer, epoxy, fusible glass or a metal chosen from indium, tin, lead or alloys thereof.

Method and apparatus for thin-film battery having ultra-thin electrolyte

A method and system for fabricating solid-state energy-storage devices including fabrication films for devices without an anneal step. A film of an energy-storage device is fabricated by depositing a first material layer to a location on a substrate. Energy is supplied directly to the material forming the film. The energy can be in the form of energized ions of a second material. Supplying energy directly to the material and/or the film being deposited assists in controlling the growth and stoichiometry of the film. The method allows for the fabrication of ultrathin films such as electrolyte films and dielectric films.

WAFER SUBSTRATE REMOVAL

A semiconductor device is formed on a semiconductor substrate, including a primary portion of the substrate. An active component of the semiconductor device is disposed in the primary portion of the substrate. An interconnect region is formed on a top surface of the substrate. Semiconductor material is removed from the substrate in an isolation region, which is separate from the primary portion of the substrate; the isolation region extends from the top surface of the substrate to a bottom surface of the substrate. A dielectric replacement material is formed in the isolation region. The semiconductor device further includes an isolated component which is not disposed in the primary portion of the substrate. The dielectric replacement material in the isolation region separates the isolated component from the primary portion of the substrate.

MODULE

A module includes a substrate having a main surface, a first component mounted on the main surface, and two or more wires bonded to the main surface so as to straddle the first component. Each of the two or more wires has a first end and a second end. When attention is paid to two wires adjacent to each other out of the two or more wires, a distance between the first ends of the two wires is shorter than a distance between the second ends of the two wires.

Continuous processing of thin-film batteries and like devices

A system for making a thin-film device includes a substrate-supply station that supplies a substrate having a major surface area. The substrate has a first layer on a first surface area of the substrate's major surface area. Also included is a device for depositing a second layer onto the first layer, wherein the device supplies energy to the second layer to aid in layer formation without substantially heating the substrate.

Flexible semiconductor package and method for fabricating the same

A flexible semiconductor package includes a flexible substrate. A data chip is disposed over the flexible substrate. The data chip includes a data storage unit for storing data and first bonding pads that are electrically connected to the data storage unit. A control chip is disposed over the flexible substrate. The control chip includes a data processing unit for processing the data in the data chip and second bonding pads that are electrically connected to the data processing unit. Wirings are formed in order to electrically connect the first bonding pads to the second bonding pads.

High density ball grid array (BGA) package capacitor design

A circuit package is provided that includes a substrate having a first side and a second side, an integrated circuit component coupled to the second side of the substrate, and a ball grid array formed on the first side of the substrate, the ball grid array including multiple contact balls arranged in a pattern. Each of a first subset of the contact balls is electrically coupled to a first voltage input of an integrated circuit component, and each of a second subset of the contact balls is electrically coupled to a second voltage input of the integrated circuit component. The package also includes a capacitor mounted to the first side and having a first terminal coupled to a first contact ball in the first subset of the contact balls and a second terminal coupled to a second contact ball in the second subset of the contact balls.

Methods of and apparatuses for measuring electrical parameters of a plasma process

A sensor apparatus for measuring a plasma process parameter for processing a workpiece. The sensor apparatus includes a base, an information processor supported on or in the base, and at least one sensor supported on or in the base. The at least one sensor includes at least one sensing element configured for measuring an electrical property of a plasma and may include a transducer coupled to the at least one sensing element. The transducer can be configured to receive a signal from the sensing element and convert the signal into a second signal for input to the information processor.

Electronic device comprising an electronic chip provided with an optical cable

A carrier substrate includes a first network of electrical connections and recess. An electronic chip is mounted to the carrier substrate within the recess. The electronic chip includes an integrated guide of optical waves and a second network of electrical connections. A end section of an elongate optical cable is mounted on one side of the electronic chip with a longitudinal guide of optical waves optically coupled to the integrated guide of optical waves. Electrical connection elements are interposed between a face of the electronic chip and a bottom wall of the recess, such that first connect pads of the first electrical connection network are connected to second connect pads of the second electrical connection network through the electrical connection elements.

Semiconductor device having a multilayer wiring structure

A semiconductor device having a plurality of first wirings (X-direction) which include a first power supply line and a second power supply line, a plurality of third wirings (X-direction) which include a third (fourth) power supply line that is located above the first (second) power supply line and is electrically connected to the first (second) power supply line. The semiconductor device also has a plurality of second wirings (Y-direction) that include a first (second) connection wiring located above the first (second) power supply line and below the third (fourth) power supply line that is electrically connected to the first (second) power supply line and to the third (fourth) power supply line.

ASSEMBLY ARCHITECTURE EMPLOYING ORGANIC SUPPORT FOR COMPACT AND IMPROVED ASSEMBLY THROUGHPUT

An apparatus including a substrate including a first side and an opposite second side; at least one first circuit device on the first side of the substrate, at least one second device on the second side of the substrate; and a support on the second side of the substrate, the support including interconnections connected to the at least one first and second circuit device, the support having a thickness dimension operable to define a dimension from the substrate greater than a thickness dimension of the at least one second circuit device. A method including disposing at least one first circuit component on a first side of a substrate; disposing at least one second circuit component on a second side of the substrate; and coupling a support to the substrate, the substrate defining a dimension from the substrate greater than a thickness dimension of the at least one second circuit component.

THIN FILM BATTERY ON AN INTEGRATED CIRCUIT OR CIRCUIT BOARD AND METHOD THEREOF

ОФТАЛЬМОЛОГИЧЕСКОЕ УСТРОЙСТВО С ТОНКОПЛЕНОЧНЫМИ НАНОКРИСТАЛЛИЧЕСКИМИ ИНТЕГРАЛЬНЫМИ ЦЕПЯМИ НА ОФТАЛЬМОЛОГИЧЕСКИХ УСТРОЙСТВАХ

Изобретение относится к офтальмологическому устройству, которое содержит первый вкладыш-субстрат, содержащий активное оптическое устройство, первый тонкопленочный нанокристаллический транзистор, первый элемент питания и первую проводящую дорожку, причем первый тонкопленочный нанокристаллический транзистор содержит нанокристаллический слой n-типа, первый элемент питания расположен вблизи первой проводящей дорожки так, что первый элемент питания находится в электрическом соединении с первым тонкопленочным нанокристаллическим транзистором, активное оптическое устройство содержит жидкостный менисковый линзовый элемент, содержащий две несмешивающиеся текучие среды с образованием мениска между ними, причем активное оптическое устройство находится в электрическом соединении с первым элементом питания и первым тонкопленочным нанокристаллическим транзистором, а активное оптическое устройство выполнено с возможностью изменения фокусных характеристик офтальмологического устройства при приложении электрического ...

ЭЛЕКТРОННЫЙ КОМПОНЕНТ И ЭЛЕКТРОННОЕ УСТРОЙСТВО

... 1. Электронный компонент, содержащий:электронное устройство, при этом плоскость, которая расположена между передней поверхностью и задней поверхностью электронного устройства и продолжается через боковую поверхность электронного устройства, но не продолжается через переднюю поверхность или заднюю поверхность, определена как базовая плоскость;основной элемент, который предусмотрен со стороны задней поверхности от базовой плоскости и к которому электронное устройство прикреплено связующим материалом;покрывающий элемент, который предусмотрен со стороны передней поверхности от базовой плоскости и который перекрывает электронное устройство в направлении, перпендикулярном к базовой плоскости;внешний вывод, который предусмотрен со стороны задней поверхности от базовой плоскости и который перекрывает основной элемент в направлении, перпендикулярном к базовой плоскости, причем внешний вывод электрически соединен с электродом электронного устройства через внутренний вывод;ферромагнитный элемент, ...

ПОЛНЫЕ КОЛЬЦА ДЛЯ ФУНКЦИОНАЛИЗИРОВАННОЙ МНОГОСЛОЙНОЙ ВСТАВКИ В ОФТАЛЬМОЛОГИЧЕСКОЙ ЛИНЗЕ

... 1. Активная вставка в линзу для офтальмологической линзы, содержащая:кольцевые слои подложки в форме полного круга с электрической и/или логической функциональными характеристиками; причем размер, форма и многоуровневая структура каждого из кольцевых слоев подложки зависят от толщины вокруг оптической зоны офтальмологической линзы;электрические соединения между слоями подложки; ипричем активная вставка в линзу герметично закрыта с одним или более материалами для связывания внутри основного компонента формованной офтальмологической линзы.2. Активная вставка в линзу по п.1, в которой функциональные слои подложки приклеены к изолирующим слоям с формированием многослойного элемента.3. Активная вставка в линзу по п.1 или 2, в которой кольцевые слои подложки в форме полного круга вырезают из полупроводниковой пластины.4. Активная вставка в линзу по п.1, в которой размер, форма и многоуровневая структура каждого из кольцевых слоев подложки дополнительно зависят от базовой кривизны офтальмологической ...

СПОСОБЫ И УСТРОЙСТВО ДЛЯ ОБРАЗОВАНИЯ ЭЛЕКТРОННОЙ СХЕМЫ НА ОФТАЛЬМОЛОГИЧЕСКИХ УСТРОЙСТВАХ

... 1. Офтальмологическое устройство с энергообеспечением и несущей вставкой, имеющей режим сохранения электроэнергии, содержащееисточник электроэнергии, встроенный в несущую вставку, причем герметизированная несущая вставка встроена в офтальмологическое устройство с энергообеспечением;электрическую нагрузку, встроенную в офтальмологическое устройство с энергообеспечением;среду электрического соединения для приведения электрической нагрузки в электрическую связь с источником электроэнергии, причем источник электроэнергии и электрическая нагрузка составляют часть электрической схемы; имеханизм переключения, включенный в электрическую схему и имеющий множество режимов, включая режим сохранения, при котором офтальмологическое устройство переводится в заданное состояние с низким энергопотреблением, причем механизм переключения вводит дополнительное сопротивление для ограничения величины тока, протекающего через электрическую нагрузку, и рабочий режим, при котором механизм переключения позволяет ...

Unauthorized modification indication circuit for protecting electronic component or circuit has loading detector adopting detectable permanent condition when loading exceeds given value

The circuit acts as a loading detector (20), coupled via an electrical conductor (1) to the protected electronic component or electronic circuit and adopting a detectable permanent condition when the loading exceeds a given value. A control circuit is coupled to the electrical conductor via a pair of switch elements (2,3), e.g. a pair of complementary FET's connected in series, for detecting the condition of the loading detector.

Stromspiegel in MOS-Technik mit weit aussteuerbaren Kaskodestufen

VERFAHREN ZUR DURCHFÜHRUNG VON ELEKTRONISCHEN BAUTEILEN IN DURCHGANGSLÖCHERN EINES MEHRSCHICHTIGEN MULTICHIP-MODULS

Halbleitervorrichtung und Bipolartransistor mit isoliertem Gate mit Transistorzellen und Sensorzelle

Ein Transistorzellbereich (610) einer Halbleitervorrichtung (500) umfasst Transistorzellen (TC), die elektrisch mit einer ersten Lastelektrode (310) verbunden sind. Ein inaktiver Bereich (630) umfasst eine Gateverdrahtungsstruktur (330), die elektrisch mit Gateelektroden (150) der Transistorzellen (TC) verbunden ist. Ein Übergangsbereich (620), der sandwichartig zwischen dem Transistorzellbereich (610) und dem inaktiven Bereich (630) angeordnet ist, umfasst wenigstens eine Sensorzelle (SC), die elektrisch mit einer Sensorelektrode (340) verbunden ist. Die Sensorzelle (SC) leitet in einem Einschaltzustand der Transistorzellen (TC) einen unipolaren Strom ab.

Signal testing apparatus for large circuits - has cell chain operating in normal mode to supply analog- digital signal to digital circuit and digital-analog signal to analog circuit and in test mode analog circuit is decoupled from digital circuit

The apparatus has a mixed signal circuit containing an analog circuit (4) to detect analog-to-digital signals and a digital circuit (10) to detect digital-to-analog signals. A boundary scan cell chain (50) connected between the two circuits receives the control signals. The cell chain operates in normal mode or in test mode depending on the control signals. Each analog-to-digital and digital-to-analog signals detected by the analog and digital circuits respectively are detected by the cell chain. In the normal operating mode, the analog-to-digital signal is supplied to the digital circuit and the digital-to- analog signal is supplied to the analog circuit. In the test mode, the analog circuit is decoupled from the digital circuit.

Leistungshalbleiterpackages und Multiphasengleichrichter mit einem Leistungshalbleiterpackage

Leistungshalbleiterpackage, umfassend:einen Referenzspannungsanschluss (2);einen Versorgungsspannungsanschluss (4);einen Phasenanschluss (6);einen ersten Leistungstransistor (8) mit einer Gate-Elektrode;einen zweiten Leistungstransistor (10) mit einer Gate-Elektrode,wobei der Versorgungsspannungsanschluss (4) elektrisch an den ersten Leistungstransistor (8) gekoppelt ist, der Referenzspannungsanschluss (2) elektrisch an den zweiten Leistungstransistor (10) gekoppelt ist, der Phasenanschluss (6) elektrisch zwischen den ersten Leistungstransistor (8) und den zweiten Leistungstransistor (10) geschaltet ist, der Versorgungsspannungsanschluss (4), der erste Leistungstransistor (8), der Phasenanschluss (6), der zweite Leistungstransistor (10) und der Referenzspannungsanschluss (2) nacheinander in Reihe geschaltet sind und der erste Leistungstransistor (8) und der zweite Leistungstransistor (10) einen Low-Side-Schalter und einen High-Side-Schalter einer Halbbrückenschaltung bilden;einen ersten ...

Halbleiterkomponente

Halbleiterkomponente, die ein monolithisch mit einer Schutzeinrichtung integriertes Gleichtaktfilter umfasst, wobei das Gleichtaktfilter umfasst: eine erste Spule mit ersten und zweiten Anschlüssen, und eine zweite Spule mit ersten und zweiten Anschlüssen, wobei der erste Anschluss der zweiten Spule mit dem ersten Anschluss der ersten Spule gekoppelt ist und wobei die erste Spule magnetisch mit der zweiten Spule gekoppelt ist, wobei die Schutzeinrichtung einen ersten Anschluss, der mit dem ersten Anschluss der ersten Spule gekoppelt ist, und einen zweiten Anschluss, der mit dem ersten Anschluss der zweiten Spule gekoppelt ist, aufweist.

HALBLEITERVORRICHTUNG MIT BRENNSTOFFZELLE UND VERFAHREN ZU IHRER HERSTELLUNG

Halbleiteranordnung mit einer stromabhaengigen Induktivitaet

VERFAHREN FÜR EINE ELEKTRISCHE ERKENNUNG EINER SCHÄDIGUNG EINER GESTAPELTEN DURCHKONTAKTSTRUKTUR FÜR METALLSICHERUNGSANWENDUNGEN

Verfahren für eine elektrische Erkennung einer Schädigung in dielektrischen Bereichen einer Sicherung, das die Schritte aufweist:Anlegen einer Spannung zwischen einem negativen Stromanschluss (I-) und einem positiven Stromanschluss (I+);Messen eines Stroms zwischen dem positiven Stromanschluss (I+) und dem negativen Stromanschluss (I-); undErkennen einer Schädigung in einem dielektrischen Bereich, in dem eine Schädigung existiert und sich ausgedehnt hat, wobei zwischen dem positiven Stromanschluss (I+) und dem negativen Stromanschluss (I-) ein Kurzschluss gemessen wird, und wobei die Sicherung eine Sicherungsstruktur aufweist, welche aufweist:eine erste dielektrische Schicht (120) mit einem ersten leitfähigen Durchkontakt (122) und einer ersten leitfähigen Leitung (123), die in einem ersten Hohlraum (121) angeordnet sind, der in der ersten dielektrischen Schicht (120) ausgebildet ist, wobei der erste leitfähige Durchkontakt (122) und die erste leitfähige Leitung (123) eine erste Überzugsschicht ...

Electromagnetically coupling electronic devices by driving a coupling element with one of a modulated continuous wave and an ultra-wideband pulse

An interconnect for transmitting an electric signal between electronic devices, comprising a first coupling element electromagnetically coupled to, and immediately juxtaposed to, a second coupling element. The first coupling element is mounted on and electrically connected to a first electronic device having a first integrated circuit, and the second coupling element is mounted on and electrically connected to a second electronic device having a second integrated circuit. A coupling device electrically connected to the first coupling element comprises one of a digital to ultra-wideband pulse converter and a RF modulator such that, in operation, the coupling device drives the first coupling element with one of an ultra-wideband pulse and a modulated RF signal to electromagnetically couple the first coupling element and the second coupling element.

Field plates on two opposed surfaces of double-based bidirectional bipolar transistor:devices, methods, and systems

Dual-base two-sided bipolar power transistors which use an insulated field plate to separate the emitter/collector diffusions from the nearest base contact diffusion. This provides a surprising improvement in turn-off performance, and in breakdown voltage.

Die connection monitoring system and method

A system for monitoring a die connection includes a die bonded to a substrate and a connection indicator circuit coupled to a monitor pad of the die. The connection indicator circuit is configured to detect a connection failure of the monitor pad. A signal corresponding to the monitor pad of the die is monitored, and an indication of a pad connection failure associated with the monitor pad is provided in response to a change in the monitored signal.

Electronic component and electronic apparatus

A package structure 100 for an electronic component 10 such as an image pickup or display device includes a ferromagnetic body 40 which may be a frame surrounding the device or two rods either side of the device (Fig. 11A), and conductor plates or films 811, 813 below the device and embedded in a base body 20, both of which reduce magnetic flux density through the device, hence the noise caused by magnetic fields. The conductor layer may comprise a paramagnetic or diamagnetic body having lower magnetic permeability than the ferromagnetic body. It may overlap part of the ferromagnetic body as well as the device, in which case a counter magnetic field resulting from eddy currents in the conductor caused by the undesirable magnetic field will pass orthogonally through the device and adjacent internal connectors and bond wires 3, 4, 5, in the z direction, and not cause undesirable additive magnetic field components in the x/y plane. A lid 30 placed over the device may be transparent. Outer ...

Intermeshed guard bands for multiple voltage supply structures on an integrated circuit and methods of making same

Die package with superposer substrate for passive components

A semiconductor die package 100 includes active circuitry 104 on a front side of a die 102, such as a system on chip (SoC) die or radio frequency (RF) die which includes a silicon substrate, and a separate component substrate 110 near a back side of the die to carry passive components 112 which may include high Q inductors, transformers, capacitors and resistors. The component substrate may be bump bonded to the back surface of the die. A conductive path, which may comprise a through silicon via (TSV) 116 connects passive components to the active circuitry on the die. A package substrate 106 may be positioned over the front side of the die and connected through a mold compound 108 to the die 102. A multi-die stack may include a second die on the opposite side of the component substrate to the first die (see Fig. 2; 222). The component substrate may extend laterally beyond the die allowing direct connection between the component substrate and package substrate by through mold vias (TMVs) ...

Improvements in or relating to high voltage semiconductor devices

Two gaps are placed in the reflowed phosphorus-doped silicon dioxide material overcoating of a planar high voltage semiconductor device to prevent polarization of the reflowed silox. The invention is applicable to any device using a polarizable glassy coating which will be exposed to a high electric field extending along its surface and is shown applied to a high voltage diode, a high voltage MOSFET and a high voltage TRIMOS-type device which is a semiconductor switching device using spaced MOS transistors having a common drain region.

Support structures for flexible electronic circuits

The flexible electronic structure for an RFID comprises a flexible IC package body 102 having contacts 104 to bond with an external circuit provided on a support which may comprise an antenna structure 352 (see figure 3c). Stand-off structures 302 on body 102 abut against the antenna 352 to reduce relative movement between the package body when it is mounted on the support. The stand-off structures may be formed using conductive ink.

Silicon planar transistor

Semiconductor component

PROCEDURE FOR THE EXECUTION OF ELECTRONIC CONSTRUCTION UNITS IN THROUGHHOLES OF A MULTILEVEL MULTI-CHIP MODULE

A construction unit, comprising a light detector, and a process to assemble such construction unit to a carrier, such as printed circuit card

The present invention embraces a construction unit ("K") comprising a light detector and mountable to a carrier ("B1"), such as a printed circuit card, and where said construction unit is adapted to be includable in a gas sensor-related arrangement ("A"). Said construction unit is assigned a plurality of first connection devices (4, 4a), which connection devices are adapted and distributed along a first surface portion (5) of said construction unit for an electric connection facility to second connection devices ((4), (4a)) related to said carrier ("B1"). Said construction unit ("K", 2) is adapted attachable to or placeable in the vicinity of a translucent recess ("Ba") formed in said carrier ("B1") for the formation of an aperture. An optoelectric sensor (44) is tightly placed against one side surface ("B1a") of said carrier ("B1") while a first light-generating means (1) is orientable, preferably as an individual unit, at an adapted distance from or along the other and opposite side surface ...

Anti tamper encapsulation for an integrated circuit

An integrated circuit package with permanent identification of device characteristics and method for adding the same

DRAWN DUMMY FeCAP, VIA AND METAL STRUCTURES

A process of forming an integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components.

Package systems and manufacturing methods thereof

A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.

Bond pad for wafer and package for cmos imager

An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads.

Semiconductor Device Having Island Type Support Patterns

A semiconductor device includes a plurality of cylindrical structures arranged in a first direction and a second direction, and a plurality of unit regions formed in the first direction and the second direction, each of the plurality of unit regions including an island type support pattern supporting the plurality of cylindrical structures contacting side surfaces of the plurality of cylindrical structures and an open region exposing the side surfaces of the plurality of cylindrical structures.

Semiconductor package and manufacturing method thereof

There are provided a semiconductor package including an electromagnetic shielding structure having excellent electromagnetic interference (EMI) and electromagnetic susceptibility (EMS) characteristics, while protecting individual elements in an inner portion thereof from impacts, and a manufacturing method thereof. The semiconductor package includes: a substrate having ground electrodes formed on an upper surface thereof; at least one electronic component mounted on the upper surface of the substrate; an insulating molding part including an internal space in which the electronic component is accommodated, and fixed to the substrate such that at least a portion of the ground electrode is externally exposed; and a conductive shield part closely adhered to the molding part to cover an outer surface of the molding part and electrically connected to the externally exposed ground electrodes.

Semiconductor Device And Method Of Manufacturing Semiconductor Device

A semiconductor chip includes a magnetic storage device and includes an electrode pad on a first face. The semiconductor chip is coated with a magnetic shield layer in a state in which at least the electrode pad is exposed. The semiconductor chip is mounted on an interconnect substrate through a bump. At least one of the semiconductor chip and the interconnect substrate includes a convex portion, and the bump is disposed over the convex portion.

Stackable semiconductor chip with edge features and methods of fabricating and processing same

A method of performing a function on a three-dimensional semiconductor chip package as well as on individual chips in the package is disclosed. That method involves the creation of an operative relationship between a function performer and an edge feature on the chip or chips wherein the edge feature consists of one or more of an electrically conductive pad, thermally conductive pad, a probe pad, a fuse, a resistor, a capacitor, an inductor, an optical emitter, an optical receiver, a test pad, a bond pad, a contact pin, a heat dissipator, an alignment marker, a metrology feature and a function performer may be any one or more of a test probe, the laser, a programming device, an interrogation device, a loading device or a tuning device. In addition, a chip per se with edge features is disclosed along with a three-dimensional stack of such chips in either of several different configurations. The disclosure provides information regarding the formation of edge feature, the singulation of dice having incipient edge features, the stacking of dice and the handling or dice with edge features.

Pixel of a multi-stacked cmos image sensor and method of manufacturing the same

Provided is a pixel of a multi-stacked complementary metal-oxide semiconductor (CMOS) image sensor and a method of manufacturing the image sensor including a light-receiving unit that may include first through third photodiode layers that are sequentially stacked, an integrated circuit (IC) that is formed below the light-receiving unit, electrode layers that are formed on and below each of the first through third photodiode layers, and a contact plug that connects the electrode layer formed below each of the first through third photodiode layers with a transistor of the IC.

MEMS and Protection Structure Thereof

A protection structure of a pad is provided. The pad is disposed in a dielectric layer on a semiconductor substrate and the pad includes a connection region and a peripheral region which encompasses the connection region. The protection structure includes at least a barrier, an insulation layer and a mask layer. The barrier is disposed in the dielectric layer in the peripheral region. The insulation layer is disposed on the dielectric layer. The mask layer is disposed on the dielectric layer and covers the insulation layer and the mask layer includes an opening to expose the connection region of the pad.

Semiconductor device and method of producing semiconductor device

A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.

Esd network circuit with a through wafer via structure and a method of manufacture

A method includes forming an ESD active device on a substrate, forming a ground plane on a backside of the substrate and forming at least one through wafer via electrically connected to a negative power supply of the ESD active device and the ground plane to provide a low series resistance path to the substrate.

Protection layer for preventing laser damage on semiconductor devices

A method for forming a semiconductor structure is provided to prevent energy that is used to blow at least one fuse formed on a metal layer above a semiconductor substrate from causing damage on the structure. The semiconductor structure includes a device, guard ring, protection ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. A seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.

Semiconductor device having groove-shaped via-hole

The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66 a having a pattern bent at a right angle; and buried conductors 70, 72 a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66 a. A groove-shaped via-hole 66 a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Electronic devices with floating metal rings

A electronic device is provided. The electronic device includes a first electrode formed in a first layer; a second electrode formed in the first layer, wherein the first electrode and the second electrode are symmetrically disposed with respect to a first point; and a first floating metal ring formed in the first layer and enclosing the first electrode and the second electrode.

Die Seal for Integrated Circuit Device

Disclosed herein is a semiconductor device having a novel stress reduction structures that are employed in an effort to eliminate or at least reduce undesirable cracking or chipping of semiconductor die. In one example, the device includes a die comprising a semiconducting substrate, wherein the die includes a cut surface. The device also includes a first die seal that defines a perimeter, and at least one stress reducing structure, at least a portion of which is positioned between the perimeter defined by the first die seal and the cut surface, wherein the cut surface exposes at least a portion of the stress reducing structure.

Seal ring structure with capacitor

A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate of a conductivity type having a chip region enclosed by a seal ring region. An insulating layer is on the semiconductor substrate. A seal ring structure is embedded in the insulating layer corresponding to the seal ring region. A capacitor is disposed under the seal ring structure and is electrically connected thereto, wherein the capacitor includes a body of the semiconductor substrate.

Crack detection line device and method

A crack detection line device and a method are disclosed. An embodiment comprises a semiconductor device comprising a crack detection line within a chip, the crack detection line surrounding an inner area of the chip, wherein the crack detection line comprises a first terminal and a second terminal. The semiconductor device further comprises a test circuit connected to the first terminal and the second terminal, the test circuit configured to measure a signal over the crack detection line and an output terminal, the output terminal connected to the test circuit and configured to provide a measured signal.

Semiconductor device and test method

A semiconductor device includes a semiconductor substrate including an element region, an inner sealing and an outer sealing which are formed on the element region and have a first opening part and a second opening part, respectively, a multilayer interconnection structure which is formed on the substrate and stacks multiple inter-layer insulation films each including a wiring layer, a moisture resistant film formed between a first inter-layer insulation film and a second inter-layer insulation film which are included in the multilayer interconnection structure, a first portion which extended from a first side of the moisture resistant film and passes the first opening part, a second portion which extended from a second side of the moisture resistant film and passes through the second opening part, and a wiring pattern including a via plug which penetrates the moisture resistant film and connects the first portion and the second portion.

Semiconductor structure including guard ring

One or more embodiments relate to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer guard ring and the conductive feature, the inner guard ring being electrically coupled to the conductive feature.

TEST CARRIER

A test carrier which can suppress the occurrence of contact defects while securing positional precision of the terminals is provided. A test carrier comprises: a base film which has one main surface which has bumps which contact electrodes of the die and a cover film which is laid over the base film the die is held between the base film and the cover film the base film has: a first region which has a first thickness t; and a second region which has a second thickness twhich is thinner than the first thickness t, and the second region faces at least a part of the edge of the die 1. A test carrier comprising:a film-shaped first member which has a one main surface which has terminals which contact electrodes of an electronic device; anda second member which is laid over the first member, whereinthe electronic device is held between the first member and the second member,the first member has:a first region which has a first thickness; anda second region which has a second thickness which is thinner than the first thickness, andthe second region faces at least a part of the outer peripheral edge of the electronic device.2. The test carrier as set forth in claim 1 , whereinthe second region faces at least a part of the outer peripheral edge near at least one of the electrodes.3. The test carrier as set forth in claim 1 , whereinthe second region faces all the electrodes of the electronic device.4. The test carrier as set forth in claim 1 , whereinthe second region is formed by thinning the first member from the other main surface.5. The test carrier as set forth in claim 1 , whereinthe first member has at least:a first resin layer; anda second resin layer which is laid over the first resin layer, andthe second region is formed by removing the second resin layer from the first resin layer.6. The test carrier as set forth in claim 1 ,the electronic device under test is a die which is diced from a semiconductor wafer. The present invention relates to a test carrier to which ...

Discontinuous thin semiconductor wafer surface features

A semiconductor wafer has a semiconductor substrate and films on the substrate. The substrate and/or the films have at least one etch line creating a discontinuous surface that reduces residual stress in the wafer. Reducing residual stress in the semiconductor wafer reduces warpage of the wafer when the wafer is thin. Additionally, isolation plugs may be used to fill a portion of the etch lines to prevent shorting of the layers.

Die package, method of manufacturing the same, and systems including the same

A die package includes a substrate, a die mounted on the substrate, and a ZQ resistor disposed in the die package and connected to the substrate and the die. The ZQ resistor may be used to calibrate impedance of the die.

Visual indicator for semiconductor chips for indicating mechanical or esd damage

A semiconductor device including a semiconductor substrate having a surface including an active semiconductor device including one of a laser and a photodiode; and a visual indicator disposed on the semiconductor body and at least adjacent to a portion of said active semiconductor device, the indicator having a state that shows if damage to the active semiconductor device may have occurred.

Ultra high speed signal transmission/reception

An interconnect for transmitting an electric signal between electronic devices includes a first coupling element electromagnetically coupled to, and immediately juxtaposed to, a second coupling element. The first coupling element is mounted on and is electrically connected to a first electronic device having a first integrated circuit. The second coupling element may be mounted on and electrically connected to the first electronic device, and electrically connected to an interconnect on a second electronic device, or the second coupling element may be mounted on and electrically connected to the second electronic device.

Integrated Circuit Having Stress Tuning Layer and Methods of Manufacturing Same

Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

Integrated Mechanical Device for Electrical Switching

An integrated circuit comprising a mechanical device for electrical switching comprising a first assembly being thermally deformable and having a beam held at at least two different locations by at least two arms, the beam and the arms being metal and disposed within the same metallization level, and further comprising at least one electrically conducting body. The first assembly has a first configuration at a first temperature and a second configuration at a second temperature different from the first temperature. The beam is out of contact with the electrically conducting body in one configuration in contact with the body in the other configuration. The beam establishes or breaks an electrical link passing through the said at least one electrically conducting body and through the said beam in the different configurations. 1. An integrated circuit , comprising:a plurality of metallization levels separated by an insulating region and disposed on a substrate; and a first assembly being thermally deformable and disposed within an enclosure and having a beam held at at least two different locations by at least two arms rigidly attached to edges of the enclosure, the beam and the arms being metal and disposed within a same metallization level; and', 'at least one electrically conducting body, the said first assembly having at least a first configuration at a first temperature and a second configuration when at least one of the arms is at a second temperature different from the first temperature;, 'a mechanical device for electrical switching comprisingwherein the beam is out of contact with the said at least one electrically conducting body in one of the first configuration and second configuration and in contact with the said at least one electrically conducting body in the other of the first configuration and the second configuration and establishing or breaking an electrical link passing through the said at least one electrically conducting body and through the said ...

Semiconductor device and process for producing semiconductor device

A semiconductor device includes: a substrate in which a product region and scribe regions are defined; a 1st insulation film formed above the substrate; a metal film in the 1st insulation film, disposed within the scribe regions in such a manner as to surround the product region; a 2nd insulation film formed on the 1st insulation film and the metal film; a 1st groove disposed more inside than the metal film in such a manner as to surround the product region, and reaching from a top surface of the 2nd insulation film to a position deeper than a top surface of the metal film; and a 2nd groove disposed more outside than the metal film in such a manner as to surround the metal film, and reaching from the top surface of the 2nd insulation film to a position deeper than the top surface of the metal film.

3D INTEGRATED CIRCUIT

A method for manufacturing an integrated circuit, including the steps of forming first transistors on a first semiconductor layer; depositing a first insulating layer above the first semiconductor layer and the first transistors, and leveling the first insulating layer; depositing a conductive layer above the first insulating layer, and covering the conductive layer with a second insulating layer; bonding a semiconductor wafer to the second insulating layer; thinning the semiconductor wafer to obtain a second semiconductor layer; and forming second transistors on the second semiconductor layer. 1. A method for manufacturing an integrated circuit , comprising the steps of:forming first transistors on a first semiconductor layer;depositing a first insulating layer above the first semiconductor layer and the first transistors, and leveling the first insulating layer;depositing a conductive layer above the first insulating layer, and covering the conductive layer with a second insulating layer;bonding a semiconductor wafer to the second insulating layer;thinning the semiconductor wafer to obtain a second semiconductor layer; andforming second transistors on the second semiconductor layer.2. The method of claim 1 , further comprising claim 1 , after the step of forming of the second transistors on the second semiconductor layer claim 1 , a step of deposition of a third insulating layer on the second semiconductor layer and the second transistors claim 1 , and a step of forming of a contact crossing the third insulating layer and the second insulating layer all the way to the conductive layer.3. The method of claim 1 , wherein the first insulating layer is made of silicon oxide and has a thickness ranging between 20 and 100 nm between the gates of the first transistors and the conductive layer claim 1 , and wherein the second insulating layer is made of silicon oxide and has a thickness ranging between 10 and 25 nm.4. The method of claim 1 , wherein the conductive layer ...

Methods of manufacture and use of energized ophthalmic devices having an electrical storage mode

This invention discloses methods of manufacture and use of an energized Ophthalmic Device with an incorporated Storage Mode for a power source, the method of manufacturing said device, and a method of activation that may restore the power source to an operational mode.

Gate conductor with a diffusion barrier

A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species across the barrier region. The barrier region comprises at least one sublithographic gap in the gate conductor structure. The sublithographic gap is formed by using self-assembling copolymers to form a sublithographic patterned mask over the gate conductor structure. According to one embodiment, at least one sublithographic gap is a slit or line that traverses the width of the gate conductor structure. The sublithographic gap is sufficiently deep to minimize or prevent cross-diffusion of the implanted dopant from the upper portion of the gate conductor. According to another embodiment, the sublithographic gaps are of sufficient density that cross-diffusion of dopants is reduced or eliminated during an activation anneal such that changes in Vt are minimized. 113-. (canceled)14. A structure comprising:a semiconductor region comprising a first doped region and a second doped region; andan air gap extending across a width of the semiconductor region between the first doped region and the second doped region.15. The structure of claim 14 , wherein the air gap extends from at least an upper portion of the semiconductor region.16. The structure of claim 14 , wherein the first doped region comprises a p-type dopant and the second doped region comprises an n-type dopant.17. The structure of claim 14 , wherein the air gap extends to a depth where a dopant concentration of the semiconductor region measured at a bottom of the air gap is less than 50% of the highest dopant concentration in the semiconductor region located at a top of the semiconductor region.18. The structure of claim 14 , wherein the semiconductor region comprises a gate conductor between a first semiconductor device and a second semiconductor device.19. A structure comprising:a semiconductor region comprising a first ...

METHOD AND SYSTEM FOR BINDING HALIDE-BASED CONTAMINANTS

A method and apparatus are presented for reducing halide-based contamination within deposited titanium-based thin films. Halide adsorbing materials are utilized within the deposition chamber to remove halides, such as chlorine and chlorides, during the deposition process so that contamination of the titanium-based film is minimized. A method for regenerating the halide adsorbing material is also provided.

Semiconductor component that includes a protective structure

In accordance with an embodiment a semiconductor component includes an electrically conductive structure formed over a portion of a semiconductor material. An electrical interconnect having a top surface and opposing edges contacts the electrically conductive structure. A protective structure is formed on the top surface and the opposing edges of the electrical interconnect and over a portion of the electrically conductive structure, wherein the protective structure forms a seal that protects the electrical interconnect. 1. A semiconductor component , comprising:a semiconductor material having a major surface;an electrically conductive structure over a portion of the major surface;an electrical interconnect having a top surface and opposing edges in contact with the electrically conductive structure; anda protective structure on the top surface and the opposing edges of the electrical interconnect and over a portion of the electrically conductive structure, wherein the protective structure forms a seal that protects the electrical interconnect.2. The semiconductor component of claim 1 , wherein the electrically conductive structure includes a layer of aluminum in contact with the major surface and at least one layer of metal over the layer of aluminum claim 1 , and wherein the electrical interconnect comprises copper and the protective structure comprises one of an electrically conductive material or an electrically non conductive material.3. The semiconductor component of claim 1 , wherein the protective structure comprises:a first layer of metal over the electrical interconnect; anda second layer of metal over the first layer of metal.4. The semiconductor component of claim 3 , wherein the first layer of metal comprises a metal selected from the group of metals comprising nickel claim 3 , tin claim 3 , copper claim 3 , and solder and the second metal layer comprises a metal selected from the group of metals comprising gold claim 3 , tin claim 3 , palladium claim 3 ...

Inductor for Post Passivation Interconnect

An inductor device and method of forming the inductor device are provided. In some embodiments the inductor device includes a post passivation interconnect (PPI) layer disposed and an under bump metallization (UBM) layer, each disposed over a substrate. The PPI layer forms a coil and dummy pads. The dummy pads are disposed around a substantial portion of the coil to shield the coil from electromagnetic interference. A first portion of the UBM layer is electrically coupled to the coil and configured to interface with an electrical coupling member.

Semiconductor devices including electromagnetic interference shield

Provided are a semiconductor device including an EMI shield, a method of manufacturing the same, a semiconductor module including the semiconductor device, and an electronic system including the semiconductor device. The semiconductor device includes a lower semiconductor package, an upper semiconductor package, a package bump, and an EMI shield. The lower semiconductor package includes a lower substrate, a lower semiconductor chip mounted on the lower substrate, and a ground wire separated from the lower semiconductor chip. The upper semiconductor package includes an upper substrate stacked on the lower semiconductor package, and an upper semiconductor chip stacked on the upper substrate. The package bump electrically connects the upper semiconductor package and the lower semiconductor package. The EMI shield covers the upper and lower semiconductor packages and is electrically connected to the ground wire.

METHOD FOR MANUFACTURING FINE-PITCH BUMPS AND STRUCTURE THEREOF

A method for manufacturing fine-pitch bumps comprises providing a silicon substrate; forming a titanium-containing metal layer having a plurality of first zones and a plurality of second zones on the silicon substrate; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer; forming a plurality of copper bumps having a plurality of first top surfaces and a plurality of first ring surfaces; heating the photoresist layer to form a plurality of body portions and removable portions; etching the photoresist layer; forming a plurality of bump protection layers on the titanium-containing metal layer, the first top surface and the first ring surface, each of the bump protection layers comprises a bump coverage portion; plating a plurality of gold layers at the bump coverage portion; eventually, removing the second zones to enable each of the first zones to form an under bump metallurgy layer. 1. A fine-pitch bump structure at least comprising:a silicon substrate having a surface, a plurality of bond pads disposed at the surface and a protective layer disposed at the surface, wherein the protective layer comprised a plurality of openings, and the bond pads are revealed by the openings;a plurality of under bump metallurgy layers formed on the bond pads, each of the under bump metallurgy layers comprises a bearing portion and an extending portion;a plurality of copper bumps formed on the under bump metallurgy layers, each of the copper bumps comprises a first top surface and a first ring surface, the bearing portion of each of the under bump metallurgy layers is located under each of the copper bumps, and the extending portion of each of the under bump metallurgy layers is protruded to the first ring surface of each of the copper bumps;a plurality of bump protection layers formed on the extending portions of the under bump metallurgy layers, the first top surface and the first ring surface of each of the copper bumps, each of the ...

Power line filter for multidimensional integrated circuits

An interposer element in a multidimensional integrated circuit with stacked elements has one or more conductors, especially power supply lines, coupled through decoupling networks defining low impedance shunts for high frequency signals to ground. The interposer has successive tiers including silicon, metal and dielectric deposition layers. The decoupling network for a conductor has at least one and preferably two reactive transmission lines. A transmission line has an inductor in series with the conductor and parallel capacitances at the inductor terminals. The inductors are formed by traces in spaced metal deposition layers forming coil windings and through vias connecting between layers to permit conductor crossovers. The capacitances are formed by MOScaps in the interposer layers. An embodiment has serially coupled coils with capacitances at the input, output and junction between the coils, wherein the coils are magnetically coupled to form a transformer.

INTEGRATED ELECTRONIC COMPONENTS AND METHODS OF FORMATION THEREOF

Provided are integrated electronic components which include a waveguide microstructure formed by a sequential build process and an electronic device, and methods of forming such integrated electronic components. The microstructures have particular applicability to devices for transmitting electromagnetic energy and other electronic signals. 19-. (canceled)10. An integrated electronic component , comprising:an electronic device; anda microstructure comprising a waveguide section having a non-solid core volume within an outer conductor surrounding the core volume, and a transition structure coupling the waveguide section to the electronic device.11. The integrated electronic component according to claim 10 , wherein the waveguide section includes first and second ports and wherein the electronic device is coupled to the waveguide section intermediate the first and second ports.12. The integrated electronic component according to claim 10 , wherein the outer conductor has an opening disposed therein and the electronic device is disposed within the opening.13. The integrated electronic component according to claim 10 , wherein the electronic device is coupled at a location proximate an upper surface of the outer conductor.14. The integrated electronic component according to claim 10 , wherein the electronic device is mechanically coupled to the outer conductor.15. The integrated electronic component according to claim 10 , wherein the transition structure includes a support post mechanically coupling the electronic device to the waveguide section.16. The integrated electronic component according to claim 10 , wherein the transition structure includes a support post electrically coupling the electronic device to the waveguide section.17. The integrated electronic component according to claim 10 , wherein the waveguide section comprises a center conductor within the outer conductor and wherein the transition structure includes a support post that mechanically couples the ...

CHIP STRUCTURE AND WAFER STRUCTURE

A chip structure includes a substrate and a stress buffer layer. The substrate has a first surface and a second surface opposite to the first surface. The stress buffer layer is disposed on the periphery of the substrate and located in at least one of the first surface and the second surface of the substrate. 1. A chip structure , comprising:a substrate having a first surface and a second surface opposite to the first surface; anda stress buffer layer disposed on the periphery of the substrate and located in at least one of the first surface and the second surface of the substrate.2. The chip structure as claimed in claim 1 , wherein a material of the stress buffer layer comprises metal claim 1 , glass claim 1 , or a polymer material.3. The chip structure as claimed in claim 1 , wherein the stress buffer layer protrudes from one of the first surface and the second surface of the substrate.4. The chip structure as claimed in claim 1 , wherein the stress buffer layer is embedded in one of the first surface and the second surface of the substrate.5. The chip structure as claimed in claim 1 , wherein the substrate comprises a plurality of active circuits located on the first surface claim 1 , and the stress buffer layer is located on an area outside the active circuits.6. The chip structure as claimed in claim 5 , further comprising at least a conductive through hole penetrating the second surface of the substrate and connecting the active circuits.7. The chip structure as claimed in claim 1 , further comprising at least a conductive through hole penetrating the substrate and connecting the first surface and the second surface of the substrate.8. A wafer structure claim 1 , comprising:a substrate having a first surface, a second surface opposite to the first surface, and a plurality of cutting paths dividing the substrate into a plurality of chip units; anda stress buffer layer surrounding each of the chip units and disposed on at least one of the first surface and the ...

Adjusting configuration of a multiple gate transistor by controlling individual fins

In a sophisticated semiconductor device, FINFET elements may be provided with individually accessible semiconductor fins which may be connected to a controllable interconnect structure for appropriately adjusting the transistor configuration, for instance with respect to current drive capability, replacing defective semiconductor fins and the like. Consequently, different transistor configurations may be obtained on the basis of a standard transistor cell architecture, which may result in increased production yield of highly complex manufacturing strategies in forming non-planar transistor devices.

Miniaturized Implantable Sensor Platform Having Multiple Devices and Sub-Chips

An implantable, miniaturized platform and a method for fabricating the platform is provided, where the e platform includes a top cover plate and a bottom substrate, top cover plate including an epitaxial, Si-encased substrate and is configured to include monolithically grown devices and device contact pads, the Si-encased substrate cover plate including a gold perimeter fence deposited on its Si covered outer rim and wherein the bottom substrate is constructed of Si and includes a plurality of partial-Si-vias (PSVs), electronic integrated circuits, device pads, pad interconnects and a gold perimeter fence, wherein the device pads are aligned with a respective device contact pad on the top cover plate and includes gold bumps having a predetermined height, the top cover plate and the bottom substrate being flip-chip bonded to provide a perimeter seal and to ensure electrical connectivity between the plurality of internal devices and at least one external component. 1. A device platform , which contains at least one internal component , wherein the device platform is configured to isolate the at least one internal component from an environment external to the device platform while providing for electrical connectivity to at least one external component externally located on the outer surface of the said device platform , the device comprising:an enclosure, said enclosure including a top cover plate and a bottom substrate configured to define a sealed enclosure cavity for containing the at least one component,wherein said top cover plate is configured to allow reception and transmission of electromagnetic radiation, the surface of said top cover plate adjacent said enclosure cavity being covered with an epitaxial Si film in intimate cohesion, andwherein said bottom substrate is constructed of a high resistivity Si having a Si substrate material conductivity and includes at least one partial Si via (PSV), wherein said at least one partial Si via (PSV) is configured to ...

Semiconductor device

A semiconductor device includes a superjunction structure. The influence of external charge on device performance is suppressed using a shield electrode, field plate electrodes, and cover electrodes in various configurations. Optional embodiments include placing an interconnection film between certain electrodes and the upper surface of the superjunction structure. Cover electrodes may also be connected to various potentials to limit the effects of external charge on device performance.

Semiconductor integrated circuit and method for measuring internal voltage thereof

A semiconductor integrated circuit includes at least one second semiconductor chip configured to generate an internal voltage, and a first semiconductor chip including a monitoring unit configured to monitor the internal voltage, and a first pad configured to provide monitoring result information outputted from the monitoring unit to a test device.

ELECTRONIC DEVICE MANUFACTURING METHOD, ELECTRONIC DEVICE, AND CHIP ASSEMBLY

An electronic device manufacturing method includes a cutting step at which a wafer is cut to obtain chips before pattern formation and a polishing step at which cut surfaces of the obtained chips are subjected in one batch to barrel polishing. The method further includes an aligning step at which the polished chips are aligned so that front surfaces thereof face in an upward direction. The method further includes a bonding step at which the cut surfaces of the aligned chips are bonded together with an adhesive to thereby form a chip assembly. The method further includes a pattern forming step at which a circuit pattern is formed on each of the chips of the chip assembly and a melting step at which the adhesive on the chip assembly is melted to thereby separate the chip assembly into chips after pattern formation. 1. A method for manufacturing an electronic device , the method comprising:cutting a wafer to obtain chips before pattern formation;polishing a cut surface of each of the obtained chips in one batch;bonding together the cut surfaces of the polished chips with an adhesive; andforming a pattern on each of the chips bonded together.2. The method for manufacturing an electronic device according to claim 1 , the method further comprising:aligning the polished chips so that intended surfaces thereof on which the patterns are to be formed face in an identical direction, whereinthe cut surfaces of the aligned chips are bonded together with the adhesive.3. The method for manufacturing an electronic device according to claim 2 , the method further comprising:melting the adhesive that bonds together the chips on which the patterns are formed.4. The method for manufacturing an electronic device according to claim 2 , wherein the bonding includes applying the adhesive to gaps between the aligned chips to thereby bond together the cut surfaces of the chips.5. The method for manufacturing an electronic device according to claim 2 , wherein the bonding includes applying ...

THROUGH SILICON VIA GUARD RING

The present disclosure relates to forming a plurality of through silicon vias guard rings proximate the scribes streets of a microelectronic device wafer. The microelectronic device wafer includes a substrate wherein the through silicon via guard ring is fabricated by forming vias extending completely through the substrate. The through silicon via guard rings act as crack arresters, such that defects caused by cracks resulting from the dicing of the microelectronic wafer are substantially reduced or eliminated. 1. A method of forming a guard ring , comprising:forming a microelectronic device wafer comprising a substrate having a first and second surface and an interconnect layer disposed on the substrate first surface, the substrate including a plurality of integrated circuits formed proximate the substrate first surface, wherein each of the plurality of the plurality of integrated circuits are separated by at least one dicing street; andforming a plurality of vias proximate the dicing street and extending from the substrate second surface to the substrate first surface.2. The method of claim 1 , further comprising cutting through the substrate wafer within said dicing street.3. The method of claim 1 , wherein providing a microelectronic device wafer further comprises providing a microelectronic device wafer comprising an interconnect guard ring within the interconnect layer and proximate the dicing street.4. The method of claim 3 , wherein forming a plurality of vias extending from the substrate second surface to the substrate first surface comprises forming a plurality of vias extending from the substrate second surface to the substrate first surface claim 3 , wherein the via abuts the interconnect guard ring at the substrate first surface.5. The method of claim 1 , wherein forming the plurality of vias comprises forming a plurality of vias and filling the plurality of vias prior to the forming of the interconnect layer. The present application is a divisional of ...

Method of producing semiconductor wafer, semiconductor wafer, method of producing semiconductor device and semiconductor device

There is provided a fabrication technique of a MOS structure that has a small EOT without increasing the interface trap density. More specifically, provided is a method of producing a semiconductor wafer that includes a semiconductor crystal layer, an interlayer made of an oxide, nitride, or oxynitride of a semiconductor crystal constituting the semiconductor crystal layer, and a first insulating layer made of an oxide and in which the semiconductor crystal layer, the interlayer, and the first insulating layer are arranged in the stated order. The method includes (a) forming the first insulating layer on an original semiconductor crystal layer, and (b) exposing a surface of the first insulating layer with a nitrogen plasma to nitride, oxidize, or oxynitride a part of the original semiconductor crystal layer, thereby forming the interlayer, together with the semiconductor crystal layer that is the rest of the original semiconductor crystal layer.

Scribe line structure for wafer dicing and method of making the same

A scribe line structure between die regions is disclosed. The scribe line structure includes a dielectric layer disposed on a substrate; and a plurality of metal structures arranged up-and-down in the dielectric layer on the substrate, the plurality of metal structures comprising metal layers and metal vias, wherein the metal vias are disposed on the dicing path and regions outside the dicing path and the metal vias on the dicing path have a lower metal density than the metal vias not on the dicing path.

LOW RESISTIVITY GATE CONDUCTOR

Embodiments of the invention provide an approach for bottom-up growth of a low resistivity gate conductor. Specifically, a low resistivity metal (e.g., aluminum or cobalt) is selectively grown directly over metal layers in a set of gate trenches using a chemical vapor deposition or atomic layer deposition process to form the gate conductor. 1. A method for forming a device , the method comprising:forming a set of trenches in a dielectric material;forming a low-resistivity gate conductor atop each of a set of metal layers in each of the set of trenches; andforming a capping layer over the low-resistivity gate conductor.2. The method according to claim 1 , the forming the set of trenches in the dielectric material comprising performing an etch.3. The method according to claim 1 , the set of metal layers comprising at least one of: titanium nitride and titanium carbide.4. The method according to claim 1 , the low-resistivity gate conductor comprising at least one of: aluminum claim 1 , cobalt claim 1 , and nitride.5. The method according to claim 1 , the forming the low-resistivity gate conductor comprising one of: atomic layer deposition claim 1 , and chemical vapor deposition.6. The method according to claim 1 , the capping layer comprising silicon nitride.7. The method according to claim 1 , wherein the dielectric material comprises a high-k dielectric.8. A method for forming a semiconductor gate stack claim 1 , the method comprising:forming a set of trenches in a dielectric material;forming a low-resistivity conductive metal atop each of a set of metal layers in each of the set of trenches; andforming a capping layer over the low-resistivity conductive metal.9. The method according to claim 8 , the forming the set of trenches in the dielectric material comprising performing an etch.10. The method according to claim 8 , the set of metal layers comprising at least one of: titanium nitride claim 8 , and titanium carbide.11. The method according to claim 8 , the low- ...

SEMICONDUCTOR DEVICE

A carrier is prevented from being stored in a guard ring region in a semiconductor device. The semiconductor device has an IGBT cell including a base region and an emitter region formed in an n− type drift layer, and a p type collector layer arranged under the drift layer with a buffer layer interposed therebetween. A guard ring region having a guard ring is arranged around the IGBT cell. A lower surface of the guard ring region has a mesa structure provided by removing the collector layer. 1. A semiconductor device comprising:a first semiconductor layer having a first conductivity type;a second semiconductor layer arranged under said first semiconductor layer and having a second conductivity type;an IGBT cell having a base region and an emitter region formed in said first semiconductor layer, and a collector layer provided as said second semiconductor layer; anda guard ring region provided around a cell region having said IGBT cell, and having a guard ring formed in said first semiconductor layer, whereinsaid second semiconductor layer is removed from a lower part of said guard ring region.2. The semiconductor device according to claim 1 , whereinsaid first semiconductor layer comprises:a drift layer; anda buffer layer having an impurity concentration higher than that of said drift layer, and interposed between said drift layer and said second semiconductor layer, andan impurity layer having said second conductivity type is formed on a bottom part of said drift layer in said guard ring region.3. The semiconductor device according to claim 2 , whereina thickness of said impurity layer increases toward an outer periphery of a chip.4. The semiconductor device according to claim 2 , whereinsaid impurity layer is divided into several parts.5. The semiconductor device according to claim 1 , whereina lower surface of said guard ring region is covered with a protection film.6. A semiconductor device comprising:a first semiconductor layer having a first conductivity type;a ...

SEMICONDUCTOR DEVICE

To suppress the noise caused by an inductor leaks to the outside, and also to be configured such that magnetic field intensity change reaches the inductor. 1. A semiconductor device , comprising:a substrate;an internal circuit;a multilayered wiring layer formed over the substrate;an inductor which is formed by use of the multilayered wiring layer and provided so as to surround the internal circuit in a planar view, and both ends of which are coupled to the internal circuit;an upper shield part which is formed by use of the multilayered wiring layer, overlaps the inductor in the planar view, is located in a layer higher than the inductor in a thickness direction, and has plural first openings each overlapping the inductor; anda lower shield part which overlaps the inductor in the planar view and is located in a layer lower than the inductor in the thickness direction.2. The semiconductor device according to claim 1 ,wherein the lower shield part is formed by use of the multilayered wiring layer.3. The semiconductor device according to claim 2 ,wherein the lower shield part has plural second openings each overlapping the inductor.4. The semiconductor device according to claim 3 ,wherein the first opening and the second opening overlap each other at least in a part thereof.5. The semiconductor device according to claim 2 ,wherein the lower shield part further includes an impurity layer formed in the substrate.6. The semiconductor device according to claim 1 ,wherein the lower shield part includes an impurity layer formed in the substrate.7. The semiconductor device according to claim 6 ,wherein a silicide layer formed in a surface layer of the impurity layer is provided.8. The semiconductor device according to claim 1 ,wherein the first opening has a rectangular shape and also has a longitudinal direction parallel to the inductor.9. The semiconductor device according to claim 1 ,whereinthe inductor surrounds the internal circuit in plural turns, and also a first ring- ...

POWER SEMICONDUCTOR HOUSING WITH REDUNDANT FUNCTIONALITY

In various embodiments, a power semiconductor housing having an integrated circuit is provided. The integrated circuit may include: a first gate pad and a second gate pad; and a first gate contact and a second gate contact; wherein the first gate pad is electrically connected to the first gate contact; wherein the second gate pad is electrically connected to the second gate contact. The integrated circuit may further include a drain-contact surface, wherein the drain-contact surface is connected to a drain contact; and a second drain contact, which is electrically connected to the drain-contact surface of the integrated circuit. 1. A power semiconductor housing having an integrated circuit , the integrated circuit comprising:a first gate pad and a second gate pad; anda first gate contact and a second gate contact;wherein the first gate pad is electrically connected to the first gate contact;wherein the second gate pad is electrically connected to the second gate contact;the integrated circuit further comprising;a drain-contact surface, wherein the drain-contact surface is connected to a drain contact; anda second drain contact, which is electrically connected to the drain-contact surface of the integrated circuit.2. The power semiconductor housing of claim 1 ,wherein the drain-contact surface is formed by means of a chip island andwherein the chip island also forms a drain contact.3. The power semiconductor housing of claim 1 ,wherein the integrated circuit has a source-contact surface;wherein the power semiconductor housing has a first source contact and a second source contact;wherein the first source contact is connected to the source-contact surface of the integrated circuit; andwherein the second source contact is connected to the source-contact surface of the integrated circuit.4. A method for increasing the fail-safety of electronic components claim 1 , wherein at least one gate contact and a drain contact are embodied on a redundant basis.5. The method of ...

Semiconductor device and test method

A semiconductor device includes a semiconductor substrate including an element region, an inner sealing and an outer sealing which are formed on the element region and have a first opening part and a second opening part, respectively, a multilayer interconnection structure which is formed on the substrate and stacks multiple inter-layer insulation films each including a wiring layer, a moisture resistant film formed between a first inter-layer insulation film and a second inter-layer insulation film which are included in the multilayer interconnection structure, a first portion which extended from a first side of the moisture resistant film and passes the first opening part, a second portion which extended from a second side of the moisture resistant film and passes through the second opening part, and a wiring pattern including a via plug which penetrates the moisture resistant film and connects the first portion and the second portion.

Method for forming semiconductor die and semiconductor device thereof

A method for forming a semiconductor die, includes forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region, forming a metal pad and a test pad on the interlayer dielectric layer, forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad, first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process, second etching the passivation dielectric layer to expose the metal pad and the test pad, forming a bump on the metal pad, and dicing the substrate while removing the scribe line region by mechanical sawing.

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

There are provided a semiconductor package including an electromagnetic shielding structure having excellent electromagnetic interference (EMI) and electromagnetic susceptibility (EMS) characteristics, while protecting individual elements in an inner portion thereof from impacts, and a manufacturing method thereof. The semiconductor package includes: a substrate having ground electrodes formed on an upper surface thereof; at least one electronic component mounted on the upper surface of the substrate; an insulating molding part including an internal space in which the electronic component is accommodated, and fixed to the substrate such that at least a portion of the ground electrode is externally exposed; and a conductive shield part closely adhered to the molding part to cover an outer surface of the molding part and electrically connected to the externally exposed ground electrodes. 14-. (canceled)5. A manufacturing method of a semiconductor package , the manufacturing method comprising:preparing a substrate having ground electrodes formed on an upper surface thereof;mounting electronic components on the upper surface of the substrate;seating a molding part having a cap shape on the substrate such that a portion of the ground electrodes is externally exposed; andforming a conductive shield part on an outer surface of the molding part, the conductive shield part being electrically connected to the externally exposed ground electrodes.6. The manufacturing method of claim 5 , wherein the forming of the conductive shield part includes forming the conductive shield part through a conformal coating method.7. The manufacturing method of claim 5 , wherein the forming of the conductive shield part includes forming the conductive shield part through a screen printing method.8. The manufacturing method of claim 5 , wherein the ground electrodes are formed on the substrate along edges thereof.9. The manufacturing method of claim 5 , wherein the preparing of the substrate ...

SYSTEMS AND METHODS FOR INTEGRATING BATTERIES WITH STACKED INTEGRATED CIRCUIT DIE ELEMENTS

A system comprises an integrated circuit die substrate; volatile memory electrically coupled to the integrated circuit die substrate; a first integrated circuit die element electrically coupled to the integrated circuit die substrate, the first integrated circuit die element comprising a first field programmable gate array (FPGA), and the first integrated circuit die element disposed adjacent to the volatile memory; a battery charger operable to receive power from a main power supply, the main power supply having an on state and an off state, wherein the main power supply is supplying power in the on state and not supplying power in the off state; and a battery module disposed on a top portion of the first integrated circuit die element, the battery module operable to receive power from the battery charger, and the battery module operable to supply power to the volatile memory at least when the main power supply is in the off state. 1. A system comprising:an integrated circuit die substrate; a processor;', 'volatile memory electrically coupled to the processor; and', 'a field programmable gate array (FPGA) having a configuration based on configuration data stored in configuration memory;, 'a die stacking package electrically coupled to the integrated circuit die substrate, the die stacking package including'}a battery charger operable to receive power from a main power supply, the main power supply having an on state and an off state, the main power supply operable to supply power to assist in maintaining the volatile memory when the main power supply is in the on state and operable not to supply power to assist in maintaining the volatile memory when the main power supply is in the off state; anda battery module operable to receive power from the battery charger, and operable to supply power to the volatile memory to maintain the volatile memory at least when the main power supply is in the off state.2. The system of claim 1 , wherein the volatile memory comprises ...

Semiconductor Device Including a Contact Structure Directly Adjoining a Mesa Section and a Field Electrode

A semiconductor device includes a gate structure that extends from a first surface into a semiconductor portion and that surrounds a transistor section of the semiconductor portion. A field plate structure includes a field electrode and extends from the first surface into the transistor section. A mesa section of the semiconductor portion separates the field plate structure and the gate structure. A contact structure includes a first portion directly adjoining the mesa section and a second portion directly adjoining the field electrode. The first and second portions include stripes and are directly connected to each other. 1. A semiconductor device , comprising:a gate structure extending from a first surface into a semiconductor portion and surrounding a transistor section of the semiconductor portion;a field plate structure extending from the first surface into the transistor section and comprising a field electrode;a mesa section of the semiconductor portion separating the field plate structure and the gate structure; anda contact structure comprising a first portion directly adjoining the mesa section and a second portion directly adjoining the field electrode, wherein the first and second portions include stripes and are directly connected to each other.2. The semiconductor device of claim 1 , wherein the first portion includes stripes forming a closed claim 1 , polygonal frame in a horizontal cross-section parallel to the first surface.3. The semiconductor device of claim 1 , wherein the first portion includes stripes forming a closed claim 1 , regular polygonal frame in a horizontal cross-section parallel to the first surface.4. The semiconductor device of claim 1 , wherein the first portion includes four stripes forming a closed square frame in a horizontal cross-section parallel to the first surface.5. The semiconductor device of claim 1 , wherein the first portion forms a closed oval frame in a horizontal cross-section.6. The semiconductor device of claim 1 ...

CHARGE COMPENSATION DEVICE AND MANUFACTURING THEREFOR

A charge-compensation semiconductor device includes a semiconductor body having a first surface, a lateral edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area, and a peripheral area arranged between the active area and the lateral edge. A source metallization is arranged on the first surface. A drain metallization is arranged opposite to the source metallization. The semiconductor body further includes a drift region in Ohmic contact with the drain metallization, and a plurality of compensation regions forming respective pn-junctions with the drift region, which are arranged in the active area and in the peripheral area, and are in Ohmic contact with the source metallization via respective body regions arranged in the active area and having a higher doping concentration than the compensation regions. In a horizontal cross-section substantially parallel to the first surface the compensation regions are at least in a respective portion shaped as a strip oriented in a direction which is tilted with respect to the lateral edge by a tilt angle. 1. A charge-compensation semiconductor device , comprising:a semiconductor body comprising a first surface, a lateral edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area, and a peripheral area arranged between the active area and the lateral edge;a source metallization arranged on the first surface; and a drift region in Ohmic contact with the drain metallization; and', 'a plurality of compensation regions each of which forms a pn-junction with the drift region, is arranged in the active area and in the peripheral area, and is in Ohmic contact with the source metallization via a respective body region which is arranged in the active area and has a higher doping concentration than the compensation regions, in a horizontal cross-section substantially parallel to the first surface the ...

Printed circuit board element and method for producing a printed circuit board element

The invention relates to an electronic component, namely a printed circuit board element comprising a first semiconductor component () which is arranged on an upper side of an electrically conductive intermediate plate () such that a connector pad () of the semiconductor component () is electrically contacted with the intermediate plate () and comprising a second semiconductor component () which is arranged on a lower side of the intermediate plate (). The second semiconductor component () comprises a first connector pad () and a second connector pad (), wherein both connector pads () are aligned in the direction of the intermediate plate () and wherein the first connector pad () is contacted with the intermediate plate (), and wherein the second connector pad () is not contacted with the intermediate plate (). Moreover, the invention relates to a method for producing such a printed circuit board element. 1. A printed circuit board element comprising:a first semiconductor component which is arranged on an upper side of an electrically conductive intermediate plate such that a connector pad of the first semiconductor component has a whole-area electrical contact with the intermediate plate;a second semiconductor component which is arranged on a lower side of the intermediate plate;the second semiconductor component comprises a first connector pad and a second connector pad;both connector pads are aligned in the direction of the intermediate plate; andthe first connector pad is contacted with the intermediate plate, the second connector pad is not contacted with the intermediate plate, and the intermediate plate forms a phase tap of the printed circuit board element.2. The printed circuit board element as claimed in claim 1 , wherein the intermediate plate comprises a recess for avoiding electrical contact between the intermediate plate and the second connector pad of the second semiconductor component.3. The printed circuit board element as claimed in claim 2 , ...

METHOD FOR FORMING HYBRID-BONDING STRUCTURE

A method for forming a hybrid-bonding structure is provided. The method includes forming a first dielectric layer over a first semiconductor substrate. The first semiconductor substrate includes a conductive structure. The method also includes partially removing the first dielectric layer to form a first dielectric dummy pattern, a second dielectric dummy pattern and a third dielectric dummy pattern and an opening through the first dielectric layer. The first dielectric dummy pattern, the second dielectric dummy pattern and the third dielectric dummy pattern are surrounded by the opening. In addition, the method includes forming a first conductive line in the opening. The first conductive line is in contact with the conductive structure. 1. A method for forming a hybrid-bonding structure , comprising:forming a first dielectric layer over a first semiconductor substrate, wherein the first semiconductor substrate comprises a conductive structure;partially removing the first dielectric layer to form a first dielectric dummy pattern, a second dielectric dummy pattern and a third dielectric dummy pattern and an opening through the first dielectric layer, wherein the first dielectric dummy pattern, the second dielectric dummy pattern and the third dielectric dummy pattern are surrounded by the opening; andforming a first conductive line in the opening, wherein the first conductive line is in contact with the conductive structure.2. The method for forming a hybrid-bonding structure as claimed in claim 1 , wherein forming the first conductive line in the opening comprises:depositing a conductive material to fill the opening; andremoving the conductive material outside the opening.3. The method for forming a hybrid-bonding structure as claimed in claim 2 , further comprising:depositing a seed layer to line the opening before depositing a conductive material to fill the opening.4. The method for forming a hybrid-bonding structure as claimed in claim 1 , wherein the opening ...

Electric Magnetic Shielding Structure in Packages

A package includes a device die, a molding material molding the device die therein, and a through-via penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via. A metal ring is close to edges of the package, wherein the metal ring is coplanar with the redistribution line. 1. A method comprising:encapsulating a device die in an encapsulating material; and forming a first portion over the encapsulating material;', 'forming a second portion under the encapsulating material; and', 'forming a plurality of through-vias penetrating through the encapsulating material, wherein the plurality of through-vias electrically connects the first portion to the second portion of the metal shield, and wherein the device die and the metal shield are in a package., 'forming a metal shield to enclose the device die therein, wherein the forming the metal shield comprises2. The method of claim 1 , wherein the forming the first portion of the metal shield comprises forming a metal ring claim 1 , with each side-portion of the metal ring adjacent to and parallel to a respective edge of the package.3. The method of claim 2 , wherein the forming the first portion of the metal shield further comprises forming a metal ring extension encircled by the metal ring claim 2 , wherein the metal ring extension is connected to the metal ring.4. The method of further comprising electrically grounding the metal shield.5. The method of claim 4 , wherein the electrically grounding the metal shield is achieved by electrically connecting the metal shield through a plurality of solder regions claim 4 , each located at a corner of the package.6. The method of claim 1 , wherein the plurality of through-vias comprises four corner through-vias claim 1 , each at a corner of the package claim 1 , and the method further comprises:attaching four solder regions to electrically coupling to the metal shield, each ...

Semiconductor Device Packages, Packaging Methods, and Packaged Semiconductor Devices

Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature. 1. A semiconductor device comprising:a protection pattern located over an encapsulant;a dielectric material isolating the protection pattern, the dielectric material extending from over the encapsulant to over a semiconductor die;conductive redistribution elements within the dielectric material, the conductive redistribution elements electrically connecting the semiconductor die to an external connection; anda packaged semiconductor device connected to the external connection.2. The semiconductor device of claim 1 , wherein the packaged semiconductor device is a package-on-package device.3. The semiconductor device of claim 2 , wherein the package-on-package device comprises dynamic random access memory devices.4. The semiconductor device of claim 1 , wherein the conductive redistribution elements are a same size as conductive elements of the protection pattern.5. The semiconductor device of claim 1 , further comprising through vias extending from a first side of the encapsulant to a second side of the encapsulant.6. The semiconductor device of claim 1 , wherein a portion of the protection pattern material extends beneath the conductive redistribution elements.7. A semiconductor device comprising:a conductive redistribution layer extending over both a first semiconductor device and an encapsulant adjacent to the first semiconductor device;a protection pattern located over the encapsulant, the protection pattern comprising a second conductive ...

DYNAMIC RANDOM ACCESS MEMORY STRUCTURE

A dynamic random access memory (DRAM) structure is provided, and the DRAM structure includes a substrate, a DRAM, and a guard ring structure. The substrate includes a memory cell region. The DRAM is disposed in the memory cell region. The DRAM includes a capacitor contact coupled to a capacitor structure. The guard ring structure surrounds a border of the memory cell region. The capacitor contact and the guard ring structure originate from the same conductive layer. 1. A dynamic random access memory (DRAM) structure , comprising:a substrate, comprising a memory cell region;a DRAM, disposed in the memory cell region, wherein the DRAM comprises a capacitor contact coupled to a capacitor structure; anda guard ring structure, surrounding a border of the memory cell region, wherein the capacitor contact and the guard ring structure originate from the same conductive layer.2. The DRAM structure as claimed in claim 1 , further comprising a stopper layer claim 1 , wherein the stopper layer is disposed on the guard ring structure and covers the memory cell region.3. The DRAM structure as claimed in claim 1 , wherein the DRAM comprises:a buried conductive line, disposed in the substrate;a dielectric layer structure, disposed on the substrate;a conductive line structure, disposed on the substrate and located in the dielectric layer structure;the capacitor contact, disposed in the dielectric layer structure and connected to the substrate; andthe capacitor structure, disposed on the capacitor contact.4. The DRAM structure as claimed in claim 3 , wherein the buried conductive line comprises:a buried conductive layer, disposed in the substrate;a cap layer, disposed on the buried conductive layer; anda dielectric layer, disposed between the buried conductive layer and the substrate.5. The DRAM structure as claimed in claim 1 , wherein the substrate further comprises a peripheral circuit region claim 1 , and the DRAM structure further comprises a transistor structure disposed in the ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a semiconductor layer having a termination region surrounding a device region, the termination region including a first stacked body having a first, insulating, layer located on a surface of the substrate, a second, conductive, layer located over the first layer, and a third, insulating, layer located over the second layer, an opening extending through the first stacked body, a fourth, insulating, layer located in the opening in the first stacked body and over the surface of the semiconductor substrate in the opening, a fifth, insulating, layer, located over the fourth layer, and a wall surrounding the device region, the wall extending inwardly of the opening and contacting one of the surface of the semiconductor substrate or a nitride material on the surface of the substrate, wherein the composition of the third and fifth layers is different from that of the first and third layers. 1. A semiconductor memory device , comprising:a semiconductor substrate comprising a termination region surrounding a device region thereof, the termination region comprising a first stacked body extending around the device region and including a first layer composed of an insulating material located on a surface of the substrate, a second layer composed of a conductive material located over the first layer, and a third layer composed of an insulating material located over the second layer;an opening extending through the first stacked body and extending around the device region;a fourth layer, composed of an insulating material, located in the opening in the first stacked body and over the surface of the semiconductor substrate in the opening;a fifth layer, composed of an insulating material, located over the fourth layer; anda wall surrounding the device region, the wall extending inwardly of the opening and contacting one of the surface of the semiconductor substrate or a nitride material on the surface of the substrate, whereinthe composition of ...

Reduction of electric field enhanced moisture penetration by metal shielding

The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a top electrode overlying a substrate. A passivation layer overlies the top electrode. The passivation layer has a step region that continuously contacts and extends from a top surface of the top electrode to sidewalls of the top electrode. A metal frame overlies the passivation layer. The metal frame continuously contacts and extends from a top surface of the passivation layer to upper sidewalls of the passivation layer in the step region. The metal frame has a protrusion that extends through the passivation layer and contacts the top surface of the top electrode.

MAGNETICALLY COUPLED GALVANICALLY ISOLATED COMMUNICATION USING LEAD FRAME

An integrated circuit package includes a lead frame and an encapsulation that substantially encloses the lead frame. The lead frame further includes a first conductor comprising a first conductive loop and a second conductor galvanically isolated from the first conductor, proximate to and magnetically coupled to the first conductive loop to provide a communication link between the first and second conductor. The second conductor includes a first conductive portion, a second conductive portion, and a wire coupling together the first conductive portion and the second conductive portion. 1. An integrated circuit package , comprising:an encapsulation; and a first conductive loop disposed substantially within the encapsulation;', 'a second conductive loop disposed substantially within the encapsulation and substantially all of the second conductive loop is outside of the first conductive loop; and', 'wherein the first and second conductive loops are configured to form a magnetically coupled communication link.', 'a galvanic isolator coupled to the first conductive loop such that there is galvanic isolation between the first and the second conductive loops,'}], 'a lead frame, a portion of the lead frame disposed within the encapsulation, the lead frame comprising2. The integrated circuit package of claim 1 , further comprising:a first circuit coupled to the first conductive loop; and wherein one of the first and second circuits is configured to control properties of a transmitter current to produce a changing magnetic field in proximity to a corresponding one of the first and second conductive loops, thereby inducing a voltage that is generated across an other one of the first and second conductive loops that is subjected to the changing magnetic field and results in a current flow in the other one of the inner and outer conductive loops, and', 'wherein the other one of the first and second circuits is configured to receive an electrical parameter induced by the one of ...

Semiconductor module

A semiconductor module includes a semiconductor device having a gate runner extending in a first direction at an upper surface of the semiconductor device, and a metal wiring plate having a first bonding portion with a bonding surface to which the upper surface of the semiconductor device is bonded via a first bonding material. The first bonding portion has a plurality of first protrusions at the bonding surface. Each first protrusion protrudes toward the semiconductor device, and is provided in a position away from the gate runner by a first distance in a plan view of the semiconductor module.

Multi-chip package structure

A multi-chip package structure includes outer leads, a first chip and a second chip. The outer leads are disposed on four sides of a chip bonding area of a package carrier thereof, respectively. The first chip is fixed on the chip bonding area and includes a core and a seal ring. Input/output units, and first bonding pads are disposed, in an outward order, on the sides of the core. Each first bonding pad is electrically connected to a corresponding outer lead through a first wire. Dummy pads are disposed between the input/output units and the at least one side of the core. The second chip is stacked on the core and includes second bonding pads connected to the corresponding outer leads through second wires and dummy pads, so as to prevent from short circuit caused by soldering overlap and contact between the wires.

Multichip package manufacturing process

Multichip package manufacturing process is disclosed to form external pins at one side or each side of die-bonding area of package carrier board and to bond first IC and second IC to die-bonding area in stack. First IC and second IC each comprise transistor layer with core circuits, plurality of metal layers, plurality of VIA layers and solder pad layer. During production of first IC, design of at least one metal layer, VIA layer and dummy pads can be modified according to change of design of second IC. After chip probing, die sawing and bonding, wire bonding, packaging and final test are performed to package the package carrier board, first IC and second IC into automotive multichip package, achieving purpose of first IC only need to modify at least one layer or more than one layer to cooperate with second IC design change to carry out multichip packaging process.

APPARATUS COMPRISING A SEMICONDUCTOR ARRANGEMENT

An apparatus comprising: a substrate; an integrated circuit region formed in the substrate; a seal ring disposed in the substrate to form a ring around the integrated circuit region, the seal ring configured to provide for protection against one or more of moisture ingress and ion ingress to the integrated circuit region and crack propagation through the substrate; and a defect sensor comprising a conductive track formed of at least one conductive layer in the substrate, the conductive track disposed outwardly of the seal ring and arranged to at least partially surround the integrated circuit region and seal ring, the conductive track having a first end terminal and a second end terminal to receive a detection signal therebetween to pass through the conductive track to detect a break in the conductive track and thereby a defect in the substrate. 1. An apparatus comprising:a substrate;an integrated circuit region formed in the substrate;a seal ring disposed in the substrate to form a ring around the integrated circuit region, the seal ring configured to provide for protection against one or more of moisture ingress and ion ingress to the integrated circuit region and crack propagation through the substrate; anda defect sensor comprising a conductive track formed of at least one conductive layer in the substrate, the conductive track disposed outwardly of the seal ring and arranged to at least partially surround the integrated circuit region and seal ring, the conductive track having a first end terminal and a second end terminal to receive a detection signal therebetween to pass through the conductive track to detect a break in the conductive track and thereby a defect in the substrate.2. The apparatus of claim 1 , wherein the integrated circuit region includes a defect detection circuitry within the seal ring for providing the detection signal between the first end terminal and the second end terminal3. The apparatus of claim 2 , wherein the connection between the ...

SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE

A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer. 1. A semiconductor device comprising:a substrate that includes four corners;a semiconductor element formed in a region of the substrate;a first insulating film formed above the substrate;a first metal line that extends along an edge of the substrate in a plan view;a second metal line that extends along the edge of the substrate in a plan view;a frame-shaped shield that surrounds the region in a plan view;a second insulating film formed above the first metal line and the second metal line; anda groove formed in the second insulating film and overlapped with the first metal line in a plan view,whereinthe first metal line is located between the frame-shaped shield and the second metal line in a plan view,the first metal line includes a plurality of first wirings and a plurality of first vias,an uppermost wiring of the first wirings is formed in the first insulating film,one of the first wirings and one of the first vias are formed together of a dual damascene structure,the second metal line includes a plurality of second wirings,an uppermost wiring of the second wirings is formed in the first insulating film, andthe frame-shaped shield includes a plurality of third wirings.2. The semiconductor device according to claim 1 , whereinthe frame-shaped shield includes second vias, andone of the third wirings and one of the second vias are formed together of a dual damascene structure.3. The semiconductor device according to claim 2 , further comprising a third insulating film formed above the substrate and ...

GUARD RING METHOD FOR SEMICONDUCTOR DEVICES

A customized seal ring for a semiconductor device is formed of multiple seal ring cells that are selected and arranged to produce a seal ring design. The cells include first cells that are coupled to ground and second cells that are not coupled to ground. The second cells that are not coupled to ground, include a higher density of metal features in an inner portion thereof, than the first seal ring cells. Dummy metal vias and other metal features that may be present in the inner portion of the second seal ring cells are absent from the inner portion of the first seal ring cells that are coupled to ground. The seal ring design may include various arrangements, including alternating and repeating sequences of the different seal ring cells. 1. A method for fabricating an integrated circuit , comprising:fabricating at least one semiconductor device; andfabricating a seal ring surrounding the at least one semiconductor device in a plurality of metal layers, the seal ring comprising first seal ring cells, second seal ring cells, and corner cells, the corner cells located at respective corners of the seal ring, wherein a sequence of abutting first seal ring cells and second seal ring cells extends an entire distance between at least two adjacent corner cells,each of the first seal ring cells including an inner portion having metal vias in each of a plurality of metal layers, said first cells not coupled to ground, and each of the second seal ring cells including an inner portion having a ground connection in at least one of the plurality of metal layers, and metal vias in each of the plurality of metal layers excluding the at least one of the plurality of metal layers having the ground connection.2. The method as in claim 1 , wherein said first seal ring cells and said second seal ring cells are of a same dimension and include substantially identical outer portions.3. The method as in claim 1 , wherein said fabricating includes forming said first and second seal ring cells ...

SEMICONDUCTOR INTEGRATED CIRCUIT

A high-resistance region is formed right under a seal ring by irradiating a semiconductor substrate with hydrogen ions or helium ions. The high-resistance region has a greater thickness than an isolation insulating layer formed as a shallow trench isolation (STI) region on the surface of the semiconductor substrate. As a result, a semiconductor integrated circuit including a seal ring achieving excellent high-frequency isolation is provided. 1. A semiconductor integrated circuit comprising:a semiconductor substrate;a first circuit formed on the semiconductor substrate;a seal ring formed on the semiconductor substrate to surround at least part of the first circuit; anda high-resistance region formed on a propagation path of noise leaking out of or into the first circuit through the seal ring in the semiconductor substrate to have a higher resistivity than a surrounding region, whereinthe high-resistance region is formed by irradiating the semiconductor substrate with ions.2. A semiconductor integrated circuit comprising:a semiconductor substrate;a first circuit formed on the semiconductor substrate;a seal ring formed on the semiconductor substrate to surround at least part of the first circuit; anda high-resistance region formed on a propagation path of noise leaking out of or into the first circuit through the seal ring in the semiconductor substrate to have a higher resistivity than a surrounding region, whereinthe high-resistance region contains hydrogen or helium.3. The semiconductor integrated circuit of claim 1 , whereinthe resistivity of the high-resistance region is ten times or more as high as that of the surrounding region.4. The semiconductor integrated circuit of claim 1 , whereinthe high-resistance region is located within a depth of 10 μm from a surface of the semiconductor substrate.5. The semiconductor integrated circuit of claim 1 , whereinthe high-resistance region is deeper than a well formed in a surface of the semiconductor substrate.6. The ...

Electronic device and connection body

An electronic device has a sealing part 90 , a first main terminal 11 protruding outward from the sealing part 90 , a second main terminal 12 protruding outwardly from the sealing part, an electronic element 95 provided in the sealing part and having a front surface electrically connected to the first main terminal 11 and a back surface electrically connected to the second main terminal 12 , a head part 40 connected to the front surface of the electronic element 95 , a sensing terminal 13 protruding to an outside from the sealing part 90 and used for sensing and a connection part 35 integrally formed with the head part 40 and electrically connected to the sensing terminal 13 . A current flowing through the sensing terminal 13 and the connection part 35 among a sensing current path does not overlap a main current path flowing through the second main terminal 12 , the electronic element 95 and the first main terminal 11.

Packaged Electronic Module and Manufacturing Method Thereof

The present invention is a packaged electronic module with embedded electronics for use in smart cards. This invention assembles a plurality of electronics components on a flexible printed circuit, together with an integrated circuit chip and a contact plate, into a module. This module can then be embedded into a plastic card, using regular milling techniques, by a card manufacturer. This method packages the plurality of electronics components into a module. The present invention provides a business with the capability to avoid additional capital expenditure required for special equipment and enables all existing card manufacturers to manufacture smart cards with embedded electronics.

ELECTRONIC DEVICE, MANUFACTURING METHOD OF THE SAME, AND NETWORK SYSTEM

An electronic device includes: a substrate; a first all-solid-state secondary cell provided on the substrate, the first all-solid-state secondary cell including a first electrode layer, a solid electrolyte layer, and a second electrode layer; a first transistor including a first source drain, a second source drain electrically connected to the second electrode layer, and a first gate electrode; a first terminal electrically connected to the first electrode layer; a second terminal to control a potential of the first gate electrode; a third terminal electrically connected to the first source drain; and a sealing layer covering the first all-solid-state secondary cell and the first transistor, wherein the first terminal, the second terminal, and the third terminal are exposed on an upper surface of the sealing layer. 1. An electronic device comprising:a substrate;a first all-solid-state secondary cell provided on the substrate, the first all-solid-state secondary cell including a first electrode layer, a solid electrolyte layer, and a second electrode layer;a first transistor including a first source drain, a second source drain electrically connected to the second electrode layer, and a first gate electrode;a first terminal electrically connected to the first electrode layer;a second terminal to control a potential of the first gate electrode;a third terminal electrically connected to the first source drain; anda sealing layer covering the first all-solid-state secondary cell and the first transistor, whereinthe first terminal, the second terminal, and the third terminal are exposed on an upper surface of the sealing layer.2. The electronic device according to claim 1 , whereinthe first electrode layer is a negative electrode,the second electrode layer is a positive electrode, andthe first transistor is of an n type.3. The electronic device according to claim 1 , further comprising an n type second transistor covered with the sealing layer claim 1 , the second ...

Methods of Packaging Semiconductor Devices and Packaged Semiconductor Devices

Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a dam structure on dies proximate edge regions of the dies. A molding material is disposed around the dies, and a top portion of the molding material and a top portion of the dam structure are removed. 1. A method of packaging a semiconductor device , the method comprising:forming a dam structure on a plurality of dies proximate edge regions of the plurality of dies;disposing a molding material around the plurality of dies; andremoving a top portion of the molding material and a top portion of the dam structure.2. The method according to claim 1 , wherein removing the top portion of the molding material and the top portion of the dam structure comprises a grinding process or a chemical-mechanical polishing (CMP) process.3. The method according to claim 1 , wherein removing the top portion of the molding material comprises removing a portion of the molding material proximate the dam structure.4. The method according to claim 1 , further comprising forming an interconnect structure over the plurality of dies and the molding material.5. The method according to claim 4 , further comprising coupling a plurality of connectors to the interconnect structure.6. The method according to claim 4 , wherein forming the interconnect structure comprises forming fan-out regions.7. The method according to claim 4 , wherein forming the interconnect structure comprises forming a post-passivation interconnect (PPI) structure or a redistribution layer (RDL).8. A method of packaging a semiconductor device claim 4 , the method comprising:coupling a plurality of dies to a carrier;forming a dam structure on each of the plurality of dies proximate edge regions of the plurality of dies;disposing a molding material over the carrier around the plurality of dies;removing a top portion of the molding material and a top ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor substrate including a main surface with a polygonal geometry and a main electric circuit manufactured within a main region on the semiconductor substrate. The main electric circuit is operable to perform an electric main function. The main region extends over the main surface of the semiconductor substrate leaving open at least one corner area at a corner of the polygonal geometry of the main surface of the semiconductor substrate. The corner area extends at least 300 μm along the edges of the semiconductor substrate beginning at the corner. 1. A power semiconductor device comprising:a semiconductor substrate comprising a main surface with a polygonal geometry; anda main electric circuit manufactured within a main region on the semiconductor substrate, wherein the main electric circuit is operable to perform an electric main function, wherein at least one active element of the main electric circuit comprises a breakdown voltage higher than 10V,wherein the main region extends over the main surface of the semiconductor substrate leaving open at least one corner area at a corner of the polygonal geometry of the main surface of the semiconductor substrate, wherein the corner area extends at least 300 μm along the edges of the semiconductor substrate beginning at the corner.2. The power semiconductor device according to claim 1 , wherein the main region extends over the main surface of the semiconductor substrate leaving open a corner area at every corner of the polygonal geometry of the main surface of the semiconductor substrate claim 1 , wherein each corner area extends at least 300 μm along the edges of the semiconductor substrate beginning at the respective corners.3. The power semiconductor device according to claim 1 , wherein the at least one corner area extends at least over a triangle area claim 1 , wherein the corner of the at least one corner area is a corner of the triangle and the edges of semiconductor ...

SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME

A semiconductor device includes a plurality of transistor components disposed on a semiconductor substrate, and a guard ring disposed on the semiconductor substrate surrounding the transistor components. The guard ring includes a plurality of fin structures disposed in parallel on the semiconductor substrate, a plurality of first conductive connection members disposed on the fin structures and connecting at least two fin structures, and a plurality of second conductive connection members connecting at least two first conductive connection members. The first conductive connection members and the second conductive connection members are formed as one structure. 1. A semiconductor device comprising:a plurality of transistor components disposed on a semiconductor substrate; a plurality of fin structures disposed in parallel on the semiconductor substrate;', 'a plurality of first conductive connection members disposed on the fin structures and connecting at least two fin structures; and', 'a plurality of second conductive connection members connecting at least two first conductive connection members,', 'wherein the first conductive connection members and the second conductive connection members are formed as one structure., 'a guard ring disposed on the semiconductor substrate surrounding the transistor components, wherein the guard ring comprises2. The semiconductor device according to claim 1 , wherein the first conductive connection members and the second conductive connection members are formed in a mesh configuration.3. The semiconductor device according to claim 1 , wherein the second conductive connection member is perpendicular to the first conductive connection member.4. The semiconductor device according to claim 1 , wherein the second conductive connection members have a same width claim 1 , and wherein adjacent second conductive connection members are spaced apart by a same distance.5. The semiconductor device according to claim 1 , wherein the first ...

Crack Stop Barrier and Method of Manufacturing Thereof

A semiconductor device includes a chip, a first kerf adjacent the chip and having a first main direction, a second kerf adjacent the chip and having a second main direction. A kerf junction is formed by the first kerf and the second kerf. A crack stop barrier is located along a first portion of a perimeter of the kerf junction. 1. A semiconductor device comprising:a chip;a first kerf adjacent the chip and having a first main direction;a second kerf adjacent the chip and having a second main direction;a kerf junction formed by the first kerf and the second kerf; anda first crack stop barrier located along a first portion of a perimeter of the kerf junction.2. The device of claim 1 , wherein the first crack stop barrier extends in the first main direction into the second kerf.3. The device of claim 1 , wherein a second crack stop barrier is located along a second portion of the perimeter of the kerf junction.4. The device of claim 3 , wherein the second crack stop barrier extends in the second main direction into the first kerf.5. The device of claim 1 , wherein the first crack stop barrier comprises a width of about 3 μm to about 12 μm.6. The device of claim 1 , wherein the first crack stop barrier comprises a single barrier line.7. The device of claim 1 , wherein the first crack stop barrier comprises a plurality of barrier lines.8. The device of claim 1 , wherein the first crack stop barrier comprises sawtooth or zigzag lines.9. A semiconductor device comprising:a chip;a first kerf adjacent the chip and having a first main direction;a second kerf adjacent the chip and having a second main direction;a kerf junction formed by the first kerf and the second kerf;a first crack stop barrier disposed around the chip, the first crack stop barrier having a first section oriented in the first main direction; anda second crack stop barrier oriented in the first main direction disposed along a first portion of a perimeter of the kerf junction, the second crack stop barrier ...

THREE-DIMENSIONAL STACKING STRUCTURE

A three-dimensional stacking structure is described. The stacking structure includes at least a bottom die, a top die and a spacer protective structure. The bottom die includes contact pads in the non-bonding region. The top die is stacked on the bottom die without covering the contact pads of the bottom die and the bottom die is bonded with the top die through bonding structures there-between. The spacer protective structure is disposed on the bottom die and covers the top die to protect the top die. By forming an anti-bonding layer before stacking the top dies to the bottom dies, the top die can be partially removed to expose the contact pads of the bottom die for further connection. 1. A stacking structure , comprising:a first die, having a first bonding structure, wherein the first bonding structure comprises contact pads;a second die, having a second bonding structure, wherein the second die is stacked on the first die, and the second bonding structure is bonded with the first bonding structure;a spacer protective structure, disposed over the first die and surrounding the second die, wherein the spacer protective structure covers sidewalls of the second die; andan anti-bonding layer, disposed over the first die and located between the spacer protective structure and the first die.2. The structure of claim 1 , wherein the first bonding structure further comprises first bonding elements embedded in a first dielectric material claim 1 , and the second bonding structure comprises second bonding elements embedded in a second dielectric material.3. The structure of claim 2 , wherein the second bonding structure is bonded with the first bonding structure through the bonding of the first and second bonding elements and the bonding of the first and second dielectric materials.4. The structure of claim 2 , wherein the second bonding structure further comprises at least one seal ring structure embedded within the second dielectric material claim 2 , arranged along a ...

Semiconductor Device Having Shielding Structure

The present invention provides a semiconductor device with a shielding structure. The semiconductor device includes a substrate, an RF circuit, a shielding structure and an interconnection system. The substrate includes an active side and a back side. The RF circuit is disposed on the active side of the substrate. The shielding structure is disposed on the active side and encompasses the RF circuit. The shielding structure is grounded. The shielding structure includes a shielding TST which does not penetrate through the substrate. The interconnection system is disposed on the active side of the substrate. The interconnection system includes a connecting unit electrically connect a signal to the RF circuit.

SEMICONDUCTOR STRUCTURE

A semiconductor structure includes a semiconductor device, a plurality of through semiconductor vias (TSV), a first seal ring, and a second seal ring. The TSVs penetrate through the semiconductor device. The TSVs are adjacent to an edge of the semiconductor device. The first seal ring is disposed on and physically connected to one end of each of the TSVs. The second seal ring is disposed on and physically connected to another end of each of the TSVs. 1. A semiconductor structure , comprising:a semiconductor device;a plurality of through semiconductor vias (TSV) penetrating through the semiconductor device, wherein the plurality of TSVs is adjacent to an edge of the semiconductor device;a first seal ring, disposed on and physically connected to one end of each of the plurality of TSVs; anda second seal ring, disposed on and physically connected to another end of each of the plurality of TSVs.2. The semiconductor structure according to claim 1 , wherein the plurality of TSVs comprises polygonal columns claim 1 , cylindrical columns claim 1 , or elliptical columns.3. The semiconductor structure according to claim 2 , wherein a width or a diameter of each TSV ranges between 1 μm and 100 μm claim 2 , and a minimum distance between two adjacent TSVs ranges between 1 μm and 100 μm.4. The semiconductor structure according to claim 1 , wherein the first seal ring and the second seal ring are respectively a single seal ring loop pattern.5. The semiconductor structure according to claim 4 , wherein the plurality of TSVs physically connects the seal ring loop pattern of the first seal ring and the seal ring loop pattern of the second seal ring.6. The semiconductor structure according to claim 1 , wherein the first seal ring and the second seal ring are respectively a multiple seal ring loop pattern claim 1 , the multiple seal ring loop pattern comprises a first seal ring loop pattern and a second seal ring loop pattern surrounding the first seal ring loop pattern.7. The ...

METAL-FREE FRAME DESIGN FOR SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES

Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate. 1. A semiconductor structure , comprising:a substrate having an insulating layer thereon, the substrate having a perimeter, and the substrate comprising silicon;a metallization structure on the insulating layer, the metallization structure comprising conductive routing in a dielectric material stack;a first metal guard ring in the dielectric material stack and continuous around the conductive routing;a second metal guard ring in the dielectric material stack and continuous around the first metal guard ring;a plurality of staggered mini guard rings between the first metal guard ring and the second metal guard ring; anda metal-free region of the dielectric material stack surrounding the second metal guard ring, the metal-free region adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.2. The semiconductor structure of claim 1 , wherein at least one of the first metal guard ring or the second metal guard ring provides a hermetic seal for the metallization structure.3. The semiconductor structure of claim 1 , further comprising:a metal feature between the first metal ...

CELL-MOUNTED MONOLITHIC INTEGRATED CIRCUIT FOR MEASURING, PROCESSING, AND COMMUNICATING CELL PARAMETERS

A battery system has a battery cell including a can, and a ceramic substrate, including a patterned metallized surface, mounted to the can via a thermally conductive adhesive. The battery system also has a monolithic integrated circuit that measures and transmits data about the cell mounted to the patterned metallized surface such that the ceramic substrate and monolithic integrated circuit are electrically isolated from one another. 1. A battery system comprising:a battery cell including a can;a ceramic substrate, including a patterned metallized surface, mounted to the can via a thermally conductive adhesive; anda monolithic integrated circuit configured to measure and transmit data about the cell mounted to the patterned metallized surface such that the ceramic substrate and monolithic integrated circuit are electrically isolated from one another.2. The battery system of claim 1 , wherein the patterned metallized surface defines traces electrically connected with the monolithic integrated circuit.3. The battery system of claim 2 , wherein the monolithic integrated circuit includes solder bumps in contact with the traces.4. The battery system of claim 2 , wherein the monolithic integrated circuit includes a bonding pad wire bonded to the traces.5. The battery system of claim 1 , wherein the data is current data claim 1 , temperature data claim 1 , or voltage data.6. The battery system of claim 1 , wherein the patterned metallized surface includes aluminum or copper.7. A battery system comprising:a battery cell including a can;a ceramic substrate, including opposing metallized surfaces and a metal via extending between the metallized surfaces, mounted to the can via an electrically and thermally conductive adhesive that is in contact with one of the metallized surfaces; anda monolithic integrated circuit mounted to another of the metallized surfaces and configured to measure and transmit data about the battery cell.8. The battery system of claim 7 , wherein the ...

FLEX LEAD ON CELL CONTAINER FOR ELECTROMAGNETIC SHIELDING

A battery system has a battery cell including a can and tabs, flexible circuits on and electrically isolated from the can, and electrically connected with the tabs, and a monolithic integrated circuit. The monolithic integrated circuit is mounted to the can via thermally conductive adhesive such that the can and monolithic integrated circuit are electrically isolated from one another. The monolithic integrated circuit is also wire bonded to the flexible circuits, and configured to measure and transmit data about the battery cell. 1. A battery system comprising:a battery cell including a can and tabs;flexible circuits on and electrically isolated from the can, and electrically connected with the tabs; and mounted to the can via thermally conductive adhesive such that the can and monolithic integrated circuit are electrically isolated from one another,', 'wire bonded to the flexible circuits, and', 'configured to measure and transmit data about the battery cell., 'a monolithic integrated circuit'}2. The battery system of claim 1 , wherein the monolithic integrated circuit includes bonding pads electrically connected with the flexible circuits.3. The battery system of claim 1 , wherein the data is current data claim 1 , temperature data claim 1 , or voltage data.4. The battery system of claim 1 , wherein the flexible circuits are flexible printed circuits.5. A battery system comprising:a battery cell including a can and tabs;flexible circuits on the can and electrically connected with the tabs; andcircuitry adhered to the can, wire bonded to the flexible circuits, and configured to measure and transmit data about the battery cell.6. The battery system of claim 5 , wherein the circuitry is adhered to the can via a thermally conductive adhesive.7. The battery system of claim 5 , wherein the flexible circuits are electrically isolated from the can.8. The battery system of claim 5 , wherein the circuitry includes bonding pads electrically connected with the flexible ...

CAPACITOR SENSOR STRUCTURE, CIRCUIT BOARD STRUCTURE WITH CAPACITOR SENSOR, AND PACKAGE STRUCTURE OF CAPACITIVE SENSOR

A capacitive sensor structure includes: a substrate; a multilayer wire structure, disposed on the substrate to form a passive sensing circuit; and a semiconductor chip, formed thereon a control circuit, fixedly mounted on a surface of the substrate and electrically connected to the multilayer wire structure. 1. A capacitive fingerprint sensor structure , comprising:a substrate;a multilayer wire structure, disposed on the substrate, comprising a plurality of sensing electrodes to form a passive sensing circuit; anda semiconductor chip, fixedly mounted on a surface of the substrate, electrically connected to the multilayer wire structure;wherein, the multilayer wire structure is formed by a redistribution layer (RDL) process.2. The capacitive fingerprint sensor structure according to claim 1 , wherein the multilayer wire structure is formed by at least one of an un-doped intrinsic semiconductor material claim 1 , a precision high-purity alumina ceramic substrate claim 1 , a packaging molding material claim 1 , and a packaging liquid material.3. The capacitive fingerprint sensor structure according to claim 1 , wherein the semiconductor chip is electrically connected to the multilayer wire structure on the substrate by a flip-chip method and via at least one bonding pad structure.4. The capacitive fingerprint sensor structure according to claim 3 , wherein the substrate further comprises an interconnection terminal and a stiffener metal ring formed on the multilayer wire structure.5. The capacitive fingerprint sensor structure according to claim 3 , wherein the substrate further comprises at least one through-base via (TBV) to electrically conduct the multilayer wire structure and the semiconductor chip claim 3 , a protection layer is further disposed above an upper surface of the substrate claim 3 , and the protection layer is formed by one of a ceramic adhesive and a hard coating.6. The capacitive fingerprint sensor structure according to claim 1 , wherein the ...

Gap-filling dielectric layer method for manufacturing the same and applications thereof

A gap-filling dielectric layer, method for fabricating the same and applications thereof are disclosed. A silicon-containing dielectric layer is firstly deposited on a substrate. The silicon-containing dielectric layer is then subjected to a curing process, an in-situ wetting treatment and an annealing process in sequence, whereby a gap-filling dielectric layer with a nitrogen atom density less than 1×10 22 atoms/cm 3 is formed.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a substrate defined with a seal ring region and a circuit region, the substrate includes a seal ring structure and an integrated circuit structure, the seal ring structure is disposed in the seal ring region and includes a plurality of stacked conductive layers interconnected by a plurality of via layers, the integrated circuit structure is disposed in the circuit region and includes an active or a passive device; a metal pad disposed over the seal ring region and contacted with the seal ring structure; a passivation layer disposed over the substrate and covering the metal pad; a polymeric layer disposed over the passivation layer and the circuit region; and a molding disposed over the passivation layer and the polymeric layer, wherein the seal ring structure is covered by the molding.

Semiconductor device and semiconductor system

A semiconductor device is provided. The semiconductor device includes a seal ring and a noise-absorbing circuit. The noise-absorbing circuit is electrically connected between the seal ring and a ground pad. The noise-absorbing circuit includes at least one capacitor and at least one inductor to form a first noise-absorbing path, a second noise-absorbing path and a third noise-absorbing path.

SEMICONDUCTOR DEVICE

The present disclosure provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Vias are formed in each layer on a dicing region side. The vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented. 1. A semiconductor device having a first region , a second region and a third region , and the first region , the second region and the third region are arranged toward the inside from the outside in this order , a circuit formation region is arranged in the third region and a seal ring is arranged in the second region in a plan view , comprising:a silicon substrate;a first interlayer insulating film formed over the silicon substrate;a first interconnecting layer and a first slit via each formed within the first interlayer insulating film; anda first single metal and a plurality of first vias formed in the first interlayer insulating film, and disposed in the first region,wherein the first interconnecting layer and the first slit via form the seal ring,wherein the plurality of first vias are disposed under the first single metal, andwherein the plurality of first vias are connected to the first single metal.2. The semiconductor device according to claim 1 , wherein the first interlayer insulating film is a carbon-containing silicon oxide film.3. The semiconductor device according to claim 1 , wherein the seal ring surrounds the circuit formation region.4. The semiconductor device according to claim 1 , wherein the slit via is longer than each of the first via.5. The semiconductor ...

PACKAGE STRUCTURE

A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread. 1. A package structure , comprising:a bottom plate;a wafer level package, disposed over the bottom plate, and the wafer level package comprising and insulating encapsulant, at least one die encapsulated by the insulating encapsulant and at least one device stacked over the at least one die;a top plate, disposed over the wafer level package, and the top plate comprising an internal thread in a screw hole of the top plate;a buffer layer, disposed between the wafer level package and the top plate, wherein the buffer layer comprises an opening aligned with the screw hole of the top plate;a first thermal interface material (TIM) disposed between the at least one device and the top plate, wherein the first TIM is embedded in and in contact with the buffer layer; anda screw, penetrating through the bottom plate, the wafer level package and the screw hole of the top plate, and the screw comprising an external thread engaged to the internal thread of the top plate.2. The package structure as claimed in claim 1 , wherein the buffer layer is in contact with the at least one device claim 1 , and the buffer layer is not in contact with the insulating encapsulant.3. The package structure as claimed in claim 1 , wherein the screw further comprises a main portion and a head portion connected to the main portion claim 1 , the external thread is on an external surface of the main ...

Packaged Semiconductor Device Including Liquid-Cooled Lid and Methods of Forming the Same

Semiconductor devices including lids having liquid-cooled channels and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first integrated circuit die; a lid coupled to the first integrated circuit die, the lid including a plurality of channels in a surface of the lid opposite the first integrated circuit die; a cooling cover coupled to the lid opposite the first integrated circuit die; and a heat transfer unit coupled to the cooling cover through a pipe fitting, the heat transfer unit being configured to supply a liquid coolant to the plurality of channels through the cooling cover. 1. A semiconductor device comprising:a first integrated circuit die;a lid coupled to the first integrated circuit die, the lid comprising a plurality of channels in a surface of the lid opposite the first integrated circuit die;a cooling cover coupled to the lid opposite the first integrated circuit die; anda heat transfer unit coupled to the cooling cover through a pipe fitting, wherein the heat transfer unit is configured to supply a liquid coolant to the plurality of channels through the cooling cover.2. The semiconductor device of claim 1 , wherein the lid is coupled to the first integrated circuit die by dielectric-to-dielectric bonds.3. The semiconductor device of claim 1 , further comprising an encapsulant laterally surrounding the first integrated circuit die claim 1 , wherein the lid is coupled to the encapsulant by dielectric-to-dielectric bonds.4. The semiconductor device of claim 1 , further comprising an encapsulant laterally surrounding the first integrated circuit die claim 1 , wherein a width of the lid is equal to a width of the first integrated circuit die.5. The semiconductor device of claim 1 , further comprising an encapsulant laterally surrounding the first integrated circuit die claim 1 , wherein a width of the lid is equal to a width of the cooling cover and greater than a width of the encapsulant.6. The semiconductor ...

EXTENDED SEAL RING STRUCTURE ON WAFER-STACKING

Embodiments include a wafer-on-wafer bonding where each wafer includes a seal ring structure around die areas defined in the wafer. Embodiments provide a further seal ring spanning the interface between the wafers. Embodiments may extend the existing seal rings of the wafers, provide an extended seal ring structure separate from the existing seal rings of the wafers, or combinations thereof. 1. A package device comprising: a first seal ring structure disposed around a periphery of the first die in a first interconnect of the first die,', 'a first dielectric layer over the first interconnect, and', 'a first seal ring extension disposed in the first dielectric layer, the first seal ring extension aligned with and physically coupled to the first seal ring structure, the first seal ring extension extending continuously around the periphery of the first die; and, 'a first die comprising a second dielectric layer disposed under a second interconnect, and', 'a second seal ring extension disposed in the second dielectric layer, the second seal ring extension aligned with and physically coupled to the first seal ring extension., 'a second die comprising2. The package device of claim 1 , wherein the first seal ring extension and the second seal ring extension are physically coupled by a direct metal-to-metal bond without a eutectic material formed there between.3. The package device of claim 1 , wherein an air gap between the first die and the second die is sealed by the coupled first seal ring extension and the second seal ring extension.4. The package device of claim 1 , wherein the first seal ring extension and the second seal ring extension are offset by a lateral distance.5. The package device of claim 1 , further comprising a third seal ring extension extending through the second die and into the first die claim 1 , the third seal ring surrounding first connectors of the first die and second connectors of the second die.6. The package device of claim 5 , wherein the ...

Multi-layer semiconductor package with stacked passive components

A semiconductor package includes a first layer including a semiconductor die embedded within a dielectric substrate, and a first set of metal pillars extending through the dielectric substrate, a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer, and a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.

SEAL RING STRUCTURES WITH REDUCED MOISTURE-INDUCED RELIABILITY DEGRADATION

A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening. 1. An integrated circuit structure comprising:a semiconductor chip;a seal ring adjacent to edges of the semiconductor chip;an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening extends from a region encircled by the seal ring to a region outside the seal ring, and wherein the seal ring comprises a first end and a second end facing each other, with the opening between the first end and the second end;a first moisture barrier connected to the first end of the seal ring; anda second moisture barrier connected to the first end of the seal ring, wherein each of the first moisture barrier and the second moisture barrier comprises a first portion, and wherein the first portions of the first moisture barrier and the second moisture barrier are on opposite sides of, and are aligned to, the opening.2. The integrated circuit structure of claim 1 , wherein each of the first moisture barrier and the second moisture barrier comprises a second portion claim 1 , and wherein the second portions of the first moisture barrier and the second moisture barrier are on opposite sides of claim 1 , and are aligned to claim 1 , a portion of the seal ring claim 1 , with the second end of the seal ring being an end of the portion of the seal ring.3. The integrated circuit structure of claim 1 , wherein the opening and the first portion of the first moisture barrier have a distance comparable to a width of the opening.4. The integrated circuit structure of claim 1 , wherein the first moisture ...

Semiconductor device

A semiconductor device includes: on an upper surface of a second semiconductor chip on a circuit board, a ring dam section formed at an outer circumference of a mounting region above which a first semiconductor chip is mounted; and an interconnect extending from the dam section to a center section of the first semiconductor chip or the second semiconductor chip in a region in which the first semiconductor chip faces the second semiconductor chip. The interconnect is electrically connected to a connection terminal on a circuit formation surface of the first or second semiconductor chip at the center section of the first or second semiconductor chip. The dam section and the interconnect are power supply interconnects or ground interconnects.

Semiconductor device

A semiconductor device includes an extended semiconductor chip including a first semiconductor chip and an extension outwardly extending from a side surface of the first semiconductor chip; and a second semiconductor chip connected to the extended semiconductor chip through a plurality of bumps and electrically connected to the first semiconductor chip. The first semiconductor chip is smaller than the second semiconductor chip. At least one external terminal is provided on the extension.

INTEGRATED CIRCUIT APPARATUS

An integrated circuit apparatus includes a substrate, an IC chip disposed above the substrate, and an electromagnetic shielding layer disposed on a surface of the substrate. The IC chip includes an electromagnetic coupling device. The electromagnetic shielding layer and the electromagnetic coupling device partially overlap in a vertical projection direction of the surface of the substrate. 1. An integrated circuit (IC) apparatus comprising:a substrate;an IC chip disposed above the substrate, the IC chip comprising an electromagnetic coupling device; andan electromagnetic shielding layer disposed on a surface of the substrate, wherein the electromagnetic shielding layer and the electromagnetic coupling device partially overlap in a vertical projection direction of the surface of the substrate.2. The integrated circuit apparatus of claim 1 , wherein the electromagnetic shielding layer comprises a symmetric pattern.3. The integrated circuit apparatus of claim 2 , wherein the symmetric pattern is a radial pattern.4. The integrated circuit apparatus of claim 3 , wherein the radial pattern is a star-shaped pattern or a snowflake-shaped pattern.5. The integrated circuit apparatus of claim 2 , wherein the electromagnetic shielding layer further comprises a frame pattern circling the symmetric pattern claim 2 , and the frame pattern and the symmetric pattern are connected to each other.6. The integrated circuit apparatus of claim 5 , wherein the frame pattern and the symmetric pattern are connected to each other through a branch of the symmetric pattern.7. The integrated circuit apparatus of claim 1 , wherein the electromagnetic shielding layer has a closed-loop pattern.8. The integrated circuit apparatus of claim 1 , wherein the electromagnetic shielding layer has an opened-loop pattern.9. The integrated circuit apparatus of claim 1 , wherein the electromagnetic shielding layer is floating.10. The integrated circuit apparatus of claim 1 , wherein the electromagnetic ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor layer including a wide bandgap semiconductor, the semiconductor layer having an element region and an outer peripheral region surrounding an outer periphery of the element region when viewed two-dimensionally, forming a step portion surrounding the outer periphery of the element region in the outer peripheral region, and forming a metal layer along the step portion. The step portion has a sidewall recessed downward from a main surface of the element region in a cross section parallel to a thickness direction of the semiconductor layer, and the metal layer extends to cover at least a portion of the sidewall. The method of manufacturing a semiconductor device further includes the step of dividing the semiconductor layer into the element regions on an outside of the step portion when viewed from the element region. 111.-. (canceled)12. A semiconductor device comprising:a semiconductor layer including a wide bandgap semiconductor, said semiconductor layer having an element region and an outer peripheral region surrounding an outer periphery of said element region when viewed two-dimensionally;a step portion formed in said outer peripheral region and surrounding said outer periphery of said element region; anda metal layer formed along said step portion,said step portion having a sidewall recessed downward from a main surface of said element region in a cross section parallel to a thickness direction of said semiconductor layer, said metal layer extending to cover at least a portion of said sidewall.13. The semiconductor device according to claim 12 , further comprising a first insulating film formed on said semiconductor layer claim 12 , whereinsaid metal layer covers an end face of said first insulating film.14. The semiconductor device according to claim 12 , whereinan inner peripheral surface including said sidewall is continuous with an outer peripheral end face of said ...

CRACK DETECTION CHIP AND CRACK DETECTION METHOD USING THE SAME

A crack detection chip includes a chip which includes an internal region and an external region surrounding the internal region, a guard ring formed inside the chip along an edge of the chip to define the internal region and the external region, an edge wiring disposed along an edge of the internal region in the form of a closed curve and a pad which is exposed on a surface of the chip and is connected to the edge wiring. The edge wiring is connected to a Time Domain Reflectometry (TDR) module which applies an incident wave to the edge wiring through the pad, and detects a reflected wave formed in the edge wiring to detect a position of a crack. 1. A semiconductor chip configured to apply an incident wave , and detect a reflected wave formed in response to the incident wave to detect a position of a crack ,the semiconductor chip comprising:a chip which includes an internal region and an external region surrounding the internal region;a guard ring formed inside the chip, extending from an upper surface of the chip, and along an edge of the chip to define the internal region and the external region;a pad which is exposed on a surface of the chip; andan edge wiring disposed along an edge of the internal region in a form of a closed curve and connected to the pad,wherein the incident wave is applied to the edge wiring through the pad.2. The semiconductor chip of claim 1 , wherein the guard ring comprises first and second guard rings claim 1 , anda distance between the first guard ring and the internal region is larger than a distance between the second guard ring and the internal region.3. The semiconductor chip of claim 1 , wherein a direction of the upper surface of the chip is a first direction claim 1 , anda width of the guard ring in the first direction is larger than a width of the edge wiring in the first direction.4. The semiconductor chip of claim 1 , further comprising:a current input module connected to the edge wiring and configured to apply a heat ...

Packaging Devices and Methods of Manufacture Thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming an interconnect wiring over a substrate, and forming conductive balls over portions of the interconnect wiring. A molding material is deposited over the conductive balls and the substrate, and a portion of the molding material is removed from over scribe line regions of the substrate. 1. A packaging device comprising:a contact pad over a circuit region of a substrate, the substrate comprising a seal ring proximate a perimeter of the circuit region;a passivation layer over the substrate and over a first portion of the contact pad;a post passivation interconnect (PPI) structure over the passivation layer, wherein the PPI structure is coupled to a second portion of the contact pad;a conductive ball coupled to the PPI structure; anda molding material around the conductive ball, over the PPI structure, and over the passivation layer, wherein the molding material comprises a first thickness directly over the seal ring and a second thickness proximate the conductive ball, the second thickness being greater than the first thickness.2. The package device of claim 1 , wherein the molding material comprises:a first upper surface directly over the seal ring;a second upper surface proximate the conductive ball; anda slanted sidewall connecting the first upper surface and the second upper surface.3. The package device of claim 1 , wherein the conductive ball extends above an uppermost surface of the molding material.4. The package device of claim 1 , wherein the first thickness is about 30 μm or less.5. The package device of claim 1 , wherein the seal ring extends from a first surface of the passivation layer distal the substrate to a second surface of the passivation layer opposing the first surface.6. The package device of claim 5 , wherein the seal ring further extends into the substrate.7. The package ...