Rectifier for three=phase alternator of motor vehicle

The rectifier includes at least one diode, several diode chip terminals (22,24) and a cooler body (12,14). The diode is coupled to a construction part in a thermally and electrically conductive manner. The diode as a chip (20) is fitted between two of the terminals, of which one is in contact with the construction part. The diode chip terminals are embedded in a hard cast (42) on the cooler body. Pref the hard cast is a hardenable plastic, such as based on epoxy resin. A solder (26) may be used for contacting the diode chip to the terminals, formed typically by on platelets. The solder may be of a high-melt soft type.

MOS-Halbleiteranordnung

MOS-Halbleiteranordnung mit einem Halbleitersubstrat, einem Halbleiterelement (4) in MOS-Ausführung mit einer ersten Elektrode, einer zweiten Elektrode und einer Gateelektrode als Steuereingang eines Steuerabschnitts mit MOS-Aufbau, einem mit der ersten Elektrode verbundenen ersten Ausgangsanschluß (S) und einem mit der zweiten Elektrode verbundenen zweiten Ausgangsanschluß (D), einem Steuereingangsanschluß (G), einer internen Steuerschaltung (9), die zwischen den Steuereingangsanschluß (G) und die Gateelektrode (g) des Halbleiterelements (4) geschaltet ist, und einer Schutzeinrichtung (Z1p, Z21, Z3pr), die zwischen den Steuereingangsanschluß (G) und den ersten Ausgangsanschluß (S) geschaltet ist und zum Schutz gegen Überspannungen dient, sowie einen ersten Zweig, der eine erste Zenerdiode (Z1p) enthält, die eine auf einem isolierenden Film auf dem Halbleitersubstrat aufgebrachte Polysiliciumschicht aufweist, und einen zweiten Zweig umfaßt, der eine zweite Zenerdiode (Z21), die in einer ...

Verfahren zur Herstellung von Halbleiter-Gleichrichteranordnungen mit tablettenförmigen Gleichrichterelementen

Halbleiter-Gleichrichteranordnung mit tablettenförmigen Gleichrichterelementen

Machine comprenant deux électrodes alimentées par un dispositif redresseur à double alternance

Electric motor and method for producing said motor

CASE FOR A PLURALITY OF SEMICONDUCTOR DEVICES

ENSEMBLE DE DISPOSITIFS ELECTRONIQUES A SEMI-CONDUCTEURS MONTES SUR RADIATEUR

L'INVENTION CONCERNE UN ENSEMBLE COMPRENANT DES DISPOSITIFS ELECTRONIQUES A SEMI-CONDUCTEURS ET UN RADIATEUR 7 SUR LEQUEL SONT MONTES DIRECTEMENT LESDITS DISPOSITIFS SOUS LA FORME DE PUCES NUES 1, 3, 5, CHACUNE DE CELLES-CI ETANT EN CONTACT AVEC LE RADIATEUR PAR L'UNE DES ELECTRODES QU'ELLE COMPORTE. DEUX ENSEMBLES COMPLEMENTAIRES ET SIX PUCES DE DIODES PERMETTENT DE REALISER UN PONT DE GRAETZ, LES TROIS PUCES DE L'UN DES RADIATEURS ETANT SOUDEES PAR LEUR FACE ANODIQUE ET CELLES DE L'AUTRE RADIATEUR PAR LEUR FACE CATHODIQUE.

Assembly of semiconductor electronic devices mounted on a dissipator

ELECTRONIC POWER MODULE AND ELECTRICAL CONVERTER INCLUDING POWER

Power electronic component with cooling surfaces includes dual cooling panels forming sandwich to enclose semiconductor element

Ce composant (28) comprend une semelle (2) destinée à reposer sur un premier élément de refroidissement (30), au moins une première structure composite (4) de transfert thermique et d'isolation électrique, et au moins un premier circuit semi-conducteur de puissance (10) comportant des plots (12) métalliques de connexion. Les plots de connexion sont assujettis, par leur face opposée à ladite première structure (4), à un réseau plan (18A) d'éléments conducteurs isolés entre eux, qui appartient à un ensemble de liaison rapporté (22), apte à entrer en contact, par sa face opposée audit réseau plan, avec un deuxième élément de refroidissement (32). Ce composant peut être refroidi à la fois depuis sa face supérieure et sa face inférieure.

ELECTRONIC POWER MODULE

L'invention concerne un module électronique de puissance, en particulier pour des systèmes de commande de vol électromécaniques. Il présente un premier substrat ayant des pistes conductrices appliquées sur celui-ci, ainsi qu'un composant à semi-conducteur de puissance et au moins un capteur de courant, de même qu'un second substrat, une première carte de circuit imprimé qui est fixée sur le second substrat et une seconde carte de-circuit imprimé qui est agencée au-dessus de la première carte de circuit imprimé, sur la première carte de circuit imprimé, dans lequel au moins un contact à ressort est connecté électriquement de manière ponctuelle à la première carte de circuit imprimé.

Power module package and method for manufacturing the same

A semi-conductor rectifier device

Semiconductor structure, 3dic structure and method of fabricating the same

Semiconductor apparatus having stacked devices and method of manufacture thereof

Aspects of the disclosure provide a semiconductor apparatus including a plurality of structures. A first one of the structures comprises a first stack of transistors that includes a first transistor formed on a substrate and a second transistor stacked on the first transistor along a Z direction substantially perpendicular to a substrate plane of the semiconductor apparatus. The first one of the structures further includes local interconnect structures. The first transistor is sandwiched between two of the local interconnect structures. The first one of the structures further includes vertical conductive structures substantially parallel to the Z direction. The vertical conductive structures are configured to provide at least power supplies for the first one of the structures by electrically coupling with the local interconnect structures. A height of one of the vertical conductive structures along the Z direction is at least a height of the first one of the structures.

Manufacturing method of package-on-package structure

POWER MODULE

The invention relates to a power module comprising a substrate (2), whose surfaces are provided with at least one electrically conductive layer (4, 6), at least one active semiconductor chip (8), which is electrically connected to an electrically conductive layer (6), a film (12) consisting of an electrically conductive material, which is in close contact with the surfaces of the semiconductor chips (8) of the electrically conductive layer (6) and the substrate (2) and is provided with planar printed conductors (16). According to the invention: the module is equipped with a second film (18), which is in close contact with the surfaces of the printed conductors (16) and the first film (12); a passive semiconductor chip (22) is applied to said second film (18), above the active semiconductor chip (8) and is electrically connected to the planar printed conductor (16) lying below by means of a window (14) that is configured in the second film (18); the module is equipped with a third film ( ...

ENERGY CONVERTER

An energy converter made of semiconductor material is designed to convert thermal energy Q into electrical energy E. The enerby converter generates a d.c. voltage between an anode (15) and a cathode (16) terminal via parallel-connected components (7). The components (7) consist of series-connected dipoles. Each component (7) has at least two of the dipoles, at least one of which is configured as a rectifier, the current of which flows towards the cathode (16). The energy converter converts part of the thermal energy Q1 in its environment (25) via its rectifiers, the capacitance C of which is lower than 1 fF, into electrical energy E by rectifying a.c. voltages of the thermal noise. The energy converter may be used as a d.c. source or as a heat pump.

Semiconductor device package and method for manufacturing the same

A semiconductor device package includes a first substrate, a second substrate, a conductive structure, a first solder and a second solder. The second substrate is disposed over the first substrate. The conductive structure is disposed between the first substrate and the second substrate. The conductive structure includes a first wetting portion, a second wetting portion, and a non-wetting portion disposed between the first wetting portion and the second wetting portion. The first solder covers the first wetting portion and connects the conductive structure to the first substrate. The second solder covers the second wetting portion and connects the conductive structure to the second substrate. The first solder is spaced apart from the second solder by the non-wetting portion.

Package structure having adhesive layer surrounded dam structure

A package structure includes a substrate, a die, an adhesive layer, a dam structure, and an encapsulant. The die is disposed on the substrate. The adhesive layer is disposed between the substrate and the die. The adhesive layer has a curved surface. The dam structure is disposed on the substrate and surrounded by the adhesive layer. The encapsulant encapsulates the die.

POWER TRANSISTOR ARRANGEMENT AND PACKAGE HAVING THE SAME

Various embodiments provide a power transistor arrangement, which may include a carrier including at least a main region, a first terminal region and a second terminal region being electrically isolated from each other; a first power transistor having a control electrode, a first power electrode and a second power electrode, and being arranged on the main region of the carrier such that its first power electrode is facing towards and is electrically coupled to the main region of the carrier; a second power transistor having a control electrode, a first power electrode and a second power electrode, and being arranged on the terminal regions of the carrier such that its control electrode and its first power electrode are facing towards the terminal regions, and having its control electrode being electrically coupled to the first terminal region and its first power electrode being electrically coupled to the second terminal region.

COOLED ELECTRONICS PACKAGE WITH STACKED POWER ELECTRONICS COMPONENTS

An electronics package includes an electrically conducting support layer; at least one electrically conducting outer layer; at least two power electronics components arranged on different sides of the support layer and electrically interconnected with the support layer and with the at least one outer layer; and isolation material, in which the support layer and the at least two power electronics components are embedded, the support layer and the at least one outer layer are laminated together with the isolation material; and a cooling channel for conducting a cooling fluid through the electronics package, the cooling channel runs between the at least two power electronics components through the support layer. 1. An electronics package , comprising:an electrically conducting support layer;at least one electrically conducting outer layer;at least two power electronics components arranged on different sides of the support layer and electrically interconnected with the support layer and with the at least one outer layer;an isolation material, in which the support layer and the at least two power electronics components are embedded, wherein the support layer and the at least one outer layer are laminated together with the isolation material;a cooling channel for conducting a cooling fluid through the electronics package, wherein the cooling channel runs between the at least two power electronics components through the support layer; andwherein at least a part of the cooling channel is provided by an electrically conducting component of the support layer.2. The electronics package of claim 1 ,wherein the support layer comprises an isolation element for electrically isolating two electrically conducting components of the support layer;wherein the cooling channel runs through the isolation element.3. The electronics package of claim 2 ,wherein the isolation element is an isolation layer arranged between two electrically conducting sublayers of the support layer.4. The ...

Integrated Cylindrical Power Cell Module and Manufacturing Method Thereof

The present invention relates to an integrated cylindrical power cell module and a manufacturing method thereof, and belongs to the field of power cells. The cylindrical cells in the present invention are placed in the mounting holes corresponding to each other one by one on a first housing and a second housing, and both poles of the cylindrical cell are respectively fitted on heat management modules by a heat-conducting adhesive. In this way, the cylindrical cell is light in weight, low in cost, and good in sealing performance and also in heat dissipation. Temperature acquisition modules are provided on a cylindrical surface and two poles of the cylindrical cell to coordinate with the heat management modules, allowing the cylindrical cell to have a better operating temperature. Conical guideposts surrounding the mounting holes are provided around the mounting holes. 1. An integrated cylindrical power cell module , comprising a plurality of cylindrical cells , a plurality of jumpers , a housing for placing the cylindrical cells , heat management modules , temperature acquisition modules and a processor module;wherein,the housing consists of a first housing and a second housing, the first housing and the second housing have jointing surfaces matched with each other; a plurality of mounting holes corresponding to each other one by one are formed in the first housing and the second housing; a plurality of jumpers are respectively provided on the first housing and the second housing, the jumpers on the first housing and the second housing are arranged oppositely, and the jumpers on the first housing have a same shape as the opposite jumpers on the second housing; holes are formed on the jumpers at positions corresponding to the mounting holes; two ends of the cylindrical cell are respectively placed in the mounting holes in the first housing and the second housing; and the first housing and the second housing are jointly fixed;two poles of the cylindrical cell are ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a first semiconductor chip having a first chip substrate, the first chip substrate having a first upper surface and a first lower surface opposite to each other, a first through-silicon via (TSV), a lower connection pad and a first lower passivation layer on the first lower surface of the first chip substrate, the first lower passivation layer exposing a portion of the lower connection pad, an upper connection pad and a first upper passivation layer on the first upper surface of the first chip substrate, the first upper passivation layer including a first upper inorganic material layer, and a second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a second TSV, wherein the first lower passivation layer has a stacked structure of a first lower inorganic material layer and a lower organic material layer.

Semiconductor Device with Shield for Electromagnetic Interference

A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.

Device Including Two Power Semiconductor Chips and Manufacturing Thereof

A device includes a first power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The device further includes a second power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The first and second power semiconductor chips are arranged one above another, and the first face of the first power semiconductor chip faces in the direction of the first face of the second power semiconductor chip. In addition, the first power semiconductor chip is located laterally at least partially outside of the outline of the second power semiconductor chip.

SEMICONDUCTOR DEVICE

A semiconductor device includes an inverter circuit having a first switching element and a second switching element, a first control circuit, a second control circuit, and a limiting unit. The first switching element is supplied with a power supply voltage. The second switching element includes a first terminal connected to the first switching element, a second terminal connected to ground, and a control terminal. The first control circuit controls the first switching element. The second control circuit controls the second switching element. The limiting unit reduces fluctuation in voltage between the second terminal and the control terminal based on voltage fluctuation at the second terminal of the second switching element.

DISAGGREGATED TRANSISTOR DEVICES

A multi-component transistor structure includes components each comprising an individual, discrete, and separate component substrate and a component transistor. The component transistor includes a transistor element having a transistor element resistance. A component connection is disposed external to the transistor element and has a connection resistance. The component connection electrically connects the transistor elements in the components in parallel. The connection resistance is less than the transistor element resistance of at least one corresponding transistor element, less than an average of the transistor element resistances of all of the corresponding transistor elements, or less than the sum of all of the transistor element resistances of all of the corresponding transistor elements. The component transistors are functionally similar and at least one of the components is disposed on another different one of the components in a component stack.

Fabrication of semiconductor packages

Power semiconductor device comprises vertical MOSFETs and insulated gate bipolar transistors as power semiconductor chip component, a stack from a vertical junction field effect transistor and MOSFET, bridge circuit, and cascade circuit

The power semiconductor device comprises vertical MOSFETs and insulated gate bipolar transistors as power semiconductor chip component (6), a stack from a vertical junction field effect transistor and the MOSFET, a bridge circuit, a cascade circuit made of stacked semiconductor chips, connecting elements (12) with circuit board segments (27) and through-contacts (25), and a bonding wire to a contact surface of a control electrode. The chip component has electrodes on its upper- and lower side with a large surface area. The power semiconductor device comprises vertical MOSFETs and insulated gate bipolar transistors as power semiconductor chip component (6), a stack from a vertical junction field effect transistor and the MOSFET, a bridge circuit, a cascade circuit made of stacked semiconductor chips, connecting elements (12) with circuit board segments (27) and through-contacts (25), and a bonding wire to a contact surface of a control electrode. The chip component has electrodes on its ...

STROMRICHTER

Power electronics module

STROMRICHTER

STATIC INVERTER

LAMINATED SEMICONDUCTER ASSEMBLY

B01537 LAMINATED SEMICONDUCTOR ASSEMBLY The problem of compensating for dimensional differences occuring in the length of adjacent stacks of semiconductors or other electronic components in an electrical assembly of such components is avoided through the use of a plurality of housing sections one for each stack with each housing section being comprised of stacked thin sheets of electrically conductive or electrically insulating material. Some of the sheets have cutouts to receive semiconductors. The stacks are tied together by ribbon-like flexible tabs integral with at least some of the sheets and interconnecting the housing sections. The tabs are constructed to be deformable generally independently of the other of the tabs.

HIGH POWER GALLIUM NITRIDE DEVICES AND STRUCTURES

Described herein are semiconductor devices and structures with improved power handling and heat dissipation. Embodiments are suitable for implementation in gallium nitride. Devices may be provided as individual square or diamond-shaped dies having electrode terminals at the die corners, tapered electrode bases, and interdigitated electrode fingers. Device matrix structures include a plurality of device dies arranged on a substrate in a matrix configuration with interdigitated conductors. Device lattice structures are based on a unit cell comprising a plurality of individual devices, the unit cells disposed on a chip with geometric periodicity. Also described herein are methods for implementing the semiconductor devices and structures.

STRUCTURE AND METHOD FOR THE FABRICATION OF LPMCM SEMICONDUCTOR PACKAGES

A heat-conductive honeycomb ceramic spacer having an array of apertures therein for facilitating assembly of a semiconductor device including a plurality of semiconductor stacks using a low-profile contact comprising a foil with raised portions corresponding to the locations of apertures in the ceramic spacer for forming contacts with the semiconductor stacks when the spacer and the stacks are sandwiched between the foil and another conductive sheet. Use of such a foil also allows disconnection of defective stacks in the device which includes extra stacks to compensate therefore, according to an n - x design philosophy. Solder preforms may be included on the stacks and enhanced connections made to the foil of conductive sheet by causing reflux of the solder preforms. The invention may also be applied to multi-layer device constructions.

ELECTRONIC POWER DEVICE

Ce dispositif (1) comprend une semelle conductrice (2) sur laquelle repose un premier arrangement plan de circuits semi-conducteurs, formé par des diodes (4) et des IGBT (6) pourvus de plots de connexion (12, 14, 16). Le dispositif comprend au moins un deuxième arrangement plan de circuits semi-conducteurs (104, 106), deux arrangements voisins (4, 6, 104, 106) étant séparés par un réseau plan conducteur (18, 28A, 28B) comprenant au moins une barre (20) conductrice électrique et de dissipation de chaleur reliant des plots (12, 16) des circuits (4, 6) d'un premier arrangement, ladite barre (20) supportant en outre des circuits (104, 106) d'un second arrangement plan, au moins un élément conducteur (28A, 28B) isolé électriquement de ladite barre (20) étant connecté à d'autres plots (14) des circuits (4, 6) dudit premier arrangement et étant disposé dans le volume de ladite barre (20).

The embedded chip manufacturing method

ELECTRONIC POWER

Rectifying device with semiconductors, comprising rectifying elements in the form of shelves

ELECTRONIC POWER MODULE AND ELECTRONIC SYSTEM HAVING SUCH AN ELECTRONIC MODULE

A SEMICONDUCTOR DEVICE

Semiconductor device

A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a plurality of first semiconductor dies, a first adhesive layer, a plurality of second semiconductor dies, a second adhesive layer, and a plurality of first metal bumps. The first semiconductor dies are embedded in a first photosensitive layer of a first group of wafers. The first adhesive layer is disposed between at least two of the first group of wafers to form a first structure. The second semiconductor dies are embedded in a second photosensitive layer of a second group of wafers. The second adhesive layer is disposed between at least two of the second group of wafers to form a second structure. The first metal bumps are disposed between the first structure and second structure, in which the first structure is connected to the second structure with the first metal bumps.

CONVERTISSEUR STATIQUE

POWER SEMICONDUCTOR MODULE

L'invention concerne un module à semi-conducteur de puissance qui comprend une pile constituée de substrats de support disposés les uns sur les autres, substrats dont au moins une surface principale est recouverte d'une piste conductrice. Entre deux substrats de support adjacents de la pile est disposé un composant à semi-conducteur électronique qui est mis en contact électrique et thermoconducteur avec au moins une piste conductrice d'un substrat de support placé, dans la pile, au-dessus du composant à semi-conducteur, et avec au moins une autre piste conductrice d'un substrat de support disposé, dans la pile, au-dessous du composant à semi-conducteur. L'objectif de l'invention est, dans un tel module, d'obtenir, avec une structure la plus compacte possible, une meilleure dissipation de la chaleur. A cet effet, il est proposé que les deux substrats de support extérieurs de la pile soient conçus sous la forme d'une paroi supérieure et d'une paroi inférieure d'une partie boîtier fermée entourant ...

Semiconductor module

The present invention provides a semiconductor module capable of improving a bandwidth between a logic chip and a RAM. According to the present invention, a semiconductor module 1 is provided with: a logic chip; a pair of RAM units 30 each composed of a lamination-type RAM module; a first interposer 10 electrically connected to the logic chip and to each of the pair of RAM units 30; and a connection unit 40 that communicatively connects the logic chip and each of the pair of RAM units 30, wherein one RAM unit 30a is placed on the first interposer 10, and has one end portion disposed so as to overlap, in the lamination direction C, one end portion of the logic chip with the connection unit 40 therebetween, and the other RAM unit 30b is disposed so as to overlap the one RAM unit 30a with the connection unit 40 therebetween, and is also disposed along the outer periphery of the logic chip.

Semiconductor package for discharging heat generated by semiconductor chip

Disclosed is a semiconductor package comprising a package substrate, a first semiconductor chip on the package substrate and including a first region and a second region, a second semiconductor chip on the first region, a heat radiation spacer on the second region, a third semiconductor chip supported by the second semiconductor chip and the heat radiation spacer, and a molding layer covering the first to third semiconductor chips and the heat radiation spacer.

Power Semiconductor Component Having Chip Stack

A power semiconductor component (2) has a chip stack, which contains a first chip (10), a second chip (6) and a third chip (8), where at least the second chip (6) and the third chip (8) are the same height. The power semiconductor component (2) also has a package in which the first chip (10), the second chip (6) and the third chip (8) are placed. The second chip (6) and the third chip (8) are mounted side by side on a lead (4), and the first chip (10) rests both on the second chip (6) and on the third chip (8).

POWER SEMICONDUCTOR MODULE WITH POWER SEMICONDUCTOR SWITCHES

A power semiconductor module has a first and second intermediate circuit rail, an AC potential rail and with a packaged first and second power semiconductor switch. The respective power semiconductor switch has a first and second load current terminal and a control terminal, wherein the first power semiconductor switch is between the first intermediate circuit rail and the AC potential rail and the second power semiconductor switch is between the second intermediate circuit rail and the AC potential rail. The first load terminal of the first power semiconductor switch is contacted to the first intermediate circuit rail and the second load terminal of the first power semiconductor switch is electrically conductively contacted to the AC potential rail.

SEMICONDUCTOR DEVICE INCLUDING VERTICALLY INTEGRATED GROUPS OF SEMICONDUCTOR PACKAGES

A semiconductor device is disclosed including at least first and second vertically stacked and interconnected groups of semiconductor packages. The first and second groups of semiconductor packages may differ from each other in the number of packages and functionality.

Seal ring structures and methods of forming same

A three-dimensional (3D) integrated circuit (IC) includes a first IC die and a second IC die. The first IC die includes a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The second IC die includes a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD

A semiconductor device includes a plurality of semiconductor units each including a laminated substrate formed by laminating an insulating board and a circuit board and a semiconductor element joined to the circuit board using a joining material which irreversibly makes a phase transition into a solid-phase state. In addition, the semiconductor device may include a base plate to which each of the plurality of semiconductor units is joined using solder and a connection unit which electrically connects the plurality of semiconductor units in parallel.

Pop devices and methods of forming the same

PoP devices and methods of forming the same are disclosed. A PoP device includes a first package structure and a second package structure. The first package structure includes a first chip, and a plurality of active through integrated fan-out vias and a plurality of dummy through integrated fan-out vias aside the first chip. The second package structure includes a plurality active bumps bonded to the plurality of active through integrated fan-out vias, and a plurality of dummy bumps bonded to the plurality of dummy through integrated fan-out vias. Besides, a total number of the active through integrated fan-out vias and the dummy through integrated fan-out vias at a first side of the first chip is substantially the same as a total number of the active through integrated fan-out vias and the dummy through integrated fan-out vias at a second side of the first chip.

ELECTRICAL MODULE

HALBLEITERPAKETE UND -VERFAHREN ZUR BILDUNG DERSELBEN

Eine Ausführungsform ist eine Vorrichtung, die einen integrierten Schaltkreisdie enthält, der eine aktive Seite und eine Rückseite aufweist, wobei die Rückseite der aktiven Seite gegenüberliegt, eine Formmasse, die den integrierten Schaltkreisdie verkapselt, und eine erste Umverteilungsstruktur, die über dem integrierten Schaltkreisdie und der Formmasse liegt, wobei die erste Umverteilungsstruktur eine erste Metallisierungsstruktur und eine erste dielektrische Lage aufweist, wobei die erste Metallisierungsstruktur elektrisch mit der aktiven Seite des integrierten Schaltkreisdies gekoppelt ist, und mindestens ein Abschnitt der ersten Metallisierungsstruktur einen Induktor bildet.

Halbleitermodul

Es wird ein Halbleitermodul (100) mit einer Vielzahl von Halbleiterelementen (31, 32) angegeben, wobei die Verdrahtungslängen der nebeneinander angeordneten Halbleiterelemente (31, 32) etwa gleich sind. Der Halbleitermodul weist ein unteres Schichtsubstrat (10) und ein oberes Schichtsubstrat (20) auf, wobei eine erste und eine zweite Elektroden-Anschlußfläche, die in einer vorderen Oberfläche des unteren Schichtsubstrats ausgebildet sind, mit einem ersten und einem zweiten Leiter (12) durch einen ersten und einen zweiten Überbrückungsleiter (22) verbunden sind, die in einer rückwärtigen Oberfläche des oberen Schichtsubstrats (20) ausgebildet sind.

STATIC CONVERTER INCORPORATING THYRISTORS

... 1484700 Thyristor devices SIEMENS AG 11 Oct 1974 [31 Oct 1973] 44226/74 Heading H1K [Also in Division H2] A static thyristor converter, e.g. for high voltage inversion, rectification or static frequency changing, comprises (Figs. 1a 1b 1c) air or oil cooled columns 4 of thyristors stacked in tiers 1, 2, 3 on supporting rails 5, and supplied with coolant over ducts 6a, 6b, 6c from a common line; the coolant exhausting to a further common line over ducts 7a, 7b, 7c. Framework members 8 comprise flat sided hollow potshaped first support members 9 of, e.g. brass, and underlying second insulant support members 10, of e.g. cast resin one first support member 9 carrying the supporting rails 5 of each tier 1, 2, 3, which are mutually isolated by second support members 10. A further tier 11 carries a fuse assembly 12 on rail 5; first support members 9 carrying current to the fuse posts and the thyristors. Framework members 8, 8a are positioned respectively on the high and low voltage sides; first ...

Semiconductor rectifying structures

... 1,120,598. Welding by pressure. D. SCIAKY. 14 June, 1966 [1 Sept., 1965], No. 26500/66. Heading B3R. [Also in Division H1] The invention relates to the construction of a full wave semi-conductor rectifying assembly (see Division H1). Fig. 3 shows the rectifying assembly 1, 2, mounted between conductors 3 connected to the ends of the secondary winding of transformer 14. Direct current is supplied via intermediate conductor 3 and flexible conductor 16 to upper welding electrode 15 thus allowing free vertical movement of electrode 15. The lower electrode 16 is connected to the centre tip on the transformer secondary via face plate 18. Arrangements for use with a three phase supply or a Scott connected transformer with reactances in series in the secondary leads, are also described. Further embodiments relate to a portable spot welding gun and a flash butt welder.

STATIC INVERTER

LEADER PLATE WITH ELECTRONIC ELEMENT

COMPACT CONVERTER BUILDING BLOCK SYSTEM

Handheld terminal and fingerprint identification module thereof, and fingerprint encapsulation structure

Power semiconductor module and method of manufacturing the same

Disclosed herein is a power semiconductor module. The module includes metal plates each having a first through hole, with an anodic oxidation layer formed on a surface of metal plates and an interior of the first through hole. A cooling member has a second through hole at a position corresponding to the first through hole, and the metal plates are attached to both sides of the cooling member. A circuit layer is formed on the anodic oxidation layer and performs an interlayer connection through a via formed in the first and second through holes. A power device is connected to the circuit layer.A resin encapsulant encloses the circuit layer and the power device. A housing is installed to each of the metal plates to form a sealing space for the resin encapsulant.

Rectifying device with semiconductors made up of elements in the shape of pastilles

HIGH POWER ELECTRONIC MODULE AND METHOD FOR MANUFACTURING SUCH A MODULE

POWER ELECTRONIC DEVICE

가압 요소를 갖는 클램핑 조립체

... 본 발명은 스택을 형성하도록 서로의 위에 배치되는 기계적으로 지지된 구성 요소(3-7)의 배열(2), 구성 요소의 배열에 대해 기계적 압축력을 생성하기 위한 클램핑 디바이스, 및 클램핑 디바이스로부터 배열로 기계적 압축력을 전달하기 위한 가압 요소(10)를 갖는 클램핑 조립체(1)와 관련된다. 압축력의 평탄하고 균일한 전달을 위해, 가압 요소(10)는 본 발명에 따라 금속 폼을 포함한다.

Fanout integration for stacked silicon package assembly

A chip package assembly and method for fabricating the same are provided which utilize a plurality of posts in mold compound for improved resistance to delamination. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die, a substrate, a redistribution layer, a mold compound and a plurality of posts. The redistribution layer provides electrical connections between circuitry of the first IC die and circuitry of the substrate. The mold compound is disposed in contact with the first IC die and spaced from the substrate by the redistribution layer. The plurality of posts are disposed in the mold compound and are laterally spaced from the first IC die. The plurality of posts are not electrically connected to the circuitry of the first IC die.

Package structure and manufacturing method thereof

A package structure includes a substrate, a die, an adhesive layer, a dam structure, and an encapsulant. The die is disposed on the substrate. The adhesive layer is disposed between the substrate and the die. The adhesive layer has a curved surface. The dam structure is disposed on the substrate and surrounded by the adhesive layer. The encapsulant encapsulates the die.

Semiconductor package structure and method for preparing the same

The present disclosure provides a semiconductor package structure. The semiconductor package structure includes a first die, a second die and a hybrid bonding structure disposed between the first die and the second die. The first die includes a first front side and a first back side opposite to the first front side. The second die includes a second front side and a second back side opposite to the second front side. The hybrid bonding structure is disposed between the first back side of the first die and the second front side of the second die. The first die and the second die are bonded to each other by the hybrid bonding structure. The hybrid bonding structure includes an organic barrier layer and an inorganic barrier layer bonded to each other.

SEMICONDUCTOR DEVICE

A semiconductor device is reduced in size without connecting an external diode, and the heat caused by current is prevented from being concentrated on the central part of the semiconductor substrate. First base regions (16) of sequentially stacked first and second IGBTs (1, 2) each have a peripheral region (26) neighboring the side surface (31c) of a semiconductor substrate (31). Each of the IGBTs (1, 2) includes a p-type peripheral base region (27) forming a diode (21) adjacently to the peripheral region (26) of the n-type first base region (16) and a diode electrode (24) formed on the upper surface (26a) of the peripheral region (26) of the first base region (16). The diode electrode (24) and collector electrode (23) of each of the IGBTs (1, 2) are electrically connected with each other. When the semiconductor device is on, current flows toward the central part of the semiconductor substrate (31) apart from the side surface (31c). When the semiconductor is off, if reverse current occurs ...

ELECTRIC MOTOR AND METHOD FOR PRODUCING SAID MOTOR

The invention relates to an electric motor (10), in particular for displacing moving parts in a motor vehicle. Said motor comprises an electronic unit (70) with a sandwich construction, which contains a first electrically conductive substrate (71) and a second electrically conductive substrate (72). Power components are located between said substrates and are electrically connected to both substrates (71, 72). The side (84) of the second substrate (72) facing away from the first substrate (71) is equipped with additional electronic components (56). The first substrate (71) is configured as a conductive punched grid (44), which together with the second substrate (72) is surrounded by a plastic body (95) in an insert moulding process, in such a way that extensions (97) of the punched grid (44) protrude from the plastic body (95), forming an electrical and/or mechanical interface (98) for connecting additional motor components (99, 38, 40, 104, 102, 80).

RESISTANCE WELDING MACHINE

WAFER-LEVEL PACKAGING METHOD AND PACKAGE STRUCTURE

The present disclosure provides a wafer level packaging method and a package structure. The wafer level packaging method includes: forming a bonding structure including a device wafer and a plurality of first chips bonded to the device wafer; conformally covering the plurality of first chips and the device wafer exposed by the plurality of first chips with an insulating layer; conformally covering the insulating layer with a shielding layer; and forming an encapsulation layer on the shielding layer. The wafer level package structure includes: a device wafer; a plurality of first chips bonded to the device wafer; an insulating layer conformally covering the plurality of first chips and the device wafer exposed by the plurality of first chips; a shielding layer conformally covering the insulating layer; and an encapsulation layer formed on the shielding layer. The wafer level package structure provides a reduced volume and a reduced thickness.

Automotive bridge rectifier assembly with thermal protection

A rectifier assembly employs a set of diodes to rectify alternating current from an alternator to direct current for use by the electrical system of an automobile. The rectifier includes a plurality of thermal safety disconnects coupled along circuit paths within the rectifier assembly. When the resultant temperature caused by the heat provided to the safety disconnect as a result of the diodes overheating is above a threshold level, the safety disconnect melts away to disconnect the circuit path associated with the safety disconnect.

SEMICONDUCTOR PACKAGE FOR DISCHARGING HEAT GENERATED BY SEMICONDUCTOR CHIP

Disclosed is a semiconductor package comprising a package substrate, a first semiconductor chip on the package substrate and including a first region and a second region, a second semiconductor chip on the first region, a heat radiation spacer on the second region, a third semiconductor chip supported by the second semiconductor chip and the heat radiation spacer, and a molding layer covering the first to third semiconductor chips and the heat radiation spacer. 1. A semiconductor package , comprising;a package substrate;a first semiconductor chip on the package substrate and including a first region and a second region; a base including a first segment on the first region and a second segment on the second region, and', 'a protrusion on the second segment;, 'a heat radiation spacer on the first semiconductor chip, the heat radiation spacer comprising'}a second semiconductor chip on the first segment;a third semiconductor chip supported by the second semiconductor chip and the protrusion; anda molding layer covering the first to third semiconductor chips and the heat radiation spacer.2. The semiconductor package of claim 1 , wherein the first semiconductor chip includes a heat source in the second region.3. The semiconductor package of claim 2 , wherein the heat source is vertically overlapped by the protrusion.4. The semiconductor package of claim 1 , wherein a level of a top surface of the protrusion is substantially the same as a level of a top surface of the second semiconductor chip.5. The semiconductor package of claim 1 , wherein the protrusion and the third semiconductor chip are in direct contact with each other.6. The semiconductor package of claim 1 , further comprising:a heat pathway pattern that penetrates the molding layer and is connected to the protrusion; anda heat radiation member on the molding layer,wherein a thermal conductivity of the heat pathway pattern is greater than a thermal conductivity of the molding layer.7. The semiconductor package of ...

Wafer to wafer bonding process and structures

Bonded structures and method of forming the same are provided. A conductive layer is formed on a first surface of a bonded structure, the bonded structure including a first substrate bonded to a second substrate, the first surface of the bonded structure being an exposed surface of the first substrate. A patterned mask having first openings and second openings is formed on the conductive layer, the first openings and the second openings exposing portions of the conductive layer. First portions of first bonding connectors are formed in the first openings and first portions of second bonding connectors are formed in the second openings. The conductive layer is patterned to form second portions of the first bonding connectors and second portions of the second bonding connectors. The bonded structure is bonded to a third substrate using the first bonding connectors and the second bonding connectors.

SEMICONDUCTOR PACKAGES HAVING PACKAGE-ON-PACKAGE (POP) STRUCTURES

Disclosed is a semiconductor package having a package-on-package (PoP) structure in which a signal region and a power region are formed separately. The semiconductor package includes a lower semiconductor package and an upper semiconductor package on the lower semiconductor package. The upper semiconductor package includes an upper package substrate, a memory chip on the upper package substrate, a wire that electrically connects the memory chip to the upper package substrate, a power connector on the upper semiconductor package, a signal connector on the bottom surface of the upper package substrate, and an upper package molding material.

Halbleitermodul

Ein Halbleitermodul umfasst: eine erste Isolierplatte; eine zweite Isolierplatte, die über der ersten Isolierplatte angeordnet ist; eine erste Halbleitervorrichtung, die auf einer oberen Oberfläche der ersten Isolierplatte vorgesehen ist; eine zweite Halbleitervorrichtung, die auf einer unteren Oberfläche der zweiten Isolierplatte vorgesehen ist; ein Isoliersubstrat, das eine dritte Isolierplatte, die zwischen der ersten Isolierplatte und der zweiten Isolierplatte angeordnet ist, und einen Leiter umfasst, der auf der dritten Isolierplatte vorgesehen und mit den ersten und zweiten Halbleitervorrichtungen verbunden ist; und ein Versiegelungsharz, das die ersten und zweiten Halbleitervorrichtungen und das Isoliersubstrat versiegelt, wobei eine Stehspannung der dritten Isolierplatte niedriger als Stehspannungen der ersten und zweiten Isolierplatten ist.

Halbleitereinrichtung mit einem Schaltelement, das eine Potentialschwankung unterdrückt

Die Halbleitereinrichtung (11, 111, 211) ist mit einer Vielzahl von Schaltelementen (14), die parallel miteinander verbunden sind, und einer Vielzahl von Rücklaufelementen (15), die parallel zu der vorstehend erwähnten Vielzahl von Schaltelementen verbunden sind, bereitgestellt. Eine Emitterelektrode (14b) dient als ein Referenzpotential der vorstehend erwähnten Vielzahl von Schaltelementen und eine Anodenelektrode (15b) dient als ein Referenzpotential der vorstehend erwähnten Vielzahl von Rücklaufelementen, die durch das gleiche plattenähnliche Element (17), da aus einem leitenden Material besteht, elektrisch verbunden sind. Die vorstehend erwähnten Schaltelemente und die vorstehend erwähnten Rücklaufelemente, die auf der niedrigsten Potentialseite parallel miteinander verbunden sind, sind derart ausgestaltet, dass die Entfernung von dem Emitteranschluss (11n), der mit der vorstehend erwähnten Emitterelektrode verbunden ist, zu dem vorstehend erwähnten Rücklaufelement nicht größer wird ...

Herstellung von Halbleiterpackungen

Vorrichtung mit zwei Leistungshalbleiterchips und Verfahren für ihre Herstellung

Eine Vorrichtung umfasst einen ersten Leistungshalbleiterchip mit einer ersten Kontaktstelle und einer zweiten Kontaktstelle auf einer ersten Fläche und einer dritten Kontaktstelle auf der zweiten Fläche. Die Vorrichtung umfasst ferner einen zweiten Leistungshalbleiterchip mit einer ersten Kontaktstelle und einer zweiten Kontaktstelle auf einer ersten Fläche und einer dritten Kontaktstelle auf der zweiten Fläche. Der erste und der zweite Leistungshalbleiterchip sind übereinander angeordnet und die erste Fläche des ersten Leistungshalbleiterchips ist in die Richtung der ersten Fläche des zweiten Leistungshalbleiterchips gewandt. Außerdem ist der erste Leistungshalbleiterchip seitlich zumindest teilweise außerhalb des Umrisses des zweiten Leistungshalbleiterchips angeordnet.

POWER SEMICONDUCTOR

Power converter and method for producing the same

ELECTRONIC COMPONENT MODULE

The invention relates to an electronic component module, comprising at least one first multi-layer circuit board module (21, 22; 31, 32; 41, 42) and a cooling arrangement (23, 33, 43), the cooling arrangement (23, 33, 43) being in contact with an upper side of the circuit board module (21, 22; 31, 32; 41, 42). The cooling arrangement (23, 33, 43) is designed such that waste heat generated during operation of the electronic component module (2, 3, 4) is extracted in a lateral direction with relation to the arrangement of the circuit board module (21,22; 31, 32; 41, 42) by means of the cooling arrangement (23, 33, 43).

ELECTRONIC POWER DEVICE

Ce dispositif (1) comprend une semelle conductrice (2) sur laquelle repose un premier arrangement plan de circuits semi-conducteurs, formé par des diodes (4) et des IGBT (6) pourvus de plots de connexion (12, 14, 16). Le dispositif comprend au moins un deuxième arrangement plan de circuits semi-conducteurs (104, 106), deux arrangements voisins (4, 6, 104, 106) étant séparés par un réseau plan conducteur (18, 28A, 28B) comprenant au moins une barre (20) conductrice électrique et de dissipation de chaleur reliant des plots (12, 16) des circuits (4, 6) d'un premier arrangement, ladite barre (20) supportant en outre des circuits (104, 106) d'un second arrangement plan, au moins un élément conducteur (28A, 28B) isolé électriquement de ladite barre (20) étant connecté à d'autres plots (14) des circuits (4, 6) dudit premier arrangement et étant disposé dans le volume de ladite barre (20).

Stacked semiconductor package

SEMICONDUCTOR DEVICE PACKAGE

SEMICONDUCTOR DEVICE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME

Modular liquid-cooled power semiconductor module, and arrangement therewith

Package structure of micro memory and package structure of memory

Ultra small molded module integrated with die by module-on-wafer assembly

PRINTED CIRCUIT BOARD WITH ELECTRONIC COMPONENT

The invention relates to a printed circuit board (1) with a sheet-like board substrate (2) and with at least one electronic component (3), wherein it is provided that the component (3) is arranged within the board substrate (2). The invention also relates to a corresponding method for producing the printed circuit board.

Semiconductor module including a switch and non-central diode

A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.

Stacked Half-Bridge Power Module

According to an exemplary embodiment, a stacked half-bridge power module includes a high side device having a high side power terminal coupled to a high side substrate and a low side device having a low side power terminal coupled to a low side substrate. The high side and low side devices are stacked on opposite sides of a common conductive interface. The common conductive interface electrically, mechanically, and thermally couples a high side output terminal of the high side device to a low side output terminal of the low side device. The high side device and the low side device can each include an insulated-gate bipolar transistor (IGBT) in parallel with a diode.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

A semiconductor substrate of a semiconductor device has a sensor region and an integrated circuit region, and a cavity is formed immediately under a surface layer portion of the sensor region. A capacitive acceleration sensor is formed on the sensor region by working a surface layer portion of the semiconductor substrate opposed to the cavity. The capacitive acceleration sensor includes an interdigital fixed electrode and an interdigital movable electrode. A CMIS transistor is formed on the integrated circuit region. The CMIS transistor includes a P-type well region and an N-type well region formed on the surface layer portion of the semiconductor substrate. A gate electrode is opposed to the respective ones of the P-type well region and the N-type well region through a gate insulating film formed on a surface of the semiconductor substrate. 1. A semiconductor device comprising:a semiconductor substrate having a sensor region and an integrated circuit region, with a cavity formed immediately under a surface layer portion of the sensor region;a capacitive acceleration sensor formed on the sensor region; anda CMIS transistor formed on the integrated circuit region, whereinthe capacitive acceleration sensor includes an interdigital fixed electrode and an interdigital movable electrode formed by working the surface layer portion opposed to the cavity to mesh with each other at an interval, andthe CMIS transistor includes an N-type well region formed on a surface layer portion of the semiconductor substrate in the integrated circuit region and having a P-type source region and a P-type drain region, a P-type well region formed on the surface layer portion of the semiconductor substrate in the integrated circuit region and having an N-type source region and an N-type drain region, and a gate electrode opposed to the respective ones of the N-type well region and the P-type well region through a gate insulating film formed on a surface of the semiconductor substrate.2. The ...

System in package process flow

A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.

FLIP-CHIP, FACE-UP AND FACE-DOWN WIREBOND COMBINATION PACKAGE

A microelectronic assembly can include a substrate having an aperture extending between first and second surfaces thereof, the substrate having substrate contacts at the first surface and terminals at the second surface. The microelectronic assembly can include a first microelectronic element having a front surface facing the first surface, a second microelectronic element having a front surface facing the first microelectronic element, and leads electrically connecting the contacts of the second microelectronic element with the terminals. The second microelectronic element can have contacts exposed at the front surface thereof beyond an edge of the first microelectronic element. The first microelectronic element can be configured to regenerate at least some signals received by the microelectronic assembly at the terminals and to transmit said signals to the second microelectronic element. The second microelectronic element can embody a greater number of active devices to provide memory storage array function than any other function. 1a substrate having oppositely-facing first and second surfaces, the substrate having substrate contacts at the first surface and terminals at the second surface;a first microelectronic element having a front surface facing the first surface, a rear surface remote therefrom, and an edge extending between the front and rear surfaces, the first microelectronic element having a plurality of contacts at the front surface that face and are joined to corresponding ones of the substrate contacts;a second microelectronic element having a front surface facing the first microelectronic element, the second microelectronic element having a plurality of contacts exposed at the front surface thereof beyond the edge of the first microelectronic element, the second microelectronic element embodying a greater number of active devices to provide memory storage array function than any other function; andleads electrically connecting the contacts of the ...

SEMICONDUCTOR DEVICE WITH SHIELD FOR ELECTROMAGNETIC INTERFERENCE

A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side. 1. A semiconductor device comprising:a first die embedded in a molding material, wherein contact pads of the first die are proximate a first side of the molding material;a redistribution structure over the first side of the molding material;a first metal coating along sidewalls of the first die and between the first die and the molding material; anda second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.2. The semiconductor device of claim 1 , wherein the first metal coating and the second metal coating are electrically connected to a ground contact.3. The semiconductor device of claim 1 , wherein the redistribution structure comprises a via that is electrically coupled to the first metal coating.4. The semiconductor device of claim 3 , wherein the via has a first dimension along a first direction and a second dimension along a second direction perpendicular to the first direction claim 3 , the second dimension being smaller than the first dimension.5. The semiconductor device of claim 1 , wherein the first die has a plurality of conductive pillars coupled to respectively ones of the contact pads claim 1 , wherein at least one of the plurality of conductive pillars is electrically coupled to the first metal coating.6. The semiconductor device of claim 5 , wherein an upper surface of the plurality of the conductive pillars distal the contact pads is level with the first side of ...

POWER MODULE WITH THE INTEGRATION OF CONTROL CIRCUIT

The present disclosure provides a power module with the integration of a control circuit at least, including: a power substrate; a power device mounted on the power substrate; and at least one control substrate which supports the control circuit, is electrically connected with the power substrate and disposed at an angle of inclination on a surface of the power substrate on which the power device is mounted; wherein the angle of inclination is greater than or equal to 45 degrees and smaller than or equal to 135 degrees. In the power module provided by the present disclosure, only the power substrate as well as the connections between the control substrate and the power substrate occupies the footprint area of the power module, and thus the horizontal footprint area of the power module is effectively reduced and thereby the power density of the power module is increased. 1. A power module with the integration of a control circuit , comprising:a power substrate;a power device mounted on the power substrate; andat least one control substrate which supports the control circuit, is electrically connected with the power substrate and disposed at an angle of inclination on a surface of the power substrate on which the power device is mounted;wherein the angle of inclination is greater than or equal to 45 degrees and smaller than or equal to 135 degrees.2. The power module according to claim 1 , wherein the power substrate comprises at least one conductive wiring layer on which the power device is disposed.3. The power module according to claim 1 , wherein the at least one control substrate comprises at least one conductive wiring layer and at least one insulation layer claim 1 , and a control device in the control circuit is disposed on the at least one conductive wiring layer.4. The power module according to claim 3 , wherein the at least one control substrate comprises two conductive wiring layers disposed on both sides of the at least one insulation layer claim 3 , ...

Pad Design For Reliability Enhancement in Packages

A package includes a corner, a device die, a molding material molding the device die therein, and a plurality of bonding features. The plurality of bonding features includes a corner bonding feature at the corner, wherein the corner bonding feature is elongated. The plurality of bonding features further includes an additional bonding feature, which is non-elongated. 1. A package comprising: a corner;', 'a device die;', 'a molding material molding the device die therein; and', a corner bonding feature at the corner, wherein the corner bonding feature is elongated; and', 'an additional bonding feature, wherein the additional bonding feature is non-elongated., 'a plurality of bonding features comprising], 'a first package comprising2. The package of claim 1 , wherein the plurality of bonding features comprises a plurality of bonding pads.3. The package of further comprising a dielectric layer on a backside of the device die claim 2 , wherein the corner bonding feature comprises a first portion in the dielectric layer claim 2 , and a second portion protruding beyond the dielectric layer.4. The package of claim 1 , wherein the plurality of bonding features comprises a plurality of through-vias penetrating through the molding material.5. The package of further comprising:a second package; anda first solder region bonding the corner bonding feature to the second package; anda second solder region bonding the additional bonding feature to the second package.6. The package of claim 5 , wherein the second package comprises a metal pad in contact with the first solder region claim 5 , wherein the metal pad is elongated.7. The package of claim 5 , wherein the first solder region and the second solder region are in contact with a sidewall of the corner bonding feature and a sidewall of the additional bonding feature claim 5 , respectively.8. The package of claim 7 , wherein the second package comprises a first and a second metal pad in contact with the first solder region and ...

Semiconductor device

A semiconductor device includes first and second chips that are stacked such that first surfaces of their element layers face each other. Each chip has a substrate, an element layer on a first surface of the substrate, pads on the element layer, and vias that penetrate through the substrate and the element layer. Each via is exposed from a second surface of the substrate and directly connected to one of the pads. The vias include a first via of the first chip directly connected to a first pad of the first chip and a second via of the second chip directly connected to a second pad of the second chip. The pads further include a third pad of the second chip which is electrically connected to the second pad by a wiring in the element layer of the second chip and to the first pad through a micro-bump.

SEMICONDUCTOR PACKAGE HAVING REDISTRIBUTION LAYER

A semiconductor package includes a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity, a first semiconductor chip in the cavity, a plurality of conductive vias in the plurality of through holes, a first redistribution layer on the silicon substrate and connected to the first semiconductor chip and the conductive vias, and a second redistribution layer below the silicon substrate and connected to the first semiconductor chip and the plurality of conductive vias. 1. A semiconductor package comprising:first redistribution layer;a second redistribution layer below the first redistribution layer;a plurality of conductive vias electrically connecting the first redistribution layer and the second redistribution layer;a lower semiconductor chin on the second redistribution layer, the lower semiconductor chip including a through-electrode passing through the lower semiconductor chip; andan upper semiconductor chip on the lower semiconductor chip;wherein the upper semiconductor chin is electrically connected to the first redistribution layer and the lower semiconductor chip is electrically connected to the second redistribution layer; andwherein the plurality of conductive vias surround the lower semiconductor chip and the upper semiconductor chip.2. The semiconductor package of claim 1 , further comprising:via insulating layers covering side surfaces of the plurality of conductive vias.3. The semiconductor package of claim 1 , wherein lower portions of the plurality of conductive vias extend to an upper surface of the second redistribution layer.4. The semiconductor package of claim 1 , wherein an upper surface of the plurality of conductive vias extend to a lower surface of the first redistribution layer.5. The semiconductor package of claim 1 , wherein the lower semiconductor chip and the upper semiconductor chip are disposed in a cavity between the first redistribution layer the second redistribution layer.6. The ...

Package-on-Package Devices with Upper RDL of WLPS and Methods Therefor

Package-on-package (“PoP”) devices with upper RDLs of WLP (“WLP”) components and methods therefor are disclosed. In a PoP device, a first IC die is surface mount coupled to an upper surface of the package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region with reference to the first IC. A molding layer is formed over the upper surface of the package substrate. A first and a second WLP microelectronic component is located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. Each of the first and the second WLP microelectronic components have a second IC die located below a first RDL respectively thereof. A third and a fourth IC die are respectively surface mount coupled over the first and the second WLP microelectronic components. 1. A package-on-package device , comprising:a package substrate;a first integrated circuit die surface mount coupled to an upper surface of the package substrate;conductive lines coupled to the upper surface of the package substrate in a fan-out region with reference to the first integrated circuit, the first conductive lines extending away from the upper surface of the package substrate;a molding layer formed over the upper surface of the package substrate, around sidewall surfaces of the first integrated circuit die, and around bases and shafts of the conductive lines;a first and a second wafer-level packaged microelectronic component located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines;each of the first and the second wafer-level packaged microelectronic components having a second integrated circuit die located below a first redistribution layer respectively thereof; anda third and a fourth integrated circuit die respectively surface mount coupled over the first and the second wafer-level ...

Method for preparing semiconductor package structure

The present disclosure provides a method for preparing a semiconductor package structure. The method includes the following steps. A first die is provided. A second die including a plurality of first conductors is bonded to the first die. A plurality of second conductors are disposed on the first die. A molding is disposed to encapsulate the first die, the second die and the plurality of second conductors. An RDL is disposed on the second die and the molding. A plurality of connecting structures are disposed on the RDL.

Manufacturing method of semiconductor package

A manufacturing method of a semiconductor package is provided as follows. A semiconductor die is provided, wherein the semiconductor die comprises a semiconductor substrate, an interconnection layer and a through semiconductor via, the interconnection layer is disposed on an active surface of the semiconductor substrate, the through semiconductor via penetrates the semiconductor substrate from a back surface of the semiconductor substrate to the active surface of the semiconductor substrate. An encapsulant is provided to laterally encapsulate the semiconductor die. A through encapsulant via penetrating through the encapsulant is formed.

SEMICONDUCTOR MODULE STRUCTURE

A semiconductor module structure includes: a semiconductor element portion including a plurality of capacitor elements; two bus bars sandwiching the semiconductor element portion and being electrically connected to the semiconductor element portion; and cooling fins, which are conductive, formed on respective surfaces of the bus bars at positions sandwiching the semiconductor element portion. Further, insulating refrigerant is provided in the cooling fins. 1. A semiconductor module structure comprising:a semiconductor element portion including a plurality of capacitor elements;two bus bars sandwiching the semiconductor element portion and being electrically connected to the semiconductor element portion; andcooling fins, which are conductive, formed on respective surfaces of the bus bars at positions sandwiching the semiconductor element portion,wherein insulating refrigerant is provided in the cooling fins.2. The semiconductor module structure according to claim 1 , wherein the semiconductor element portion has a package structure housing semiconductor elements therein claim 1 , and a space in the package structure is filled with a resin mold.3. The semiconductor module structure according to claim 1 , wherein the bus bars are formed of an annular member claim 1 , and a plurality of pairs of the semiconductor element portion and the capacitor elements are arranged along a circumferential direction of the bus bars. The present application claims priority to and incorporates by reference the entire contents of Japanese Patent Application No. 2019-135894 filed in Japan on Jul. 24, 2019.The present disclosure relates to a semiconductor module structure.Japanese Laid-open Patent Publication No. 2017-188998 describes a structure including: a switching element; a capacitor; a bus bar that electrically connects the switching element and the capacitor; and a cooler for cooling by arranging the switching element and the capacitor on the same plane. Further, the bus bar is in ...

SEMICONDUCTOR DEVICE

A lower electrode, an upper electrode provided above the lower electrode, a semiconductor chip provided between the lower electrode and the upper electrode, a pressure pad provided between the lower electrode and the upper electrode to be overlapped with the semiconductor chip, and a spiral conductor provided between the lower electrode and the upper electrode to be overlapped with the semiconductor chip and the pressure pad are provided. The spiral conductor has an upper spiral conductor, and a lower spiral conductor which is in contact with a lower end of the upper spiral conductor and faces the upper spiral conductor, and by forming grooves in the upper spiral conductor and the lower spiral conductor, a direction of a current flowing through the upper spiral conductor coincides with a direction of a current flowing through the lower spiral conductor in plan view. 1. A semiconductor device comprising:a lower electrode;an upper electrode provided above the lower electrode;a semiconductor chip provided between the lower electrode and the upper electrode;a pressure pad provided between the lower electrode and the upper electrode to be overlapped with the semiconductor chip; anda spiral conductor provided between the lower electrode and the upper electrode to be overlapped with the semiconductor chip and the pressure pad, whereinthe spiral conductor has an upper spiral conductor, and a lower spiral conductor which is in contact with a lower end of the upper spiral conductor and faces the upper spiral conductor, andby forming grooves in the upper spiral conductor and the lower spiral conductor, a direction of a current flowing through the upper spiral conductor coincides with a direction of a current flowing through the lower spiral conductor in plan view.2. The semiconductor device according to claim 1 , wherein a portion of the upper spiral conductor that has a largest width is brought into contact with a portion of the lower spiral conductor that has a largest width ...

LOW STRESS ASYMMETRIC DUAL SIDE MODULE

Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers. 1. A semiconductor package comprising:a first substrate comprising two or more die coupled to a first side of the first substrate, wherein a clip is coupled to each of the two or more die;a second substrate comprising two or more die coupled to a first side of the second substrate, wherein a clip is coupled to each of the two or more die;two or more spacers coupled to the first side of the first substrate; anda lead frame comprised between the first substrate and the second substrate;a molding compound encapsulating the lead frame wherein a second side of each of the first substrate and the second substrate are exposed through the molding compound; andwherein a perimeter of the first substrate and a perimeter of the second substrate do not fully overlap when coupled through the two or more spacers.2. The semiconductor package of claim 1 , wherein the two or more die include an insulated-gate bipolar transistors (IGBT) and a fast recovery die (FRD).3. The semiconductor package of claim 1 , wherein the first substrate and the second substrate comprise a direct bonded copper substrate with one of an alumina (AlO) ceramic doped with zirconium dioxide (ZrO) claim 1 , a silicon ...

SEMICONDUCTOR DEVICE

A semiconductor device includes an inverter circuit having a first switching element and a second switching element, a first control circuit, a second control circuit, and a limiting unit. The first switching element is supplied with a power supply voltage. The second switching element includes a first terminal connected to the first switching element, a second terminal connected to ground, and a control terminal. The first control circuit controls the first switching element. The second control circuit controls the second switching element. The limiting unit reduces fluctuation in voltage between the second terminal and the control terminal based on voltage fluctuation at the second terminal of the second switching element. 1. A semiconductor device comprising: a first switching element supplied with a power supply voltage, and', a first terminal connected to the first switching element,', 'a second terminal connected to ground, and', 'a control terminal;, 'a second switching element including'}], 'an inverter circuit including'}a first control circuit that controls the first switching element;a second control circuit that controls the second switching element; anda limiting unit that reduces fluctuation in voltage between the second terminal and the control terminal based on voltage fluctuation at the second terminal of the second switching element.2. The semiconductor device according to claim 1 , further comprising:an integrated circuit element spaced apart from the inverter circuit, wherein the second control circuit is mounted on the integrated circuit, and the integrated circuit includes an output terminal and an input terminal electrically connected to the second control circuita control wire that electrically connects the control terminal and the output terminal, andthe limiting unit includes a limiting wire that is separate from the control wire and electrically connected to the input terminal and the second terminal.3. The semiconductor device according ...

POWER ELECTRONICS MODULE

A power electronics module comprises a first liquid cooler comprising a cooling channel for receiving a cooling liquid, wherein the first liquid cooler comprises a metal body providing a first terminal of the power electronics module; a second liquid cooler comprising a cooling channel for receiving a cooling liquid, wherein the second liquid cooler comprises a metal body providing a second terminal of the power electronics module; a plurality of semiconductor chips arranged between the first liquid cooler and the second liquid cooler, such that a first electrode of each semiconductor chip is bonded to the first liquid cooler, such that the first electrode is in electrical contact with the first liquid cooler, and an opposite second electrode of each semiconductor chip is in electrical contact with the second liquid cooler; and an insulating encapsulation, formed by molding the first liquid cooler, the second liquid cooler and the plurality of semiconductor chips into an insulation material, such that the first liquid cooler, the second liquid cooler and the plurality of semiconductor chips are at least partially embedded onto the insulation material. 1. A power electronics module , comprising:a first liquid cooler comprising a cooling channel for receiving a cooling liquid, wherein the first liquid cooler comprises a metal body providing a first terminal of the power electronics module;a second liquid cooler comprising a cooling channel for receiving a cooling liquid, wherein the second liquid cooler comprises a metal body providing a second terminal of the power electronics module;a plurality of semiconductor chips arranged between the first liquid cooler and the second liquid cooler, such that a first electrode of each semiconductor chip is bonded to the first liquid cooler, such that the first electrode is in electrical contact with the first liquid cooler, and an opposite second electrode of each semiconductor chip is in electrical contact with the second ...

SEMICONDUCTOR DEVICE AND METHOD OF INTEGRATING POWER MODULE WITH INTERPOSER AND OPPOSING SUBSTRATES

A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly. 1. A method of making a semiconductor device , comprising:providing an interposer with a vertical interconnect structure;providing a first substrate including a first conductive layer formed over a first surface of the first substrate and a second conductive layer formed over a second surface of the first substrate opposite the first surface, wherein the first substrate is thermally conductive and electrically insulative so that no portion of the first conductive layer is electrically connected to any portion of the second conductive layer;disposing a first semiconductor die between the interposer and first substrate;providing a second substrate including a third conductive layer formed over a first surface of the second substrate and a fourth conductive layer formed over a second surface of the second substrate opposite the first surface, wherein the second substrate is thermally conductive and electrically insulative so that no portion of the third conductive layer is electrically connected to any portion of the fourth conductive ...

PACKAGED POWER ELECTRONIC DEVICE, IN PARTICULAR BRIDGE CIRCUIT COMPRISING POWER TRANSISTORS, AND ASSEMBLING PROCESS THEREOF

The device has a first support element forming a first thermal dissipation surface and carrying a first power component; a second support element forming a second thermal dissipation surface and carrying a second power component, a first contacting element superimposed to the first power component; a second contacting element superimposed to the second power component; a plurality of leads electrically coupled with the power components through the first and/or the second support elements; and a thermally conductive body arranged between the first and the second contacting elements. The first and the second support elements and the first and the second contacting elements are formed by electrically insulating and thermally conductive multilayers. 1. A packaged power electronic device , comprising:a first support element having a first face and a second face, the first face of the first support element forming a first thermal dissipation surface of the device;a second support element having a first face and a second face, the first face of the second support element forming a second thermal dissipation surface of the device, the first and the second support elements being superimposed on each other with the respective second faces facing each other;a first power component attached to the second face of the second support element;a second power component attached to the second face of the first support element;a first contacting element on the second power component;a second contacting element on the first power component;a first lead electrically coupled with the first power component through the first support element;a second lead electrically coupled with the second power component through the second support element; anda thermally conductive body arranged between the first and second contacting elements;wherein the first and second support elements and the first and second contacting elements are formed respectively by electrically insulating and thermally ...

Pad Design For Reliability Enhancement in Packages

A package includes a corner, a device die, a molding material molding the device die therein, and a plurality of bonding features. The plurality of bonding features includes a corner bonding feature at the corner, wherein the corner bonding feature is elongated. The plurality of bonding features further includes an additional bonding feature, which is non-elongated. 1. A method comprising: a device die;', 'a first through-via and a second through-via, wherein the first through-via has an elongated top-view shape, and the second through-via has a non-elongated top-view shape; and', 'a molding material molding the device die, the first through-via, and the second through-via therein;, 'forming a first package comprisingetching a dielectric material of the first package to expose surfaces of the first through-via and the second through-via; andforming a first solder region and a second solder region contacting the surfaces of the first through-via and the second through-via.2. The method of claim 1 , wherein the etching comprises an isotropic etching process.3. The method of claim 1 , wherein after the etching claim 1 , top surfaces of the first through-via and the second through-via are higher than top surfaces of the molding material.4. The method of claim 3 , wherein the etching the dielectric material comprises:etching a dielectric layer to reveal the first through-via and the second through-via; andperforming an over-etching process to etch a top portion of an molding material under the dielectric layer to expose sidewalls of the first through-via and the second through-via.5. The method of further comprising claim 4 , before the etching the dielectric material:forming the dielectric layer, wherein the first through-via and the second through-via are covered by the dielectric layer at a time the etching is started.6. The method of claim 1 , wherein after the etching the dielectric material claim 1 , a die-attach film is revealed.7. The method of claim 6 , wherein ...

Semiconductor device

There is provided a semiconductor device including: a first semiconductor element including a first gate electrode, a first source electrode, and a first drain electrode; a second semiconductor element including a second gate electrode, a second source electrode, and a second drain electrode; a gate lead, a source lead, a first drain lead, and a second drain lead; and a resin part, wherein the first gate electrode and the first source electrode, and the first drain electrode are provided on opposite sides to each other in a first direction, wherein the second gate electrode and the second source electrode, and the second drain electrode are provided on opposite sides to each other in the first direction, wherein the first gate electrode and the second gate electrode are opposed to the first source electrode and the second source electrode, respectively, in the first direction.

Electronic module

An electronic module comprising a first electronic unit 51 which has a first insulating substrate 61 and a first electronic element 41 provided on the first insulating substrate 61 via a first conductor layer 21 , a second electronic unit 52 which has a second insulating substrate 62 and a second electronic element 42 provided on the second insulating substrate 62 via a second conductor layer 22 , a connecting body 29 provided between the first electronic unit 51 and the second electronic unit 52 and a coil 70 wound around the connecting body 29.

MULTI-CHIP SILICON SUBSTRATE-LESS CHIP PACKAGING

Examples generally provide a stacked silicon interconnect product and method of manufacture. The stacked silicon interconnect product includes a silicon substrate-less interposer comprising a plurality of metallization layers, wherein at least one metallization layer includes a plurality of metal segments separated by dielectric material. The stacked silicon interconnect product also includes a first die coupled to a first side of the silicon substrate-less interposer via a first plurality of microbumps. The stacked silicon interconnect product further includes a second die coupled to a second side of the silicon substrate-less interposer via a second plurality of microbumps, the second die communicatively coupled to the first die through a metallization layer of the plurality of metallization layers. 1. A stacked silicon interconnect product , comprising:a silicon substrate-less interposer comprising a plurality of metallization layers, wherein at least one metallization layer includes a plurality of metal segments separated by dielectric material;a first die coupled to a first side of the silicon substrate-less interposer via a first plurality of microbumps; anda second die coupled to a second side of the silicon substrate-less interposer via a second plurality of microbumps, the second die communicatively coupled to the first die through a metallization layer of the plurality of metallization layers.2. The stacked silicon interconnect product of claim 1 , wherein the silicon substrate-less interposer further comprises:a dielectric layer defining the second side of the silicon substrate-less interposer, wherein the dielectric layer includes an opening exposing a metal segment included in the metallization layer.3. The stacked silicon interconnect product of claim 2 , wherein the silicon substrate-less interposer further comprises:a passivation layer formed on the dielectric layer and having an opening that corresponds spatially with the opening in the dielectric ...

POWER SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME

A power semiconductor module is provided. The power semiconductor module includes a lower substrate and a first electronic device bonded to a surface of the lower substrate. A lead frame has a first side surface bonded to a surface of the first electronic device by a first adhesive, and a second electronic device bonded to a second side surface of the lead frame by the first adhesive. An upper substrate is bonded to a surface of the second electronic device. 1. A power semiconductor module , comprising:a lower substrate;a first electronic device bonded to a surface of the lower substrate;a lead frame having a first side surface bonded to a surface of the first electronic device by a first adhesive;a second electronic device bonded to a second side surface of the lead frame by the first adhesive; andan upper substrate bonded to a surface of the second electronic device.2. The power semiconductor module of claim 1 , wherein the upper substrate and the lower substrate are each a conductive heat radiating processing substrate having an insulator disposed therein to emit heat.3. The power semiconductor module of claim 1 , wherein the lead frame is positioned at a center between the upper substrate and the lower substrate with the upper substrate and the lower substrate positioned adjacent to each other to provide a heat radiating path.4. The power semiconductor module of claim 1 , wherein the first electronic device and the second electronic device are different.5. The power semiconductor module of claim 4 , wherein the first electronic device and the second electronic device are each a power semiconductor device or a polar semiconductor device.6. The power semiconductor module of claim 5 , wherein the power semiconductor device is selected from a group consisting of an insulated gate transistor (IGBT) claim 5 , a bipolar claim 5 , and a power metal oxide silicon field effect transistor (MOSFET) claim 5 , and the polar semiconductor device is a diode.7. The power ...

Electronic power module with enhanced thermal dissipation and manufacturing method thereof

An electronic power module comprising a case that houses a stack, which includes: a first substrate of a DBC type or the like; a die, integrating an electronic component having one or more electrical-conduction terminals, mechanically and thermally coupled to the first substrate; and a second substrate, of a DBC type or the like, which extends over the first substrate and over the die and presents a conductive path facing the die. The die is mechanically and thermally coupled to the first substrate by a first coupling region of a sintered thermoconductive paste, and the one or more conduction terminals of the electronic component are mechanically, electrically, and thermally coupled to the conductive path of the second substrate by a second coupling region of sintered thermoconductive paste.

Semiconductor Package, Semiconductor Module and Methods for Manufacturing a Semiconductor Package and a Semiconductor Module

A semiconductor package includes a semiconductor die having opposing first and second main surfaces, a first power electrode on the first main surface and a second power electrode on the second main surface, a first lead having an inner surface attached to the first power electrode and a distal end having a first protruding side face extending substantially perpendicularly to the first main surface of the die, a second lead having an inner surface attached to the second power electrode and a distal end having a second protruding side face extending substantially perpendicularly to the second main surface of the die, and a mold compound enclosing at least part of the die and at least part of the first and second leads. The first lead includes a recess positioned in an edge of the inner surface. The second lead includes a recess positioned in an edge of the inner surface. 1. A semiconductor package , comprising:a semiconductor die comprising opposing first and second main surfaces, a first power electrode on the first main surface and a second power electrode on the second main surface;a first lead comprising an inner surface attached to the first power electrode of the semiconductor die and a distal end that comprises a first protruding side face that extends substantially perpendicularly to the first main surface of the semiconductor die;a second lead comprising an inner surface attached to the second power electrode of the semiconductor die and a distal end that comprises a second protruding side face that extends substantially perpendicularly to the second main surface of the semiconductor die; anda mold compound enclosing at least part of the semiconductor die and at least part of the first and second leads,wherein the first lead comprises a recess positioned in an edge of the inner surface,wherein the second lead comprises a recess positioned in an edge of the inner surface.2. The semiconductor package of claim 1 , wherein the first lead is attached to the first ...

Power module

A power module will be provided which can suppress insulation performance deterioration caused by heat cycle to ensure insulation performance, by suppressing generation of bubbles and occurrence of detachments between silicone gel and an insulating substrate at a high or low temperature or at a high working voltage. The power module includes: an insulating substrate 2 on a first face of which a semiconductor element 3 is provided; a base plate 1 joined to a second face of the insulating substrate 2; a case member 6 surrounding the insulating substrate 2 and being in contact with a face of the base plate 1, that is joined to the insulating place 2; sealing resin 8 filling a region surrounded by the base plate 1 and the case member 6 to seal the insulating substrate 2; a pressing plate 9 disposed in close contact with a surface of the sealing resin 8 in a side of the first face of the insulating substrate 2; and a lid member 7 facing an opposite face of the pressing plate 9 with respect to a face thereof in close contact with the sealing resin 8, and being fixed to the case member 6 at a position to prevent the pressing plate 9 from ascending.

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor substrate in which a through hole is formed, a transistor formed on the upper surface side of the semiconductor substrate, a detection circuit formed on the upper surface side of the semiconductor substrate and connected to the transistor, a dielectric film covering the transistor and the detection circuit, a solder bump formed on the dielectric film, and a pad electrode having a first portion connected to an output of the detection circuit in the through hole, and a second portion connected to the first portion and provided on a lower surface of the semiconductor substrate. 1. A semiconductor device comprising:a semiconductor substrate in which a through hole is formed;a transistor formed on the upper surface side of the semiconductor substrate;a detection circuit formed on the upper surface side of the semiconductor substrate and connected to the transistor;a dielectric film covering the transistor and the detection circuit;a solder bump formed on the dielectric film; anda pad electrode having a first portion connected to an output of the detection circuit in the through hole, and a second portion connected to the first portion and provided on a lower surface of the semiconductor substrate.2. The semiconductor device according to claim 1 , wherein the detection circuit is connected on the output side of the transistor.3. The semiconductor device according to claim 2 , further comprising:an input-side detection circuit formed in the dielectric film and connected on the input side of the transistor; andan input detection pad electrode having a third portion connected to an output of the input-side detection circuit in a through hole provided in the semiconductor substrate other than the aforementioned through hole, and a fourth portion connected to the third portion and provided on the lower surface of the semiconductor substrate.4. A semiconductor device comprising:a semiconductor substrate in which a through hole is ...

POWER SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME

The present disclosure describes a power electronics module comprising a lead frame in which a chip of a first semiconductor device is embedded, a first PCB mounted on top of the lead frame and the chip of the first semiconductor device, and a support frame mounted on top of the PCB, the support frame comprising a cavity in which the chip of a second semiconductor device is embedded, wherein the chips of the first semiconductor device and the second semiconductor device are positioned on top of each other, and the first PCB comprises a first electrically conducting path between the chips of the first semiconductor device and the second semiconductor device. 1. A power electronics module comprising a first semiconductor device and a second semiconductor device , wherein the module is configured to operate such that , in response to a control signal , a current flowing through one of the semiconductor devices commutates to flow through the other semiconductor device , wherein the power electronics module further comprisesa lead frame in which a chip of the first semiconductor device is embedded,a first PCB mounted on top of the lead frame and the chip of the first semiconductor device, anda support frame mounted on top of the PCB, wherein the chip of the second semiconductor device is embedded in the support frame, andwherein 'the first PCB comprises a first electrically conducting path between the chips of the first semiconductor device and the second semiconductor device.', 'the chips of the first semiconductor device and the second semiconductor device are positioned on top of each other,'}2. A power electronics module according to claim 1 , the power electronics module comprising a first semiconductor switch and a second semiconductor switch connected in series claim 1 , a first semiconductor rectifier connected in parallel with the first switch claim 1 , and a second semiconductor rectifier connected in parallel with the second switch claim 1 , wherein the first ...

Pad Design for Reliability Enhancement in Packages

A package includes a corner, a device die, a molding material molding the device die therein, and a plurality of bonding features. The plurality of bonding features includes a corner bonding feature at the corner, wherein the corner bonding feature is elongated. The plurality of bonding features further includes an additional bonding feature, which is non-elongated. 1. A package comprising: a corner;', 'a device die;', 'a molding material molding the device die therein; and', a first bonding feature at the corner, wherein the first bonding feature is elongated in a top view of the first package; and', 'a second bonding feature, wherein the second bonding feature is non-elongated, and wherein the first bonding feature and the second bonding feature have a same top-view area., 'a plurality of bonding features comprising], 'a first package comprising2. The package of claim 1 , wherein the first bonding feature and the second bonding feature comprise a first bonding pad and a second bonding pad claim 1 , respectively.3. The package of claim 1 , wherein the first bonding feature and the second bonding feature comprise a first through-via and a second through-via claim 1 , respectively claim 1 , with the first through-via and the second through-via penetrating through the molding material.4. The package of further comprising:a second package; anda first solder region bonding the first bonding feature to the second package; anda second solder region bonding the second bonding feature to the second package.5. The package of claim 4 , wherein the first solder region and the second solder region are in contact with a first sidewall of the first bonding feature and a second sidewall of the second bonding feature claim 4 , respectively.6. The package of claim 5 , wherein an interface between the first solder region and the first sidewall of the first bonding feature form a ring.7. The package of claim 4 , wherein the second package comprises a metal pad in contact with the ...

Semiconductor package and method for routing the package

A semiconductor package having improved performance and reliability and a method of fabricating the same are provided. The semiconductor package includes a processing chip including a first pin at a first side to output a first signal, and a second pin at a second side to output a second signal different from the first signal, and a substrate having the processing chip thereon, the substrate including a first bump ball electrically connected to the first pin and a second bump ball electrically connected to the second pin, wherein the first bump ball and the second bump ball are adjacent at one of the first and second sides of the substrate.

Semiconductor module and method of manufacturing the same

There is provided a semiconductor module capable of being easily manufactured. The semiconductor module includes: a control part including at least one control device; and a power part including at least one power device, wherein any one of the control part and the power part includes contact pins having elasticity, and the control part and the power part are electrically connected to each other by the contact pins.

ELEMENT MODULE

An element module includes a cooler, a plurality of elements, and a conductive member. The cooler includes a first element disposition portion and a second element disposition portion which are provided on both sides in a predetermined direction. The plurality of elements are disposed in each of the first element disposition portion and the second element disposition portion. The conductive member is disposed in a space portion of the cooler. The space portion penetrates the cooler between the plurality of elements in each of the first element disposition portion and the second element disposition portion. The space portion allows the first element disposition portion and the second element disposition portion to communicate with each other. The conductive member is connected to the element of the first element disposition portion and the element of the second element disposition portion. 13-. (canceled)4. An element module , comprising:a cooler including a first element disposition portion and a second element disposition portion which are provided on both sides in a predetermined direction, and including at least one refrigerant storage portion configured to internally store a refrigerant between the first element disposition portion and the second element disposition portion;a plurality of elements disposed in each of the first element disposition portion and the second element disposition portion, and including transistors;a conductive member disposed in a space portion through which the first element disposition portion and the second element disposition portion are allowed to communicate with each other by penetrating the cooler between the plurality of elements in each of the first element disposition portion and the second element disposition portion, and connected to the element of the first element disposition portion and the element of the second element disposition portion;a plurality of conductor plates disposed on a side opposite to each facing side of ...

POWER ELECTRONICS ASSEMBLY HAVING STAGGERED AND DIAGONALLY ARRANGED TRANSISTORS

Methods, apparatuses and systems to provide for technology to that includes a first power electronics module including a plurality of first transistors that are diagonally offset from each other, and a second power electronics module stacked on the first power electronics module. The second power electronics module includes second transistors that are diagonally offset from each other. The second transistors are staggered relative to the first transistors.

POWER SEMICONDUCTOR MODULE FOR IMPROVED HEAT DISSIPATION AND POWER DENSITY, AND METHOD FOR MANUFACTURING THE SAME

The present disclosure relates to a semiconductor module, especially a power semiconductor module, in which the heat dissipation is improved and the power density is increased. The semiconductor module may include at least two electrically insulating substrates, each having a first main surface and a second main surface opposite to the first main surface. On the first main surface of each of the substrates, at least one semiconductor device is mounted. An external terminal is connected to the first main surface of at least one of the substrates. The substrates are arranged opposite to each other so that their first main surfaces are facing each other. 1. A semiconductor module , comprising:at least two electrically insulating substrates, each having a first main surface and a second main surface opposite to the first main surface;for each of the substrates, at least one semiconductor device mounted on the first main surface of the corresponding substrate;an external terminal connected to the first main surface of at least one of the substrates; andthe at least two substrates electrically interconnected by an internal lead frame or by internal pins;wherein the substrates are arranged opposite to each other so that respective first main surfaces of the substrates are facing each other.2. The semiconductor module according to claim 1 , further comprising:an encapsulation, wherein the second main surfaces of each of the substrates are exposed on opposite sides of the encapsulation.3. The semiconductor module according to claim 1 , wherein the substrates are thermally conductive.4. The semiconductor module according to claim 1 , wherein the at least one semiconductor device is a power semiconductor device.5. The semiconductor module according to claim 1 , wherein a heat sink is mounted to at least one of the second main surfaces of the substrates.6. The semiconductor module according to claim 1 , whereinthe external terminal comprises at least two external leads, and ...

Multi-phase common contact package

In some examples, a device includes a first leadframe segment and a second leadframe segment, wherein the second leadframe segment is electrically isolated from the first leadframe segment. The device further includes at least four transistors comprising at least two high-side transistors electrically connected to the first leadframe segment and at least two low-side transistors electrically connected to the second leadframe segment. The device further includes at least two conductive output elements, wherein each conductive output element of the at least two conductive output elements is electrically connected to a respective high-side transistor of the at least two high-side transistors and a respective low-side transistor of the at least two low-side transistors. The device further includes an integrated circuit electrically connected to a control terminal of each transistor of the at least four transistors.

Semiconductor package having dummy pads and method of manufacturing semiconductor package having dummy pads

A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the second semiconductor chip, and a plurality of dummy pads disposed outside of an area occupied by the first semiconductor chip or the second semiconductor chip from a top-down view and disposed on the top surface of the interposer substrate. Each pad of the first plurality of signal pads and the second plurality of signal pads is configured to transfer signals between the interposer substrate and a respective semiconductor chip, and each pad of the dummy pads is not configured to transfer signals between the interposer substrate and any semiconductor chip disposed thereon.

Semiconductor device and method of manufacturing semiconductor device

A source terminal and a gate terminal are connected to a wiring pattern of the first substrate. A diode is provided under a second substrate such that an anode is connected to a wiring pattern of the second substrate. A plate-like portion of the first electrode is provided between the switching element and the diode, and a linking section of the first electrode connects the plate-like portion and the wiring pattern of the first substrate. A second electrode being substantially columnar and connecting the wiring pattern of the first substrate and the wiring pattern of the second substrate is provided in an opposite side to the linking section with the switching element interposed. A thickness of the plate-like portion of the first electrode is less than or equal to a thickness of each of the wiring pattern of the first substrate and the wiring pattern of the second substrate.

Semiconductor Device With shield for Electromagnetic interference

A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.

SEMICONDUCTOR MODULE

A semiconductor module includes a plurality of insulating circuit boards including semiconductor chips, each of the plurality of insulating circuit boards including a first outer edge among outer edges of the insulating circuit board facing an adjacent insulating circuit board of the plurality of insulating circuit boards, and a second outer edge among the outer edges excluding the first outer edge; a resin frame body having a crosspiece abutting against the first outer edges, and a frame element abutting against the second outer edges; a conductive component striding over the crosspiece to electrically connect the insulating circuit boards to each other; and an upper lid having a lid element covering an opening disposed at an upper part of the resin frame body and a partition protruding from a face of the lid element facing the insulating circuit boards to abut against a part of the crosspiece. 1. A semiconductor module comprising:a plurality of insulating circuit boards including semiconductor chips, each of the plurality of insulating circuit boards including a first outer edge among outer edges of the insulating circuit board facing an adjacent insulating circuit board of the plurality of insulating circuit boards, and a second outer edge among the outer edges of the insulating circuit board excluding the first outer edge;a resin frame body having a crosspiece abutting against the first outer edges of the plurality of insulating circuit boards, and a frame element abutting against the second outer edges of the plurality of insulating circuit boards;a conductive component striding over the crosspiece to electrically connect the insulating circuit boards to each other; andan upper lid having a lid element covering an opening disposed at an upper part of the resin frame body, and a partition protruding from a face of the lid element facing the insulating circuit boards and abutting against a part of the crosspiece.2. The semiconductor module according to claim 1 , ...

Laminated substrate and method for manufacturing laminated substrate

A laminated substrate includes: a core portion; a first wiring portion configured to be stacked on the core portion and to include a first exposed surface formed by exposing at least part of a surface of the first wiring portion; and a second wiring portion configured to be stacked on the first wiring portion, to include a second exposed surface formed by exposing at least part of a surface of the second wiring portion, and to have higher wiring density of conductor than the first wiring portion has, wherein the first exposed surface and the second exposed surface are provided respectively with a first pad and a second pad which are to be connected to electrodes of one semiconductor chip to be mounted on both the first exposed surface and the second exposed surface.

Manufacturing method of package-on-package structure

A manufacturing method of a POP structure including at least the following steps is provided. A first package structure is formed and a second package structure is formed on the first package structure. The first package structure includes a circuit carrier and a die disposed on the circuit carrier. Forming the first package structure includes providing a conductive interposer on the circuit carrier, encapsulating the conductive interposer by an encapsulant and removing a portion of the encapsulant and the plate of the conductive interposer. The conductive interposer includes a plate, a plurality of conductive pillars and a conductive protrusion respectively extending from the plate to the circuit carrier and the die. The conductive protrusion disposed on the die, and the conductive pillars are electrically connected to the circuit carrier. The second package structure is electrically connected to the first package structure through the conductive interposer.

Package structure and manufacturing method thereof

A package structure and a manufacturing method thereof are provided. The package structure includes a circuit carrier, a substrate, a die, a plurality of conductive wires and an encapsulant. The substrate is disposed on the circuit carrier and includes a plurality of openings. The die is disposed between the circuit carrier and the substrate. The conductive wires go through the openings of the substrate to electrically connect between the substrate and the circuit carrier. The encapsulant is disposed on the circuit carrier and encapsulates the die, the substrate and the conductive wires.

Chip package structure and manufacturing method thereof

A chip package structure including a substrate, a first chip, a frame, a plurality of first conductive connectors, a first encapsulant, and a package is provided. The first chip is disposed on the substrate. The first chip has an active surface and a back surface opposite to the active surface, and the active surface faces the substrate. The frame is disposed on the back surface of the first chip and the frame has a plurality of openings. The first conductive connectors are disposed on the substrate and the first conductive connectors are disposed in correspondence to the openings. The first encapsulant is disposed between the substrate and the frame and encapsulates the first chip. The package is disposed on the frame and is electrically connected to the substrate via the first conductive connectors.

Semiconductor package structures, semiconductor device packages and methods of manufacturing the same

A semiconductor package structure includes a first substrate, a second substrate, a first redistribution layer, and a first reconnection layer. The first substrate may have a first surface. The second substrate can be spaced apart from the first substrate with a gap and may have a second surface. The first redistribution layer can be disposed between the first redistribution layer and the gap. The first substrate can be electrically connected to the second substrate via the first reconnection layer.

TRIPLE STACK SEMICONDUCTOR PACKAGE

A method for forming a stacked semiconductor package includes providing a bottom leadframe (LF) panel including LFs downset each including at least a plurality of terminals. Low side (LS) transistors are attached to the first die attach area. A first clip panel including first clips downset and interconnected are placed on the bottom LF panel. A dielectric interposer is attached on the first clips over the LS transistors. High side (HS) transistors are attached on the interposers. A second clip panel including a plurality of second clips is mated to interconnect to the HS transistors including mating together the second clip panel, first clip panel and bottom LF panel. The LFs can include a second die attach area, and a controller die attached on the second die attach area, and then pads of the controller die wirebonded to the plurality of terminals. 18-. (canceled)8. A method for forming a stacked semiconductor package , comprising:providing a bottom leadframe (LF) panel including an interconnected plurality of LFs downset each including a first die attach area, a second die attach area, and a plurality of terminals;attaching a plurality of low side (LS) transistors to said first die attach area;mating a first clip panel including a plurality of first clips downset and interconnected on said bottom LF panel;attaching a dielectric interposer on each of said plurality of first clips over said LS transistors;attaching a plurality of high side (HS) transistors on said interposers;mating a second clip panel including a plurality of second clips to interconnect to said HS transistors including mating together said second clip panel, said first clip panel and said bottom LF panel; attaching a controller die on said second die attach area; and', 'wire bonding bond pads of said controller die to ones of said plurality of terminals., 'after said mating second clip panel,'}9. The method of claim 8 , further comprising molding with a mold material and then sawing to form a ...

High Density Microelectronics Packaging

Example packaging of microelectronics and example methods of manufacturing the same are provided herein. The packaging can enable and/or improve the use of the microelectronics in a downhole, high temperature and/or high pressure setting. The microelectronics packaging can include double-sided active components, heat sinks, and/or three-dimensional stacking of dies. 1. A high temperature multi-chip module packaging comprising:a ceramic substrate having two sides with active components on both sides; anda housing attached to the ceramic substrate by brazing.2. The high temperature multi-chip module packaging of claim 1 , wherein the ceramic substrate is directly brazed to the housing.3. The high temperature multi-chip module packaging of claim 1 , wherein the ceramic substrate is brazed to a metal frame claim 1 , the metal frame being welded to the housing.4. The high temperature multi-chip module packaging of claim 1 , wherein the ceramic substrate is brazed to at least one metal post claim 1 , the at least one metal post being welded to the housing.5. The high temperature multi-chip module packaging of claim 1 , further comprising a heat sink attached to the housing.6. The high temperature multi-chip module packaging of claim 5 , wherein the heat sink is brazed to the metal housing.7. The high temperature multi-chip module packaging of claim 5 , further comprising at least one power consumption module disposed on the heat sink.8. The high temperature multi-chip module packaging of claim 7 , wherein the at least one power consumption module is mounted directly on the heat sink.9. The high temperature multi-chip module packaging of claim 7 , wherein the at least one power consumption module is mounted on a second substrate claim 7 , the second substrate comprising at least one of BeO and AlN claim 7 , the second substrate being mounted onto the heat sink.10. The high temperature multi-chip module packaging of claim 1 , further comprising a set of vertically stacked ...

Semiconductor Device and Method of Manufacture

A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device includes a first set of through vias between and connecting a top package and a redistribution layer (RDL), the first set of through vias in physical contact with a molding compound and separated from a die. The semiconductor device also includes a first interconnect structure between and connecting the top package and the RDL, the first interconnect structure separated from the die and from the first set of through vias by the molding compound. The first interconnect structure includes a second set of through vias and at least one integrated passive device. 1. A method comprising: forming an integrated passive device on a first substrate; and', 'forming a first through substrate via (TSV) in the first substrate;, 'forming a first Integrated Passive Device Structure (IPDS), comprisingforming a first via on a second substrate;disposing a first semiconductor device and the first IPDS on the second substrate, wherein the first semiconductor device, the first IPDS, and the first via are separated from each other;encapsulating the first semiconductor device, the first IPDS, and the first via with a first encapsulant, wherein the first via extends from a first side of the encapsulant to a second side of the encapsulant; andforming a first redistribution layer (RDL) over the first side of the encapsulant, wherein the first RDL is electrically connected to the first semiconductor device, the first IPDS, and the first via.2. The method of claim 1 , wherein forming the integrated passive device comprises forming a deep-trench capacitor.3. The method of claim 1 , wherein forming a first IPDS further comprises forming a metallization layer over the substrate claim 1 , and wherein the first RDL is electrically connected to the integrated passive device through the metallization layer.4. The method of claim 1 , further comprising:forming a second IPDS; anddisposing the second ...

Integrated circuit supports with microstrips

Disclosed herein are integrated circuit (IC) supports with microstrips, and related embodiments. For example, an IC support may include a first microstrip; a first surface dielectric region over the first microstrip, wherein the first surface dielectric region has a first thickness, and the first thickness is nonzero; a second microstrip; and a second surface dielectric region over the second microstrip, wherein the second surface dielectric region has a second thickness, the second thickness is nonzero, and the first thickness is different than the second thickness.

Semiconductor device

A semiconductor device may include a cooling unit, the cooling unit including a circuit unit, a first flow path member comprised of an insulating material, and a second flow path member comprised of an insulating material. The circuit unit may include a heat sink layer, a wiring layer, and a semiconductor element that is disposed between the heat sink layer and the wiring layer. The circuit unit is disposed between the first flow path member and the second flow path member. The wiring layer may face the first flow path member or the second flow path member.

LIGHT EMITTING APPARATUS

A light emitting apparatus including a first semiconductor layer, a light emitting layer, a second semiconductor layer, an insulation layer, a first electrode and a second electrode is provided. The light emitting layer is disposed on the first semiconductor layer. The second semiconductor layer is disposed on the light emitting layer. The insulation layer is at least disposed on a side wall of the first semiconductor layer. The first electrode is disposed on a bottom surface of the first semiconductor layer and at least one portion of the insulation layer. The second electrode is disposed on the second semiconductor layer. 1. A light emitting apparatus , comprising:a first semiconductor layer;a light emitting layer disposed on the first semiconductor layer;a second semiconductor layer disposed on the light emitting layer, wherein the light emitting layer has a bottom surface, a top surface and a side wall, the side wall of the light emitting layer is connected between the bottom surface of the light emitting layer and the top surface of the light emitting layer, the first semiconductor layer has a bottom surface, a top surface and a side wall, the side wall of the first semiconductor layer is connected between the bottom surface of the first semiconductor layer and the top surface of the first semiconductor layer, and the top surface of the first semiconductor layer is disposed between the bottom surface of the first semiconductor layer and the bottom surface of the light emitting layer;an insulation layer at least disposed on the side wall of the first semiconductor layer;a first electrode disposed on the bottom surface of the first semiconductor layer and at least one portion of the insulation layer, wherein the first electrode covers at least one portion of the side wall of the first semiconductor layer;a second electrode disposed on the second semiconductor layer;a conductive pattern, disposed on the first electrode covering at least part of the side wall of ...

Semiconductor Device With Shield for Electromagnetic Interference

A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side. 1. A semiconductor device comprising:a first die;a molding material around the first die;a redistribution structure along a first side of the molding material and along a first side of the first die, the redistribution structure being electrically coupled to the first die;a first conductive coating comprising a first portion that extends along and contacts sidewalls of the first die, the first portion being disposed between the first die and the molding material; anda second conductive coating extending along sidewalls of the molding material distal from the first die, along a second side of the molding material opposing the first side of the molding material, and along a second side of the first die opposing the first side of the first die, wherein the molding material is between the first conductive coating and the second conductive coating.2. The semiconductor device of claim 1 , wherein the first conductive coating further comprises a second portion that extends along the second side of the molding material and contacts the second conductive coating.3. The semiconductor device of claim 2 , wherein the second portion of the first conductive coating merges with respective portions of the second conductive coating to form a conductive region claim 2 , wherein the conductive region has a thickness that is about twice that of the first conductive coating or twice that of the second conductive coating.4. The semiconductor device of claim 2 , further ...

SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME

A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices. 1. A semiconductor device , comprising:an interposer disposed on a substrate, wherein a first major surface of the interposer faces the substrate;a first wiring layer disposed on a second major surface of the interposer, wherein the second major surface of the interposer opposes the first major surface of the interposer;a first passive device disposed in the second major surface of the interposer;a second wiring layer disposed on the first major surface of the interposer; anda second passive device disposed in an inductor layer between the second wiring layer and the substrate, wherein the second passive device is different than the first passive device, andwherein the interposer is made of a semiconductor material and the inductor layer is made of a dielectric material.2. The semiconductor device of claim 1 , wherein the second passive device is a magnetic core inductor.3. The semiconductor device of claim 1 , wherein the inductor layer has a thickness of 50 μm to 100 μm.4. The semiconductor device of claim 1 , further comprising at least one semiconductor chip including an integrated circuit disposed on the second major surface of the interposer.5. The semiconductor device of claim 1 , wherein the first passive device is a deep trench capacitor.6. The semiconductor device of claim 5 , wherein the deep trench capacitor has a trench depth of 20 μm to 50 μm.7. The semiconductor device of claim 1 , ...

FORMING A PANEL OF TRIPLE STACK SEMICONDUCTOR PACKAGES

A method for forming a panel of stacked semiconductor packages includes providing a bottom leadframe (LF) panel including LFs downset each including at least a plurality of terminals. Low side (LS) transistors are attached to the first die attach area. A first clip panel including first clips downset and interconnected are placed on the bottom LF panel. A dielectric interposer is attached on the first clips over the LS transistors. High side (HS) transistors are attached on the interposers. A second clip panel including a plurality of second clips is mated to interconnect to the HS transistors including mating together the second clip panel, first clip panel and bottom LF panel. The LFs can include a second die attach area, and a controller die attached on the second die attach area, and then pads of the controller die wirebonded to the plurality of terminals. 15. A method for forming a panel of stacked semiconductor packages , comprising:providing a bottom leadframe (LF) panel including an interconnected plurality of LFs downset each including at least a first die attach area, and a plurality of terminals;attaching a plurality of low side (LS) transistors to said first die attach area;placing a first clip panel including a plurality of first clips downset and interconnected on said bottom LF panel;attaching a dielectric interposer (interposer) on each of said plurality of first clips over said LS transistors;attaching a plurality of high side (HS) transistors on said interposers, and mating a second clip panel including a plurality of second clips to interconnect to said HS transistors including mating together said second clip panel, said first clip panel and said bottom LF panel.16. The method of claim 15 , wherein said plurality of LFs further include a second die attach area claim 15 , further comprising after said mating:attaching a controller die on said second die attach area, and wire bonding bond pads of said controller die to ones of said plurality of ...

SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE

A semiconductor module () has a first insulating substrate (); a first conductor layer () provided on a mounting surface of the first insulating substrate (); a first electronic element () provided on the first conductor layer (); a sealing resin (), which covers an overall mounting region within the mounting surface of the first insulating substrate (), the first conductor layer (), and the first electronic element (); and a frame body (), which is made of metal and covers the overall sealing resin (). 111-. (canceled)12. A semiconductor module comprising:a first insulating substrate;a first conductor layer provided on a mounting surface of the first insulating substrate; 'a second insulating substrate;', 'a first electronic element provided on the first conductor layer;'}a second conductor layer provided on a mounting surface of the second insulating substrate; anda second electronic element provided on the second conductor layer,a sealing resin, which covers an overall mounting region within the mounting surface of the first insulating substrate, the first conductor layer, the first electronic element, the second electronic element, the second conductor layer and an overall mounting region within the mounting surface of the second insulating substrate; anda frame body, which is made of metal and covers the overall sealing resin,wherein the first conductor layer, the first electronic element, the second electronic element and the second conductor layer are arranged in an order between the first insulating substrate and the second insulating substrate,wherein a conductive column connecting the first electronic element with the second electronic element is provided,wherein the first electronic element and the second electronic element are switching devices, and wherein the conductive column is connected to a source electrode.13. The semiconductor module claim 12 , according to claim 12 , further comprising:an outer resin, which is provided outside of the frame body, ...

SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF

A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure. 120-. (canceled)21. A semiconductor device comprising: a first dielectric layer comprising a first dielectric material;', a first trace top side that is partially covered by the first dielectric layer;', 'a first trace bottom side that is exposed at a bottom side of the first dielectric layer; and', 'a first trace lateral side that is covered by the first dielectric layer; and, 'a first conductive trace embedded in the first dielectric layer and comprising, a first via top side that is exposed at a top side of the first dielectric layer;', 'a first via bottom side that is directly coupled to the first trace top side; and', 'a first via lateral side that is covered by the first dielectric layer;, 'a first conductive via embedded in the first dielectric layer and comprising], 'a first redistribution structure comprising a second dielectric layer comprising a second dielectric material;', 'a second conductive trace; and', 'a second conductive via that extends through the second dielectric layer and electrically couples the second conductive trace to the first conductive trace;, 'a second redistribution structure on a bottom side of the first redistribution structure and comprisinga semiconductor die attached to a top side of the first redistribution structure; anda mold material covering at least a portion of the top side of the first redistribution structure and a respective lateral side of the semiconductor die.22. The semiconductor device of claim 21 , comprising an underfill that extends to at least a lateral edge of the upper redistribution structure.23. The semiconductor device of claim 21 , wherein the first and second dielectric materials are different types of dielectric materials.24 ...

Power field-effect transistor (fet), pre-driver, controller, and sense resistor integration for multi-phase power applications

Techniques are described for integrating power field-effect transistors (FETs), pre-drivers, controllers, and/or resistors into a common multi-chip package for implementing multi-phase bridge circuits. The techniques may provide a multi-chip package with at least two high-side (HS) FETs and at least two low-side (LS) FETs, and place the at least two HS FETs or the at least LS FETs on a common die. Placing at least two FETs on a common die may reduce the number of die and the number of thermal pads (i.e., die pads) needed to implement a set of power FETs, thereby decreasing component count of a multi-phase bridge circuit and/or allowing a more compact, higher current density multi-phase bridge circuit to be obtained without significantly increasing thermal power dissipation of the circuit.

PACKAGED INTEGRATED CIRCUIT DEVICES WITH THROUGH-BODY CONDUCTIVE VIAS, AND METHODS OF MAKING SAME

A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material. 1. A semiconductor device , comprising:a semiconductor die having an active surface and a back surface opposite the active surface;a continuous encapsulant in which the semiconductor die is embedded, the encapsulant having a front surface and a back surface opposite the front surface, wherein the active surface of the semiconductor die is generally flush with the front surface of the encapsulant;a conductive via extending through an entire thickness of the encapsulant from the front surface of the encapsulant to the back surface of the encapsulant; anda redistribution layer (RDL) at the front surface of the encapsulant and the active surface of the semiconductor die, the RDL including a conductive line directly coupled to the conductive via and electrically coupling the conductive via to the semiconductor die.2. The semiconductor device of claim 1 , wherein:the semiconductor die includes a bond pad at the active surface of the semiconductor die; andthe conductive line is coupled to the bond pad.3. The semiconductor device of claim 1 , wherein the conductive via is laterally spaced apart from the semiconductor die.4. The semiconductor device of claim 1 , further comprising a solder ball coupled to the conductive line.5. The semiconductor device of claim 1 , further comprising a conductive structure directly coupled to the conductive via proximate the back surface of the encapsulant.6. The semiconductor device of claim 5 , wherein the conductive structure comprises solder.7. The semiconductor device of claim 1 , wherein the back surface of the semiconductor die is embedded in the continuous encapsulant.8. The semiconductor device of claim 1 , wherein:the conductive line is a first conductive line;the conductive via is a first conductive ...

Semiconductor packages

A planar dual die package includes a package substrate and first and second semiconductor dice disposed side by side on a first surface of the package substrate. Outer connectors are disposed on a second surface of the package substrate, and the second surface of the package substrate includes a command/address ball region and a data ball region. Each of the first and second semiconductor dice includes die pads disposed in a command/address pad region corresponding to the command/address ball region and in a data pad region corresponding to the data ball region. Each of the first and second semiconductor dice are disposed on the package substrate so that a first direction from the command/address ball region toward the data ball region coincides with a second direction from the command/address pad region toward the data pad region.

ELECTRONIC POWER MODULE AND ELECTRICAL POWER CONVERTER INCORPORATING SAME

The module (PM) has an architecture with 3D stacking of the electronic power switching chips (IT, ID) and comprises first and second dielectric substrates (SH, SL) that are intended to come into thermal contact with first and second heat sinks (DH, DL), respectively, at least one pair of first and second stacked electronic power switching chips (IT, ID; IT, ID) and a common intermediate substrate (SC), the first and second electronic power switching chips being sandwiched between the first dielectric substrate and the common intermediate substrate and between the common intermediate substrate and the second dielectric substrate, respectively. According to the invention, the common intermediate substrate is a metal element formed as a single piece and comprises a central portion for the implantation of the electronic power switching chips and at least one thermal conduction portion that is in thermal contact with the first dielectric substrate and/or the second dielectric substrate. 1. Electronic power module having an architecture with 3D stacking , comprising first and second dielectric substrates that are intended to come into thermal contact with first and second heat sinks , respectively , at least one pair of first and second stacked electronic power switching chips and a common intermediate substrate , said first and second electronic power switching chips being sandwiched between said first dielectric substrate and said common intermediate substrate and between said common intermediate substrate and said second dielectric substrate , respectively , wherein said common intermediate substrate is a metal element formed as a single piece and comprises a central portion for the implantation of said electronic power switching chips , and at least one thermal conduction portion that is in thermal contact with said first dielectric substrate and/or said second dielectric substrate.2. Electronic power module according to claim 1 , wherein said common intermediate ...

Compact semiconductor package and related methods

A method of forming a semiconductor package includes providing a substrate having one or more conductive elements disposed therein. Each conductive element extends from a first surface of the substrate toward a second surface of the substrate extending beyond the second surface. The second surface comprises one or more substrate regions not occupied by a conductive element. A first die is attached within a substrate region, and the first die is coupled to at least one of the conductive elements. The first die may be coupled to at least one of the conductive elements by a wire bond connection. Alternatively, an RDL is formed over the second surface, and the first die is coupled to at least one conductive element through the RDL. A second die may be attached to an outer surface of the RDL, and the second die is electrically coupled to the first die through the RDL.

Semiconductor Package

A semiconductor package (″), the package (″) comprising a first substrate () comprising at a front cavity side (′) a plurality of cavities (′), each of the cavities (′) having a bottom wall () and side walls (), and having a conductive path () forming an electric contact surface () located at the inner side of the bottom wall () of the cavity (′), a plurality of semiconductor elements (), each of the semiconductor elements () comprising a first electric contact surface () on a first side () and a second electric contact surface () on a second side () opposite to the first side (), wherein at least one of the semiconductor elements () is placed within a corresponding cavity (′) at the front cavity side (′) of the first substrate (), wherein the first electric contact () of the semiconductor element () and the electric contact surface () at the inner side of the bottom wall () of the corresponding cavity (′) are electrically conductive bonded in a material-locking manner, and a second substrate (), the second substrate () being attached with a connection side () to the front cavity side (′) of the first substrate () thereby encapsulating the semiconductor elements () located within the corresponding cavities (′) at the front cavity side (′) of the first substrate (). 1. A semiconductor package , the package comprising:a first substrate comprising, at a front cavity side, a plurality of cavities, each of the cavities having a bottom wall and side walls, and having a conductive path forming an electric contact surface located at the inner side of the bottom wall of the cavity,a plurality of semiconductor elements, each of the semiconductor elements comprising a first electric contact surface on a first side and a second electric contact surface on a second side opposite to the first side, wherein at least one of the semiconductor elements is placed within a corresponding cavity at the front cavity side of the first substrate, wherein the first electric contact of the ...

Singulation and Bonding Methods and Structures Formed Thereby

Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure.

MICROWAVE SWITCH AND METHOD OF MANUFACTURING MICROWAVE SWITCH

Provided is a microwave switch including at least one semiconductor device connected to a transmission line and grounded in parallel, and at least one inductor connected in series to the transmission line. When the semiconductor device is shorted, the inductor may perform impedance matching through an interaction with the semiconductor device. 1. A microwave switch comprising:at least one semiconductor device connected to a transmission line, and grounded in parallel; andat least one inductor connected in series to the transmission line,wherein, when the semiconductor device is shorted,the inductor performs impedance matching through an interaction with the semiconductor device.2. The microwave switch of claim 1 , wherein the semiconductor device grounds a signal input into the transmission line to restrict an output of the input signal claim 1 , in response to the short.3. The microwave switch of claim 1 , wherein the semiconductor device corresponds to a field effect transistor (FET).4. The microwave switch of claim 1 , wherein claim 1 , when a plurality of semiconductor devices and a plurality of inductors are provided claim 1 , the semiconductor devices and the inductors are disposed alternately.5. The microwave switch of claim 4 , wherein the plurality of semiconductor devices is aligned above or below the transmission line.6. The microwave switch of claim 4 , wherein the plurality of semiconductor devices is aligned in pairs to face each other above and below the transmission line.7. A method of manufacturing a microwave switch claim 4 , the method comprising:connecting at least one semiconductor device to a transmission line and grounding the at least one semiconductor device in parallel;connecting at least one inductor in series to the transmission line; andperforming impedance matching between the inductor and the semiconductor device when the semiconductor device is shorted.8. The method of claim 7 , further comprising:grounding, by the semiconductor ...

ELECTRONIC MODULE

An electronic module has a first substrate , an electronic element provided on one side of the first substrate , a second substrate provided on one side of the electronic element and a positioning part extending from the first substrate to one side and abutting a circumferential part of the second substrate , or extending from the second substrate to the other side and abutting against a circumferential part of the first substrate 1. An electronic module comprising:a first substrate;an electronic element provided on one side of the first substrate;a second substrate provided on one side of the electronic element; anda positioning part extending from the first substrate to one side and abutting a circumferential part of the second substrate, or extending from the second substrate to the other side and abutting against a circumferential part of the first substrate, whereinthe positioning part is formed of a lead frame, andthe positioning part has a lead frame proximal end part extending in a surface direction, and a lead frame extension part provided on the lead frame proximal end part via a lead frame bent part and extending to one side or the other side.2. The electronic module according to claim 1 , whereinthe positioning part has a protrusion part protruding inwardly,when the positioning part extends from the first substrate to one side and abuts the circumferential part of the second substrate, the protrusion part abuts a surface of the other side of the second substrate, andwhen the positioning part extends from the second substrate to the other side and abuts against the circumferential part of the first substrate, the protrusion part abuts a surface of one side of the first substrate.3. The electronic module claim 2 , according to claim 2 , further comprisinga first conductive layer provided on one side of the first substrate; anda second conductive layer provided on the other side of the second substrate, and whereinwhen the positioning part extends from the ...

Semiconductor package

A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE

A semiconductor device includes a first vertical field effect transistor (VFET) formed on a substrate, and including a first fin and a first gate formed on the first fin, a second VFET formed on the substrate and connected to the first VFET, and including a second fin and a second gate formed on the second fin, and a third VFET formed on the substrate and including a third fin, the first gate being formed on the third fin. 1. A semiconductor device comprising:a first vertical field effect transistor (VFET) formed on a substrate, and comprising a first fin and a first gate formed on the first fin;a second VFET formed on the substrate and connected to the first VFET, and comprising a second fin and a second gate formed on the second fin; anda third VFET formed on the substrate and comprising a third fin, the first gate being formed on the third fin.2. The semiconductor device of claim 1 , wherein the first and second gates are formed on the third fin.3. The semiconductor device of claim 2 , further comprising:a fourth VFET formed on the substrate and connected to the third VFET, and comprising the semiconductor fin as a fourth fin, the first and second gates being formed on the fourth fin.4. The semiconductor device of claim 1 , wherein the second VFET is connected in parallel to the first VFET claim 1 , and the fourth VFET is connected in series to the third VFET.5. The semiconductor device of claim 3 , wherein the first and second VFETs comprise first and second p-type VFETs claim 3 , respectively claim 3 , and the third and fourth VFETs comprise first and second n-type VFETs claim 3 , respectively claim 3 , and the semiconductor device comprises a complementary metal oxide semiconductor (CMOS) NAND device.6. The semiconductor device of claim 5 , wherein the first and second VFETs are formed on an p-type substrate claim 5 , and the third and fourth VFETs are formed on a n-type substrate claim 5 , and [{'sub': 'DD', 'a Vcontact formed on the p-type substrate; and'}, ...

Semiconductor package and method of manufacturing the same

A semiconductor package includes a substrate, a plurality of semiconductor devices stacked on the substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the substrate and the plurality of semiconductor devices, and molding resin surrounding the plurality of semiconductor devices. At least one of the underfill fillets is exposed from side surfaces of the molding resin.

POWER MODULE

The present disclosure provides a power module including a substrate, an electronic element provided on the substrate, and a cooling fin portion provided on one surface of the substrate to form a flow path portion through which cooling water flows. The cooling fin portion is formed asymmetrically so that amounts of heat transferred by the cooling water acting on the electronic element are different. 1. A power module comprising:a substrate;an electronic element on the substrate; anda cooling fin portion on one surface of the substrate forming a flow path portion through which cooling water flows,wherein the flow path portion is configured asymmetrically on one surface of the substrate, andwherein heat transferred by the cooling water acting on the electronic element is different depending on each arrangement of the electronic element.2. The power module of claim 1 , wherein the cooling fin portion is configured such that sizes of areas for heat dissipation regions on one surface of the substrate facing the flow path portion are different from each other according to each arrangement of the electronic element.3. The power module of claim 1 , wherein the cooling fin portion is configured such that volumes of the flow path portion are different from each other according to each arrangement of the electronic element.4. The power module of claim 1 , wherein the flow path portion further comprises:a first flow path formed on a first region of the substrate and at least partially overlaps the electronic element; anda second flow path formed on a second region of the substrate,wherein an amount of heat transferred by the cooling water acting on the electronic element in the second flow path is smaller than that of the first flow path.5. The power module of claim 4 , wherein the cooling fin portion further comprises:a first cooling fin disposed on the first region and forming the first flow path; anda second cooling fin, spaced apart from the first cooling fin, disposed on ...

ELECTRONIC MODULE

An electronic module has a first substrate , a first electronic element , a second electronic element , a second substrate , a first terminal part provided on a side of the first substrate and a second terminal part provided on a side of the second substrate . The first terminal part has a first surface direction extending part and a first normal direction extending part extending toward one side or the other side. The second terminal part has a second surface direction extending part and a second normal direction extending part extending toward one side or the other side. The second surface direction extending part is provided on one side of the first surface direction extending part , and the first surface direction extending part and the second surface direction extending part overlap one another in a surface direction. 1. An electronic module comprising:a first substrate;a first electronic element provided on one side of the first substrate;a second electronic element provided on one side of the first electronic element;a second substrate provided on one side of the second electronic element;a first terminal part provided on a side of the first substrate and electrically connected to the first electronic element; anda second terminal part provided on a side of the second substrate and electrically connected to the second electronic element;wherein the first terminal part has a first terminal base end part, first surface direction extending part that extends along a surface direction of the first substrate, and a first normal direction extending part that is provided at an end part of the first surface direction extending part and extends toward one side or the other side,the second terminal part has a second terminal base end part, a second surface direction extending part that extends along a surface direction of the second substrate, and a second normal direction extending part that is provided at an end part of the second surface direction extending part and ...

Wafer to Wafer Bonding Process and Structures

Bonded structures and method of forming the same are provided. A conductive layer is formed on a first surface of a bonded structure, the bonded structure including a first substrate bonded to a second substrate, the first surface of the bonded structure being an exposed surface of the first substrate. A patterned mask having first openings and second openings is formed on the conductive layer, the first openings and the second openings exposing portions of the conductive layer. First portions of first bonding connectors are formed in the first openings and first portions of second bonding connectors are formed in the second openings. The conductive layer is patterned to form second portions of the first bonding connectors and second portions of the second bonding connectors. The bonded structure is bonded to a third substrate using the first bonding connectors and the second bonding connectors.

Semiconductor module

A semiconductor module includes: a first substrate having a first insulating substrate and a first conductor layer; a power device part having a first electrode, a second electrode and a gate electrode; a second substrate having a second insulating substrate and a second conductor layer, wherein the second conductor layer has a bonding portion and a surrounding wall portion formed at a position which surrounds the bonding portion as viewed in a plan view; an inner resin portion; a control IC; and an outer resin portion, wherein the power device part is disposed such that the gate electrode is positioned outside a region defined by the surrounding wall portion as viewed in a plan view, and the gate electrode is electrically connected to an output terminal of the control IC through a connecting member.

SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF

A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure. 120-. (canceled)21. A semiconductor device comprising: a top FSRDS side;', 'a bottom FSRDS side;', 'a lateral FSRDS side between the top FSRDS side and the bottom FSRDS side;', 'a first FSRDS dielectric layer; and', 'a first FSRDS conductive layer comprising a first FSRDS conductive trace;, 'a front side redistribution structure (“FSRDS”) comprisinga semiconductor die comprising a front die side and a back die side, the front die side facing toward and coupled to the top FSRDS side, the front die side comprising a conductive pad that is electrically coupled to the first FSRDS conductive layer;a stacked component interconnection structure (“SCIS”) comprising a top SCIS side and a bottom SCIS side, the bottom SCIS side coupled to the top FSRDS side and electrically coupled to the first FSRDS conductive layer, the top SCIS side extending vertically at least as high as the back die side; a top encapsulating material side;', 'a bottom encapsulating material side facing the front side redistribution structure; and', 'a lateral encapsulating material side between the top encapsulating material side and the bottom encapsulating material side; and, 'an encapsulating material on the top FSRDS side and laterally surrounding the semiconductor die, the encapsulating material comprising a top BSRDS side;', 'a bottom BSRDS side coupled to the top SCIS side;', 'a first BSRDS dielectric layer on the back die side and on the top encapsulating material side; and', 'a first BSRDS conductive layer comprising a first BSRDS conductive trace that is electrically coupled to the stacked component interconnection structure,, 'a back side redistribution structure (“BSRDS”) comprisingwherein the front side ...

Method of manufacturing semiconductor device

An improvement is achieved in the reliability of a semiconductor device by preventing a dielectric breakdown between two semiconductor chips facing each other. During the manufacturing of first and second semiconductor chips, the process of planarizing the upper surfaces of insulating films is performed. Then, the first and second semiconductor chips are stacked via an insulating sheet with the respective insulating films of the first and second semiconductor chips facing each other such that the respective coils of the first and second semiconductor chips are magnetically coupled to each other.

SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF

A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure. 120-. (canceled)21. A semiconductor device comprising:a front side redistribution structure (“FSRDS”) comprising a first FSRDS dielectric layer;a semiconductor die comprising a front die side and a back die side, the front die side coupled to a top side of the front side redistribution structure;a stacked component interconnection structure comprising a top side and a bottom side, the bottom side of the stacked component interconnection structure coupled to the top side of the front side redistribution structure, the top side of the stacked component interconnection structure extending vertically at least as high as the back die side;an encapsulating material on the top side of the front side redistribution structure and laterally surrounding the semiconductor die; and a first BSRDS dielectric layer on a top side of the encapsulating material;', 'a first BSRDS conductive via extending entirely through the first BSRDS dielectric layer and coupled to the top side of the stacked component interconnection structure;', 'a first BSRDS trace on a top side of the first BSRDS dielectric layer;', 'a second BSRDS dielectric layer on the top side of the first BSRDS dielectric layer, the second BSRDS dielectric layer covering lateral sides of first BSRDS trace and a top side of the first BSRDS trace;', 'a second BSRDS conductive via coupled to the top side of first BSRDS trace and extending vertically from the top side of the first BSRDS trace to a top side of the second BSRDS dielectric layer; and', 'a top side component connection pad coupled to the second BSRDS conductive via., 'a back side redistribution structure (“BSRDS”) comprising22. The semiconductor device of claim 21 , wherein the first ...

SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME

The present disclosure relates to a semiconductor module, especially a power semiconductor module, in which the heat dissipation is improved and the power density is increased. The semiconductor module may include at least two electrically insulating substrates, each having a first main surface and a second main surface opposite to the first main surface. On the first main surface of each of the substrates, at least one semiconductor device is mounted. An external terminal is connected to the first main surface of at least one of the substrates. The substrates are arranged opposite to each other so that their first main surfaces are facing each other. 1. A semiconductor module , comprising:at least two electrically insulating substrates, each having a first main surface and a second main surface opposite to the first main surface;for each of the substrates, at least one semiconductor device mounted on the first main surface of the corresponding substrate; andan external terminal connected to the first main surface of at least one of the substrates;wherein the substrates are arranged opposite to each other so that respective first main surfaces of the substrates are facing each other.2. The semiconductor module according to claim 1 , further comprising:an encapsulation, wherein the second main surfaces of each of the substrates are exposed on opposite sides of the encapsulation.3. The semiconductor module according to claim 1 , wherein the substrates are thermally conductive.4. The semiconductor module according to claim 1 , wherein the at least one semiconductor device is a power semiconductor device.5. The semiconductor module according to claim 1 , wherein a heat sink is mounted to at least one of the second main surfaces of the substrates.6. The semiconductor module according to claim 1 , whereinthe external terminal comprises at least two external leads, and wherein:all the external leads protrude in a plane from two opposite sides of the semiconductor module, ...

3D SEMICONDUCTOR DEVICE AND STRUCTURE

A 3D semiconductor device, the device including: a first die including a first transistors layer and a first interconnection layer; and a second die overlaying the first die, the second die including a second transistors layer and a second interconnection layer, where the second die thickness is less than 2 microns, and where the first die is substantially larger than the second die. 1. A 3D semiconductor device , the device comprising:a first die comprising a first transistors layer and a first interconnection layer; and wherein said second die thickness is less than 2 microns, and', 'wherein said first die is substantially larger than said second die., 'a second die overlaying said first die, said second die comprising a second transistors layer and a second interconnection layer,'}3. The device according to claim 1 , further comprising: 'wherein said isolative layer has a thermal conductivity less than 0.5 W/m-K.', 'a thermal isolative layer disposed between said first die and said second die,'}4. The device according claim 1 ,wherein said second die is a memory die.5. The device according claim 1 ,wherein said second die comprises alignment marks.6. The device according claim 1 ,wherein said first die is embedded as part of a wafer having a diameter larger than 150 mm.7. The device according claim 1 ,wherein said second die is a pre-tested die.8. A 3D semiconductor device claim 1 , the device comprising:a first strata comprising a first transistors layer and a first interconnection layer, and wherein said first strata is a wafer having a diameter larger than 150 mm, and', 'wherein said second strata is an isolated die having a size smaller than 30 mm by 30 mm, and', 'wherein said second strata has a thickness less than 2 microns., 'a second strata overlaying said first strata, said second strata comprising a second transistors layer and a second interconnection layer,'}10. The device according to claim 8 , further comprising: 'wherein said isolative layer has a ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device has a first board () having a first electrically conducting layer () and a first electronic element () that is provided on the first electrically conducting layer (); and an intermediate layer () being provided on the first board (), and having a plurality of connectors and a resin board section, in which the plurality of connectors are fixed. The connector is exposed from the resin board section on the first board () side, and connected with the first electrically conducting layer () or the first electronic element (). 1. A semiconductor device comprising:a first board having a first electrically conducting layer and a first electronic element that is provided on the first electrically conducting layer; andan intermediate layer being provided on the first board, and having a plurality of connectors and a resin board section, in which the plurality of connectors are fixed;wherein the connector is exposed from the resin board section on the first board side, and connected with the first electrically conducting layer or the first electronic element,wherein the intermediate layer has a first intermediate layer and a second intermediate layer, which is provided on the first intermediate layer,wherein the first intermediate layer has a first connector and a first resin board section, in which the first connector is fixed,wherein the second intermediate layer has a second connector and a second resin board section, in which the second connector is fixed, andwherein the first connector protrudes from the first resin board section to the side on which the second intermediate layer is provided, and the second resin board section is provided with a second insertion section, into which the first connector, which protrudes from the first resin board section, is inserted, or wherein the second connector protrudes from the second resin board section to the side on which the first intermediate layer is provided, and the first resin board section is provided ...

Semiconductor device and method for manufacturing semiconductor device

A semiconductor device has a first board ( 10 ); and an intermediate layer ( 20 ) being provided on the first board ( 10 ) and having a plurality of connectors ( 31 ), ( 41 ). The first board ( 10 ) has a positioning section ( 5 ) that positions the intermediate layer ( 20 ). The intermediate layer ( 10 ) is provided with a positioning insertion section ( 37 ), ( 47 ), into which the positioning section ( 5 ) is inserted.

SEMICONDUCTOR MODULE AND STACK ARRANGEMENT OF SEMICONDUCTOR MODULES

A semiconductor module and a stack arrangement of semiconductor modules is proposed. The semiconductor module comprises an insulated gate bipolar transistor, a wide band-gap switch, a base plate, and a press device. The insulated gate bipolar transistor and the wide band-gap switch are connected in parallel and are each mounted with a first planar terminal to a side of the base plate. Further, a second planar terminal of the insulated gate bipolar transistor and a second planar terminal of the wind band-gap switch are connected with an electrically conductive connection element, and the press device is arranged on the second planar terminal of the insulated gate bipolar transistor. Hence, when arranging the semiconductor modules in a stack arrangement, any press force is primarily applied to the insulated gate bipolar transistors of the semiconductor modules. 1. A semiconductor module , comprising:an insulated gate bipolar transistor;a wide band-gap switch;a base plate; anda press device,wherein the insulated gate bipolar transistor comprises a first planar terminal and a second planar terminal,wherein the wide band-gap switch comprises a first planar terminal and a second planar terminal,wherein the insulated gate bipolar transistor and the wide band-gap switch are connected in parallel, whereby for the parallel connection the first planar terminal of the insulated gate bipolar transistor and the first planar terminal of the wide band-gap switch are mounted to the same side of the base plate and the second planar terminal of the insulated gate bipolar transistor and the second planar terminal of the wide band-gap switch are connected with an electrically conductive connection element,wherein the press device is arranged on the second planar terminal of the insulated gate bipolar transistor, andwherein the semiconductor module further comprising at least one gate pad for connecting a gate of the insulated gate bipolar transistor and a gate of the wide band-gap ...

SEMICONDUCTOR DEVICE

A semiconductor device includes first and second metal plates which are disposed to face each other, a semiconductor chip, a first insulator block, and a package. The first semiconductor chip has first and second electrodes exposed on first and second surface respectively. The first and second electrodes are connected to the first and second metal plates, respectively. The first insulator block is adjacent to the first semiconductor chip, and has a first surface in contact with the first metal plate, and a second surface. The second surface is on the opposite side of the first insulator block from the first surface and is in contact with the second metal plate. The package is in contact with a surface to which the first semiconductor chip of the first metal plate is connected and a surface to which the first semiconductor chip of the second metal plate is connected. 1. A semiconductor device comprising:a first metal plate and a second metal plate disposed to face each other;a first semiconductor chip having a first electrode exposed on a first surface and a second electrode exposed on a second surface, the first electrode facing the first metal plate and being connected to the first metal plate by a solder, and the second electrode facing the second metal plate and being connected to the second metal plate by the solder; a first surface in contact with the first metal plate, and', 'a second surface which is on an opposite side of the first insulator block from the first surface and is in contact with the second metal plate; and, 'a first insulator block adjacent to the first semiconductor chip, the first insulator block having'}a package configured to accommodate the first semiconductor chip and be in contact with a surface of the first metal plate to which the first semiconductor chip is connected and a surface of the second metal plate to which the first semiconductor chip is connected.2. The semiconductor device according to claim 1 , wherein the first insulator ...

SEMICONDUCTOR DEVICE AND METHOD OF INTEGRATING POWER MODULE WITH INTERPOSER AND OPPOSING SUBSTRATES

A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly. 1. A semiconductor device , comprising:a first substrate including a first conductive layer formed over a first surface of the first substrate and a second conductive layer formed over a second surface of the first substrate opposite the first surface of the first substrate, wherein no portion of the first conductive layer is electrically connected to the second conductive layer;a second substrate; anda first semiconductor die disposed between the first substrate and second substrate.2. The semiconductor device of claim 1 , wherein the second substrate includes a third conductive layer formed over a first surface of the second substrate and a fourth conductive layer formed over a second surface of the second substrate opposite the first surface of the second substrate.3. The semiconductor device of claim 1 , wherein the first semiconductor die includes a power semiconductor device.4. The semiconductor device of claim 1 , further including:an interposer including a vertical interconnect structure disposed between the first substrate ...

Semiconductor device

A semiconductor device includes: a first switching element that is provided on a high side; a first diode element that is connected in parallel to the first switching element; a second switching element that is provide on a low side and connected in series to the first switching element; and a second diode element that is connected in parallel to the second switching element, wherein the first switching element and one of the first diode element and the second diode element are stacked adjacently to each other in a vertical direction of respective electrode surfaces thereof via a conductive electrode, the second switching element and the other of the first diode element and the second diode element that is different from the diode element adjacent to the first switching element are stacked adjacently to each other in a vertical direction of respective electrode surfaces thereof via a conductive electrode, and the first switching element and the second switching element are not adjacent in a vertical direction of respective electrode surfaces thereof.

SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF

A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure. 120-. (canceled)21. A semiconductor device comprising: a first dielectric layer;', a first trace top side that is at least partially covered by the first dielectric layer;', 'a first trace bottom side that is exposed at a bottom side of the first dielectric layer; and', 'a first trace lateral side that is covered by the first dielectric layer; and, 'a first conductive trace embedded in the first dielectric layer and comprising, a first via top side that is exposed at a top side of the first dielectric layer;', 'a first via bottom side that is directly coupled to the first trace top side; and', 'a first via lateral side that is covered by the first dielectric layer;, 'a first conductive via embedded in the first dielectric layer and comprising], 'a first redistribution structure comprising a second dielectric layer coupled under the bottom side of the first dielectric layer;', 'a third dielectric layer coupled under a bottom side of the second dielectric layer;', 'a second conductive trace embedded in the third dielectric layer; and', the second conductive trace extends along the bottom side of the second dielectric layer;', 'the first conductive trace extends along a top side of the second dielectric layer; and', 'the second conducive via couples the first conductive trace to the second conductive trace;, 'a second conductive via that extends through the second dielectric layer, wherein], 'a second redistribution structure on a bottom side of the first redistribution structure and comprisinga semiconductor die attached to a top side of the first redistribution structure; anda mold material covering at least a portion of the top side of the first redistribution structure and a lateral side ...

SEMICONDUCTOR DEVICE AND METHOD OF INTEGRATING POWER MODULE WITH INTERPOSER AND OPPOSING SUBSTRATES

A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly. 1. A semiconductor device , comprising:a substrate;a plurality of first interconnect pads formed over a surface of the substrate; anda plurality of second interconnect pads formed over the surface of the substrate, wherein the second interconnect pads have an area different from an area of the first interconnect pads, and the first interconnect pads and second interconnect pads are electrically common and arranged in an identifiable pattern for alignment.2. The semiconductor device of claim 1 , wherein the identifiable pattern includes rows of the first interconnect pads.3. The semiconductor device of claim 1 , wherein the identifiable pattern includes alternating offset ones of the first interconnect pads.4. The semiconductor device of claim 1 , wherein the identifiable pattern includes the first interconnect pads interposed between the second interconnect pads.5. The semiconductor device of claim 1 , further including a transistor formed within the substrate.6. The semiconductor device of claim 1 , further includes a plurality of ...

Stacked Half-Bridge Package

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal. 140-. (canceled)41. A method for manufacturing a stacked half-bridge package , said method comprising:providing a control transistor having a control drain, a control source, and a control gate;providing a sync transistor having a sync drain, a sync source, and a sync gate;stacking said control and sync transistors on opposite sides of a common leadframe, said common leadframe serving as an output terminal by coupling said control source with said sync drain.42. The method of claim 41 , wherein said common leadframe comprises a web portion and a leg portion.43. The method of claim 41 , wherein respective bottom surfaces of said sync transistor and a leg portion of said common leadframe are substantially flush with one another.44. The method of claim 41 , further comprising connecting said control drain to a control drain leadframe by a conductive clip.45. The method of claim 41 , wherein said stacked half-bridge package further comprises a conductive clip including a web portion that is coupled to said control drain and including a leg portion that is coupled to a control drain leadframe.46. The method of claim 41 , further comprising coupling a conductive clip to said control drain at a topside of said stacked ...

ELECTRONIC DEVICE, METHOD OF MANUFACTURING ELECTRONIC DEVICE, AND ELECTRONIC APPARATUS

An electronic device includes: a first layer that includes first electronic components in a group and has a first through space between adjacent ones of the first electronic components; and a second layer that is stacked over the first layer and includes second electronic components which are coupled to the first electronic components and a second through space between adjacent ones of the second electronic components, the second through space being partially overlapping with the first through space. 1. An electronic device comprising:a first layer that includes first electronic components in a group and has a first through space between adjacent ones of the first electronic components; anda second layer that is stacked over the first layer and includes second electronic components which are coupled to the first electronic components and a second through space between adjacent ones of the second electronic components, the second through space being partially overlapping with the first through space.2. The electronic device according to claim 1 , wherein one of the adjacent ones of the second electronic components is stacked over one end portions claim 1 , which are opposed with each other claim 1 , of the adjacent ones of the first electronic components claim 1 , and the other of the adjacent second electronic components is separated from the one of the adjacent second electronic components and stacked over the other end portions claim 1 , which are opposed with each other claim 1 , of the adjacent first electronic components.3. The electronic device according to claim 1 , wherein a semiconductor element is used as each of the first electronic components and each of the second electronic components.4. The electronic device according to claim 1 , wherein a semiconductor device including a semiconductor element and a circuit board on which the semiconductor element is mounted is used as each of the first electronic components and each of the second electronic ...

Semiconductor package and manufacturing method thereof

A semiconductor package and a manufacturing method are provided. The semiconductor package includes a semiconductor die, an encapsulant and a through encapsulant via. The semiconductor die includes a semiconductor substrate, an interconnection layer and a through semiconductor via. The semiconductor substrate has an active surface and a back surface opposite to the active surface. The interconnection layer is disposed over the active surface of the semiconductor substrate. The through semiconductor via penetrates through the semiconductor substrate from the back surface of the semiconductor substrate to the active surface of the semiconductor substrate. The semiconductor die is encapsulated by the encapsulant. The through encapsulant via penetrates through the encapsulant.

Pad Design For Reliability Enhancement in Packages

A package includes a corner, a device die, a molding material molding the device die therein, and a plurality of bonding features. The plurality of bonding features includes a corner bonding feature at the corner, wherein the corner bonding feature is elongated. The plurality of bonding features further includes an additional bonding feature, which is non-elongated. 1 a device die;', 'a molding material molding the device die therein; and', 'a plurality of through-vias penetrating through the molding material; and, 'etching a first dielectric layer of a first package to expose surfaces of a first bonding feature and a second bonding feature in the first package, wherein the first bonding feature is elongated, and the second bonding feature is non-elongated, and the first package comprisesforming a first solder region and a second solder region contacting the surfaces of the first bonding feature and the second bonding feature.. A method comprising: This application is a divisional of U.S. patent application Ser. No. 15/817,704, entitled “Pad Design for Reliability Enhancement in Packages,” filed on Nov. 20, 2017, which is a continuation of U.S. patent application Ser. No. 14/865,832, entitled “Pad Design for Reliability Enhancement in Packages,” and filed Sep. 25, 2015, now U.S. Pat. No. 9,824,990 issued Nov. 21, 2017, which is a continuation-in-part application of the following commonly-assigned U.S. patent application Ser. No. 14/613,997, filed Feb. 4, 2015, and entitled “Pad Design for Reliability Enhancement in Packages,” now U.S. Pat. No. 9,881,857 issued Jan. 30, 2018, which further claims the benefit of the following U.S. Provisional Application No. 62/011,432, filed Jun. 12, 2014, and entitled “Integrated Circuit Package Pad and Method of Forming Same,” which applications are hereby incorporated herein by reference.In the packaging of integrated circuits, there are various types of packaging methods and structures. For example, in a conventional Package-on- ...

ELECTRONIC MODULE

An electronic module has an insulating substrate , a conductor layer provided on the insulating substrate , an electronic element provided on the conductor layer , and a heat radiation layer provided on the insulating substrate in an opposite side of the electronic element . The heat radiation layer has a plurality of heat radiation layer patterns divided in a plane direction. 1. An electronic module comprising:an insulating substrate;a conductor layer provided on the insulating substrate;an electronic element provided on the conductor layer; anda heat radiation layer provided on the insulating substrate in an opposite side of the electronic element,wherein the conductor layer has a separation part separated from the insulating substrate, andwherein the electronic element is provided on the separation part.2. The electronic module according to claim 1 ,wherein the electronic element includes a switching element.3. The electronic module according to claim 1 ,wherein the heat radiation layer has a plurality of heat radiation layer patterns divided in a plane direction andwherein the heat radiation layer patterns include an entire area where the electronic element is disposed when viewed from a side of the heat radiation layer patterns.4. The electronic module according to claim 3 ,wherein at least a part of the heat radiation layer patterns entirely covers a plurality of the electronic elements when viewed from the side of the heat radiation layer patterns.5. The electronic module according to claim 1 ,wherein an insulating substrate has a first insulating substrate and a second insulating substrate,wherein the electronic element has a first electronic element and a second electronic element,wherein the heat radiation layer has a first heat radiation layer and a second heat radiation layer,wherein the first electronic element is provided on one side of the first insulating substrate,wherein the first heat radiation layer is provided on the other side of the first ...

Power semiconductor module

A power semiconductor module may include a first plate, a second plate configured to include first and second device receiving portions thereinside, and coupled to one side of the first plate, first and second power semiconductor devices arranged in the first and second device receiving portions, first and second input bus bars coupled to an outside of the second plate, a third plate configured to include third and fourth device receiving portions thereinside, and coupled to the other side of the first plate, third and fourth power semiconductor devices arranged in the third and fourth device receiving portions, and third and fourth input bus bars coupled to an outside of the third plate.

Power Semiconductor Package Having a Parallel Plate Waveguide

A power semiconductor package includes a first group of semiconductor dies attached to a first side of a substrate and evenly distributed over a width of the substrate and a second group of semiconductor dies attached to the first side of the substrate and evenly distributed over the substrate width. Each die in the first and second groups has all terminals at one side which is attached to the first side of the substrate and an insulated or isolated face at a side opposite the side with the terminals. A first intermediary metal layer of the substrate forms a first DC terminal. A second intermediary metal layer of the substrate forms a second DC terminal. These intermediary metal layers are insulated from one another and form a parallel plate waveguide. Additional power semiconductor package embodiments are described. 1. A power semiconductor package , comprising:a substrate comprising a lowermost metal layer, an uppermost metal layer, and at least a first insulating layer separating the lowermost metal layer from the uppermost metal layer, the uppermost metal layer being patterned into a plurality of strips which extend in parallel over a width of the substrate;a first group of semiconductor dies attached to a first one of the strips of the uppermost metal layer and evenly distributed over the width of the first strip, each semiconductor die in the first group having an insulated or isolated face attached to the first strip;a second group of semiconductor dies attached to the first strip of the uppermost metal layer and evenly distributed over the width of the first strip, each semiconductor die in the second group having an insulated or isolated face attached to the first strip;a first DC terminal attached to the first strip of the uppermost metal layer and evenly distributed over the width of the first strip; anda second DC terminal attached to a second one of the strips of the uppermost metal layer and evenly distributed over the width of the second strip,wherein ...

Semiconductor package for multiphase circuitry device

In some examples, a device includes a power supply element and a reference voltage element, wherein the reference voltage element is electrically isolated from the power supply element. The device further includes a high-side semiconductor die including at least two high-side transistors, wherein each high-side transistor of the at least two high-side transistors is electrically connected to the power supply element. The device also includes a low-side semiconductor die including at least two low-side transistors, wherein each low-side transistor of the at least two low-side transistors is electrically connected to the reference voltage element. The device includes at least two switching elements, wherein each switching element of the at least two switching elements is electrically connected to a respective high-side transistor of the at least two high-side transistors and to a respective low-side transistor of the at least two low-side transistors.

EMBEDDED POWER MODULE

A transport system in a structure includes a car and a plurality of motor modules. The car is constructed and arranged to move along a lane generally defined at least in-part by the structure. The plurality of motor modules are distributed along the lane and are constructed and arranged to propel the car. Each one of the pluralities of motor modules include an embedded power module. 1. A transport system in a structure comprising:a car constructed and arranged to move along a lane generally defined at least in-part by the structure; anda plurality of motor modules distributed along the lane and constructed and arranged to propel the car, each one of the plurality of motor modules including an embedded power module.2. The transport system set forth in claim 1 , wherein the embedded power module includes a substrate having opposite first and second surfaces; a first semiconductor device embedded in the substrate and spaced between the first and second surfaces; a second semiconductor device embedded in the substrate claim 1 , spaced between the first and second surfaces claim 1 , and spaced from the first semiconductor device; a first gate located on the first surface; a second gate located on the second surface; a first via electrically engaged to the first gate and the second semiconductor device; and a second via electrically engaged to the second gate and the first semiconductor device.3. The transport system set forth in claim 2 , wherein the embedded power module includes a first collector/emitter pad located on the second surface and spaced from the second gate;at least one third via electrically engaged to the first semiconductor device and the first collector/emitter pad; and at least on fourth via electrically engaged to the second semiconductor device and the first collector/emitter pad.4. The transport system set forth in claim 3 , wherein the embedded power module includes a second collector/emitter pad located on the first surface; a third collector/ ...

PACKAGED INTEGRATED CIRCUIT DEVICES WITH THROUGH-BODY CONDUCTIVE VIAS, AND METHODS OF MAKING SAME

A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material. 1. A method , comprising:forming a body of encapsulant material around at least a portion of at least one integrated circuit die;forming at least one conductive via that extends through the body of encapsulant material; andconductively coupling the at least one conductive via to the at least one integrated circuit die.2. The method of claim 1 , further comprising performing a singulating process to define a plurality of individual embedded die claim 1 , each of which are comprised of a plurality of integrated circuit die.3. The method of claim 2 , further comprising:positioning a plurality of the individual embedded die adjacent one another; andconductively coupling the conductive via on a first of the individual embedded die to the conductive via on a second of the individual embedded die.4. The method of claim 3 , wherein the plurality of individual embedded die are positioned such that a first surface of a first individual embedded die faces a back side of an adjacent individual embedded die.5. The method of claim 3 , wherein conductively coupling the conductive vias on the first and second individual embedded die comprises forming a conductive structure between the first and second individual embedded die.6. The method of claim 5 , further comprising stacking the second individual embedded die above the first individual embedded die.7. A method claim 5 , comprising:positioning a first individual embedded die adjacent a second individual embedded die, each of the first and second individual embedded die comprising a body of encapsulant material; andforming at least one conductive via that extends through the body of encapsulant material of both of the first and second individual embedded die.8. The method of claim 7 , further ...

ULTRA SMALL MOLDED MODULE INTEGRATED WITH DIE BY MODULE-ON-WAFER ASSEMBLY

Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components. 1. A method of forming a molded module , comprising:mounting a plurality of components on a temporary adhesive formed over a carrier substrate, wherein the components each have terminals that are in contact with the temporary adhesive;encapsulating the plurality of components with a mold layer; andremoving the temporary adhesive and the carrier substrate from the mold layer, wherein the terminals are exposed and are substantially coplanar with a first surface of the mold layer.2. The method of claim 1 , further comprising:singulating the mold layer to form a plurality of molded modules.3. The method of claim 2 , further comprising:mounting at least one of the molded modules to a die, wherein the die includes a redistribution layer.4. The method of claim 1 , further comprising:forming one or more via openings in the mold layer; anddisposing a conductive material in the one or more via openings to form through mold vias.5. The method of claim 4 , wherein the via openings are formed with a laser drilling process.6. The method of claim 1 , further comprising:mounting one or more conductive pins ...