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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 820. Отображено 100.
26-09-2013 дата публикации

Methods, structures and devices for increasing memory density

Номер: US20130248800A1
Автор: John K. Zahurak, Sanh D. Tang
Принадлежит: Micron Technology Inc

Non-volatile memory devices comprising a memory string including a plurality of vertically superimposed diodes. Each of the diodes may be arranged at different locations along a length of the electrode and may be spaced apart from adjacent diodes by a dielectric material. The electrode may electrically couple the diodes of the memory strings to one another and to another memory device, such as, a MOSFET device. Methods of forming the non-volatile memory devices as well as intermediate structures are also disclosed.

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Номер записи: 1
10-10-2013 дата публикации

SIOX-BASED NONVOLATILE MEMORY ARCHITECTURE

Номер: US20130264536A1
Автор: Fowler Burt, Mortland Glenn, Tour James M., Yao Jun
Принадлежит:

Various embodiments of the present invention pertain to memresistor cells that comprise: (1) a substrate; (2) an electrical switch associated with the substrate; (3) an insulating layer; and (3) a resistive memory material. The resistive memory material is selected from the group consisting of SiO, SiOH, SiON, SiONH, SiOCz, SiOCH, and combinations thereof, wherein each of x, y and z are equal or greater than 1 or equal or less than 2. Additional embodiments of the present invention pertain to memresistor arrays that comprise: (1) a plurality of bit lines; (2) a plurality of word lines orthogonal to the bit lines; and (3) a plurality of said memresistor cells positioned between the word lines and the bit lines. Further embodiments of the present invention provide methods of making said memresistor cells and arrays. 1. A memresistor cell comprising:a substrate;an electrical switch associated with the substrate;an insulating layer; and {'sub': x', 'x', 'x', 'y', 'x', 'y', 'x', 'z', 'x', 'z, 'wherein the resistive memory material is selected from the group consisting of SiO, SiOH, SiON, SiONH, SiOC, SiOCH, and combinations thereof, wherein each of x, y and z are equal or greater than 1 or equal or less than 2.'}, 'a resistive memory material,'}2. The memresistor cell of claim 1 , wherein the memresistor cell has two terminals.3. The memresistor cell of claim 1 , wherein the substrate is selected from the group consisting of silicon claim 1 , silicon dioxide claim 1 , aluminum oxide claim 1 , sapphire claim 1 , germanium claim 1 , gallium arsenide (GaAs) claim 1 , alloys of silicon and germanium claim 1 , indium phosphide (InP) claim 1 , and combinations thereof.4. The memresistor cell of claim 1 , wherein the electrical switch is associated with two or more conductive elements.5. The memresistor cell of claim 4 , wherein the conductive elements associated with the electrical switch are selected from the group consisting of polysilicon claim 4 , n-doped polysilicon claim ...

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Номер записи: 2
17-10-2013 дата публикации

NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT, NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

Номер: US20130270510A1
Автор: Fujii Satoru, Mikawa Takumi, TSUJI Kiyotaka
Принадлежит:

A nonvolatile semiconductor memory element includes: a variable resistance element including a first electrode, a variable resistance layer, and a second electrode, and having a resistance value which changes according to a polarity of an electric pulse applied between the first electrode and the second electrode; and a current steering element which is electrically connected to the variable resistance element, allows a current to flow bidirectionally, and has a nonlinear current-voltage characteristic. The current steering element (i) has a structure in which a first current steering element electrode, a first semiconductor layer, and a second current steering element electrode are stacked in this order, and (ii) includes a second semiconductor layer which covers side surfaces of the first current steering element electrode, the first semiconductor layer, and the second current steering element electrode. 115-. (canceled)16. A nonvolatile semiconductor memory element , comprising:a variable resistance element including a first electrode, a variable resistance layer, and a second electrode, and having a resistance value which changes according to a polarity of an electric pulse applied between the first electrode and the second electrode; anda current steering element which is electrically connected to the variable resistance element, allows a current to flow bidirectionally, and has a nonlinear current-voltage characteristic,wherein the current steering element (i) has a structure in which a first current steering element electrode in a plane shape, a first semiconductor layer in a plane shape, and a second current steering element electrode in a plane shape are stacked in this order, and (ii) includes a second semiconductor layer which is provided, as seen in a direction parallel to a main surface of a substrate, on a side surface of the first semiconductor layer, on at least a portion of a side surface of the first current steering element electrode, and on at ...

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Номер записи: 3
21-11-2013 дата публикации

Nonvolatile Memory Cells and Arrays of Nonvolatile Memory Cells

Номер: US20130306933A1
Автор: Liu Zengtao T., Wells David H.
Принадлежит: MICRON TECHNOLOGY, INC.

A nonvolatile memory cell includes first and second electrodes. Programmable material and a select device are received in series between and with the first and second electrodes. Current conductive material is in series between and with the programmable material and the select device. An array of vertically stacked tiers of such nonvolatile memory cells is disclosed. Methods of forming arrays of nonvolatile memory cells are disclosed. 1. An array of vertically stacked tiers of nonvolatile memory cells , comprising:a plurality of horizontally oriented first electrode lines within individual tiers of memory cells;a plurality of horizontally oriented global second electrode lines having local vertical second electrode line extensions extending through multiple of the tiers of memory cells; and a crossing one of the horizontal first electrode lines and one of the local vertical second electrode line extensions;', 'programmable material, a select device in series with the programmable material, and current conductive material in series between and with the programmable material and the select device; the programmable material and the select device being in series with such crossing ones of the horizontal first electrode lines and local vertical second electrode line extensions; and', 'the programmable material and the select device are oriented for predominant current flow into or out of the crossing one local vertical second electrode line extension out of or into, respectively, one of the programmable material or select device in a horizontal direction, and for predominant current flow into or out of the crossing one horizontal electrode line out of or into, respectively, the other of the programmable material and select device in a vertical direction., 'individual of the memory cells comprising2. The array of wherein the first electrode lines are data/sense lines and the second electrode lines are access lines claim 1 , and the programmable material and the select ...

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Номер записи: 4
05-12-2013 дата публикации

Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same

Номер: US20130320287A1
Автор: April D. Schricker, Mark H. Clark, S. Brad Herner
Принадлежит: SanDisk 3D LLC

A method of forming a memory cell is provided that includes forming a steering element above a substrate, forming a material layer on the substrate, patterning and etching the material layer, and oxidizing the patterned and etched material layer to form a reversible resistance-switching material. Numerous other aspects are provided.

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Номер записи: 5
06-02-2014 дата публикации

Switching device having a non-linear element

Номер: US20140034898A1
Автор: Sung Hyun Jo, Wei Lu
Принадлежит: Crossbar Inc

A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.

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Номер записи: 6
07-01-2016 дата публикации

Memory Structures and Arrays, and Methods of Forming Memory Structures and Arrays

Номер: US20160005968A1
Автор: Durai Vishak Nirmal Ramaswamy, Mark S. Korber
Принадлежит: Micron Technology Inc

Some embodiments include memory structures having a diode over a memory cell. The memory cell can include programmable material between a pair of electrodes, with the programmable material containing a multivalent metal oxide directly against a high-k dielectric. The diode can include a first diode electrode directly over one of the memory cell electrodes and electrically coupled with the memory cell electrode, and can include a second diode electrode laterally outward of the first diode electrode and not directly over the memory cell. Some embodiments include memory arrays comprising the memory structures, and some embodiments include methods of making the memory structures.

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Номер записи: 7
04-01-2018 дата публикации

STRUCTURE AND METHOD FOR MEMORY CELL ARRAY

Номер: US20180006086A1
Автор: Cao Heng, Chiu Shengfen
Принадлежит:

A memory cell array structure includes memory cells arranged in m rows and n columns on a substrate, and n columns of first and second well regions with different conductivity types alternatively arranged along the column direction. Each of the memory cells includes first and second diodes. The first diode formed of a first doped region in the same column is disposed in the first well region. The second diode formed of a second doped region in the same column is disposed in the second well region. A third doped region having the conductivity type of the first well region is disposed in the first well region and is connected to the reset line of the same column. A fourth doped region having the conductivity type of the second well region is disposed in the second well region and is connected to the bit line of the same column. 1. A memory cell array structure , comprising:a semiconductor substrate;a plurality of memory cells arranged in m rows and n columns on the semiconductor substrate, m and n being positive integers, each of the memory cells including a first diode, a second diode, and a random access memory component;n columns of first well regions and n columns of second well regions spaced apart from each other in the semiconductor substrate and alternatively disposed along a column direction, the first well regions having a first conductivity type, and the second well regions having a second conductivity type different from the first conductivity type;m rows of first doped regions in the first well regions and having the second conductivity type, each one of first doped regions disposed in one of the first well regions along the column direction, one of the first doped regions and one of the first well regions disposed underneath thereof forming a first diode;m rows of second doped regions in the second well regions and having the first conductivity type, each one of second doped regions disposed in one of the second well regions along the column direction, ...

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Номер записи: 8
07-01-2021 дата публикации

System on chip (SoC) based on neural processor or microprocessor

Номер: US20210005666A1
Автор: Martínez Ángel, Mazed Mohammad A., Wiig Rex
Принадлежит:

System on chips (SoCs) based on a microprocessor or a neural processor (e.g., brain-inspired processor) electrically coupled with electronic memory devices and/or optically coupled with an optical memory device, along with embodiment(s) of a building block (an element) of the microprocessor/neural processor, the electronic memory device and the optical memory device are disclosed. It should be noted that a microprocessor can include a graphical processor. 1. A system comprising: a neural processor ,wherein the neural processor comprises memristors, wherein the memristors are arranged in three-dimension (3-D),wherein the neural processor is coupled with an optical memory device by an optical signal to electrical signal converter (OEC) device,wherein the optical signal to electrical signal converter (OEC) device is coupled with an optical device,wherein the optical device comprises(i) a first wavelength for writing,(ii) a second wavelength for erasing,(iii) a third wavelength for reading,wherein the optical memory device is activated by(i) a first wavelength for writing,(ii) a second wavelength for erasing,(iii) a third wavelength for reading,wherein the neural processor is further coupled with an electronic memory device,wherein the electronic memory device comprises a phase change material of a nanoscaled dimension, or a phase transition material of a nanoscaled dimension,wherein the nanoscaled dimension is less than 1000 nanometers in any dimension.2. The system according to claim 1 , wherein the optical signal to electrical signal converter (OEC) device comprises plasmons-polaritons.3. The system according to claim 2 , wherein the plasmons-polaritons are coupled with an interferometer.4. The system according to claim 1 , wherein the optical signal to electrical signal converter (OEC) device comprises a metalized via hole claim 1 , a light source and a photodetector.5. The system according to claim 1 , wherein the optical memory device comprises a phase change ...

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Номер записи: 9
07-01-2021 дата публикации

System on chip (Soc) based on neural processor or microprocessor

Номер: US20210005667A1
Автор: Martínez Ángel, Mazed Mohammad A., Wiig Rex
Принадлежит:

System on chips (SoCs) based on a microprocessor or a neural processor (e.g., brain-inspired processor) electrically coupled with electronic memory devices and/or optically coupled with an optical memory device, along with embodiment(s) of a building block (an element) of the microprocessor/neural processor, the electronic memory device and the optical memory device are disclosed. It should be noted that a microprocessor can include a graphical processor. Furthermore, two or more microprocessors/graphical processors/neural processors (or even a network of microprocessors/graphical processors/neural processors) can be coupled with an optical switch to mimic a (biological) cognitive system. 1. A system comprising: more than one neural processor ,wherein the one neural processor comprises memristors,wherein the one neural processor is coupled with an optical switch,wherein the one neural processor is further coupled with an optical memory device by an optical signal to electrical signal converter (OEC) device,wherein the optical signal to electrical signal converter (OEC) device is coupled with an optical device,wherein the optical device comprises(i) a first wavelength for writing,(ii) a second wavelength for erasing,(iii) a third wavelength for reading,wherein the optical memory device is activated by(i) a first wavelength for writing,(ii) a second wavelength for erasing,(iii) a third wavelength for reading,wherein the one neural processor is further coupled with an electronic memory device,wherein the electronic memory device comprises a phase change material of a nanoscaled dimension, or a phase transition material of a nanoscaled dimension,wherein the nanoscaled dimension is less than 1000 nanometers in any dimension.2. The system according to claim 1 , wherein the optical signal to electrical signal converter (OEC) device comprises plasmons-polaritons.3. The system according to claim 2 , wherein the plasmons-polaritons are coupled with an interferometer.4. The ...

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Номер записи: 10
04-01-2018 дата публикации

MEMORY CELL STRUCTURES

Номер: US20180006218A1
Автор: Sills Scott E.
Принадлежит:

The present disclosure includes memory cell structures and method of forming the same. One such memory cell includes a first electrode having sidewalls angled less than 90 degrees in relation to a bottom surface of the first electrode, a second electrode, including an electrode contact portion of the second electrode, having sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode, wherein the second electrode is over the first electrode, and a storage element between the first electrode and the electrode contact portion of the second electrode. 1. A memory cell , comprising:a first electrode having sidewalls angled less than 90 degrees in relation to a bottom surface of the first electrode;a second electrode, including an electrode contact portion of the second electrode, having sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode, wherein the second electrode is over the first electrode; anda storage element between the first electrode and the electrode contact portion of the second electrode.2. The memory cell of claim 1 , wherein an electrode contact portion of the second electrode has sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode.3. The memory cell of claim 1 , wherein the first electrode has a trapezoidal cross-sectional area and sidewalls that are selected from the group consisting of straight claim 1 , concave claim 1 , or convex.4. The memory cell of claim 3 , wherein a top surface of the trapezoidal cross-sectional area of the first electrode is an electrode contact portion of the first electrode and is in contact with the storage element.5. The memory cell of claim 1 , wherein the first electrode has a triangular cross-sectional area and sidewalls that are selected from the group consisting of straight claim 1 , concave claim 1 , or convex.6. The memory cell of claim 1 , wherein the storage element includes a resistance variable ...

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Номер записи: 11
07-01-2021 дата публикации

RESISTIVE MEMORY ARCHITECTURES WITH MULTIPLE MEMORY CELLS PER ACCESS DEVICE

Номер: US20210005811A1
Автор: Liu Jun, Violette Michael P.
Принадлежит:

A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices. 1. An apparatus , comprising:an access device comprising a gate and a drain;a dielectric that contacts at least a portion of the gate of the access device and at least a portion of the drain of the access device;a via extending through the dielectric and through at least a portion of the drain of the access device; anda deposited layer of material positioned within the via.2. The apparatus of claim 1 , further comprising:one or more tungsten contacts positioned in the via and in contact with the deposited layer of material.3. The apparatus of claim 1 , further comprising:one or more platinum contacts positioned in the via and in contact with the deposited layer of material.4. The apparatus of claim 1 , wherein the deposited layer of material comprises titanium silicide claim 1 , titanium nitride claim 1 , or a combination thereof.5. The apparatus of claim 1 , wherein the deposited layer of material comprises platinum claim 1 , or platinum silicide claim 1 , or a combination thereof.6. The apparatus of claim 1 , further comprising:a word line in contact with the gate of the access device and the drain of the access device.7. The apparatus of claim 1 , wherein a bottom of the via is p-doped or n-doped.8. A memory device claim 1 , comprising:a first memory cell;an access device comprising a gate and a drain and operatively coupled with the first memory cell; and a dielectric that contacts at least a portion of the gate of the access device and at least a portion of the drain of the access device;', 'a via extending through the dielectric and through at ...

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Номер записи: 12
02-01-2020 дата публикации

NOVEL RESISTIVE RANDOM ACCESS MEMORY DEVICE

Номер: US20200006428A1
Автор: CHENG Cheung, JIANG Jheng-Hong, LIU Chia-Wei
Принадлежит:

A memory device includes: a first conductor extending in parallel with a first axis; a first selector material comprising a first portion that extends along a first sidewall of the first conductor; a second selector material comprising a first portion that extends along the first sidewall of the first conductor; a first variable resistive material comprising a portion that extends along the first sidewall of the first conductor; and a second conductor extending in parallel with a second axis substantially perpendicular to the first axis, wherein the first portion of the first selector material, the first potion of the second selector material, and the portion of the first variable resistive material are arranged along a first direction in parallel with a third axis substantially perpendicular to the first axis and second axis. 1. A memory device , comprising:a first conductor extending substantially along a first axis;a first selector material comprising a first portion that extends along a first sidewall of the first conductor;a second selector material comprising a first portion that extends along the first sidewall of the first conductor;a first variable resistive material comprising a portion that extends along the first sidewall of the first conductor; anda second conductor extending in parallel with a second axis substantially perpendicular to the first axis,wherein the first portion of the first selector material, the first potion of the second selector material, and the portion of the first variable resistive material are stacked along a first direction in parallel with a third axis substantially perpendicular to the first axis and second axis.2. The memory device of claim 1 , wherein at least the first portion of the first selector material and the first potion of the second selector material form a selector device of a first resistive random access memory (RRAM) bit cell claim 1 , and at least the portion of the first variable resistive material forms a ...

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Номер записи: 13
03-01-2019 дата публикации

SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME

Номер: US20190006419A1
Автор: ARAI Fumitaka, Kiyotoshi Masahiro, Ozawa Yoshio, Shirota Riichiro, Yamamoto Akihito
Принадлежит: Toshiba Memory Corporation

A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode. 1. A semiconductor memory comprising:a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate;a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate;a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate; andwherein the layers are patterned in self-alignment with each other,intersections of the active areas and the first gate electrode form a plurality of memory cells, andthe plurality of memory cells in an intersecting plane share the first gate electrode.2. The memory according to claim 1 , wherein the first and second gate electrodes are formed by one layer.3. The memory according to claim 1 , wherein the first and second gate electrodes are connected to interconnections and driven independently of each other.4. The memory according to claim 1 , wherein the second gate electrode is formed parallel to the active areas claim 1 , and shared by the plurality of memory cells in a plane parallel to the active areas and perpendicular to the substrate.5. The memory according to claim 1 , wherein a ...

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Номер записи: 14
03-01-2019 дата публикации

SELECT DEVICE FOR MEMORY CELL APPLICATIONS

Номер: US20190006420A1
Автор: Cardon Christopher D., Onal Caner, Wells David H.
Принадлежит:

The present disclosure includes select devices and methods of using select device for memory cell applications. An example select device includes a first electrode having a particular geometry, a semiconductor material formed on the first electrode and a second electrode having the particular geometry with formed on the semiconductor material, wherein the select device is configured to snap between resistive states in response to signals that are applied to the select device. 1. A memory cell , comprising: a first electrode having a particular geometry;', 'a first heater formed on the first electrode;', 'a semiconductor material formed on the first heater;', 'a second heater formed on the semiconductor material; and', 'a second electrode having the particular geometry formed on the second heater; and, 'a select device includinga storage element coupled in series to the select device.2. The memory cell of claim 1 , wherein a width of the semiconductor material is less than approximately 20 nanometers.3. The memory cell of claim 1 , wherein a width of the particular geometry is based on an operating voltage associated with the memory cell.4. The memory cell of claim 1 , wherein a composition of the semiconductor material is based on an operating voltage associated with the memory cell.5. The memory cell of claim 1 , wherein the select device is configured to support bi-directional current flow therethrough.6. The memory cell of claim 1 , wherein the particular geometry is a circular geometry.7. The memory cell of claim 1 , wherein the particular geometry is a quasi-square geometry.8. A memory cell claim 1 , comprising: a first heater;', 'a first electrode on the first heater;', 'a semiconductor material on the first electrode;', 'a second electrode on the semiconductor material; and', 'a second heater on the second electrode; and, 'a select device includinga storage element coupled in series to the select device.9. The memory cell of claim 8 , wherein a vacuum is ...

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Номер записи: 15
27-01-2022 дата публикации

LOGIC DRIVE USING STANDARD COMMODITY PROGRAMMABLE LOGIC IC CHIPS COMPRISING NON-VOLATILE RANDOM ACCESS MEMORY CELLS

Номер: US20220029626A1
Автор: Lee Jin-Yuan, Lin Mou-Shiung
Принадлежит:

A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64. 1. A chip package comprising:a non-volatile memory cell configured to store resulting data of a look-up table (LUT) therein;a sense amplifier configured to sense input data thereof associated with the resulting data of the look-up table (LUT) stored in the non-volatile memory cell to generate output data of the sense amplifier;a logic circuit comprising a static-random-access-memory (SRAM) cell configured to store first data therein associated with the output data of the sense amplifier, and a selection circuit comprising a first set of input points for a first input data set for input data of a logic operation and a second set of input points for a second input data set having second data associated with the first data stored in the static-random-access-memory (SRAM) cell, wherein the selection circuit is configured to select, in accordance with the first input data set, input data from the second input data set as output data of the logic operation; anda plurality of metal bumps at a bottom of the chip package, wherein the plurality of metal bumps comprise five metal bumps arranged in a line.2. The chip package of claim 1 , wherein the sense amplifier and logic circuit are provided by a ...

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Номер записи: 16
12-01-2017 дата публикации

RESISTIVE RANDOM-ACCESS MEMORY WITH IMPLANTED AND RADIATED CHANNELS

Номер: US20170012083A1
Автор: WANG Shih-Ping, WANG Shih-Yuan
Принадлежит:

Resistive RAM (RRAM) devices having increased uniformity and related manufacturing methods are described. Greater uniformity of performance across an entire chip that includes larger numbers of RRAM cells can be achieved by uniformly creating enhanced channels in the switching layers through the use of radiation damage. The radiation, according to various described embodiments, can be in the form of ions, electromagnetic photons, neutral particles, electrons, and ultrasound. 162-. (canceled)63. A resistive random-access memory device comprising:a first electrode;a second electrode; anda switching region that is between the first and second electrodes and comprises one or more enhanced mobility pathway structures in an otherwise solid material that have been formed in a process of fabricating the device and extend at respective locations in the switching region; are configured to provide enhanced mobility of charged species;', 'have respective electrical resistances that vary with a switching voltage applied between the first and second electrodes; and', 'comprise damage in the switching region caused by ion implantation in which a key portion of the ions impinging on the switching region have passed through and exited the switching region., 'wherein said enhanced mobility pathway structures64. The resistive memory device of wherein said enhanced mobility pathway structures are formed absent an application of a voltage across to the switching region equal to or greater than a breakdown voltage.65. The resistive memory device of wherein a predominant peak in a distribution profile of ions implanted in said ion implantation is outside the switching region.66. The resistive memory device of wherein said ion implantation causes substantial collision events throughout a thickness of the switching region.67. The resistive memory device of wherein said ion implantation is through the first and second electrodes.68. The resistive memory device of wherein one of the ...

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Номер записи: 17
11-01-2018 дата публикации

Memory including Bi-polar Memristor

Номер: US20180012654A1
Автор: Chia Leong Yap, GE NING, Koh Ser Chia, Wong Wai Mun
Принадлежит: Hewlett-Packard Development Company, L.P.

A memory cell includes an input coupled to a read line, an output coupled to a circuit ground, a bi-polar memristor, and at least one address switch coupled to an address line to select the memory cell. A memory includes the bi-polar memristor and a one-way current conducting device, wherein the one-way current conducting device is positioned between the memristor cell output and the circuit ground, or between the read line and the memristor cell input. 1. A memory circuit including:a memory cell including an input coupled to a read line, an output coupled to a circuit ground, a bi-polar memristor and at least one address switch coupled to an address line to select the memory cell; anda one-way current conducting device to prevent resetting of the bi-polar memristor;wherein the one-way current conducting device is positioned between the memristor cell output and the circuit ground, or between the read line and the memristor cell input.2. The memory circuit of wherein the one-way current conducting device is a diode.3. The memory circuit of wherein a breakdown voltage of the diode is at least 10V.4. The memory circuit of wherein the one-way current conducting device is a transistor including a gate and a drain claim 1 , wherein the gate of the transistor is coupled to the drain of the transistor.5. The memory circuit of wherein the memory circuit includes a plurality of memory cells claim 1 , each memory cell being connected to a common line to a circuit ground and wherein the one-way current conducting device is positioned on the common line to the circuit ground to prevent resetting of the plurality of memory cells.6. The memory circuit of wherein the memory circuit includes a plurality of blocks claim 5 , each block including a plurality of bi-polar memristors claim 5 , each bi-polar memristor associated with a respective column switch and all bi-polar memristors in a block sharing a common row switch;wherein a plurality of row switches connect to a common line to ...

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Номер записи: 18
14-01-2016 дата публикации

GATING DEVICE CELL FOR CROSS ARRAY OF BIPOLAR RESISTIVE MEMORY CELLS

Номер: US20160013246A1
Автор: Liu Ming, Liu Qi, Long Shibing, Lv Hangbing, Wang Yan
Принадлежит:

A gating device cell for a cross array of bipolar resistive memory cells comprises an n-p diode and a p-n diode, wherein the n-p diode and the p-n diode have opposite polarities and are connected in parallel, such that the gating device cell exhibits a bidirectional rectification feature. The gating device cell exhibits the bidirectional rectification feature, that is, it can provide a relatively high current density at any voltage polarity in its ON state, and also a relatively great rectification ratio (R/R) under a read voltage. Therefore, it is possible to suppress read crosstalk in the cross array of bipolar resistive memory cells to avoid misreading, thereby solving the problem that a conventional rectifier diode is only applicable to a cross array of unipolar resistive memory cells. 1. A gating device cell for a cross array of bipolar resistive memory cells , comprising an n-p diode and a p-n diode , wherein the n-p diode and the p-n diode have opposite polarities and are connected in parallel , such that the gating device cell exhibits a bidirectional rectification feature.2. The gating device cell according to claim 1 , wherein the n-p diode and the p-n diode are connected in parallel with a dielectric isolation layer interposed therebetween.3. The gating device cell according to claim 2 , wherein the dielectric isolation layer comprises one of SiO claim 2 , SiN claim 2 , HfO claim 2 , ZrO claim 2 , or AlO.4. The gating device cell according to claim 1 , wherein the n-p diode comprises a first lower conductive electrode claim 1 , a first n-type doped semiconductor layer claim 1 , a first p-type doped semiconductor layer claim 1 , and a first upper conductive electrode that are stacked sequentially from bottom to top claim 1 , and the p-n diode comprises a second lower conductive electrode claim 1 , a second p-type doped semiconductor layer claim 1 , a second n-type doped semiconductor layer claim 1 , and a second upper conductive electrode that are stacked ...

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Номер записи: 19
11-01-2018 дата публикации

MEMORY DEVICE

Номер: US20180013061A1
Автор: Fukumizu Hiroyuki, YAMAGUCHI Takeshi
Принадлежит: Toshiba Memory Corporation

According to one embodiment, a memory device includes a stacked body. The stacked body includes first and second electrodes, and an oxide layer provided between the first and second electrodes. The second electrode includes a semiconductor layer, and a metal-containing region including at least one of first or second metallic element and being provided between at least a portion of the semiconductor layer and at least a portion of the oxide layer. The first metallic element includes at least one selected from Pt, Pd, Ir, Ru, Re, and Os. The second metallic element includes at least one selected Ti, W, Mo, and Ta. The stacked body has first and second states. The first state is obtained by causing a current to flow in the stacked body from the second toward first electrode. The second state is obtained by causing a current to flow from the first toward second electrode. 1. A memory device , comprising: a first electrode,', 'a second electrode, and', 'an oxide layer provided between the first electrode and the second electrode,, 'a stacked body including'} a semiconductor layer of an n-type, and', 'a metal-containing region including at least one of a first metallic element or a second metallic element and being provided between at least a portion of the semiconductor layer and at least a portion of the oxide layer,, 'the second electrode including'}the first metallic element including at least one selected from the group consisting of Pt, Pd, Ir, Ru, Re, and Os,the second metallic element including at least one selected from the group consisting of Ti, W, Mo, and Ta,the stacked body having a first state and a second state, the first state being obtained by causing a first current to flow in the stacked body from the second electrode toward the first electrode, the second state being obtained by causing a second current to flow in the stacked body from the first electrode toward the second electrode,a first resistance of the stacked body in the first state being lower ...

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Номер записи: 20
14-01-2021 дата публикации

Electronic device and method of manufacturing electronic device

Номер: US20210013409A1
Автор: Beom Seok Lee, Woo Tae Lee
Принадлежит: SK hynix Inc

A method of manufacturing an electronic device including a semiconductor memory may include forming a first active layer, forming a first electrode material over the first active layer, performing a heat treatment process on the first electrode material and the first active layer, and forming a second electrode material over the heat-treated first electrode material.

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Номер записи: 21
14-01-2021 дата публикации

APPARATUS FOR AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE

Номер: US20210013410A1
Автор: JUNG Jaeho, Kim Kyoung Sun, PARK Changyup, PARK JeongHee, Park Jiho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

An apparatus of fabricating a semiconductor device may include a chamber including a housing and a slit valve used to open or close a portion of the housing, a heater chuck provided in a lower region of the housing and used to heat a substrate, a target provided over the heater chuck, a plasma electrode provided in an upper region of the housing and used to generate plasma on the target, a heat-dissipation shield surrounding the inner wall of the housing between the plasma electrode and the heater chuck, and an edge heating structure provided between the heat-dissipation shield and the inner wall of the housing and configured to heat the heat-dissipation shield and an edge region of the substrate and to reduce a difference in temperature between center and edge regions of the substrate. 120.-. (canceled)21. A method of fabricating a semiconductor device , comprising:providing a substrate on a heater chuck in a chamber including a housing and a slit valve, wherein the slit valve is configure to open or close a portion of the housing;heating the substrate using the heater chuck; anddepositing a phase transition layer on the substrate by a physical vapor deposition method using a heat-dissipation shield between the housing and the heater chuck, and an edge heating structure between the heat-dissipation shield and the housing, an upper lamp provided above a level of a top surface of the slit valve, and', 'a lower lamp provided below a level of a bottom surface of the slit valve, and, 'wherein the edge heating structure compriseswherein the heat-dissipation shield includes a tube shield, which extends from a top portion of the housing to a region below the heater chuck and has a first opening adjacent to the slit valve.22. The method of claim 21 , wherein the heater chuck is rotated by a shaft in a bottom of the housing claim 21 , and the heat-dissipation shield further comprises a first sector shield configured to open or close the first opening.23. The method of claim ...

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Номер записи: 22
09-01-2020 дата публикации

PCRAM STRUCTURE

Номер: US20200013951A1
Автор: WU Jau-Yi
Принадлежит:

A memory device includes the following items. A substrate. A bottom electrode disposed over the substrate. An insulating layer disposed over the bottom electrode, the insulating layer having a through hole defined in the insulating layer. A heater disposed in the through hole. A phase change material layer disposed over the heater. A selector layer disposed over the phase change material layer. An intermediate layer disposed over the through hole. Also, a metal layer disposed over the selector layer. The metal layer is wider than the phase change material layer. 1. A memory device comprising:a substrate;a bottom electrode disposed over the substrate;an insulating layer disposed over the bottom electrode, the insulating layer having a through hole defined in the insulating layer;a heater disposed in the through hole;a phase change material layer disposed over the heater;a selector layer disposed over the phase change material layer;an intermediate layer over the through hole; anda metal layer disposed over the selector layer.2. The memory device of claim 1 , wherein the intermediate layer is wider than a diameter of the through hole.3. The memory device of claim 1 , wherein the metal layer is wider than the phase change material layer.4. The memory device of claim 1 , wherein the phase change material layer is disposed in the through hole.5. The memory device of claim 1 , wherein the selector layer is disposed in the through hole.6. The memory device of claim 1 , wherein the intermediate layer contacting the metal layer.7. The memory device of claim 1 , wherein the intermediate layer is formed of at least one of carbon and tungsten.8. The memory device of claim 1 , wherein the metal layer functions as a top electrode.9. A memory device comprising:a substrate;a bottom electrode disposed over the substrate;a first heater disposed over the bottom electrode;a first phase change material layer disposed over the first heater;a first selector layer disposed over the first ...

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Номер записи: 23
18-01-2018 дата публикации

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20180018263A1
Автор: Cho Jong-Young, HWANG Eung-Rim, KIM In-Hoe, LEE Gwang-Won, NA Young-Min
Принадлежит:

An electronic device is provided. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a substrate including a first region in which a plurality of memory cells are disposed and a second region adjacent to the first region; a first interlayer insulating layer disposed over the substrate; a plurality of first memory cells penetrating through the first interlayer insulating layer in the first region, an uppermost portion of each memory cell of the first memory cells having a first conductive carbon-containing pattern; and a first insulating carbon-containing pattern located over the first interlayer insulating layer in the second region. 1. An electronic device comprising a semiconductor memory , wherein the semiconductor memory comprises:a substrate including a first region in which a plurality of memory cells are disposed and a second region adjacent to the first region;a first interlayer insulating layer disposed over the substrate;a plurality of first memory cells penetrating through the first interlayer insulating layer in the first region, an uppermost portion of each memory cell of the first memory cells having a first conductive carbon-containing pattern; anda first insulating carbon-containing pattern located over the first interlayer insulating layer in the second region.2. The electronic device of claim 1 , wherein the first conductive carbon-containing pattern includes graphite or carbon nanotubes.3. The electronic device of claim 1 , wherein the first insulating carbon-containing pattern includes SiC claim 1 , SiCN claim 1 , SiOC claim 1 , SiOCN claim 1 , DLC (Diamond-like carbon) or amorphous carbon.4. The electronic device of claim 3 , wherein the first insulating carbon-containing pattern has a carbon content of from 10 wt % to 100 wt %.5. The electronic device of claim 1 , wherein a height of a top surface of the first ...

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Номер записи: 24
21-01-2016 дата публикации

VARIABLE RESISTANCE MEMORY DEVICE

Номер: US20160020252A1
Автор: CHO Han Woo, LEE Hyun Min
Принадлежит:

A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device includes a first insulating layer formed on a semiconductor substrate, the first insulating layer having a first hole formed therein. A switching device is formed in the first hole. A second insulating layer is formed over the first insulating layer and the second insulating layer includes a second hole. A lower electrode is formed along a surface of the second insulating layer that defines the second hole. A spacer is formed on the lower electrode and exposes a portion of the surface of the lower electrode. A variable resistance material layer is formed in the second hole, and an upper electrode is formed on the variable resistance material layer. 1. A variable resistance memory device , comprising:a first insulating layer formed on a semiconductor substrate, the first insulating layer having a first hole formed therein;a switching device formed in the first hole;a second insulating layer formed over the first insulating layer, the second insulating layer including a second hole;a lower electrode formed along a surface of the second insulating layer that defines the second hole;a spacer formed on the lower electrode, the spacer exposing a portion of the surface of the lower electrode;a variable resistance material layer formed in the second hole; andan upper electrode formed on the variable resistance material layer.2. The variable resistance memory device of claim 1 , wherein a height a portion of the lower electrode that is formed on sidewalls of the second insulating layer that define the second hole is less than a depth of the second hole by a predetermined height.3. The variable resistance memory device of claim 2 , wherein the lower electrode is formed of a material that does not contain carbon.4. The variable resistance memory device of claim 3 , wherein the portion of the lower electrode that is formed on the sidewalls of the second ...

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Номер записи: 25
21-01-2016 дата публикации

EMBEDDED NON-VOLATILE MEMORY

Номер: US20160020253A1
Автор: APODACA Mac D., HSU James Juen, SHEPARD Daniel R., TRENT Thomas Michael
Принадлежит:

The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F.sup.2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.

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Номер записи: 26
18-01-2018 дата публикации

METHOD OF FORMING SEMICONDUCTOR DEVICE INCLUDING P-N DIODE

Номер: US20180019318A1
Автор: AN Ho Kyun, IM Dong Hyun
Принадлежит:

Forming a semiconductor device includes forming a first conductive line on a substrate, forming a memory cell including a switching device and a data storage element on the first conductive line, and forming a second conductive line on the memory cell. Forming the switching device includes forming a first semiconductor layer, forming a first doped region by injecting a n-type impurity into the first semiconductor layer, forming a second semiconductor layer thicker than the first semiconductor layer, on the first semiconductor layer having the first doped region, forming a second doped region by injecting a p-type impurity into an upper region of the second semiconductor layer, and forming a P-N diode by performing a heat treatment process to diffuse the n-type impurity and the p-type impurity in the first doped region and the second doped region to form a P-N junction of the P-N diode in the second semiconductor layer. 1. A method of forming a semiconductor device , the method comprising:forming a first conductive line on a substrate;forming a memory cell including a switching device and a data storage element on the first conductive line; andforming a second conductive line on the memory cell, forming a first semiconductor layer;', 'forming a first doped region using a first doping process of injecting a n-type impurity into the first semiconductor layer;', 'forming a second semiconductor layer to be thicker than the first semiconductor layer, on the first semiconductor layer having the first doped region;', 'forming a second doped region using a second doping process of injecting a p-type impurity into an upper region of the second semiconductor layer; and', 'forming a P-N diode by performing a heat treatment process to diffuse the n-type impurity and the p-type impurity in the first doped region and the second doped region such that a P-N junction of the P-N diode is formed in the second semiconductor layer., 'wherein forming the switching device includes2. The ...

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Номер записи: 27
17-01-2019 дата публикации

Three dimensional memory array with select device

Номер: US20190019842A1
Автор: D.V. Nirmal Ramaswamy, Gurtej S. Sandhu, Scott E. Sills
Принадлежит: Micron Technology Inc

Three dimensional memory arrays and methods of forming the same are provided. An example three dimensional memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines such that the at least one conductive extension intersects each of the plurality of first conductive lines. Storage element material is arranged around the at least one conductive extension, and a select device is arranged around the storage element material. The storage element material is radially adjacent an insulation material separating the plurality of first conductive lines, and the plurality of materials arranged around the storage element material are radially adjacent each of the plurality of first conductive lines.

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Номер записи: 28
21-01-2021 дата публикации

MEMORY DEVICE AND A METHOD FOR FORMING THE MEMORY DEVICE

Номер: US20210020834A1
Автор: Loy Desmond Jia Jun, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

A memory device may include at least one inert electrode, at least one mask element arranged over the at least one inert electrode, a switching layer arranged over the at least one mask element and the at least one inert electrode, and at least one active electrode arranged over the switching layer. Both of the at least one mask element and the switching layer may be in contact with a top surface of the at least one inert electrode. The switching layer in this memory device may thus include corners at which the conductive filaments may be confined. This memory device may be formed with a process that may utilize the at least one mask element to help reduce the chances of shorting between the inert and active electrodes. 1. A memory device comprising:at least one inert electrode;at least one mask element arranged over the at least one inert electrode;a switching layer arranged over the at least one mask element and the at least one inert electrode, wherein both of the at least one mask element and the switching layer are in contact with a top surface of the at least one inert electrode; andat least one active electrode arranged over the switching layer.2. The memory device of claim 1 , wherein the at least one inert electrode comprises two or more inert electrodes separated from each other.3. The memory device of claim 2 , wherein the memory device further comprises an insulating layer below the at least one mask element and wherein the two or more inert electrodes are arranged within the insulating layer.4. The memory device of claim 1 , wherein the at least one inert electrode comprises only a single inert electrode.5. The memory device of claim 1 , wherein the at least one active electrode comprises two or more active electrodes separated from each other.6. The memory device of claim 1 , wherein the at least one active electrode comprises only a single active electrode.7. The memory device of claim 1 , wherein the at least one mask element comprises only a single ...

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Номер записи: 29
26-01-2017 дата публикации

MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20170025473A1
Автор: Lai Erh-Kun, Lee Dai-Ying, Lin Yu-Hsuan, Wu Chao-I
Принадлежит:

A memory device having an array area and a periphery area is provided. The memory device includes a substrate, an isolation layer formed in the substrate, a first doped region formed on the isolation layer in the array area, a second doped region formed on the first doped region, a metal silicide layer formed on the second doped region, and a metal silicide oxide layer formed on the metal silicide layer. 1. A memory device having an array area and a periphery area , comprising:a substrate;an isolation layer formed in the substrate;a first doped region formed on the isolation layer in the array area;a second doped region formed on the first doped region;a first metal silicide layer formed on the second doped region;a metal silicide oxide layer formed on the first metal silicide layer;a P-well formed in the substrate in the periphery area;a N-well formed adjacent to the P-well in the periphery area;two first electrodes formed in the P-well;a first gate oxide layer formed on the P-well;two second electrodes formed in the N-well;a second gate oxide layer formed on the N-well;a first doped polysilicide layer formed on the first gate oxide layer;a second doped polysilicide layer formed on the second gate oxide layer; anda plurality of second metal silicide layers formed on the first doped polysilicide layer and the second doped polysilicide layer;wherein portions of the isolation layer is formed between the P-well and the N-well.2. The memory device according to claim 1 , further comprising:a plurality of first metal silicide layers; anda spacer formed between two of the first metal silicide layers.3. The memory device according to claim 1 , further comprising:an undoped region formed between the first doped region and the second doped region.45-. (canceled)6. The memory device according to claim 1 , further comprising:a first extension portion connected with one of the first electrodes;a second extension portion connected with another one of the first electrodes,a third ...

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Номер записи: 30
28-01-2016 дата публикации

VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME

Номер: US20160027845A1
Автор: Choi Jung-Dal, JUNG Seung-Jae, KANG YOUN-SEON, Seong Dong-jun
Принадлежит:

A variable resistance memory device, and methods of manufacturing the same, include a plurality of first conductive structures extending in a first direction, a plurality of second conductive structures extending in a second direction crossing the first direction over the first conductive structures, the second conductive structures, and a plurality of memory cells that are formed at intersections at which the first conductive structures and the second conductive structures overlap each other, and each includes a selection element and a variable resistance element sequentially stacked. An upper surface of each of the first conductive structures has a width in the second direction less than a width of a bottom surface of each of the selection elements. 1. A variable resistance memory device , comprising:a plurality of first conductive structures extending in a first direction;a plurality of second conductive structures over the first conductive structures, the second conductive structures extending in a second direction crossing the first direction; anda plurality of memory cells, each including a selection element and a variable resistance element sequentially stacked, the memory cells being formed at intersections at which the first conductive structures and the second conductive structures overlap each other,wherein an upper surface of each of the first conductive structures has a width in the second direction less than a width in the second direction of a bottom surface of each of the selection elements.2. The variable resistance memory device of claim 1 , wherein each of the first conductive structure includes a plurality of protrusions in the first direction claim 1 , each of the protrusions contacting the bottom surface of each of the selection elements.3. The variable resistance memory device of claim 2 , wherein each of the protrusions has a width in the first direction less than a width in the first direction of the bottom surface of each of the selection ...

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Номер записи: 31
26-01-2017 дата публикации

Array Of Cross Point Memory Cells And Methods Of Forming An Array Of Cross Point Memory Cells

Номер: US20170025604A1
Автор: Ramaswamy Durai Vishak Nirmal, Sills Scott E.
Принадлежит:

A method of forming an array of cross point memory cells comprises forming spaced conductive lower electrode pillars for individual of the memory cells being formed along and elevationally over spaced lower first lines. Walls cross elevationally over the first lines and between the electrode pillars that are along the first lines. The electrode pillars and walls form spaced openings between the first lines. The openings are lined with programmable material of the memory cells being formed to less-than-fill the openings with the programmable material. Conductive upper electrode material is formed over the programmable material within remaining volume of the openings and spaced upper second lines are formed which cross the first lines elevationally over the conductive upper electrode material that is within the openings. A select device is between the lower electrode pillar and the underlying first line or is between the conductive upper electrode material and the overlying second line for the individual memory cells. Aspects of the invention include an array of cross point memory cells independent of method of manufacture. 115-. (canceled)16. An array of cross point memory cells comprising: a select device and a programmable device in series with each other, the select device being proximate and electrically coupled to one of the first or second lines, the programmable device being proximate and electrically coupled to one of the other of the first or second lines; and', a first pillar electrode elevationally over the one of the first lines, the first pillar electrode comprising a top and opposing sidewalls;', 'programmable material laterally outward of the opposing sidewalls of the first pillar electrode;', 'a second electrode outward of the programmable material laterally over the opposing sidewalls of the first pillar electrode; and', 'one of the first pillar electrode or the second electrode being electrically coupled to the select device, the other of the first ...

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Номер записи: 32
10-02-2022 дата публикации

SELECTOR DEVICES

Номер: US20220045127A1
Автор: Dewey Gilbert W., Le Van H., Pillarisetty Ravi, Rachmady Willy, SHARMA Abhishek A.
Принадлежит: Intel Corporation

Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electrode. The selector material may include a dielectric material and a conductive dopant. 1. A selector device , comprising:a first electrode;a second electrode; anda selector material between the first electrode and the second electrode, wherein the selector material comprises a dielectric material and a conductive dopant, wherein the dielectric material comprises a chalcogenide.2. The selector device of claim 1 , wherein the chalcogenide comprises at least one of silicon and tellurium.3. The selector device of claim 2 , wherein the chalcogenide comprises germanium.4. The selector device of claim 1 , wherein the chalcogenide comprises a group IV or group VI element.5. The selector device of claim 1 , wherein the conductive dopant includes platinum claim 1 , silver claim 1 , gold claim 1 , tantalum claim 1 , copper claim 1 , cobalt claim 1 , tungsten claim 1 , ruthenium claim 1 , palladium claim 1 , or carbon.6. The selector device of claim 1 , wherein the conductive dopant has a work function less than 4.5 electron volts.7. The selector device of claim 1 , wherein the conductive dopant has a first ion migration velocity claim 1 , the dielectric material has a second ion migration velocity claim 1 , and the second ion migration velocity is greater than the first ion migration velocity by a factor of at least 10.8. The selector device of claim 1 , wherein the selector device has a threshold voltage between 0.4 volts and 2.5 volts claim 1 , and the selector device has a holding voltage between 0.1 volts and 2.5 volts.9. The selector device of claim 1 , further comprising a getter layer between the first electrode and the selector material.10. A memory cell claim 1 , comprising:a storage element; anda selector device coupled to the storage ...

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Номер записи: 33
10-02-2022 дата публикации

SEMICONDUCTOR STORAGE DEVICE

Номер: US20220045129A1
Автор: HARA Hiroyuki, Suzuki Yoshinori
Принадлежит:

A semiconductor storage device includes lower and upper bit lines, word lines between the bit lines, and memory cells between the bit lines and the word lines. The memory cells are divided into logical slices and a memory cell from each logical slice is selected when carrying out a read or write operation. A first logical slice includes memory cells, each of which is between one of two bit lines and one of three word lines that are adjacent to each other. The two bit lines include one lower bit line and one upper bit line. A second logical slice includes memory cells, each of which is between one of three bit lines and one of three word lines that are not adjacent to each other. The three bit lines include one lower bit line and two upper bit lines. 1. A semiconductor storage device comprising:a plurality of lower bit lines extending in a first direction, the lower bit lines including first and second outer lower bit lines and a plurality of inner lower bit lines between the first and second outer lower bit lines;a plurality of word lines extending in a second direction crossing the first direction, and spaced from the plurality of lower bit lines in a third direction crossing the first and second directions, the word lines including first, second, and third word lines that are adjacent, and fourth and fifth word lines that are adjacent;a plurality of upper bit lines extending in the first direction, and spaced from the plurality of word lines in the third direction, the upper bit lines including first and second outer upper bit lines and a plurality of inner upper bit lines between the first and second outer upper bit lines, the inner upper bit lines including a first inner upper bit line adjacent to the first outer upper bit line and a second inner upper bit line adjacent to the second outer upper bit line;a memory cell array including a plurality of memory cells electrically connected between the lower bit lines and the word lines and between the upper bit lines ...

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Номер записи: 34
24-01-2019 дата публикации

SEMICONDUCTOR DEVICES

Номер: US20190027200A1
Автор: Hong HyeongSun, Hur Kijae, Hwang Yoosang, Kim Bong-Soo, KIM SungWoo, Kim Youngbae, KOH GWANHYEOB
Принадлежит:

A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed next to each other on a substrate; and a second memory section laterally spaced apart from the first memory section, the second peripheral circuit section and the second memory section disposed next to each other on the substrate, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, and the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, wherein the second memory cells are higher from the substrate than each of the capacitors. 1. A semiconductor device , comprising:a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed next to each other on a substrate; anda second memory section laterally spaced apart from the first memory section, the second peripheral circuit section and the second memory section disposed next to each other on the substrate, whereinthe first memory section comprises a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, andthe second memory section comprises a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other,wherein the second memory cells are higher from the substrate than each of the capacitors.2. The semiconductor device of claim 1 , wherein the variable resistance element and the select element of each of the second memory cells are higher from the substrate than each of the capacitors.3. The semiconductor device of claim 2 , wherein the second memory section ...

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Номер записи: 35
24-01-2019 дата публикации

CORRELATED ELECTRON SWITCH PROGRAMMABLE FABRIC

Номер: US20190027216A1
Автор: Chandra Vikas, Cline Brian, Shifren Lucian, Sinha Saurabh, Yeric Greg
Принадлежит:

Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices. 123-. (canceled)24. A method , comprising:selectively connecting or disconnecting one or more portions of an integrated circuit to one or more other portions of the integrated circuit at least in part by selectively applying a programming voltage to one or more correlated electron switch devices to cause a transition in the one or more correlated electron switch devices from a first impedance state to a second impedance state, wherein the one or more correlated electron switch devices are respectively positioned between one or more electrodes of a first metallization layer and one or more electrodes of a second metallization layer.25. The method of claim 24 , wherein the selectively connecting or disconnecting the one or more portions of the integrated circuit to the one or more other portions of the integrated circuit comprises compensating for manufacturing errors in the integrated circuit.26. The method of claim 24 , wherein the selectively connecting or disconnecting the one or more portions of the integrated circuit to the one or more other portions of the integrated circuit comprises compensating for design errors in the integrated circuit.27. The method of claim 24 , wherein the selectively connecting or disconnecting the one or more portions of the integrated circuit to the one or more other portions of the integrated circuit comprises reducing power consumption in the integrated circuit at least in part by selectively disconnecting a supply voltage from the one or more portions of the integrated circuit.28. The method of claim 24 , wherein the selectively connecting or disconnecting the one or more portions of the integrated circuit to the one or more other portions of the integrated circuit comprises adjusting clock skew between specified portions of the integrated circuit.29. The method of claim 28 , wherein the integrated circuit comprises a ...

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Номер записи: 36
24-01-2019 дата публикации

BURIED LOW-RESISTANCE METAL WORD LINES FOR CROSS-POINT VARIABLE-RESISTANCE MATERIAL MEMORIES

Номер: US20190027684A1
Автор: Liu Jun, Violette Michael P.
Принадлежит:

Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line. 1. A process of forming a memory structure , comprising:forming a first recess in a semiconductive substrate by use of a hard mask to define a pillar formed at least in part of a material of the semiconductive substrate;depositing a metal material within the first recess, and establishing conditions to form a silicide within the material of the semiconductive substrate surrounding the first recess;patterning the silicide to define a word line extending through the pillar;forming a second recess in the hard mask, the second recess exposing an upper surface of the pillar;forming a diode in the second recess; andforming a variable-resistance material coupled to the diode.2. The process of claim 1 , wherein the metal material and the silicide are heated to form the word line extending through the pillar.3. The process of claim 1 , wherein forming the diode in the second recess in the hard mask comprises:etching the hard mask to form the second recess in the hard mask;forming an epitaxial first film on the upper surface of the pillar; andforming an epitaxial second film on the epitaxial first film.4. The process of claim 3 , wherein forming the variable-resistance material comprises siliciding a portion of the epitaxial second film to form a silicide contact.5. The process of claim 4 , wherein forming the variable-resistance material further comprises forming a bottom electrode on the silicide contact.6. The process of claim 5 , wherein forming the variable-resistance material further comprises forming the variable-resistance material on the bottom electrode.7. ...

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Номер записи: 37
24-01-2019 дата публикации

BURIED LOW-RESISTANCE METAL WORD LINES FOR CROSS-POINT VARIABLE-RESISTANCE MATERIAL MEMORIES

Номер: US20190027685A1
Автор: Liu Jun, Violette Michael P.
Принадлежит:

Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line. 1. A memory structure , comprising:a semiconductive substrate, wherein the semiconductive substrate includes a pillar that is isolated from an adjacent pillar by a shallow trench isolation (STI) structure;an epitaxial first film disposed on an upper surface of the pillar;an epitaxial second film disposed above and on the epitaxial first film;a diode over the pillar and formed by the epitaxial first film and the epitaxial second film;a variable resistance material coupled to the diode; anda salicide word line having at least a portion disposed below the epitaxial first film and in the pillar, the salicide word line having an outer surface coplanar with an outer surface of the pillar, and the upper surface of the pillar being above a top surface of the salicide word line.2. The apparatus of claim 1 , further comprising a spacer disposed over the salicide word line.3. The apparatus of claim 1 , further comprising a buried oxide layer that fills an undercut in the pillar.4. The apparatus of claim 1 , further comprisinga spacer disposed above the salicide word line; anda buried oxide layer that fills an undercut in the pillar.5. The apparatus of claim 1 , wherein the salicide word line comprises cobalt silicide.6. The apparatus of claim 1 , wherein the variable-resistance material comprises a phase-change material.7. The apparatus of claim 1 , wherein the variable resistance material is selected from an alloy claim 1 , a quasi-metal composition claim 1 , a metal oxide claim 1 , and a chalcogenide.8. The apparatus of claim 1 , wherein the variable-resistance ...

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Номер записи: 38
01-02-2018 дата публикации

THERMAL MANAGEMENT OF SELECTOR

Номер: US20180033825A1
Автор: APODACA Mac D., RUBIN Kurt Allan
Принадлежит:

A non-volatile memory device that limits the temperature excursion of a selector during operation to enhance the cycling life of the non-volatile memory device. A selector, in line with a memory element, may be degraded with repeated temperature excursions as current passes through a stack during the read/write process. The selector changes from an amorphous state to become crystalline thus reducing the life of a memory device. The memory device includes a word line, a bit line disposed perpendicular to the word line, a stack—including a memory element, a selector, and a spacer—disposed between the word line and bit line, and one or more insulating layers surrounding an outer surface of the stack disposed between the word line and bit line. By surrounding the selector with a high thermal conductive heat-sink material, heat is directed away from the selector helping maintain the selector's amorphous state longer. 14-. (canceled)5. The memory device of claim 30 , wherein the spacer layer comprises a material selected from the group consisting of TiN claim 30 , TaN claim 30 , TiSiN claim 30 , TiAlN claim 30 , Co claim 30 , Ni claim 30 , and Cu.6. The memory device of claim 30 , wherein the bit line and word line comprises a material selected from the group consisting of Cu claim 30 , Al claim 30 , and W.7. The memory device of claim 30 , wherein the stack further comprises one or more electrode contacts claim 30 , the electrode contacts comprising a material selected from the group consisting of Ti claim 30 , Ta claim 30 , W claim 30 , Al claim 30 , Cr claim 30 , Zr claim 30 , Nb claim 30 , Mo claim 30 , Hf claim 30 , B claim 30 , C claim 30 , carbon intermixed with other elements claim 30 , conductive nitrides claim 30 , and combinations thereof.8. The memory device of claim 30 , wherein the memory element is selected from the group consisting of PCM claim 30 , RRAM claim 30 , MRAM and other temperature-generating memory elements.9. (canceled)10. The memory device of ...

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Номер записи: 39
01-02-2018 дата публикации

FIN SELECTOR WITH GATED RRAM

Номер: US20180033963A1
Автор: Quek Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

A method of fabricating a fin selector with a gated RRAM and the resulting device are disclosed. Embodiments include forming a bottom electrode layer and a hardmask on a semiconductor substrate; etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure; forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively; forming spacers on vertical surfaces of the first and second dummy gate stacks; forming an ILD surrounding the spacers; removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure; forming an RRAM layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; and filling each of the first and second cavities with a top electrode. 1. A phase-change random access memory (PCRAM) comprising:a semiconductor substrate;a heater layer formed on the semiconductor substrate, the heater layer and the semiconductor substrate forming a fin-like structure;an interlayer dielectric (ILD) formed on side surfaces of the fin-like structure;{'sub': 2', '2', '5, 'a GeSbTe(GST) material formed in contact with the heater layer; and'}a top electrode formed on the GST layer, to form the PCRAM.2. The PCRAM according to claim 1 , comprising:a hardmask on the heater layer, the GST layer on a top surface of the ILD on each side of the fin-like structure and on each side surface of the heater layer and the hardmask, and a top electrode on each side of the fin-like structure; orthe GST layer on the heater layer, and the top electrode over the GST layer and the ILD on each side of the fin-like structure.3. The PCRAM according to claim 1 , wherein the heater layer comprises: TaN claim 1 , TiN claim 1 , titanium tungsten (TiW) claim 1 , titanium silicon nitride (TiSiN) claim 1 , or tantalum silicon nitride (TaSiN) claim 1 , and formed to a thickness of 3 to 20 nm ...

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Номер записи: 40
17-02-2022 дата публикации

MEMORY DEVICE, MEMORY ARRAY AND METHOD OF FORMING THE SAME

Номер: US20220052112A1
Автор: CHANG WEI, TAN Juan Boon, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

A memory device may be provided. The memory device may include a substrate, wherein the substrate includes a well having a first conductivity type. The memory device may further include a contact element arranged in the well and including a first contact having the first conductivity type; a diode layer arranged in the well and having a second conductivity type opposite to the first conductivity type; and a dummy gate configured to isolate the first contact from the diode layer. The memory device may further include a memory element electrically connected to the diode layer. 1. A memory device comprising:a substrate, wherein the substrate comprises a well having a first conductivity type;a contact element arranged in the well, wherein the contact element comprises a first contact having the first conductivity type;a diode layer arranged in the well, wherein the diode layer has a second conductivity type opposite to the first conductivity type;a dummy gate configured to isolate the first contact from the diode layer; anda memory element electrically connected to the diode layer.2. The memory device of claim 1 , wherein the diode layer and at least a portion of the well form a diode.3. The memory device of claim 1 , further comprising:a channel layer having the second conductivity type, wherein the channel layer is arranged in the well; anda further diode layer arranged in the channel layer, wherein the further diode layer has the first conductivity type and is electrically connected to the memory element, wherein the further diode layer and at least a portion of the channel layer form a further diode.4. The memory device of claim 3 , further comprising an isolation element arranged in the substrate and an isolation well under the isolation element claim 3 ,wherein the isolation element is arranged between the diode layer and the further diode layer, andwherein the isolation well has the second conductivity type.5. The memory device of claim 3 , wherein the contact ...

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Номер записи: 41
31-01-2019 дата публикации

SELF-ALIGNED MEMORY DECKS IN CROSS-POINT MEMORY ARRAYS

Номер: US20190036022A1
Автор: Conti Anna Maria, Pellizzer Fabio, Pirovano Agostino, Redaelli Andrea, Tortorelli Innocenzo
Принадлежит:

A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck. 1. A method of fabricating an electronic device comprising:forming, on a substrate, a first electrode layer and a first self-selecting memory stack on the first electrode layer, wherein the first self-selecting memory stack comprises a first layer of chalcogenide glass for both selection and storage;etching, in a first etching operation, the first electrode layer and the first self-selecting memory stack to form a first set of rows extending in a first direction on the substrate, each row of the first set of rows comprising remaining portions of the first electrode layer and the first self-selecting memory stack;forming a second electrode layer and a second self-selecting memory stack on the first set of rows, wherein the second self-selecting memory stack comprises a second layer of chalcogenide glass for both selection and storage;etching, in a second etching operation, the second electrode layer and the second self-selecting memory stack to form a first set of columns extending in a second direction on the first set of rows, each column of the first set of columns comprising remaining portions of the ...

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Номер записи: 42
04-02-2021 дата публикации

Semiconductor memory device

Номер: US20210036218A1
Автор: Hiroyuki Ode
Принадлежит: Kioxia Corp

According to one embodiment, a semiconductor memory device includes a first electrode and a second electrode, a phase change layer disposed between the first electrode and the second electrode, and a conducting layer disposed between the first electrode and the phase change layer. The phase change layer contains a crystal having a Face-Centered Cubic lattice structure with a first lattice constant. The conducting layer contains a crystal having a Face-Centered Cubic lattice structure with a second lattice constant. The second lattice constant is larger than 80% and smaller than 120% of the first lattice constant.

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Номер записи: 43
19-02-2015 дата публикации

TWO TERMINAL SWITCHING DEVICE HAVING BIPOLAR SWITCHING PROPERTY, METHOD OF FABRICATING THE SAME, AND RESISTIVE MEMORY CROSS-POINT ARRAY HAVING THE SAME

Номер: US20150048299A1
Автор: HWANG Hyunsang, Woo Ji Yong
Принадлежит: POSTECH ACADEMY - INDUSTRY FOUNDATION

Provided are a two-terminal switching device having a bidirectional switching property, and a resistive memory cross-point array including the same. The two-terminal switching device includes a first electrode. A first tunneling barrier layer is disposed on the first electrode. An oxide semiconductor layer is disposed on the first tunneling barrier layer. A second tunneling barrier layer is disposed on the oxide semiconductor layer. A second electrode is disposed on the second tunneling barrier layer. 1. A two-terminal switching device , comprising:a first electrode;a first tunneling barrier layer disposed on the first electrode;an oxide semiconductor layer disposed on the first tunneling barrier layer;a second tunneling barrier layer disposed on the oxide semiconductor layer; anda second electrode disposed on the second tunneling barrier layer.2. The two-terminal switching device of claim 1 , wherein the first tunneling barrier layer and the second tunneling barrier layer are independently an insulating metal oxide layer or a metal nitride layer.3. The two-terminal switching device of claim 2 , wherein the first tunneling barrier layer and the second tunneling barrier layer are independently layers selected from the group consisting of SiO claim 2 , TiO claim 2 , AlO claim 2 , HfO claim 2 , SiN claim 2 , WO claim 2 , SrTiO claim 2 , LaAlO claim 2 , YO claim 2 , and TaO.4. The two-terminal switching device of claim 1 , wherein the first tunneling barrier layer and the second tunneling barrier layer have a thickness of 2 to 10 nm independently.5. The two-terminal switching device of claim 1 , wherein the first tunneling barrier layer is a TiOlayer.6. The two-terminal switching device of claim 1 , wherein the oxide semiconductor layer is a metal oxide layer including oxygen vacancies.7. The two-terminal switching device of claim 6 , wherein the oxide semiconductor layer has a higher concentration of oxygen vacancies at an interface in contact with the second tunneling ...

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Номер записи: 44
07-02-2019 дата публикации

CURRENT DELIVERY AND SPIKE MITIGATION IN A MEMORY CELL ARRAY

Номер: US20190043923A1
Автор: Ahmed Shafqat, Pangal Kiran
Принадлежит:

A single memory cell array is formed to maintain current delivery and mitigate current spike through the deposition of resistive materials in two or more regions of the array, including at least one region of memory cells nearer to contacts on the conductive lines and at least one region of memory cells farther from the contacts, where the contacts connect the conductive lines to the current source. Higher and lower resistive materials are introduced during the formation of the memory cells and the conductive lines based on the boundaries and dimensions of the two or more regions using a photo mask. Multiple memory cell arrays formed to maintain current delivery and mitigate current spike can be arranged into a three-dimensional memory cell array. The regions of memory cells in each memory cell array can vary depending on resistance at the contacts on the conductive lines that provide access to the memory cells, where the resistance can vary from one memory cell array to another. 1. A circuit comprising:first conductive lines in a first orientation in a plane parallel to second conductive lines in a second orientation, the first conductive lines overlapping the second conductive lines to form cross points;memory cells coupled to the first and second conductive lines at the cross points, near memory cells near to contacts at an end of any of the first and second conductive lines and far memory cells far from the contacts;a high resistive material along any of the first and second conductive lines at a cross point of a near memory cell, the high resistive material to increase a resistance of a current path for the near memory cell; anda low resistive material along any of the first and second conductive lines at a cross point of a far memory cell, the low resistive material to reduce a resistance of the current path for the far memory cell.2. The circuit of claim 1 , wherein the contacts at the end of any of the first and second conductive lines connect to a current ...

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Номер записи: 45
18-02-2021 дата публикации

Crosspoint Phase Change Memory with Crystallized Silicon Diode Access Device

Номер: US20210050384A1
Автор: Asit Ray, Bahman Hekmatshoartabari, Fabio Carta, Matthew J. BrightSky, Wanki Kim
Принадлежит: International Business Machines Corp

A method of fabricating an access device in a crosspoint memory array structure during BEOL processing includes: forming at least a first doped semiconductor layer on an upper surface of a first conductive layer, the first doped semiconductor layer being in electrical connection with the first conductive layer; exposing at least a portion of the first doped semiconductor layer to a directed energy source to cause localized annealing in the first doped semiconductor layer to activate a dopant of a first conductivity type in the first doped semiconductor layer, thereby converting at least a portion of the first doped semiconductor layer into a polycrystalline layer; forming a second conductive layer over a least a portion of the first doped semiconductor layer; and etching the first doped semiconductor layer and the first and second conductive layers to form an access device that is self-aligned with the first and second conductive layers.

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Номер записи: 46
18-02-2016 дата публикации

RESISTIVE MEMORY DEVICE AND METHOD OF OPERATING RESISTIVE MEMORY DEVICE

Номер: US20160049447A1
Автор: Choi Jung-Dal, JUNG Seung-Jae, KANG YOUN-SEON
Принадлежит:

A resistive memory device includes a plurality of memory cell pillars arranged in a line in one direction and each having a memory layer and a top electrode layer connected to the memory layer, a top conductive line having a plurality of protrusions extending downwardly and between which pockets in the bottom of the top conductive line are defined, and a plurality of insulating pillars. The protrusions of the top conductive line face and are electrically connected to the memory cell pillars, respectively, so as to be electrically connected to the memory layer through the top electrode layer of the memory cell pillar. The insulating pillars extend from insulating spaces, between side wall surfaces of the memory layers and top electrode layers of the memory cell pillars, into the pockets in the bottom of the top conductive line. 1. A resistive memory device comprising:a plurality of memory cell pillars spaced in a line in one direction and each comprising a memory layer and a top electrode layer electrically connected to the memory layer;a top conductive line having protrusions at its bottom and pockets in its bottom,wherein the pockets are defined by and between the protrusions in said one direction such that the pockets and protrusions are alternately disposed along said one direction, whereby the top conductive line has an uneven bottom surface, andthe protrusions are connected to the memory cell pillars at tops of the memory pillars, respectively, andeach of the protrusions is electrically connected to the memory layer of a respective one of the memory cell pillars through the top electrode layer of the memory cell pillar; anda plurality of insulating pillars occupying insulating spaces defined by side surfaces of the memory layer and side surfaces of the top electrode layer, the insulating pillars extending into the pockets in the bottom of the top conductive line, respectively.2. The resistive memory device of claim 1 , wherein the insulating pillars contact ...

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Номер записи: 47
06-02-2020 дата публикации

RESISTIVE MEMORY ARCHITECTURES WITH MULTIPLE MEMORY CELLS PER ACCESS DEVICE

Номер: US20200044151A1
Автор: Liu Jun, Violette Michael P.
Принадлежит:

A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices. 1. (canceled)2. A memory device , comprising:a first stacked memory structure including a first memory cell and a second memory cell;an electrode operatively coupling the first memory cell and the second memory cell to a cell select line;a first access device operatively coupled with the first memory cell; anda second stacked memory structure including a third memory cell and a fourth memory cell, wherein the electrode operatively couples the third memory cell and the fourth memory cell to the cell select line.3. The memory device of claim 2 , further comprising:a first rectifying device operatively coupled to the first memory cell and the first access device.4. The memory device of claim 2 , further comprising:a second access device operatively coupled to the second memory cell.5. The memory device of claim 4 , further comprising:a third rectifying device operatively coupled to the second memory cell and the second access device.6. The memory device of claim 4 , wherein:a position of the second access device is offset in a horizontal direction from the position of the first stacked memory structure.7. The memory device of claim 2 , further comprising:a second rectifying device operatively coupled to the electrode and the cell select line.8. The memory device of claim 2 , wherein the first memory cell and the second memory cell each comprise a phase change memory cell.9. The memory device of claim 2 , wherein the first memory cell and the second memory cell each comprise a resistive memory cell.10. The memory device of claim 2 , wherein a top surface ...

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Номер записи: 48
19-02-2015 дата публикации

Current steering element formation for memory arrays

Номер: US20150050788A1
Автор: Shepard Daniel Robert
Принадлежит: Contour Semiconductor, Inc.

The present invention is a method for forming a self-aligned, three dimensional structure in a crystalline surface and then converting that self-aligned, three dimensional structure into an array of diodes or current switches so as to minimize reverse leakage in the resulting array. 1. A method of forming a memory array comprising the steps of:a. patterning and etching to form a self-aligned, three dimensional structure in a crystalline surface and,b. converting that self-aligned, three dimensional structure into an array of current controlling devices by implanting and annealing.2. The method of further comprising the formation of an information storage element.3. The method of whereby the information storage element material comprises a resistive change material.4. The method of whereby the information storage element material comprises a phase-change material.5. The method of whereby the phase-change material is a Chalcogenide alloy.6. The method of whereby the semiconducting material comprises silicon.7. The method of whereby the semiconducting material comprises germanium.8. The method of whereby the semiconducting material comprises a III-V semiconductor.9. The method of whereby the current controlling devices are diodes.10. The method of whereby the current controlling devices are transistors. This application claims priority to and the benefit of, and incorporates herein by reference in its entirety, U.S. Provisional Patent Application No. 61/463,289 by Shepard titled “ CURRENT STEERING ELEMENT FORMATION FOR MEMORY ARRAYS ” which was filed on Feb. 15, 2011. This application makes reference to U.S. Pat. No. 5,673,218 by Shepard which issued on Sep. 30, 1997 and is titled “DUAL-ADDRESSED RECTIFIER STORAGE DEVICE” and this patent is incorporated herein by reference in its entirety.In various embodiments, the present invention relates to storage elements as they relate to memory devices, and more particularly to storage elements comprising rectifiers or diodes ...

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Номер записи: 49
19-02-2015 дата публикации

DIODE FOR VARIABLE-RESISTANCE MATERIAL MEMORIES, PROCESSES OF FORMING SAME, AND METHODS OF USING SAME

Номер: US20150050795A1
Автор: Liu Jun, Violette Michael P.
Принадлежит:

A variable-resistance material memory (VRMM) device includes a container conductor disposed over an epitaxial semiconductive prominence that is coupled to a VRMM. A VRMM device may also include a conductive plug in a recess that is coupled to a VRMM. A VRMM array may also include a conductive plug in a surrounding recess that is coupled to a VRMM. Apparatuses include the VRMM with one of the diode constructions. 1. A process comprising:forming an island in a semiconductive film to include an island first height;reducing the island first height to an island second height, wherein the island second height is defined by first and second walls in the semiconductive film first height that are arrayed in a second direction that is orthogonal to the first direction;forming a diode plug above and against the island second height, wherein the diode plug also contacts the first and second walls;forming an electrode above and on the diode plug; andcoupling the electrode to a variable-resistance material memory (VRMM) cell.2. The process of claim 1 , wherein forming the diode plug includes filling a metal at the island second height and between the first and second walls.3. The process of claim 1 , wherein forming the island includes:forming a patterned nitride film above the semiconductive film; andetching to expose the semiconductive material substrate.4. The process of claim 1 , wherein the first and second walls are formed including:forming a patterned nitride film above the semiconductive film;etching to expose the semiconductive material substrate;filling adjacent the island with a shallow-trench isolation (STI);cross-patterning the patterned nitride film to expose a portion of the patterned nitride film; andetching to expose the first and second walls, the island second height, and wherein etching to expose the first and second walls also forms a recess with a floor thereof that includes the island second height, the first and second walls, and the STI.5. The process of ...

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Номер записи: 50
16-02-2017 дата публикации

TUNABLE VOLTAGE MARGIN ACCESS DIODES

Номер: US20170047515A1
Автор: Bajaj Mohit, Deb Arpan K., KONAR Aniruddha, Murali Kota V. R. M., Pandey Rajan K., Virwani Kumar R.
Принадлежит:

The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices. 1forming a mixed ionic-electronic conduction (MIEC) layer directly on a carbon doped silicon germanium substrate;patterning the doped MIEC layer into multiple ribbons each having an approximate width of 1 nm;forming a first titanium electrode at a first end of the ribbons, a bottom surface of the first titanium electrode is in direct contact with a top surface of the MIEC layer; andforming a second titanium electrode at a second end of the ribbons such that current flows horizontally from the first titanium electrode to the second titanium electrode and through the MIEC layer, a bottom surface of the second titanium electrode is in direct contact with a top surface of the MIEC layer.. A method comprising: The present invention relates generally to high current density access devices, and more particularly, to a structure and method of forming tunable voltage margin access diodes using layers of mixed ionic-electronic conduction (MIEC) materials.In order to increase the density of memory technologies (both volatile and nonvolatile), a crosspoint design is typically preferred. In such an optimized design, the wordlines and bitlines (hereafter referred to as memory ...

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Номер записи: 51
14-02-2019 дата публикации

Phase Change Memory with Diodes Embedded in Substrate

Номер: US20190051528A1
Автор: HO ChiaHua, LAI Fang-Shi Jordan, YANG Fu-Liang
Принадлежит:

An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type. 1. A method comprising:forming a first plurality of isolation regions extending into a semiconductor substrate;forming a plurality of word lines, each between two of the first plurality of isolation regions;forming a plurality of diodes laid out as an array comprising a plurality of rows and a plurality of columns, wherein each row of the plurality of diodes overlaps, and is electrically coupling to, one of the plurality of word lines;forming a second plurality of isolation regions extending into the semiconductor substrate, wherein each of the second plurality of isolation regions separates two of the columns of the plurality of diodes; andconverting a column of the plurality of diodes into a plurality of pickup regions, wherein each of the plurality of pickup regions extends to one of the plurality of word lines.2. The method of claim 1 , wherein the second plurality of isolation regions are formed as being extend to a smaller depth into the semiconductor substrate than the first plurality of isolation regions.3. The method of claim 1 , wherein each of the plurality of diodes comprises an upper portion of a first conductivity type claim 1 , and a lower portion of a second conductivity type opposite to the first conductivity type claim 1 , and wherein the lower portions of the plurality of diodes are part of a continuous semiconductor strip of the second conductivity type.4. The method of claim 1 , wherein the converting the column of the ...

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Номер записи: 52
25-02-2016 дата публикации

Semiconductor Constructions and Methods of Forming Memory Cells

Номер: US20160056375A1
Автор: Cappelletti Paolo Giuseppe, Cupeta Carmela, Redaelli Andrea
Принадлежит:

Some embodiments include semiconductor constructions having stacks containing electrically conductive material over dielectric material. Programmable material structures are directly against both the electrically conductive material and the dielectric material along sidewall surfaces of the stacks. Electrode material electrically coupled with the electrically conductive material of the stacks. Some embodiments include methods of forming memory cells in which a programmable material plate is formed along a sidewall surface of a stack containing electrically conductive material and dielectric material. 134-. (canceled)35. A semiconductor construction , comprising:spaced-apart electrical nodes supported by a semiconductor substrate, upper surfaces of the nodes forming a two-dimensional array having rows and columns, with the columns being substantially orthogonal to the rows; nodes within a common row as one another being coupled to one another through wordlines under the rows;bridging structures over the nodes and bridging pairs of nodes to one another; the bridging structures extending in a direction substantially orthogonal to the wordlines; the bridging structures comprising first electrically conductive material stacked over dielectric material; the bridging structures comprising opposing sidewall surfaces;programmable material structures along the sidewall surfaces, the programmable material structures being directly against both the first electrically conductive material and the dielectric material of the bridging structures; each programmable material structure having two opposing sides; one of said sides being directly against both the first electrically conductive material and the dielectric material of the bridging structures and an entirety of the other of the opposing sides being directly against an insulative structure; andelectrically conductive bitlines of second electrically conductive material extending across the bridging structures; the electrically ...

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Номер записи: 53
13-02-2020 дата публикации

STORAGE APPARATUS

Номер: US20200052040A1
Автор: Aratani Katsuhisa, Nonoguchi Seiji, Ohba Kazuhiro
Принадлежит:

A storage apparatus according to an embodiment of the present disclosure includes a plurality of first wiring layers extending in one direction, a plurality of second wiring layers extending in another direction, and a plurality of memory cells provided in respective opposing regions in which the plurality of first wiring layers and the plurality of second wiring layers are opposed to each other. The plurality of memory cells each includes a selector element layer, a storage element layer, and an intermediate electrode layer provided between the selector element layer and the storage element layer. One or more of the selector element layer, the storage element layer, and the intermediate electrode layer is a common layer that is common between the plurality of memory cells, in which the plurality of memory cells is adjacent to each other and extends in the one direction or the other direction. The intermediate electrode layer includes a nonlinear resistive material. 1. A storage apparatus comprising:a plurality of first wiring layers extending in one direction;a plurality of second wiring layers extending in another direction; anda plurality of memory cells provided in respective opposing regions in which the plurality of first wiring layers and the plurality of second wiring layers are opposed to each other,the plurality of memory cells each including a selector element layer, a storage element layer, and an intermediate electrode layer provided between the selector element layer and the storage element layer,one or more of the selector element layer, the storage element layer, and the intermediate electrode layer being a common layer that is common between the plurality of memory cells, the plurality of memory cells being adjacent to each other and extending in the one direction or the other direction,the intermediate electrode layer including a nonlinear resistive material.2. The storage apparatus according to claim 1 , wherein the intermediate electrode layer is ...

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Номер записи: 54
10-03-2022 дата публикации

System and Device Including Memristor Material

Номер: US20220077390A1
Автор: Hamilton Brandon C., Rowenhorst Bruce, Snyder Kyle B., Wiebers Steven J., Wyckoff Nathaniel P.
Принадлежит:

A system may include a first conductive plate configured at least to receive an input signal and a second conductive plate configured at least to output an output signal. The system may further include a first memristor material positioned between the first conductive plate and the second conductive plate. The system may further include a second memristor material positioned between the first conductive plate and the second conductive plate. The first memristor material and the second memristor material may be in parallel electrically. The first memristor material may be different from the second memristor material. 1. A system , comprising:a first conductive plate configured at least to receive an input signal;a second conductive plate configured at least to output an output signal;a first memristor material positioned between the first conductive plate and the second conductive plate; anda second memristor material positioned between the first conductive plate and the second conductive plate, the first memristor material and the second memristor material being in parallel electrically, the first memristor material being different from the second memristor material.2. The system of claim 1 , further comprising a memristor claim 1 , the memristor comprising the first conductive plate claim 1 , the second conductive plate claim 1 , the first memristor material claim 1 , and the second memristor.3. The system of claim 2 , further comprising an integrated circuit (IC) claim 2 , the IC comprising the memristor.4. The system of claim 3 , wherein the IC is at least one of a non-volatile memory device or a radio frequency (RF) tuning device.5. The system of claim 2 , wherein the first memristor material has a first current-voltage (I-V) curve claim 2 , wherein the second memristor material has a second I-V curve claim 2 , wherein the memristor has a third I-V curve claim 2 , wherein each of the first claim 2 , second claim 2 , and third I-V curves is different.6. The ...

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Номер записи: 55
03-03-2016 дата публикации

ELECTRONIC DEVICE

Номер: US20160064659A1
Автор: CHO Kwang-Hee
Принадлежит:

An electronic device includes a semiconductor memory. The semiconductor memory includes a selection element layer; a material layer directly coupled to a first surface of the selection element layer and including a conductive filament; and a variable resistance layer coupled to a second surface of the selection element layer opposite to the first surface. 1. An electronic device comprising a semiconductor memory unit , the semiconductor memory unit comprising:a stack structure including a selection element layer and a material layer which is directly coupled to a first surface of the selection element layer and includes a conductive filament; anda variable resistance layer coupled to the stack structure.2. The electronic device according to claim 1 , wherein the variable resistance layer is coupled to a second surface of the selection element layer opposite to the first surface.3. The electronic device according to claim 1 , wherein the material layer has a variable resistance characteristic.4. The electronic device according to claim 3 , wherein the material layer includes a metal oxide claim 3 , andthe metal oxide includes oxygen vacancies so that the conductive filament is generated depending on movement of the oxygen vacancies in the metal oxide.5. The electronic device according to claim 3 , wherein the variable resistance layer and the material layer include a metal oxide claim 3 , anda thickness of the variable resistance layer is larger than that of the material layer.6. The electronic device according to claim 3 , wherein the variable resistance layer and the material layer include a metal oxide claim 3 , anda density of oxygen vacancies in the variable resistance layer is lower than that of the material layer.7. The electronic device according to claim 1 , wherein the material layer has an insulating characteristic.8. The electronic device according to claim 7 , wherein a part of the material layer is in a dielectric breakdown state so that the conductive ...

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Номер записи: 56
01-03-2018 дата публикации

NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

Номер: US20180061888A1
Автор: KWON Euipil
Принадлежит:

The nonvolatile memory device includes a semiconductor substrate, a first and a second diffusion regions formed under a surface of the semiconductor substrate, a storage layer formed on the semiconductor substrate, a gate stacked on the storage layer, wherein the first diffusion region may at least one of active regions being separated by a part of the semiconductor substrate forming a channel region., wherein the second diffusion region may include an active region intersecting the gate insulating layer, wherein the storage layer may include an insulating layer or a variable resistor, and may service as a data storage layer to store data, and may be selected by a structure including the first and the second diffusion regions. 1. A semiconductor device comprising: a plurality of memory cells , wherein a memory cell of the plurality of the memory cells , comprising:a semiconductor substrate;a storage layer formed on the semiconductor substrate;a first diffusion region formed in the semiconductor substrate on one side of the storage layer;and a second diffusion regions formed in the semiconductor substrate under the storage layer;anda gate stacked on the storage layer,wherein the storage layer includes an insulating layer or a variable resistor, andwherein the first diffusion region is formed apart from the storage layer.2. The device of claim 1 , wherein further comprising:a sidewall spacer formed along laterally sidewall of the gate, wherein the sidewall spacer is formed on a portion of the second diffusion region.3. The device of claim 1 , wherein the plurality of the memory cells is configured to share the first diffusion region of the memory cell.4. The device of claim 1 , wherein the plurality of memory cells is configured to share the gate of the memory cell.5. The device of claim 4 , wherein the device further comprising:an insulating isolation layer is formed between the second diffusion regions of the plurality of memory cells.6. The device of claim 1 , ...

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Номер записи: 57
01-03-2018 дата публикации

RESISTIVE MEMORY CELL WITH INTRINSIC CURRENT CONTROL

Номер: US20180062075A1
Автор: Atiquzzaman FNU, Bettinger Joanna, Jo Sung Hyun, Lin Fengchiao Joyce, Liu Xianliang, Ren Zeying, ZHAO Xu
Принадлежит:

Providing for a two-terminal memory cell having intrinsic current limiting characteristic is described herein. By way of example, the two-terminal memory cell can comprise a particle donor layer having a moderate resistivity, comprised of unstable or partially unstable metal compounds. The metal compounds can be selected to release metal atoms in response to an external stimulus (e.g., an electric field, a voltage, a current, heat, etc.) into an electrically-resistive switching medium, which is at least in part permeable to drift or diffusion of the metal atoms. The metal atoms form a thin filament through the switching medium, switching the memory cell to a conductive state. The moderate resistivity of the particle donor layer in conjunction with the thin filament can result in an intrinsic resistance to current through the memory cell at voltages above a restriction voltage, protecting the memory cell from excessive current. 1. A method for an electronic device having a non-volatile memory cell , comprising:applying a program signal across a first electrode and a second electrode of the non-volatile memory cell;providing from a particle donor layer adjacent to the second electrode to an electrically-resistive switching layer disposed between the particle donor layer and the first electrode, current-carrying particles in response to the program signal;beginning formation of a conductive filament in the electrically-resistive switching layer in response to the current-carrying particles from the particle donor layer and to the program signal;wherein the particle donor layer maintains a first resistance during the beginning formation of the conductive filament;completing formation of the conductive filament in the electrically-resistive switching layer in response to the current-carrying particles from the particle donor layer and to the program signal; andwherein the particle donor layer changes resistance from the first resistance to the second resistance in ...

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Номер записи: 58
04-03-2021 дата публикации

ONE SELECTOR ONE RESISTOR RAM THRESHOLD VOLTAGE DRIFT AND OFFSET VOLTAGE COMPENSATION METHODS

Номер: US20210065791A1
Автор: BEDAU Daniel, Grobis Michael K.
Принадлежит: SanDisk Technologies LLC

A memory system is provided that includes a first memory array including a first memory cell, a second memory array including a second memory cell, and a memory controller configured to determine a threshold voltage of the second memory cell to compensate a drift of a threshold voltage of the first memory cell and/or determine an offset voltage of the second memory cell to compensate an offset voltage of the first memory cell. 1. A memory system comprising:a first memory array comprising a first memory cell;a second memory array comprising a second memory cell; anda memory controller configured to determine a threshold voltage of the second memory cell to compensate a drift of a threshold voltage of the first memory cell and/or determine an offset voltage of the second memory cell to compensate an offset voltage of the first memory cell.2. The memory system of claim 1 , wherein the first memory cell and the second memory cell each comprise a reversible resistance-switching memory element coupled in series with a selector element.3. The memory system of claim 1 , wherein the first memory cell and the second memory cell each comprise one or more of a magnetoresistive random access memory element claim 1 , a phase change memory element claim 1 , and a reversible resistance-switching random access memory element.4. The memory system of claim 1 , wherein the first memory cell and the second memory cell each comprise one or more of a threshold selector device claim 1 , a conductive bridge threshold selector device claim 1 , an ovonic threshold switch claim 1 , and a Metal Insulator Transition of a Phase Transition Material type threshold selector device.5. The memory system of claim 1 , wherein the first memory array comprises data memory cells and the second memory array comprises read reference memory cells or write reference memory cells.6. The memory system of claim 1 , wherein the memory controller is further configured to adjust a read voltage used to read the first ...

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Номер записи: 59
04-03-2021 дата публикации

VIA RESISTANCE REDUCTION

Номер: US20210066394A1
Автор: Casellato Cristina, Conti Anna Maria, Redaelli Andrea
Принадлежит:

One embodiment provides a method of making a memory device. The method includes forming a via in a bit line, an interlayer and a dielectric region. The bit line is formed on the interlayer. The interlayer is formed partially on the dielectric region and partially on a plurality of memory cells. The via has a first end included in, and in direct contact with, the bit line and a second end to couple to an electrical contact. 126-. (canceled)27. A method of making a memory device , the method comprising:forming a via in a bit line, an interlayer and a dielectric region, the bit line formed on the interlayer, the interlayer formed partially on the dielectric region and partially on a plurality of memory cells,the via having a first end included in, and in direct contact with, the bit line and a second end to couple to an electrical contact.28. The method of claim 27 , wherein the forming the via comprises depositing a protective layer on the bit line and forming a void claim 27 , corresponding to the via claim 27 , in the bit line claim 27 , the interlayer and the dielectric region.29. The method of claim 28 , further comprising filling the void with a conductive material claim 28 , the filling forming a conductive layer of conductive material on the protective layer.30. The method of claim 29 , further comprising removing the conductive layer to the protective layer after filling the void with the conductive material.31. The method of claim 30 , further comprising removing the protective layer after removing the conductive layer.32. The method of claim 28 , wherein forming the void comprises etching to selectively remove a portion of the bit line claim 28 , a portion of the interlayer and a portion of the dielectric region claim 28 , the portions corresponding to the via.33. The method of claim 27 , wherein the via and the bit line are self-aligned.34. The method of claim 27 , wherein the interlayer is to enhance operation of the plurality of memory cells.35. The ...

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Номер записи: 60
17-03-2022 дата публикации

SELECTION DEVICE AND MEMORY DEVICE USING THE SAME

Номер: US20220085104A1
Автор: PARK Jea Gun
Принадлежит: IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)

The present invention discloses a selection device and a memory device including the same. The selection device according to an embodiment of the present invention has high reliability and a high selection ratio. Accordingly, when the selection device is used, a highly integrated memory cell capable of selecting a desired cell without leakage current may be provided. 1. A selection device , comprising:a first electrode;a second electrode disposed to face the first electrode;at least one selector layer disposed between the first electrode and the second electrode and comprising a metal concentration profile; anda diffusion barrier layer disposed between the first electrode, the second electrode, and the at least one selector layer to prevent diffusion of a metal.2. The selection device according to claim 1 , wherein the at least one selector layer consists of at least one first selector layer and at least one second selector layer claim 1 , andthe at least one first selector layer and the at least one second selector layer have different metal doping concentrations, and thus metal concentration profiles thereof are different from each other.3. The selection device according to claim 1 , wherein the diffusion barrier layer serves to prevent diffusion of a metal doped in the at least one selector layer into adjacent layers claim 1 , thereby maintaining difference in metal concentration profiles in the at least one selector layer.4. The selection device according to claim 1 , wherein the metal concentration profile is controlled by adjusting a thickness of the diffusion barrier layer.5. The selection device according to claim 1 , wherein materials forming the first and second electrodes comprise at least one selected from platinum (Pt) claim 1 , tungsten (W) claim 1 , titanium nitride (TiN) claim 1 , tantalum nitride (TaN) claim 1 , gold (Au) claim 1 , rubidium (Ru) claim 1 , iridium (Ir) claim 1 , palladium (Pd) claim 1 , titanium (Ti) claim 1 , hafnium (Hf) claim 1 , ...

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Номер записи: 61
28-02-2019 дата публикации

MEMORY CELL, MEMORY CELL ARRAY, MEMORY DEVICE AND OPERATION METHOD OF MEMORY CELL ARRAY

Номер: US20190066785A1
Автор: Cao Heng, CHIU Sheng Fen
Принадлежит:

Semiconductor devices and fabrication methods thereof are provided to form a memory cell. The memory cell includes a first diode, a second diode separated from the first diode. The first diode includes a first well region in a substrate, a first N-type doped region adjacent to the first well region and connected to a bit line, and a first P-type doped region adjacent to the first well region and separated from the first N-type doped region. The second diode includes a second well region in the substrate, a second N-type doped region adjacent to the second well region, and a second P-type doped region. The memory cell further includes a bottom electrode connected to the first P-type doped region and the second N-type doped region, respectively, a top electrode connected to a word line, and a data storage material layer located between the bottom electrode and the top electrode. 1. A memory cell , comprising: a first well region in a substrate;', 'a first N-type doped region adjacent to the first well region and connected to a bit line; and', 'a first P-type doped region adjacent to the first well region and separated from the first N-type doped region;, 'a first diode, comprising a second well region in the substrate, wherein the second well region has a conductivity type same as the first well region;', 'a second N-type doped region adjacent to the second well region; and', 'a second P-type doped region, adjacent to the second well region, connected to a reset line, and separated from the second N-type doped region;, 'a second diode separated from the first diode, and comprisinga bottom electrode connected to the first P-type doped region and the second N-type doped region, respectively;a top electrode connected to a word line; anda data storage material layer located between the bottom electrode and the top electrode.2. The memory cell according to claim 1 , wherein the data storage material layer comprises one of a phase change material layer and a variable ...

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Номер записи: 62
28-02-2019 дата публикации

THREE DIMENSIONAL MEMORY ARRAYS

Номер: US20190067371A1
Автор: Pellizzer Fabio, Pirovano Agostino, Redaelli Andrea, Tortorelli Innocenzo
Принадлежит:

In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material. 1. A memory array , comprising:a plurality of first dielectric materials and a plurality of stacks, wherein each respective first dielectric material and each respective stack alternate, and wherein each respective stack comprises a first conductive material and a storage material on only one side of the first conductive material; anda second conductive material passing through the plurality of first dielectric materials and the plurality of stacks such that a major axis of the second conductive material is perpendicular to a major axis of the storage material;wherein each respective stack further comprises a second dielectric material between the first conductive material and the second conductive material.2. The memory array of claim 1 , further comprising a third dielectric material between the second conductive material and the plurality of stacks and between the second conductive material and the plurality of first dielectric materials.3. The memory array of claim 2 , wherein the third dielectric material is in direct physical contact with the plurality of stacks claim 2 , the plurality of first dielectric materials claim 2 , and the second conductive material.4. The memory array of claim 1 , wherein each respective stack further comprises a third dielectric material between the first conductive material and the storage material.5. The memory array of claim 1 , wherein the first conductive material and the storage ...

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Номер записи: 63
09-03-2017 дата публикации

RESISTIVE MEMORY ARCHITECTURES WITH MULTIPLE MEMORY CELLS PER ACCESS DEVICE

Номер: US20170069838A1
Автор: Liu Jun, Violette Michael P.
Принадлежит:

A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices. 1. (canceled)2. A memory device , comprising:a stacked memory structure including a first memory cell and a second memory cell;an electrode positioned between the first memory cell and the second memory cell, the electrode operatively coupling the first memory cell and the second memory cell to a cell select line; anda first access device operatively coupled to the first memory cell.3. The memory device of claim 2 , further comprising:a first rectifying device operatively coupled to the first memory cell and the first access device.4. The memory device of claim 2 , further comprising:a second access device operatively coupled to the second memory cell.5. The memory device of claim 4 , further comprising:a third rectifying device operatively coupled to the second memory cell and the second access device.6. The memory device of claim 4 , wherein:a position of the second access device is offset in a horizontal direction from the position of the stacked memory structure.7. The memory device of claim 2 , further comprising:a second rectifying device operatively coupled to the electrode and the cell select line.8. The memory device of claim 2 , wherein the first memory cell and the second memory cell each comprise a phase change memory cell.9. The memory device of claim 2 , wherein the first memory cell and the second memory cell each comprise a resistive memory cell.10. The memory device of claim 2 , wherein a top surface of the first memory cell is in contact with a first surface of the electrode and a top surface of the second memory cell is in contact ...

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Номер записи: 64
27-02-2020 дата публикации

RESISTIVE MEMORY DEVICE

Номер: US20200066796A1
Автор: YUN Jin-chan
Принадлежит:

A resistive memory device including: first conductive lines extending in a first direction; second conductive lines extending in a second direction crossing the first direction; and memory cells connected to the first conductive lines and the second conductive lines, wherein the memory cells include: a first memory cell including a first resistive memory layer and a first heating electrode layer, the first heating electrode layer includes a first contact surface in contact with the first resistive memory layer and the first contact surface has a first contact resistance; and a second memory cell including a second resistive memory layer and a second heating electrode layer, the second heating electrode layer includes a second contact surface in contact with the second resistive memory layer and the second contact surface has a second contact resistance different from the first contact resistance. 1. A resistive memory device , comprising:a plurality of first conductive lines extending in a first direction;a plurality of second conductive lines extending in a second direction crossing the first direction; anda plurality of memory cells connected to the plurality of first conductive lines and the plurality of second conductive lines,wherein the plurality of memory cells comprise:a first memory cell comprising a first resistive memory layer and a first heating electrode layer, the first heating electrode layer comprises a first contact surface in contact with the first resistive memory layer and the first contact surface has a first contact resistance; anda second memory cell comprising a second resistive memory layer and a second heating electrode layer, the second heating electrode layer comprises a second contact surface in contact with the second resistive memory layer and the second contact surface has a second contact resistance different from the first contact resistance.2. The resistive memory device of claim 1 , wherein an area of the first contact surface is ...

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Номер записи: 65
11-03-2021 дата публикации

3D VERTICAL MEMORY ARRAY CELL STRUCTURES WITH INDIVIDUAL SELECTORS AND PROCESSES

Номер: US20210074764A1
Автор: Hsu Fu-Chang
Принадлежит:

Three-dimensional vertical memory array cell structures and processes. In an exemplary embodiment, a 3D vertical memory array structure is formed by performing operations that include forming an array stack having alternating metal layers and insulator layers, forming a hole through the array stack to expose internal surfaces of the metal layers and internal surfaces of the insulator layers, and performing a metal-oxidation process on the internal surfaces of the metal layers to form selector devices on the internal surfaces of the metal layers. The operations also include depositing one of resistive material or phase-change material within the hole on the selector devices and the internal surfaces of the insulator layers, such that the hole is reduced to a smaller hole, and depositing conductor material in the smaller hole. 1. A 3D vertical memory array structure , comprising:an array stack having alternating metal layers and insulator layers, and wherein the array stack includes a hole that exposes internal surfaces of the metal layers and internal surfaces of the insulator layers;metal-oxidation on the internal surfaces of the metal layers that forms selector devices on the internal surfaces of the metal layers;one of resistive material or phase-change material within the hole and coupled to the selector devices, and wherein the hole is reduced to a smaller hole; andconductor material in the smaller hole and coupled to the resistive material or the phase-change material.2. The structure of claim 1 , wherein the metal layers comprise one of Tantalum (Ta) claim 1 , Niobium (Nb) claim 1 , Titanium (Ti) claim 1 , Zirconium (Zr) claim 1 , Vanadium-Chromium (VCr) claim 1 , and wherein based on the metal layer the metal-oxidation comprises one of TaOx claim 1 , NbOx claim 1 , TiOX claim 1 , ZrOx claim 1 , or VCrOx claim 1 , respectively.3. The structure of claim 1 , wherein the resistive material comprises one of HfOx claim 1 , LiSiOx claim 1 , ZrSiOx claim 1 , WOx ...

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Номер записи: 66
11-03-2021 дата публикации

SELECTOR DEVICES

Номер: US20210074825A1
Автор: Dewey Gilbert W., Le Van H., Pillarisetty Ravi, Rachmady Willy, SHARMA Abhishek A.
Принадлежит: Intel Corporation

Disclosed herein are selector devices, and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, a selector material between the first electrode and the second electrode, and a getter layer between the first electrode and the selector material. The first electrode may include a material having a work function that is less than 4.5 electron volts. 1. A selector device , comprising:a first electrode, wherein the first electrode includes a material having a work function that is less than 4.5 electron volts;a second electrode;a selector material between the first electrode and the second electrode; anda getter layer between the first electrode and the selector material.2. The selector device of claim 1 , wherein the selector material includes hafnium claim 1 , tantalum claim 1 , niobium claim 1 , vanadium claim 1 , or titanium.3. The selector device of claim 2 , wherein the selector material includes an oxide.4. The selector device of claim 1 , wherein the selector material includes a chalcogenide.5. The selector device of claim 1 , wherein the material includes tantalum claim 1 , titanium claim 1 , or carbon.6. The selector device of claim 1 , wherein the first electrode is substantially uniformly composed of the material.7. The selector device of claim 1 , wherein the first electrode includes a skin layer of the material around another material.8. The selector device of claim 1 , wherein the getter layer includes tantalum claim 1 , titanium claim 1 , hafnium claim 1 , aluminum claim 1 , or chromium.9. The selector device of claim 8 , wherein the getter layer includes a nitride.10. The selector device of claim 8 , wherein the getter layer is a first getter layer claim 8 , and the selector device further includes:a second getter layer between the second electrode and the selector material.11. The selector device of claim 10 , wherein the material is a first material claim 10 , and the second electrode ...

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Номер записи: 67
24-03-2022 дата публикации

MEMORY ARRAY AND MEMORY STRUCTURE

Номер: US20220093686A1
Автор: Ho Hsin-Yi
Принадлежит: MACRONIX INTERNATIONAL CO., LTD.

A memory array and structure are provided The array includes driving elements arranged in array; memory cells arranged in array and respectively corresponding to the driving elements, where one end of each memory cell is coupled to a first end of the corresponding driving element; word lines and bit lines arranged to intersect with each other, where each word lines is coupled to control ends of the driving elements in the same word line, and each bit line is respectively coupled to the other ends of the memory cells. For each word line, the first end of one driving element is connected to the first end of at least one other driving element in the same word line by a metal line, so as to form share driving elements. 1. A memory array , comprising:a plurality of driving elements, arranged in an array with a plurality of rows and a plurality of columns;a plurality of memory cells, arranged in an array with a plurality of rows and a plurality of columns and respectively corresponding to the plurality of driving elements, wherein one end of each of the plurality of memory cells is coupled to a first end of the corresponding driving element; anda plurality of word lines and a plurality of bit lines, arranged to intersect with each other, wherein each of the plurality of word lines is respectively coupled to control ends of the plurality of driving elements in the same row, and each of the plurality of bit lines is respectively coupled to the other ends of the plurality of memory cells;wherein for each of the plurality of word lines, the first end of one of the plurality of driving elements is connected to the first end of at least one other driving element in the same row by a metal line, so as to form share driving elements.2. The memory array according to claim 1 , wherein the metal line is one of metal lines in an interconnection between the memory cell and the first end of the corresponding driving element.3. The memory array according to claim 1 , wherein the driving ...

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Номер записи: 68
24-03-2022 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20220093688A1
Автор: Lue Hang-Ting
Принадлежит:

A semiconductor device includes a substrate, a stack, a conductive pillar, a memory layer, and a salicide layer. The stack is disposed on the substrate, wherein the stack includes a plurality of insulating layers and a plurality of conductive layers that are alternately stacked along a first direction. The conductive pillar penetrates the stack along the first direction. The memory layer surrounds the conductive pillar. The salicide layer surrounds the conductive pillar, wherein the memory layer is disposed between the conductive pillar and the salicide layer. 1. A semiconductor device , comprising:a substrate;a stack disposed on the substrate, wherein the stack comprises a plurality of insulating layers and a plurality of conductive layers that are alternately stacked along a first direction;a conductive pillar penetrating the stack along the first direction;a memory layer surrounding the conductive pillar; anda salicide layer surrounding the conductive pillar, wherein the memory layer is disposed between the conductive pillar and the salicide layer.2. The semiconductor device according to claim 1 , wherein the memory layer comprises a resistive memory material.3. The semiconductor device according to claim 1 , wherein the memory layer comprises a resistive random access memory material.4. The semiconductor device according to claim 1 , wherein the memory layer comprises a phase change memory material.5. The semiconductor device according to claim 1 , wherein the salicide layer and one conductive layer of the conductive layers form a Schottky diode.6. The semiconductor device according to claim 2 , wherein the Schottky diode is used as a selector.7. The semiconductor device according to claim 1 , wherein each of the conductive layers is doped with a dopant claim 1 , and the dopant in a region adjacent to the salicide layer has a first concentration claim 1 , and the dopant in a region far away from the salicide layer has a second concentration claim 1 , and the ...

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Номер записи: 69
05-03-2020 дата публикации

MEMORY SELECTOR AND MEMORY DEVICE INCLUDING SAME

Номер: US20200075676A1
Автор: Salahuddin Shairfe Muhammad, Spessot Alessio
Принадлежит:

The disclosed technology generally relates to a memory selector and to a memory device including the memory selector, and more particularly to the memory selector and the memory device implemented in a crossbar memory architecture. In one aspect, a memory selector for a crossbar memory architecture comprises a metal bottom electrode, a metal top electrode and an intermediate layer stack between and in contact with the metal top and bottom electrodes. A bottom Schottky barrier having a bottom Schottky barrier height (Φ) is formed at the interface between the metal bottom electrode and the intermediate layer stack. A top Schottky barrier having a top Schottky barrier height (Φ) is formed at the interface between the metal top electrode and the intermediate layer stack. The disclosed technology further relates to a random access memory (RAM) and a memory cell including the memory selector. 1. A memory selector comprising back-to-back Schottky diodes for a crossbar memory architecture , the memory selector comprising:a metal bottom electrode, a metal top electrode and an intermediate layer stack arranged between and in contact with the metal top and bottom electrodes;{'sub': 'B', 'a bottom Schottky barrier having a bottom Schottky barrier height (Φ) formed at an interface between the metal bottom electrode and the intermediate layer stack; and'}{'sub': 'T', 'a top Schottky barrier having a top Schottky barrier height (Φ) formed at an interface between the metal top electrode and the intermediate layer stack,'}wherein the intermediate layer stack comprises one or more atomic layers of at least one two-dimensional (2D) material formed at one or both interfaces between the intermediate layer stack and the metal top and bottom electrodes.2. The memory selector according to claim 1 , wherein the one or more atomic layers are barrier formation layers claim 1 , each barrier formation layer being adapted to form or modulate a respective Schottky barrier height between the ...

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Номер записи: 70
05-03-2020 дата публикации

VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING VARIABLE RESISTANCE MEMORY DEVICES

Номер: US20200075850A1
Автор: Ahn Dongho, PARK Changyup, PARK JeongHee, Park Jiho
Принадлежит:

A variable resistance memory device may include insulating layers stacked on a substrate, a first conductive line penetrating the insulating layers, switching patterns between the insulating layers, a phase change pattern between the first conductive line and each of the switching patterns, and a capping pattern disposed between the phase change pattern and the first conductive line and disposed in a region surrounded by the phase change pattern. 1. A variable resistance memory device comprising:insulating layers stacked on a substrate;a first conductive line penetrating the insulating layers;switching patterns between the insulating layers;a phase change pattern between the first conductive line and each of the switching patterns; anda capping pattern between the phase change pattern and the first conductive line and at least partially surrounded by the phase change pattern.2. The variable resistance memory device of claim 1 , wherein the phase change pattern and the capping pattern are in contact with the first conductive line.3. (canceled)4. The variable resistance memory device of claim 1 , wherein the phase change pattern comprises: first material layers and second material layers claim 1 , which are alternately stacked on a sidewall of each of the switching patterns.5. The variable resistance memory device of claim 1 , wherein the first conductive line is in contact with the substrate.6. The variable resistance memory device of claim 1 , wherein at least one of the insulating layers is in contact with the substrate.7. The variable resistance memory device of claim 1 , further comprising:a first filling insulation pattern and a second filling insulation pattern, which are spaced apart from each other with the first conductive line interposed therebetween when viewed in a plan view,wherein the phase change pattern comprises:a first horizontal portion contacting a bottom surface of an upper one of a first insulating layer;a second horizontal portion contacting a ...

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Номер записи: 71
05-03-2020 дата публикации

SELF-ALIGNED MEMORY DECKS IN CROSS-POINT MEMORY ARRAYS

Номер: US20200075858A1
Автор: Conti Anna Maria, Pellizzer Fabio, Pirovano Agostino, Redaelli Andrea, Tortorelli Innocenzo
Принадлежит:

A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck. 1. A memory device , comprising:a first array of memory cells that each comprise a self-selecting memory storage element, the first array of memory cells having a first plurality of columns extending in a first direction and a first plurality of rows extending in a second direction; anda second array of memory cells that each comprise a self-selecting memory storage element, the second array of memory cells having a second plurality of columns extending in the first direction and a second plurality of rows extending in the second direction, wherein the second array overlies the first array, each of the second plurality of columns overlay respective columns of the first plurality of columns, and a width of each column of the first plurality of columns is a same width as a width of each respective column of the second plurality of columns.2. The memory device of claim 1 , wherein the first array of memory cells comprises a barrier material above access lines of the first array claim 1 , and wherein the barrier material above an access line for the first array comprises a shunt for the access line claim 1 , ...

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Номер записи: 72
05-03-2020 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

Номер: US20200075859A1
Автор: NODA Kotaro
Принадлежит: Toshiba Memory Corporation

According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction, a plurality of stacked films respectively provided between the first interconnects and the second interconnects, each of the plurality of stacked films including a variable resistance film, a first inter-layer insulating film provided in a first region between the stacked films, and a second inter-layer insulating film provided in a second region having a wider width than the first region. The second inter-layer insulating film includes a plurality of protrusions configured to support one portion of the plurality of second interconnects on the second region. A protruding length of the protrusions is less than a stacking height of the stacked films. 1forming a plurality of stacked films to extend in a first direction to be respectively stacked on a plurality of first interconnects extending in the first direction, each of the plurality of stacked films including a variable resistance film;forming a first inter-layer insulating film in a first region between the stacked films;forming a second inter-layer insulating film in a second region having a wider width than the first region;forming a plurality of second interconnects on the stacked films, on the first inter-layer insulating film, and on the second inter-layer insulating film to extend in a second direction crossing the first direction; andetching the stacked films and the first inter-layer insulating film under a space between the second interconnects,the second inter-layer insulating film under the space between the second interconnects being etched at an etching rate lower than an etching rate of the first inter-layer insulating film in the etching of the stacked films and the first inter-layer insulating film.. A method for manufacturing a semiconductor memory device, comprising: This application is a ...

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Номер записи: 73
26-03-2015 дата публикации

RESISTANCE CHANGE MEMORY

Номер: US20150085562A1
Автор: Kondo Masaki, OKAMURA Takayuki, Shigeoka Takashi, SONEHARA Takeshi
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectifying element connected in series between the first and second conductive lines, and a control circuit which is connected to both of the first and second conductive lines. The control circuit controls a voltage to change a resistance of the memory element between first and second values reversibly. The rectifying element is a diode including an anode layer, a cathode layer and an insulating layer therebetween. 1. (canceled)2. A resistance change memory comprising:a first conductive line extending in a first direction;a second conductive line extending in a second direction which is crossed to the first direction;a cell unit including a memory element and a rectifying element connected in series between the first and second conductive lines; anda control circuit which is connected to both of the first and second conductive lines,wherein the control circuit is configured to control a voltage to change a resistance of the memory element between first and second values reversibly,wherein the rectifying element is a diode including a first metal layer, a first insulating layer, a second insulating layer, a second metal layer,wherein the first insulating layer, and the second insulating layer are sandwiched between the first metal layer and the second metal layer, andwherein the first insulating layer is sandwiched between the first metal layer and the second insulating layer.3. The memory according to claim 2 , wherein barrier height of the first insulating layer differs from barrier height of the second insulating layer.4. The memory according to claim 3 , wherein the barrier height of the first insulating layer is higher than that of the second insulating layer.5. The memory according to claim 2 , wherein electron affinity of the ...

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Номер записи: 74
24-03-2016 дата публикации

Diode/Superionic Conductor/Polymer Memory Structure

Номер: US20160087007A1
Автор: Campbell Kristy A.
Принадлежит: MICRON TECHNOLOGY, INC.

A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. The first metal-chalcogenide layer has a first conductivity type and the second metal-chalcogenide layer has a second conductivity type. The plane of contact between the first and second metal-chalcogenide layers creates the p-n junction of the built-in diode. Then a polymer layer is selectively deposited on the second metal-chalcogenide layer. The second metal-chalcogenide layer provides ions to the polymer layer to change its resistivity. A top electrode is then provided over the polymer layer. An exemplary memory cell may have the following stacked structure: first electrode/n-type semiconductor/p-type semiconductor/conjugated polymer/second electrode. 139-. (canceled)40. A method of forming a semiconductor device comprising:forming a first electrode over a substrate;forming a polymer memory element in contact with said first electrode;forming a first metal-chalcogenide layer having a first conductivity type in contact with said polymer memory element;forming a second metal-chalcogenide layer having a second conductivity type in contact with said first metal-chalcogenide layer; andforming a second electrode in contact with said second metal-chalcogenide layer.41. The method of claim 40 , wherein said steps of forming said first metal-chalcogenide layer and forming said second metal-chalcogenide layer include sputtering and etching.42. The method of claim 40 , wherein said step of forming a polymer memory element includes depositing a material that adheres preferentially to the second metal-chalcogenide layer.43. The method of claim 42 , wherein said material is a conjugated polymer that changes resistance in response to an applied electric field.44. The method of claim 43 , wherein said conjugated polymer is selected ...

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Номер записи: 75
24-03-2016 дата публикации

NON-VOLATILE RESISTIVE RANDOM ACCESS MEMORY CROSSBAR DEVICES WITH MAXIMIZED MEMORY ELEMENT DENSITY AND METHODS OF FORMING THE SAME

Номер: US20160087197A1
Автор: QUEK Elgin Kiok Boone, Toh Eng Huat, TRAN Xuan Anh
Принадлежит:

Non-volatile resistive random access memory crossbar devices and methods of fabricating the same are provided herein. In an embodiment, a non-volatile resistive random access memory crossbar device includes a crossbar array including a bitline and a wordline. A hardmask that includes dielectric material is disposed over the bitline. The hardmask and the bitline include a first sidewall. A memory element layer and a selector layer are disposed in overlying relationship on the first sidewall of the bitline and hardmask. The memory element layer and a selector layer are further disposed between the bitline and the wordline, to form a first memory element and selector pair. 1. A non-volatile resistive random access memory crossbar device comprising:a crossbar array comprising a bitline and a wordline;a hardmask comprising dielectric material and disposed over the bitline, wherein the hardmask and the bitline comprise a first sidewall; anda memory element layer and a selector layer disposed in overlying relationship on the first sidewall of the bitline and hardmask, and further disposed between the bitline and the wordline, to form a first memory element and selector pair.2. The non-volatile resistive random access memory crossbar device of claim 1 , wherein the hardmask and the bitline further comprise a second sidewall on an opposing side thereof from the first sidewall claim 1 , and wherein the memory element layer and the selector layer are further disposed over the second sidewall of the bitline and hardmask.3. The non-volatile resistive random access memory crossbar device of claim 2 , wherein the memory element layer is further disposed over a top surface of the hardmask.4. The non-volatile resistive random access memory crossbar device of claim 3 , wherein the memory element layer is continuous over the first sidewall claim 3 , the top surface of the hardmask claim 3 , and the second sidewall claim 3 , and wherein the selector layer is discontinuous over the top ...

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Номер записи: 76
23-03-2017 дата публикации

VARIABLE RESISTANCE MATERIAL LAYERS AND VARIABLE RESISTANCE MEMORY DEVICES INCLUDING THE SAME

Номер: US20170084834A1
Автор: Ahn Dong-ho, Cho Sung-Lae, Kim Do-Hyung, KIM Jong-uk
Принадлежит:

A variable resistance material layer including germanium (Ge), antimony (Sb), tellurium (Te), and at least one type of impurities X. The variable resistance material layer having a composition represented by a chemical formula of X(GeSbTe), wherein an atomic concentration of the impurities X is in a range of 0 Подробнее

Номер записи: 77
19-06-2014 дата публикации

NONVOLATILE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL

Номер: US20140166968A1
Автор: HERNER Scott Brad, Kumar Tanmay, Petti Christopher J.
Принадлежит: SanDisk 3D LLC

A nonvolatile memory cell is provided that includes a diode and a reversible resistance-switching element that includes a resistance-switching metal oxide or nitride, the metal oxide or nitride including only one metal. Numerous other aspects are provided. 1. A nonvolatile memory cell comprising:a diode; anda reversible resistance-switching element comprising a resistance-switching metal oxide or nitride, the metal oxide or nitride comprising only one metal.2. The nonvolatile memory cell of claim 1 , wherein the metal oxide or nitride comprises one or more of NiO claim 1 , NbO claim 1 , TiO claim 1 , HfO claim 1 , AlO claim 1 , MgO claim 1 , CoO claim 1 , CrO claim 1 , VO claim 1 , ZnO claim 1 , ZrO claim 1 , BN claim 1 , and AlN.3. The nonvolatile memory cell of claim 1 , wherein the metal oxide or nitride comprises one or more of NiO claim 1 , NbO claim 1 , TiO claim 1 , HfO claim 1 , AlO claim 1 , MgO claim 1 , CrO claim 1 , VO claim 1 , BN claim 1 , and AlN.4. The nonvolatile memory cell of claim 1 , wherein the diode and the reversible resistance-switching element are coupled in series.5. The nonvolatile memory cell of claim 1 , wherein the diode is above or below the reversible resistance-switching element.6. The nonvolatile memory cell of claim 1 , wherein the diode comprises a vertically oriented pillar.7. The nonvolatile memory cell of claim 1 , wherein the diode comprises a semiconductor junction diode.8. The nonvolatile memory cell of claim 7 , wherein the semiconductor junction diode is vertically oriented claim 7 , comprising a bottom heavily doped region having a first conductivity type claim 7 , a middle intrinsic or lightly doped region claim 7 , and a top heavily doped region having a second conductivity type.9. The nonvolatile memory cell of claim 1 , wherein the reversible resistance-switching element comprises a pillar.10. The nonvolatile memory cell of claim 1 , wherein the memory cell comprises a first memory level.11. The nonvolatile memory ...

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Номер записи: 78
12-03-2020 дата публикации

Semiconductor storage device and method of reading data therefrom

Номер: US20200082880A1
Автор: Takaaki Nakazato, Yuki Inuzuka
Принадлежит: Kioxia Corp

A semiconductor storage device includes a memory cell having a first variable resistance element changeable from a first state to a second state at which a resistance value of the first variable resistance element is higher than that of the first variable resistance element at the first state, and a second variable resistance element connected to the first variable resistance element in series and changeable from a third state to a fourth state at which a resistance value of the second variable resistance element is higher than that of the second variable resistance element at the third state. In the memory cell, a first snapback occurs at a first threshold current and a first threshold voltage, and a second snapback occurs at a second threshold current that is greater than the first threshold current and a second threshold voltage that is greater than the first threshold voltage.

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Номер записи: 79
31-03-2016 дата публикации

NON-VOLATILE RANDOM ACCESS MEMORY (NVRAM)

Номер: US20160093671A1
Автор: Roy Anirban
Принадлежит:

A semiconductor device and methods for making the same are disclosed. The device may include: a first transistor structure; a second transistor structure; a capacitor structure comprising a trench in the substrate between the first and second transistor structures, the capacitor structure further comprising a doped layer over the substrate, a dielectric layer over the doped layer, and a conductive fill material over the dielectric layer; a first conductive contact from the first transistor structure to a first bit line; a second conductive contact from the second transistor to a non-volatile memory element; and a third conductive contact from the non-volatile memory element to a second bit line. 1. A method of making a semiconductor device , the method comprising:forming a first transistor structure over a substrate;forming a second transistor structure over the substrate; a doped layer over the substrate;', 'a dielectric layer over the doped layer; and', 'a conductive fill material over the dielectric layer;, 'forming a capacitor structure as a trench in the substrate between the first and second transistor structures, the capacitor structure comprisingforming a first conductive contact from the first transistor structure to a first bit line;forming a second conductive contact from the second transistor to a non-volatile memory element; andforming a third conductive contact from the non-volatile memory element to a second bit line.2. The method of claim 1 , wherein the doped layer is electrically coupled to a source/drain portion of the first transistor structure.3. The method of claim 1 , wherein the doped layer is electrically coupled to a source/drain portion of the second transistor structure.4. The method of claim 1 , wherein the capacitor structure further comprises a conductive cap structure over the conductive fill material.5. The method of claim 1 , wherein the first conductive contact comprises:a first via electrically coupled to a source/drain region of ...

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Номер записи: 80
29-03-2018 дата публикации

Methods Of Forming An Array Of Cross Point Memory Cells

Номер: US20180090679A1
Автор: Ramaswamy Durai Vishak Nirmal, Sills Scott E.
Принадлежит:

A method of forming an array of cross point memory cells comprises forming spaced conductive lower electrode pillars for individual of the memory cells being formed along and elevationally over spaced lower first lines. Walls cross elevationally over the first lines and between the electrode pillars that are along the first lines. The electrode pillars and walls form spaced openings between the first lines. The openings are lined with programmable material of the memory cells being formed to less-than-fill the openings with the programmable material. Conductive upper electrode material is formed over the programmable material within remaining volume of the openings and spaced upper second lines are formed which cross the first lines elevationally over the conductive upper electrode material that is within the openings. A select device is between the lower electrode pillar and the underlying first line or is between the conductive upper electrode material and the overlying second line for the individual memory cells. Aspects of the invention include an array of cross point memory cells independent of method of manufacture. 1. A method of forming an array of cross point memory cells , comprising:forming spaced lower electrode pillars for individual of the memory cells being formed along and elevationally over spaced lower first lines, walls crossing elevationally over the first lines and between the electrode pillars that are along the first lines, the electrode pillars and walls forming spaced openings between the first lines;lining the openings with programmable material of the memory cells being formed to less-than-fill the openings with the programmable material; andforming conductive upper electrode material over the programmable material within remaining volume of the openings and forming spaced upper second lines which cross the first lines elevationally over the conductive upper electrode material that is within the openings, a select device being between the ...

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Номер записи: 81
21-03-2019 дата публикации

Memory device

Номер: US20190088327A1
Автор: Yuichi Ito
Принадлежит: Toshiba Memory Corp

A memory device includes first and second resistance change elements and first and second double-gate transistors. The first resistance change element includes first and second terminals. The second resistance change element includes a third terminal coupled to the first terminal and a fourth terminal. The first double-gate transistor includes a fifth terminal coupled to the second terminal, a sixth terminal, and a first gate coupled to a first word line and a second gate coupled to a second word line. The second double-gate transistor includes a seventh terminal coupled to the fourth terminal, an eighth element, and a third gate coupled to the first word line and a fourth gate coupled to a third word line.

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Номер записи: 82
21-03-2019 дата публикации

Rf/dc decoupling system for rf switches based on phase change material

Номер: US20190088721A1
Автор: Alexandre Leon, Bruno Reig, Damien Saint-Patrice
Принадлежит: Commissariat a lEnergie Atomique et aux Energies Alternatives CEA

An RF switch provided with a first region based on a phase change material disposed between a first conductive element and a second conductive element and state control means for said first region, the switch being further provided with at least one first decoupling switch provided with a second region of phase change material.

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Номер записи: 83
09-04-2015 дата публикации

SEMICONDUCTOR DEVICE HAVING SELECTOR AND RESISTIVE CHANGE DEVICE AND METHOD OF FORMING THE SAME

Номер: US20150097154A1
Автор: KIM Gun-Hwan, KIM Kyung-min, YANG Min-Kyu
Принадлежит:

At least one example embodiment discloses a semiconductor device including a first wiring on a substrate. A second wiring is on the first wiring. A first cell is between the first wiring and the second wiring. The first cell has a first selector and a first resistive change device. A third wiring is on the second wiring. A second cell is between the second wiring and the third wiring. The second cell has a second selector and a second resistive change device. The second selector has a different thickness from the first selector. 1. A semiconductor device , comprising:a first wiring on a substrate;a second wiring on the first wiring;a first cell between the first wiring and the second wiring, the first cell having a first selector and a first resistive change device;a third wiring on the second wiring; anda second cell between the second wiring and the third wiring, the second cell having a second selector and a second resistive change device, the second selector having a different thickness than the first selector.2. The semiconductor device according to claim 1 , wherein the second selector includes a semiconductor pattern having a different impurity concentration than a semiconductor pattern of the first selector.3. The semiconductor device according to claim 1 , wherein the second selector is thinner than the first selector.4. The semiconductor device according to claim 1 , wherein the first selector includes a first N-type semiconductor pattern and a first P-type semiconductor pattern claim 1 , and the second selector includes a second N-type semiconductor pattern and a second P-type semiconductor pattern.5. The semiconductor device according to claim 4 , further comprising:a first intrinsic semiconductor pattern between the first N-type semiconductor pattern and the first P-type semiconductor pattern; anda second intrinsic semiconductor pattern between the second N-type semiconductor pattern and the second P-type semiconductor pattern.6. The semiconductor ...

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Номер записи: 84
21-03-2019 дата публикации

PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS

Номер: US20190088867A9
Автор: Chan Tsz W., Hu Yongjun Jeff, Lengade Swapnil, McTeer Everett Allen, Qin Shu
Принадлежит:

Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall 1. A method of fabricating a memory stack , comprising:forming the memory stack comprising multiple stacked elements, the memory stack defined in part by sidewalls;forming an adhesion species on at least one sidewall of the memory stack, including intermixing the adhesion species with an element of the memory stack, and further including forming a film of the adhesion species on an outer surface of the intermixed adhesion species; andimplanting a dielectric material into the adhesion species film.2. The method of claim 1 , wherein intermixing the adhesion species with the element comprises implanting the adhesion species into the sidewall of the element.3. The method of claim 2 , wherein implanting the adhesion species into the sidewall of the element comprises performing a plasma doping process at an energy less than 3 keV.4. The method of claim 1 , wherein implanting the dielectric material into the adhesion species film comprises a plasma doping process at an energy within the range of 0-2 keV.5. The method of claim 1 , wherein forming the adhesion species comprises performing both a plasma doping process and a deposition process.6. The method of claim 5 , wherein performing the plasma doping process comprises performing a plasma doping of boron into the sidewall of the element of the memory stack.7. The method of claim 6 , wherein ...

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Номер записи: 85
21-03-2019 дата публикации

ACCESS DEVICES TO CORRELATED ELECTRON SWITCH

Номер: US20190088875A1
Автор: Paz de Araujo Carlos Alberto, Shifren Lucian
Принадлежит:

Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices. 1. A device comprising:one or more first layers comprising a metallic oxide comprising a correlated electron switch (CES);one or more terminals; andone or more second layers formed between a first terminal of the one or more terminals and the one or more first layers to form a first access device to the CES, the first access device comprising a metal-insulator-metal (MIM) diode, a tunnel diode or a varistor, or a combination thereof.2. (canceled)3. The device of claim 1 , wherein at least one of the one or more second layers comprises zinc oxide doped with bismuth.4. The device of claim 1 , wherein the device comprises a correlated electron random access memory (CeRAM) element in a crosspoint memory array.5. The device of claim 1 , wherein the one or more first layers and the one or more second layers are formed from a correlated electron material (CEM) claim 1 , and wherein at least one of the one or more first layers is p-type doped claim 1 , wherein the CES comprises a bulk switch in which a majority of material forming the CES is switchable from an insulative/higher impedance state to a conductive/lower impedance state claim 1 , or from a conductive/lower impedance state to an insulative/higher impedance state.6. The device of claim 5 , wherein at least one of the one or more second metallic oxide layers is n-type doped.7. The device of claim 5 , wherein at least one of the one or more second metallic oxide layers comprises the CEM in an intrinsic state.8. The device of claim 1 , and further comprising one or more third layers formed between a second terminal of the one or more terminals and the one or more first layers to form a second access device to the CES.9. The device of claim 8 , wherein the one or more first metal oxide layers are separated from the one or more second metallic oxide layers by a first metallic layer claim 8 , and wherein the ...

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Номер записи: 86
30-03-2017 дата публикации

Arrays Of Memory Cells And Methods Of Forming An Array Of Memory Cells

Номер: US20170092695A1
Автор: Jun Liu, Kunal R. Parekh
Принадлежит: Micron Technology Inc

An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed.

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Номер записи: 87
19-03-2020 дата публикации

Shared Three-Dimensional Vertical Memory

Номер: US20200091232A1
Автор: ZHANG Guobiao
Принадлежит: HangZhou HaiCun Information Technology Co., Ltd.

In a shared three-dimensional vertical memory (3D-M), each horizontal address line comprises at least two regions: a lightly-doped region and a low-resistivity region. The lightly-doped region is formed around selected memory holes and shared by a plurality of low-leakage memory cells. The low-resistivity region forms a conductive network to reduce the resistance of the horizontal address line. 1. A three-dimensional vertical memory (3D-M) , comprising:a semiconductor substrate including a substrate circuit;a plurality of horizontal address lines stacked above said substrate circuit;a plurality of memory holes penetrating through said horizontal address lines;a plurality of programmable layers covering the sidewalls of said memory holes;a plurality of vertical address lines formed in said memory holes; said first region comprises at least a lightly-doped semiconductor material surrounding selected ones of said memory holes;', 'said first region has a higher resistivity than said second region; and,', 'a first plurality of said memory holes penetrate through said first region;', 'a second plurality of said memory holes penetrate through said second region., 'each of said horizontal address lines including at least a first region and a second region outside said first region, wherein2. The 3D-Maccording to claim 1 , wherein a plurality of low-leakage memory cells are formed at the intersections between said memory holes and said first region; and claim 1 , another plurality of high-leakage memory cells are formed at the intersections between said memory holes and said second region.3. The 3D-Maccording to claim 1 , wherein the intersections of said selected ones of said memory holes and said each of said horizontal address lines constitute at least two rows and at least two columns.4. The 3D-Maccording to claim 1 , wherein the intersections of said selected ones of said memory holes and said each of said horizontal address lines are not separated by said second region ...

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Номер записи: 88
19-03-2020 дата публикации

Storage device

Номер: US20200091235A1
Автор: Kazuhiko Yamamoto
Принадлежит: Toshiba Memory Corp

A storage device includes: a first conductive layer; a second conductive layer; and a resistance-variable layer disposed between the first conductive layer and the second conductive layer, and including a first chalcogenide containing a first element which is either silicon or germanium. An insulating layer is disposed in a second direction perpendicular to a first direction from the first conductive layer to the second conductive layer with respect to the resistance-variable layer. A first region is disposed between the resistance-variable layer and the insulating layer, and has a third concentration of the first element higher than both a first concentration of the first element in the resistance-variable layer and a second concentration of the first element in the insulating layer.

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Номер записи: 89
19-03-2020 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20200091236A1
Автор: Hokazono Akira, IWAI Hitoshi
Принадлежит: Toshiba Memory Corporation

A semiconductor memory device includes a substrate, a plurality of first wirings arranged in a first direction, a second wiring extending in the first direction, a resistance change film provided between the first wiring and the second wiring, a third wiring which extends in the second direction, a first semiconductor layer connected to the second wiring and the third wiring, a first electrode, a fourth wiring connected to the second wiring, and extends in the third direction, a fifth wiring provided between the fourth wiring and the substrate, extending in the first direction, and connected to the fourth wiring, a sixth wiring provided between the fifth wiring and the substrate, a second semiconductor layer provided between the fifth wiring and the sixth wiring and connected to the fifth wiring and the sixth wiring, and a second electrode. 1. A semiconductor memory device comprising:a substrate;a plurality of first wirings arranged in a first direction intersecting with a surface of the substrate;a second wiring extending in the first direction;a resistance change film provided between the first wiring and the second wiring;a third wiring which is closer to the substrate than the second wiring and extends in a second direction intersecting with the first direction;a first semiconductor layer provided between the second wiring and the third wiring and connected to the second wiring and the third wiring;a first electrode facing the first semiconductor layer;a fourth wiring which is farther from the substrate than the second wiring, is connected to the second wiring, and extends in a third direction intersecting with the first direction;a fifth wiring provided between the fourth wiring and the substrate, extending in the first direction, and connected to the fourth wiring;a sixth wiring provided between the fifth wiring and the substrate;a second semiconductor layer provided between the fifth wiring and the sixth wiring and connected to the fifth wiring and the sixth ...

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Номер записи: 90
19-03-2020 дата публикации

STORAGE DEVICE

Номер: US20200091238A1
Автор: SANUKI Tomoya
Принадлежит:

According to one embodiment, a storage device includes a first conductor extending along a first direction, first variable-resistance elements on the first conductor, and a second conductor on the first variable-resistance elements and extending along a second direction. A plurality of second variable-resistance elements is on the second conductor. A third conductor is on the plurality of second variable-resistance elements. The third conductor extends along the first direction. A first switching element is connected between the second conductor and a corresponding one of the first variable-resistance elements. A second switching element is connected between the third conductor and a corresponding one of second variable-resistance elements. 1. A storage device , comprising:a first conductor extending along a first direction;a plurality of first variable-resistance elements on the first conductor;a second conductor on the plurality of first variable-resistance elements, the second conductor extending along a second direction;a plurality of second variable-resistance elements on the second conductor;a third conductor on the plurality of second variable-resistance elements, the third conductor extending along the first direction;a first switching element connected between the second conductor and a corresponding one of the first variable-resistance elements; anda second switching element connected between the third conductor and a corresponding one of second variable-resistance elements.2. The storage device according to claim 1 , wherein the first switching element is between the second conductor and the corresponding one of the first variable-resistance elements.3. The storage device according to claim 1 , wherein the first switching element is between the first conductor and the corresponding one of the first variable-resistance elements.4. The storage device according to claim 1 , wherein the second switching element is between the second conductor and the ...

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Номер записи: 91
19-03-2020 дата публикации

Semiconductor device

Номер: US20200091239A1
Автор: Takayuki Miyazaki
Принадлежит: Kioxia Corp

A semiconductor device includes a plurality of first conductive lines in a first wiring layer, a plurality of second conductive lines in a second wiring layer, and a plurality of memory cells between the first and second conductive lines in a first direction in a first region. A plurality of third conductive lines in the first wiring layer, a plurality of fourth conductive lines in the second wiring, and a plurality of first memory lines are in a second region. The third conductive lines extends in a second direction and are spaced from each other in a third direction. The fourth conductive lines extend in the second direction and are spaced in the third direction. The first memory lines are between the third conductive lines and the fourth conductive lines in the first direction. The first memory lines comprise the same materials as the memory cells.

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Номер записи: 92
16-04-2015 дата публикации

SWITCHING DEVICE HAVING A NON-LINEAR ELEMENT

Номер: US20150102281A1
Автор: Jo Sung Hyun, Lu Wei
Принадлежит:

A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold. 111-. (canceled)12. A method for a semiconductor device having a plurality of memory devices are formed between intersections of a first plurality of electrodes and a second plurality of electrodes , the method comprising:applying a read threshold voltage across a first electrode from the first plurality of electrodes and a second electrode from the second plurality of electrodes, to thereby change a resistance state of a non-linear element in a first memory device that is coupled to the first electrode and the second electrode, from a high resistance state to a low resistance state, wherein the read threshold voltage is greater than a threshold voltage associated with the non-linear element, and wherein the read threshold voltage is less than a program threshold voltage associated with a first memory cell in the first memory device;while the resistance state of the non-linear element is the low resistance state, applying a read voltage across the first electrode and the second electrode to thereby promote a first current flow through the first memory device, wherein the read voltage is greater than a hold voltage associated with the non-linear element, and wherein the read voltage is less than the read threshold voltage; anddetermining a resistance state associated with the first memory device in response to the first current flow.13. The method of wherein the read voltage is less than the threshold voltage associated with the non-linear element.14. The ...

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Номер записи: 93
16-04-2015 дата публикации

METHOD OF FABRICATING DUAL TRENCH ISOLATED SELECTIVE EPITAXIAL DIODE ARRAY

Номер: US20150102455A1
Автор: Zhang Chao
Принадлежит: Semiconductor Manufacturing International (Shanghai) Corporation

Methods and devices associated with phase change memory include diodes operating as selector switches having a large driving current and high switching speed. A method of forming a semiconductor device includes providing a semiconductor substrate, defining a diode array region and a peripheral region on the semiconductor substrate, forming an N+ buried layer in the diode array region by performing an ion implantation process and an annealing process. The method also includes forming a semiconductor epitaxial layer on the N+ buried layer, forming deep trench isolations through the epitaxial layer and the N+ buried layer into a portion of the substrate in the first direction, and forming shallow trench isolations in the diode array region and in the peripheral region in the second direction. The shallow trench isolation has a depth equal to or greater than a thickness of the epitaxial layer. 1. A method of manufacturing a semiconductor device , the method comprising:providing a p-type semiconductor substrate;defining a diode array region and a peripheral device region on the p-type semiconductor substrate;forming a N+ buried layer in the diode array region by performing an ion implantation process and an annealing process;forming a semiconductor epitaxial layer on the N+ buried layer;forming a deep trench isolation through the epitaxial layer and the N+ buried layer into a portion of the substrate in a first direction;forming a shallow trench isolation in the diode array region in a second direction and a shallow trench isolation in the peripheral region in the second direction, the shallow trench isolation having a depth equal to or greater than a thickness of the epitaxial layer;forming a well region and a gate electrode of a CMOS device in the peripheral region;forming a source and a drain of the CMOS device;forming a P+ layer in the epitaxial layer; andforming N+ contact regions in the diode array region and in the peripheral device region.2. The method of claim 1 ...

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Номер записи: 94
01-04-2021 дата публикации

CROSS-POINT MEMORY ARRAY AND RELATED FABRICATION TECHNIQUES

Номер: US20210098531A1
Автор: Castro Hernan A., Russell Stephen W., Tang Stephen H., Tang Stephen W.
Принадлежит:

Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device. 1. (canceled)2. An apparatus , comprising:an upper layer of a stack, the upper layer comprising a plurality of holes that each have a first width;a first electrode layer within the stack, the first electrode layer comprising a first electrode and a second electrode; anda dielectric channel aligned with the plurality of holes and separating the first electrode from the second electrode by a first distance that is greater than the first width.3. The apparatus of claim 2 , further comprising:a memory layer within the stack, the memory layer comprising a sheet of memory material perforated by a plurality of dielectric plugs.4. The apparatus of claim 2 , further comprising:a second electrode layer within the stack, the second electrode layer comprising a third electrode and a fourth electrode; anda memory layer within the stack, the memory layer comprising a memory material element that is coupled with the first electrode, the second electrode, and the third electrode.5. The apparatus of claim 4 , wherein the memory material element is coupled with the fourth electrode.6. The apparatus of claim 2 ...

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Номер записи: 95
12-05-2022 дата публикации

NEURON, NEUROMORPHIC SYSTEM INCLUDING THE SAME

Номер: US20220149200A1
Автор: KIM Dong Won, PARK Jea Gun
Принадлежит: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY

Disclosed are a neuron and a neuromorphic system including the same. More particularly, a neuron according to an embodiment of the present invention includes a completely depleted Silicon-On-Insulator (SOI) device whose a depletion region is controlled according to an inputted electrical signal to perform integration and leakage. 1. A neuron , comprising a completely depleted Silicon-On-Insulator (SOI) device , wherein a depletion region of the SOI device is controlled according to an inputted electrical signal to perform integration and leakage.2. The neuron according to claim 1 , wherein the electrical signal inputted through at least one synapse is accumulated in the form of a potential to perform the integration.3. The neuron according to claim 1 , wherein the leakage is performed within an interval time section that is a section from a time at which the electrical signal is input to a time at which a next electrical signal is input.4. The neuron according to claim 1 , wherein the completely depleted SOI device is an NMOS transistor device that comprises:a substrate with a Silicon On Insulator (SOI) structure that sequentially comprises a first semiconductor layer; a buried insulating layer; and a second semiconductor layer used as a channel layer;a gate insulating film formed on the second semiconductor layer;a gate electrode formed on the gate insulating film; anda source region and drain region disposed on opposite side of the gate electrode and formed to be spaced apart from each other in the second semiconductor layer.5. The neuron according to claim 4 , wherein the second semiconductor layer is formed to a thickness of 3 nm to 100 nm.6. The neuron according to claim 4 , wherein the second semiconductor layer comprises at least one of silicon claim 4 , strained silicon and relaxed silicon-germanium (SiGe).7. The neuron according to claim 4 , wherein the electrical signal is input through the drain region.8. A neuromorphic system claim 4 , comprising:at ...

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Номер записи: 96
14-04-2016 дата публикации

Methods of fabricating a variable resistance memory device using masking and selective removal

Номер: US20160104746A1
Автор: Ki-jin Park, Soonwon Hwang, Youngsoo Lim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device is fabricated by forming a semiconductor layer on a substrate, patterning the semiconductor layer in a first direction parallel to a top surface of the substrate to form semiconductor patterns extending parallel to the first direction, forming sacrificial patterns in gap regions between the semiconductor patterns, forming mask patterns on the semiconductor patterns and the sacrificial patterns extending parallel to a second direction crossing the first direction, removing the sacrificial patterns, and patterning the semiconductor patterns using the mask patterns as an etch mask to form an array of selection devices for a variable resistance memory device on the substrate.

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Номер записи: 97
14-04-2016 дата публикации

MEMORY CELL ARRAY STRUCTURES AND METHODS OF FORMING THE SAME

Номер: US20160104748A1
Автор: Donadio Gabriel L., Ravasio Marcello, Sciarrillo Samuele, Somaschini Roberto
Принадлежит:

The present disclosure includes memory cell array structures and methods of forming the same. One such array includes a stack structure comprising a memory cell between a first conductive material and a second conductive material. The memory cell can include a select element and a memory element. The array can also include an electrically inactive stack structure located at an edge of the stack structure. 120.-. (canceled)21. An array of memory cells , comprising:a first stack structure; andan electrically inactive stack structure located at an edge of the first stack structure, wherein the electrically inactive stack structure is physically isolated from a conductive material to which the first stack structure is coupled.22. The array of claim 21 , wherein the first stack structure further comprises:a select element between a first electrode and a second electrode; anda memory element between the second electrode and a third electrode.23. The array of claim 21 , further comprising a second stack structure formed on the first stack structure claim 21 , each of the first and the second stack structure comprising the conductive material.24. The array of claim 21 , further comprising a dielectric material between the first stack structure and between the first stack structure and the electrically inactive stack structure.25. The array of claim 21 , wherein the first stack structure comprises a different dimension than the electrically inactive stack structure.26. The array of claim 21 , wherein the array is a cross-point array.27. An array of memory cells claim 21 , comprising:a first electrically active stack structure;a second electrically active stack structure coupled to the first electrically active stack structure;a first electrically inactive stack structure; and 'wherein the first and the second electrically inactive stack structures are physically isolated from a conductive material to which the first and the second electrically active stack structures are ...

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Номер записи: 98
03-07-2014 дата публикации

CURRENT SELECTOR FOR NON-VOLATILE MEMORY IN A CROSS BAR ARRAY BASED ON DEFECT AND BAND ENGINEERING METAL-DIELECTRIC-METAL STACKS

Номер: US20140183439A1
Автор: Ananthan Venkat, Chiang Tony P., Hashim Imran, Phatak Prashant B.
Принадлежит: INTERMOLECULAR, INC.

Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a high leakage dielectric layer sandwiched between two lower leakage dielectric layers. The low leakage layers can function to restrict the current flow across the selector device at low voltages. The high leakage dielectric layer can function to enhance the current flow across the selector device at high voltages. 1. A selector device comprising 'wherein the first layer is operable as a first electrode;', 'a first layer,'} wherein the second layer comprises a dielectric layer,', {'sup': 3', '2, 'wherein the second layer comprises a material having a leakage current density less than 10A/cmat 2 V;'}], 'a second layer disposed on the first layer,'} wherein the third layer comprises a dielectric layer,', 'wherein the third layer comprises a material different from that of the second layer,', {'sup': 6', '2, 'wherein the third layer comprises a material having a leakage current density greater than 10A/cmat 2 V;'}], 'a third layer,'} wherein the fourth layer comprises a dielectric layer,', {'sup': 3', '2, 'wherein the fourth layer comprises a material having a leakage current density less than 10A/cmat 2 V;'}], 'a fourth layer,'} wherein the fifth layer is operable as a second electrode,', 'wherein a Schottky barrier between the fifth layer and the fourth layer is higher than 1 eV,', 'wherein a Schottky barrier between the first layer and the second layer is higher than 1 eV., 'a fifth layer,'}2. A selector device as in wherein the material of the first layer is different from or the same as the material of the fifth layer.3. A selector device ...

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Номер записи: 99
13-04-2017 дата публикации

MEMORY INCLUDING A SELECTOR SWITCH ON A VARIABLE RESISTANCE MEMORY CELL

Номер: US20170104030A1
Автор: Pirovano Agostino, Redaelli Andrea
Принадлежит:

Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed. 1. (canceled)2. A method of forming a memory device , comprising:forming a memory cell coupled with a bit line and a word line;forming a selector switch in contact with and disposed on a portion the memory cell;forming a sealing layer in contact with an upper surface and a pair of sidewalls of the selector switch and a pair of sidewalls of the memory cell;forming a first conductive plug in contact with and disposed on a portion of an upper surface of the sealing layer;forming a first diffusion layer in contact with a pair of sidewalls of the first conductive plug;forming a second conductive plug in contact with a lower surface of the memory cell; andforming a second diffusion layer in contact with a pair of sidewalls of the second conductive plug.3. The method of claim 2 , wherein the selector switch comprises a Schottky diode.4. The method of claim 2 , wherein forming the selector switch is based at least in part on a thermal budget of less than 150° C.5. The method of claim 2 , wherein the memory cell comprises a variable resistance memory material.6. The method of claim 2 , wherein the first conductive plug is configured to pass electrical current between the selector switch and the word line.7. The method of claim 2 , wherein the second conductive plug is configured to pass electrical current between the memory cell and the bit line.8. An apparatus comprising:a selector switch in contact with a memory cell;a sealing layer in contact with an upper surface and a pair of sidewalls of the selector switch and a pair of sidewalls of the memory cell;a first conductive plug in contact with and disposed on a portion of the sealing layer;a first diffusion layer ...

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Номер записи: 100