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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 1647. Отображено 100.
18-04-2013 дата публикации

SEMICONDUCTOR DEVICE AND OPERATION METHOD FOR SAME

Номер: US20130092895A1
Автор: Hada Hiromitsu, Miyamura Makoto, Tada Munehiro
Принадлежит: NEC Corporation

A semiconductor device includes a first switching element, a second switching element, and at least one third switching element; wherein the third switching element includes a first terminal and a second terminal, wherein each of the first switching element and the second switching element includes an ion conductor, a first electrode which is disposed so as to have contact with the ion conductor and supplies metal ions to the ion conductor, and a second electrode which is disposed so as to have contact with the ion conductor and is less susceptible to ionization than the first electrode; and wherein 1. A semiconductor device , comprising:a first switching element, a second switching element, and at least one third switching element; whereinthe third switching element comprises a first terminal and a second terminal, whereineach of the first switching element and the second switching element comprises an ion conductor, a first electrode which is disposed so as to have contact with the ion conductor and supplies metal ions to the ion conductor, and a second electrode which is disposed so as to have contact with the ion conductor and is less susceptible to ionization than the first electrode; and wherein(a) the first electrode of the first switching element and the first electrode of the second switching element are electrically connected each other, and the first terminal of the third switching element is electrically connected to only the first electrodes which are electrically connected each other, or(b) the second electrode of the first switching element and the second electrode of the second switching element are electrically connected each other, andthe first terminal of the third switching element is electrically connected to only the second electrodes which are electrically connected each other.24-. (canceled)5. The semiconductor device according to claim 1 , whereinthe third switching element comprises a first transistor,the first transistor comprises a source ...

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Номер записи: 1
25-07-2013 дата публикации

Light-Emitting Device, Display Device, and Semiconductor Device

Номер: US20130187187A1
Автор: Matsukura Hideki
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

A light-emitting device which includes a semiconductor layer; a first insulating layer over the semiconductor layer; a gate electrode and a first conductive layer over the first insulating layer; a second insulating layer over the gate electrode and the first conductive layer; source and drain electrodes and a second conductive layer over the second insulating layer; a third insulating layer over the source and drain electrodes and the second conductive layer; a first electrode and a third conductive layer over the third insulating layer; a planarization film covering an end portion of the first electrode; an electroluminescent layer over the first electrode; and a second electrode over the electroluminescent layer and the planarization film is provided. The second electrode is electrically connected to the third conductive layer through an opening portion provided in the planarization film. The opening portion overlaps with the first, second, and third conductive layers. 1. A light-emitting device comprising:a transistor and a first conductive layer;an insulating layer over the transistor and the first conductive layer;a first electrode and a second conductive layer over the insulating layer;a planarization film over the first electrode, the planarization film comprising an opening portion;an electroluminescent layer over the first electrode and the planarization film; anda second electrode over the electroluminescent layer and the planarization film,wherein the second electrode is electrically connected to the second conductive layer through the opening portion,wherein the opening portion overlaps with the first conductive layer and the second conductive layer, andwherein the first conductive layer is electrically floating.2. The light-emitting device according to claim 1 ,wherein the first conductive layer is in the same layer as a gate electrode of the transistor, andwherein the second conductive layer is in the same layer as the first electrode.3. The light- ...

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Номер записи: 2
10-10-2013 дата публикации

SIOX-BASED NONVOLATILE MEMORY ARCHITECTURE

Номер: US20130264536A1
Автор: Fowler Burt, Mortland Glenn, Tour James M., Yao Jun
Принадлежит:

Various embodiments of the present invention pertain to memresistor cells that comprise: (1) a substrate; (2) an electrical switch associated with the substrate; (3) an insulating layer; and (3) a resistive memory material. The resistive memory material is selected from the group consisting of SiO, SiOH, SiON, SiONH, SiOCz, SiOCH, and combinations thereof, wherein each of x, y and z are equal or greater than 1 or equal or less than 2. Additional embodiments of the present invention pertain to memresistor arrays that comprise: (1) a plurality of bit lines; (2) a plurality of word lines orthogonal to the bit lines; and (3) a plurality of said memresistor cells positioned between the word lines and the bit lines. Further embodiments of the present invention provide methods of making said memresistor cells and arrays. 1. A memresistor cell comprising:a substrate;an electrical switch associated with the substrate;an insulating layer; and {'sub': x', 'x', 'x', 'y', 'x', 'y', 'x', 'z', 'x', 'z, 'wherein the resistive memory material is selected from the group consisting of SiO, SiOH, SiON, SiONH, SiOC, SiOCH, and combinations thereof, wherein each of x, y and z are equal or greater than 1 or equal or less than 2.'}, 'a resistive memory material,'}2. The memresistor cell of claim 1 , wherein the memresistor cell has two terminals.3. The memresistor cell of claim 1 , wherein the substrate is selected from the group consisting of silicon claim 1 , silicon dioxide claim 1 , aluminum oxide claim 1 , sapphire claim 1 , germanium claim 1 , gallium arsenide (GaAs) claim 1 , alloys of silicon and germanium claim 1 , indium phosphide (InP) claim 1 , and combinations thereof.4. The memresistor cell of claim 1 , wherein the electrical switch is associated with two or more conductive elements.5. The memresistor cell of claim 4 , wherein the conductive elements associated with the electrical switch are selected from the group consisting of polysilicon claim 4 , n-doped polysilicon claim ...

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Номер записи: 3
12-12-2013 дата публикации

THREE-DIMENSIONAL RESISTIVE RANDOM ACCESS MEMORY DEVICES, METHODS OF OPERATING THE SAME, AND METHODS OF FABRICATING THE SAME

Номер: US20130328005A1
Автор: SHIN Yoocheol, Yang Min Kyu
Принадлежит:

A semiconductor device includes a substrate extending in a horizontal direction. An active pillar is present on the substrate extending in a vertical direction relative to the horizontal direction of extension of the substrate. A variable resistive pattern is present on the substrate extending in the vertical direction along the active pillar, an electrical resistance of the variable resistive pattern being variable in response to an oxidation or reduction thereof. A gate is present at a sidewall of the active pillar. 1. A semiconductor device comprising:a substrate extending in a horizontal direction:an active pillar on the substrate extending in a vertical direction relative to the horizontal direction of extension of the substrate;a variable resistive pattern on the substrate extending in the vertical direction along the active pillar, an electrical resistance of the variable resistive pattern being variable in response to an oxidation or reduction thereof; anda gate at a sidewall of the active pillar.2. The semiconductor device of wherein the active pillar is a cup-shaped structure including sidewalls and a base.3. The semiconductor device of wherein the variable resistive pattern is a cup-shaped structure including sidewalls and a base.4. The semiconductor device of wherein the variable resistive pattern is at an inner region of the sidewalls of the active pillar and on the base of the active pillar.5. The semiconductor device of wherein the variable resistive pattern is a hollow structure including sidewalls at an inner region of the sidewalls of the active pillar.6. The semiconductor device of wherein the active pillar is a cup-shaped structure including sidewalls and a base claim 1 , and wherein the sidewalls of the active pillar comprise first and second active layers.7. The semiconductor device of further comprising a pad of single crystal material between the active pillar and the substrate.8. The semiconductor device of wherein the pad of single crystal ...

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Номер записи: 4
09-01-2014 дата публикации

VARIABLE RESISTANCE NONVOLATILE STORAGE DEVICE AND METHOD OF FORMING MEMORY CELL

Номер: US20140008599A1
Автор: Fujii Satoru, Kanzawa Yoshihiko, Katayama Koji, Mitani Satoru, Muraoka Shunsaku, SHIMAKAWA Kazuhiko, TAKAGI Takeshi
Принадлежит: Panasonic Corporation

A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate, (ii) a variable resistance element having: lower and upper electrodes; and a variable resistance layer whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is applied between the electrodes, and (iii) a MOS transistor formed on the substrate, wherein the variable resistance layer includes: oxygen-deficient transition metal oxide layers having compositions MOand MO(where x Подробнее

Номер записи: 5
23-01-2014 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Номер: US20140021428A1
Автор: Adachi Takao, KAKEGAWA Tomoyasu, TANAKA Yoshinori
Принадлежит:

A semiconductor device comprises a first transistor including a first diffusion region, a first body region, and a second diffusion region, formed to align in a direction orthogonal to a main surface; a second transistor including a third diffusion region, a second body region, and a fourth diffusion region, formed to align in a direction orthogonal to the main surface; a first variable resistance element provided in the second diffusion region of the first transistor; a second variable resistance element provided in the fourth diffusion region of the second transistor; a bit line commonly connected to the first variable resistance element and the second variable resistance element; a first word line arranged on a first side of the first body region; a second word line arrange between a second side of the first body region and a first side of the second body region; and a third word line arranged on a second side of the second body region. 1. A semiconductor device comprising:a first transistor including a first diffusion region of a first conductivity type, a first body region of a second conductivity type and a second diffusion region of the first conductivity type, the first and second diffusion regions and the first body region being arranged in a direction orthogonal to a main surface;a second transistor including a third diffusion region of the first conductivity type, a second body region of the second conductivity type and a fourth diffusion region of the first conductivity type, the third and fourth diffusion regions and the second body region being arranged in the direction orthogonal to the main surface;a first variable resistance element provided on the second diffusion region of the first transistor;a second variable resistance element provided on the fourth diffusion region of the second transistor;a bit line commonly connected to the first variable resistance element and the second variable resistance element;a first word line arranged on a first side ...

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Номер записи: 6
06-03-2014 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20140061572A1
Автор: CHO Heung-Jae
Принадлежит: SK HYNIX INC.

This technology relates to a semiconductor device and a method of manufacturing the same. A semiconductor device may include a line layer formed over a substrate, and connection structures each configured to include a first metal layer pattern, a barrier layer pattern, and a second metal layer pattern sequentially stacked over the line layer, for bonding another substrate to the substrate. In accordance with this technology, abnormal silicidation may be prevented because the barrier layer is formed at the bonding interface of the substrates, and the bonding energy of the substrates may be improved by titanium (Ti)-silicon (Si) bonding. 1. A semiconductor device , comprising:a line layer formed over a substrate; andconnection structures each configured to comprise a first metal layer pattern, a barrier layer pattern, and a second metal layer pattern sequentially stacked over the line layer, for bonding another substrate to the substrate.2. The semiconductor device of claim 1 , wherein the first metal layer pattern comprises tungsten (W) claim 1 , copper (Cu) claim 1 , gold (Au) claim 1 , or aluminum (Al) claim 1 , or a combination thereof.3. The semiconductor device of claim 1 , wherein the barrier layer pattern comprises metal nitride or nitrided metal silicide claim 1 , or a combination thereof.4. The semiconductor device of claim 1 , wherein second metal layer pattern comprises titanium.5. The semiconductor device of claim 1 , further comprising:cell transistors connected to top surfaces of the connection structures; andstorage elements connected to top surfaces of the cell transistors.6. The semiconductor device of claim 5 , wherein:each of the cell transistors comprises the impurity layer pattern vertically protruded from the substrate, andthe impurity layer pattern comprises silicon.7. The semiconductor device of claim 5 , wherein:each of the storage elements comprises a lower electrode and an upper electrode separated from the lower electrode, anda variable ...

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Номер записи: 7
20-03-2014 дата публикации

SEMICONDUCTOR DEVICE INCLUDING FINFET DEVICE

Номер: US20140077146A1
Автор: Kakoschke Ronald, SCHRUEFER Klaus
Принадлежит:

A memory element includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element. 1. An apparatus , comprising , comprising:a memory element having two terminals;a source line, extending in a first direction above the surface of a substrate;a pair of fins, extending in parallel in a second direction above the surface of the substrate, each of the fins being partially wrapped around by the source line;a local interconnect extending in the first direction above the surface of the substrate, contacting one terminal of the memory element, and partially wrapping around the pair of fine;a gate line extending in the first direction above the surface of the substrate, arranged between the source line and the local interconnect, and partially wrapping around the pair of the fins; anda bit line coupled to another terminal of the memory element, and extending in the second direction above the substrate, but not in contact with the source line and the gate line.2. The apparatus of claim 1 , wherein the memory element is a NVM.3. The apparatus of claim 1 , wherein the memory element is selected from the group of elements consisting of PCRAM claim 1 , NRAM claim 1 , CMRAM claim 1 , and FeRAM.4. The apparatus of claim 1 , wherein the local interconnect is made of a conductive material.5. The apparatus of claim 1 , wherein the local interconnect is made of a conductive material selected from the one or more of copper claim 1 , silver claim 1 , gold claim 1 , aluminum claim 1 , and their alloys.6. A memory device claim 1 , comprising:a memory element;a pair of fins extending in parallel;a gate line coupled to each of the pair of fins; anda local interconnect coupled between the memory element and and the pair of fins, the local interconnect being in direct contact with a top surface of each of the pair of fins.7. The memory device of claim 6 , wherein the local interconnect ...

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Номер записи: 8
06-01-2022 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20220005869A1
Автор: Cho JungHyun, KIM Song Yi
Принадлежит:

A semiconductor memory device is disclosed. The device may include a device isolation layer in a substrate to define first and second active portions, a first contact on the substrate, first and second memory cells spaced apart from the first contact in a first direction by first and second distances, respectively, first and second conductive lines connected to the first and second memory cells, respectively, and extending in a second direction, and first and second selection transistors respectively connected to the first and second conductive lines. A length of a bottom surface of a first gate electrode of the first selection transistor overlapping the first active portion in a third direction may be different from a length of a bottom surface of a second gate electrode of the second selection transistor overlapping the second active portion in the third direction. 1. A semiconductor memory device , comprising:a device isolation layer provided in a substrate to define a first active portion and a second active portion;a first contact disposed on the substrate;a first memory cell and a second memory cell, which are spaced apart from the first contact in a first direction by a first distance and a second distance, respectively;a first conductive line connected to the first memory cell and extending in a second direction crossing the first direction;a second conductive line connected to the second memory cell and extending in the second direction;a first selection transistor connected to the first conductive line and including the first active portion; anda second selection transistor connected to the second conductive line and including the second active portion,wherein the first selection transistor comprises a first gate electrode crossing the first active portion in a third direction, the third direction being the same as or different from the second direction,the second selection transistor comprises a second gate electrode crossing the second active portion in ...

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Номер записи: 9
05-01-2017 дата публикации

Method, Apparatus and Device for Operating Logical Operation Array of Resistive Random Access Memory

Номер: US20170004880A1
Автор: Junfeng Zhao, Ronggang Xu, Xiangshui Miao, Yaxiong Zhou, Yi Li, Zhulin Wei
Принадлежит: Huawei Technologies Co Ltd

A logical operation array of a resistive random access memory includes at least one logical operation unit; each logical operation unit includes multiple resistive random access memories, multiple field effect transistor switches and a voltage converter. The logical operation array is set for performing logical operation and enable to storage output level signal in one resistive random access memory after the logical operation

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Номер записи: 10
05-01-2017 дата публикации

REDUCED CURRENT MEMORY DEVICE

Номер: US20170004883A1
Автор: Sekar Deepak Chandra
Принадлежит: RAMBUS INC.

A memory device includes a local bit line coupled to a plurality of memory cells and a global bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path is active in at least one of a set operation or a forming operation and the second path is active in a reset operation. A select device to select a memory element includes a drain having a first doping level and a source having a second doping level lower than the first doping level, wherein the device is configured to provide a break for vias first on impedance or a second on impedance to the or dummies resistive memory element in response to a control signal. 1. A memory device , comprising:a local bit line electrically coupled to a plurality of resistive memory cells; anda global bit line electrically coupled to the local bit line through first and second selectable parallel paths having first and second impedances, respectively;wherein the first path is active in at least one of a set operation or and a forming operation; andwherein the second path is active in a reset operation.23-. (canceled)4. The memory device of claim 1 ,wherein the first path comprises a first switching element serially coupled to a first resistor; andwherein the second path comprises a second switching element.5. (canceled)6. The memory device of claim 1 ,wherein the first path comprises a first type of switching element; andwherein the second path comprises a second type of switching element different from the first type of switching element.7. The memory device of claim 6 ,wherein the first type of switching element comprises a first source and drain doping level; andwherein the second type of switching element comprises a second source and drain doping level different from the first source and drain doping level.811-. (canceled)12. The memory device of claim 1 ,wherein the global bit line electrically couples to the local bit line through a multiple gate switching ...

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Номер записи: 11
05-01-2017 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

Номер: US20170005264A1
Автор: MASUOKA Fujio, Nakamura Hiroki
Принадлежит:

The present invention provides a memory structure including a resistance-changing storage element, which enables a reset operation with a reset gate and in which cross-sectional areas of a resistance-changing film and a lower electrode in a current-flowing direction can be decreased. The semiconductor device of the present invention comprises a first pillar-shaped semiconductor layer, a gate insulating film formed around the first pillar-shaped semiconductor layer, a gate electrode made of a metal and formed around the gate insulating film, a gate line made of a metal and connected to the gate electrode, a second gate insulating film formed around an upper portion of the first pillar-shaped semiconductor layer, a first contact made of a second metal and formed around the second gate insulating film, a second contact which is made of a third metal and which connects an upper portion of the first contact to an upper portion of the first pillar-shaped semiconductor layer, a second diffusion layer formed in a lower portion of the first pillar-shaped semiconductor layer, a pillar-shaped insulating layer formed on the second contact, a resistance-changing film formed around an upper portion of the pillar-shaped insulating layer, a lower electrode formed around a lower portion of the pillar-shaped insulating layer and connected to the resistance-changing film, a reset gate insulating film that surrounds the resistance-changing film, and a reset gate that surrounds the reset gate insulating film. 1a seventh step of depositing a second interlayer insulating film, forming a contact hole, depositing a fourth metal and a nitride film,removing portions of the fourth metal and the nitride film on the second interlayer insulating film to form a pillar-shaped nitride film layer and a lower electrode in the contact hole, the lower electrode surrounding a bottom portion of the pillar-shaped nitride film layer and the pillar-shaped nitride film layer,etching back the second interlayer ...

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Номер записи: 12
05-01-2017 дата публикации

TRANSISTOR USING PIEZORESISTOR AS CHANNEL, AND ELECTRONIC CIRCUIT

Номер: US20170005265A1
Автор: Funakubo Hiroshi, KUROSAWA Minoru, Shuto Yusuke, Sugahara Satoshi, Yamamoto Shuichiro
Принадлежит: JAPAN SCIENCE AND TECHNOLOGY AGENCY

A transistor includes: a piezoresistor through which carriers conduct; a source that injects the carriers into the piezoresistor; a drain that receives the carriers from the piezoresistor; a piezoelectric material that is located so as to surround the piezoresistor and applies a pressure to the piezoresistor; and a gate that applies a voltage to the piezoelectric material so that the piezoelectric material applies a pressure to the piezoresistor. 1. A transistor characterized by comprising:a piezoresistor through which carriers conduct;a source that injects the carriers into the piezoresistor;a drain that receives the carriers from the piezoresistor;a piezoelectric material that is located so as to surround the piezoresistor and applies a pressure to the piezoresistor; anda gate that applies a voltage to the piezoelectric material so that the piezoelectric material applies a pressure to the piezoresistor.2. The transistor of claim 1 , whereinthe gate is located so as to surround the piezoelectric material, andthe piezoelectric material is dielectrically polarized in a direction from the piezoresistor to the gate or in a direction from the gate to the piezoresistor.3. The transistor of claim 1 , whereina plurality of the gates are located in a direction parallel to a conduction direction of the carriers conducting through a channel in the piezoresistor, andthe piezoelectric material is dielectrically polarized in the direction parallel to the conduction direction.4. The transistor of claim 1 , whereinthe piezoelectric material is located so as to surround the piezoresistor in all directions perpendicular to a conduction direction of the carriers.5. The transistor of claim 1 , whereinthe piezoelectric material is located so as to partially surround the piezoresistor in directions perpendicular to a conduction direction of the carriers.6. The transistor of claim 1 , further comprising:a support that is formed on a substrate and supports the piezoresistor,wherein an ...

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Номер записи: 13
13-01-2022 дата публикации

METHOD OF FORMING MULTI-BIT RESISTIVE RANDOM ACCESS MEMORY CELL

Номер: US20220013718A1
Автор: YANG PO-YU
Принадлежит: UNITED MICROELECTRONICS CORP.

A multi-bit resistive random access memory cell includes a plurality of bottom electrodes, a plurality of dielectric layers, a top electrode and a resistance layer. The bottom electrodes and the dielectric layers are interleaved layers, each of the bottom electrodes is sandwiched by the dielectric layers, and a through hole penetrates through the interleaved layers. The top electrode is disposed in the through hole. The resistance layer is disposed on a sidewall of the through hole and is between the top electrode and the interleaved layers, thereby the top electrode, the resistance layer and the bottom electrodes constituting a multi-bit resistive random access memory cell. The present invention also provides a method of forming the multi-bit resistive random access memory cell. 1. A method of forming a multi-bit resistive random access memory cell , comprising:sequentially forming a first dielectric layer, a first bottom electrode, a second dielectric layer, a second bottom electrode, a third dielectric layer, a third bottom electrode and a fourth dielectric layer on a layer;performing a first etching process to pattern the fourth dielectric layer, the third bottom electrode, the third dielectric layer, the second bottom electrode, the second dielectric layer, the first bottom electrode and the first dielectric layer to forma through hole in the first dielectric layer, the first bottom electrode, the second dielectric layer, the second bottom electrode, the third dielectric layer, the third bottom electrode and the fourth dielectric layer; andforming a resistance layer conformally covering a sidewall of the through hole and filling a top electrode in the through hole, thereby the multi-bit resistive random access memory cell being formed.2. The method of forming the multi-bit resistive random access memory cell according to claim 1 , wherein the steps of forming the resistance layer conformally covering the sidewall of the through hole and filling the top ...

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Номер записи: 14
07-01-2016 дата публикации

SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR PRODUCING THE SAME

Номер: US20160005792A1
Автор: HASE Takashi, Ikarashi Nobuyuki, Kawahara Jun, TAKEUCHI Kiyoshi, Ueki Makoto
Принадлежит:

Provided is a semiconductor memory device (resistance random access memory element) improved in properties. A Ru film is formed as a film of a lower electrode by sputtering, and a Ta film is formed thereonto by sputtering. Next, the Ta film is oxidized with plasma to oxidize the Ta film. In this way, a compound TaOis produced and further Ru is diffused into the compound to form a layer (variable resistance layer) in which Ru is diffused into the compound TaO. Such an incorporation of a metal (such as Ru) into a transition metal oxide TMO (such as TaO) makes it possible to form electron conductive paths additional to filaments to lower the filaments in density and thickness. Thus, the memory element can be restrained from undergoing OFF-fixation, by which the element is not easily lowered in resistance, to be improved in ON-properties. 1. A semiconductor memory device , comprising:a first electrode;a second electrode; anda variable resistance layer arranged between the first and second electrodes;wherein the variable resistance layer comprises an oxide layer of a first metal, and a second metal contained in the oxide layer of the first metal,wherein the first metal is a transition metal; andwherein the second metal is a metal that produces an electronic level inside a band gap of the oxide layer of the first metal.2. The semiconductor memory device according to claim 1 ,{'sub': 2', '5', '2', '2, 'wherein the oxide layer of the first metal comprises at least one selected from the group consisting of TaO, ZrO, and HfO.'}3. The semiconductor memory device according to claim 2 ,wherein the second metal is selected from the group consisting of Ru, Re, Ir, Os, and Nb.4. The semiconductor memory device according to claim 3 ,wherein the content by percentage of the second metal is from 1 to 20% by atom of the first metal in the oxide layer of the first metal.5. The semiconductor memory device according to claim 1 ,wherein the variable resistance layer is over the first ...

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Номер записи: 15
07-01-2021 дата публикации

MEMORY DEVICE AND A METHOD FOR FORMING THE MEMORY DEVICE

Номер: US20210005251A1
Автор: TAN Juan Boon, Tan Shyue Seng, Toh Eng Huat, Wang Lanxiang
Принадлежит:

A memory device may include a substrate having conductivity regions and a channel region. A first voltage line may be arranged over the channel region. Second, third, and fourth voltage lines may each be electrically coupled to a conductivity region. Resistive units may be arranged between the third voltage line and the conductivity region electrically coupled to the third voltage line, and between the fourth voltage line and the conductivity region electrically coupled to the fourth voltage line. A resistance adjusting element may have at least a portion arranged between one of the resistive units and one of the conductivity regions. An amount of the resistance adjusting element between the first resistive unit and the conductivity region electrically coupled to the third voltage line may be different from that between the second resistive unit and the conductivity region electrically coupled to the fourth voltage line. 1. A memory device comprising:a substrate comprising a first conductivity region and a second conductivity region at least partially arranged within the substrate, and a channel region arranged between the first conductivity region and the second conductivity region;a first voltage line arranged over the channel region;a second voltage line electrically coupled to the first conductivity region;a third voltage line electrically coupled to one of the conductivity regions; anda fourth voltage line electrically coupled to one of the conductivity regions;a first resistive unit arranged between the third voltage line and the conductivity region to which the third voltage line is electrically coupled, and a second resistive unit arranged between the fourth voltage line and the conductivity region to which the fourth voltage line is electrically coupled;a resistance adjusting element having at least a portion arranged between one of the resistive units and one of the conductivity regions;wherein an amount of the resistance adjusting element between the ...

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Номер записи: 16
04-01-2018 дата публикации

METHOD FOR BASE CONTACT LAYOUT, SUCH AS FOR MEMORY

Номер: US20180006087A1
Автор: Capetti Gianfranco, Pellizzer Fabio, Rigano Antonino
Принадлежит:

Embodiments disclosed herein may relate to forming a base contact layout in a memory device. 1. A memory device , comprising:an array of memory cells comprising a plurality of electrodes individually comprising one or more base contact areas at a common depth, wherein a subset of the one or more base contact areas are electrically connected to a respective electrically conductive interconnect that provides an electrically conductive path to one or more selector transistors associated with one or more memory cells of the array.2. The memory device of claim 1 , wherein subsets of contact areas for electrodes of the plurality of electrodes are coupled with electrically conductive interconnects in a substantially alternating pattern.3. The memory device of claim 2 , wherein the substantially alternating pattern comprises a contact area of an electrode being coupled with the respective electrically conductive interconnect if a corresponding contact area of an immediately adjacent electrode is not coupled with an electrically conductive interconnect.4. The memory device of claim 3 , wherein the one or more selector transistors comprise one or more bipolar junction transistors claim 3 , and wherein the respective electrically conductive interconnect comprises an electrically conductive interconnect coupled between the contact area and a component of the one or more bipolar junction transistors.5. The memory device of claim 1 , wherein the array of memory cells comprises an array of phase change memory cells.6. The memory device of claim 1 , wherein the array of memory cells comprises a chalcogenide material.7. The memory device of claim 1 , wherein the plurality of electrodes comprise a plurality of word-line electrodes.8. The memory device of claim 1 , wherein the plurality of electrodes comprise a plurality of bit-line electrodes.9. A memory device claim 1 , comprising a plurality of word-line interconnect portions extending in a first direction claim 1 , each word-line ...

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Номер записи: 17
07-01-2021 дата публикации

RESISTIVE MEMORY ARCHITECTURES WITH MULTIPLE MEMORY CELLS PER ACCESS DEVICE

Номер: US20210005811A1
Автор: Liu Jun, Violette Michael P.
Принадлежит:

A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices. 1. An apparatus , comprising:an access device comprising a gate and a drain;a dielectric that contacts at least a portion of the gate of the access device and at least a portion of the drain of the access device;a via extending through the dielectric and through at least a portion of the drain of the access device; anda deposited layer of material positioned within the via.2. The apparatus of claim 1 , further comprising:one or more tungsten contacts positioned in the via and in contact with the deposited layer of material.3. The apparatus of claim 1 , further comprising:one or more platinum contacts positioned in the via and in contact with the deposited layer of material.4. The apparatus of claim 1 , wherein the deposited layer of material comprises titanium silicide claim 1 , titanium nitride claim 1 , or a combination thereof.5. The apparatus of claim 1 , wherein the deposited layer of material comprises platinum claim 1 , or platinum silicide claim 1 , or a combination thereof.6. The apparatus of claim 1 , further comprising:a word line in contact with the gate of the access device and the drain of the access device.7. The apparatus of claim 1 , wherein a bottom of the via is p-doped or n-doped.8. A memory device claim 1 , comprising:a first memory cell;an access device comprising a gate and a drain and operatively coupled with the first memory cell; and a dielectric that contacts at least a portion of the gate of the access device and at least a portion of the drain of the access device;', 'a via extending through the dielectric and through at ...

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Номер записи: 18
02-01-2020 дата публикации

CIRCUIT AND LAYOUT FOR RESISTIVE RANDOM-ACCESS MEMORY ARRAYS HAVING TWO BIT LINES PER COLUMN

Номер: US20200006429A1
Автор: McCollum John L.
Принадлежит: Microsemi SoC Corp.

A layout is presented for a ReRAM memory cell array including rows and columns of ReRAM cells, each ReRAM cell is in a row and column of ReRAM cells. Each ReRAM cell includes a ReRAM device. A first transistor is coupled between the ReRAM device and a first bit line associated with the column containing the ReRAM cell. The first transistor has a gate coupled to a first word line associated with the row containing the ReRAM cell. A second transistor is coupled between the ReRAM device and a second bit line associated with the column containing the ReRAM cell. The second transistor has a gate coupled to a second word line associated with the row containing the ReRAM cell. 1. A layout for a ReRAM memory array including rows and columns of ReRAM cells , each ReRAM cell in a row and column of ReRAM cells comprising:a ReRAM device;a first FinFET transistor coupled between the ReRAM device and a first bit line associated with the column containing the ReRAM cell, the first FinFET transistor having a gate coupled to a first word line associated with the row containing the ReRAM cell;a second FinFET transistor coupled between the ReRAM device and a second bit line associated with the column containing the ReRAM cell, the second FinFET transistor having a gate coupled to a second word line associated with the row containing the ReRAM cell;wherein each column includes a first group of fins and a second group of fins separate from the first group of fins;the first FinFET transistor for each memory cell in every column of the array is formed on the first group of fins associated with that column; andthe second FinFET transistor for each memory cell in every column of the array is formed on the second group of fins associated with that column.2. The ReRAM memory array of further including a sense amplifier for each column of the array claim 1 , the sense amplifier for each column in the array coupled to one of the first and second bit lines associated with its column in the array ...

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Номер записи: 19
02-01-2020 дата публикации

CIRCUIT AND LAYOUT FOR RESISTIVE RANDOM-ACCESS MEMORY ARRAYS

Номер: US20200006430A1
Автор: McCollum John L
Принадлежит: Microsemi SoC Corp.

A ReRAM memory array includes rows and columns of ReRAM cells. Each ReRAM cell in a row and column of the array includes a ReRAM device having an ion source end coupled to a bias line associated with the row of the array containing the ReRAM device. A first transistor is coupled between the solid electrolyte end of the ReRAM device and a bit line associated with the column of the array containing the ReRAM cell. The first transistor has a gate coupled to a first word line associated with the row containing the ReRAM cell. A second transistor is coupled between the solid electrolyte end of the ReRAM device and the bit line associated with the column of the array containing the ReRAM cell. The second transistor has a gate coupled to a second word line associated with the row containing the ReRAM cell. 1. A ReRAM memory array including rows and columns of ReRAM cells , each ReRAM cell in a row and column of ReRAM cells comprising:a ReRAM device having an ion source end and a solid electrolyte end, the ion source end coupled to a bias line associated with the row of the array containing the ReRAM device;a first n-channel transistor coupled between the solid electrolyte end of the ReRAM device and a bit line associated with the column of the array containing the ReRAM cell, the first n-channel transistor having a gate coupled to a first word line associated with the row containing the ReRAM cell; anda second n-channel transistor coupled between the solid electrolyte end of the ReRAM device and the bit line associated with the column of the array containing the ReRAM cell, the second n-channel transistor having a gate coupled to a second word line associated with the row containing the ReRAM cell;wherein the first word line and the second word line associated with the row containing the memory cell are electrically connected together.2. The ReRAM memory array of further including a sense amplifier coupled to the bit line for each column in the array.3. The ReRAM memory ...

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Номер записи: 20
03-01-2019 дата публикации

THREE-DIMENSIONAL RERAM MEMORY DEVICE EMPLOYING REPLACEMENT WORD LINES AND METHODS OF MAKING THE SAME

Номер: US20190006418A1
Автор: MUSHIGA Mitsuteru, Nishida Akio, Pham Tuan, Sel Jongsun, SHIH Vincent
Принадлежит:

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, resistive memory elements located in the alternating stack in first and second array regions and contact via structures located in a contact region between the first and the second array regions. The contact via structures have different depths and contact different electrically conductive layers. Support pillars are located in the contact region and extending through the alternating stack. At least one conduction channel area is located between the contact via structures in the contact region. The conduction channel area contains no support pillars, and all electrically conductive layers in the conduction channel area are continuous from the first array region to the second array region. 1. A three-dimensional memory device , comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;resistive memory elements located in the alternating stack in first and second array regions;contact via structures located in a contact region between the first and the second array regions, wherein the contact via structures have different depths and contact different electrically conductive layers;support pillars located in the contact region and extending through the alternating stack; andat least one conduction channel area located between the contact via structures in the contact region, wherein the conduction channel area contains no support pillars, and all electrically conductive layers in the conduction channel area are continuous from the first array region to the second array region.2. The three-dimensional memory device of claim 1 , wherein:the three-dimensional memory device comprises a ReRAM memory device;the electrically conductive layers comprise word lines of the ReRAM memory device;the first array region comprises a first memory plane;the second array region comprises a ...

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Номер записи: 21
03-01-2019 дата публикации

SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME

Номер: US20190006419A1
Автор: ARAI Fumitaka, Kiyotoshi Masahiro, Ozawa Yoshio, Shirota Riichiro, Yamamoto Akihito
Принадлежит: Toshiba Memory Corporation

A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode. 1. A semiconductor memory comprising:a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate;a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate;a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate; andwherein the layers are patterned in self-alignment with each other,intersections of the active areas and the first gate electrode form a plurality of memory cells, andthe plurality of memory cells in an intersecting plane share the first gate electrode.2. The memory according to claim 1 , wherein the first and second gate electrodes are formed by one layer.3. The memory according to claim 1 , wherein the first and second gate electrodes are connected to interconnections and driven independently of each other.4. The memory according to claim 1 , wherein the second gate electrode is formed parallel to the active areas claim 1 , and shared by the plurality of memory cells in a plane parallel to the active areas and perpendicular to the substrate.5. The memory according to claim 1 , wherein a ...

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Номер записи: 22
02-01-2020 дата публикации

COMPACT RESISTIVE RANDOM ACCESS MEMORY INTEGRATED WITH A PASS GATE TRANSISTOR

Номер: US20200006656A1
Автор: Leobandung Effendi
Принадлежит:

A method of forming a resistive random access memory (ReRAM) device is provided. The method includes depositing a lower cap layer on a substrate, depositing a dielectric memory layer on the lower cap layer, and depositing an upper cap layer on the dielectric memory layer. The method further includes removing portions of the lower cap layer to form a lower cap slab, dielectric memory layer to form a dielectric memory slab on the lower cap slab, and upper cap layer to form an upper cap slab on the dielectric memory slab, wherein the lower cap slab, dielectric memory slab, and upper cap slab form a resistive memory element. 1. A method of forming a resistive random access memory (ReRAM) device , comprising:depositing a lower cap layer directly on a source/drain contact, wherein the source/drain contact is in direct contact with a source/drain on a substrate;depositing a dielectric memory layer on the lower cap layer;depositing an upper cap layer on the dielectric memory layer;forming a resistive element template on the upper cap layer;removing portions of the lower cap layer to form a lower cap slab, dielectric memory layer to form a dielectric memory slab on the lower cap slab, and upper cap layer to form an upper cap slab on the dielectric memory slab, exposed by the resistive element template, wherein the lower cap slab, dielectric memory slab, and upper cap slab form a resistive memory element; andforming a protective liner on the resistive element template and resistive memory element.2. The method of claim 1 , wherein the lower cap layer and upper cap layer each have a thickness in a range of about 2 nanometers (nm) to about 50 nm.3. The method of claim 1 , wherein the dielectric memory layer has a thickness in a range of about 2 nm to about 15 nm.4. The method of claim 1 , further comprising forming a field effect transistor device on the substrate claim 1 , wherein the field effect transistor device includes the source/drain claim 1 , and wherein the resistive ...

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Номер записи: 23
27-01-2022 дата публикации

LOGIC DRIVE USING STANDARD COMMODITY PROGRAMMABLE LOGIC IC CHIPS COMPRISING NON-VOLATILE RANDOM ACCESS MEMORY CELLS

Номер: US20220029626A1
Автор: Lee Jin-Yuan, Lin Mou-Shiung
Принадлежит:

A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64. 1. A chip package comprising:a non-volatile memory cell configured to store resulting data of a look-up table (LUT) therein;a sense amplifier configured to sense input data thereof associated with the resulting data of the look-up table (LUT) stored in the non-volatile memory cell to generate output data of the sense amplifier;a logic circuit comprising a static-random-access-memory (SRAM) cell configured to store first data therein associated with the output data of the sense amplifier, and a selection circuit comprising a first set of input points for a first input data set for input data of a logic operation and a second set of input points for a second input data set having second data associated with the first data stored in the static-random-access-memory (SRAM) cell, wherein the selection circuit is configured to select, in accordance with the first input data set, input data from the second input data set as output data of the logic operation; anda plurality of metal bumps at a bottom of the chip package, wherein the plurality of metal bumps comprise five metal bumps arranged in a line.2. The chip package of claim 1 , wherein the sense amplifier and logic circuit are provided by a ...

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Номер записи: 24
11-01-2018 дата публикации

RRAM CELL WITH PMOS ACCESS TRANSISTOR

Номер: US20180012657A1
Автор: CHANG Chih-Yang, Chen Hsia-Wei, Chu Wen-Ting, Liao Yu-Wen, Shih Sheng-Hung, Tu Kuo-Chi, Yang Chin-Chieh, Yang Jen-Sheng
Принадлежит:

In some embodiments, the present disclosure relates to a method of operating an RRAM cell having a PMOS access transistor. The method may be performed by turning on a PMOS transistor having a drain terminal coupled to a lower electrode of an RRAM device. A first voltage is provided to a source terminal of the PMOS transistor, and a second voltage is provided to a bulk terminal of the PMOS transistor. The second voltage is larger than the first voltage. A third voltage is provided to an upper electrode of the RRAM device. The third voltage is larger than the first voltage. 1. A method of operating a resistive random access memory (RRAM) cell , comprising:turning on a PMOS transistor having a drain terminal coupled to a lower electrode of an RRAM device;providing a first voltage to a source terminal of the PMOS transistor;providing a second voltage to a bulk terminal of the PMOS transistor, wherein the second voltage is larger than the first voltage; andproviding a third voltage to an upper electrode of the RRAM device, wherein the third voltage is larger than the first voltage.2. The method of claim 1 , wherein the first voltage has a value that is substantially equal to zero.3. The method of claim 1 , wherein the third voltage is larger than the second voltage.4. The method of claim 1 , wherein the second voltage is larger than a drain voltage at the drain terminal of the PMOS transistor.5. The method of claim 1 , wherein providing the third voltage to the upper electrode causes an initial conductive filament to be formed within the RRAM device.6. The method of claim 5 , further comprising:performing a reset operation by turning on the PMOS transistor while providing a non- zero reset voltage to the bulk terminal.7. The method of claim 1 , wherein providing the third voltage to the upper electrode causes a conductive filament to be reformed within the RRAM device.8. The method of claim 1 , wherein the third voltage is more than twice as large as the second voltage.9 ...

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Номер записи: 25
11-01-2018 дата публикации

RESISTIVE MEMORY CELL HAVING A COMPACT STRUCTURE

Номер: US20180012935A1
Автор: Boivin Philippe, JEANNOT Simon
Принадлежит:

The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material. 1. A memory cell comprising:a selection transistor having a control gate and a first conduction terminal; a semiconductor substrate,', 'a first insulating layer covering the semiconductor substrate, and', 'a semiconductor active layer covering the insulating layer, the control gate being formed on the active layer and having a lateral flank,, 'a variable-resistance element connected to the first conduction terminal, the selection transistor and variable-resistance element being formed in a wafer that includesa second insulating layer covering the lateral flank of the control gate,a first trench formed through the active layer at a lateral flank of the active layer, along the lateral flank of the gate, and reaching the first insulating layer, wherein the variable-resistance element includes a layer of variable-resistance material positioned in the first trench along the lateral flank of the active layer, anda trench conductor formed in the first trench and against a lateral flank of the layer of variable-resistance material along the lateral flank of the active layer.2. The memory cell according to claim 1 , comprising adjacent trench isolations claim 1 , in which ...

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Номер записи: 26
11-01-2018 дата публикации

ELECTRONIC DEVICE

Номер: US20180012936A1
Автор: Kang Hee-Sung
Принадлежит:

An electronic device is provided to comprise a semiconductor memory unit that comprises: a substrate including active regions, which are extended in a second direction and disposed from each other in a first direction; a plurality of gates extended in the first direction and across with the active regions; a lower contact disposed in both sides of gates and coupling the active regions in the first direction; an upper contact of the lower contact overlapping with the active region out of the active regions in a side of each gate, and overlapping with the active regions in the other side of each gate; and first and second interconnection lines coupled to the upper contact, extended in the second direction, and being alternately disposed from each other in the first direction, wherein the upper contact of a side of the gates has a zigzag shape in a first oblique direction. 120-. (canceled)21. An electronic device comprising a semiconductor memory unit that comprises:a plurality of memory cells;a mat region having N number of first interconnection lines coupled to terminals of the plurality of memory cells; anda switching region for controlling a coupling between each of the N number of first interconnection lines and an external region,wherein the switching region comprises:a substrate having N number of second active regions, which are extended in a second direction and are disposed from each other in a first direction across the second direction;N number of second gates extended in the first direction and across the N number of second active regions;a second lower contact disposed in both sides of each of the N number of second gates and coupling the N number of second active regions in the first direction;a second upper contact overlapping with a corresponding second active region out of the N number of second active regions in a side of each of the N number second gates, and disposed to have a zigzag shape in a first oblique direction;a third upper contact ...

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Номер записи: 27
11-01-2018 дата публикации

Two-Terminal Switching Devices Comprising Coated Nanotube Elements

Номер: US20180013084A1
Автор: Ghenciu Eliodor G., Kocab J. Thomas, Rueckes Thomas, Yao Thierry
Принадлежит:

An improved switching material for forming a composite article over a substrate is disclosed. A first volume of nanotubes is combined with a second volume of nanoscopic particles in a predefined ration relative to the first volume of nanotubes to form a mixture. This mixture can then be deposited over a substrate as a relatively thick composite article via a spin coating process. The composite article may possess improved switching properties over that of a nanotube-only switching article. A method for forming substantially uniform nanoscopic particles of carbon, which contains one or more allotropes of carbon, is also disclosed. 1. A two-terminal switching device comprising:a first electrode;a second electrode; anda switching composite article disposed between and in constant electrical communication with each of said first electrode and said second electrode of said two terminal switching device, wherein said composite article is comprised of comprises a plurality of nanotube elements and a volume of nanoscopic particles;wherein said volume of nanoscopic particles is miscible with said plurality of nanotube elements and forms a continuous material around at least one of said nanotube elements.2. The two-terminal switching device of wherein substantially all of said nanotube elements are coated in a continuous material formed from said nanoscopic particles.3. The two-terminal switching device of wherein said continuous material coating increases the distance between said nanotube elements within said composite article.4. The two-terminal switching device of wherein said continuous material coating improves the switching functionality of said two-terminal switching device.5. The two-terminal switching device of wherein said volume of nanoscopic particles includes silicon oxide particles.6. The two-terminal switching device of wherein said volume of nanoscopic particles includes silicon nitride particles.7. The two-terminal switching device of wherein said nanotube ...

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Номер записи: 28
10-01-2019 дата публикации

INTERCONNECTION FOR MEMORY ELECTRODES

Номер: US20190013052A1
Автор: Castro Hernan A., Flores Everardo Torres, Tang Stephen H.S.
Принадлежит:

Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level. 1. (canceled)2. An apparatus , comprising:a first access line and a second access line extending in a same direction, wherein at least a portion of the first access line extends beyond a portion of the second access line, and wherein the first access line comprises a first jog segment and the second access line comprises a second jog segment; anda connector coupled with the first jog segment, or the second jog segment, or both.3. The apparatus of claim 2 , further comprising:a socket region comprising a first socket coupled with the first access line and a second socket coupled with the second access line, wherein the first access line extends beyond a boundary of the socket region, and wherein the second access line is located entirely within the boundary of the socket region.4. The apparatus of claim 2 , wherein a distance between the first jog segment and the second jog segment is greater than a distance between another portion of the first access line and another portion of the second access line.5. The apparatus of claim 2 , further comprising:a third access line extending in a different direction than the first access line and the second access line, wherein at least a portion of the third access line intersects at least a portion of the first access line, at least a portion of the second access line, or both.6. The apparatus of claim 2 , wherein the first access line and the second access line are formed at a first vertical level of a stack.7. The apparatus of claim 6 , further comprising:a second vertical level of the stack comprising a fourth access line and a fifth access line extending in a second direction.8. ...

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Номер записи: 29
10-01-2019 дата публикации

MEMORY DEVICE ARCHITECTURE

Номер: US20190013068A1
Автор: Castro Hernan A., Flores Everardo Torres, Hirst Jeremy M.
Принадлежит:

Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array. 1. A method , comprising:forming a memory array of memory cells occupying a footprint; andforming a plurality of word line drivers in a circuit level, the plurality of word line drivers within the footprint of the memory array; andforming a plurality of digit line drivers in the circuit level, the plurality of digit line drivers within the footprint of the memory array,wherein the circuit level comprises a plurality of word line driver connection points and digit line driver connection points distributed across the footprint.2. The method of claim 1 , further comprising:forming a plurality of word lines each coupled with and laterally traversing at least one of the plurality of word line drivers at a different vertical level from the plurality of word line drivers.3. The method of claim 2 , wherein each word line driver connection point of the plurality of word line driver connection points is centered along a word line direction within a word line driver region of a plurality of word line driver regions.4. The method of claim 1 , further comprising:forming a plurality of digit lines each coupled with and laterally traversing at least one of the plurality of digit line drivers at a different vertical level from the plurality of digit line drivers.5. The method of claim 4 , wherein each of the digit line driver connection points is centered along a digit line direction within a digit line driver region of a plurality of digit line driver regions.6. The method of claim 1 , wherein at least two word line drivers of the plurality of word line drivers are positioned along a first direction and at least two digit line drivers of the plurality of digit line drivers are positioned along a second direction orthogonal to the first direction.7. The method of claim 1 , wherein the memory array of memory cells comprises two word lines positioned ...

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Номер записи: 30
10-01-2019 дата публикации

MEMORY DEVICE ARCHITECTURE

Номер: US20190013069A1
Автор: Castro Hernan A., Flores Everardo Torres, Hirst Jeremy M.
Принадлежит:

Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array. 1. A device , comprising:a plurality of memory cells within a footprint of the device; anda plurality of word line drivers and digit line drivers in a circuit level positioned below the plurality of memory cells, wherein the circuit level comprises a plurality of word line driver connection points and digit line driver connection points within the footprint.2. The device of claim 1 , wherein the plurality of word line drivers are distributed across and within the footprint in a plurality of word line driver regions claim 1 , and wherein the plurality of digit line drivers are distributed across and within the footprint in a plurality of digit line driver regions.3. The device of claim 2 , wherein word line electrodes connecting the plurality of word line drivers to the plurality of memory cells of the device are staggered relative to one another by shifting the word line electrodes relative to one another along their axis of elongation.4. The device of claim 3 , wherein digit line electrodes connecting the plurality of digit line drivers to the plurality of memory cells of the device are staggered relative to one another by shifting the digit line electrodes relative to one another along their axis of elongation.5. The device of claim 1 , wherein the plurality of memory cells comprises word lines positioned along a first direction and digit lines positioned along a second direction different from the first direction.6. The device of claim 1 , further comprising:a plurality of word lines each coupled with at least one of the plurality of word line drivers at a different vertical level from the plurality of word line drivers.7. The device of claim 6 , wherein each word line driver connection point of the plurality of word line driver connection points is positioned along a word line direction within a word line driver region of a ...

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Номер записи: 31
14-01-2021 дата публикации

RESISTIVE RANDOM ACCESS MEMORY AND RESETTING METHOD THEREOF

Номер: US20210012839A1
Автор: Chen Yu-Ting, Liao Shao-Ching, Lin Ming-Che, Liu Chi-Ching, Pai Chang-Tsung, Wang Ping-Kun
Принадлежит: WINBOND ELECTRONICS CORP.

Provided is a resistive random access memory (RRAM) including at least one memory cell. The at least one memory cell includes a top electrode, a bottom electrode, a data storage layer, an oxygen gettering layer, a first barrier layer, and an oxygen supplying layer. The data storage layer is disposed between the top electrode and the bottom electrode. The oxygen gettering layer is disposed between the data storage layer and the top electrode. The first barrier layer is disposed between the oxygen gettering layer and the data storage layer. The oxygen supplying layer is disposed between the oxygen gettering layer and the top electrode and/or between the oxygen gettering layer and the first barrier layer. 1. A resistive random access memory (RRAM) , comprising at least one memory cell , the at least one memory cell comprising:a data storage layer, disposed between an upper electrode and a lower electrode;an oxygen gettering layer, disposed between the data storage layer and the upper electrode;a first barrier layer, disposed between the oxygen gettering layer and the data storage layer; anda first oxygen supplying layer, disposed between the oxygen gettering layer and the upper electrode.2. The RRAM according to claim 1 , wherein an oxygen content of the first oxygen supplying layer decreases along a direction from close to the oxygen gettering layer to away from the oxygen gettering layer.3. The RRAM according to claim 1 , further comprising a second barrier layer disposed between the oxygen gettering layer and the upper electrode.4. The RRAM according to claim 3 , wherein the first oxygen supplying layer comprises:a first region directly contacting the oxygen gettering layer;a second region directly contacting the second barrier layer; anda third region located between the first region and the second region, and an oxygen content of the first region greater than an oxygen content of the second region.5. The RRAM according to claim 3 , further comprising a second ...

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Номер записи: 32
10-01-2019 дата публикации

RECONFIGURABLE CIRCUIT, RECONFIGURABLE CIRCUIT SYSTEM, AND METHOD FOR OPERATING RECONFIGURABLE CIRCUIT

Номер: US20190013811A1
Автор: BAI Xu, Miyamura Makoto, Nebashi Ryusuke, Sakamoto Toshitsugu, TADA Ayuka, TSUJI Yukihide
Принадлежит: NEC Corporation

The purpose of the present invention is to increase the efficiency with which silicon on a chip is used, and to easily reduce the size of a logic cell. To accomplish the purpose, this reconfigurable circuit includes: a logic memory unit configured from a resistance change element, and positioned distributed into at least two units; a logic unit for referencing the logic memory unit and performing logical operations; and a signal path switching unit for receiving the results of the logical operation of the logic unit and outputting said results to the outside. The logic memory part and the signal path switching part constitute part of a crossbar switching circuit, and share write wiring to the resistance change element. 1. A reconfigurable circuit comprising:a logic memory unit that includes a resistance change element and is disposed by distribution into at least two units;a logic unit that refers to the logic memory unit and executes a logical operation; anda signal path switching unit that receives a result of a logical operation of the logic unit and outputs the result to an outside,the logic memory unit and the signal path switching unit that configures a crossbar switch circuit and shares write wiring to the resistance change element.2. The reconfigurable circuit according to claim 1 , wherein the logic unit is disposed by distribution into at least 2 units and each of the logic units disposed by distribution is connected to the associated logic memory unit.3. The reconfigurable circuit according to claim 2 , whereinthe crossbar switch circuit further includes a signal switching unit that outputs a control signal to the logic unit, andthe logic unit closest to the signal switching unit executes a logical operation among the logic units disposed by distribution into at least two units.4. The reconfigurable circuit according to claim 1 , wherein the logic unit and the signal path switching unit are adjacently disposed.5. The reconfigurable circuit according to ...

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Номер записи: 33
09-01-2020 дата публикации

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME

Номер: US20200013668A1
Автор: Choi Byoungdeog, Chung Hyun-Woo, Han Sangyeon, Hwang Yoosang, KIM HONGRAE, SEO JungWoo
Принадлежит:

A semiconductor device includes bit line structures on a substrate, the bit line structures extending along a first direction and being spaced apart from each other along a second direction perpendicular to the first direction, contact plugs spaced apart from each other along the first direction and being on active regions of the substrate between adjacent bit line structures, a linear spacer on each longitudinal sidewall of a bit line structure, landing pads on the contact plugs, respectively, the landing pads being electrically connected to the contact plugs, respectively, and landing pads that are adjacent to each other along the first direction being offset with respect to each other along the second direction, as viewed in a top view, a conductive pad between each of the contact plugs and a corresponding active region, a vertical axes of the conductive pad and corresponding active region being horizontally offset. 1. A semiconductor device , comprising:a plurality of bit line structures on a substrate, the plurality of bit line structures extending along a first direction and being spaced apart from each other along a second direction perpendicular to the first direction, and each of the bit line structures including a bit line and a hard mask pattern;a plurality of contact plugs spaced apart from each other along the first direction, the plurality of contact plugs being on active regions of the substrate between adjacent ones of plurality of bit line structures;a linear spacer on each longitudinal sidewall of a bit line structure of the plurality of bit line structures, the linear spacer being between the bit line structure of the plurality of bit line structures and the plurality of contact plugs;a plurality of landing pads on the plurality of contact plugs, respectively, the plurality of landing pads being electrically connected to the plurality of contact plugs, respectively, and landing pads of the plurality of landing pads that are adjacent to each other ...

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Номер записи: 34
14-01-2021 дата публикации

RESISTIVE SWITCHING NONVOLATILE RANDOM ACCESS MEMORY DEVICE

Номер: US20210013405A1
Автор: LIM JU DY, SEET CHIM SENG, WONG DAO HWEE GRAYSON, Yamane Kazutaka, ZENG DINGGUI
Принадлежит:

The disclosure relates generally to resistive switching nonvolatile random access memory (ReRAM) devices, and more generally to structures and methods of fabricating multiple conductive elements in ReRAM devices. A resistive memory device is presented, the device comprising a first electrode having a first work function, and a second electrode having a second work function, the first work function being different from the second work function. A dielectric layer is disposed between the first and second electrodes. The device further comprises a set of nanocrystal structures distributed in the dielectric layer. A conductive layer is also disposed in the dielectric layer. 1. A resistive memory device comprising:a first electrode having a first work function;a second electrode having a second work function, wherein the first work function is different from the second work function;a dielectric layer disposed between the first and second electrodes;a set of nanocrystal structures distributed in the dielectric layer; anda conductive layer disposed in the dielectric layer.2. The resistive memory device of claim 1 , wherein the set of nanocrystal structures is a first set of nanocrystal structures and the conductive layer is a second set of nanocrystal structures.3. The resistive memory device of claim 1 , wherein the conductive layer is a metal layer.4. The resistive memory device of further comprising a third set of nanocrystal structures distributed in the dielectric layer.5. The resistive memory device of further comprising a metal layer disposed in the dielectric layer.6. The resistive memory device of claim 3 , further comprising a second metal layer disposed in the dielectric layer.7. The resistive memory device of further comprising:a fourth set of nanocrystal structures distributed in the dielectric layer anda fifth set of nanocrystal structures distributed in the dielectric layer;wherein the first and fifth sets of nanocrystal structures have at least one ...

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Номер записи: 35
14-01-2021 дата публикации

NON-VOLATILE MEMORY ELEMENTS WITH FILAMENT CONFINEMENT

Номер: US20210013406A1
Автор: LIU BIN, Loy Desmond Jia Jun, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

Structures for a non-volatile memory and methods of forming and using such structures. A resistive memory element includes a first electrode, a second electrode, and a switching layer arranged between the first electrode and the second electrode. A transistor includes a drain coupled with the second electrode. The switching layer has a top surface, and the first electrode is arranged on a first portion of the top surface of the switching layer. A hardmask, which is composed of a dielectric material, is arranged on a second portion of the top surface of the switching layer. 1. A method comprising:depositing a layer stack including a first electrode and a switching layer on the first electrode;forming a hardmask covering a first portion of a top surface of the switching layer;forming a second electrode on a second portion of the top surface of the switching layer at an outer side surface of the hardmask; andafter forming the second electrode, patterning the first electrode and the switching layer,wherein the first electrode, the second electrode, and the switching layer provide a first resistive memory element.2. The method of wherein forming the second electrode on the second portion of the top surface of the switching layer at the outer side surface of the hardmask comprises:conformally depositing an electrode layer over the hardmask and the second portion of the top surface of the switching layer; andetching the electrode layer to form the second electrode.3. The method of further comprising:forming a sidewall spacer arranged to surround the second electrode,wherein the sidewall spacer comprised of a dielectric material.4. The method of wherein the sidewall spacer is arranged on a third portion of the top surface of the switching layer.5. The method of wherein the hardmask claim 4 , the first electrode claim 4 , and the sidewall spacer cover substantially all of the top surface of the switching layer after the first electrode and the switching layer are patterned.6 ...

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Номер записи: 36
09-01-2020 дата публикации

FRONT TO BACK RESISTIVE RANDOM-ACCESS MEMORY CELLS

Номер: US20200013952A1
Автор: Greene Jonathan, Hawley Frank, McCollum John
Принадлежит: Microsemi SoC Corp.

A resistive random-access memory device formed on a semiconductor substrate includes a first interlayer dielectric formed over the semiconductor substrate and includes a first via. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A lower metal layer formed in the first via has a top surface extending above a top surface of the chemical-mechanical-polishing stop layer. A dielectric layer is formed over the chemical-mechanical-polishing stop layer and is in electrical contact with the lower metal layer. A barrier metal layer is formed over the dielectric layer. Edges of the dielectric layer and the first barrier metal layer extend beyond outer edges of the first via. A second interlayer dielectric layer including a second via is formed over the dielectric layer. An upper metal layer formed in the second via in electrical contact with the barrier metal layer. 1. A resistive random-access memory device formed on a semiconductor substrate and comprising:a first interlayer dielectric formed on the semiconductor substrate and having a first via formed therethrough;a chemical-mechanical-polishing stop layer formed over the first interlayer dielectric, the first via formed through the chemical-mechanical-polishing stop layer;a lower metal layer formed in the first via, the lower metal layer serving as an ion source, a top surface of the lower metal layer extending above a top surface of the chemical-mechanical-polishing stop layer;a dielectric layer formed over the lower metal layer in the first via and extending over the chemical-mechanical-polishing stop layer;a barrier metal layer formed over the dielectric layer;edges of the barrier metal layer and the dielectric layer extending beyond outer edges of the first via;a second interlayer dielectric formed over the barrier metal layer, the second interlayer dielectric including a second via formed therethrough communicating with the barrier metal layer; andan upper metal layer formed in the ...

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Номер записи: 37
03-02-2022 дата публикации

Memory cell array circuit and method of forming the same

Номер: US20220035981A1
Автор: Chi-Hsiang Weng, Yu-Der Chih
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A memory cell array includes a first and a second column of memory cells, a first and a second bit line, a source line and a first set of vias. The first or second bit line includes a first conductive line located on a first metal layer, and a second conductive line located on a second metal layer. The first and second conductive lines overlap a source of a transistor of a memory cell of the first column or second column of memory cells. The source line is coupled to the first and second column of memory cells. The first set of vias is electrically coupled to the first and second conductive line. A pair of vias of the first set of vias is located above where the first conductive line overlaps each memory cell of the first or second column of memory cells.

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Номер записи: 38
18-01-2018 дата публикации

DYNAMIC LOGIC MEMCAP

Номер: US20180017870A1
Автор: GE NING, Li Zhiyong, Williams R. Stanley, Yang Jianhua
Принадлежит: Hewlett-Packard Development Company, L.P.

An integrated circuit may include a substrate with a plurality of transistors formed in the substrate. The plurality of transistors may be coupled to a first metal layer formed over the plurality of transistors. A plurality of high dielectric nanometer capacitors may be formed of memristor switch material between the first metal layer and a second metal layer formed over the plurality of high dielectric capacitors. The plurality of high dielectric capacitors may operate as memory storage cells in dynamic logic. 1. An integrated circuit , comprising:a substrate with a plurality of transistors formed in the substrate, the plurality of transistors coupled to a first metal layer formed over the plurality of transistors; anda plurality of high dielectric nanometer capacitors formed of memristor switch material creating an active region between the first metal layer and a second metal layer formed over the plurality of high dielectric memcaps, wherein the plurality of high dielectric memcaps are to operate as memory storage cells in dynamic logic.2. The integrated circuit of claim 1 , wherein the memristor switch material is formed of memristor switch oxide of the first metal layer and additionally operational as memristors.3. The integrated circuit of wherein the memristor switch material active region is formed of memristor switch elemental or compound semiconductor and doped with mobile dopants to allow for memristor operation.4. The integrated circuit of claim 2 , further comprising a second plurality of transistors coupled between respective plurality of high dielectric nanometer memcaps and a programming source to allow for programming the memristors.5. The integrated circuit of wherein the dynamic logic is to operate as a set of shift registers.6. The integrated circuit of wherein the set of shift registers is to control a set of fluid jet resistors.7. The integrated circuit of wherein the set of shift registers have set/reset functionality by programming the ...

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Номер записи: 39
21-01-2016 дата публикации

ASYMMETRICAL MEMRISTOR

Номер: US20160019453A1
Автор: HILLER Lars, HOERSELMANN Ingo, HUSAR Peter, KLEFENZ Frank, SCHOBER Andreas, SCHUMANN Lars, WILLIAMSON Adam
Принадлежит:

Embodiments of the present invention provide a memristor having a first electrode, a second electrode and a memristive layer arranged between the first electrode and the second electrode. Thereby, the memristor is adapted to obtain an asymmetrical current density distribution in the memristive layer.

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Номер записи: 40
21-01-2016 дата публикации

ELECTRONIC DEVICE

Номер: US20160019956A1
Автор: CHUNG Sung-Woong, Song Seok-Pyo, YI Jae-Yun
Принадлежит:

This patent document relates to memory circuits or devices and their applications in electronic devices or systems. The disclosed technology in this patent document includes memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device in which an electronic device capable of reducing an area, improving device characteristics due to a reduction in the resistance of a switching transistor, simplifying the process, and reducing a cost is provided. In accordance with the electronic device of this patent document, an area can be reduced, device characteristics can be improved due to a reduction in the resistance of the switching transistor, the process can be simplified, and a cost can be reduced.

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Номер записи: 41
21-01-2016 дата публикации

EMBEDDED NON-VOLATILE MEMORY

Номер: US20160020253A1
Автор: APODACA Mac D., HSU James Juen, SHEPARD Daniel R., TRENT Thomas Michael
Принадлежит:

The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F.sup.2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.

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Номер записи: 42
21-01-2016 дата публикации

MEMORY HOLE BIT LINE STRUCTURES

Номер: US20160020255A1
Автор: Petti Christopher, Ratnam Perumal, Yan Tianhong
Принадлежит: SanDisk 3D LLC

Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.

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Номер записи: 43
18-01-2018 дата публикации

TOP ELECTRODE FOR DEVICE STRUCTURES IN INTERCONNECT

Номер: US20180019390A1
Автор: CHANG Chih-Yang, Chen Hsia-Wei, Chu Wen-Ting, Liao Yu-Wen, Shih Sheng-Hung, Tu Kuo-Chi, Yang Chin-Chieh, You Wen-Chun
Принадлежит:

Some embodiments relate to an integrated circuit device, which includes a bottom electrode, a dielectric layer, and top electrode. The dielectric layer is disposed over the bottom electrode. The top electrode is disposed over the dielectric layer, and an upper surface of the top electrode exhibits a recess. A via is disposed over the top electrode. The via makes electrical contact with only a tapered sidewall of the recess without contacting a bottom surface of the recess. 1. An integrated circuit device , comprising:a bottom electrode;a dielectric layer disposed over the bottom electrode;a top electrode disposed over the dielectric layer, wherein an upper surface of the top electrode comprises a tapered recess; anda via disposed over the top electrode, wherein the via establishes electrical contact with an inner sidewall of the tapered recess but not with a central bottom surface of the tapered recess.2. The integrated circuit device of claim 1 , further comprising:a dielectric material arranged under the via and contacting the central bottom surface of the tapered recess of the top electrode.3. The integrated circuit device of claim 2 , wherein the dielectric material further comprises outer sidewalls that contact a bottom inner sidewall of the tapered recess under the via.4. The integrated circuit device of claim 1 , further comprising:sidewall spacers disposed over the bottom electrode and along outer sidewalls of the top electrode.5. The integrated circuit device of claim 1 , wherein the top electrode comprises:a central upper electrode portion having a first thickness; anda peripheral upper electrode portion having a second thickness that differs from the first thickness.6. The integrated circuit device of claim 5 , wherein the first thickness is less than the second thickness.7. The integrated circuit device of claim 5 , wherein the first thickness is half of or less than half of the second thickness.8. The integrated circuit device of claim 1 , wherein the ...

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Номер записи: 44
22-01-2015 дата публикации

Programmably Reversible Resistive Device Cells Using CMOS Logic Processes

Номер: US20150021543A1
Автор: Chung Shine C.
Принадлежит:

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive devices, such as PCM, RRAM, CBRAM, or other memory cells. The reversible resistive devices have a reversible resistive element coupled to a diode. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a voltage or a current between a reversible resistive element and the N terminal of a diode, the reversible resistive device can be programmed into different states based on magnitude, duration, voltage-limit, or current-limit in a reversible manner. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations. 1. A reversible resistive memory , comprising: a plurality of active region lines running in a first direction, each of the active region lines being in separated by a CMOS well;', 'a plurality of isolation lines running in a second direction substantially perpendicular to the first direction to separate one or more of the active region lines into a plurality of isolated active regions, at least one of the isolated active regions being fabricated from sources or drains of CMOS devices and being implanted with a first type of dopant and a shared second type of dopant to constitute a first and a second terminals of diodes, respectively, the second terminal of the diodes being coupled to a first supply voltage line;', 'a plurality of metal lines running in the second direction and coupled to a second supply voltage line;', 'a contact hole being built at a cross over point of the metal lines and the isolated active regions; and', 'at least one reversible resistive element built in the contact hole that couples to the isolated active region with the first type of dopant and to the metal lines,, 'a plurality of reversible resistive cells, at least one of the reversible resistive cells comprisingwherein ...

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Номер записи: 45
16-01-2020 дата публикации

Dynamic random access memory

Номер: US20200020696A1
Автор: Xi Lin, Yi Hua SHEN
Принадлежит: Semiconductor Manufacturing International Beijing Corp, Semiconductor Manufacturing International Shanghai Corp

A dynamic random access memory (DRAM) is provided and includes a base substrate. The base substrate includes a semiconductor substrate, a plurality of fins formed on the semiconductor substrate, and an isolation structure formed on the semiconductor substrate and covering portions of side surfaces of the plurality of fins. The dynamic random access memory further includes an interlayer dielectric layer formed over the base substrate and covering top surfaces of the plurality of fins and the isolation structure; and a memory structure, formed in an opening passing through the interlayer dielectric layer and each of the plurality of fins, the opening extending to and exposing a top surface of a portion of the isolation structure. The memory structure includes a first conductive layer, a memory medium layer on the first conductive layer, and a second conductive layer on the memory medium layer.

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Номер записи: 46
16-01-2020 дата публикации

MEMORY CIRCUIT AND FORMATION METHOD THEREOF

Номер: US20200020744A1
Автор: Huang Kuo-Ching, Ong Tong-Chern, Tsai Chun-Yang
Принадлежит:

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may include forming a control device within a substrate. A first plurality of interconnect layers are formed within a first inter-level dielectric (ILD) structure over the substrate. A first memory device and a second memory device are formed over the first ILD structure. A second plurality of interconnect layers are formed within a second ILD structure over the first ILD structure. The first plurality of interconnect layers and the second plurality of interconnect layers couple the first memory device and the second memory device to the control device. 1. A method of forming an integrated chip , comprising:forming a control device within a substrate;forming a first plurality of interconnect layers within a first inter-level dielectric (ILD) structure over the substrate;forming a first memory device over the first ILD structure;forming a second memory device over the first ILD structure;forming a second plurality of interconnect layers within a second ILD structure over the first ILD structure; andwherein the first plurality of interconnect layers and the second plurality of interconnect layers couple the first memory device and the second memory device to the control device.2. The method of claim 1 , wherein the second plurality of interconnect layers comprise a metal wire directly between the first memory device and the second memory device.3. The method of claim 1 , wherein the second ILD structure is formed to laterally surround the first memory device and the second memory device.4. The method of claim 1 , further comprising:wherein the first memory device has a first lower electrode over the first ILD structure and a first upper electrode over the first lower electrode; andwherein the first plurality of interconnect layers and the second plurality of interconnect layers are coupled between the first upper electrode and control device.5. The method of ...

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Номер записи: 47
16-01-2020 дата публикации

INTERCONNECT LANDING METHOD FOR RRAM TECHNOLOGY

Номер: US20200020745A1
Автор: CHANG Chih-Yang, Chen Hsia-Wei, Chu Wen-Ting, Liao Yu-Wen, Tu Kuo-Chi, Yang Chin-Chieh, Yang Jen-Sheng
Принадлежит:

The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit has a first inter-level dielectric (ILD) layer over a substrate. A lower electrode is over the first ILD layer, a data storage structure is over the lower electrode, and an upper electrode is over the data storage structure. An upper interconnect wire directly contacts an entirety of an upper surface of the upper electrode. A conductive via directly contacts an upper surface of the upper interconnect wire. The conductive via has an outermost sidewall that is directly over the upper surface of the upper interconnect wire. 1. An integrated chip , comprising:a first inter-level dielectric (ILD) layer over a substrate;a lower electrode over the first ILD layer;a data storage structure over the lower electrode;an upper electrode over the data storage structure;an upper interconnect wire directly contacting an entirety of an upper surface of the upper electrode; anda conductive via directly contacting an upper surface of the upper interconnect wire, wherein the conductive via has an outermost sidewall that is directly over the upper surface of the upper interconnect wire.2. The integrated chip of claim 1 , further comprising:a sidewall spacer covering sidewalls of the lower electrode, the data storage structure, and the upper electrode.3. The integrated chip of claim 2 , further comprising:a second ILD layer over the first ILD layer and laterally separated from the data storage structure by the sidewall spacer.4. The integrated chip of claim 2 , wherein the upper interconnect wire laterally extends over a top of the sidewall spacer.5. The integrated chip of claim 2 , wherein the sidewall spacer comprises a first sidewall directly contacting the data storage structure and a second sidewall directly contacting the upper interconnect wire.6. The integrated chip of claim 2 , further comprising:an etch stop layer disposed on the sidewall spacer, wherein the sidewall spacer and ...

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Номер записи: 48
16-01-2020 дата публикации

RRAM CELL STRUCTURE WITH CONDUCTIVE ETCH-STOP LAYER

Номер: US20200020856A1
Автор: Hsu Chern-Yow, Liu Ming Chyi, Liu Shih-Chang, Tsai Chia-Shiung, Tseng Yuan-Tai
Принадлежит:

The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode. 1. A resistive random access memory (RRAM) device comprising:a semiconductor substrate;a metal interconnect structure disposed within a low-k dielectric layer and disposed over the semiconductor substrate;a conductive etch-stop layer (CESL) abutting an upper surface of the metal interconnect structure;a bottom electrode structure over the CESL;a variable resistance dielectric structure over the bottom electrode structure;a top electrode structure over the variable resistance dielectric structure;sidewall spacers about outer sidewalls of the top electrode structure; andwherein outer sidewalls of the bottom electrode structure are spaced apart by a first distance, and outer sidewalls of the top electrode structure are spaced apart by a second distance which is less than the first distance;wherein the CESL is a transitional metal nitride layer having an etch-selectivity that differs from an etch-selectivity of the bottom electrode structure.2. The RRAM device of claim 1 , wherein the bottom electrode structure is a single conductive electrode layer.3. The RRAM device of claim 1 , ...

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Номер записи: 49
21-01-2021 дата публикации

THREE-DIMENSIONAL SEMICONDUCTOR DEVICES

Номер: US20210020628A1
Автор: HA Yongho, Hyun Sangjin, Kang Pil-kyu, KIM Kughwan, KIM WeonHong, Lee Sang Woo, Lim SungKeun, OH Seungha, SASAKI Yuichiro
Принадлежит:

A three-dimensional semiconductor device includes a lower substrate, a plurality of lower transistors disposed on the lower substrate, an upper substrate disposed on the lower transistors, a plurality of lower conductive lines disposed between the lower transistors and the upper substrate, and a plurality of upper transistors disposed on the upper substrate. At least one of the lower transistors is connected to a corresponding one of the lower conductive lines. Each of the upper transistors includes an upper gate electrode disposed on the upper substrate, a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode, and a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode. The upper gate electrode includes silicon germanium (SiGe). 1. A three-dimensional semiconductor device , comprising:a lower substrate;a plurality of lower transistors disposed on the lower substrate;an upper substrate disposed on the lower transistors;a plurality of lower conductive lines disposed between the lower transistors and the upper substrate; anda plurality of upper transistors disposed on the upper substrate,wherein at least one of the lower transistors is connected to a corresponding one of the lower conductive lines, an upper gate electrode disposed on the upper substrate;', 'a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode; and', 'a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode,', 'wherein the upper gate electrode comprises silicon germanium (SiGe)., 'wherein each of the upper transistors comprises2. The three-dimensional semiconductor device of claim 1 , wherein the upper substrate comprises a channel region disposed below the upper gate electrode claim 1 , and the channel region comprises silicon.3. The three-dimensional ...

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Номер записи: 50
21-01-2021 дата публикации

MEMORY DEVICE AND A METHOD FOR FORMING THE MEMORY DEVICE

Номер: US20210020834A1
Автор: Loy Desmond Jia Jun, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

A memory device may include at least one inert electrode, at least one mask element arranged over the at least one inert electrode, a switching layer arranged over the at least one mask element and the at least one inert electrode, and at least one active electrode arranged over the switching layer. Both of the at least one mask element and the switching layer may be in contact with a top surface of the at least one inert electrode. The switching layer in this memory device may thus include corners at which the conductive filaments may be confined. This memory device may be formed with a process that may utilize the at least one mask element to help reduce the chances of shorting between the inert and active electrodes. 1. A memory device comprising:at least one inert electrode;at least one mask element arranged over the at least one inert electrode;a switching layer arranged over the at least one mask element and the at least one inert electrode, wherein both of the at least one mask element and the switching layer are in contact with a top surface of the at least one inert electrode; andat least one active electrode arranged over the switching layer.2. The memory device of claim 1 , wherein the at least one inert electrode comprises two or more inert electrodes separated from each other.3. The memory device of claim 2 , wherein the memory device further comprises an insulating layer below the at least one mask element and wherein the two or more inert electrodes are arranged within the insulating layer.4. The memory device of claim 1 , wherein the at least one inert electrode comprises only a single inert electrode.5. The memory device of claim 1 , wherein the at least one active electrode comprises two or more active electrodes separated from each other.6. The memory device of claim 1 , wherein the at least one active electrode comprises only a single active electrode.7. The memory device of claim 1 , wherein the at least one mask element comprises only a single ...

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Номер записи: 51
28-01-2016 дата публикации

NONVOLTILE RESISTANCE MEMORY AND ITS OPERATION THEREOF

Номер: US20160027507A1
Автор: Chung Steve S., HSIEH E-Ray
Принадлежит:

A memory cell and the associated array circuits are disclosed. The memory array circuit includes a plurality of memory units, in which each of the memory units includes a storage device and a field-effect transistor. The storage device includes a top electrode, a bottom electrode and an oxide-based dielectric layer. The top electrode is formed by metal or metallic oxide dielectrics and connected to a word line. The bottom electrode is formed by metal, and the oxide-based dielectric layer is placed between the top electrode and the bottom electrode. The field-effect transistor includes a gate terminal connected to the bottom electrode, a source terminal connected to a ground line, and a drain terminal connected to a bit line. The resistance of the storage device is configured to be adjusted according to a first voltage applied to the word line and a second voltage applied to the bit line. 1. A memory array circuit , comprising:a plurality of memory units, wherein each of the memory units comprises: a top electrode formed by metal or metallic oxide compound or metallic-semiconductor compound connected to a word line;', 'a bottom electrode formed by metal or metallic oxide compound or metallic-semiconductor compound; and', 'an oxide-based dielectric formed between the top electrode and the bottom electrode; and, 'a storage device, comprising a gate terminal connected to the bottom electrode of the storage device;', 'a source terminal connected to a ground line; and', 'a drain terminal connected to a bit line;', 'a channel between the source terminal, the drain terminal, and the gate terminal;', 'wherein the resistance or conductivity of the storage device is configured to be adjusted according to the differences of voltages between the corresponding word lines, the corresponding bit lines, or the corresponding ground lines connected to memory units., 'a field-effect transistor, comprising2. The memory array circuit of claim 1 , wherein the storage device is configured ...

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Номер записи: 52
26-01-2017 дата публикации

Array Of Cross Point Memory Cells

Номер: US20170025474A1
Автор: Calderoni Alessandro, Ramaswamy Durai Vishak Nirmal, Sills Scott E.
Принадлежит:

An array of cross point memory cells comprises spaced first lines which cross spaced second lines. Two memory cells are individually between one of two immediately adjacent of the second lines and a same single one of the first lines. 1. An array of cross point memory cells comprising spaced first lines which cross spaced second lines , two memory cells individually between one of two immediately adjacent of the second lines and a same single one of the first lines.2. The array of wherein the memory cells comprise select devices.3. The array of comprising one select device for every memory cell.4. The array of comprising one select device for every two memory cells.5. The array of wherein the two memory cells each comprise programmable material claim 1 , and comprising a single shared select device electrically coupled to the one first line and electrically coupled to the programmable material of each of the two memory cells.6. The array of wherein the two memory cells each comprise programmable material claim 1 , and comprising two non-shared select devices individually electrically coupled to a respective one of the two immediately adjacent second lines and electrically coupled to the programmable material of a different one of the two memory cells.7. The array of wherein the first and second lines angle relative one another other than orthogonally.8. The array of wherein the first and second lines angle relative one another at about 45°.9. The array of wherein the second lines are elevationally outward of the first lines.10. The array of wherein the first and second lines are individually straight linear within the array.11. The array of wherein the two memory cells are individually elevationally elongated and share an elevationally elongated conductive pillar.12. The array of wherein the shared conductive pillar is elevationally over the one first line.13. The array of wherein the two memory cells are individually elevationally elongated claim 1 , the two memory ...

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Номер записи: 53
28-01-2016 дата публикации

NAND-type Resistance Random Access Memory Circuit And Operation Thereof

Номер: US20160027844A1
Автор: Chung Steve S., HSIEH E-Ray
Принадлежит:

A high density NAND-type nonvolatile resistance random access storage circuit and its operations are disclosed herein. A unit memory cell of the circuit includes a field effect transistor (FET) with a resistance changeable component connected to its gate electrode. The field effect transistor is an n-channel field effect transistor or a p-channel field effect transistor. By applying the voltage or current between the top electrode of the resistive random access component and the FET drain or source electrode, more than two stable states can be maintained such that these states can be drawn from the FET drain or source electrode. The NAND circuit includes the above unit cell as a center to form a multi-bit memory. The circuit consists of multi-bit memories connected in series, has a NAND logic gate function, and forms output of this NAND circuit which can be drawn in a form of series output. 1. A non-volatile resistance random access storage circuit comprising a plurality of memory units , wherein each of the memory units comprises:a field effect transistor comprising a gate electrode, a source electrode, a drain electrode, and a channel between the gate electrode, the source electrode, and the drain electrode;a resistance changeable component comprising:a first terminal electrically connected to the gate electrode; anda second terminal electrically connected to a conducting electrode;wherein the resistance changeable component is formed by laminating at least one oxide layer onto at least one first metal layer, and then laminating at least one second metal layer onto the oxide layer,wherein the resistance, conductivity or conducting current of the resistance changeable component has equivalent to or more than two stable states by voltage or current sources applied between the first terminal and the second terminal of the resistance changeable component.2. The non-volatile resistance random access storage circuit of claim 1 , wherein the gate electrode is also used ...

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Номер записи: 54
28-01-2016 дата публикации

RESISTIVE MEMORY DEVICE

Номер: US20160028009A1
Автор: QUEK Elgin Kiok Boone, SUN YUAN, Tan Shyue Seng, Toh Eng Huat, TRAN Xuan Anh
Принадлежит:

A non-volatile memory device and a manufacturing method thereof are provided. The memory device includes a substrate, a lower cell dielectric layer with gate conductors and a body unit conductor disposed on the lower cell dielectric layer and gates. Memory element conductors are disposed on the body unit and lower cell dielectric layer. An upper cell dielectric layer may be on the substrate and over the lower cell dielectric layer, body unit conductor and memory element conductors. The upper cell dielectric layer isolates the memory element conductors. 1. A method for forming a device comprising:providing a substrate prepared with a lower cell dielectric layer with gate conductors disposed in a first direction, the gate conductors separated the lower cell dielectric layer;forming a body unit conductor on the lower cell dielectric layer and gate conductors, wherein the body unit conductor is disposed along a second direction and traverses the gate conductors;forming memory element conductors on the body unit and lower cell dielectric layer, the memory element conductors are disposed along the first direction over the gate conductors; andforming an upper cell dielectric layer on the substrate to cover the lower cell dielectric layer, body unit conductor and memory element conductors, the upper cell dielectric layer isolating the memory element conductors.2. The method of wherein the gate conductors have a planar surface with the lower cell dielectric layer.3. The method of wherein:the gate conductors have a top surface disposed over a top surface of the lower cell dielectric layer, creating gate conductor mesas;the body unit conductor is disposed on the gate conductor mesas, creating body mesas; andforming memory element conductors on the body mesas.4. The method of wherein:the gate conductors have a top surface disposed below a top surface of the lower cell dielectric layer, creating gate conductor recesses;the body unit conductor is disposed on the lower cell ...

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Номер записи: 55
25-01-2018 дата публикации

HIGH DENSITY MULTI-TIME PROGRAMMABLE RESISTIVE MEMORY DEVICES AND METHOD OF FORMING THEREOF

Номер: US20180026076A1
Автор: Toh Eng Huat, TRAN Xuan Anh
Принадлежит:

Multi-time programmable (MTP) random access memory (RRAM) devices and methods for forming a MTP RRAM device are disclosed. The method includes providing a substrate. The substrate is prepared with at least a first region for accommodating one or more multi-programmable based resistive random access memory (RRAM) cell. A fin-type based selector is provided over the substrate in the first region. A storage element of the RRAM cell is formed over the fin-type based selector. The fin-type based selector is coupled in series with the storage element of the RRAM cell. 1. A semiconductor device comprising:a substrate having at least a first region for accommodating one or more multi-time programmable resistive random access memory (RRAM) cell, wherein the substrate comprises a fin structure disposed in the first region, wherein the fin structure comprises first polarity dopants;an isolation layer disposed on the substrate, wherein the isolation layer surrounds a bottom fin portion of the fin structure, wherein a top fin portion of the fin structure is exposed above the isolation layer;a first semiconductor layer disposed over the top fin portion of the fin structure, wherein the first semiconductor layer wraps around a top surface and sides of the top fin portion, and the first semiconductor layer comprises second polarity type dopants opposite to the first polarity type;a second semiconductor layer disposed over the first semiconductor layer in the first region, wherein the second semiconductor layer wraps around a top surface and sides of the first semiconductor layer, and the second semiconductor layer comprises the first polarity type dopants, wherein the combination of the fin structure, the first semiconductor layer and the second semiconductor layer defines a fin-type selector in the first region; anda storage element of the RRAM cell disposed over the fin-type selector, wherein the fin-type selector is coupled in series with the storage element of the RRAM cell.2. ...

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Номер записи: 56
10-02-2022 дата публикации

SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

Номер: US20220045125A1
Автор: Kimura Hajime, KUROKAWA Yoshiyuki
Принадлежит:

A semiconductor device that can perform product-sum operation with low power consumption is provided. The semiconductor device includes first and second circuits; the first circuit includes a first holding node and the second circuit includes a second holding node. The first circuit is electrically connected to first and second input wirings and first and second wirings, the second circuit is electrically connected to the first and second input wirings and the first and second wirings, and the first and second circuits each have a function of holding first and second potentials corresponding to first data at the first and second holding nodes. When a potential corresponding to second data is input to each of the first and second input wirings, the first circuit outputs a current to one of the first wiring and the second wiring and the second circuit outputs a current to the other of the first wiring and the second wiring. The currents output from the first and second circuits to the first wiring or the second wiring are determined in accordance with the first and second potentials held at the first and second holding nodes. 1. A semiconductor device comprising a first circuit and a second circuit ,wherein the first circuit comprises a first holding node,wherein the second circuit comprises a second holding node,wherein the first circuit is electrically connected to a first input wiring, a second input wiring, a first wiring, and a second wiring,wherein the second circuit is electrically connected to the first input wiring, the second input wiring, the first wiring, and the second wiring,wherein the first circuit is configured to hold a first potential corresponding to first data at the first holding node,wherein the second circuit is configured to hold a second potential corresponding to the first data at the second holding node, output a current corresponding to the first potential to the first wiring when a high-level potential is input to the first input wiring ...

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Номер записи: 57
24-01-2019 дата публикации

CORRELATED ELECTRON SWITCH PROGRAMMABLE FABRIC

Номер: US20190027216A1
Автор: Chandra Vikas, Cline Brian, Shifren Lucian, Sinha Saurabh, Yeric Greg
Принадлежит:

Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices. 123-. (canceled)24. A method , comprising:selectively connecting or disconnecting one or more portions of an integrated circuit to one or more other portions of the integrated circuit at least in part by selectively applying a programming voltage to one or more correlated electron switch devices to cause a transition in the one or more correlated electron switch devices from a first impedance state to a second impedance state, wherein the one or more correlated electron switch devices are respectively positioned between one or more electrodes of a first metallization layer and one or more electrodes of a second metallization layer.25. The method of claim 24 , wherein the selectively connecting or disconnecting the one or more portions of the integrated circuit to the one or more other portions of the integrated circuit comprises compensating for manufacturing errors in the integrated circuit.26. The method of claim 24 , wherein the selectively connecting or disconnecting the one or more portions of the integrated circuit to the one or more other portions of the integrated circuit comprises compensating for design errors in the integrated circuit.27. The method of claim 24 , wherein the selectively connecting or disconnecting the one or more portions of the integrated circuit to the one or more other portions of the integrated circuit comprises reducing power consumption in the integrated circuit at least in part by selectively disconnecting a supply voltage from the one or more portions of the integrated circuit.28. The method of claim 24 , wherein the selectively connecting or disconnecting the one or more portions of the integrated circuit to the one or more other portions of the integrated circuit comprises adjusting clock skew between specified portions of the integrated circuit.29. The method of claim 28 , wherein the integrated circuit comprises a ...

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Номер записи: 58
24-01-2019 дата публикации

SWITCHING BLOCK CONFIGURATION BIT COMPRISING A NON-VOLATILE MEMORY CELL

Номер: US20190027219A1
Автор: Jo Sung Hyun, Nazarian Hagop
Принадлежит:

A configuration bit for a switching block routing array comprising a non-volatile memory cell is provided. By way of example, the configuration bit and switching block routing array can be utilized for a field programmable gate array, or other suitable circuit(s), integrated circuit(s), application specific integrated circuit(s), electronic device or the like. The configuration bit can comprise a switch that selectively connects or disconnects a node of the switching block routing array. A non-volatile memory cell connected to the switch can be utilized to activate or deactivate the switch. In one or more embodiments, the non-volatile memory cell can comprise a volatile resistance switching device connected in serial to a gate node of the switch, configured to trap charge at the gate node to activate the switch, or release the charge at the gate node to deactivate the switch. 1a non-volatile switch comprising an input node, an output node and a control gate, the input node connected to a first conductive line of a switching block routing array and the output node connected to a second conductive line of the switching block routing array;a volatile switch having a first contact and a second contact, the second contact is conductively connected to the control gate of the non-volatile switch; anda program circuit configured to selectively provide a voltage from a voltage source to the first contact of the volatile switch.. A circuit, comprising: This application for patent is a continuation of and claims priority to U.S. application Ser. No. 15/469,179, titled SWITCHING BLOCK CONFIGURATION BIT COMPRISING A NON-VOLATILE MEMORY CELL and filed Mar. 24, 2017, which is hereby incorporated by reference herein in its entirety and for all purposes.U.S. application Ser. No. 14/717,185 entitled “NON-VOLATILE MEMORY CELL UTILIZING VOLATILE SWITCHING TWO TERMINAL DEVICE AND A MOS TRANSISTOR” and filed May 20, 2015, U.S. application Ser. No. 14/588,185 entitled “SELECTOR DEVICE FOR ...

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Номер записи: 59
24-01-2019 дата публикации

SEMICONDUCTOR DEVICES

Номер: US20190027482A1
Автор: Hong HyeongSun, Hur Kijae, Hwang Yoosang, Kim Bong-Soo, KIM SungWoo, Kim Youngbae, KOH GWANHYEOB
Принадлежит:

A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section on a substrate; a second memory section on the second peripheral circuit section; and a wiring section between the second peripheral circuit section and the second memory section, the first memory section includes a plurality of first memory cells, the first memory cells each including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, the second memory cells each including a variable resistance element and a select element in series, and the wiring section includes a plurality of line patterns, at least one of the line patterns and at least one of the capacitors at the same level from the substrate, the second memory cells are higher from the substrate than the at least one of the capacitors. 1. A semiconductor device , comprising:a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed on a substrate;a second memory section on the second peripheral circuit section; anda wiring section between the second peripheral circuit section and the second memory section, whereinthe first memory section comprises a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor,the second memory section comprises a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, andthe wiring section comprises a plurality of line patterns, at least one of the line patterns and at least one of the capacitors being at the same level with respect to the substrate,wherein the second memory cells are higher from the substrate than the at least one of the capacitors.2. The semiconductor device of claim 1 , wherein the second memory ...

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Номер записи: 60
24-01-2019 дата публикации

Logic integrated circuit and semiconductor device

Номер: US20190028101A1
Автор: Ayuka Tada, Makoto Miyamura, Ryusuke Nebashi, Toshitsugu Sakamoto, Xu Bai, Yukihide Tsuji
Принадлежит: NEC Corp

An object of the present invention is to provide a logic integrated circuit that increases reliability of configuration information held in a switch while maintaining high tamper resistance and a small chip area. The logic integrated circuit according to the present invention includes: a three-terminal resistance change switch including a first resistance change switch and a second resistance change switch connected in series; a reading circuit which reads first data based on a resistance state of the first resistance change switch and second data based on a resistance state of the second resistance change switch; and a first error detection circuit which compares the first data with the second data and issue an output based on a result of the comparison.

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Номер записи: 61
23-01-2020 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20200027734A1
Автор: Hwang Yoosang, KIM Hui-Jung, KIM KEUNNAM, LEE KISEOK
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises alternately stacking a plurality of dielectric layers and a plurality of first semiconductor layers to form a mold structure on a substrate, forming a hole penetrating the mold structure, forming on the substrate a second semiconductor layer filling the hole, and irradiating a laser onto the second semiconductor layer. 1. A method of manufacturing a semiconductor device , the method comprising:alternately stacking a plurality of dielectric layers and a plurality of first semiconductor layers to form a mold structure on a substrate;forming a hole penetrating the mold structure;forming on the substrate a second semiconductor layer filling the hole; andirradiating a laser onto the second semiconductor layer.2. The method of claim 1 , wherein forming the hole exposes a top surface of the substrate.3. The method of claim 1 , wherein irradiating the laser comprises:single-crystallizing the second semiconductor layer along crystallinity of the substrate; andsingle-crystallizing the first semiconductor layers along crystallinity of the second semiconductor layer that has been single-crystallized.4. The method of claim 3 , whereinsingle-crystallizing the second semiconductor layer comprises converting the second semiconductor layer from amorphous into single crystalline, andsingle-crystallizing the first semiconductor layers comprises converting the first semiconductor layer from amorphous into single crystalline.5. The method of claim 4 , wherein the substrate includes a single crystalline semiconductor material.6. The method of claim 1 , wherein irradiating the laser comprises:causing the laser to increase temperature of the second semiconductor layer; andproviding the first semiconductor layers with heat from the second semiconductor layer.7. The method of claim 1 , wherein forming the second semiconductor layer comprises allowing the second semiconductor layer to cover a ...

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Номер записи: 62
23-01-2020 дата публикации

MEMORY CIRCUIT AND FORMATION METHOD THEREOF

Номер: US20200027922A1
Автор: Huang Kuo-Ching, Ong Tong-Chern, Tsai Chun-Yang
Принадлежит:

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a control device arranged within a substrate and having a terminal. A first memory device is coupled between the terminal of the control device and a first bit-line. A second memory device is coupled between the terminal of the control device and a second bit-line. 1. An integrated chip , comprising:a control device arranged within a substrate and having a terminal;a first memory device coupled between the terminal of the control device and a first bit-line; anda second memory device coupled between the terminal of the control device and a second bit-line.2. The integrated chip of claim 1 ,wherein the control device is a transistor having a gate structure laterally disposed between a source region and a drain region; andwherein the first memory device and the second memory device are coupled to the drain region.3. The integrated chip of claim 1 ,wherein the first memory device comprises a first data storage layer over a first lower electrode and a first upper electrode over the first data storage layer, the first upper electrode coupled between the first data storage layer and the terminal; andwherein the second memory device comprises a second data storage layer over a second lower electrode and a second upper electrode over the second data storage layer, the second lower electrode coupled between the second data storage layer and the terminal.4. The integrated chip of claim 1 , further comprising:a plurality of interconnect layers disposed within a dielectric structure over the substrate and electrically coupling the terminal to the first memory device and the second memory device, wherein one of the plurality of interconnect layers is disposed directly between the first memory device and the second memory device.5. The integrated chip of claim 1 , further comprising:an interconnect wire disposed within a dielectric structure over the substrate and coupled ...

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Номер записи: 63
23-01-2020 дата публикации

RRAM MEMORY CELL WITH MULTIPLE FILAMENTS

Номер: US20200027924A1
Автор: CHANG Chih-Yang, Chu Wen-Ting, Liao Yu-Wen, Yang Chin-Chieh
Принадлежит:

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a conductive element disposed within a dielectric structure over the substrate. The conductive element has a top surface extend between outermost sidewalls of the conductive element. A first resistive random access memory (RRAM) element is arranged within the dielectric structure and has a first data storage layer directly contacting the top surface of the conductive element. A second RRAM element is arranged within the dielectric structure and has a second data storage layer directly contacting the top surface of the conductive element. 1. An integrated chip , comprising:a conductive element disposed within a dielectric structure over a substrate, wherein the conductive element comprises a top surface extending between outermost sidewalls of the conductive element;a first resistive random access memory (RRAM) element arranged within the dielectric structure and having a first data storage layer directly contacting the top surface of the conductive element; anda second RRAM element arranged within the dielectric structure and having a second data storage layer directly contacting the top surface of the conductive element.2. The integrated chip of claim 1 , wherein a bottom surface of the conductive element has smaller width than the top surface of the conductive element.3. The integrated chip of claim 2 , further comprising:one or more lower interconnect layers disposed within a lower inter-level dielectric (ILD) structure that is between the bottom surface of the conductive element and the substrate.4. The integrated chip of claim 3 , wherein the conductive element is a different material than the one or more lower interconnect layers.5. The integrated chip of claim 3 , further comprising:an insulating layer disposed over the lower ILD structure and laterally surrounding a part of the conductive element, wherein the conductive element has a lower surface that is ...

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Номер записи: 64
23-01-2020 дата публикации

Method for forming a phase change memory (pcm) cell with a low deviation contact area between a heater and a phase change element

Номер: US20200028075A1
Автор: Shih-Chang Liu, Yi Jen Tsai
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A phase change memory (PCM) cell with a low deviation contact area between a heater and a phase change element is provided. The PCM cell comprises a bottom electrode, a dielectric layer, a heater, a phase change element, and a top electrode. The dielectric layer overlies the bottom electrode. The heater extends upward from the bottom electrode, through the dielectric layer. Further, the heater has a top surface that is substantially planar and that is spaced below a top surface of the dielectric layer. The phase change element overlies the dielectric layer and protrudes into the dielectric layer to contact with the top surface of the heater. Also provided is a method for manufacturing the PCM cell.

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Номер записи: 65
23-01-2020 дата публикации

Resistive memory crossbar array with top electrode inner spacers

Номер: US20200028076A1
Автор: Hiroyuki Miyazoe, Iqbal R. Saraf, Shyng-Tsong Chen, Takashi Ando
Принадлежит: International Business Machines Corp

A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming conductive lines within an interlayer dielectric (ILD), forming a metal nitride layer over at least one conductive line, forming a bottom electrode, forming a RRAM stack over the metal nitride layer, the RRAM stack including a first top electrode and a second top electrode, undercutting the second top electrode to define recesses, and filling the recesses with inner spacers.

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Номер записи: 66
23-01-2020 дата публикации

METAL LANDING ON TOP ELECTRODE OF RRAM

Номер: US20200028077A1
Автор: CHANG Chih-Yang, Chu Wen-Ting
Принадлежит:

Some embodiments relate to an integrated circuit including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer. A memory cell includes a bottom electrode disposed over the lower metal interconnect layer, a data storage or dielectric layer disposed over the bottom electrode, and a top electrode disposed over the data storage or dielectric layer. An upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer. Sidewall spacers are arranged along sidewalls of the top electrode, and have bottom surfaces that rest on an upper surface of the data storage or dielectric layer. 1. An integrated circuit (IC) including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer , a memory cell comprising:a bottom electrode disposed over the lower metal interconnect layer;a data storage or dielectric layer disposed over the bottom electrode;a top electrode disposed over the data storage or dielectric layer, wherein an upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer; andsidewall spacers arranged along sidewalls of the top electrode, and having bottom surfaces that rest on an upper surface of the data storage or dielectric layer.2. The IC of claim 1 , wherein the top electrode has an upper planar surface which extends continuously between sidewalls of the top electrode and which directly abuts the upper metal interconnect layer.3. The IC of claim 2 , wherein the bottom electrode has sidewalls which are aligned with the sidewalls of the top electrode.4. The IC of claim 1 , further comprising:a capping layer ...

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Номер записи: 67
28-01-2021 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR MEMORY DEVICE

Номер: US20210028188A1
Автор: KIM Nam Kuk, LEE Nam Jae
Принадлежит: SK HYNIX INC.

A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a doped semiconductor pattern including a body portion and a first protrusion protruding from the body portion in a first direction, a first channel pattern disposed on a top surface of the first protrusion and extending in the first direction, a first memory pattern surrounding a sidewall of the first channel pattern and extending on a sidewall of the first protrusion, and interlayer insulating layers and conductive patterns alternately stacked on each other in the first direction. 1. A semiconductor memory device , comprising:a doped semiconductor pattern including a body portion and a first protrusion protruding from the body portion in a first direction;a first channel pattern disposed on a top surface of the first protrusion and extending in the first direction;a first memory pattern surrounding a sidewall of the first channel pattern and extended to surround a sidewall of the first protrusion; andinterlayer insulating layers and conductive patterns alternately stacked on each other in the first direction,wherein each of the interlayer insulating layers and the conductive patterns surrounds the first memory pattern.2. The semiconductor memory device of claim 1 , wherein the body portion comprises:an upper pattern extending from the first protrusion and along a bottom surface of the first memory pattern;a first horizontal pattern extending from the upper pattern and in parallel with a bottom surface of a stack structure, the stack structure including the interlayer insulating layers and the conductive patterns;a coupling pattern extending from the first horizontal pattern in a second direction opposite to the first direction; anda second horizontal pattern extending from the coupling pattern and in parallel with the first horizontal pattern.3. The semiconductor memory device of claim 1 , wherein the doped ...

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Номер записи: 68
28-01-2021 дата публикации

CROSSBAR ARRAY CIRCUIT WITH 3D VERTICAL RRAM

Номер: US20210028230A1
Автор: GE NING, Zhang Minxian
Принадлежит: TETRAMEM INC.

Provided are 3D One-Transistor-N-RRAM (1TNR) structures and One-Selector-One-RRAM (1S1R) structures and methods for manufacturing the same. An example 3D 1TNR structure comprises: a plurality of gate lines; and a plurality of crossbar arrays (e.g., a first crossbar array and a second crossbar array). The first and second crossbar arrays are positioned on a first vertical plane and a second vertical plane, respectively. Each crossbar array in the plurality of crossbar arrays includes a first plurality of bit lines and a second plurality of word lines; Each word line in the second plurality of word lines is connected to a source and a destination of a second transistor; and each gate line in the plurality of gate lines is connected to a gate of a first transistor located in the first crossbar array and a gate of a second transistor located in the second crossbar array. 1. A 3D One-Transistor-N-RRAM (1TNR) structure comprising:a plurality of gate lines; and the first crossbar array is positioned on a first vertical plane;', 'the second crossbar array is positioned on a second vertical plane different from the first vertical plane;', 'each crossbar array in the plurality of crossbar arrays includes a first plurality of bit lines and a second plurality of word lines;', 'each word line in the second plurality of word lines is connected to a source and a destination of a second transistor;', 'each gate line in the plurality of gate lines is connected to a gate of a first transistor located in the first crossbar array and a gate of a second transistor located in the second crossbar array., 'a plurality of crossbar arrays, including a first crossbar array and a second crossbar array, wherein'}2. The 3D One-Transistor-N-RRAM (1TNR) structure of claim 1 , wherein the plurality of crossbar arrays includes a third crossbar array positioned on a third vertical plane different from both the first crossbar array and the second crossbar array.3. The 3D One-Transistor-N-RRAM (1TNR) ...

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Номер записи: 69
28-01-2021 дата публикации

RESISTIVE 3D MEMORY

Номер: US20210028231A1
Автор: ANDRIEU Francois
Принадлежит: Commissariat A L'Energie Atomique Et Aux Energies Alternatives

A memory device is provided support and several superimposed levels of resistive memory cells formed on the support, each level having one or more rows of one or more resistive memory cell(s), each resistive memory cell having a variable resistance memory element formed by an area of variable resistivity material arranged between first electrode and a second electrode. The memory element is connected to a source region or drain region of a control transistor, the control transistor being formed in a given semiconductor layer of a stack of semiconductor layers formed on the support and wherein respective channel regions of respective control transistors of resistive memory cells are arranged. 1. A memory device provided with a support and several superimposed levels of resistive memory cells formed on the support , each level including one or more rows of one or more resistive memory cell(s) , each resistive memory cell comprising a variable resistance memory element , formed of a variable resistivity material zone disposed between a first electrode and a second electrode , the memory element being connected to a source or drain region of a control transistor , the control transistor being formed into a given semi-conducting layer of a superimposition of semi-conducting layers formed on the support and in which respective channel regions of respective control transistors of resistive memory cells are arranged.2. The memory device according to claim 1 , wherein a first vertical column of cells of different levels includes a first cell of a first level and a second cell of a second level from the superimposed levels of cells claim 1 , the first cell and second cell being respectively provided with a first control transistor and second control transistor claim 1 , the first control transistor and second control transistor having a common gate electrode or having respective gate electrodes connected to each other and to a same conducting zone.3. The memory device ...

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Номер записи: 70
02-02-2017 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20170033157A1
Автор: Ichiro Fujiwara, Mitsuharu Shoji
Принадлежит: Sony Corp

A semiconductor device including: a first member including a selection transistor on a front surface side of a first substrate; and a second member including a resistance change device and a connection layer that comes in contact with the resistance change device, the connection layer being bonded to a back surface of the first member.

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Номер записи: 71
02-02-2017 дата публикации

Resistive Switching Random Access Memory with Asymmetric Source and Drain

Номер: US20170033159A1
Автор: CHANG Chih-Yang, Chen Hsia-Wei, Chu Wen-Ting, Liao Yu-Wen, Tu Kuo-Chi, Yang Chin-Chieh
Принадлежит:

A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate and designed for data storage. The resistive element includes a resistive material layer. The resistive element further includes first and second electrodes interposed by the resistive material layer. The resistive element further includes a field effect transistor (FET) formed on the semiconductor substrate and coupled with the resistive memory element, wherein the FET includes asymmetric source and drain, the drain having a higher doping concentration than the source. The resistive memory element is coupled with the drain. 1. A resistive random access memory (RRAM) structure , comprising: a resistive material layer, and', 'first and second electrodes interposed by the resistive material layer; and, 'a resistive memory element formed on a semiconductor substrate and designed for data storage, wherein the resistive element includes'}a field effect transistor (FET) formed on the semiconductor substrate and coupled with the resistive memory element, wherein the FET includes an asymmetric source and drain, the drain having a higher doping concentration than the source;wherein the resistive memory element is coupled with the drain.2. The RRAM structure of claim 1 , wherein the source and drain are designed asymmetrically such that a voltage drop over the FET during a forming operation and an off-state leakage current are collectively optimized.3. The RRAM structure of claim 1 , wherein the FET further includes:a channel region formed in the semiconductor substrate; anda gate vertically disposed over the channel region and horizontally interposed between the source and drain,wherein the source and drain of the FET further include light doped drain (LDD) source and drain features that are asymmetric.4. The RRAM structure of claim 3 , wherein:the LDD source feature has a first doping concentration; andthe LDD drain feature has a second doping ...

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Номер записи: 72
02-02-2017 дата публикации

HIGH DENSITY RESISTIVE RANDOM ACCESS MEMORY (RRAM)

Номер: US20170033284A1
Автор: Liu Qing, Zhang John Hongguang
Принадлежит: STMicroelectronics, Inc.

A memory cell includes a substrate layer, with a plurality of silicided semiconductor fins stacked on the substrate layer and spaced apart from one another. A first metal liner layer is stacked on the plurality of silicided semiconductor fins and on the substrate layer. A plurality of first contact pillars are stacked on the first metal liner layer adjacent a different respective one of the plurality of silicided semiconductor fins. A configurable resistance structure covers portions of the first metal liner layer that are stacked on the substrate layer and portions of the first metal liner layer that are stacked on each of the plurality of silicided semiconductor fins. A metal fill layer is stacked on the configurable resistance structure. A plurality of second contact pillars ism stacked on the metal fill layer adjacent a space between a different pair of adjacent silicided semiconductor fins of the plurality thereof. 1. A memory cell , comprising:a substrate layer;a plurality of semiconductor fins stacked on the substrate layer and spaced apart from one another;a first metal liner layer stacked on the plurality of semiconductor fins and on the substrate layer;a plurality of first contact pillars, each first contact pillar being stacked on the first metal liner layer adjacent a different respective one of the plurality of semiconductor fins;a configurable resistance structure having a configurable resistance and covering portions of the first metal liner layer that are stacked on each of the plurality of semiconductor fins;a metal fill layer in contact with the configurable resistance structure; anda plurality of second contact pillars, each second contact pillar being stacked on the metal fill layer adjacent a space between adjacent ones of semiconductor fins.2. The memory cell of claim 1 , wherein the configurable resistance structure also covers portions of the first metal liner layer that are stacked on the substrate layer.3. The memory cell of claim 1 , ...

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Номер записи: 73
04-02-2016 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

Номер: US20160035792A1
Автор: Imamura Tsubasa, Sasaki Toshiyuki, Takahashi Atsushi
Принадлежит:

According to one embodiment, a semiconductor memory device includes a substrate including a major surface; a plurality of first films having conductivity or semiconductivity, the first films being provided above the substrate and extending in a first direction inclined with respect to the major surface; a plurality of second films having conductivity, the second films being provided above the substrate and extending in a second direction inclined with respect to the major surface and crossing the first direction; and a plurality of storage films provided in crossing sections of the first films and the second films. 1. A semiconductor memory device comprising:a substrate including a major surface;a plurality of first films having conductivity or semiconductivity, the first films being provided above the substrate and extending in a first direction inclined with respect to the major surface;a plurality of second films having conductivity, the second films being provided above the substrate and extending in a second direction inclined with respect to the major surface and crossing the first direction; anda plurality of storage films provided in crossing sections of the first films and the second films.2. The device according to claim 1 , wherein the first films pierce through layered second films.3. The device according to claim 1 , whereina stacked body including a plurality of electrode films as the second films and a plurality of insulating films respectively provided among the electrode films is provided above the substrate,a plurality of semiconductor bodies as the first films extend in the first direction piercing through the stacked body, andthe storage films include charge storage films provided between the electrode films and the semiconductor bodies.4. The device according to claim 3 , whereinthe storage films extend continuously in the first direction, anda plurality of columnar sections including the storage films and the semiconductor bodies extend in the ...

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Номер записи: 74
01-02-2018 дата публикации

Current Forming Of Resistive Random Access Memory (RRAM) Cell Filament

Номер: US20180033482A1
Автор: CHEN ZHIXIAN, Do Nhan, Hariharan Santosh, Lemke Steven, Liu Xian, Tran Hieu Van, WANG Xinpeng, Zhou Feng
Принадлежит:

A memory device includes a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and an electrical current source configured to apply one or more electrical current pulses through the metal oxide material. For each of the one or more electrical current pulses, an amplitude of the electrical current increases over time during the electrical current pulse to form a conductive filament in metal oxide material. 1. A method of forming a conductive filament in metal oxide material disposed between and in electrical contact with first and second conductive electrodes , the method comprising:applying one or more electrical current pulses through the metal oxide material;wherein for each of the one or more electrical current pulses, an amplitude of the electrical current increases over time during the electrical current pulse.2. The method of claim 1 , wherein for each of the one or more of the electrical current pulses claim 1 , the amplitude of the electrical current increases in discrete steps.3. The method of claim 2 , wherein for each of the one or more of the electrical current pulses claim 2 , a number of the discrete steps exceeds that of any of the one or more of the electrical current pulses preceding the electrical current pulse.4. The method of claim 1 , wherein for each of the one or more of the electrical current pulses claim 1 , a maximum of the electrical current amplitude exceeds that of any of the one or more of the electrical current pulses preceding the electrical current pulse.5. The method of claim 1 , wherein for each of the one or more of the electrical current pulses claim 1 , a duration of the one electrical current pulse exceeds that of any of the one or more of the electrical current pulses preceding the electrical current pulse.6. The method of claim 1 , wherein all of the one or more of the electrical current pulses have a same duration.7. The method of claim 1 , wherein for each of the one ...

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Номер записи: 75
01-02-2018 дата публикации

RESISTIVE RANDOM ACCESS MEMORY DEVICE

Номер: US20180033484A1
Автор: CHIH Yu-Der, CHOU Chung-Cheng, Chu Wen-Ting
Принадлежит:

A memory architecture includes: a first memory macro comprising a first plurality of memory cells that each comprises a first variable resistance dielectric layer with a first geometry parameter; and a second memory macro comprising a second plurality of memory cells that each comprises a second variable resistance dielectric layer with a second geometry parameter, wherein the first geometry parameter is different from the second geometry parameter thereby causing the first and second memory macros to have first and second endurances. The first and second variable resistance dielectric layers are formed using a single process recipe. The first endurance comprises a maximum number of cycles for which the first plurality of memory cells can transition between first and second logical states, and the second endurance comprises a maximum number of cycles for which the second plurality of memory cells can transition between the first and second logical states. 1. A memory architecture , comprising:a first memory macro comprising a first plurality of memory cells that each comprises a first variable resistance dielectric layer with a first geometry parameter; anda second memory macro comprising a second plurality of memory cells that each comprises a second variable resistance dielectric layer with a second geometry parameter,wherein the first geometry parameter is different from the second geometry parameter thereby causing the first and second memory macros to have first and second endurances,wherein the first and second variable resistance dielectric layers are formed using a single process recipe, andwherein the first endurance comprises a maximum number of cycles for which the first plurality of memory cells can transition between first and second logical states, and the second endurance comprises a maximum number of cycles for which the second plurality of memory cells can transition between the first and second logical states.2. The architecture of wherein the ...

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Номер записи: 76
01-02-2018 дата публикации

THERMAL MANAGEMENT OF SELECTOR

Номер: US20180033825A1
Автор: APODACA Mac D., RUBIN Kurt Allan
Принадлежит:

A non-volatile memory device that limits the temperature excursion of a selector during operation to enhance the cycling life of the non-volatile memory device. A selector, in line with a memory element, may be degraded with repeated temperature excursions as current passes through a stack during the read/write process. The selector changes from an amorphous state to become crystalline thus reducing the life of a memory device. The memory device includes a word line, a bit line disposed perpendicular to the word line, a stack—including a memory element, a selector, and a spacer—disposed between the word line and bit line, and one or more insulating layers surrounding an outer surface of the stack disposed between the word line and bit line. By surrounding the selector with a high thermal conductive heat-sink material, heat is directed away from the selector helping maintain the selector's amorphous state longer. 14-. (canceled)5. The memory device of claim 30 , wherein the spacer layer comprises a material selected from the group consisting of TiN claim 30 , TaN claim 30 , TiSiN claim 30 , TiAlN claim 30 , Co claim 30 , Ni claim 30 , and Cu.6. The memory device of claim 30 , wherein the bit line and word line comprises a material selected from the group consisting of Cu claim 30 , Al claim 30 , and W.7. The memory device of claim 30 , wherein the stack further comprises one or more electrode contacts claim 30 , the electrode contacts comprising a material selected from the group consisting of Ti claim 30 , Ta claim 30 , W claim 30 , Al claim 30 , Cr claim 30 , Zr claim 30 , Nb claim 30 , Mo claim 30 , Hf claim 30 , B claim 30 , C claim 30 , carbon intermixed with other elements claim 30 , conductive nitrides claim 30 , and combinations thereof.8. The memory device of claim 30 , wherein the memory element is selected from the group consisting of PCM claim 30 , RRAM claim 30 , MRAM and other temperature-generating memory elements.9. (canceled)10. The memory device of ...

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Номер записи: 77
01-02-2018 дата публикации

3DIC DEVICE WITH MEMORY

Номер: US20180033881A1
Автор: OR-BACH Zvi, Widjaja Yuniarto
Принадлежит: MonolithIC 3D Inc.

A semiconductor device, the device including: a first stratum including memory periphery circuits; a second stratum including an array of first memory cells, where the first stratum is overlaid by the second stratum; a third stratum including an array of second memory cells, where the second stratum is overlaid by the third stratum, where the first memory cells include a plurality of first polysilicon structures and the second memory cells include a plurality of second polysilicon structures, and where at least one of the first memory cells is self-aligned to at least one of the second memory cells. 1. A semiconductor device , the device comprising:a first stratum comprising memory periphery circuits; 'wherein said first stratum is overlaid by said second stratum;', 'a second stratum comprising an array of first memory cells,'} wherein said second stratum is overlaid by said third stratum,', 'wherein said first memory cells comprise a plurality of first polysilicon structures and said second memory cells comprise a plurality of second polysilicon structures, and', 'wherein at least one of said first memory cells is self-aligned to at least one of said second memory cells., 'a third stratum comprising an array of second memory cells,'}2. The semiconductor device according to claim 1 ,wherein at least one of said plurality of first polysilicon structures is directly connected to at least one of said plurality of second poly silicon structures.3. The semiconductor device according to claim 1 , further comprising: 'wherein said poly silicon pillar comprises at least one of said plurality of first poly silicon structures and at least one of said plurality of second poly silicon structures.', 'a poly silicon pillar,'}4. The semiconductor device according to claim 1 ,wherein said memory periphery circuits comprise a metal interconnect.5. The semiconductor device according to claim 1 ,wherein said memory periphery circuits comprise a metal interconnect, andwherein said ...

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Номер записи: 78
01-02-2018 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20180033961A1
Автор: Chen Ko-Chi, Hsu Chia-Ching, Wang Shen-De, YI LIANG
Принадлежит:

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a bottom metal layer, a resistive random access memory (ReRAM) cell structure, and an upper metal layer. The bottom metal layer is located above the substrate. The ReRAM cell structure is formed on the bottom metal layer. The ReRAM cell structure includes a bottom electrode, a memory cell layer, a top electrode, and a spacer. The memory cell layer is formed on the bottom electrode. The top electrode is formed on the memory cell layer. The spacer is formed on two sides of the bottom electrode, the memory cell layer and the top electrode. The upper metal layer is electrically connected to and directly contacting the top electrode. 1. A semiconductor device , comprising:a bottom metal layer located above the substrate; a bottom electrode;', 'a memory cell layer formed on the bottom electrode;', 'a top electrode formed on the memory cell layer; and', 'a spacer formed on two sides of the bottom electrode, the memory cell layer and the top electrode; and, 'a resistive random access memory (ReRAM) cell structure formed on the bottom metal layer, comprisingan upper metal layer electrically connected to and directly contacting the top electrode.2. The semiconductor device according to claim 1 , further comprising:an inter-metal dielectric formed on the bottom metal layer, wherein the ReRAM cell structure and the upper metal layer are formed within the inter-metal dielectric.3. The semiconductor device according to claim 2 , wherein the inter-metal dielectric has a thickness of 2500-3500 Å.4. The semiconductor device according to claim 2 , further comprising:a via formed in the inter-metal dielectric and located at a lateral side of the ReRAM cell structure, wherein the upper metal layer is electrically connected to the bottom metal layer through the via.5. The semiconductor device according to claim 4 , wherein the via has a height of 1000-1500 Å.6. The ...

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Номер записи: 79
01-02-2018 дата публикации

FIN SELECTOR WITH GATED RRAM

Номер: US20180033963A1
Автор: Quek Elgin, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

A method of fabricating a fin selector with a gated RRAM and the resulting device are disclosed. Embodiments include forming a bottom electrode layer and a hardmask on a semiconductor substrate; etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure; forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively; forming spacers on vertical surfaces of the first and second dummy gate stacks; forming an ILD surrounding the spacers; removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure; forming an RRAM layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; and filling each of the first and second cavities with a top electrode. 1. A phase-change random access memory (PCRAM) comprising:a semiconductor substrate;a heater layer formed on the semiconductor substrate, the heater layer and the semiconductor substrate forming a fin-like structure;an interlayer dielectric (ILD) formed on side surfaces of the fin-like structure;{'sub': 2', '2', '5, 'a GeSbTe(GST) material formed in contact with the heater layer; and'}a top electrode formed on the GST layer, to form the PCRAM.2. The PCRAM according to claim 1 , comprising:a hardmask on the heater layer, the GST layer on a top surface of the ILD on each side of the fin-like structure and on each side surface of the heater layer and the hardmask, and a top electrode on each side of the fin-like structure; orthe GST layer on the heater layer, and the top electrode over the GST layer and the ILD on each side of the fin-like structure.3. The PCRAM according to claim 1 , wherein the heater layer comprises: TaN claim 1 , TiN claim 1 , titanium tungsten (TiW) claim 1 , titanium silicon nitride (TiSiN) claim 1 , or tantalum silicon nitride (TaSiN) claim 1 , and formed to a thickness of 3 to 20 nm ...

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Номер записи: 80
05-02-2015 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20150037931A1
Автор: KUNIYA Takuji
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A method of manufacturing a semiconductor device includes forming a stack of films including a conductive film layer above a semiconductor substrate; patterning the stack of films by dry etching; and cleaning including generation of plasma in an ambient including BCland controlling a bias power to a nonbiased state. 1. A method of manufacturing a semiconductor device comprising:forming a stack of films including a conductive film layer above a semiconductor substrate;patterning the stack of films by dry etching; and{'sub': '3', 'cleaning including generation of plasma in an ambient including BCland controlling a bias power to a nonbiased state.'}2. The method according to claim 1 , wherein forming the stack of films includes:forming a first metal film,forming a polysilicon film including a portion of a first conductivity type and a portion of a second conductivity type stacked one over the other,forming a switching element film, andforming a second metal film.3. The method according to claim 1 , wherein the dry etching is carried out in an etching chamber and the cleaning immediately following the dry etching is carried out without removing the semiconductor substrate from the dry etching chamber.4. The method according to claim 1 , wherein cleaning generates plasma in an ambient including BCl claim 1 , Cl claim 1 , HBr claim 1 , and O.5. The method according to claim 2 , wherein the first metal film comprises tungsten.6. The method according to claim 2 , wherein the portion of the first conductivity type includes at least either of phosphorous and arsenic claim 2 , and the portion of the second conductivity type includes boron.7. The method according to claim 6 , wherein the portion of the first conductivity type is located in a first metal film side claim 6 , and the portion of the second conductivity type is located in a second metal film side.8. The method according to claim 2 , wherein the switching element film includes a metal oxide film or a chalcogenide ...

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Номер записи: 81
17-02-2022 дата публикации

Rram device structure and manufacturing method

Номер: US20220052258A1
Автор: Chung-Liang Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A resistive random access memory cell includes a gate all around transistor and a resistor device. The resistor device includes a first electrode including a plurality of conductive nanosheets. The resistor device includes a high-K resistive element surrounds the conductive nanosheets. The resistor device includes a second electrode separated from the conductive nanosheets by the resistive element.

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Номер записи: 82
31-01-2019 дата публикации

Semiconductor structure with data storage structure and method for manufacturing the same

Номер: US20190035850A1
Автор: Chrong-Jung Lin, Huang-Kui CHEN, Tzong-Sheng Chang, Woan-Yun HSIAO, Ya-Chin King
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure. In addition, the first conductive structure is in direct contact with the first source/drain structure, and the second conductive structure is not in direct contact with the second source/drain structure.

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Номер записи: 83
30-01-2020 дата публикации

SEMICONDUCTOR MEMORY DEVICE INCLUDING PHASE CHANGE MATERIAL LAYERS AND METHOD FOR MANUFACTURING THEREOF

Номер: US20200035752A1
Автор: WU Jau-Yi
Принадлежит:

A semiconductor memory device disposed over a substrate includes a common electrode, a selector material layer surrounding the common electrode, and a plurality of phase change material layers in contact with the selector material layer. 1. A method for manufacturing a semiconductor memory device over a substrate , the method comprising:forming a plurality of conductive wires stacked in a first direction perpendicular to a surface of the substrate and separated by one or more interlayer dielectric (ILD) layers;forming an opening by etching the plurality of conductive wires and the one or more ILD layers;forming a plurality of cavities by recessing the plurality of conductive wires in the opening;forming a plurality of phase change material layers in the plurality of cavities;forming a selector material layer in contact with the plurality of phase change material layers; andforming a common electrode in contact with the selector material layer.2. The method of claim 1 , wherein the plurality of conductive wires have a different length from each other.3. The method of claim 1 , further comprising forming a lower electrode in a lower ILD layer claim 1 ,wherein in the forming the opening, an upper surface of the lower electrode is exposed.4. The method of claim 3 , wherein the common electrode is formed in contact with the lower electrode.5. The method of claim 1 , wherein each of the plurality of phase change material layers is formed in a ring shape.6. The method of claim 1 , wherein the plurality of phase change material layers is formed by an atomic layer deposition method.7. The method of claim 1 , wherein the selector material layer is formed by an atomic layer deposition method.8. The method of claim 1 , wherein the plurality of phase change memory layers includes one or more selected from the group consisting of Ge claim 1 , Ga claim 1 , Sn and In claim 1 , and one or more selected from the group consisting of Sb and Te.9. The method of claim 8 , wherein the ...

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Номер записи: 84
30-01-2020 дата публикации

PHASE CHANGE MEMORY STRUCTURE TO REDUCE POWER CONSUMPTION

Номер: US20200035919A1
Автор: Liu Shih-Chang, Tsai Yi Jen
Принадлежит:

A phase change memory (PCM) cell with enhanced thermal isolation and low power consumption is provided. In some embodiments, the PCM cell comprises a bottom electrode, a dielectric layer, a heating element, and a phase change element. The dielectric layer is on the bottom electrode. The heating element extends through the dielectric layer, from a top of the dielectric layer to the bottom electrode. Further, the heating element has a pair of opposite sidewalls laterally spaced from the dielectric layer by a cavity. The phase change element overlies and contacts the heating element. An interface between the phase change element and the heating element extends continuously respectively from and to the opposite sidewalls of the heating element. Also provided is a method for manufacturing the PCM cell. 1. A phase change memory (PCM) cell comprising:a bottom electrode;a first dielectric layer overlying the bottom electrode, wherein the first dielectric layer has a first dielectric sidewall;a phase change element overlying the first dielectric layer;a heater element extending through the first dielectric layer, from the bottom electrode to the phase change element, wherein the heater element has a first heater sidewall facing the first dielectric sidewall and separated from the first dielectric sidewall by a cavity; anda second dielectric layer lining and partially filling the cavity.2. The PCM cell according to claim 1 , wherein the second dielectric layer directly contacts the first dielectric sidewall and the first heater sidewall.3. The PCM cell according to claim 1 , wherein a width of the heater element increases from the bottom electrode to the phase change element.4. The PCM cell according to claim 1 , wherein the second dielectric layer has a ring-shaped profile at the first dielectric sidewall and the first heater sidewall.5. The PCM cell according to claim 1 , wherein the first dielectric layer has a second dielectric sidewall on an opposite side of the heater ...

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Номер записи: 85
04-02-2021 дата публикации

3D RRAM CELL STRUCTURE FOR REDUCING FORMING AND SET VOLTAGES

Номер: US20210036057A1
Автор: Chen Tzu-Yu, Hsieh Te-Hsien, Tseng Yuan-Tai, Tu Kuo-Chi
Принадлежит:

An RRAM cell stack is formed over an opening in a dielectric layer. The dielectric layer is sufficiently thick and the opening is sufficiently deep that an RRAM cell can be formed by a planarization process. The resulting RRAM cells may have a U-shaped profile. The RRAM cell area includes contributions from a bottom portion in which the RRAM cell layers are stacked parallel to the substrate and a side portion in which RRAM cell layers are stacked roughly perpendicular to the substrate. The combined side and bottom portions of the curved RRAM cell provide an increased area in comparison to a planar cell stack. The increased area lowers forming and set voltages for the RRAM cell. 1. An integrated circuit (IC) device , comprising:a substrate having a surface;a metal interconnect structure formed over the surface; anda resistance switching random access memory (RRAM) cell formed within the metal interconnect structure, the RRAM cell comprising a bottom electrode layer, a top electrode layer, and a switching layer between the bottom electrode layer and the top electrode layer;wherein a top of the top electrode layer and a top of the bottom electrode have equal height over the substrate.2. The IC device of claim 1 , wherein:the RRAM cell has edges that comprise the bottom electrode layer, the switching layer, and the top electrode layer; andthe edges all lie in a plane.3. The IC device of claim 2 , wherein the plane is parallel to the surface.4. The IC device of claim 1 , wherein the bottom electrode layer and the switching layer terminate at edges that form closed loops aligned in a plane.5. The IC device of claim 1 , wherein the bottom electrode layer encompasses the switching layer.6. The IC device of claim 5 , wherein the switching layer encompasses the top electrode layer.7. The IC device of claim 1 , wherein the bottom electrode layer is surrounded by low κ dielectric layer.8. The IC device of claim 1 , wherein the bottom electrode layer is surrounded by and ...

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Номер записи: 86
04-02-2021 дата публикации

MEMRISTOR AND NEURAL NETWORK USING SAME

Номер: US20210036223A1
Автор: KIMURA Mutsumi, MIYAMAE Yoshinori, SUGISAKI Sumio
Принадлежит:

Provided is a memristor that can be manufactured at a low temperature, and does not include metals of which resources might be depleted. This memristor includes a first electrode, a second electrode, and a memristor layer of an oxide having elements of Ga, Sn, and oxygen, disposed between the first electrode and the second electrode. When voltage is applied to the first electrode with respect to the second electrode, the voltage being positive or negative, a current flows; when voltage of a data-set voltage value is applied, a state is transitioned from a high-resistance state to a low-resistance state; and when voltage of a data-reset voltage value that is of an opposite sign to that of the data-set voltage value is applied, the state is transitioned from a low-resistance state to a high-resistance state. 1. A memristor , comprising:a first electrode;a second electrode; anda memristor layer of an oxide having elements of Ga, Sn, and oxygen, disposed between the first electrode and the second electrode, wherein,when voltage is applied to the first electrode with respect to the second electrode, the voltage being positive or negative, a current flows; when voltage of a data-set voltage value is applied, a state is transitioned from a high-resistance state to a low-resistance state; and when voltage of a data-reset voltage value that is of an opposite sign to that of the data-set voltage value is applied, the state is transitioned from a low-resistance state to a high-resistance state.2. The memristor according to claim 1 , whereinthe oxide is an amorphous oxide.3. The memristor according to claim 1 , whereinthe first electrode and/or the second electrode is/are formed by deposition of aluminum.4. A neural network claim 1 , comprising a plurality of neuron circuits; and a plurality of synapse devices claim 1 , wherein{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the synapse devices include the memristor according to .'}5. A neural network claim 1 , comprising a ...

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Номер записи: 87
11-02-2016 дата публикации

RESISTIVE MEMORY DEVICE WITH ZERO-TRANSISTOR, ONE-RESISTOR BIT CELLS INTEGRATED WITH ONE-TRANSISTOR, ONE-RESISTOR BIT CELLS ON A DIE

Номер: US20160043137A1
Автор: Kang Seung Hyuk, Lu Yu
Принадлежит:

A resistive memory array includes an array of one-transistor, one-resistor (1T1R) bit cells on a die. The resistive memory array also includes an array of zero-transistor, one-resistor (0T1R) bit cells arranged with the array of 1T1R bit cells on the same die. 1. A resistive memory array , comprising:an array of one-transistor, one-resistor (1T1R) bit cells on a die; andan array of zero-transistor, one-resistor (0T1R) bit cells arranged with the array of 1T1R bit cells on the same die.2. The resistive memory array of claim 1 , in which the array of 0T1R bit cells is stacked on the array of 1T1R bit cells.3. The resistive memory array of claim 1 , in which a 0T1R bit cell is disposed within a footprint of a 1T1R bit cell.4. The resistive memory array of claim 1 , in which the array of 0T1R bit cells and the array of 1T1R bit cells are integrated within different back-end-of-line (BEOL) interconnect layers.5. The resistive memory array of claim 1 ,in which the array of 0T1R bit cells comprises a resistive random access memory (RRAM), a phase change memory (PCM) or a spin-transfer-torque magnetoresistive random access memory (STT-MRAM), andin which the array of 1T1R bit cells comprises RRAM, PCM or STT-MRAM.6. The resistive memory array of claim 1 , in which each 1T1R bit cell comprises a single-crystal semiconductor device directly coupled to a resistor.7. The resistive memory array of claim 6 , in which the resistor comprises a resistive random access memory (RRAM) element claim 6 , a conductive-bridge-RAM (CBRAM) element claim 6 , a phase change memory (PCM) element claim 6 , a magnetic random access memory (MRAM) magnetic tunnel junction (MTJ) or a spin transfer torque magnetoresistive random access memory (STT-MRAM).8. The resistive memory array of claim 1 , in which each 0T1R bit cell comprises a resistor claim 1 , the resistor comprising a resistive random access memory (RRAM) element claim 1 , a conductive-bridge-RAM (CBRAM) element claim 1 , a phase change ...

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Номер записи: 88
11-02-2016 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20160043138A1
Автор: YI Jae-Yun
Принадлежит:

A semiconductor device includes a memory block including a transistor region and a memory region. A variable resistance layer of the memory region acts as a gate insulating layer in the transistor region. 120-. (canceled)21. A method for fabricating a semiconductor device , comprising:forming an interlayer dielectric defining a transistor region and a memory region;forming a plurality of gate electrodes on the interlayer dielectric in the transistor region and forming a plurality of first conductive lines on the interlayer dielectric in the memory region;forming a first insulating layer on the interlayer dielectric;forming a second insulating layer on the first insulating layer; andforming a first electrode and a second electrode on the second insulating layer in the transistor region to overlap a portion of the gate electrode and forming a plurality of second conductive lines crossing over the first conductive lines in the memory region.22. The method of claim 21 , further comprising:exposing the first insulating layer in the memory region by selectively etching the second insulating layer, after the forming of the second insulating layer.23. The method of claim 21 , further comprising:dividing the second insulating layer of the transistor region and the second insulating layer of the memory region by selectively etching the second insulating layer, after the forming of the second insulating layer.2423. The method of claim 21 , further comprising:dividing the first insulating layer of the transistor region and the first insulating layer of the memory region by selectively etching the first insulating layer, after the forming of the second insulating layer.25. The method of claim 21 , wherein the first insulating layer and the second insulating layer comprise an oxide layer claim 21 , and the oxide layer includes a plurality of oxygen vacancies.26. The method of claim 25 , wherein the second insulating layer comprises at least one material selected from the group ...

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Номер записи: 89
08-02-2018 дата публикации

Semiconductor memory device

Номер: US20180040561A1
Автор: Bong-Soo Kim, Daeik Kim, Eunjung Kim, Hui-jung Kim, Keunnam Kim, Yoosang Hwang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

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Номер записи: 90
08-02-2018 дата публикации

SEMICONDUCTOR DEVICE AND COMPOSITE SEMICONDUCTOR DEVICE

Номер: US20180040601A1
Автор: Kihara Seiichiro
Принадлежит: SHARP KABUSHIKI KAISHA

Provided is a lateral field effect transistor in which response performance is improved. In a lateral field effect transistor, a block is arranged closer to a gate terminal than a Zener diode. 1. A semiconductor device comprising:a plurality of normally-off or normally-on field effect transistors;a gate terminal;a drain terminal;a source terminal;each of the field effect transistors having a gate electrode connected to the gate terminal, a drain electrode connected to the drain terminal, and a source electrode connected to the source terminal; anda Zener diode that has an anode electrode connected to the source terminal and a cathode electrode connected to the drain terminal, whereinthe field effect transistors are each arranged to have a distance from the gate terminal increasing in order and form a block, andthe block is arranged closer to the gate terminal than the Zener diode.2. The semiconductor device according to claim 1 , whereinthe Zener diode is provided at one end,the gate terminal is provided at the other end opposite the one end, anda length between the Zener diode and the gate terminal in a first direction is longer than a length in a second direction orthogonal to the first direction.3. The semiconductor device according to claim 1 , whereineach of the field effect transistors is a normally-off field effect transistor,the gate terminal and any one of the drain terminal and the source terminal are formed on a first same surface, andthe other of the drain terminal and the source terminal is formed on a back surface of the first same surface.4. A composite semiconductor device claim 1 , comprising:{'claim-ref': {'@idref': 'CLM-00003', 'claim 3'}, 'the semiconductor device according to ;'}a normally-on field effect transistor that has a gate electrode, a drain electrode, and a source electrode;a second gate terminal;a second drain terminal; anda second source terminal, whereinthe second drain terminal is connected to the drain electrode of the normally-on ...

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Номер записи: 91
08-02-2018 дата публикации

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20180040670A1
Автор: Glova Alvin Oliver, Sim Joon-Seop
Принадлежит:

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a first portion of a variable resistance element, the first portion having an island shape and including at least a free layer which has a variable magnetization direction; a second portion of the variable resistance element, the second portion having a line shape which extends in a direction over the first portion and including at least a pinned layer which has a pinned magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer. 1. An electronic device comprising a semiconductor memory ,wherein the semiconductor memory comprises:a variable resistance element including a first portion having a first shape and including a free layer which exhibits a variable magnetization direction, a second portion having a second shape different from the first shape, disposed over the first portion and including a pinned layer with a pinned magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer.2. The electronic device of claim 1 , wherein:the second portion is shaped to extend along an extended direction,a width of the first portion along a direction perpendicular to the extended direction decreases from a top to a bottom of the first portion along a vertical direction perpendicular to the extended direction, anda width of the second portion along the direction perpendicular to the extended direction increases from a top of the second portion to a bottom of the second portion along the vertical direction.3. The electronic device of claim 1 , wherein the tunnel barrier layer is included in the first portion and has a sidewall aligned with a sidewall of the free layer.4. The electronic device of claim 1 , wherein the tunnel barrier layer is included in the second portion and has a sidewall aligned with a sidewall of the pinned layer.5. The electronic device of claim 1 , wherein the ...

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Номер записи: 92
24-02-2022 дата публикации

Data Storage Cell, Memory, and Memory Fabrication Method Thereof

Номер: US20220059616A1
Автор: Hsueh Sheng-Yuan, Lee Kuo-Hsing
Принадлежит:

The invention discloses a memory fabrication method. The memory fabrication method includes forming a plurality of gate electrode lines to respectively form a plurality of gates of a plurality of data storage cells, and forming a plurality of conductive lines. The plurality of data storage cells are arranged in an array. Each of the plurality of conductive lines is coupled to two of the plurality of gate electrode lines. Each of the plurality of conductive lines at least partially overlaps the two gate electrode lines of the plurality of gate electrode lines. 1. A memory fabrication method , comprising:forming a plurality of gate electrode lines to respectively form a plurality of gates of a plurality of data storage cells, wherein the plurality of data storage cells are arranged in an array; andforming a plurality of conductive lines, wherein each of the plurality of conductive lines is coupled to two of the plurality of gate electrode lines, and each of the plurality of conductive lines at least partially overlaps the two gate electrode lines of the plurality of gate electrode lines.2. The memory fabrication method of claim 1 , further comprising:forming a plurality of bit lines, wherein the plurality of bit lines are parallel to the plurality of conductive lines, and at least four adjacent ones of the plurality of bit lines are located between two adjacent and aligned ones of the plurality of conductive lines.3. The memory fabrication method of claim 1 , further comprising:forming a plurality of source lines, wherein the plurality of source lines are parallel to the plurality of conductive lines, and two of the plurality of conductive lines respectively adjacent to opposite sides of one of the plurality of source lines are staggered and non-aligned.4. The memory fabrication method of claim 1 , wherein each of the plurality of conductive lines is electrically connected to and contacts two of the plurality of gate electrode lines.5. The memory fabrication method of ...

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Номер записи: 93
24-02-2022 дата публикации

Semiconductor storage device

Номер: US20220059617A1
Автор: Yusuke NIKI
Принадлежит: Kioxia Corp

A memory includes first signal-lines divided into groups. Global signal lines correspond to the first signal-lines. The global signal-lines include a selected global signal-line and a non-selected global signal-line. First transistors correspond to the first signal-lines. The first transistors are connected between a corresponding first signal-line and any of the global signal-lines. Selection signal-lines correspond to the groups. The selection signal-lines are connected to gate electrodes of the first transistors included in a corresponding group. Second transistors are connected between the first signal-lines that belong to adjacent two of the groups. When one of the first signal-lines which is electrically connected to the selected global signal-line is a selected first signal-line, the first transistors corresponding to one of the groups which includes the selected first signal-line is in a conducting state. One of the second transistors which is connected to the selected first signal-line is in a non-conducting state.

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Номер записи: 94
19-02-2015 дата публикации

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE, VARIABLE RESISTIVE MEMORY DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME

Номер: US20150048293A1
Автор: Park Nam Kyun
Принадлежит: SK HYNIX INC.

A three-dimensional semiconductor device, a resistive variable memory device including the same, and a method of manufacturing the same are provided. The 3D semiconductor device includes a source formed of a first semiconductor material, a channel layer formed on the source and formed of the first semiconductor material, a lightly doped drain (LDD) region formed on the channel layer and formed of a second semiconductor material having a higher oxidation rate than that of the first semiconductor material, a drain formed on the LDD region and formed of the first semiconductor material, and a gate insulating layer formed on outer circumferences of the channel layer, the LDD region, and the drain. 1. A three-dimensional (3D) semiconductor device , comprising:a source formed of a first semiconductor material;a channel layer formed on the source and formed of the first semiconductor material;a lightly doped drain (LDD) region formed on the channel layer and formed of a second semiconductor material having a higher oxidation rate than that of the first semiconductor material;a drain formed on the LDD region and formed of the first semiconductor material; anda gate insulating layer formed on outer circumferences of the channel layer, the LDD region, and the drain.2. The 3D semiconductor device of claim 1 , wherein the first semiconductor material is silicon.3. The 3D semiconductor device of claim 2 , wherein the second semiconductor material is silicon germanium (SiGe).4. The 3D semiconductor device of claim 1 , wherein a portion of the gate insulating layer claim 1 , formed on the outer circumference of the LDD region claim 1 , is thicker than portions of the gate insulating layer claim 1 , formed on the outer circumferences of the channel layer and the drain.5. The 3D semiconductor device of claim 1 , further comprising a gate formed to surround an outer circumference of the gate insulating layer.6. The 3D semiconductor device of claim 5 , wherein the gate is formed to ...

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Номер записи: 95
19-02-2015 дата публикации

SEMICONDUCTOR DEVICE HAVING FIN GATE, RESISTIVE MEMORY DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME

Номер: US20150048295A1
Автор: Park Nam Kyun
Принадлежит:

A semiconductor device having a fin gate that improves an operation current, and a method of manufacturing the same are provided. The semiconductor device includes an active pillar formed on a semiconductor substrate, and including a first region and a second region surrounding at least one surface of the first region, and a fin gate extending to overlap an upper surface and a lateral surface of the active pillar. The first region of the active pillar is formed of a semiconductor layer having a lattice constant smaller than that of the second region of the active pillar. 1. A semiconductor device , comprising:an active pillar formed on a semiconductor substrate, and including a first region and a second region surrounding at least one surface of the first region; anda fin gate extending to overlap an upper surface and a lateral surface of the active pillar,wherein the first region of the active pillar is formed of a semiconductor layer having a lattice constant smaller than that of the second region of the active pillar.2. The semiconductor device of claim 1 , further comprising a gate insulating layer interposed between the active pillar and the fin gate.3. The semiconductor device of claim 1 , wherein the active pillar has a longitudinal axis extending in a direction substantially perpendicular to a longitudinal axis of the fin gate claim 1 , andthe first region extends to a direction substantially parallel to the longitudinal axis of the active pillar.4. The semiconductor device of claim 1 , wherein at least one of the semiconductor substrate and the second region includes a Si-containing material.5. The semiconductor device of claim 1 , wherein the semiconductor layer includes SiC claim 1 , AlN claim 1 , GaN claim 1 , ZnS claim 1 , ZnO claim 1 , ZnSe claim 1 , CdS claim 1 , BP claim 1 , or InN.6. The semiconductor device of claim 1 , wherein the first region is an SiC layer and the first region is formed of a first C-low concentration-SiC layer that contains a ...

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Номер записи: 96
19-02-2015 дата публикации

Semiconductor device having fin gate, resistive memory device including the same, and method of manufacturing the same

Номер: US20150048296A1
Автор: Nam Kyun PARK
Принадлежит: SK hynix Inc

A semiconductor device having a fin gate that improves an operation current, and a method of manufacturing the same. The semiconductor device includes an active pillar formed on a semiconductor substrate, the active pillar including an inner region and an outer region surrounding the inner region, and a fin gate overlapping an upper surface and a lateral surface of the active pillar. The inner portion of the active pillar includes a first semiconductor layer having a first lattice constant, and the outer region of the active pillar includes a second semiconductor layer having a second lattice constant smaller than the first lattice constant.

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Номер записи: 97
07-02-2019 дата публикации

MEMRISTIVE CONTROL CIRCUITS WITH CURRENT CONTROL COMPONENTS

Номер: US20190043573A1
Автор: Buchanan Brent, STRACHAN John Paul, Zheng Le
Принадлежит:

In one example in accordance with the present disclosure a control circuit is described. The control circuit includes a source following component to receive an input voltage and output a switching voltage. The circuit also includes an input leg of a current mirror coupled to the source following component. The input leg of the current mirror replicates the switching voltage to an output leg of the current mirror of a memristive bit cell. The circuit also includes a number of current control components. At least one of the current control components enforces a constant current through the source following component and other current control components maintain the input leg of the current mirror and the output leg of the current mirror at the same current. 1. A control circuit for a memristive device comprising:a source following component to receive an input voltage and output a switching voltage;an input leg of a current mirror coupled to the source following component, the input leg of the current mirror to replicate the switching voltage to an output leg of the current mirror of a memristive bit cell; and enforce a constant current through the source following component; and', 'maintain the input leg of the current mirror and the output leg of the current mirror at the same current., 'a number of current control components to2. The control circuit of claim 1 , wherein the source following component is a transistor to receive the input voltage at a gate of the transistor.3. The control circuit of claim 1 , wherein the input voltage is a non-square voltage pulse.4. The control circuit of claim 1 , wherein the input voltage is a square voltage pulse.5. The control circuit of claim 1 , wherein the current control components comprise:a first current control component comprising a transistor to enforce the constant current through the source following component; anda number of additional current control components comprising transistors to maintain a similar current ...

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Номер записи: 98
07-02-2019 дата публикации

Phase-Change Memory Device with Drive Circuit

Номер: US20190043574A1
Автор: DISEGNI Fabio Enrico Carlo, Fidone Massimo, Manfré Davide, TORTI Cesare
Принадлежит:

A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET. 1. A memory device comprising:an array of phase-change material (PCM) memory cells;a word line coupled to the array of PCM memory cells;a low voltage circuit comprising an output coupled to the word line; anda high voltage circuit comprising an output coupled to the word line, wherein the low voltage circuit and the high voltage circuit are formed on the same semiconductor substrate, wherein the low voltage circuit comprises a first silicon-on-insulator transistor comprising a first gate dielectric and the high voltage circuit comprises a second silicon-on-insulator transistor comprising a second gate dielectric, wherein the second gate dielectric is thicker than the first gate dielectric.2. The memory device of claim 1 , wherein the low voltage circuit comprises:a first pull-up transistor;a first pull-down transistor;a second pull-up transistor; anda second pull-down transistor.3. The memory device of claim 2 , wherein gate terminals of the first pull-up transistor and of the first pull-down transistor are coupled to a control node.4. The memory device of claim 3 , wherein the control node is coupled to an output terminal of a logic inverter.5. The memory device of claim 3 , wherein a drain terminal of the first pull-up ...

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Номер записи: 99
06-02-2020 дата публикации

HIGH DENSITY MEMORY ARCHITECTURE USING BACK SIDE METAL LAYERS

Номер: US20200043980A1
Автор: MORROW Patrick, Wang Yih
Принадлежит: Intel Corporation

A microelectronic memory having metallization layers formed on a back side of a substrate, wherein the metallization layers on back side may be used for the formation of source lines and word lines. Such a configuration may allow for a reduction in bit cell area, a higher memory array density, and lower source line and word line resistances. Furthermore, such a configuration may also provide the flexibility to independently optimize interconnect performance for logic and memory circuits. 1. A microelectronic memory comprising:a substrate comprising a single material structure, wherein the substrate has a front surface and an opposing back surface,a memory bitcell transistor on the substrate front surface, wherein the memory bitcell transistor includes at least one source/drain structure formed in the substrate, wherein the source line is electrically connected to the at least one source/drain structure;a word line formed on the substrate back surface;a word line strap comprising the word line on the substrate back surface electrically connected to a word line within a memory bitcell transistor;a source line positioned between the word line and the substrate; anda memory cell transistor array on the substrate front surface.2. The microelectronic memory of claim 1 , wherein the source line is electrically connected to the at least one source/drain structure through a deep diffusion contact within the substrate.3. The microelectronic memory of claim 1 , wherein the word line on the substrate back surface is electrically connected to a word line within a memory bitcell transistor through a source/drain structure and a deep diffusion contact within the substrate.4. The microelectronic memory of claim 1 , wherein the memory cell transistor array comprises a plurality of resistance based memory transistors.5. The microelectronic memory of claim 1 , further including the source line directly contacting the substrate back surface.6. The microelectronic memory of claim 1 , ...

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Номер записи: 100