Steuerbares Halbleiterelement mit erhoehter Zuendgeschwindigkeit

HOCHFREQUENZTRANSISTOR UND VERFAHREN ZU SEINER HERSTELLUNG

Halbleiterbauelement,insbesondere Flaechentransistor

IMPROVEMENTS IN AND RELATING TO SEMICONDUCTOR DEVICES

... 1,214,151. Semi-conductor devices. ASSOCIATED SEMICONDUCTOR MFGS. Ltd. 5 Feb., 1968 [7 Feb., 1967], No. 5717/67. Heading H1K. A semi-conductor device comprises a semiconductor wafer with at least first, second and third regions 31, 32, 33 of successively opposite conductivity type, the first region 31, which may be annular, underlying a depression 39 in one face of the wafer and the PN junction 36 between the second and third regions having a stepped formation under the first region with its periphery extending to a bevelled surface 45 of the body. The peripheral surface of the wafer is bevelled and the angle between this junction 36 and the surface is between 170 and 180 degrees. Electrodes are connected to the regions. In the embodiment shown in Fig. 3 where the device is a thyristor a further conductivity region 34 exists in the wafer opposite the depression 39, and a further bevel exists at the peripheral surface at an angle of between 15 and 60 degrees with the PN junction 37. The ...

Semiconductive pnpn devices

... 909,870. Semi-conductor devices, WESTERN ELECTRIC CO. Inc. May 30, 1961 [June 10, 1960], No. 19470/61. Class 37. The turn-off gain of a PNPN(NPNP) device is made large by arranging that the total is slightly greater than unity, the of one of the included transistors being less than but close to unity and the other greater than but close to zero. In the arrangement shown in Fig. 2, the NPN transistor is made by conventional methods to have a gain of about 0.99 but the PNP transistor is made to have a gain of about 0.05 by making the injection efficiency low. This is achieved in practice by making the sheet resistance of P zone 24 much higher than that of base zone 23. Actual figures are 1000 ohms/ square for the P zone and 50 ohms/square for the N zone. The device may be produced by starting with a N-type silicon base 23, the P and N zones 22, 21 being produced by successive diffusion of boron and phosphorous respectively and P region 24 is produced by phosphorous diffusion. In a further ...

ORGANIC SEMICONDUCTOR COMPOSITIONS WITH NANO-PARTICLES

DREIENDIGER METAL INSULATOR TRANSITION SWITCH, SCHALTSYSTEM THEREBY AS WELL AS PROCEDURES FOR THE CONTROLLING OF THE METAL INSULATOR TRANSITION OF IT

Semiconductor device

SEMICONDUCTOR DEVICE

Steuerbarer Gleichrichter

Steuerbares Halbleiterventil

Steuerbares Halbleitergleichrichterelement für Starkstrom

Verfahren zur Herstellung von pn-Übergängen in einem Grundkörper aus einkristallinem Halbleitermaterial

Procédé de réalisation d'un composant semiconducteur à shunt d'émetteur et composant obtenu par la mise en oeuvre de ce procédé

Steuerbare Halbleiteranordnung

Halbleitervorrichtung und Verfahren zu ihrer Herstellung

Steuerbare bistabile Halbleiteranordnung

Steuerbarer Halbleitergleichrichter

THYRISTOR.

Halbleiterelement mit mindestens drei pn-Übergängen

Procédé de réalisation de shunts ohmiques d'émetteur sur un composant semi-conducteur

Halbleiter-Schalteinrichtung

Steuerbarer Halbleitergleichrichter

Soupape commandée, à semi-conducteur monocristallin

Gleichrichterschaltung

Halbleiterelement

Halbleiterelement mit mindestens einer Steuerelektrode

Steuerbares Halbleiterelement

Semiconductor device

Manufacturing method of TFT substrate and manufactured TFT substrate

Controlled valve, with single-crystal semiconductor

System semiconductor with four layers and isolated base

PROCESS FOR MAKING SEMICONDUCTOR COMPONENTS

D-flip flop using integrated injection logic techniques - has surface area reduced by clocking set and reset over inverters

TUNNEL FET AND METHODS FOR FORMING THE SAME

Styrbar halvledaranordning av PNPN-typ

Low leakage diodes

A diode includes an anode of a first conductivity type; a first cathode of the first conductivity type; and a second cathode of a second conductivity type opposite the first conductivity type. A lightly-doped region of the first conductivity type is under and vertically overlaps the anode and the first and the second cathodes. The portion of the lightly-doped region directly under the second cathode is fully depleted at a state when no bias voltage is applied between the anode and the second cathode.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

A semiconductor device includes: a semiconductor substrate, an upper electrode, a lower electrode and a gate electrode. In the semiconductor substrate, a body region, a pillar region, and a barrier region are formed. The pillar region has an n-type impurity, is formed on a lateral side of the body region, and extends along a depth from a top surface of the semiconductor substrate to a lower end of the body region. The barrier region has an n-type impurity and is formed on a lower side of the body region and the pillar region. The barrier region is formed on the lower side of the pillar region. An n-type impurity concentration distribution in a depth direction in the pillar region and the barrier region has a maximum value in the pillar region. The n-type impurity concentration distribution has a folding point on a side deeper than the maximum value.

DIODE

A diode has a semiconductor layer and cathode and anode electrodes on a surface of the semiconductor layer. The semiconductor layer has cathode and anode regions respectively contacting the cathode and anode electrodes. The anode region has a first diffusion region having high surface concentration, a second diffusion region having intermediate surface concentration, and a third diffusion region having low surface concentration. The first diffusion region is covered with the second and third diffusion regions. The second diffusion region has a first side surface facing the cathode region, a second side surface opposite to the cathode region, and a bottom surface extending between the first and second side surfaces. The third diffusion region covers at least one of the first corner part connecting the first side surface with the bottom surface and the second corner part connecting the second side surface with the bottom surface.

Halbleiterschalter

Halbleiterbauelement mit gleichrichtenden Übergängen sowie Herstellungsverfahren zur Herstellung desselben

Halbleiterbauelement aufweisend: – einen Halbleiterkörper mit einem ersten Halbleitergebiet (11) vom ersten Leitungstyp; – mindestens einen ersten gleichrichtenden Übergang (1) zum ersten Halbleitergebiet (11); – mindestens einen zweiten gleichrichtenden Übergang (2) zum ersten Halbleitergebiet (11); und – mindestens einen dritten gleichrichtenden Übergang (3) zum ersten Halbleitergebiet (11); – wobei die drei gleichrichtenden Übergänge (1, 2, 3) jeweils eine unterschiedlich hohe Barrierenhöhe aufweisen, wobei der zweite gleichrichtende Übergang (2) eine niedrigere Barrierenhöhe als der erste gleichrichtende Übergang (1) aufweist, der erste gleichrichtende Übergang (1) eine niedrigere+ Barrierenhöhe als der dritte gleichrichtende Übergang (3) aufweist, und der zweite gleichrichtende Übergang (2) zwischen erstem und drittem gleichrichtenden Übergang (1, 3) angeordnet ist.

Halbleitervorrichtung

Die Erfindung schafft eine Halbleitervorrichtung, bei der der Nutzer mit niedrigen Kosten eine gewünschte Schaltung (Heruntertransformationsschaltung (oder Herauftransformations/Heruntertransformations-Schaltung) und Herauftransformationsschaltung) auswählen kann. Eine Halbleitervorrichtung in Übereinstimmung mit der Erfindung enthält ein Diodenelement (10) und ein Schaltelement (IGBT) (20). Ein Anodenanschluss (T2) des Diodenelements (10) und ei (20) sind in einer vorgegebenen Entfernung voneinander benachbart angeordnet. Außerdem sind ein Katodenanschluss (T4) des Diodenelements (10) und der andere Hauptelektrodenanschluss (T3) des Schaltelements (20) in einer anderen vorgegebenen Entfernung voneinander benachbart angeordnet.

VERGRABENE ISOLIERUNGSGEBIETE UND VERFAHREN ZU DEREN BILDUNG

Ein Verfahren zum Herstellen einer Halbleitervorrichtung umfasst ein Ausbilden eines vergrabenen Isolierungsgebiets innerhalb eines Substrats, indem das Substrat unter Verwendung von Ätz- und Abscheidungsprozessen bearbeitet wird. Über dem vergrabenen Isolierungsgebiet wird an einer ersten Seite des Substrats eine Halbleiterschicht gebildet. Vorrichtungsgebiete werden in der Halbleiterschicht geschaffen. Das Substrat wird von einer zweiten Seite des Substrats aus abgedünnt, um das vergrabene Isolierungsgebiet freizulegen. Das vergrabene Isolierungsgebiet wird selektiv entfernt, um eine untere Oberfläche des Substrats freizulegen. Unter der unteren Oberfläche des Substrats wird ein leitfähiges Gebiet ausgebildet.

Verfahren zum Kontaktieren von mindestens zwei benachbarten Zonen entgegengesetzten Leitungstyps eines steuerbaren Halbleiterbauelementes

Thin film transistor

Thin film transistor

A thin film transistor 100 has a source 30 and a drain 50 above a gate 10. A channel 70 is formed between an edge 32 of the source 30 and an edge 52 of the drain 50. The source edge 32 and the drain edge 52 are nonlinear, and the size of the channel 50 decreases from 4.5mm at its middle to smaller than 4.5mm (but greater than 2.5mm) at its ends. The source edge 32 has three segments. A first and third segment [322, 326 figure 4] are arranged symmetrically at ends of a second segment [324 figure 4]. The second segment may be linear. The first and third segments may be curved or straight. The source edge 32 and the drain edge 52 may be the same shape. The channel shape may provide more consistent light transmittance at each part of the channel during an exposure process.

Controllable semi-conductor device

... 1,106,637. Semi-conductor devices. BROWN. BOVERI & CO. Ltd. 20 April, 1967 [22 April, 1966], No. 18203/67. Heading H1K. A controlled rectifier consists of a PNP structure in which one of the outer P zones, 2, has a P + region 6 incorporated in one part of its surface, an N+ region 4 in another part of the same surface, and a common electrode 7 linking these two regions. The resulting structure thus comprises a PNPN + device shunted by a PNPP+ device. In the N region common to both devices the dopant concentration is non- uniform, such that the inner N zone II of the PNPP+ device is more highly doped than the inner N zone I of the PNPN+ device. This ensures that breakdown occurs in the former in preference to the latter device, and the Specification establishes with respect to I-V diagrams (Figs. 2 to 4, not shown) that this property enhances the performance as a controlled rectifier of the structure as a whole. The device is made by: taking an N-type ...

Divided base four-layer semiconductor device

... 1,021,147. Semi-conductor devices. TEXAS INSTRUMENTS Inc. April 3, 1963 [Nov. 13, 1962], No. 13230/63. Heading H1K. A four-layer semi-conductor device comprises first and second zones of opposite conductivity types, a plurality of mutually spaced third zones, contiguous with, and of opposite conductivity type to, the second zone, and a plurality of fourth zones each contiguous with one of, and of opposite conductivity type to, the third zones. Ohmic connections are made to each of the third zones and to the first zone and a common ohmic connection is made to the plurality of fourth zones. In one embodiment the first, second and third zones 12, 10, 11, Fig. 1 (not shown), are prepared of P-, N- and P-type material respectively and the fourth layer 13, of N-type material, is formed to cover part only of the surface of the third layer 11. The surface is then etched to provide a channel 14 which extends completely through the third and fourth layers so as to divide each of these two layers ...

SEMICONDUCTOR DEVICES

... 1460037 Semi-conductor devices SONY CORP 20 Dec 1973 [29 Dec 1972] 59093/73 Heading H1K A high gain, low noise emitter structure for a transistor or thyristor comprises a relatively low-doped emitter portion 4, Fig. 2, forming a PN junction with the base region 3, and a more heavily-doped emitter portion 5 spaced from the emitter-base junction by less than the minority carrier diffusion length in the portion 4 and forming with the portion 4 on energy barrier such that the minority carrier flows in opposite directions are substantially balanced, the emitter portion 5 being narrower than the portion 4. Fig. 2 also shows preferred doping levels in the various regions and illustrates, in curve (c), the substantially constant minority carrier concentration achieved across the emitter portion 4 by the invention. Fig. 3 illustrates a Si integrated-circuit having, at the right-hand side, a conventional PNP transistor and, at the left-hand side, an NPN transistor using the inventive emitter structure ...

Thyristors

... 1,162,140. PNPN switches. JOSEPH LUCAS (INDUSTRIES) Ltd. 8 Nov., 1966 [6 Dec., 1965], No. 51618/65. Heading H1K. In a PNPN switch in which the surface of the P-type gate layer is divided into two parts by the cathode layer the gate contact is disposed on one part while a layer containing diffused recombination centres extends across the junction between the other part and the cathode layer. A typical thyristor of this type is made by lapping and etching a 40 ohm cm. N-type silicon wafer to a thickness of 10 mils, placing it in vacuo at 1250‹ C. for an hour with a source of aluminium vapour and maintaining the heating in air for 4 hours after removing the aluminium source. After cooling the wafer is heated in a flow of phosphorus pentoxide vapour to complete an NPNPN structure. After etching off one of the outer N layers the remaining outer N layer is reduced to the required shape 16 (Fig. 8) by photo-resist etching. The wafer is then heated in boron to increase the surface doping of the ...

Thyristors

... 1,152,464. Semi-conductor devices. JOSEPH LUCAS (INDUSTRIES) Ltd. 30 Aug., 1968 [8 Sept., 1965], No. 38309/65. Heading H1K. The gate region of an SCR comprises a major portion the junction between which portion and the cathode region is short circuited, and a minor portion to which the gate electrode is applied. The device is produced by lapping and etching an N-type silicon wafer, diffusing aluminium into the surfaces and driving-in the aluminium by heating in air to produce P-type layers, and then heating in phosphorus pentoxide vapour to produce N-type layers. The lower N-type layer is removed and the upper N-type layer, which forms the cathode region, is masked using black wax or a photo-resist and etched. As shown, Fig. F, the cathode region comprises a central mesa from which two arms extend to the edge of the wafer dividing the exposed annular peripheral part of the underlying gate region into a major portion 16a and a minor portion 16b. Boron is diffused into these exposed portions ...

SEMICONDUCTOR CONSTRUCTION UNIT

SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE

SCHOTTKY BARRIER DIODE AND METHOD OF MANUFACTURING THE SAME

SEMICONDUCTOR DEVICE

QUANTUM DEVICE COMPRISING FET TRANSISTORS AND CO-INTEGRATED QUBITS ON A SAME SUBSTRATE

BIDIRECTIONAL SWITCH OF POWER COMMANDABLE TO CLOSING AND THE OPENING

L'invention concerne un transistor de puissance symétrique formé horizontalement dans une couche semiconductrice (31) reposant sur une tranche semiconductrice (35) fortement dopée avec interposition d'une couche isolante (33), la tranche étant adaptée à être polarisée à une tension de référence, le produit entre la concentration moyenne de dopants et l'épaisseur de la couche semiconductrice (31) étant compris entre 5.1011 cm-2 et 5. 1012 cm-2.

BIDIRECTIONAL SWITCH OF POWER COMMANDABLE TO CLOSING AND THE OPENING

에어컨 저장시스템 및 그 제어방법

... 본 발명은 한약재의 에어컨 저장시스템에 관한 것으로서, 중앙제어장치와, 각각 한약재를 저장하는 하나 이상의 기밀호위구조를 관리하는 하나 이상의 한약재 에어컨 저장 서브 시스템을 포함하며, 중앙제어장치는 실시간으로 하나 이상의 한약재 에어컨 저장 서브 시스템을 감시하고, 하나 이상의 기밀호위구조 중 산소 함유량과 습도를 제어하도록 배치된다. 또한, 한약재의 에어컨 저장시스템의 제어방법에 있어서, 실시간으로 각각 한약재를 저장하는 하나 이상의 기밀호위구조를 관리하는 하나 이상의 한약재 에어컨 저장 서브 시스템을 감시하는 단계와, 실시간으로 하나 이상의 기밀호위구조 중 산소 함유량과 습도를 제어하는 단계를 포함한다. 본 발명은 중앙제어장치에 의해 멀티 시스템, 멀티 공간의 집중제어를 실현할 수 있을 뿐만 아니라 사용자의 단말기기와 연결하여 실시간으로 데이터를 단말기 사용자에게 전송할 수도 있다. 동시에 다른 종류의 약재 살충이나 유지의 요구에 대응하기 위해 최적의 유지저장 또는 살충조정제어 파라미터의 자동 생성과 중 · 대형 한약재 창고관리 요구사항의 달성, 불필요한 수동작업의 감소, 창고관리자의 전문 수준에 대한 요구의 저하, 관리효율의 향상을 실현하고, 창고관리시스템의 추적관리를 실현하며, 한약재의 전체 프로세스의 관리를 보장하고 기업의 운영비용을 저감 함과 동시에 한약재의 품질보증을 향상할 수 있다.

Vertical dmos-field effect transistor

Diodes, and methods of forming diodes

Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction

A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.

Method and Apparatus for Poling Polymer Thin Films

A poling apparatus for poling a polymer thin film formed on a workpiece carried by a workpiece carrier. The workpiece has grounding electrodes and grounding pads located at edges, and a thin film covering the grounding electrodes but exposing the grounding pads. The workpiece carrier has carrier electrodes located around the workpiece and inside grounding ports at the bottom. The poling apparatus includes, in a poling chamber, a poling source generating a plasma, a Z-elevator to raise the workpiece carrier toward the poling source using the grounding ports, and grounding mechanisms including downwardly biased electrical contacts which, when the workpiece carrier is raised by the Z-elevator, connect the grounding pads of the workpiece with the carrier electrodes, to ground the workpiece. The poling apparatus additionally includes preparation platform and transfer platform with conveyer systems with rollers and Z-elevators to move the workpiece carrier in and out of the poling chamber.

Halbleiteranordnung

Mehrschichtiges Halbleiterbauelement eines Thyristortyps

Thin film transistor

Semiconductor controlled rectifier having a shorted emitter

... 1,088,776. Semi-conductor devices. WESTINGHOUSE ELECTRIC CORPORATION. March 24, 1965 [April 1, 1964], No. 12484/65. Heading H1K. In a PNPN semi-conductor controlled rectifier an emitter-base junction emerges at a major face of the wafer and is shorted by a plurality of spaced fused metal elements 40 to 43 which are substantially enclosed by the emitter electrode 22 and are also in non-rectifying contact with the adjacent base region to which a gate electrode 36 is applied. The various electrodes and shorting elements are of suitably-doped gold foil alloyed to the semi-conductor wafer. Several arrangements of the shorting elements are described, including one (Fig. 5, not shown) in which they are located in openings lying wholly within the emitter electrode.

Semi-conductor devices and the manufacture thereof

... 1,095,047. Semi-conductor controlled rectifiers. WESTINGHOUSE BRAKE & SIGNAL CO. Ltd. Sept. 3, 1965 [Sept. 9, 1964; Dec. 8, 1964; Jan. 18, 1965], Nos. 36848/64, 49881/64 and 2115/65. Heading H1K. A junction in a semi-conductor controlled rectifier is treated to reduce its injection efficiency at low current densities whilst increasing or at least not degrading its injection efficiency at high current densities. To achieve this result all or part of a junction region may be doped with a transition element from the first long series. In one example, a monocrystalline silicon PNP wafer (formed by diffusion of gallium into an N-type wafer) has a gold-antimony pellet alloyed to it to form a further PN junction. A fast diffusing transition metal such as nickel is applied to the recrystallized region either by direct plating from solution or by placing on the region a nickelled disc or ring of a low expansion coefficient material such as molybdenum. The assembly is then heated to a temperature ...

GATE-CONTROLLED THYRISTORS

SEMICONDUCTOR SWITCHING DEVICE

... 1,211,745. Semi-conductor controlled rectifiers. GENERAL ELECTRIC CO. 27 Nov., 1967 [19 Dec., 19661, No. 53971/67. Heading H1K. In a PNPN switching device one of the outermost zones consists of a main region to which the anode or cathode is ohmically connected and an auxiliary region carrying a non-ohmic gate contactor having an area arranged for exposure to a controllable illumination source, the construction being such that the resistance between the gate contact or area and the anode or cathode is higher than that of any current path of the same length in the main region. This accelerates the spread of current of firing thus reducing the turn on delay and rise times and is achieved either by making the auxiliary region thinner or by isolating it from the main region. Where a thinned region is used may be circular and disposed, preferably centrally, within the main region or segmental or annular and disposed at or near the edge of the main region, or there may be plurality of regions ...

HALBLEITERBAUTEIL

Controllable semiconductor electric rectifier element for heavy current

Controllable semiconductor element with a disk, which exhibits four zones of alternating Leitungstyps

SEMICONDUCTOR DEVICE AND PROCEDURE FOR OF THEM HESTELLUNG

Semiconductor device

Schottky barrier diode

A Schottky barrier diode, comprises: a GaN layer; and a Schottky electrode formed on said GaN layer, wherein a region of said GaN layer in contact with said Schottky electrode has a dislocation density of 1*10<8 >cm<-2 >or less, the reverse leak current can be significantly reduced. In addition, Ni or Ni alloy that can achieve an increase in barrier height as a result of heat treatment is used as the Schottky electrode. Accordingly, since the reverse leak current caused by dislocation is small when the Schottky barrier diode is reversely biased, the withstand voltage of the Schottky barrier diode can be enhanced due to an increase in barrier height of the Schottky electrode.

SEMICONDUCTOR SWITCHING DEVICE

Switch with semiconductor supporting of the currents growing quickly

elements with asymmetrical conductibility for devices with junction and process for its manufacture

Semiconductor switch and its manufactoring process

ordered rectifying element with semiconductor for high tension currents

SEMICONDUCTOR DEVICE

수직 반도체 컬럼을 구비한 메모리 소자

... 본 발명은 메모리 소자, 그 동작 방법, 및 그 제조 방법을 제공한다. 이 메모리 소자는 기판 상에서 수직으로 연장되고 차례로 제1 도전형의 소오스 영역, 제2 도전형의 드레인 영역, 상기 소오스 영역과 상기 드레인 영역 사이에 배치된 진성 영역, 및 상기 진성 영역과 상기 드레인 영역 사이에 배치된 제1 도전형의 장벽 영역을 포함하는 반도체 컬럼; 상기 진성 영역을 감싸도록 배치된 게이트 전극; 및 상기 게이트 전극과 상기 진성 영역 사이에 배치된 게이트 절연막을 포함한다.

METHOD OF FABRICATING A GAN MERGED P-I-N SCHOTTKY (MPS) DIODE

A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial structure including a first III-nitride epitaxial layer coupled to the first side of the III-nitride substrate and a plurality of III-nitride regions of a second conductivity type. The plurality of III-nitride regions have at least one III-nitride epitaxial region of the first conductivity type between each of the plurality of III-nitride regions. The semiconductor structure further includes a first metallic structure electrically coupled to one or more of the plurality of III-nitride regions and the at least one III-nitride epitaxial region. A Schottky contact is created between the first metallic structure and the at least one III-nitride epitaxial region.

SEMI-CONDUCTOR ELEMENTS FOR JUNCTION DEVICES AND THE MANUFACTURE THEREOF

Bipolar method and structure having improved BVCEO/RCS trade-off made with depletable collector columns

In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternating doped regions, wherein the plurality of alternating doped regions alternate in a lateral direction from a net first conductivity to a net second conductivity, and a collector contact in electrical contact with the collector. The bipolar transistor can also comprise a heavily doped buried layer below the collector, a base in electrical contact with a base contact, wherein the base is doped to a net second conductivity type and wherein the base spans a portion of the plurality of alternating doped regions, and an emitter disposed within the base, the emitter doped to a net first conductivity, wherein a portion of the alternating doped region under the emitter is doped to a concentration of less than about 3x10¹² cm ...

Semiconductor device

A semiconductor device includes first electrode, first semiconductor layer of first conductivity type on the first electrode, second semiconductor layer of second conductivity type on the first semiconductor layer, third semiconductor layer of the first conductivity type on second semiconductor layer, fourth semiconductor layer of the second conductivity type selectively located on the third semiconductor layer, gate electrode through the third and fourth semiconductor layers and into the second semiconductor layer and insulated therefrom, second electrode on the fourth semiconductor layer, fifth semiconductor layer of the second conductivity type between the first electrode and the second semiconductor layer, sixth semiconductor layer of the first conductivity type on the second semiconductor layer contacting the second electrode, and seventh semiconductor layer of the first conductivity type in the second and sixth semiconductor layers, such that the bottom thereof is closer to the first ...

ORGANIC LIGHT EMITTING DIODE DISPLAY

A diode display includes a substrate having a first island and a second island spaced apart from each other, a first pixel disposed on the first island, and a second pixel disposed on the second island. The first pixel includes a first base layer, a first transistor on the first base layer, a first light emitting element electrically connected to the first transistor, and a first encapsulation layer covering the first light emitting element. The second pixel includes a second base layer, a second transistor on the second base layer, a second light emitting element connected to the second transistor, and a second encapsulation layer covering the second light emitting element.

ТОНКОПЛЕНОЧНЫЙ ТРАНЗИСТОР

Halbleiterbauelemente, eine Halbleiterdiode und ein Verfahren zum Bilden eines Halbleiterbauelements

Ein Halbleiterbauelement (100, 200, 300, 400, 500, 600, 700, 800, 900, 110, 120, 125, 130), umfassend:zumindest eine hoch dotierte Region (101) einer elektrischen Bauelementanordnung, die in einem Halbleitersubstrat (102) gebildet ist; undeine Kontaktstruktur (103), die einen NTC-Abschnitt (104) umfasst, der benachbart zu der zumindest einen hoch dotierten Region (101) an einer Vorderseitenoberfläche (105) des Halbleitersubstrats (102) angeordnet ist, wobei der NTC-Abschnitt (104) ein Material mit einem Widerstand mit einem negativen Temperaturkoeffizienten umfasst,wobei ein spezifischer elektrischer Widerstand des Materials mit einem Widerstand mit einem negativen Temperaturkoeffizienten des NTC-Abschnitts (104) der Kontaktstruktur (103) sich um zumindest 50 % seines spezifischen elektrischen Widerstandswertes bei 150°C in einem Temperaturintervall von 30°C zwischen 170 °C und 250 °C ändert und/oder sich um zumindest 95 % seines spezifischen elektrischen Widerstandswertes bei 150°C in ...

Halbleiter mit vier Zonen

Bipolar device compatible with cmos process technology

The present invention discloses a bipolar device. An emitter is formed in a semiconductor substrate. A collector is laterally spaced from the emitter in the substrate. A gate terminal is formed on the substrate, defining a space between the emitter and the collector. An extrinsic base is formed on the substrate with a predetermined distance from either the emitter or the collector, wherein the base, the emitter, the collector and the gate terminal are located in an active area defined by a hole in a surrounding isolation structure in the substrate.

Trench mosfet having floating dummy cells for avalanche improvement

A trench MOSFET comprising source regions having a doping profile of a Gaussian-distribution along the top surface of epitaxial layer and floating dummy cells formed between edge trench and active area is disclosed. A SBR of n region existing at cell corners renders the parasitic bipolar transistor difficult to turn on, and the floating dummy cells having no parasitic bipolar transistor act as buffer cells to absorb avalanche energy when gate bias is increasing for turning on channel, therefore, the UIS failure issue is avoided and the avalanche capability of the trench MOSFET is enhanced.

Semiconductor device

A semiconductor device includes a body region of a first conductivity type and a gate pattern disposed on the body region. The gate pattern has a linear portion extending in a first direction and having a uniform width and a bending portion extending from one end of the linear portion. The portion of a channel region located beneath the bending portion constitutes a channel whose length is greater than the length of the channel constituted by the portion of the channel region located beneath the linear portion.

Method and structure for forming high-k/metal gate extremely thin semiconductor on insulator device

A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers.

Semiconductor device and method of manufacturing the same

Provided is a semiconductor device that includes a vertical MOS transistor having a trench structure capable of enhancing a driving performance of the vertical MOS transistor. A thick oxide film is formed next to a gate electrode led out of a trench of the vertical MOS transistor having the trench structure, and is removed to form a stepped portion which has a face lower than a surrounding plane and has slopes as well. This makes it possible to form a heavily doped diffusion layer right under the gate electrode through ion implantation for forming a heavily doped source diffusion layer, thereby solving a problem of no current flow in a part of a driver element and enhancing the driving performance of the vertical MOS transistor.

High Voltage Semiconductor Devices

In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.

Integrated electronic device and method for manufacturing thereof

An embodiment of an integrated electronic device formed in a body of semiconductor material, which includes: a substrate of a first semiconductor material, the first semiconductor material having a first bandgap; a first epitaxial region of a second semiconductor material and having a first type of conductivity, which overlies the substrate and defines a first surface, the second semiconductor material having a second bandgap wider than the first bandgap; and a second epitaxial region of the first semiconductor material, which overlies, and is in direct contact with, the first epitaxial region. The first epitaxial region includes a first buffer layer, which overlies the substrate, and a drift layer, which overlies the first buffer layer and defines the first surface, the first buffer layer and the drift layer having different doping levels.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a drift layer, a base layer on the drift layer, and trench gate structures. Each trench gate structure includes a trench reaching the drift layer by penetrating the base layer, a gate insulation layer on a wall surface of the trench, and a gate electrode on the gate insulation layer. A bottom portion of the trench gate structure is located in the drift layer and expands in a predetermined direction so that a distance between the bottom portions of adjacent trench gate structures is less than a distance between opening portions of adjacent trench gate structures in the direction. A thickness of the gate insulation layer is greater in the bottom portion than in the opening portion.

Pseudo buried layer and manufacturing method of the same, deep hole contact and bipolar transistor

The present invention discloses a pseudo buried layer, a deep hole contact and a bipolar transistor, and also discloses a manufacturing method of a pseudo buried layer, including: etching a silicon substrate to form an active region and shallow trenches; sequentially implanting phosphorous ion and arsenic ion into the bottom of the shallow trenches to form phosphorus impurity regions and arsenic impurity regions; conducting thermal annealing to the phosphorus impurity regions and arsenic impurity regions. The implantation of the pseudo buried layer, adopting phosphorous with rapid thermal diffusion and arsenic with slow thermal diffusion, can improve the impurity concentration on the surface of the pseudo buried layers, reduce the sheet resistance of the pseudo buried layer, form a good ohmic contact between the pseudo buried layer and a deep hole and reduce the contact resistance, and improve the frequency characteristic and current output of triode devices.

Field effect transistor and method for manufacturing the same

A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A channel layer may be formed on a portion of the gate electrode, with source and drain regions formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions of the FET may be perpendicular to a surface of the semiconductor substrate.

Power semiconductor device and method of manufacturing the same

A power semiconductor device includes a first semiconductor layer of a first conductivity type, a first drift layer, and a second drift layer. The first drift layer includes a first epitaxial layer of the first conductivity type, a plurality of first first-conductivity-type pillar layers, and a plurality of first second-conductivity-type pillar layers. The second drift layer is formed on the first drift layer and includes a second epitaxial layer of the first conductivity type, a plurality of second second-conductivity-type pillar layers, a plurality of second first-conductivity-type pillar layers, a plurality of third second-conductivity-type pillar layers, and a plurality of third first-conductivity-type pillar layers. The plurality of second second-conductivity-type pillar layers are connected to the first second-conductivity-type pillar layers. The plurality of second first-conductivity-type pillar layers are connected to the first first-conductivity-type pillar layers. The plurality of third second-conductivity-type pillar layers are arranged on the first epitaxial layer.

Control device of semiconductor device

A control device of a semiconductor device is provided. The control device of a semiconductor device is capable of reducing both ON resistance and feedback capacitance in a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided. In the control device controlling driving of a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided, a signal of tuning ON or OFF is outputted to a gate electrode in a state of outputting a signal of turning OFF to the second gate electrode.

Semiconductor device, method of fabricating the same, and patterning mask utilizied by the method

A semiconductor device. The device comprises an active region isolated by an isolation structure on a substrate. The device further comprises a gate electrode extending across the active area and overlying the substrate, a pair of source region and drain region, disposed on either side of the gate electrode on the substrate in the active area, and a gate dielectric layer disposed between the substrate and the gate electrode. The gate dielectric layer comprises a relatively-thicker high voltage (HV) dielectric portion and a relatively-thinner low voltage (LV) dielectric portion, wherein the HV dielectric portion occupies a first intersection among the drain region, the isolation structure, and the gate electrode, and a second intersection among the source region, the isolation structure, and the gate electrode.

Semiconductor device

According to one embodiment, a semiconductor device includes a drift region of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, a gate electrode in a trench shape, a contact region of the second conductivity type, a drain electrode, and a source electrode. The drift region is selectively provided in a drain layer of the first conductivity type from a surface of the drain layer to an inside of the drain layer. The base region is selectively provided in the drift region from a surface of the drift region to an inside of the drift region. The source region is selectively provided in the base region from a surface of the base region to an inside of the base region. The gate electrode penetrates from a part of the source region through the base region adjacent to the part of the source region to reach a part of the drift region in a direction substantially parallel to a major surface of the drain layer. The contact region is selectively provided on the surface of the drift region. The contact region contains an impurity having a concentration higher than an impurity concentration of the base region. The drain electrode is connected to the drain layer. The source electrode is connected to the source region and the contact region. The contact region extends from a side of the drain layer toward the drift region and does not contact the drain layer.

Bipolar junction transistor

A bipolar junction transistor includes a semiconductor island on an insulating substrate; an emitter and at least one of a collector and sub collector within the semiconductor island, the emitter and the at least one of the collector and the sub collector being of a first conductivity type; a base within the semiconductor island separating the emitter and the at least one of the collector and the sub collector, the base being of a second conductivity type; a base contact region within the semiconductor island, the base contact region being of the second conductivity type; and a connecting base region adjacent the base within the semiconductor island and connecting the base to the base contact region while not directly contacting the emitter, the connecting base region being of the second conductivity type with a doping concentration less than a doping concentration of the base contact region.

Semiconductor device

The present teachings provide a semiconductor device comprising: an IGBT element region, a diode element region and a boundary region provided between the IGBT element region and the diode element region are formed in one semiconductor substrate. The boundary region comprises a second conductivity type first diffusion region, a first conductivity type second diffusion region, and a second conductivity type third diffusion region. A first drift region of the IGBT element region contiguously contacts the first diffusion region of the boundary region, and a second drift region of the diode element region contiguously contacts the first diffusion region of the boundary region. A first body region of the IGBT element region contiguously contacts the second diffusion region of the boundary region, and a second body region of the diode element region contiguously contacts the second diffusion region of the boundary region.

Fet structures with trench implantation to improve back channel leakage and body resistance

An FET structure on a semiconductor substrate which includes forming recesses for a source and a drain of the gate structure on a semiconductor substrate, halo implanting regions through the bottom of the source and drain recesses, the halo implanted regions being underneath the gate stack, implanting junction butting at the bottom of the source and drain recesses, and filling the source and drain recesses with a doped epitaxial material. In exemplary embodiments, the semiconductor substrate is a semiconductor on insulator substrate including a semiconductor layer on a buried oxide layer. In exemplary embodiments, the junction butting and halo implanted regions are in contact with the buried oxide layer. In other exemplary embodiments, there is no junction butting. In exemplary embodiments, halo implants implanted to a lower part of the FET body underneath the gate structure provide higher doping level in lower part of the FET body to reduce body resistance, without interfering with FET threshold voltage.

Strained structure of a p-type field effect transistor

In a p-type field effect transistor, a pair of spacers are formed over the top surface of a substrate. A channel recess cavity includes an indentation in the substrate top surface between the pair of spacers. A gate stack has a bottom portion in the channel recess cavity and a top portion extending outside the channel recess cavity. A source/drain (S/D) recess cavity has a bottom surface and sidewalls below the substrate top surface. The S/D recess cavity has a portion extending below the gate stack. A strained material is filled the S/D recess cavity

Hybrid-mode ldmos

An MOS-bipolar hybrid-mode LDMOS device has a main gate input and a control gate input wherein the device operates in an MOS mode when both gate inputs are enabled, and operates in a bipolar mode when the main gate input is enabled and the control gate input is disabled. The device can drive the gate of a power MOSFET to deliver the high current required by the power MOSFET while in the bipolar mode, and provide a fully switching between supply voltage and ground to the gate of the power MOSFET while in the MOS mode.

Reacted Conductive Gate Electrodes and Methods of Making the Same

A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.

Semiconductor device

A semiconductor device is disclosed wherein a peripheral region with a high breakdown voltage and high robustness against induced surface charge is manufactured using a process with high mass productivity. The device has n-type drift region and p-type partition region of layer-shape deposited in a vertical direction to one main surface of n-type semiconductor substrate with high impurity concentration form as drift layer, alternately adjacent parallel pn layers in a direction along one main surface. Active region through which current flows and peripheral region enclosing the active region include parallel pn layers. P-type partition region has impurity concentration distribution where concentration decreases from surface toward substrate side, n-type surface region disposed on parallel pn layers in peripheral region, p-type guard rings disposed separately from each other on n-type surface region, and field plate disposed on inner and outer circumferential sides of p-type guard rings, and electrically connected.

Method of fabricating semiconductor device

A method of fabricating a semiconductor device includes sequentially forming a first gate insulating layer and a second gate insulating layer on a substrate, implanting impurity ions into the substrate and performing a first thermal process for activating the impurity ions to form a source and drain region, and forming a third gate insulating layer on the substrate after the first thermal process has been completed.

Trench-Gate Field Effect Transistors and Methods of Forming the Same

A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region.

Semiconductor device

A field-effect transistor ( 142 ) includes a lowly p-doped region 110 formed on a surface of a substrate ( 102 ), an n-doped drain region 112 and n-doped source region 114 arranged on a surface of the lowly p-doped region 110 , and a device isolation insulating film 132 and device isolation insulating film 134 . Here, the device isolation insulating film 132 is formed greater in film thickness than the device isolation insulating film 134 ; and in the n-doped source region 114 , the peak concentration section having a highest dopant concentration is formed in a deeper position than in the n-doped drain region 112.

Metal-insulator-semiconductor tunneling contacts

A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator.

Source tip optimization for high voltage transistor devices

The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.

Semiconductor component with high breakthrough tension and low forward resistance

A semiconductor component having a semiconductor body is disclosed. In one embodiment, the semiconductor component includes a drift zone of a first conductivity type, a drift control zone composed of a semiconductor material which is arranged adjacent to the drift zone at least in places, a dielectric which is arranged between the drift zone and the drift control zone at least in places. A quotient of the net dopant charge of the drift control zone, in an area adjacent to the accumulation dielectric and the drift zone, divided by the area of the dielectric arranged between the drift control zone and the drift zone is less than the breakdown charge of the semiconductor material in the drift control zone.

Oxide terminated trench mosfet with three or four masks

An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process.

Power device with low parasitic transistor and method of making the same

The power device with low parasitic transistor comprises a recessed transistor and a heavily doped region at a side of a source region of the recessed transistor. The conductive type of the heavily doped region is different from that of the source region. In addition, a contact plug contacts the heavily doped region and connects the heavily doped region electrically. A source wire covers and contacts the source region and the contact plug to make the source region and the heavily doped region have the same electrical potential.

Semiconductor Device

A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type.

Semiconductor device

In a semiconductor power device such as a power MOSFET having a super-junction structure in each of an active cell region and a chip peripheral region, an outer end of a surface region of a second conductivity type coupled to a main junction of the second conductivity type in a surface of a drift region of a first conductivity type and having a concentration lower than that of the main junction is located in a middle region between an outer end of the main junction and an outer end of the super-junction structure in the chip peripheral region.

Transistor and method for forming the same

The invention discloses a semiconductor device which comprises an NMOS transistor and a PMOS transistor formed on a substrate; and grid electrodes, source cathode doped areas, drain doped areas, and side walls formed on two sides of the grid electrodes are arranged on the NMOS transistor and the PMOS transistor respectively. The device is characterized in that the side walls on the two sides of the grid electrode of the NMOS transistor possess tensile stress, and the side walls on the two sides of the grid electrode of the PMOS transistor possess compressive stress. The stress gives the side walls a greater role in adjusting the stress applied to channels and the source/drain areas, with the carrier mobility further enhanced and the performance of the device improved.

Flat response device structures for bipolar junction transistors

Bipolar transistors with tailored response curves, as well as fabrication methods for bipolar transistors and design structures for BiCMOS integrated circuits. The bipolar transistor includes a first section of a collector region implanted with a first dopant concentration and a second section of the collector region implanted with a second dopant concentration that is higher than the first dopant concentration. A first emitter is formed in vertical alignment with the first section of the collector region. A second emitter is formed in vertical alignment with the second section of the collector region.

Metal-oxide-semiconductor device having trenched diffusion region and method of forming same

An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.

Semiconductor device

A source region and a drain region are disposed in a substrate. A gate insulating film is disposed on the substrate. A gate electrode is disposed on the gate insulating film. The gate electrode may include a first gate portion adjacent to the source region and a second gate portion adjacent to the drain region. The first and second gate portions have different work functions from each other.

Stressed channel fet with source/drain buffers

A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers.

Semiconductor device and manufacturing method thereof

A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate. Then, on the wafer, a trench to become a scribing line is formed with a crystal face exposed so as to form a side wall of the trench. On that side wall, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to dice a collector electrode, formed on the p collector region, together with the p collector region.

Method for Manufacturing a Semiconductor Device

A method for forming a semiconductor device is provided. The method includes providing a semiconductor body with a horizontal surface. An epitaxy hard mask is formed on the horizontal surface. An epitaxial region is formed by selective epitaxy on the horizontal surface relative to the epitaxy hard mask so that the epitaxial region is adjusted to the epitaxy hard mask. A vertical trench is formed in the semiconductor body. An insulated field plate is formed in a lower portion of the vertical trench and an insulated gate electrode is formed above the insulated field plate. Further, a method for forming a field-effect semiconductor device is provided.

Method of forming an integrated power device and structure

In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.

Twin-Drain Spatial Wavefunction Switched Field-Effect Transistors

A field-effect transistor is provided and includes source, gate and drain regions, where the gate region controls charge carrier location in the transport channel, the transport channel includes a asymmetric coupled quantum well layer, the asymmetric quantum well layer includes at least two quantum wells separated by a barrier layer having a greater energy gap than the wells, the transport channel is connected to the source region at one end, and the drain regions at the other, the drain regions include at least two contacts electrically isolated from each other, the contacts are connected to at least one quantum well. The drain may include two regions that are configured to form the asymmetric coupled well transport channel. In an embodiment, two sources and two drains are also envisioned.

Short Channel Lateral MOSFET

A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region.

Semiconductor devices and methods of fabricating the same

A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate.

Semiconductor device

According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductive type, and a periodic array structure having a second semiconductor layer of a first conductive type and a third semiconductor layer of a second conductive type periodically arrayed on the first semiconductor layer in a direction parallel with a major surface of the first semiconductor layer. The second semiconductor layer and the third semiconductor layer are disposed in dots on the first semiconductor layer. A periodic structure in the outermost peripheral portion of the periodic array structure is different from a periodic structure of the periodic array structure in a portion other than the outermost peripheral portion.

Tunable semiconductor device

Embodiments of the invention include a method for forming a tunable semiconductor device and the resulting structure. The invention comprises forming a semiconductor substrate. Next, pattern a first mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector. Remove the first mask. Pattern a second mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector. Remove the second mask and form a collector above the second discontinuous subcollector. Breakdown voltage of the device may be tuned by varying the gaps separating doped regions within the first and second discontinuous subcollectors. Doped regions of the first and second discontinuous subcollectors may be formed in a mesh pattern.

Superjunction Structures for Power Devices and Methods of Manufacture

A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

Integrating schottky diode into power mosfet

A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.

Resurf structure and ldmos device

A reduced surface field (RESURF) structure and a lateral diffused metal oxide semiconductor (LDMOS) device including the same are provided. The RESURF structure includes a substrate of a first conductivity type, a deep well region of a second conductivity type, an isolation structure, at least one trench insulating structure, and at least one doped region of the first conductivity type. The deep well region is disposed in the substrate. The isolation structure is disposed on the substrate. The trench insulating structure is disposed in the deep well region below the isolation structure. The doped region is disposed in the deep well region and surrounds a sidewall and a bottom of the trench insulating structure.

Inverted-trench grounded-source fet structure using conductive substrates, with highly doped substrates

This invention discloses an inverted field-effect-transistor (iT-FET) semiconductor device that includes a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate. The semiconductor power device further comprises a trench-sidewall gate placed on sidewalls at a lower portion of a vertical trench surrounded by a body region encompassing a source region with a low resistivity body-source structure connected to a bottom source electrode and a drain link region disposed on top of said body regions thus constituting a drift region. The drift region is operated with a floating potential said iT-FET device achieving a self-termination.

Source and body contact structure for trench-dmos devices using polysilicon

A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

SOI SiGe-BASE LATERAL BIPOLAR JUNCTION TRANSISTOR

A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.

High voltage and ultra-high voltage semiconductor devices with increased breakdown voltages

A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.

Semiconductor structure and method of forming the same

An embodiment of the disclosure includes a semiconductor structure. The semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. An interface is defined between the first III-V compound layer and the second III-V compound layer. A gate is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on opposite side of the gate. Each of the source feature and the drain feature includes a corresponding metal feature at least partially embedded in the second III-V compound layer. A corresponding intermetallic compound underlies each metal feature. Each intermetallic compound contacts a carrier channel located at the interface.

Semiconductor apparatus and method for manufacturing semiconductor apparatus

A semiconductor apparatus includes a substrate having a device region and a peripheral region located around the device region. A first semiconductor region is formed within the device region, is of a first conductivity type, and is exposed at an upper surface of the substrate. Second-fourth semiconductor regions are formed within the peripheral region. The second semiconductor region is of the first conductivity type, has a lower concentration of the first conductivity type of impurities, is exposed at the upper surface, and is consecutive with the first semiconductor region directly or indirectly. The third semiconductor region is of a second conductivity type, is in contact with the second semiconductor region from an underside, and is an epitaxial layer. The fourth semiconductor region is of the second conductivity type, has a lower concentration of the second conductivity type of impurities, and is in contact with the third semiconductor region from an underside.

Mosfet-schottky rectifier-diode integrated circuits with trench contact structures

A trench MOSFET device with embedded Schottky rectifier, Gate-Drain and Gate-Source clamp diodes on single chip is formed to achieve device shrinkage and performance improvement. The present semiconductor devices achieve low Vf and reverse leakage current for embedded Schottky rectifier, have overvoltage protection for Gate-Source clamp diode and avalanche protection for Gate-Drain clamp diode.

Semiconductor device

A super-junction semiconductor substrate is configured in such a manner that an n-type semiconductor layer of a parallel pn structure is opposed to a boundary region between an active area and a peripheral breakdown-resistant structure area. A high-concentration region is formed at the center between p-type semiconductor layers that are located on both sides of the above n-type semiconductor layer. A region where a source electrode is in contact with a channel layer is formed over the n-type semiconductor layer. A portion where the high-concentration region is in contact with the channel layer functions as a diode. The breakdown voltage of the diode is set lower than that of the device.

Integrated circuit having a stressor and method of forming the same

An embodiment of the disclosure includes a method of forming a semiconductor structure. A substrate has a region adjacent to a shallow trench isolation (STI) structure in the substrate. A patterned mask layer is formed over the substrate. The patterned mask layer covers the STI structure and a portion of the region, and leaves a remaining portion of the region exposed. A distance between an edge of the remaining portion and an edge of the STI structure is substantially longer than 1 nm. The remaining portion of the region is etched thereby forms a recess in the substrate. A stressor is epitaxially grown in the recess. A conductive plug contacting the stressor is formed.

Semiconductor device

In one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating layer, and a gate insulator provided on a side surface of the gate electrode. The device includes a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator. The upper or lower main terminal layer is provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer.

Semiconductor device

A semiconductor device includes a stripe-shaped gate trench formed in one major surface of n-type drift layer, a gate trench including gate polysilicon formed therein, and a gate polysilicon connected to a gate electrode. A p-type base layer is formed selectively in mesa region between adjacent gate trenches and a p-type base layer including an n-type emitter layer and connected to emitter electrode. One or more dummy trenches are formed between p-type base layers adjoining to each other in the extending direction of gate trenches. An electrically conductive dummy polysilicon is formed on an inner side wall of dummy trench with a gate oxide film interposed between the dummy polysilicon and dummy trench. The dummy polysilicon is spaced apart from the gate polysilicon and may be connected to the emitter electrode.

Nitride semiconductor transistor

A nitride semiconductor transistor includes a heterojunction layer including a plurality of nitride semiconductor layers having different polarizations, and a gate electrode disposed on the heterojunction layer. An electron current reduction layer having a p-type conductivity is disposed between the heterojunction layer and the gate electrode to pass hole current therethrough and reduce electron current.

High density lateral dmos and associated method for making

The present disclosure discloses a lateral DMOS with recessed source contact and method for making the same. The lateral DMOS comprises a recessed source contact which has a portion recessed into a source region to reach a body region of the lateral DMOS. The lateral DMOS according to various embodiments of the present invention may have greatly reduced size and may be cost saving for fabrication.

Energy conversion device and methods of manufacturing and operating the same

An energy conversion device, and methods of manufacturing and operating the same. The energy conversion device includes: a monolithic single-crystal silicon layer that includes a plurality of doping regions; a vibrator that is disposed in the single-crystal silicon layer and is connected to a doping region of the plurality of doping regions; a first diode that is a PN junction diode and allows an input signal applied to the vibrator to pass therethrough; and a second diode that is a PN junction diode and allows a signal output from the vibrator to pass therethrough.

Trenched power semiconductor device and fabrication method thereof

A trenched power semiconductor device on a lightly doped substrate is provided. The device has a base, a plurality of trenches including at least a gate trench, a plurality of first heavily doping regions, a body region, a source doped region, a contact window, a second heavily doped region, and a metal layer. The trenches are formed in the base. The first heavily doped regions are beneath the trenches respectively and spaced from the bottom of the respective trench with a lightly doped region. The body region encircles the trenches and is away from the first heavily doped region with a predetermined distance. The source doped region is in an upper portion of the body region. The contact window is adjacent to the edge of the base. The second heavily doped region is below the contact window filled by the metal layer for electrically connecting the second heavily doped region.

Semiconductor device with high-voltage breakdown protection

A semiconductor device includes: a semiconductor substrate having a first conductivity type; a well having a second conductivity type and provided inside the semiconductor substrate; a first impurity region having the first conductivity type and provided within the well; a second impurity region having the second conductivity type, provided inside the well and away from the first impurity region; and a third impurity region having a first conductivity type, provided surrounding the well and away from the second impurity region. In this semiconductor device, the well is formed to be deeper than the first impurity region, the second impurity region, and the third impurity region, in a thickness direction of the semiconductor substrate; and a minimum distance between the first impurity region and the second impurity region is smaller than a minimum distance between the second impurity region and the third impurity region.

Power semiconductor device

A power semiconductor device includes a high resistance epitaxial layer having a first pillar region and a second pillar region as a drift layer. The first pillar region includes a plurality of first pillars of the first conductivity type and a plurality of second pillars of the second conductivity type disposed alternately along a first direction. The second pillar region is adjacent to the first pillar region along the first direction. The second pillar region includes a third pillar and a fourth pillar of a conductivity type opposite to a conductivity type of the third pillar. A net quantity of impurities in the third pillar is less than a net quantity of impurities in each of the plurality of first pillars. A net quantity of impurities in the fourth pillar is less than the net quantity of impurities in the third pillar.

Strapped dual-gate vdmos device

Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance. A conductive layer may be formed over the first gate region and the second gate region to lower the effective resistance of the dual-gate.

Semiconductor device and manufacturing method of the same

A semiconductor device includes first, second, and third semiconductor layers each having multiple diffusion layers. The first direction widths of the first diffusion layers are the same. The amount of impurity within the first diffusion layers gradually increases from the bottom end towards the top end of the first semiconductor layer. The first direction widths of the second diffusion layers are the same. The amounts of impurity within the second diffusion layers are the same. The first direction widths of the third diffusion layers are narrower than the first direction widths of the first diffusion layers and the first direction widths of the second diffusion layers at the same level, and gradually become narrower from the bottom end towards the top end of the third semiconductor layer. The amount of impurity within the third. diffusion layers are the same.

Switching device and method for manufacturing the same

A method for manufacturing a switching device, which includes a trench type gate electrode and first to fourth semiconductor regions, is provided. The first semiconductor region is in contact with a gate insulating film and is of n-type. The second semiconductor region is in contact with the gate insulating film, and is of p-type. The third semiconductor region is in contact with the gate insulating film, and is of n-type. The fourth semiconductor region is a p-type semiconductor region which is positioned in a range deeper than the second semiconductor region and consecutive with the second semiconductor region, and which faces the gate insulating film via the third semiconductor region. The manufacturing method includes forming the second semiconductor region in which aluminum is doped, and implanting boron into a range in which the fourth semiconductor region is to be formed in the semiconductor substrate.

Method for manufacturing semiconductor device and semiconductor device

A manufacturing method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer; forming diffusion layers in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer; forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring; forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring; and forming a contact.

Oxide terminated trench mosfet with three or four masks

An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process.

Semiconductor device

In the interior of a semiconductor substrate having a main surface, a first p − epitaxial region is formed, a second p − epitaxial region is formed on the main surface side, and an n-type drift region and a p-type body region are formed on the main surface side. An n + buried region is formed between the first p − epitaxial region and the second p − epitaxial region in order to electrically isolate the regions. A p + buried region having a p-type impurity concentration higher than that of the second p − epitaxial region is formed between the n + buried region and the second p − epitaxial region. The p + buried region is located at least immediately under the junction between the n-type drift region and the p-type body region so as to avoid a site immediately under a drain region which is in contact with the n-type drift region.

Power semiconductor device

Provided is a power semiconductor device including a semiconductor substrate, in which a current flows in a thickness direction of the semiconductor substrate. The semiconductor substrate includes a resistance control structure configured so that a resistance to the current becomes higher in a central portion of the semiconductor substrate than a peripheral portion of the semiconductor substrate.

Mechanisms for forming stressor regions in a semiconductor device

The embodiments of processes and structures described above provide mechanisms for improving mobility of carriers. The dislocations in the source and drain regions and the strain created by the doped epitaxial materials next to the channel region of a transistor both contribute to the strain in the channel region. As a result, the device performance is improved.

Deep trench embedded gate transistor

A semiconductor device includes a source extending into a surface of a substrate, a drain extending into the surface of the substrate, and an embedded gate in the substrate extending from the source to the drain.

METHOD AND STRUCTURE FOR FORMING HIGH-K/METAL GATE EXTREMELY THIN SEMICONDUCTOR ON INSULATOR DEVICE

A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers. 1. A semiconductor device comprising:a gate structure present on a substrate, the gate structure comprising a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region;a spacer adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region; anda raised source region and a raised drain region present adjacent to the spacer, wherein the raised source region and the raised drain region are separated from the gate conductor by the extension portion of the spacer.2. The semiconductor device of claim 1 , wherein the substrate is composed of a semiconductor material that is selected from the group consisting of Si claim 1 , strained Si claim 1 , SiC claim 1 , SiGe claim 1 , SiGeC claim 1 , Si alloys claim 1 , Ge claim 1 , Ge alloys claim 1 , GaAs claim 1 , InAs claim 1 , InP claim 1 , and combinations thereof.3. The semiconductor device of claim 1 , wherein the substrate is comprised of a semiconductor layer having a thickness of less than 10 nm that is present on a dielectric layer.4. The semiconductor ...

Transistor with enhanced channel charge inducing material layer and threshold voltage control

High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.

Complementary junction field effect transistor device and its gate-last fabrication method

The disclosure relates to a complementary junction field effect transistor (c-JFET) and its gate-last fabrication method. The method of fabricating a semiconductor device includes: forming a dummy gate on a first conductivity type wafer, forming sidewall spacers on opposite sides of the dummy gate, forming a source and a drain regions on the opposite sides of the dummy gate, removing the dummy gate, forming a first semiconductor region of a second conductivity type in an opening exposed through the removing the dummy gate, and forming a gate electrode in the opening.

Field effect transistor with a vertical channel and fabrication method thereof

Disclosed herein is a field effect transistor with a vertical channel and a fabrication method thereof. A channel region of the field effect transistor is a circular ring-shaped Si platform, which is formed over a substrate and perpendicular to the substrate; a source, which is made of polysilicon, is located at an upper end of the Si platform; a drain is disposed at an outside of a lower end of the circular ring-shaped Si platform; a gate is placed on an outer side surface of the circular ring-shaped Si platform; and an inside of the circular ring-shaped Si platform is filled with a dielectric material. In comparison with the conventional vertical structure MOSFET with a Si platform, the circular ring-shaped structure field effect transistor according to the invention can effectively suppress the short channel effect and improve the device performance.

Semiconductor device and fabricating method thereof

A semiconductor device is provided. The semiconductor device includes a plurality of first epitaxial layers, a second epitaxial layer and a gate structure. The plurality of first epitaxial layers is stacked on a substrate and has a first conductivity type. Each first epitaxial layer includes at least one first doping region and at least one second doping region adjacent thereto. The first doping region has a second conductivity and the second doping region has the first conductivity type. The second epitaxial layer is disposed on the plurality of first epitaxial layers, having the first conductivity type. The second epitaxial layer has a trench therein and a third doping region having the second conductivity type is adjacent to a sidewall of the trench. The gate structure is disposed on the second epitaxial layer above the second doping region. A method of fabricating a semiconductor device is also disclosed.

Self-aligned contacts

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

Semiconductor device

A semiconductor device is disclosed that has enhanced its electric charge resistance. A first parallel p-n layer is disposed in an element activating part, and a second parallel p-n layer is disposed in an element peripheral edge part. An n − surface area is disposed between the second parallel p-n layer and a first principal face. Two or more p-type guard ring areas are disposed so as to be separate from each other on the first principal face side of the n − surface area. First field plate electrodes and second field plate electrodes are electrically connected to p-type guard ring areas. Second field plate electrodes cover the first field plate electrodes adjacent to each other so as to cover the first principal face between the first field plate electrodes through a second insulating film.

Lateral double diffused mos transistors and methods of fabricating the same

A lateral double diffused MOS transistor including substrate of a first conductivity type, drift region of a second conductivity type and body region of the first conductivity type disposed in the substrate, source region of the second conductivity type disposed in the body region, drain region of the second conductivity type disposed in the drift region, isolation layer disposed in the drift region to surround sidewalls of the drain region, gate insulation layer and gate electrode sequentially stacked generally on the body region, first field plate extending from the gate electrode to overlap the drift region and to overlap a portion of the isolation layer, second field plate disposed above the isolation layer spaced apart from the first field plate, and coupling gate disposed above the isolation layer generally between the drain region and the second field plate, wherein the coupling gate is electrically connected to the second field plate.

Semiconductor device with high voltage transistor

A method for manufacturing a semiconductor includes: forming an isolation region defining first, second and third active regions; implanting first impurity ions of a first conductivity type to form first, second and third wells; implanting second impurity ions of the first conductivity type to form first and second channel regions; implanting second impurity ions of a second conductivity to form a first drain region, such that a portion of the first channel region is overlapped with the first drain region; forming first, second and third gate electrodes, the first gate electrode superposing a portion of the first drain region and covering one lateral end of the first channel region; forming first insulating side wall spacers and a second insulating side wall spacer on a side wall of the first gate electrode; and implanting fourth impurity ions of the second conductivity type to form second drain/source regions.

Symmetric ldmos transistor and method of production

The symmetric LDMOS transistor comprises a semiconductor substrate ( 1 ), a well ( 2 ) of a first type of conductivity in the substrate, and wells ( 3 ) of an opposite second type of conductivity. The wells ( 3 ) of the second type of conductivity are arranged at a distance from one another. Source/drain regions ( 4 ) are arranged in the wells of the second type of conductivity. A gate dielectric ( 7 ) is arranged on the substrate, and a gate electrode ( 8 ) on the gate dielectric. A doped region ( 10 ) of the second type of conductivity is arranged between the wells of the second type of conductivity at a distance from the wells. The gate electrode has a gap ( 9 ) above the doped region ( 10 ), and the gate electrode overlaps regions that are located between the wells ( 3 ) of the second type of conductivity and the doped region ( 10 ).

Semiconductor device and method of fabricating the same

A semiconductor device includes a semiconductor substrate, a buried layer, a deep well having a first conductivity type being disposed on the buried layer, a first doped region having the first conductivity type and a well having the second conductivity type being disposed in the deep well, a first heavily doped region having the first conductivity type being disposed in the first doped region, a second heavily doped region having the first conductivity type being disposed in the well, a gate disposed between the first heavily doped region and the second heavily doped region, and a first trench structure and a second trench structure being disposed at the two sides of the gate in the semiconductor substrate. The first trench structure contacts the buried layer, and a depth of the second trench structure is substantially larger than a depth of the buried layer.

Stepped-source ldmos architecture

A semiconductor device can include a source region near a working top surface of a semiconductor region. The device can also include a gate located above the working top surface and located laterally between the source and a drain region. The source region and the gate can at least partially laterally overlap a body region near the working top surface. The source region can include a first portion having the first conductivity type, a second portion having a second conductivity type, and a third portion having the second conductivity type. The second portion can be located laterally between the first and third portions and can penetrate into the semiconductor region to a greater depth than the third portion but no more than the first portion. The lateral location of the third portion can be determined at least in part using the lateral location of the gate.

High-beta bipolar junction transistor and method of manufacture

An NPN bipolar junction transistor is disclosed that exhibits a collector-to-emitter breakdown voltage greater than 10 volts and a beta greater than 300. The large value of beta is obtained by fabricating the transistor with an extra IN-type layer that reduces recombination of electrons and holes.

High voltage ldmos device

A high voltage lateral double diffused metal-oxide-semiconductor field effect transistor (LDMOS) comprises a substrate; an epitaxy layer on the substrate; a drift region on the epitaxy layer; and a drain region and a source region at two ends. At least one pair of n-type and p-type semiconductor regions is arranged alternately above the interface of the substrate and the epitaxy layer and firmly attached to a lower surface of the drifting region; the n-type and p-type semiconductor regions are firmly closed to each other and arranged to form a lateral PN junction; and the p-type semiconductor region and the drifting region form a vertical PN junction. The n-type and p-type semiconductor regions are also totally called “a reduced surface field (RESURF) layer in body”, and the LDMOS device with a RESURF layer in body effectively solves conflict between raising reverse withstand voltage and reducing forward on-resistance of the current LDMOS devices.

Electric power semiconductor device and manufacturing method of the same

A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.

Semiconductor structure and manufacturing process thereof

A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness.

Power field effect transistor

A field-effect transistors (FET) cell structure has a substrate, an epitaxial layer of a first conductivity type on the substrate, first and second base regions of the second conductivity type arranged within the epitaxial layer or well and spaced apart, and first and second source regions of a first conductivity type arranged within the first and second base region, respectively. Furthermore, a gate structure insulated from the epitaxial layer by an insulation layer is provided and arranged above the region between the first and second base regions and covering at least partly the first and second base region, and a drain contact reaches from a top of the device through the epitaxial layer to couple a top contact or metal layer with the substrate.

Checkerboarded High-Voltage Vertical Transistor Layout

In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Semiconductor device and semiconductor module

In one embodiment, a semiconductor device includes a semiconductor substrate having first and second main surfaces, and including a first semiconductor layer of a first conductivity type in the substrate, a second semiconductor layer of a second conductivity type on a surface of the first semiconductor layer on a first main surface side, a third semiconductor layer of the first conductivity type on a surface of the second semiconductor layer, and a fourth semiconductor layer of the second conductivity type on a surface of the first semiconductor layer on a second main surface side. The device further includes a control electrode and a first main electrode on the first main surface side of the substrate, and a second main electrode and a junction termination portion on the second main surface side of the substrate, the junction termination portion having an annular planar shape surrounding the fourth semiconductor layer.

Methods of forming replacement gate structures with a recessed channel

Disclosed herein are various methods of forming replacement gate structures with a recessed channel region. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define an initial gate opening having sidewalls and to expose a surface of the substrate and performing an etching process on the exposed surface of the substrate to define a recessed channel in the substrate. The method includes the additional steps of forming a sidewall spacer within the initial gate opening on the sidewalls of the initial gate opening to thereby define a final gate opening and forming a replacement gate structure in the final gate opening.

Gate Overvoltage Protection for Compound Semiconductor Transistors

A transistor device includes a compound semiconductor body, a drain disposed in the compound semiconductor body and a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region. A gate is provided for controlling the channel region. The transistor device further includes a gate overvoltage protection device connected between the source and the gate, the gate overvoltage protection device including p-type and n-type silicon-containing semiconductor material.

Method for fabricating super-junction power device with reduced miller capacitance

A method for fabricating a super-junction semiconductor power device with reduced Miller capacitance includes the following steps. An N-type substrate is provided and a P-type epitaxial layer is formed on the N-type substrate. At least a trench is formed in the P-type epitaxial layer followed by forming a buffer layer on interior surface in the trench. An N-type dopant layer is filled into the trench and then the N-type dopant layer is etched to form a recessed structure at an upper portion of the trench. A gate oxide layer is formed, and simultaneously, dopants in the N-type dopant layer diffuse into the P-type epitaxial layer, forming an N-type diffusion layer. Finally, a gate conductor is filled into the recessed structure and an N-type source doped region is formed around the gate conductor in the P-type epitaxial layer.

Semiconductor device

Trenches are formed in a base layer and extend parallel to each other. A gate insulating film is formed on the inner wall of each of multiple trenches. A gate electrode GE is buried in each of the trenches. The source layer is formed in the base layer to a depth less than the base layer. The source layer is disposed between each of the trenches. A second conduction type high concentration layer is formed between the source layer and the trench in a plan view. The trench, the source layer, and the second conduction type high concentration are arranged in this order repetitively in a plan view. One lateral side of the trench faces the source layer and the other lateral side of the trench faces the second conduction type high concentration layer.

Memory Device Having Electrically Floating Body Transistor

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

Semiconductor Device with Integrated Breakdown Protection

A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path.

Semiconductor device with reduced contact resistance and method of manufacturing thereof

A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.