Halbleitervorrichtung

Improvements in or relating to processes for the manufacture of alloy type semi-conductor rectifiers and transistors

... 815,335. Semi-conductor devices. MARCONI'S WIRELESS TELEGRAPH CO. Ltd. Jan. 24, 1957 [April 27, 1956], No. 12990/56. Drawings to Specification. Class 37. An alloy junction device is formed by superposing sheets of support metal and activator metal of the same size and shape, heating in vacuo to cause the activator metal to wet the sheet of support metal and then allowing it to solidify in the form of a layer with a convex surface, placing the composite sheet convex face downwards on a wafer of semi-conductor material and heating the assembly to alloy the activator metal with the semi-conductor. In one embodiment a clean sheet of indium is fused to a nickel supporting sheet by heating to 500‹ C. in hydrogen. After cooling the indiumcoated sheet is placed convex face downwards on a wafer of germanium mounted on a pretinned base tab. A further thin sheet of indium is then laid on top of the indium-coated sheet and the assembly heated in two stages as in Specification 797,687. In the first ...

Improvements in or relating to semi-conductor arrangements and methods of producing such arrangements

... 896,730. Transistors. SIEDMENS & HALSKE A.G. Jan. 21, 1960 [Jan. 27, 1959], No. 2299/60. Class 37. A unipolar transistor comprises a body of one conductivity type with a surface layer of opposite conductivity type and of higher resistivity, formed by impurity diffusion, spaced portions of which are provided with ohmic contacts. In the embodiments a further layer of the same conductivity type as the body is provided on the first layer between the ohmic contacts. In one embodiment the first layer, which is a P-type layer 9 (Fig. 5), on a circular N-type disc 4 is provided with a central ohmic electrode 1, annular ohmic electrode 2, and an annular N-type layer beneath electrode 3. In another arrangement a P-type layer 9 surrounding an N-type cylinder (Fig. 4a) is provided with an annular N-type layer associated with electrode 3, and annular ohmic electrodes 2. Alternatively (Fig. 4b) the N- type layer extends the full length of the cylinder, in which case washer shaped ohmic contacts are provided ...

Components, methods and assemblies for multi-chip packages

Steuerbarer Gleichrichter

Unipolartransistor und Verfahren zur Herstellung desselben

Verfahren zur Herstellung von pn-Übergängen in einem Grundkörper aus einkristallinem Halbleitermaterial

Procédé de réalisation d'un composant semiconducteur à shunt d'émetteur et composant obtenu par la mise en oeuvre de ce procédé

Leistungstransistor

Schaltungsanordnung, die mindestens einen Thyristor mit einem Halbleiterkörper mit Basis- und Emitterschichten enthält

SEMICONDUCTOR CHARGE TRANSFER DEVICE.

Improvements with the transistors

Device with thin film

ELECTRODE HAS DOUBLE SLIT FOR DEVICE HAS TRANSFER OF CHARGE

PROCESS FOR MAKING SEMICONDUCTOR COMPONENTS

실리콘 재료 및 이차 전지의 부극

... 부극 활물질로서 유용한 실리콘 재료를 제공한다. Si/O 원자비가 1/0.5 를 초과하고 또한 1/0.1 이하의 범위에 있고, 밴드 갭이 1.1 eV 를 초과하고 또한 2.1 eV 이하의 범위에 있는 실리콘 재료. 이 실리콘 재료를 부극 활물질로서 사용한 이차 전지는, 수명이 길다.

DETECTION CIRCUIT FOR CHARGE TRANSFER DEVICES OF THE SEMICONDUCTOR

Method of forming semiconductor device using titanium-containing layer

A method of forming a Semiconductor device includes etching an inter-layer dielectric (ILD)to form a contact opening exposing a portion of a Source/drain (S/D). The method further includes depositing a titanium-containing material into the contact opening, wherein an energy of depositing the titanium-containing material is Sufficient to cause re-deposition of a material of the S/D along Sidewalls of the ILD to form protrusions extending from a top Surface of the S/D. The method further includes annealing the Semiconductor device to form a Silicide layer in the S/D and in the protrusions.

TOUCH PANEL, METHOD FOR FABRICATING THE SAME, AND TOUCH DEVICE

Disclosed are a touch panel, a method for fabricating the same, and a touch device. The touch panel includes a display area and a non-display area; the display area includes first touch-electrodes extending in a first direction, and second touch-electrodes extending in a second direction, insulated from each other and arranged intersecting with each other on a substrate, first signal-lines connected with the first touch-electrodes, and second signal-lines connected with second touch-electrodes; the non-display area includes a driver circuit arranged at one end of extension direction of second touch-electrodes, and connected with first signal-lines and second signal-lines; each first touch-electrode includes first grid-shaped electrode bumps connected in sequence in the first direction; and there are overlapping areas between orthographic-projections of first signal-lines, and orthographic-projections of first touch-electrodes onto the substrate, and orthographic-projections of first signal-lines ...

METHODS AND APPARATUS FOR METAL SILICIDE DEPOSITION

Methods and apparatuses for processing substrates, such as during metal silicide applications, are provided. In one or more embodiments, a method of processing a substrate includes depositing an epitaxial layer on the substrate, depositing a metal silicide seed layer on the epitaxial layer, and exposing the metal silicide seed layer to a nitridation process to produce a metal silicide nitride layer from at least a portion of the metal silicide seed layer. The method also includes depositing a metal silicide bulk layer on the metal silicide nitride layer and forming or depositing a nitride capping layer on the metal silicide bulk layer, where the nitride capping layer contains a metal nitride, a silicon nitride, a metal silicide nitride, or a combination thereof.

Method of manufacturing semiconductor device

Disclosed are a semiconductor device and a method of manufacturing the same. In the semiconductor device according to an exemplary embodiment of the present disclosure, at the time of forming a source electrode, a drain electrode, a field plate electrode, and a gate electrode on a substrate having a heterojunction structure such as AlGaN/GaN, the field plate electrode made of the same metal as the gate electrode is formed on the side surface of a second support part positioned below a head part of the gate electrode so as to prevent the gate electrode from collapsing and improve high-frequency and high-voltage characteristic of the semiconductor device.

Multilayer build-up wiring board

Mesh holes 35a and 59a of upper solid layers 35 and upper solid layers 59 are formed to overlie on one another, so that the insulating properties of interlayer resin insulating layers 50 are not lowered. Here, the diameter of each mesh hole is preferably 75 to 300 mum. The reason is as follows. If the diameter of the mesh hole is less than 75 mum, it is difficult to overlay the upper and lower mesh holes on one another. If the diameter exceeds 300 mum, the insulating properties of the interlayer resin insulating layers deteriorate. In addition, the distance between the mesh holes is preferably 100 to 2000 mum. The reason is as follows. If the distance is less than 100 mum, the solid layer cannot function. If the distance exceeds 2000 mum, the deterioration of the insulating properties of the interlayer resin insulating film occurs.

Methods and apparatus for metal silicide deposition

Methods and apparatuses for processing substrates, such as during metal silicide applications, are provided. In one or more embodiments, a method of processing a substrate includes depositing an epitaxial layer on the substrate, depositing a metal silicide seed layer on the epitaxial layer, and exposing the metal silicide seed layer to a nitridation process to produce a metal silicide nitride layer from at least a portion of the metal silicide seed layer. The method also includes depositing a metal silicide bulk layer on the metal silicide nitride layer and forming or depositing a nitride capping layer on the metal silicide bulk layer, where the nitride capping layer contains a metal nitride, a silicon nitride, a metal silicide nitride, or a combination thereof.

PMOS and NMOS contacts in common trench

Techniques are disclosed for using compositionally different contact materials for p-type and n-type source/drain regions on a common substrate. The different contact materials may be within a common source/drain contact trench, or in type-dedicated trenches. A given contact trench may span one or more fins and include one or more source/drain regions on which a corresponding contact structure is to be made. In an embodiment, an isolation structure between p-type and n-type fins is selective to the trench etch and therefore remains intact within the trench after the target source/drain regions have been exposed. In such cases, the isolation structure physically separates n-type source/drain regions from p-type source/drain regions. The contact structures on the different type source/drain regions may be shorted proximate the top of the isolation structure. Numerous material systems can be used for the channel and source/drain regions, including germanium, group III-V materials, and 2-D ...

Schottky barrier diode

A Schottky barrier diode 1 includes: a semiconductor substrate made of gallium oxide; a drift layer made of gallium oxide; an anode electrode brought into Schottky contact with an upper surface of the drift layer; and a cathode electrode brought into ohmic contact with a lower surface of the semiconductor substrate. A ring-shaped outer peripheral trench is formed in the upper surface of the drift layer, and the anode electrode is partly filled in the outer peripheral trench. A ring-shaped back surface trench is formed in the lower surface of the semiconductor substrate such that the bottom thereof reaches the drift layer. This limits a current path to the area surrounded by the back surface trench, thereby mitigating electric field concentration in the vicinity of the bottom of the outer peripheral trench.

Verfahren zum Kontaktieren von mindestens zwei benachbarten Zonen entgegengesetzten Leitungstyps eines steuerbaren Halbleiterbauelementes

Improvements in or relating to crystal apparatus for use in connection with electric oscillations

... 264,270. Wilcockson, J., and Roberts, H. W. Oct. 31, 1925. Crystal detectors; non-therniionic amplifiers; oscillation generators.-A crystal combination of alum in contact with saltpetre is stated to rectify and amplify received wireless signals. Under the influence of radio-frequency oscillations, the com. bination also emits a ray capable of oxidizing metals and influencing an adjacent electroscope. As shown in Fig. 1, the alum 3 and saltpetre 5 are mounted in insulating blocks 4, 6, carried by two casings 7, 8 which may telescope together to maintain contact between the crystals; or suitable means may be provided to feed the crystals towards each other automatically. An electric potential of the value normally used across the plate and filament of a thermionic valve is applied to the alum 3 by conductors 9, 10 taken to suitable terminals 9A, 10 on a plug base as shown, whilst a lower potential corresponding to the filament voltage is applied to the saltpetre through conductors 11, ...

Improvements in or relating to semi-conductor devices

... 917,667. Semi-conductor devices. -WESTINGHOUSE BRAKE & SIGNAL CO. Ltd. Nov. 23, 1960 [Dec. 17, 1959], No. 42912/59. Class 37. In a semi-conductor device having a contact 4 extending over a face of a semi-conductor wafer 1 and beyond an edge of the face, an incision 9 is made across the contact adjacent this edge. In the drawings, a PNN+ silicon diode is provided with gold contacts 4, in the form of layers of gold on Ni-Fe alloy tags 5. A plated tag is initially placed in a jig having pins to guide a hacksaw blade or file over the tag to make in - cision 9, which extends into the Ni-Fe alloy material. The tag is then alloyed to the wafer, which may be etched in a hydrofluoric/nitric acid mixture, and encapsulated.

Thyristors

... 1,162,140. PNPN switches. JOSEPH LUCAS (INDUSTRIES) Ltd. 8 Nov., 1966 [6 Dec., 1965], No. 51618/65. Heading H1K. In a PNPN switch in which the surface of the P-type gate layer is divided into two parts by the cathode layer the gate contact is disposed on one part while a layer containing diffused recombination centres extends across the junction between the other part and the cathode layer. A typical thyristor of this type is made by lapping and etching a 40 ohm cm. N-type silicon wafer to a thickness of 10 mils, placing it in vacuo at 1250‹ C. for an hour with a source of aluminium vapour and maintaining the heating in air for 4 hours after removing the aluminium source. After cooling the wafer is heated in a flow of phosphorus pentoxide vapour to complete an NPNPN structure. After etching off one of the outer N layers the remaining outer N layer is reduced to the required shape 16 (Fig. 8) by photo-resist etching. The wafer is then heated in boron to increase the surface doping of the ...

Improvements in and relating to dry surface-contact electric rectifiers

... 500,344. Asymmetrically conducting resistances. BRITISH THOMSON-HOUSTON CO., Ltd. Sept. 21, 1938, No. 27540. Convention date, Sept. 22, 1937. [Class 37] In an electric valve of the dry rectifier type a control grid 3 is embedded in the semiconductor layer 2 and is coated with an insulating layer 4. The grid 3 may be of aluminium and the insulator an oxide film or of silver with a coating of quartz vaporized on it.

SEMICONDUCTOR DEVICE

... 1,272,154. Semi-conductor devices. CKD PRAHA OBOROVY PODNIK. 10 June, 1970 [12 June, 1969], No. 28113/70. Heading H1K. A thyristor including cathode-emitter-shunts 7 uniformly distributed beneath the annular cathode electrode 1 is provided with additional shunts 71 beneath the inner periphery of and partially overlapped by the cathode electrode 1. These shunts 71 are spaced from each other by a distance equal to or less than the mutual spacing of the fully covered shunts 7, and are spaced by 5-100 Ám. from the inner peripheral surfaceemergent portion 8 of the cathode-emitter junction 6, which portion 8 surrounds a central surface-emergent area of the base region 3 where it is contacted by the control electrode 11.

Improvements in or relating to methods of manufacturing semiconductor systems

... 786,281. Semi-conductor devices electrodepositing indium. PHILIPS ELECTRICAL INDUSTRIES, Ltd. Dec. 30, 1954 [Dec. 31, 1953], No. 37658/54. Classes 37 and 41. A method of making semi-conductor devices comprises applying electrode material to one end of a connecting conductor, placing said end on a semi-conductor body and then heating the whole assembly to fuse the electrode material to the conductor and to alloy it with the body. The material may be applied to the conductor by cataphoresis, evaporation or atomization, or by electrolysis, e.g. from a solution of In, KCN, KOH, and dextrose in water in the apparatus shown in Fig. 1 in which the conductors 4 are held in a clamp 5. Where an alloy electrode material, e.g. Pb-Sb alloy on a nickel wire, is required, the components thereof are electrolytically deposited separately and fused to form an alloy either before or during the process of alloying with the semi-conductor. It is desirable to use a connecting conductor non-wettable by the electrode ...

Semiconductor device

Metal stack for integrated circuit having two thin layers of titanium with dedicated chamber depositions

SEMICONDUCTOR ELECTROCHEMICAL SENSORS

Described herein are substrates, sensors and systems related to measuring the concentration of an analyte such as hydrogen ion in a sample. Redox act ive moieties whose reduction and/or oxidation potentials are sensitive to th e presence of an analyte are immobilized onto a semiconductor surface. Immob ilized redox active moieties whose reduction and/or oxidation potential are insensitive to the analyte can be used for reference. Voltammetric measureme nts made using such modified semiconductor surfaces can accurately determine the presence and/or concentrations of analytes in a sample of interest. The semiconductor electrochemical sensors of the invention are robust and can b e made so as not to require calibration or re-calibration.

Semiconductor device and manufacturing method thereof

Improvements with the structures with semiconductor

Process of application of contacts on semiconductor bodies

FILTRE TRANSVERSAL COMPORTANT AU MOINS UN REGISTRE A DECALAGE ANALOGIQUE ET PROCEDE POUR SA MISE EN OEUVRE

L'invention concerne un filtre transversal. Dans un filtre transversal comportant un registre à décalage et des circuits de pondération formés par des couples de condensateurs sur un substrat semi-conducteur 1, au moins un circuit de pondération possède une région dopée 2 munie d'une indentation dans laquelle est inséré un premier condensateur à couche isolante ou à couche d'arrêt (électrode 3), qui comporte une indentation, dans laquelle est inséré un second condensateur à couche isolante ou à couche d'arrêt (électrode 4). Application notamment aux filtres pour signaux analogiques.

Manufactoring process of systems of electrodes

METHOD OF MAKING A SEMICONDUCTOR DEVICE

MANUFACTURING METHOD OF TRANSISTOR

... 박막 트랜지스터의 오프 전류를 저감시키고, 온 전류를 향상시키고, 전기적 특성의 편차를 저감시킨다. 역 스태거, 채널 에치형의 박막 트랜지스터의 제작 방법에 있어서, 소스 전극 및 드레인 전극에서 노출되는 일 도전형을 부여하는 불순물 원소를 포함하는 반도체 층 및 그 아래에 접하여 형성되는 층에 있는 비정질 반도체 층의 일부를 제 1 드라이 에칭에 의하여 제거하고, 제 1 드라이 에칭에 의하여 노출된 비정질 반도체 층의 일부를 제 2 드라이 에칭에 의하여 제거하고, 제 2 드라이 에칭에 의하여 노출된 비정질 반도체 층의 표면에 플라즈마 처리를 행함으로써 변질층(變質層)을 형성한다.

Transistor à diffusion unipolaire.

Semiconductor structure and method of manufacturing the same

The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.

Method of forming semiconductor device using titanium-containing layer and device formed

A method of forming a semiconductor device includes depositing a titanium-containing material over a source/drain (S/D), wherein an energy of depositing the titanium-containing material is sufficient to cause re-deposition of a material of the S/D along sidewalls of a dielectric layer adjacent the S/D to form protrusions extending from a top surface of the S/D. The method further includes annealing the semiconductor device to form a silicide layer in the S/D and in the protrusions.

Semiconductor device having trench with vertically formed field oxide

A semiconductor device includes a substrate, a plurality of active regions on the substrate, the active regions having recessed and elevated types and being alternatively in parallel with the substrate, respectively, and a plurality of first and second field insulating layers at field regions adjacent to the active regions, the first field insulating layer being parallel with the substrate and the second field insulating layer being perpendicular to the substrate.

Semiconductor device

A semiconductor device comprises a substrate (42), having at one surface thereof a region (45) of uniform conductivity type covered by an insulation layer (43), formed with a window (RCW) through which a conductive layer (ME2) makes contact with the said region of the substrate. A source of atoms (DRCW) of the semiconductor material is provided in contact with the conductive layer, between the window and a major portion of the conductive layer, whereby diffusion of atoms from the source into the conductive layer serves to stabilize the concentration of semiconductor atoms in the vicinity of the window and so stabilizes the contact resistance between the said region of the substrate and the conductive layer.

DEVICE AND METHOD FOR PROCESSING SUBSTRATE

A method of fabricating a memory device includes preparing a silicon substrate; depositing a layer of high-k insulator on the silicon substrate; depositing a buffering layer on the high-k insulating layer; depositing a layer of ferroelectric material on the buffering layer by metal organic chemical vapor deposition; forming a top electrode on the layer of ferroelectric material; and completing the device obtained by above steps.

Plug-Herstellungsverfahren für Halbleitervorrichtung

Plug-Herstellungsverfahren für eine Halbleitervorrichtung, umfassend die folgenden Schritte: Erzeugen einer Isolationsschicht (3) in bzw. auf einem Halbleitersubstrat (1), Erzeugen einer Öffnung (4a 4b) auf einem vorbestimmten Oberflächenteil des Halbleitersubstrates (1), Erzeugen einer Polysiliziumschicht (5) auf der Isolationsschicht (3) einschließlich der Öffnung (4a, 4b), und Rückätzen der Polysiliziumschicht (5) mittels eines Mischgases, das aus SF6-Gas als erstes Gas und einem zweiten Gas besteht, das aus der Gruppe von NO, SO2 und N2O ausgewählt ist, um den Plug herzustellen.

Electrical features improvement method for nano-electronic structure, involves arranging nanoelectronic structure between two electrodes, applying metallic salt solution on nanowires and nanotubes

The method involves arranging a nanoelectronic structure between two electrodes, applying a metallic salt solution on a nanowires (2) and nanotubes. An alternating voltage applying on the electrodes, so that electrical fields are formed at defects of the nanowires and nanotube and metal is separated at the defects. The method involves an electrically leading or semiconducting nanowires and nanotubes with a certain diameter. The nanowires and nanotubes is made of carbon. Independent claims are also included for the following: (1) an arrangement for improvement of the electrical features of an nanoelectronic structure, which has nanoelectronic structure with electrically leading or semi conducting nanowires and nanotube (2) an application of a dielectrophoresis cell, which has two electrodes and a metallic salt solution (3) a nanoelectronic structure, which has electrically leading or semi conducting nanowires and nanotubes (4) an application of a nanoelectronic structure as sensor for measuring ...

Halbleitervorrichtung

Eine Emitterelektrode weist eine erste Elektrodenschicht, eine zweite Elektrodenschicht und eine dritte Elektrodenschicht auf. Die erste bis dritte Elektrodenschicht sind in dieser Reihenfolge auf eine Emitterschicht gelegt. Eine Lötmittelschicht ist weiter auf die dritte Elektrodenschicht gelegt. Die erste Elektrodenschicht bedeckt die Emitterschicht und eine Gate-Oxidschicht in einer vorderen Oberfläche eines Halbleiter-Chips. Ein erstes elektrisch leitendes Material, das die erste Elektrodenschicht bildet, weist AlSi als seine Hauptkomponente auf. Ein zweites elektrisch leitendes Material, das die zweite Elektrodenschicht bildet, weist einen linearen Ausdehnungskoeffizienten auf, der sich von dem des ersten elektrisch leitenden Materials unterscheidet, und weist eine geringere mechanische Festigkeit auf als das erste elektrisch leitende Material. Ein drittes elektrisch leitendes Material, das die dritte Elektrodenschicht bildet, weist einen linearen Ausdehnungskoeffizienten auf, der ...

SEMICONDUCTOR DEVICE

CHARGE TRANSFER APPARATUS

Improvements in semiconductor devices

... 1,103,771. Semi-conductor devices. ASSOCIATED SEMICONDUCTOR MANUFACTURERS Ltd. 29 Jan., 1965, No. 4027/65. Heading H1K. In a semi-conductor device which is not completely circularly symmetrical the effect of " current hogging " is reduced by contacting one region with a conductive layer the distance of the edge of which from the junction decreases as the distance from a low resistance contact applied to the layer increases. " Current hogging " is the concentration of the current flow at certain areas of a junction due to the geometry of the device. In a first embodiment a planar transistor having interdigitated base and emitter regions is produced and, as shown in Fig. 4, the emitterbase junction 13 is protected by an oxide layer the edge 12 of which defines the effective edge of a conductive layer 15 forming the emitter contact. Layer 15 is provided with a low resistance contact 18 and the effective edge 12 of the emitter contact 15 is closest to the junction 13 at those regions furthest ...

Thyristor

Semiconductor switch and its manufactoring process

DETECTION CIRCUIT FOR CHARGE TRANSFER DEVICES SEMICONDUCTOR

CIRCUIT DE DETECTION POUR DES DISPOSITIFS DE TRANSFERT DE CHARGES A SEMICONDUCTEUR

L'invention concerne un appareil semi-conducteur et, plus particulièrement, des circuits electriques pour détecter le signal de sortie d'un dispositif semi-conducteur à transfert de charges. Le circuit de détection du signal de sortie du dispositif à transfert de charges comprend deux amplificateurs 40 et 60 qui sont prévus pour détecter l'un le signal différentiel utile apparaissant sur les électrodes partagées et, l'autre, pour supprimer le signal inutile de mode commun. En outre, le circuit de détection comprend des moyens de remise à zéro pour éliminer les signaux parasites dus aux charges réparties et des circuits de maintien pour éliminer le bruit thermique. L'invention est applicable aux dispositifs de transfert de charges à semi-conducteur du type à charges couplées ou à godets.

DIELECTRIC ISOLATION IN GATE-ALL-AROUND DEVICES

A semiconductor device is fabricated with a first layer of a first sacrificial material deposited over a surface of a substrate. A first set of layers of a second sacrificial material and a second set of layers of a channel material are deposited over the first layer. A liner is deposited in a first recess, which exposes a first connection end of a layer in the second set, where the first recess reaches into the substrate for at least a fraction of a total depth of the substrate. An insulator material is filled in the first recess and etched up to a stop depth, stopping the etching at a height above the surface of the substrate. The liner is removed from at least the first connection end of the layer in the second set. An electrical connection is formed with a source/drain structure using the first connection end.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Disclosed are a semiconductor device and a method of manufacturing the same. In the semiconductor device according to an exemplary embodiment of the present disclosure, at the time of forming a source electrode, a drain electrode, a field plate electrode, and a gate electrode on a substrate having a heterojunction structure such as AlGaN/GaN, the field plate electrode made of the same metal as the gate electrode is formed on the side surface of a second support part positioned below a head part of the gate electrode so as to prevent the gate electrode from collapsing and improve high-frequency and high-voltage characteristic of the semiconductor device.

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

PURPOSE: To contrive to prevent the titled device from generation of a parasitic MOS without reducing the degree of integration of IC's by a method wherein an electrode is provided on the whole surface holding at high electric potential on a group of wirings interposing a second insulating film between them, and a high concentration diffusion layer the same conductive type with a substrate is provided as the channel stopper between diffusion layers containing the part directly under the wirings to cross the diffusion layers thereof. CONSTITUTION: When the Al wirings 21 exist on the p type diffusion layers of two pieces crossing them, the high electric potential Al electrode 16 is formed on the whole surface interposing the insulating film 15 between them, and the n+ type diffusion layer 22 is provided partially as the channel stopper between the two diffusion layers at the part containing the directly under part of the Al wiring 21. Accordingly, unstably movable ions on the surface of the ...

Verfahren zur Herstellung eines Halbleiterbauelements mit einem kapazitiven Element

Halbleitendes Elektrodensystem

Passivierungsstruktur mit Spannungsausgleichschleifen

Halbleiter-Bauelement, das Folgendes umfasst:einen Halbleiterkörper eines ersten Leitfähigkeitstyps,ein in dem Halbleiterkörper ausgebildetes aktives Gebiet, das ein Gebiet eines zweiten Leitfähigkeitstyps enthält, das in der Nähe der äußeren Grenze des aktiven Gebietes endet, undeine Passivierungsstruktur, die um das aktive Gebiet herum angeordnet ist undein durchgängiges Band aus Widerstandsmaterial mit im Wesentlichen gleichmäßiger Breite, wobei sich das durchgängige Band nach einer Umrundung des aktiven Gebietes mit sich selbst kreuzt und eine erste geschlossene Schleife aus einem Widerstandsmaterial bildet, die als innere Grenze der Passivierungsstruktur dient, ein schleifenbildendes Band aus dem Widerstandsmaterial aufweist, das die erste geschlossene Schleife unter Bildung von Schleifen umgibt, ohne sich zu kreuzen, wobei das durchgängige Band sich ein zweites Mal mit sich selbst kreuzt und um die erste geschlossene Schleife herum eine zweite geschlossene Schleife aus dem Widerstandsmaterial ...

Thin film device

... 1,061,074. Semi-conductor devices. SPERRY RAND CORPORATION. May 19, 1964 [May 31, 1963], No. 20593/64. Heading H1K. A thin-film tunnel - emission triode, comprising a metallic emitter 10, base 12 and collector 16 separated from each other by insulating films 11 and 14, is further provided with a porous or foraminous electricallycontinuous metallic film 15 embedded within the insulating film 14 separating the base 12 and collector 16. At a suitable potential, the film 15 screens the collector from the base and thereby decreases the base-collector capacitance.

Semiconductor electrochemical sensors

IMPROVED ELECTRICAL SWITCHING MEANS

... 1,222,144. S.C.Rs. ALLMANNA SVENSKA ELEKTRISKA A.B. 25 June, 1968 [30 June, 1967], No. 30258/68. Heading HlK. An S.C.R. is provided with an ignition electrode and at least one bias electrode on one of its base layers, the bias electrode being supplied with a voltage such that the junction between the said base layer and the adjacent emitter layer is reverse biased at least during the blocking interval of the device. As shown, Fig. 2, an S.C.R. has a cathode electrode 6 and a central ignition electrode 97 contacting the adjacent base layer 4 which is also provided with three bias electrodes 91, 92, 93 which are connected together and biased negatively with respect to the cathode by source 12. The device is fired by applying a positive voltage to the ignition electrode 97. In a second embodiment, Fig. 3 (not shown), six bias electrodes are provided and each is connected to the central ignition electrode by means of a diode. The bias and ignition voltages are applied directly between the ignition ...

Semiconductor electrochemical sensors

OHMIC CONTACT FOR GAAS AND GAA1AS

Method of forming semiconductor device using titanium-containing layer

METHOD OF MANUFACTURING A FIELD EFFECT TRANSISTOR GATE CONFORMAL

L'invention concerne un procédé de fabrication d'un transistor à effet de champ à grille enrobante (41), comprenant : -fournir une superposition de premier à troisième nanofils (11-17), chacun en matériau semi-conducteur, le deuxième nanofil étant soumis à une contrainte selon son axe longitudinal, la partie médiane des premier à troisième nanofils étant recouverte par une grille sacrificielle (31) ; -former des évidements par retrait d'une partie intermédiaire des premier et troisième nanofils (11, 13) entre leurs extrémités et leur partie médiane, en conservant la superposition des premier à troisième nanofils (11, 12, 13) au niveau des extrémités et sous la grille sacrificielle (31) ; -former un isolant électrique dans lesdits évidements autour du deuxième nanofil (12) ; -retirer ladite grille sacrificielle (31) et la partie médiane des premier et troisième nanofils (11, 13); -former une électrode de grille enrobant la partie médiane dudit deuxième nanofil (12).

Devices of transmission

Switch with semiconductor

Manufactoring process of rectifiers and transistors with semiconductors of the type with allied junction

Device with field effect

TRANSVERSE FILTER COMPRISING AT LEAST A SHIFT REGISTER ANALOGICAL AND PROCESS FOR SA IMPLEMENTED

LADDNINGSOVERFORANDE ANORDNING

Semiconductor device and method for manufacturing a semiconductor device

A semiconductor device includes a semiconductor substrate including a main surface with a polygonal geometry and a main electric circuit manufactured within a main region on the semiconductor substrate. The main electric circuit is operable to perform an electric main function. The main region extends over the main surface of the semiconductor substrate leaving open at least one corner area at a corner of the polygonal geometry of the main surface of the semiconductor substrate. The corner area extends at least 300 m along the edges of the semiconductor substrate beginning at the corner.

METAL GATE STRUCTURES FOR CMOS TRANSISTOR DEVICES HAVING REDUCED PARASITIC CAPACITANCE

A method of forming a field effect transistor (FET) device includes forming a gate structure over a substrate, the gate structure including a wide bottom portion and a narrow portion formed on top of the bottom portion; the wide bottom portion comprising a metal material and having a first width that corresponds substantially to a transistor channel length, and the narrow portion also including a metal material having a second width smaller than the first width.

EMBEDDED TOUCH PANEL AND MANUFACTURING METHOD

An embedded touch panel and a manufacturing method are provided. Touch drive lines of a touch panel adopt a segmented structure design so that spacings between the touch drive lines and the touch sense lines are changed, and changes of the spacings cause changes of capacitance values between the touch drive lines and the touch sense lines. Through detecting an amount of change of the capacitance value, a magnitude of a user's pressing force is determined to make a further judgment as to whether it is a light press or a heavy press so as to retrieve a corresponding instruction. Only four masks are needed to fabricate the structure of the touch circuit lines. The manufacturing process is relatively simple to reduce the manufacturing cost.

КРЕМНИЕВЫЙ МАТЕРИАЛ И ОТРИЦАТЕЛЬНЫЙ ЭЛЕКТРОД АККУМУЛЯТОРНОЙ БАТАРЕИ

Изобретение относится к кремниевому материалу, используемому в качестве активного материала отрицательного электрода аккумуляторных батарей. Предложен новый кремниевый материал, который имеет атомное отношение Si/O в диапазоне более 1/0,5 и не более 1/0,1 и ширину запрещенной зоны в диапазоне более 1,1 эВ и не более 2,1 эВ. Аккумуляторная батарея, в которой этот кремниевый материал используется в качестве активного материала отрицательного электрода, обладает повышенной начальной эффективностью и длительным ресурсом работы. 4 н. и 7 з.п. ф-лы, 3 ил., 1 табл., 9 пр.

TRANSVERSALFILTER

Semiconductor electrochemical sensors

Described herein are substrates, sensors and systems related to measuring the concentration of an analyte such as hydrogen ion in a sample for determining the samples pH. Redox active moieties whose reduction and/or oxidation potentials are sensitive to the presence of an analyte (such as H<+> ion) are immobilized onto a semiconductor surface. Immobilized redox active moieties whose reduction and/or oxidation potential are insensitive to the analyte can also be used for reference or can be used to detect a second analyte (such as ammonia, oxygen or carbon dioxide). Voltammetric measurements made using such modified semiconductor surfaces can accurately determine the presence and/or concentrations of analytes in a sample of interest. The semiconductor electrochemical sensors of the invention are accurate and robust and can be made so as not to require calibration or re-calibration. Figure 5 shows one embodiment wherein a silicon semiconducting electrode is modified with ferrocene moieties ...

SENSING CIRCUIT FOR SEMICONDUCTOR CHARGE TRANSFER DEVICES

SENSING CIRCUIT FOR SEMICONDUCTOR CHARGE TRANSFER DEVICES A sensing circuit is disclosed for detecting and amplifying the output signal of a semiconductor charge transfer device, particularly of the transversal filter type containing sensing split-electrodes for sensing the charge packets being transferred through the device. The circuit includes two amplifier means, one of which suppresses the (useless) common mode signal and the other of which detects the (useful) difference signal of the split-electrodes. In addition, the sensing circuit is provided both with "reset" switching means for eliminating spurious signals due to stray charges that accumulate on the sensing electrodes and with "clamping" switching means for eliminating noise of the kTC type generated by the "reset" switching.

semiconductor element being able to be ordered and manufactoring process of this one

SEMICONDUCTOR DEVICE

Semiconductor device having improved mechanical and thermal reliability

Compound semiconductor device and power amplifier module

ELECTRONIC DEVICES WITH YIELDING SUBSTRATES

In accordance with certain embodiments, a semiconductor die is adhered directly to a yielding substrate with a pressure-activated adhesive notwithstanding any nonplanarity of the surface of the semiconductor die or non-coplanarity of the semiconductor die contacts.

Silicon Carbide Semiconductor Device and Method of Manufacturing

A semiconductor device includes a trench structure extending from a first surface into a silicon carbide semiconductor body. The trench structure includes an auxiliary electrode at a bottom of the trench structure and a gate electrode arranged between the auxiliary electrode and the first surface. A shielding region adjoins the auxiliary electrode at the bottom of the trench structure and forms a first pn junction with a drift structure. A corresponding method of manufacturing the semiconductor device is also described.

Semiconductor Device with Surge Current Protection

A power device includes an active area having at least two switchable regions with different threshold voltages.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a substrate; an n-type transistor including a first junction region positioned on the substrate, a first channel region positioned on the first junction region, a second junction region positioned on the first channel region, and a first gate stack at least partially surrounding the first channel region; and a p-type transistor including a third junction region positioned on the substrate, a second channel region positioned on the third junction region, a fourth junction region positioned on the second channel region, and a second gate stack at least partially surrounding the second channel region, in which the first channel region and the second channel region are epitaxial channel layers.

METHODS AND APPARATUS FOR METAL SILICIDE DEPOSITION

Methods and apparatuses for processing substrates, such as during metal silicide applications, are provided. In one or more embodiments, a method of processing a substrate includes depositing an epitaxial layer on the substrate, depositing a metal silicide seed layer on the epitaxial layer, and exposing the metal silicide seed layer to a nitridation process to produce a metal silicide nitride layer from at least a portion of the metal silicide seed layer. The method also includes depositing a metal silicide bulk layer on the metal silicide nitride layer and forming or depositing a nitride capping layer on the metal silicide bulk layer, where the nitride capping layer contains a metal nitride, a silicon nitride, a metal silicide nitride, or a combination thereof.

Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant

A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the first semiconductor die and carrier and around the conductive pillars. A recess is formed in a first surface of the encapsulant over the first semiconductor die. The recess has sloped or stepped sides. A first interconnect structure is formed over the first surface of the encapsulant. The first interconnect structure follows a contour of the recess in the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant and first semiconductor die. The first and second interconnect structures are electrically connected to the conductive pillars. A second semiconductor die is mounted in the recess. A third semiconductor die is mounted over the recess and second semiconductor die.

Semiconductor device with a noise prevention structure

A semiconductor device. The device includes a substrate of the first semiconductor type comprising a pad region and a noise prevention structure in the substrate, on least one side of the pad region. The device further includes the substrate structure, a pad, and a dielectric layer therebetween.

SEMICONDUCTOR STRUCTURE AND ASSOCIATED FABRICATING METHOD

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.

Semiconductor charge coupled device with split electrode configuration

Ohmische Elektrode, Verfahren zur Herstellung und integrierte Schaltung, die diese Elektrode benützt

Non-volatile semiconductor memory device with intrinsic charge trapping layer

A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween.

Semiconductor device and method of manufacturing semiconductor device

A conductive film having a first width in a first direction, an ONO film, and a control gate are formed above a tunnel gate insulating film. With the control gate as a mask, the conductive film is etched to form a floating gate. Then, an inter-layer insulating film is formed. A contact hole whose width in the first direction is larger than the first width is formed in the inter-layer insulating film. Then, sidewall spacer is formed on an inside wall of the contact hole.

Semiconductor device having switching element and free wheel diode and method for controlling the same

A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.

Method of forming a non-volatile electron storage memory and the resulting device

The invention provides a method of forming an electron memory storage device and the resulting device. The device comprises a gate structure which, in form, comprises a first gate insulating layer formed over a semiconductor substrate, a self-forming electron trapping layer of noble metal nano-crystals formed over the first gate insulating layer, a second gate insulating layer formed over the electron trapping layer, a gate electrode formed over the second gate insulating layer, and source and drain regions formed on opposite sides of the gate structure.

Trench mosfet having floating dummy cells for avalanche improvement

A trench MOSFET comprising source regions having a doping profile of a Gaussian-distribution along the top surface of epitaxial layer and floating dummy cells formed between edge trench and active area is disclosed. A SBR of n region existing at cell corners renders the parasitic bipolar transistor difficult to turn on, and the floating dummy cells having no parasitic bipolar transistor act as buffer cells to absorb avalanche energy when gate bias is increasing for turning on channel, therefore, the UIS failure issue is avoided and the avalanche capability of the trench MOSFET is enhanced.

Non-volatile memory device and sensing method for forming the same

A non-volatile memory device and a method for forming the same are disclosed, which relate to a ferroelectric memory device having non-volatile characteristics. The non-volatile memory device includes a control gate configured to receive a read voltage, an insulation film formed over the control gate, a metal layer formed over the insulation film, configured to include a channel region, and a drain region and source region at both ends of the channel region, a ferroelectric layer formed over the channel region of the metal layer, and a program and read gate formed over the ferroelectric layer. A write operation of data corresponding to a resistance state of the channel region is performed by changing polarity of the ferroelectric layer in response to a voltage applied to the program and read gate, the drain and source regions, and the control gate. A read operation of data is performed by sensing a current value changing with a polarity state of the ferroelectric layer on the condition that the read voltage is input to the control gate and a sensing bias voltage is input to one of the drain region and the source region.

Nonvolatile Semiconductor Memory Device Having Multi-Layered Oxide/(OXY) Nitride Film as Inter-Electrode Insulating Film and Manufacturing Method Thereof

A nonvolatile semiconductor memory device includes a first insulator, first conductor, element isolation insulator, second insulator and second conductor. The first insulator is formed on the main surface of a substrate and the first conductor is formed on the first insulator. The element isolation insulator is filled into at least part of both side surfaces of the first insulator in a gate width direction thereof and both side surfaces of the first conductor in a gate width direction thereof and is so formed that the upper surface thereof will be set with height between those of the upper and bottom surfaces of the first conductor. The second insulator includes a three-layered insulating film formed of a silicon oxide film, a silicon oxynitride film and a silicon oxide film formed on the first conductor and element isolation insulator. The second conductor is formed on the second insulator.

Semiconductor device with protective films and manufacturing method thereof

A semiconductor device includes a semiconductor substrate having a drain region, a source region and an impurity diffusion region; an oxide film formed on the impurity diffusion region; a first protective film including a SiN film as a principle component and being formed on the oxide film; and a second protective film containing carbon and being formed on the first protective film. A method of manufacturing the semiconductor device, includes doping an impurity into a semiconductor substrate, thereby forming a drain region, a source region and an impurity diffusion region; forming an oxide film on the impurity diffusion region; forming a first protective film including a SiN film as a principle component on the oxide film; and forming a second protective film containing carbon on the first protective film.

Reduced process sensitivity of electrode-semiconductor rectifiers

Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion.

Methods Of Forming Patterns, And Methods Of Forming Integrated Circuits

Some embodiments include methods of forming patterns in substrates by utilizing block copolymer assemblies as patterning materials. A block copolymer assembly may be formed over a substrate, with the assembly having first and second subunits arranged in a pattern of two or more domains. Metal may be selectively coupled to the first subunits relative to the second subunits to form a pattern of metal-containing regions and non-metal-containing regions. At least some of the block copolymer may be removed to form a patterned mask corresponding to the metal-containing regions. A pattern defined by the patterned mask may be transferred into the substrate with one or more etches. In some embodiments, the patterning may be utilized to form integrated circuitry, such as, for example, gatelines.

Integrated electronic device and method for manufacturing thereof

An embodiment of an integrated electronic device formed in a body of semiconductor material, which includes: a substrate of a first semiconductor material, the first semiconductor material having a first bandgap; a first epitaxial region of a second semiconductor material and having a first type of conductivity, which overlies the substrate and defines a first surface, the second semiconductor material having a second bandgap wider than the first bandgap; and a second epitaxial region of the first semiconductor material, which overlies, and is in direct contact with, the first epitaxial region. The first epitaxial region includes a first buffer layer, which overlies the substrate, and a drift layer, which overlies the first buffer layer and defines the first surface, the first buffer layer and the drift layer having different doping levels.

Patterning a gate stack of a non-volatile memory (nvm) with simultaneous etch in non-nvm area

Forming a gate stack of a non-volatile memory (NVM) over a substrate having an NVM region and non-NVM region which does not overlap the NVM region includes forming a select gate layer over the substrate in the NVM and non-NVM regions; simultaneously etching the select gate layer in the NVM and non-NVM regions; forming a charge storage layer over the substrate in the NVM and non-NVM regions; forming a control gate layer over the charge storage layer in the NVM and non-NVM regions; and simultaneously etching the charge storage layer in the NVM and the non-NVM regions. Etching the select gate layer in the NVM region results in a portion of the charge storage layer over a portion of the select gate layer and overlapping a sidewall of the select gate layer and results in a portion of the control gate layer over the portion of the charge storage layer.

Power semiconductor device and method of manufacturing the same

A power semiconductor device includes a first semiconductor layer of a first conductivity type, a first drift layer, and a second drift layer. The first drift layer includes a first epitaxial layer of the first conductivity type, a plurality of first first-conductivity-type pillar layers, and a plurality of first second-conductivity-type pillar layers. The second drift layer is formed on the first drift layer and includes a second epitaxial layer of the first conductivity type, a plurality of second second-conductivity-type pillar layers, a plurality of second first-conductivity-type pillar layers, a plurality of third second-conductivity-type pillar layers, and a plurality of third first-conductivity-type pillar layers. The plurality of second second-conductivity-type pillar layers are connected to the first second-conductivity-type pillar layers. The plurality of second first-conductivity-type pillar layers are connected to the first first-conductivity-type pillar layers. The plurality of third second-conductivity-type pillar layers are arranged on the first epitaxial layer.

Control device of semiconductor device

A control device of a semiconductor device is provided. The control device of a semiconductor device is capable of reducing both ON resistance and feedback capacitance in a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided. In the control device controlling driving of a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided, a signal of tuning ON or OFF is outputted to a gate electrode in a state of outputting a signal of turning OFF to the second gate electrode.

Nonvolatile semiconductor memory

According to one embodiment, in a nonvolatile semiconductor memory in which a charge store layer is formed on a tunnel insulating film formed on a channel region of a semiconductor substrate, a first nanoparticle layer containing first conductive nanoparticles is formed on the channel side, and a second nanoparticle layer containing a plurality of second conductive nanoparticles having an average particle size larger than the first conductive nanoparticles is formed on the charge store layer side. An average energy value ΔE 1 required for charging one electron in the first conductive nanoparticle is smaller than an average energy value ΔE required for charging one electron in the second conductive nanoparticle, and a difference between ΔE 1 and ΔE is larger than a heat fluctuation energy (k B T).

Power Semiconductor Chip Package

A device includes a vertical power semiconductor chip having an epitaxial layer and a bulk semiconductor layer. A first contact pad is arranged on a first main face of the power semiconductor chip and a second contact pad is arranged on a second main face of the power semiconductor chip opposite to the first main face. The device further comprises an electrically conducting carrier attached to the second contact pad.

Electrochemical sensors

Described herein are substrates, sensors and systems related to measuring the concentration of an analyte such as hydrogen ion in a sample. Redox active moieties whose reduction and/or oxidation potentials are sensitive to the presence of an analyte are immobilized onto a surface of an electrode. Immobilized redox active moieties whose reduction and/or oxidation potential are insensitive to the analyte can be used for reference. Voltammetric measurements made using such modified surfaces can accurately determine the presence and/or concentrations of analytes in a sample of interest. The electrochemical sensors of the invention are robust and can be made so as not to require calibration or recalibration.

Field modulating plate and circuit

Consistent with various example embodiments, a field-controlling electrode applies a negative bias, relative to a source/drain electrode, increase voltage breakdown. The field-controlling electrode is located over a channel region and between source and drain electrodes, and adjacent a gate electrode. The field electrode shapes a field in a portion of the channel region laterally between the gate electrode and one of the source/drain electrodes, in response to a negative bias applied thereto.

EEPROM-based, data-oriented combo NVM design

A nonvolatile memory device has a combination of FLOTOX EEPROM nonvolatile memory arrays. Each FLOTOX-based nonvolatile memory array is formed of FLOTOX-based nonvolatile memory cells that include at least one floating gate tunneling oxide transistor such that a coupling ratio of the control gate to the floating gate of the floating gate tunneling oxide transistor is from approximately 60% to approximately 70% and a coupling ratio of the floating gate to the drain region of the floating gate tunneling oxide transistor is maintained as a constant of is from approximately 10% to approximately 20% and such that a channel length of the channel region is decreased such that during the programming procedure a negative programming voltage level is applied to the control gate and a moderate positive programming voltage level is applied to the drain region to prevent the moderate positive programming voltage level from exceeding a drain-to-source breakdown voltage.

Method of forming lutetium and lanthanum dielectric structures

Methods of forming dielectric structures are shown. Methods of forming dielectric structures are shown that include lutetium oxide and lanthanum aluminum oxide crystals embedded within the lutetium oxide. Specific methods shown include monolayer deposition which yields process improvements such as chemistry control, step coverage, crystallinity/microstructure control.

Multi-gate bandgap engineered memory

Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation.

Dielectric stack

A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness T FD . A capping layer is formed on the substrate having a formed thickness T FC . Forming the capping layer consumes a desired amount of the device layer to cause the thickness of the device layer to be about the target thickness T TD . The thickness of the capping layer is adjusted from T FC to about a target thickness T TC .

Dummy gate for a high voltage transistor device

The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped regions are oppositely doped. The semiconductor device includes a first gate formed over the substrate. The first gate overlies a portion of the first doped region and a portion of the second doped region. The semiconductor device includes a second gate formed over the substrate. The second gate overlies a different portion of the second doped region. The semiconductor device includes a first voltage source that provides a first voltage to the second gate. The semiconductor device includes a second voltage source that provides a second voltage to the second doped region. The first and second voltages are different from each other.

Semiconductor device

A semiconductor device is disclosed wherein a peripheral region with a high breakdown voltage and high robustness against induced surface charge is manufactured using a process with high mass productivity. The device has n-type drift region and p-type partition region of layer-shape deposited in a vertical direction to one main surface of n-type semiconductor substrate with high impurity concentration form as drift layer, alternately adjacent parallel pn layers in a direction along one main surface. Active region through which current flows and peripheral region enclosing the active region include parallel pn layers. P-type partition region has impurity concentration distribution where concentration decreases from surface toward substrate side, n-type surface region disposed on parallel pn layers in peripheral region, p-type guard rings disposed separately from each other on n-type surface region, and field plate disposed on inner and outer circumferential sides of p-type guard rings, and electrically connected.

Trench-Gate Field Effect Transistors and Methods of Forming the Same

A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region.

Bipolar transistor with guard region

A bipolar transistor comprising an emitter region, a base region and a collector region, and a guard region spaced from and surrounding the base. The guard region can be formed in the same steps that form the base, and can serve to spread out the depletion layer in operation.

Methods of forming fine patterns and methods of fabricating semiconductor devices

Method of forming fine patterns and methods of fabricating semiconductor devices by which a photoresist (PR) pattern may be transferred to a medium material layer with a small thickness and a high etch selectivity with respect to a hard mask to form a medium pattern and the hard mask may be formed using the medium pattern. According to the methods, the PR pattern may have a low aspect ratio so that a pattern can be transferred using a PR layer with a small thickness without collapsing the PR pattern.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first semiconductor region and a second semiconductor region provided on a main surface of a substrate, being apart from each other and having first conductivity; a third semiconductor region provided between the first semiconductor region and the second semiconductor region and having second conductivity opposite to the first conductivity; a fourth semiconductor region provided on a main surface of the substrate, connected to the third semiconductor region, manufactured together with the third semiconductor region in the same manufacturing process, and having the conductivity same as that of the third semiconductor region; and trenches made on the main surface of the fourth semiconductor region and having a depth smaller than a junction depth of the fourth semiconductor region.

Non-volatile memory device and method of manufacturing the same

A non-volatile memory device includes a plurality of memory cells stacked along a channel protruded from a substrate, a first select transistor connected to one end of the plurality of memory cells, a first interlayer dielectric layer for being coupled between a source line and the first select transistor, and a second interlayer dielectric layer disposed between the first select transistor and the one end of the plurality of memory cells, and configured to include a first recess region.

Non-volatile memory and manufacturing method thereof and operating method of memory cell

A non-volatile memory and a manufacturing method thereof and a method for operating a memory cell are provided. The non-volatile memory includes a substrate, first and second doped regions, a charged-trapping structure, first and second gates and an inter-gate insulation layer. The first and second doped regions are disposed in the substrate and extend along a first direction. The first and second doped regions are arranged alternately. The charged-trapping structure is disposed on the substrate. The first and second gates are disposed on the charged-trapping structure. Each first gate is located above one of the first doped regions. The second gates extend along a second direction and are located above the second doped regions. The inter-gate insulation layer is disposed between the first gates and the second gates. Adjacent first and second doped regions and the first gate, the second gate and the charged-trapping structure therebetween define a memory cell.

Retention in nvm with top or bottom injection

Retention of charges in a nonvolatile memory (NVM) cell having a nitride-based injector (such as SiN, SIRN, SiON) for facilitating injection of holes into a charge-storage layer (for NROM, nitride) of a charge-storage stack (for NROM, ONO) may be improved by providing an insulating layer (for NROM, oxide) between the charge-storage layer and the injector has a thickness of at least 3 nm. Top and bottom injectors are disclosed. Methods of operating NVM cells are disclosed. The NVM cell may be NROM, SONOS, or other oxide-nitride technology NVM cells such as SANOS, MANOS, TANOS.

Semiconductor component with high breakthrough tension and low forward resistance

A semiconductor component having a semiconductor body is disclosed. In one embodiment, the semiconductor component includes a drift zone of a first conductivity type, a drift control zone composed of a semiconductor material which is arranged adjacent to the drift zone at least in places, a dielectric which is arranged between the drift zone and the drift control zone at least in places. A quotient of the net dopant charge of the drift control zone, in an area adjacent to the accumulation dielectric and the drift zone, divided by the area of the dielectric arranged between the drift control zone and the drift zone is less than the breakdown charge of the semiconductor material in the drift control zone.

Oxide terminated trench mosfet with three or four masks

An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process.

Method of removing nanocrystals

A method for forming a semiconductor structure includes providing a semiconductor layer, forming nanocrystals over the semiconductor layer, and using a solution comprising pure water, hydrogen peroxide, and ammonium hydroxide to remove at least a portion of the nanocrystals. A ratio by volume of pure water to ammonium hydroxide of the solution may be equivalent to or less than a ratio by volume of 10:1 of pure water to ammonium hydroxide when ammonium hydroxide has a concentration of 29% ammonia by weight. The step of using the solution to remove the at least a portion of the nanocrystals may be performed at a temperature of 50 degrees Celsius or more.

Diode

A diode has a semiconductor layer and cathode and anode electrodes on a surface of the semiconductor layer. The semiconductor layer has cathode and anode regions respectively contacting the cathode and anode electrodes. The anode region has a first diffusion region having high surface concentration, a second diffusion region having intermediate surface concentration, and a third diffusion region having low surface concentration. The first diffusion region is covered with the second and third diffusion regions. The second diffusion region has a first side surface facing the cathode region, a second side surface opposite to the cathode region, and a bottom surface extending between the first and second side surfaces. The third diffusion region covers at least one of the first corner part connecting the first side surface with the bottom surface and the second corner part connecting the second side surface with the bottom surface.

Non-volatile storage system with shared bit lines connected to single selection device

A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line.

Process margin engineering in charge trapping field effect transistors

Embodiments of the present technology are directed toward charge trapping region process margin engineering for charge trapping field effect transistor. The techniques include forming a plurality of shallow trench isolation regions on a substrate, wherein the tops of the shallow trench isolation regions extend above the substrate by a given amount. A portion of the substrate is oxidized to form a tunneling dielectric region. A first set of one or more nitride layers are deposited on the tunneling dielectric region and shallow trench isolation regions, wherein a thickness of the first set of nitride layers is approximately half of the given amount that the tops of the shallow trench isolation regions extend above the substrate. A portion of the first set of nitride layers is etched back to the tops of the trench isolation regions. A second set of one or more nitride layers is deposited on the etched back first set of nitride layers. The second set of nitride layers is oxidized to form a charge trapping region on the tunneling dielectric region and a blocking dielectric region on the charge trapping region. A gate region is then deposited on the blocking dielectric region.

Semiconductor Device

A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type.

Semiconductor device

In a semiconductor power device such as a power MOSFET having a super-junction structure in each of an active cell region and a chip peripheral region, an outer end of a surface region of a second conductivity type coupled to a main junction of the second conductivity type in a surface of a drift region of a first conductivity type and having a concentration lower than that of the main junction is located in a middle region between an outer end of the main junction and an outer end of the super-junction structure in the chip peripheral region.

Lateral extended drain metal oxide semiconductor field effect transistor (ledmosfet) with tapered dielectric plates to achieve a high drain-to-body breakdown voltage, a method of forming the transistor and a program storage device for designing the transistor

A lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) with a high drain-to-body breakdown voltage (Vb) incorporates gate structure extensions on opposing sides of a drain drift region. The extensions are tapered such that a distance between each extension and the drift region increases linearly from one end adjacent to the channel region to another end adjacent to the drain region. In one embodiment, these extensions can extend vertically through the isolation region that surrounds the LEDMOSFET. In another embodiment, the extensions can sit atop the isolation region. In either case, the extensions create a strong essentially uniform horizontal electric field profile within the drain drift. Also disclosed are a method for forming the LEDMOSFET with a specific Vb by defining the dimensions of the extensions and a program storage device for designing the LEDMOSFET to have a specific Vb.

Self-Aligned Contacts for High k/Metal Gate Process Flow

A semiconductor structure is provided that includes a semiconductor substrate having a plurality of gate stacks located on a surface of the semiconductor substrate. Each gate stack includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a conductive metal. A spacer is located on sidewalls of each gate stack and a self-aligned dielectric liner is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy. A contact metal is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner. The structure also includes another contact metal having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks. Methods of forming the semiconductor structure using a replacement gate and a non-replacement gate scheme are also disclosed.

Non-volatile finfet memory array and manufacturing method thereof

An electronic device includes a substrate with a semiconducting surface having a plurality of fin-type projections coextending in a first direction through a memory cell region and select gate regions. The electronic device further includes a dielectric isolation material disposed in spaces between the projections. In the electronic device, the dielectric isolation material in the memory cell regions have a height less than a height of the projections in the memory cell regions, and the dielectric isolation material in the select gate regions have a height greater than or equal to than a height of the projections in the select gate regions. The electronic device further includes gate features disposed on the substrate within the memory cell region and the select gate regions over the projections and the dielectric isolation material, where the gate features coextend in a second direction transverse to the first direction.

Vertical channel type non-volatile memory device and method for fabricating the same

A method for fabricating a vertical channel type non-volatile memory device including forming a source region, alternately forming a plurality of interlayer dielectric layers and a plurality of conductive layers for a gate electrode over a substrate with the source region formed therein, forming a trench exposing the source region by etching the plurality of interlayer dielectric layers and the plurality of conductive layers for a gate electrode, and siliciding the conductive layers for a gate electrode and the source region that are exposed through the trench.

Methods for manufacturing superjunction semiconductor device having a dielectric termination

A superjunction semiconductor device is provided having at least one column of a first conductivity type and at least one column of a second conductivity type extending from a first main surface of a semiconductor substrate toward a second main surface of the semiconductor substrate opposed to the first main surface. The at least one column of the second conductivity type has a first sidewall surface proximate the at least one column of the first conductivity type and a second sidewall surface opposed to the first sidewall surface. A termination structure is proximate the second sidewall surface of the at least one column of the second conductivity type. The termination structure includes a layer of dielectric of an effective thickness and consumes about 0% of the surface area of the first main surface. Methods for manufacturing superjunction semiconductor devices and for preventing surface breakdown are also provided.

Semiconductor device and manufacturing method thereof

A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate. Then, on the wafer, a trench to become a scribing line is formed with a crystal face exposed so as to form a side wall of the trench. On that side wall, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to dice a collector electrode, formed on the p collector region, together with the p collector region.

Method for Manufacturing a Semiconductor Device

A method for forming a semiconductor device is provided. The method includes providing a semiconductor body with a horizontal surface. An epitaxy hard mask is formed on the horizontal surface. An epitaxial region is formed by selective epitaxy on the horizontal surface relative to the epitaxy hard mask so that the epitaxial region is adjusted to the epitaxy hard mask. A vertical trench is formed in the semiconductor body. An insulated field plate is formed in a lower portion of the vertical trench and an insulated gate electrode is formed above the insulated field plate. Further, a method for forming a field-effect semiconductor device is provided.

Method of forming a semiconductor device termination and structure therefor

At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer.

Polysilicon control etch back indicator

This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

Nonvolatile semiconductor memory device and method of manufacturing the same

According to one embodiment, a nonvolatile semiconductor memory device includes an element region, a gate insulating film, a first gate electrode, an intergate insulating film, a second gate electrode and an element isolation region. The gate insulating film is formed on the element region. The first gate electrode is formed on the gate insulating film. The intergate insulating film is formed on the first gate electrode and has an opening. The second gate electrode is formed on the intergate insulating film and in contact with the first gate electrode via the opening. The element isolation region encloses a laminated structure formed by the element region, the gate insulating film, and the first gate electrode. The air gap is formed between the element isolation region and side surfaces of the element region, the gate insulating film and the first gate electrode.

Semiconductor device and method of manufacturing the same

A gate electrode, an element isolation film and a drain region in an LDMOS transistor formation region and a gate electrode, an element isolation film and an anode region in an ESD protection element formation region are formed to satisfy relationships of A 1 ≧A 2 and B 1 <B 2 where the LDMOS transistor formation region has an overlap length A 1 of the gate electrode and the element isolation film and a distance B 1 between the gate electrode and the drain region, and the ESD protection element formation region has an overlap length A 2 of the gate electrode and the element isolation film and a distance B 2 between the gate electrode and the anode region.

Semiconductor device

A semiconductor device comprises a semiconductor substrate; an element-forming region that includes semiconductor elements formed on the semiconductor substrate; a buried electrode plug formed so as to penetrate through the semiconductor substrate; and a trench-type electrode that is buried in a trench within the semiconductor substrate positioned between the element-forming region and the buried electrode plug.

Hybrid split gate semiconductor

In an embodiment in accordance with the present invention, a semiconductor device includes a vertical channel region, a gate at a first depth on a first side of the vertical channel region, a shield electrode at a second depth on the first side of the vertical channel region, and a hybrid gate at the first depth on a second side of the vertical channel region. The region below the hybrid gate on the second side of the vertical channel region is free of any electrodes.

Semiconductor diodes with low reverse bias currents

A diode is described with a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, wherein a first terminal is an anode adjacent to the III-N material structure and a second terminal is a cathode in ohmic contact with the electrically conductive channel, and a dielectric layer over at least a portion of the anode. The anode comprises a first metal layer adjacent to the III-N material structure, a second metal layer, and an intermediary electrically conductive structure between the first metal layer and the second metal layer. The intermediary electrically conductive structure reduces a shift in an on-voltage or reduces a shift in reverse bias current of the diode resulting from the inclusion of the dielectric layer. The diode can be a high voltage device and can have low reverse bias currents.

Semiconductor memory device including multi-layer gate structure

A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.

Floating gate flash cell device and method for partially etching silicon gate to form the same

A method for forming a split gate flash cell memory device provides for establishing a floating gate region then using spacers or other hard mask materials that cover opposed edges of a gate electrode material in the gate region, to serve as hard masks during an etching operation that partially etches the gate electrode material which may be polysilicon. The gate electrode so produced serves as a floating gate electrode and includes a recessed central portion flanked by a pair of opposed upwardly extending fins which may terminate upwardly at an apex. A floating gate oxide is then formed by thermal oxidation and/or oxide deposition techniques.

High temperature performance capable gallium nitride transistor

A transistor device capable of high performance at high temperatures. The transistor comprises a gate having a contact layer that contacts the active region. The gate contact layer is made of a material that has a high Schottky barrier when used in conjunction with a particular semiconductor system (e.g., Group-III nitrides) and exhibits decreased degradation when operating at high temperatures. The device may also incorporate a field plate to further increase the operating lifetime of the device.

Twin-Drain Spatial Wavefunction Switched Field-Effect Transistors

A field-effect transistor is provided and includes source, gate and drain regions, where the gate region controls charge carrier location in the transport channel, the transport channel includes a asymmetric coupled quantum well layer, the asymmetric quantum well layer includes at least two quantum wells separated by a barrier layer having a greater energy gap than the wells, the transport channel is connected to the source region at one end, and the drain regions at the other, the drain regions include at least two contacts electrically isolated from each other, the contacts are connected to at least one quantum well. The drain may include two regions that are configured to form the asymmetric coupled well transport channel. In an embodiment, two sources and two drains are also envisioned.

Flash cell with floating gate transistors formed using spacer technology

Methods for forming split gate flash cell structures provide for symmetrical cells that are immune to misalignment of the photoresist pattern when forming the control gates. Spacers are utilized to form the floating gates in the floating gate transistors used in the flash cells. The spacers may be oxide spacers used to mask a polysilicon layer that will form the floating gates or the spacers may be polysilicon spacers that will themselves form the floating gates. The inter-gate oxide of the floating gate transistors may be formed using HTO or may be deposited. Hard mask spacers are used in conjunction with the control gate photoresist patterning operation to control the size and configuration of the control gate and the channel length.

Normally-Off Semiconductor Devices

Normally-off semiconductor devices are provided. A Group III-nitride buffer layer is provided. A Group III-nitride barrier layer is provided on the Group III-nitride buffer layer. A non-conducting spacer layer is provided on the Group III-nitride barrier layer. The Group III-nitride barrier layer and the spacer layer are etched to form a trench. The trench extends through the barrier layer and exposes a portion of the buffer layer. A dielectric layer is formed on the spacer layer and in the trench and a gate electrode is formed on the dielectric layer. Related methods of forming semiconductor devices are also provided herein.

Inter-poly dielectric in a shielded gate mosfet device

In one general aspect, an apparatus can include a shield dielectric disposed within a trench aligned along an axis within an epitaxial layer of a semiconductor, and a shield electrode disposed within the shield dielectric and aligned along the axis. The apparatus can include a first inter-poly dielectric having a portion intersecting a plane orthogonal to the axis where the plane intersects the shield electrode, and a second inter-poly dielectric having a portion intersecting the plane and disposed between the first inter-poly dielectric and the shield electrode. The apparatus can also include a gate dielectric having a portion disposed on the first inter-poly dielectric.

Split-gate non-volatile memory cells having improved overlap tolerance

Embodiments include a split-gate non-volatile memory cell that is formed having a control gate and a select gate, where at least a portion of the control gate is formed over the select gate. A charge storage layer is formed between the select gate and the control gate. The select gate is formed using a first conductive layer and a second conductive layer. The second conductive layer is formed over the first conductive layer and has a lower resistivity than the first conductive layer. In one embodiment, the first conductive layer is polysilicon and the second conductive layer is titanium nitride (TiN). In another embodiment, the second conductive layer may be a silicide or other conductive material, or combination of conductive materials having a lower resistivity than the first conductive layer.

Semiconductor device

A semiconductor layer has a second impurity concentration. First trenches are formed in the semiconductor layer to extend downward from an upper surface of the semiconductor layer. Each of insulation layers is formed along each of the inner walls of the first trenches. Each of conductive layers is formed to bury each of the first trenches via each of the insulation layers, and extends downward from the upper surface of the semiconductor layer to a first position. A first semiconductor diffusion layer reaches a second position from the upper surface of the semiconductor layer, is positioned between the first trenches, and has a third impurity concentration lower than the second impurity concentration. A length from the upper surface of the semiconductor layer to the second position is equal to or less than half a length from the upper surface of the semiconductor layer to the first position.

Semiconductor device and manufacturing method of the same

In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n + -type semiconductor region of the protective diode are formed in the same step.

Graphene electronic device and method of fabricating the same

The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.

Semiconductor device and method of manufacturing the same

A semiconductor device in accordance with one embodiment of the invention can include a semiconductor substrate having a groove, a bit line, a pocket implantation region, a bottom insulating membrane, and a charge accumulation region. The bit line is formed on a side of the groove in the semiconductor substrate and acts as a source and a drain. The pocket implantation region is formed to touch (or contact) the bit line, has a similar conductivity type as the semiconductor substrate, and has a dopant concentration higher than that of the semiconductor substrate. The bottom insulating membrane is formed on and touches (or contacts) a side surface of the groove. The charge accumulation layer is formed on and touches (or contacts) a side surface of the bottom insulating membrane.

Superjunction Structures for Power Devices and Methods of Manufacture

A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

High electron mobility transistor

A high electron mobility transistor (HEMT) includes a substrate, a heterojunction on the substrate including a first layer having a Group III-nitride semiconductor material interfaced to a second layer having a doped Group III-nitride semiconductor material. A gate electrode is on a surface of the heterojunction, and a source and a drain are on opposite sides of said gate electrode. A patterned field shaping (FS) layer formed from a wide band-gap semiconductor material is over the heterojunction on at least a portion between the gate electrode and the drain.

Integrating schottky diode into power mosfet

A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.

Structure and method for forming shielded gate trench fet with multiple channels

In one embodiment, an apparatus can include a trench extending into a semiconductor region of a first conductivity type, an electrode disposed in the trench, and a source region of the first conductivity type abutting a sidewall of the trench. The apparatus can include a first well region of a second conductivity type disposed in the semiconductor region below the source region and abutting the sidewall of the trench lateral to the electrode where the second conductivity type is opposite the first conductivity type. The apparatus can also include a second well region of the second conductivity type disposed in the semiconductor region and abutting the sidewall of the trench, and a third well region of the first conductivity type disposed between the first well region and the second well region.

Inverted-trench grounded-source fet structure using conductive substrates, with highly doped substrates

This invention discloses an inverted field-effect-transistor (iT-FET) semiconductor device that includes a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate. The semiconductor power device further comprises a trench-sidewall gate placed on sidewalls at a lower portion of a vertical trench surrounded by a body region encompassing a source region with a low resistivity body-source structure connected to a bottom source electrode and a drain link region disposed on top of said body regions thus constituting a drift region. The drift region is operated with a floating potential said iT-FET device achieving a self-termination.

Non-volatile memory devices and methods of forming the same

A non-volatile may include a plurality of device isolation patterns disposed in a substrate to define an active region extending in a first direction, a gate pattern disposed on the substrate to extend in a second direction crossing the first direction, a charge storing pattern disposed between the active region and the gate pattern, a blocking dielectric layer disposed between the charge storing pattern and the gate pattern, and a tunnel dielectric layer disposed between the active region and the charge storing pattern. A center area of a top surface of the active region includes one of a rounded surface or a tip, and the center area of the top surface of the active region corresponds to an uppermost portion of the active region and the uppermost portion of the active region is disposed at a level lower than a lowermost portion of the gate pattern.

Structures and Methods of Improving Reliability of Non-Volatile Memory Devices

In one example, the memory device disclosed herein includes a gate insulation layer and a charge storage layer positioned above the gate insulation layer, wherein the charge storage layer has a first width. The device further includes a blocking insulation layer positioned above the charge storage layer and a gate electrode positioned above the blocking insulation layer, wherein the gate electrode has a second width that is greater than the first width. An illustrative method disclosed herein includes forming a gate stack for a memory device, wherein the gate stack includes a gate insulation layer, an initial charge storage layer, a blocking insulation layer and a gate electrode, and wherein the initial charge storage layer has a first width. The method further includes performing an etching process to selectively remove at least a portion of the initial charge storage layer so as to produce a charge storage layer having a second width that is less than the first width of the initial charge storage layer.

Method of manufacturing semiconductor device and semiconductor device

Techniques capable of improving the yield of IGBTs capable of reducing steady loss, turn-off time, and turn-off loss are provided. Upon formation of openings in an interlayer insulting film formed on a main surface of a substrate, etching of a laminated insulating film of a PSG film and an SOG film and a silicon oxide film is once stopped at a silicon nitride film. Then, the silicon nitride film and the silicon oxide film are sequentially etched to form the openings. As a result, the openings are prevented from penetrating through an n-type source layer and a p + -type emitter layer having a thickness of 20 to 100 nm and reaching the substrate.

High voltage and ultra-high voltage semiconductor devices with increased breakdown voltages

A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.

3-dimensional non-volatile memory device and method of manufacturing the same

A non-volatile memory device comprising a plurality of strings each including a drain select transistor, drain-side memory cells, a pipe transistor, source-side memory cells, and a source select transistor coupled in series, wherein the plurality of strings are arranged in a first direction and a second direction, and the strings arranged in the second direction form each of string columns; a plurality of bit lines extended in the second direction and coupled to the drain select transistors of the strings included in each string column; and a plurality of source lines extended in the first direction and in common coupled to the source select transistors of strings adjacent to each other in the second direction, wherein strings included in one of the string columns are staggered in the first direction and each of the string columns are coupled to at least two of the bit lines.

Transistor with controllable compensation regions

Disclosed is a MOSFET including at least one transistor cell. The at least one transistor cell includes a source region, a drain region, a body region and a drift region. The body region is arranged between the source region and the drift region and the drift region is arranged between the body region and the drain region. The at least one transistor cell further includes a compensation region arranged in the drift region and distant to the body region, a source electrode electrically contacting the source region and the body region, a gate electrode arranged adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a coupling arrangement including a control terminal. The coupling arrangement is configured to electrically couple the compensation region to at least one of the body region, the source region, the source electrode and the gate electrode dependent on a control signal received at the control terminal.

Semiconductor power device

A semiconductor power device includes a substrate, a first semiconductor layer on the substrate, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer. At least a recessed epitaxial structure is disposed within a cell region and the recessed epitaxial structure may be formed in a pillar or stripe shape. A first vertical diffusion region is disposed in the third semiconductor layer and the recessed epitaxial structure is surrounded by the first vertical diffusion region. A source conductor is disposed on the recessed epitaxial structure and a trench isolation is disposed within a junction termination region surrounding the cell region. In addition, the trench isolation includes a trench, a first insulating layer on an interior surface of the trench, and a conductive layer filled into the trench, wherein the source conductor connects electrically with the conductive layer.

Compound semiconductor device and method for manufacturing the same

An AlGaN/GaN-HEMT has a structure including: compound semiconductor layers formed on a substrate; a gate electrode, a gate pad that has a current path formed between the gate electrode and itself, and a semiconductor layer that is spontaneously polarized and piezoelectrically polarized, which are formed on the compound semiconductor layer; and a gate electrode connection layer formed on the semiconductor layer, wherein the gate electrode connection layer and the gate electrode are electrically connected with each other. This structure which is relatively simple allows the AlGaN/GaN-HEMT to realize an intended normally-off operation without causing such inconveniences as increase in a sheet resistance, increase in an on-resistance, and increase in a leakage current.

Semiconductor devices

An object of the present application is to reduce the gate capacitance without lowering the withstand voltage of a semiconductor device and prevent generation of a leak current between main electrodes even when an oxide film is formed poorly. A semiconductor device of the present application comprises a gate electrode and a dummy gate electrode. The gate electrode is insulated from an emitter electrode and faces a part of a body region via an insulating film, the part of the body region separating a drift region and an emitter region from each other. The dummy gate electrode is electrically connected with the emitter electrode and is connected with the drift region and the body region via the insulating film. At least a part of the dummy gate electrode comprises a first conductive region of the same type as the drift region. In the dummy gate electrode, the emitter electrode is separated from the drift region by the first conductive region.

Floating gate device with oxygen scavenging element

A floating gate device is provided. A tunnel oxide layer is formed over the channel. A floating gate is formed over the tunnel oxide layer. A high-k dielectric layer is formed over the floating gate. A control gate is formed over the high-k dielectric layer. At least one of the control gate and/or the floating gate includes an oxygen scavenging element. The oxygen scavenging element is configured to decrease an oxygen density at least one of at a first interface between the control gate and the high-k dielectric layer, at a second interface between the high-k dielectric layer and the floating gate, at a third interface between the floating gate and the tunnel oxide layer, and at a fourth interface between the tunnel oxide layer and the channel responsive to annealing.

Semiconductor device and method of manufacturing semiconductor device

A conductive film having a first width in a first direction, an ONO film, and a control gate are formed above a tunnel gate insulating film. With the control gate as a mask, the conductive film is etched to form a floating gate. Then, an inter-layer insulating film is formed. A contact hole whose width in the first direction is larger than the first width is formed in the inter-layer insulating film. Then, sidewall spacer is formed on an inside wall of the contact hole.

Semiconductor structures including bodies of semiconductor material, devices including such structures and related methods

Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. The bodies may be electrically coupled by one or more conductive structures, which may be used as an interconnect structure to electrically couple components of memory devices. By providing isolation between the bodies, the semiconductor structure provides the properties of a conventional SOI substrate (e.g., high speed, low power, increased device density and isolation) while substantially reducing fabrication acts and costs associated with such SOI substrates. Additionally, the semiconductor structures of the present disclosure provide reduced parasitic coupling and current leakage due to the isolation of the bodies by the intervening dielectric material.

Method for producing a semiconductor device including a dielectric layer

A semiconductor device with a dielectric layer is produced by providing a semiconductor body with a first trench extending into the semiconductor body, the first trench having a bottom and a sidewall. A first dielectric layer is formed on the sidewall in a lower portion of the first trench and a first plug is formed in the lower portion of the first trench so as to cover the first dielectric layer. The first plug leaves an upper portion of the sidewall uncovered. A sacrificial layer is formed on the sidewall in the upper portion of the first trench and a second plug is formed in the upper portion of the first trench. The sacrificial layer is removed so as to form a second trench having sidewalls and a bottom. A second dielectric layer is formed in the second trench and extends to the first dielectric layer.

Mosfet-schottky rectifier-diode integrated circuits with trench contact structures

A trench MOSFET device with embedded Schottky rectifier, Gate-Drain and Gate-Source clamp diodes on single chip is formed to achieve device shrinkage and performance improvement. The present semiconductor devices achieve low Vf and reverse leakage current for embedded Schottky rectifier, have overvoltage protection for Gate-Source clamp diode and avalanche protection for Gate-Drain clamp diode.

Split-gate flash memory exhibiting reduced interference

A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.

High Voltage Resistor with High Voltage Junction Termination

Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a substrate that includes a doped well disposed therein. The doped well and the substrate have opposite doping polarities. The high voltage semiconductor device includes an insulating device disposed over the doped well. The high voltage semiconductor device includes an elongate resistor disposed over the insulating device. A non-distal portion of the resistor is coupled to the doped well. The high voltage semiconductor device includes a high-voltage junction termination (HVJT) device disposed adjacent to the resistor.

Semiconductor device

A semiconductor device includes a stripe-shaped gate trench formed in one major surface of n-type drift layer, a gate trench including gate polysilicon formed therein, and a gate polysilicon connected to a gate electrode. A p-type base layer is formed selectively in mesa region between adjacent gate trenches and a p-type base layer including an n-type emitter layer and connected to emitter electrode. One or more dummy trenches are formed between p-type base layers adjoining to each other in the extending direction of gate trenches. An electrically conductive dummy polysilicon is formed on an inner side wall of dummy trench with a gate oxide film interposed between the dummy polysilicon and dummy trench. The dummy polysilicon is spaced apart from the gate polysilicon and may be connected to the emitter electrode.

Method for fabricating a damascene self-aligned ferroelectric random access memory (f-ram) device structure employing reduced processing steps

Disclosed is a novel non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM device structure on a planar surface using a reduced number of masks and etching steps.

Methods and apparatuses including memory cells with air gaps and other low dielectric constant materials

Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. A charge storage element, such as a floating gate or charge trap, is between the first dielectric material and the second dielectric material and adjacent to the conductive material. The charge storage element has a first surface and a second surface. The first and second surfaces are substantially separated from the first dielectric material and the second dielectric material, respectively, by a first air gap and a second air gap. Additional apparatuses and methods are disclosed.

Trenched power semiconductor device and fabrication method thereof

A trenched power semiconductor device on a lightly doped substrate is provided. The device has a base, a plurality of trenches including at least a gate trench, a plurality of first heavily doping regions, a body region, a source doped region, a contact window, a second heavily doped region, and a metal layer. The trenches are formed in the base. The first heavily doped regions are beneath the trenches respectively and spaced from the bottom of the respective trench with a lightly doped region. The body region encircles the trenches and is away from the first heavily doped region with a predetermined distance. The source doped region is in an upper portion of the body region. The contact window is adjacent to the edge of the base. The second heavily doped region is below the contact window filled by the metal layer for electrically connecting the second heavily doped region.

Nonvolatile memory device and method of manufacturing the same

A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

Semiconductor device with high-voltage breakdown protection

A semiconductor device includes: a semiconductor substrate having a first conductivity type; a well having a second conductivity type and provided inside the semiconductor substrate; a first impurity region having the first conductivity type and provided within the well; a second impurity region having the second conductivity type, provided inside the well and away from the first impurity region; and a third impurity region having a first conductivity type, provided surrounding the well and away from the second impurity region. In this semiconductor device, the well is formed to be deeper than the first impurity region, the second impurity region, and the third impurity region, in a thickness direction of the semiconductor substrate; and a minimum distance between the first impurity region and the second impurity region is smaller than a minimum distance between the second impurity region and the third impurity region.

Power semiconductor device

A power semiconductor device includes a high resistance epitaxial layer having a first pillar region and a second pillar region as a drift layer. The first pillar region includes a plurality of first pillars of the first conductivity type and a plurality of second pillars of the second conductivity type disposed alternately along a first direction. The second pillar region is adjacent to the first pillar region along the first direction. The second pillar region includes a third pillar and a fourth pillar of a conductivity type opposite to a conductivity type of the third pillar. A net quantity of impurities in the third pillar is less than a net quantity of impurities in each of the plurality of first pillars. A net quantity of impurities in the fourth pillar is less than the net quantity of impurities in the third pillar.

Semiconductor device and manufacturing method thereof

A semiconductor device has first and second conductive type transistors on a substrate. First conductive type transistor includes: a first lower gate electrode portion on the substrate, including silicon including first impurity ions; a first intervening layer on the first lower gate electrode portion, including silicon including oxygen and/or nitrogen; and a first upper gate electrode portion on the first intervening layer, the first upper gate electrode portion including silicon including the first impurity ions. Second conductive type transistor includes: a second lower gate electrode portion on the substrate, the second lower gate electrode portion including silicon including second impurity ions; a second intervening layer on the second lower gate electrode portion, the second intervening layer including silicon including oxygen and/or nitrogen; and a second upper gate electrode portion on the second intervening layer, the second upper gate electrode portion including silicon including the second impurity ions.

Semiconductor structure including guard ring

One or more embodiments relate to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer guard ring and the conductive feature, the inner guard ring being electrically coupled to the conductive feature.

Semiconductor device

A semiconductor device is free from degradation of characteristics attributable to a manufacturing process thereof and its characteristics are hardly affected by changes in electric potentials of bonding pads. The semiconductor device 10 includes an active region 12 , a first insulating layer 13 covering the active region 12 , a floating conductor 14 formed on the first insulating layer 13 , a second insulating layer 15 formed on the first insulating layer 13 and the floating conductor 14 , a bonding pad 18 formed on the second insulating layer 17 and interconnection vias 19, 20 for electrically connecting the active region 12 and the bonding pad 18.

Semiconductor device

A semiconductor device according to an embodiment includes: a first transistor including a gate connected to a first interconnection, a first source, and a first drain, one of the first source and the first drain being connected to a second interconnection; and a second transistor including a gate structure, a second source, and a second drain, one of the second source and second drain being connected to a third interconnection and the other of the second source and second drain being connected to a fourth interconnection. The gate structure includes a gate insulation film, a gate electrode, and a threshold-modulating film provided between the gate insulation film and the gate electrode to modulate a threshold voltage, the other of the first source and first drain of the first transistor is connected to the gate electrode.

CHARGE TRAP TYPE NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

There is provided a charge trap type non-volatile memory device and a method for fabricating the same, the charge trap type non-volatile memory device including: a tunnel insulation layer formed over a substrate; a charge trap layer formed over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer; a charge barrier layer formed over the charge trap layer; a gate electrode formed over the charge barrier layer; and an oxide-based spacer formed over sidewalls of the charge trap layer and provided to isolate the charge trap layer. 1. A method of fabricating a charge trap type non-volatile memory device , comprising:forming a tunnel insulation layer over a substrate;forming a charge trap layer over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer;forming a charge barrier layer over the charge trap layer;forming a gate electrode conductive layer over the charge barrier layer;etching the gate electrode conductive layer, the charge barrier layer, the charge trap layer, and the tunnel insulation layer to form a charge trap structure; andforming an oxide-based spacer over sidewalls of the etched charge trap layer, wherein forming the charge trap structure comprises:etching the gate electrode conductive layer to form a gate electrode;forming a nitride-based spacer over sidewalls of the gate electrode;etching the charge barrier layer, the charge trap layer, and the tunnel insulation layer using the nitride-based spacer, wherein the tunnel insulation layer is partially etched so that the substrate is not exposed; andperforming an oxidation process over the substrate structure to form an oxide-based spacer over sidewalls of the etched charge trap layer.2. The method of claim 1 , wherein the performing the oxidation process comprises using a radical oxidation method.3. The method of claim 1 , wherein forming the ...

NONVOLATILE STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME

Provided is an excellent nonvolatile storage device having advantageous in miniaturization and less variation in initial threshold value, and exhibiting a high writing efficiency, without an erasing failure and a retention failure. The nonvolatile storage device is characterized by including a film stack extending from between a semiconductor substrate and a gate electrode onto at least a surface of the gate electrode lying on a first impurity diffusion region side, the film stack including a charge accumulating layer and a tunnel insulating film sequentially from a gate electrode side. 1. A method for manufacturing a nonvolatile storage device including:a gate electrode provided on a semiconductor substrate; anda film stack extending from between the semiconductor substrate and the gate electrode onto at least a surface of the gate electrode lying on a first impurity diffusion region side and being in contact with a first impurity diffusion region, the film stack including a charge accumulating layer and a tunnel insulating film,the method comprising:(1) preparing the semiconductor substrate;(2) forming a sacrificed oxidation film and a dummy film on the semiconductor substrate;(3) partially removing the sacrificed oxidation film and the dummy film to form an opening portion reaching the semiconductor substrate and then to expose the semiconductor substrate in a lower portion of the opening portion;(4) depositing a tunnel insulating film material and a charge accumulating layer material sequentially over an entire surface of the semiconductor substrate;(5) depositing a gate electrode material over an entire surface of the charge accumulating layer material;(6) etching back the tunnel insulating film material, the charge accumulating layer material and the gate electrode material, to leave the tunnel insulating film material, the charge accumulating layer material and the gate electrode material on each of side surfaces of the opening portion opposed to each other, ...

Semiconductor device and capacitor

The present invention relates to a semiconductor device including nanodots and a capacitor. A semiconductor device includes a channel layer, a tunnel insulating layer formed on the channel layer, a memory layer formed on the tunnel insulating layer and including first nanodots, a charge blocking layer formed on the memory layer, a gate electrode conductive layer formed on the charge blocking layer, and a buffer layer located, at least one of, inside the tunnel insulating layer, inside the charge blocking layer, at an interface between the tunnel insulating layer and the memory layer and at the interface between the charge blocking layer and the memory layer, wherein the buffer layer includes second nanodots.