Elektrisch schreib- und löschbare Speicherzellenanordnung und Verfahren zu deren Herstellung

METHOD OF MAKING A TWO-TRANSISTOR MONOLITHIC INTEGRATED MEMORY CELL USING MOS TECHNOLOGY

SPEICHERZELLE MIT FLOATING-GATE-STRUKTUR MIT FLACHER OBERSEITE

Eine Speicherzelle, z. B. eine Flash-Speicherzelle, weist ein Substrat, ein Floating Gate mit flacher Oberseite, das über dem Substrat ausgebildet ist, und einen Oxidbereich mit flacher Oberseite auf, der über dem Floating Gate mit flacher Oberseite ausgebildet ist. Das Floating Gate mit flacher Oberseite kann eine Seitenwand mit einer im Allgemeinen konkaven Form aufweisen, die einen spitzen Winkel an einer oberen Ecke des Floating Gate definiert, wodurch eine Programmier- oder Löscheffizienz der Speicherzelle verbessert werden kann. Das Floating Gate mit flacher Oberseite und der darüber liegende Oxidbereich können ohne thermische Oxidation des Floating Gate ausgebildet werden, die ein herkömmliches „Football-Oxid“ ausbildet. Eine Wortleitung und ein separates Lösch-Gate können über dem Floating Gate und dem Oxidbereich ausgebildet sein. Das Lösch-Gate kann das Floating Gate um eine wesentlich größere Strecke überlappen, als die Wortleitung das Floating Gate überlappt, wodurch die Programmier ...

Multi-bit memory element and production process has U-shaped trench structure with conductive region and insulating region containing at least two floating gates

A multi-bit memory element comprise a trench structure comprising an electrically conductive region (102) on which is an insulating region (103) in or on which are at least two floating gate regions (104a,104b) that are electrically isolated from one another and from the electrically conductive region. Preferably the trench is U-shaped with a curved base region and the insulating region comprises many insulating parts (103a,103b). An independent claim is also included for a production process for the above.

KURZKANAL-FLAHEEPROM-SPEICHERANORDNUNG MIT DOPPEL-DIFFUNDIERTER SOURCE UND VERFAHREN ZUR HERSTELLUNG

REDUZIERUNG VON LADUNGSVERLUSTEN IN NICHTFLÜCHTIGEN SPEICHERZELLEN DURCH PHOSPHORIMPLANTATION IN PECVD-NITRID/OXYNITRID-FILMEN

Verfahren zur Bearbeitung eines Trägers, Verfahren zur Herstellung einer Ladungsspeicherzelle, Verfahren zur Bearbeitung eines Chips und Verfahren zum elektrischen Kontaktieren einer Abstandhalterstruktur

Ein Verfahren (100) zur Bearbeitung eines Trägers gemäß verschiedenen Ausführungsformen kann enthalten: Bilden einer Struktur über dem Träger, wobei die Struktur mindestens zwei benachbarte Bauelemente aufweist, die mit einem ersten Abstand zueinander angeordnet sind (110); Abscheiden einer Abstandhalterschicht über der Struktur, wobei die Abstandhalterschicht mit einer Dicke größer als eine Hälfte des ersten Abstandes abgeschieden werden kann, wobei die Abstandhalterschicht elektrisch leitendes Abstandhaltermaterial enthalten kann (120); Entfernen eines Teils der Abstandhalterschicht, wobei Abstandhaltermaterial der Abstandhalterschicht in einem Bereich zwischen den mindestens zwei benachbarten Bauelementen verbleiben kann (130); und elektrische Kontaktierung des verbleibenden Abstandhaltermaterials (140).

Method of producing widened n-doped channel connection zones in a field effect semiconductor component and memory element use ion irradiation and then thermal treatment to form secondary defects

Forming widened n-doped channel connection zones (2) in a field effect-controlled semiconductor component comprises forming a p-doped region (8) with a p-doped channel (7) between it and an n-doped surface layer, irradiating channel connection zone regions with non-electron-donating light ions to form a grid of primary defects and warming to generate electron-donating secondary defects and form the n-doped zone widening. An independent claim is also included for a method of forming a memory element as above.

EEPROM-Zelle

Es wird ein Verfahren zur Herstellung eines Bauelements offenbart. Das Verfahren umfasst das Bereitstellen eines Substrats, das mit einem Zellenbereich versehen ist, der von anderen aktiven Bereichen durch Isolationsgebiete getrennt ist. Es werden ein erstes und ein zweites Gate eines ersten eines zweiten Transistors in dem Zellenbereich hergestellt. Das erste Gate enthält ein erstes und ein zweites Teil-Gate, die durch eine erste dielektrische Zwischen-Gate-Schicht voneinander getrennt. Das zweite Gate enthält ein zweites Teil-Gate, das ein erstes Teil-Gate gibt. Das erste und das zweite Teil-Gate des zweiten Gates sind durch eine zweite dielektrische Zwischen-Gate-Schicht voneinander getrennt. Es werden ein erster und zweiter Übergänge des ersten und des zweiten Transistors hergestellt. Das Verfahren umfasst ferner das Bilden eines ersten Gateanschlussest, der mit dem zweiten Teil-Gate des ersten Transistors verbunden ist, und das Bilden eines zweiten Gateanschlusses, der mit mindestens ...

Nicht-flüchtige Halbleiter-Speicherzelle mit verbesserten Programmiereigenschaften sowie zugehöriges Herstellungsverfahren

Halbleitereinrichtung und Verfahren zum Herstellen einer Halbleitereinrichtung

Ein oder mehr Ausführungsbeispiele betreffen eine Speichereinrichtung, aufweisend: ein Substrat (210), einen Gate-Stapel (300), angeordnet über dem Substrat (210), wobei der Gate-Stapel (300) aufweist eine Ladungsspeicherschicht (230') und eine Hohes-k-Dielektrikum-Schicht; und eine Abdeckschicht (3hen der Hohes-k-Dielektrikum-Schicht.

Vertical memory device and method

Floating gate transistors

NON VOLATILE MEMORY CELL WITH MATERIAL WITH HIGH K AND PROGRAMIERUNG BETWEEN GATES

PROCEDURE FOR MANUFACTURING AN ASYMMETRICAL NON VOLATILE MEMORY CELL, WHOSE FLOATING GATE WITH A SHARP EDGE IS BY SMALL ONE, IN SITU ENDOWED POLYSILIZIUM SPACER MISTAKE

SILICON UP INSULATOR READ WRITE PERMANENT MEMORY WITH A LATERAL THYRISTOR AND A TRAP LAYER

NITROGEN OXIDATION OF ETCHED MOS GATE STRUCTURE

Nonvolatile memory

Method for forming high quality oxide layers of different thickness in one processing step

Self-aligned non-volatile memory cell

Nrom cell with improved programming, erasing and cycling

METHOD OF FABRICATING A SELF-ALIGNED NON-VOLATILE MEMORY CELL

Disclosed is a self-aligned non-volatile memory cell (200) comprising a small sidewall spacer (239) electrically coupled and being located next to a main floating gate region (212). Both the small sidewall spacer and the main floating gate region are formed on a substrate (204) and both form the floating gate of the non-volatile memory cell. Both are isolated electrically from the substrate by oxide layers (208, 232, 242) which are thinner (260; 232, 242) between the small sidewall spacer and the substrate; and is thicker (263; 208) between the main floating gate region and the substrate. The small sidewall spacer can be made small; therefore, the thin oxide layer area can also be made small to create a small pathway for electrons to tunnel into the floating gate.

Electrically erasable and programmable non-volatile memory cell

The non-volatile memory cell uses field-effect emission for the reading and/or for writing. It consists of a MOS transistor with a floating gate (8), coupled capacitively to a control electrode (9). On the drain (5) side, the floating gate is situated above a well (51) and, on the source (6) side, it is placed above the substrate (1). The regions (3) and (3'), at the silicon-oxide interface below the gate (8), are textured so that the effectiveness of the field-effect mechanism is greatly enhanced. ...

METHOD FOR PRODUCING A NONVOLATILE SEMICONDUCTOR MEMORY CELL WITH A SEPARATE TUNNELING WINDOW

Forming method of flash memory

The invention discloses a forming method of a flash memory, which comprises the steps as follows: providing a substrate of a semiconductor, wherein the substrate of the semiconductor is provided with a floating gate and an interbedded insulating layer positioned on the floating gate; forming a polysilicon layer on the substrate of the semiconductor, wherein the polysilicon layer covers the floating gate; forming a grinding protection layer on the polysilicon layer; flattening the grinding protection layer and the polysilicon layer; and etching the polysilicon layer till to be exposed out of the substrate of the semiconductor, and forming a control gate on the interbedded insulating layer at the position of the floating grate. The method improves the condition that the polysilicon layer is fallen from the interbedded insulating layer.

Self-aligned non-volatile memory cell

Substrate processing method and substrate processing apparatus

Semiconductor device and manufacturing method thereof

Flash memory device and method of manufacturing the same

A memory structure and a method for manufacture that same

Twin EEPROM memory transistors with subsurface stepped floating gates

Non-volatile semiconductor memory, and production method for non-volatile semiconductor memory

Provided is a non-volatile semiconductor memory with which process charging damage is eliminated. This non-volatile semiconductor memory is characterized in that: said memory includes a silicon substrate, a first silicon oxide film, a second silicon oxide film, a first silicon nitride film, and a second silicon nitride film; the first silicon oxide film is layered upon the silicon substrate; the first silicon nitride film is layered upon the first silicon oxide film; the second silicon oxide film is layered upon the first silicon nitride film; and the second silicon nitride film is layered such that a first section thereof is in contact with the first silicon nitride film, and a second section thereof is in contact with the silicon substrate.

Semiconductor device and manufacturing method thereof

Semiconductor device and method for manufacturing the same

The floating gate of the depletion mode channel has the split gate memory cell and manufacturing method thereof

... 种存储器装置，具有：第导电类型的半导体材料衬底；在所述衬底中第二导电类型的第和第二间隔开的区域，在所述衬底中在所述第和第二间隔开的区域之间具有沟道区；在所述衬底上方且与所述衬底绝缘的导电浮置栅极，其中所述浮置栅极至少部分地布置在所述第区域和所述沟道区的第部分上方；与所述浮置栅极横向相邻且与所述浮置栅极绝缘的导电第二栅极，其中所述第二栅极至少部分地布置在所述沟道区的第二部分上方且与所述沟道区的第二部分绝缘；并且其中，所述沟道区第部分的至少部分为第二导电类型。 ...

Flash memory device and methods for fabricating the same

The invention provides a flash memory device and a method for manufacturing the same. The method of fabricating a flash memory device includes forming a stack electrode on a semiconductor substrate; forming a side spacer on a side wall of the stack electrode; forming a photo-resist film pattern with a predetermined thickness on the side wall of the side spacer; and forming a source/drain junctionon the semiconductor substrate through ion implant using the photo-resist film as a mask for ion implant. The invention improves stability and reliability of the product through preventing or releasing electron capturing phenomenon.

Non-volatile memory device manufacturing method

SEMICONDUCTOR OF NONVOLATILE MEMORY AND PROCEEDED DEVICE OF FABRICATIONCORRESPONDANT

STRUCTURE OF CELL EEPROM HAVING A THICKNESS OF DIELECTRIC OF CHANNEL NONUNIFORM AND MANUFACTORING PROCESS

CELLULE DE MEMOIRE REMANENTE A " GACHETTE " FLOTTANTE, MODIFIABLE ELECTRIQUEMENT

UNE CELLULE, CONFORME AUX TECHNIQUES USUELLES POUR MOS "SILICON GATE" A CANAL N A DOUBLE COUCHE DE SILICIUM POLYCRISTALLIN, COMPREND, SUR UNE FACE EXTREMEMENT REDUITE, UN TRANSISTOR DE MEMORISATION T ET UN TRANSISTOR DE SELECTION T. LA "GACHETTE" FLOTTANTE SURMONTE EN PARTIE LA REGION DE "DRAIN" 6; LA "GACHETTE" DE COMMANDE 14, COMMUNE AUX DEUX TRANSISTORS, N'EST GUERE ACCOUPLEE A LA "GACHETTE" FLOTTANTE 10, CE QUI FAIT QUE LA "GACHETTE" FLOTTANTE PRESENTE, PAR RAPPORT AU DRAIN, UNE CAPACITE ELECTRIQUE ELEVEE ET, PAR RAPPORT A LA "GACHETTE" DE COMMANDE, UNE FAIBLE CAPACITE. L'ECRITURE EST QUASIMENT INDEPENDANTE DE LA TENSION DE LA "GACHETTE" DE COMMANDE, TANDIS QUE L'EFFACEMENT DEPUIS LA "GACHETTE" FLOTTANTE EST TRES EFFICACE. LES RAPPORTS CAPACITIFS SONT FAVORABLES A UN FONCTIONNEMENT OPTIMAL DE LA CELLULE AVEC UNE FAIBLE DENSITE D'ELECTRONS EN JEU ET SANS CIRCUITS DE LECTURE PARTICULIEREMENT SENSIBLES.

METHOD FOR REALIZATION Of a DEVICE REPORT HAS CONDUCTING NANOPARTICULES

SELF-ALIGNING ETCHING METHOD OF A DOUBLE LAYER OF POLYCRYSTALLINE SILICON

CELL MEMORY ELECTRICALLY PROGRAMMABLE

L'invention concerne un procédé de fabrication d'une cellule mémoire électriquement programmable à grille flottante latérale par rapport à la grille de commande, comprenant les étapes consistant à former une grille de commande isolée (4) sur une zone active; former une couche mince isolante (5) autour de la grille de commande; déposer successivement une couche mince d'un matériau conducteur (21) et une couche d'un matériau isolant; graver de façon anisotrope le matériau isolant pour former des espaceurs (23, 24) de ce matériau; et éliminer les parties de la couche mince conductrice (21) non revêtues des espaceurs.

PROTECTED INTEGRATED CIRCUIT AGAINST SHORT CIRCUITS CAUSED BY THE SILICIDE.

TWIN MEMORY CELLS INDIVIDUALLY ACCESSIBLE READ

L'invention concerne une mémoire non volatile (MA2) sur substrat semi-conducteur , comprenant : une première cellule mémoire comportant un transistor à grille flottante (TRi,j) et un transistor de sélection (ST) ayant une grille de contrôle verticale enterrée (CSG), une seconde cellule mémoire (Ci,j+i) comportant un transistor à grille flottante (TRi,j+i) et un transistor de sélection (ST) ayant la même grille de contrôle (CSG) que le transistor de sélection de la première cellule mémoire, une première ligne de bit (RBLj) reliée au transistor à grille flottante (TRi,j) de la première cellule mémoire, et une seconde ligne de bit (RBLj+1) reliée au transistor à grille flottante (TRi,j+i) de la seconde cellule mémoire (Ci,j+i).

Fabrication of a flash memory from a semiconductor substrate provided with a self-aligned source line and two adjacent rows of floating gate transistors and an oxide gate

L'invention concerne un procédé de fabrication d'une mémoire flash (1) à partir d'un substrat semiconducteur (2) muni d'au moins deux rangées adjacentes (31, 32) d'empilements précurseurs de transistors à grille flottante, les empilements (31, 32) étant au moins partiellement recouverts d'une résine de protection (14) et étant séparés par une zone de formation d'une ligne de source (71), le procédé comprenant les étapes consistant à: - former une tranchée dans la zone de formation de la ligne de source (71) par une attaque de cette zone et de la résine de protection (14), ce dont il résulte un dépôt de résidus (15) de la résine au-dessous des empilements; - retirer ultérieurement le dépôt de résidu (15); - implanter ultérieurement une ligne de source (7) dans la zone de formation au-dessous des empilements. Ce procédé permet de réduire le temps d'effacement de la mémoire. L'invention porte également sur une mémoire Flash.

A method and an apparatus for detecting water on a ship's deck

FLASH MEMORY WITH ULTRA THIN VERTICAL BODY TRANSISTORS

LOW POWER FLASH MEMORY CELL AND METHOD

FLASH MEMORY WITH RECESSED FLOATING GATE

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

3차원 반도체 장치 및 그 제조 방법

... 3차원 반도체 장치 및 그 제조 방법이 제공된다. 이 장치는 수직하게 차례로 적층된 주형막들, 적층된 주형막들 사이에 배치되는 도전 패턴, 적층된 주형막들을 수직하게 관통하는 플러깅 패턴, 도전 패턴과 플러깅 패턴 사이에 배치되는 중간개재 패턴, 그리고 중간개재 패턴에 의해 수직하게 분리되면서 주형막들과 플러깅 패턴 사이에 배치되는 보호막 패턴들을 포함한다.

3차원 메모리 구조

... 3차원 메모리 구조를 제조하는 방법은, 어레이 스택을 형성하는 단계, 어레이 스택 위에 희생 재료의 층을 생성하는 단계, 희생 재료의 층 및 어레이 스택을관통하여 홀을 에칭하는 단계, 홀에 반도체 재료의 필러(pillar)를 생성하여, 필러를 공통 바디로서 사용하는 적어도 2개의 수직 스택형(stacked) 플래시 메모리 셀들을 형성하는 단계, 필러 주위의 희생 재료의 층의 적어도 일부를 제거하여, 필러의 일부를 노출시키는 단계, 및 이러한 필러의 부분을 FET(Field Effect Transistor)의 바디로서 사용하는 FET를 형성하는 단계를 포함한다.

METHOD FOR MANUFACTURING FLASH MEMORY CELL

PURPOSE: A method for manufacturing a flash memory cell is provided to enhance the efficiency of a program and an erase function by increasing a coupling ratio. CONSTITUTION: The first gate oxide layer(35) is formed on a semiconductor substrate(31). A floating gate(37) is formed on the first gate oxide layer(35). An interlayer dielectric(39), a control gate(41), and a cap oxide layer(43) are overlapped to a perpendicular direction of the floating gate(37). A sidewall insulating layer(45) is formed at the second side faces of the interlayer dielectric(39), the control gate(41), and the cap oxide layer(43). The floating gate(37) is patterned by using the remaining sidewall insulating layer(45) and the cap oxide layer(43) as a mask. A low density region(51) of the first conductive type is formed on the substrate(31) of the second side faces of the control gate(41) and the cap oxide layer(43). The second gate oxide layer(52) is formed at the first and the second sidewalls of the floating gate ...

FLASH MEMORY CELL FABRICATION SEQUENCE

SEMICONDUCTOR MEMORY DEVICE

Nonvolatile memory device comprising Si nanocrystal as floating gate and method of manufacturing the same

SELECTIVE ASPERITY DEFINITION TECHNIQUE SUITABLE FOR USE IN FABRICATING FLOATING-GATE TRANSISTOR

NON-VOLATILE MEMORY DEVICE IN WHICH LOW EXPENSE PROCESS AND HIGH EFFICIENCY PROCESS ARE POSSIVLE AND A MANUFACTURING METHOD THEREOF

PURPOSE: A non-volatile memory device and a manufacturing method thereof are provided to facilitate applying to a system on chip. CONSTITUTION: A non-volatile memory device comprises a substrate(11) equipped with a tunneling region and a channel region, a transistor(101) equipped with floating gate(18), and a unit cell consisting of a capacitor(102) connected to the floating gate. The tunneling region and the channel region are located on the substrate and comprise an impurity region having a complementary conductive type. The tunneling region comprises a first impurity region of a second conductive type and the channel region comprises a second impurity region of a first conductivity type. COPYRIGHT KIPO 2011 ...

NON-VOLATILE SEMICONDUCTOR DEVICE AND FABRICATING METHOD OF THE SAME

PURPOSE: A non-volatile semiconductor device is provided to prevent program disturbance resulting from a punch through phenomenon by forming an anti-punch through region of a halo structure. CONSTITUTION: A non-volatile semiconductor device comprises a memory cell forming section and a peripheral circuit section, wherein a flash memory cell transistor is formed in a memory cell forming section and a high voltage transistor and a low voltage transistor are formed in the peripheral region. An anti-punch through region surrounding a source region and a drain region is formed around the drain region of the memory cell transistor and the source and the drain regions of the low voltage transistor. The anti-punch through region is made of impurity, which is reverse-typed material of the source region and the drain region. COPYRIGHT 2000 KIPO ...

기판 스트레서 영역을 갖는 스플릿 게이트 메모리 셀, 및 이를 제조하는 방법

... 제1 도전형의 반도체 물질의 기판, 기판 내의 제2 도전형의 이격된 제1 영역 및 제2 영역 - 이들 사이의 기판 내에 채널 영역이 있음 -, 기판 위에 있으면서 그로부터 절연되는 도전성 플로팅 게이트 - 플로팅 게이트는 적어도 부분적으로 제1 영역 및 채널 영역의 제1 부분 위에 배치됨 -, 플로팅 게이트에 측방향으로 인접하면서 그로부터 절연되는 도전성 제2 게이트 - 제2 게이트는 적어도 부분적으로 채널 영역의 제2 부분 위에 배치되면서 그로부터 절연됨 -, 및 제2 게이트 아래의 기판 내에 형성되는 임베디드된 탄화규소의 스트레서 영역을 포함하는 메모리 디바이스 및 이를 형성하는 방법.

NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

SEMICONDUCTOR STRUCTURE OF MEMORY DEVICE, COMPOSED OF SUBSTRATE OF FIRST CONDUCTIVITY TYPE, FIRST DOPANT REGION OF SECOND CONDUCTIVITY TYPE, SECOND DOPANT REGION, GATE DIELECTRIC, FIRST GATE CONDUCTOR, AND FIELD-EFFECT TRANSISTOR, AND PROGRAMMING METHOD FOR NON-VOLATILE MEMORY DEVICE

PURPOSE: A semiconductor structure of a memory device and a programming method for a non-volatile memory device are provided to improve high voltage endurance of a drain or a source of a transistor. CONSTITUTION: A semiconductor structure includes a substrate(102) of a first conductivity type, a first dopant region of a second conductivity type included in the substrate, a second dopant region, a gate dielectric(110B) formed on the second dopant region, a first gate conductor(112B) formed on the gate dielectric, and a field-effect transistor having a second gate conductor coupled to the first gate conductor. The second dopant region of the first conductivity type is formed in the first dopant region and is more heavily doped than the first dopant region. The second dopant region, the gate dielectric, and the gate conductor form one capacitor. © KIPO 2005 ...

METHOD FOR MANUFACTURING FLASH MEMORY DEVICE

PURPOSE: A fabrication method of a flash memory device is provided to reduce effective thickness of a dielectric film having ONO structure by forming a nitride layer using nitridation and O2 annealing process. CONSTITUTION: A tunnel oxide layer(103) and the first polysilicon layer(104) are sequentially formed on a semiconductor substrate(101). A lower oxide layer(105) is formed on the resultant structure. After forming a nitrogen layer at the lower part of the lower oxide layer(105) by nitridation processing, a nitride layer(107) is then formed on the lower oxide layer(105) by annealing using O2 gas. An upper oxide layer(108) is formed on the resultant structure, thereby forming a dielectric film composed of the lower oxide layer(105), the nitride layer(107) and the upper oxide layer(108). After sequentially forming the second polysilicon layer, a tungsten silicide layer and an anti-reflective layer, a control gate is formed by patterning the anti-reflective layer, the tungsten silicide ...

SEMICONDUCTOR CHIP, STACK MODULE, AND MEMORY CARD CAPABLE OF EFFICIENTLY ARRANGING PENETRATION ELECTRODES IN A LIMITED SPACE

PURPOSE: A semiconductor chip, stack module, and memory card are provided to increase the capacity of a decoupling capacitor inserted into a semiconductor chip, thereby stabilizing the power in the semiconductor chip. CONSTITUTION: A semiconductor layer includes a first side(106) and a second side which face each other. A conductive layer(130) is arranged on the first side of the semiconductor layer. A penetration electrode(140) penetrates the semiconductor layer and the conductive layer. A sidewall insulating layer electrically insulates the semiconductor layer and the conductive layer from the penetration electrode. COPYRIGHT KIPO 2011 ...

CELL TRANSISTOR OF FLASH MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

PURPOSE: A cell transistor of a flash memory device and a method for manufacturing the same are provided to improve erasing efficiency by forming a recessed groove at a source portion of cells. CONSTITUTION: A recessed groove(108) is formed on a source portion of a substrate(100). A gate insulating layer(114) is formed on the resultant structure. A floating gate(116a), an inter-gate insulating layer(118a) and a control gate(120a) are sequentially stacked on the gate insulating layer to partially overlap the groove(108). A source region(112) is formed in the substrate to partially overlap the groove. A drain region(122) is formed on the substrate. © KIPO 2004 ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

METHOD OF MAKING A SPLIT GATE MEMORY CELL

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING A TUNNEL INSULATION LAYER

PURPOSE: A method for manufacturing a semiconductor device is provided to form a tunnel insulation layer applied to a reverse gate stack structure. CONSTITUTION: Conductive layers(211-216) and insulating layers(251-256) are alternative laminated on a substrate(200). An opening(290) passes through the conductive layers and the insulating layers. A blocking insulation layer(220) and a charge trapping layer(230) covering the blocking insulation layer are formed on the sidewall of the opening. A tunnel insulation layer(240) covering the charge trapping layer is formed. An active pillar is formed to fill the opening. COPYRIGHT KIPO 2010 ...

INSULATING FILM AND SEMICONDUCTOR APPARATUS, CAPABLE OF IMPROVING LEAK PROPERTY AND INTERFACIAL STABILITY BY FORMING AN INSULATING LAYER WITH A LAMINATE-TYPED STRUCTURE

PURPOSE: An insulating film and a semiconductor apparatus are provided to offer the insulating film having high reliability for a long time by a small amount of leak electric currents. CONSTITUTION: A semiconductor apparatus includes a semiconductor substrate, an insulating layer, a gate electrode, and source and drain regions. The insulating layer is formed on the semiconductor substrate and has an insulating film. The gate electrode is provided to the insulating layer. The source and drain regions are maintained on a surface of the semiconductor substrate. An area of a lower part of the gate electrode is formed between the source and drain regions. The semiconductor apparatus includes a first electrode, an insulating layer, and a second electrode. The insulating layer is formed on the first electrode and has the insulating film. The second electrode is formed on the insulating layer. © KIPO 2007 ...

Split-gate, non-volatile memory cell with floating,gate one-word-line-one erase gate

Floating gate memory cells in vertical memory

A method for fabricating semiconductor device

INTER-STACK PLUG IN THREE-DIMENSIONAL MEMORY ELEMENT AND METHOD OF FORMING SAME

NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF

Erasable programmable single-ploy nonvolatile memory

An erasable programmable single-poly nonvolatile memory includes a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.

Semiconductor device with semiconductor fins and floating gate

The utility model provides a semiconductor device and a programmable non-volatile memory device. According to an exemplary embodiment, the semiconductor device comprises a channel, a source pole and a drain pole which are arranged in a first semiconductor fin, wherein the channel is located between the source pole and the drain pole. The semiconductor device further comprises a control gate pole arranged in a second semiconductor fin. A floating gate pole is located between the first semiconductor fin and the second semiconductor fin. The semiconductor device also comprises a first dielectric region arranged between the floating gate pole and the first semiconductor fin and a second dielectric region arranged between the floating gate pole and the second semiconductor fin.

Semiconductor device and manufacturing method therefor

A memory gate electrode and a control gate electrode are formed to cover a fin projecting from the upper surface of a semiconductor substrate. A part of the fin which is covered by the memory gate electrode and the control gate electrode is sandwiched by a silicide layer as a part of a source region and a drain region of a memory cell. This silicide layer is formed as a silicide layer.

NAND memory with virtual channel

A string of nonvolatile memory cells are connected together by source/drain regions that include an inversion layer created by fixed charge in an overlying layer. Control gates extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma nitridation. Fixed charges may also be located between floating gates and the underlying substrate surface. Fixed charge over source/drain regions and under floating gates are formed together in a common deposition.

Semiconductor devices and methods of fabricating the same

A semiconductor device includes a semiconductor substrate having a plurality of active regions defined by a trench. A gate electrode crosses the plurality of active regions. A plurality of charge storing cells is disposed between the gate electrode and each of the plurality of active regions. A porous insulating layer is disposed between the gate electrode and the plurality of charge storing cells. The porous insulating layer includes a portion extended over the trench. An air gap is disposed between the extended portion of the porous insulating layer and a bottom surface of the trench.

Method of making embedded memory device with silicon-on-insulator substrate

A method of forming a semiconductor device with memory cells and logic devices on the same silicon-on-insulator substrate. The method includes providing a substrate that 5 includes silicon, a first insulation layer directly over the silicon, and a silicon layer directly over the first insulation layer. Silicon is epitaxially grown on the silicon layer in a first (memory) area of the substrate and not in a second (logic device) area of the substrate such that the silicon layer is thicker in the first area of the substrate relative to the second area of the substrate. Memory cells are formed in the first area of the substrate, and logic devices are 10 formed in the second area of the substrate.

Semiconductor structure and method for forming the same

A semiconductor structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a floating gate having a first sidewall and a second sidewall formed over the substrate. The semiconductor device further includes an insulating layer formed over the substrate to cover the first sidewall and an upper portion of the second sidewall of the floating gate. The semiconductor device further includes a control gate formed over the insulating layer. In addition, the floating gate is formed in a shark's fin shape.

Production method of non-volatile memory device

The invention relates to a production method of non-volatile memory device. Steps as follows: Form the gate oxide layer on the base. Form the stacked capacitor of the memory cell after logic gates polysilicon passing through at least two sedimentary processes. Then the redundant logic gates polysilicon is removed by an etching process to form the memory transistor and the periphery logic transistor. According to the method of the present invention, the stacked capacitor of the memory cell is formed by at least two sedimentary processes, and the memory device is fabricated in a standard logic process, so that the memory manufacturing process is simpler, the compatibility with the logic process is good, and the cost is low.

Integrated chip and formation method thereof

Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct-strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Storage device

A storage device includes: a plurality of electrode films stacked in a first direction, and extending in a second direction intersecting the first direction; a first semiconductor film provided adjacent to the plurality of electrode films, and extending in the first direction; a first charge holding film provided between one electrode film among the plurality of electrode films, and the semiconductor film, and including any one of a metal, a metal compound, and a high dielectric material; and a second semiconductor film located between the first semiconductor film and the charge holding film, and extending in the first direction along the first semiconductor film. The second semiconductor film is electrically insulated from the plurality of electrode films, the first charge holding film, and the first semiconductor film.

Manufacturing method of flash memory

A manufacturing method of flash memory, that includes at least a semiconductor substrate which comprises a gate oxide, a floating gate that is formed on the gate oxide and separated by an oxidation layer; the said floating gate having a wordline and a dielectric to separate the wordline from the floating gate; performing a first ion implantation on the substrate to form a source region and collector region on the wordline side; applying photoresist to cover at least the source region and collector region and the covered field oxide; and performing a second ion implantation on the substrate to form a common region.

Manufacturing method of flash memory cell

A manufacturing method of flash memory cell is disclosed, which comprises first using STI method to form the field isolation area of substrate; sequentially forming the gate, source and drain of the memory cell; then, forming a refractory metal film and an isolation layer and proceeding the silicide reaction of self-aligned silicide process to form a source line comprised by metal silicide and metal layer on the source area and the field isolation area adjacent to the source area, and at the same time, forming metal silicide on the source area; and finally removing the un-reacted refractory metal film.

Flash memory structure and method of making the same

Floating gate and method thereof

A method of forming a floating gate. A semiconductor substrate is provided. A gate dielectric layer, a conductor layer, and a patterned hard mask layer are sequentially formed on the semiconductor substrate. The patterned hard mask layer is covered on a gate predetermine area of the conductor layer. The conductor layer which is not covered by the patterned hard mask is etched to a predetermine thickness, and then, an indentation is formed on the conductor layer. The conductor layer is oxidized so as to forming an oxide layer on the conductor layer. The oxide layer and the conductor layer are etched to form a polyhedral structure using the patterned hard mask layer as a etching mask.

METHOD OF MAKING MIRROR IMAGE MEMORY CELL TRANSISTOR PAIRS FEATURING POLY FLOATING SPACES

La disposition de transistors de mémorisation non volatile à espaceurs flottants et à grilles (Fig. 1) par paires symétriques (30) permet d'augmenter la densité de puce. Pour chaque paire de transistors, les grilles flottantes (17a, 17b) sont alignées latéralement avec les espaceurs flottants (45, 47) apparaissant sur les bords latéralement extérieurs de chaque grille flottante. Au niveau des bords latéralement intérieurs, les deux transistors partagent une électrode commune (57). Les transistors sont indépendants l'un de l'autre sauf en ce qui concerne l'électrode partagée. L'oxyde tunnel (41) sépare l'espaceur flottant de la grille flottante, ces derniers étant maintenus à un potentiel commun, ce qui permet de créer des voies duelles pour la charge sortant de l'oxyde tunnel, lorsque la charge est propulsée par une tension de programmation. Les paires de transistors peuvent être alignées en colonnes perpendiculaires à la direction des paires, ce qui permet de former une matrice mémoire ...

SOURCE SIDE INJECTION STORAGE DEVICE AND METHOD THEREFOR

A storage device (10) has a two bit cell in which the select electrode (52) is nearest the channel between two storage layers (38, 40). Individual control electrodes (20, 22) are over individual storage layers (38, 40). Adjacent cells are separated by a doped region (34) that is shared between the adjacent cells. The doped region (34) is formed by an implant in which the control gates (22, 24) of adjacent cells are used as a mask. This structure provides for reduced area while retaining the ability to perform programming by source side injection.

ELECTRONIC DEVICE INCLUDING CHANNEL REGIONS LYING AT DIFFERENT ELEVATIONS AND PROCESSES OF FORMING THE SAME

An electronic device including a nonvolatile memory cell can include a substrate (10) including a first portion and a second portion, wherein a first major surface (111) within the first portion lies at an elevation lower than a second major surface (113) within the second portion. The electronic device can also include a charge storage stack (12) overlying the first portion, wherein the charge storage stack (12) includes discontinuous storage elements. The electronic device can further include a control gate electrode (24) overlying the first portion, and a select gate electrode (94) overlying the second portion, wherein the select gate electrode (94) includes a sidewall spacer. In a particular embodiment, a process can be used to form the charge storage stack (12) and control gate electrode (24). A semiconductor layer (40) can be formed after the charge storage stack (12) and control gate electrode (94) are formed to achieve the substrate with different major surfaces at different elevations ...

SINGLE-GATE NON-VOLATILE FLASH MEMORY CELL, MEMORY DEVICE, AND MANUFACTURING METHOD THEREOF

A single-gate non-volatile flash memory cell, a memory device including the memory cell, and a manufacturing method thereof are provided. The memory cell includes a semiconductor structure and a movable switch(200), wherein the semiconductor structure includes a floating-gate structure, and an interlayer dielectric layer(130) with an opening(1204) through which the floating-gate structure is exposed; the movable switch(200) includes a support component(210) and a conductive interconnection component(220),the support component(210) is located on the periphery of the conductive interconnection component(220) and connected with the interlayer dielectric layer(130), and the conductive interconnection component(220) is floating over the opening(1024). When a voltage is applied to the conductive interconnection component(220), the conductive interconnection component(220) is electrically connected with the floating-gate structure, so that the advantages of simple control circuit, low manufacturing ...

SUPPORT LINES TO PREVENT LINE COLLAPSE IN ARRAYS

Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be provided to prevent the collapse of closely spaced device structures during fabrication. In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be set in place prior to performing a high aspect ratio word line etch for forming the NAND strings. The one or more mechanical support structures may comprise one or more fin supports that are arranged in a bit line direction. In another example, the one or more mechanical support structures may be developed during the word line etch for forming the NAND strings.

ELECTRONIC DEVICE INCLUDING DISCONTINUOUS STORAGE ELEMENTS

An electronic device can include discontinuous storage elements (64) that lie within a trench (22, 23). The electronic device can include a substrate including a trench that includes a wall and a bottom and extends from a primary surface of the substrate (12). The electronic device can also include discontinuous storage elements, wherein a portion of the discontinuous storage elements lies at least within the trench. The electronic device can further include a first gate electrode, wherein at least a part of the portion of the discontinuous storage elements lies between the first gate electrode and the wall of the trench. The electronic device can still further include a second gate electrode overlying the first gate electrode and the primary surface of the substrate.

NOR STRUCTURE FLASH MEMORY AND MANUFACTURING METHOD THEREOF

The present invention relates to the technical field of flash memories, and provides a NOR structure flash memory and a manufacturing method thereof. In the manufacturing method, a mask dielectric layer is formed and covered on a second polysilicon layer of a gate laminated structure, a part of the mask dielectric layer is patterned and etched to expose a part of the second polysilicon layer on one side that is relatively closer to a source of the NOR structure flash memory, and self-alignment is performed on the exposed second polysilicon layer to form a metal silicide layer. Therefore, in the manufactured NOR structure flash memory, the mask dielectric layer that is not etched can be approximately disposed between the metal silicide layer and a drain contact hole of the NOR structure flash memory. The leakage current between the gate and the drain of the NOR structure flash memory is small, the processing procedure of the manufacturing method is not complex, the process window is large ...

DEPOSITION OF OXIDE LAYER ON THE GATE

L'invention concerne le dépôt d'une couche d'oxyde, suivant une épaisseur d'environ 100 à 300 Å, sur une grille et sur les zones actives d'un composant à semiconducteur, avant l'implantation des zones actives. On réalise le dépôt à une température comprise entre 750 et 900 °C, soit une fourchette suffisamment élevée pour éviter les dégâts causés par l'attaque du motif de la grille. De cette façon, on supprime la formation du bec d'oiseau de la grille, parce que le silicium présent dans la grille n'est pas consommé durant l'opération de dépôt.

MANUFACTURING METHOD OF NON-VOLATILE MEMORY AND NON-VOLATILE MEMORY

A method of manufacturing a non-volatile memory is described. A substrate including a first region and a second region located at periphery of the first region is provided. A plurality of stacked structures are formed on the first region of the substrate. A wall structure is formed on the second region of the substrate. A conductive layer is formed over the substrate. A bottom anti-reflective coating is formed over the conductive layer. The bottom anti-reflective coating and the conductive layer are etched back. The conductive layer is patterned.

Semiconductor device and method for manufacturing same

According to one embodiment, a method is disclosed for manufacturing a semiconductor device. A side face parallel to a channel direction of a plurality of gate electrodes provided above a semiconductor substrate is included as a part of an inner wall of an isolation groove provided between the adjacent gate electrodes. The method can include forming a first isolation groove penetrating through a conductive film serving as the gate electrode to reach the semiconductor substrate. The method can include forming a protection film covering a side wall of the first isolation groove including a side face of the gate electrode. The method can include forming a second isolation groove by etching the semiconductor substrate exposed to a bottom surface of the first isolation groove. The method can include oxidizing an inner surface of the second isolation groove provided on each of both sides of the gate electrode to form first insulating films, which are connected to each other under the gate electrode. In addition, the method can include filling an inside of the first isolation groove and an inside of the second isolation groove with a second insulating film.

Method of forming a non-volatile electron storage memory and the resulting device

The invention provides a method of forming an electron memory storage device and the resulting device. The device comprises a gate structure which, in form, comprises a first gate insulating layer formed over a semiconductor substrate, a self-forming electron trapping layer of noble metal nano-crystals formed over the first gate insulating layer, a second gate insulating layer formed over the electron trapping layer, a gate electrode formed over the second gate insulating layer, and source and drain regions formed on opposite sides of the gate structure.

Memory device having three-dimensional gate structure

Subject matter disclosed herein relates to a memory device, and more particularly to a nonvolatile memory device having a recess structure and methods of fabricating same.

System comprising a semiconductor device and structure

A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.

Non-volatile memory device and method of manufacturing the same

A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the first semiconductor layers. A plurality of charge storage layers may be interposed between the control gate electrodes and the first semiconductor layers.

Non-volatile memory and fabricating method thereof

A non-volatile memory having a tunneling dielectric layer, a floating gate, a control gate, an inter-gate dielectric layer and a first doping region and a second doping region is provided. The tunneling dielectric layer is disposed on a substrate. The floating gate is disposed on the tunneling dielectric layer, and has a protruding portion. The control gate is disposed over the floating gate to cover and surround the protruding portion. The protruding portion of the floating gate is fully covered and surrounded by the control gate in any direction, including extending directions of bit lines, word lines and an included angle formed between the word line and the bit line. The inter-gate dielectric layer is disposed between the floating gate and the control gate. The first doping region and the second doping region are respectively disposed in the substrate at two sides of the control gate.

Vertical channel type non-volatile memory device and method for fabricating the same

A method for fabricating a vertical channel type non-volatile memory device including forming a source region, alternately forming a plurality of interlayer dielectric layers and a plurality of conductive layers for a gate electrode over a substrate with the source region formed therein, forming a trench exposing the source region by etching the plurality of interlayer dielectric layers and the plurality of conductive layers for a gate electrode, and siliciding the conductive layers for a gate electrode and the source region that are exposed through the trench.

Ultrahigh density vertical nand memory device and method of making thereof

Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

Twin-Drain Spatial Wavefunction Switched Field-Effect Transistors

A field-effect transistor is provided and includes source, gate and drain regions, where the gate region controls charge carrier location in the transport channel, the transport channel includes a asymmetric coupled quantum well layer, the asymmetric quantum well layer includes at least two quantum wells separated by a barrier layer having a greater energy gap than the wells, the transport channel is connected to the source region at one end, and the drain regions at the other, the drain regions include at least two contacts electrically isolated from each other, the contacts are connected to at least one quantum well. The drain may include two regions that are configured to form the asymmetric coupled well transport channel. In an embodiment, two sources and two drains are also envisioned.

Flash cell with floating gate transistors formed using spacer technology

Methods for forming split gate flash cell structures provide for symmetrical cells that are immune to misalignment of the photoresist pattern when forming the control gates. Spacers are utilized to form the floating gates in the floating gate transistors used in the flash cells. The spacers may be oxide spacers used to mask a polysilicon layer that will form the floating gates or the spacers may be polysilicon spacers that will themselves form the floating gates. The inter-gate oxide of the floating gate transistors may be formed using HTO or may be deposited. Hard mask spacers are used in conjunction with the control gate photoresist patterning operation to control the size and configuration of the control gate and the channel length.

Logic-Based Multiple Time Programming Memory Cell

A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell comprises a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further comprises two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor.

Non-volatile memory cell

The non-volatile memory cell includes a coupling device and a first select transistor. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region. An electrode of the coupling device and a gate of the first floating gate transistor are a monolithically formed floating gate; wherein the first conductivity region and the second conductivity region are formed in a third conductivity region; wherein the first conductivity region, the second conductivity region, and the third conductivity region are wells.

Nonvolatile memory device and method for fabricating the same

A nonvolatile memory device includes a substrate having active regions that are defined by an isolation layer and that have first sidewalls extending upward from the isolation layer, floating gates adjoining the first sidewalls of the active regions with a tunnel dielectric layer interposed between the active regions and the floating gates and extending upward from the substrate, an intergate dielectric layer disposed over the floating gates, and control gates disposed over the intergate dielectric layer.

Non-volatile memory devices and methods of forming the same

A non-volatile may include a plurality of device isolation patterns disposed in a substrate to define an active region extending in a first direction, a gate pattern disposed on the substrate to extend in a second direction crossing the first direction, a charge storing pattern disposed between the active region and the gate pattern, a blocking dielectric layer disposed between the charge storing pattern and the gate pattern, and a tunnel dielectric layer disposed between the active region and the charge storing pattern. A center area of a top surface of the active region includes one of a rounded surface or a tip, and the center area of the top surface of the active region corresponds to an uppermost portion of the active region and the uppermost portion of the active region is disposed at a level lower than a lowermost portion of the gate pattern.

Structures and Methods of Improving Reliability of Non-Volatile Memory Devices

In one example, the memory device disclosed herein includes a gate insulation layer and a charge storage layer positioned above the gate insulation layer, wherein the charge storage layer has a first width. The device further includes a blocking insulation layer positioned above the charge storage layer and a gate electrode positioned above the blocking insulation layer, wherein the gate electrode has a second width that is greater than the first width. An illustrative method disclosed herein includes forming a gate stack for a memory device, wherein the gate stack includes a gate insulation layer, an initial charge storage layer, a blocking insulation layer and a gate electrode, and wherein the initial charge storage layer has a first width. The method further includes performing an etching process to selectively remove at least a portion of the initial charge storage layer so as to produce a charge storage layer having a second width that is less than the first width of the initial charge storage layer.

Field side sub-bitline nor flash array and method of fabricating the same

Field Side Sub-bitline NOR-type (FSNOR) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor Non-Volatile Memory (NVM) cells in a NOR-type flash array of the invention. Each field side sub-bitline is connected to a main metal bitline through a contact at its twisted point in the middle. Because there are no contacts in between the linked NVM cells' electrodes in the NOR-type flash array of the invention, the wordline pitch and the bitline pitch can be applied to the minimum geometrical feature of a specific technology node. The NOR-type flash array of the invention provides at least as high as those in the conventional NAND flash array in cell area density.

Semiconductor structures including bodies of semiconductor material, devices including such structures and related methods

Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. The bodies may be electrically coupled by one or more conductive structures, which may be used as an interconnect structure to electrically couple components of memory devices. By providing isolation between the bodies, the semiconductor structure provides the properties of a conventional SOI substrate (e.g., high speed, low power, increased device density and isolation) while substantially reducing fabrication acts and costs associated with such SOI substrates. Additionally, the semiconductor structures of the present disclosure provide reduced parasitic coupling and current leakage due to the isolation of the bodies by the intervening dielectric material.

Methods and apparatuses including memory cells with air gaps and other low dielectric constant materials

Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. A charge storage element, such as a floating gate or charge trap, is between the first dielectric material and the second dielectric material and adjacent to the conductive material. The charge storage element has a first surface and a second surface. The first and second surfaces are substantially separated from the first dielectric material and the second dielectric material, respectively, by a first air gap and a second air gap. Additional apparatuses and methods are disclosed.

ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF

Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. 1. A method of making a monolithic three dimensional NAND string , comprising:forming at least one sacrificial feature over a substrate;forming a stack of alternating layers of a first material and a second material over the at least one sacrificial feature, wherein the first material comprises a conductive or semiconductor control gate material;forming a cut area in the stack to separate the control gate material in a direction substantially perpendicular to a major surface of the substrate, wherein the cut area extends in a first direction substantially parallel to the major surface of the substrate and in a second direction substantially parallel to the major surface of the substrate, wherein the first direction is perpendicular to the second direction;etching the stack to form at least two openings in the stack;forming a blocking dielectric in the at least two openings;forming a charge storage region in the at least two openings over the blocking dielectric;removing the at least one sacrificial feature to form a hollow region extending substantially parallel to a major surface of the substrate which connects the at least two openings to form a hollow U-shaped pipe space comprising the first and the second openings extending substantially perpendicular to the major surface of the substrate connected by the hollow region;forming a tunnel dielectric over a side wall of the ...

HIGH DENSITY SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Provided are a high density semiconductor memory device capable of precisely reading data by suppressing the occurrence of a leakage current due to the high-integration of the semiconductor memory device, and a method for manufacturing the semiconductor memory device. The high density semiconductor memory device includes: source and drain electrodes disposed over a substrate, and forming a Schottky junction with a channel region; and a floating gate disposed over the substrate of the channel region, and configured with a plurality of nanodots. The nanodots may be formed of a silicon compound or any material that can be charged. 1. A high density semiconductor memory device , comprising:source and drain electrodes disposed over a substrate, and forming a Schottky junction with a channel region; anda floating gate disposed over the substrate of the channel region, and configured with a plurality of nanodots.28-. (canceled)9. The high density semiconductor memory device of claim 1 , wherein the source and drain electrodes comprise a material selected from the group consisting of platinum (Pt) claim 1 , lead (Pb) and iridium (Ir) when a hole is used as a majority carrier.10. (canceled)11. A method for manufacturing a high density semiconductor memory device claim 1 , the method comprising the steps of:a) forming a channel region and source and drain electrodes in a substrate, the source and drain electrodes forming a Schottky junction with the channel region;b) forming a tunneling dielectric layer over the substrate;c) forming a floating gate over the tunneling dielectric layer, the floating gate comprising a plurality of nanodots;d) forming a control gate over the floating gate; ande) etching the control gate, the floating gate and the tunneling dielectric layer to expose the source and drain electrodes.1217-. (canceled)18. The method of claim 11 , wherein the source and drain electrodes are formed of a material selected from the group consisting of platinum (Pt) claim ...

Semiconductor device and capacitor

The present invention relates to a semiconductor device including nanodots and a capacitor. A semiconductor device includes a channel layer, a tunnel insulating layer formed on the channel layer, a memory layer formed on the tunnel insulating layer and including first nanodots, a charge blocking layer formed on the memory layer, a gate electrode conductive layer formed on the charge blocking layer, and a buffer layer located, at least one of, inside the tunnel insulating layer, inside the charge blocking layer, at an interface between the tunnel insulating layer and the memory layer and at the interface between the charge blocking layer and the memory layer, wherein the buffer layer includes second nanodots.

ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF

Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. 1. A method of making a monolithic three dimensional NAND string , comprising:forming a stack of alternating layers of a first layer and a second layer, wherein the first layer comprises a conductive or semiconductor control gate material, and wherein the second layer comprises an insulating sub-layer and a first sacrificial sub-layer;etching the stack to form at least one opening in the stack;selectively etching the first layer to form first recesses;forming a blocking dielectric in the first recesses;forming a plurality of discrete charge storage segments separated from each other in the first recesses over the blocking dielectric;forming a tunnel dielectric over a side wall of the discrete charge storage segments exposed in the at least one opening;forming a semiconductor channel in the at least one opening;etching the stack to expose a back side of the stack;removing the first sacrificial sub-layer to form second recesses; andforming a plurality of conductive or semiconductor shielding wings separated from each other in the second recesses;wherein the first sacrificial sub-layer is located above or below the insulating sub-layer in each second layer.2. The method of claim 1 , wherein each of the plurality of shielding wings is located between adjacent two of the plurality of discrete charge storage segments.3. The method of claim 1 , wherein two of the plurality of ...

Non-volatile memory devices having vertical drain to gate capacitive coupling

Vertically fabricated non-volatile memory devices having capacitive coupling between a drain region and a floating gate. A two terminal programmable non-volatile device includes a floating gate disposed vertically about a substrate, wherein the floating gate comprises a first side, a second side, and a bottom portion. A source region is coupled to a first terminal and formed adjacent to the first side of the floating gate. A drain region is coupled to a second terminal and formed adjacent to the second side of the floating gate. The non-volatile device includes a channel coupling the source region and drain region for programming and erasing operations. The drain region is capacitively coupled to the floating gate.

Production method for semiconductor device

Provided is a production method for a semiconductor device comprising a metal silicide layer. According to one embodiment of the present invention, the production method for a semiconductor device comprises the steps of: forming an insulating layer on a substrate, on which a polysilicon pattern has been formed, in such a way that the polysilicon pattern is exposed; forming a silicon seed layer on the exposed polysilicon pattern that has been selectively exposed with respect to the insulating layer; forming a metal layer on the substrate on which the silicon seed layer has been formed; and forming a metal silicide layer by carrying out a heat treatment on the substrate on which the metal layer has been formed.

RFID TAG HAVING NON-VOLATILE MEMORY DEVICE HAVING FLOATING-GATE FETS WITH DIFFERENT SOURCE-GATE AND DRAIN-GATE BORDER LENGTHS

Non-volatile memory (NVM) devices are disclosed. In one aspect, a NVM device may include a substrate, and a field-effect transistor (FET). The FET may include a first doped region in the substrate and a second doped region in the substrate. The first and the second doped regions may define a channel region of the substrate between them. An insulating layer may overlie the channel region. A floating gate may overlie the insulating layer. Charge of an amount that encodes a value may be stored on the floating gate. The floating gate and the first and the second doped regions may be shaped such that the floating gate defines with the first doped region a first border of a first length, and the floating gate defines with the second doped region a second border of a second length that is less than 90% of the first length. 1. A method , comprising:biasing a field-effect transistor (FET) of a non-volatile memory (NVM) to inject electrons onto a floating gate of the FET;differentially and capacitively drawing at least 10% more charge carriers from the floating gate toward a first doped region of the FET than toward a second doped region of the FET;causing charge carriers to flow through a channel region of the FET between the first dope region and the second doped region to store a value; andstoring charge of an amount that encodes the value on the floating gate by injecting the electrons onto the floating gate of the FET while the charge carriers flow through the channel region of the biased FET.2. The method of claim 2 , wherein the electrons are injected onto the floating gate without controlling a voltage of the floating gate.3. The method of claim 2 , wherein differentially and capacitively drawing comprises drawing the charge carriers of the floating gate toward a first border between the floating gate and the first doped region that is at least 10% longer than a second border between the floating gate and the second doped region.4. The method of claim 3 , wherein ...

Logic and non-volatile memory (nvm) integration

A method includes forming a gate dielectric over a substrate in an NVM region and a logic region; forming a first conductive layer over the gate dielectric in the NVM region and the logic region; patterning the first conductive layer in the NVM region to form a select gate; forming a charge storage layer over the select gate in the NVM region and the first conductive layer in the logic region; forming a second conductive layer over the charge storage layer in the NVM region and the logic region; removing the second conductive layer and the charge storage layer from the logic region; patterning the first conductive layer in the logic region to form a first logic gate; and after forming the first logic gate, patterning the second conductive layer in the NVM region to form a control gate which overlaps a sidewall of the select gate.

Integrated Circuit Device, System, and Method of Fabrication

A semiconductor device, comprising a first semiconductor portion having a first end, a second end, and a slit portion, wherein the width of the slit portion is less than the width of at least one of the first end and the second end; a second portion that is a different material than the first semiconductor portion, a third portion that is a different material than the first semiconductor portion, wherein the second and third portions are on opposite sides of the slit portion, and at least three terminals selected from a group consisting of a first terminal connected to the first end, a second terminal connected to the second end, a third terminal connected to the second portion, and a fourth terminal connected to the third portion.

METHOD FOR PRODUCING A CONDUCTIVE NANOPARTICLE MEMORY DEVICE

A method for producing a memory device with nanoparticles, comprising the steps of: 1. A method for producing a memory device with nanoparticles , comprising at least the steps of:a) forming, in a substrate based on at least one semi-conductor, source and drain regions, and at least one first dielectric on at least one zone of the substrate arranged between the source and drain regions, said at least one zone intended to form a channel of the memory device,b) depositing of at least one ionic liquid that is an organic salt or mixture of organic salts in a liquid state, wherein nanoparticles of at least one electrically conductive material are suspended in the ionic liquid, said ionic liquid covering at least said first dielectric, andc) forming, after step b), a deposition of said nanoparticles at least on said first dielectric,d) removing, after step c), the ionic liquid remaining on the first dielectric,e) forming, after step d), at least one second dielectric and at least one control gate on at least one part of the nanoparticles deposited on the first dielectric,wherein the method further comprises applying a non-zero difference of electric potentials between the substrate and the ionic liquid during at least one part of step c) of the forming the deposition of nanoparticles, and wherein the difference of electric potentials is applied, via the substrate, between at least one of the source and drain region, and the ionic liquid.2. The method according to claim 1 , wherein the forming of the source and drain regions during step a) is obtained by steps comprising:a1) forming at least one dummy gate on the substrate, at said at least one zone intended to form the channel of the memory device, anda2) implanting dopants in the substrate using the dummy gate as an implantation mask, wherein doped zones of the substrate obtained from the implanting form the source and drain regions,wherein the dummy gate is removed before implementing step b).3. The method according to ...

Methods of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes forming first auxiliary patterns, alternately forming first material layers and second material layers on the sidewalls of the first auxiliary patterns so that a gap region between the first auxiliary patterns adjacent to each other is filled, removing the second material layers, and forming charge storage layers in respective regions from which the second material layers have been removed.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

The present application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device comprises an SOI substrate; a semiconductor fin formed on the SOI substrate, the semiconductor fin having a first side and a second side which are opposite to each other and stand upward on a surface of the SOI substrate, and a trench which is opened at a central portion of the second side and opposite to the first side; a channel region formed in the fin and being between the first side and the trench at the second side; source and drain regions formed in the fin and sandwiching the channel region; and a gate stack formed on the SOI substrate and being adjacent to the first side of the fin, wherein the gate stack comprises a first gate dielectric extending away from the first side and being adjacent to the channel region, a first conductor layer extending away from the first side and being adjacent to the first gate dielectric, a second gate dielectric extending away from the first side and being adjacent laterally to one side of the first conductor layer, and a second conductor layer extending away from the first side and being adjacent laterally to one side of the second gate dielectric. The embodiments of the invention can be applied in manufacturing an FinFET. 1. A semiconductor device , comprising an SOI substrate;a semiconductor fin formed on the semi-conductor-on-insulator “SOI” substrate, the semiconductor fin having a first side and a second side which are opposite to each other and stand upward on a surface of the SOI substrate, and a trench which is opened at a central portion of the second side and opposite to the first side;a channel region formed in the fin and being between the first side and the trench at the second side;source and drain regions formed in the fin and sandwiching the channel region; anda gate stack formed on the SOI substrate and being adjacent to the first side of the fin,wherein the gate stack comprises a first ...

Electronic Device Including a Tunnel Structure

An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region.

Non-volatile memory device, method for fabricating the same, and method for operating the same

A non-volatile memory device includes a first string and a second string that each include a first drain selection transistor, a second drain selection transistor, a plurality of memory cells, and a source selection transistor that are coupled in series in that order, respectively, a first bit line coupled with a node between the first and second drain selection transistors of the first string, and a second bit line coupled with an end node of the second string on the side of the first drain selection transistor of the second string, wherein gates of the first drain selection transistors of the first and second strings are coupled with each other, and gates of the second drain selection transistors of the first and second strings are coupled with each other.

NON-VOLATILE STORAGE SYSTEM WITH THREE LAYER FLOATING GATE

A non-volatile storage system includes memory cells with floating gates that comprises three layers separated by two dielectric layers (an upper dielectric layer and lower dielectric layer). The dielectric layers may be an oxide layers, nitride layers, combinations of oxide and nitride, or some other suitable dielectric material. The lower dielectric layer is close to the bottom of the floating gate (near interface between floating gate and tunnel dielectric), while the upper dielectric layer is close to top of the floating gate (near interface between floating gate and inter-gate dielectric). 1. A non-volatile storage device , comprising:a floating gate comprising three separate charge storage layers separated by floating gate dielectric layers;a tunnel dielectric layer on a surface of a substrate, between the substrate and the floating gate;a control gate; andan inter-gate dielectric between the floating gate and the control gate.2. The non-volatile storage device according to claim 1 , wherein:two or more of the three separate charge storage layers include a dosage of heavy atoms.3. The non-volatile storage device according to claim 1 , wherein:one or more of the three separate charge storage layers are doped with Carbon.4. The non-volatile storage device according to claim 1 , wherein:one or more of the three separate charge storage layers are doped with Nitrogen.5. The non-volatile storage device according to claim 1 , wherein:the floating gate dielectric layers comprise an upper dielectric layer and a lower dielectric layer;the upper dielectric layer is close to a top of the floating gate such that it is less than one third of the height of the floating gate down from the top of the floating gate; andthe lower dielectric layer is close to a bottom of the floating gate such that it is less than one third of the height of the floating gate up from the bottom of the floating gate.6. The non-volatile storage device according to claim 1 , wherein:the three separate ...

METHODS FOR ISOLATING PORTIONS OF A LOOP OF PITCH-MULTIPLIED MATERIAL AND RELATED STRUCTURES

Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other. 1. A process for forming an integrated circuit , comprising:providing a plurality of lines along sides of an other plurality of lines, the plurality of lines having first and second opposing ends;selectively removing the other plurality of lines;providing a first block of masking material at the first ends of the plurality of lines, the first block of masking material extending across a plurality of the first ends;providing a second block of masking material at the second ends of the plurality of lines, the second block of masking material extending across a plurality of the second ends; andtransferring a pattern formed by the plurality of lines and the first and second blocks of masking material to an underlying substrate, thereby forming lines of semiconductor material interconnected at each end of the lines by blocks of semiconductor material.2 ...

Manufacturing method of flash memory structure with stress area

In a manufacturing method of a flash memory structure with a stress area, a better stress effect can be achieved by controlling the manufacturing process of a tunneling oxide layer formed in a gate structure and contacted with a silicon substrate, so that an L-shaped spacer (or a first stress area) and a contact etch stop layer (or a second stress area) of each L-shaped spacer are formed between two gate structures and aligned towards each other to enhance the carrier mobility of the gate structure, so as to achieve the effects of improving a read current, obtaining the required read current by using a lower read voltage, reducing the possibility of having a stress-induced leakage current, and enhancing the data preservation of the flash memory.

Nonvolatile semiconductor memory device and method of manufacturing the same

According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure having memory cells, and a beam connected to an end portion of the structure. Each of the structure and the beam includes semiconductor layers stacked in a perpendicular direction. The beam includes a contact portion provided at one end of the beam, and a low resistance portion provided between the contact portion and the end portion of the structure.

METHOD FOR FABRICATING A FIELD SIDE SUB-BITLINE NOR FLASH ARRAY

Field Side Sub-bitline NOR-type (FSNOR) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor Non-Volatile Memory (NVM) cells in a NOR-type flash array of the invention. Each field side sub-bitline is connected to a main metal bitline through a contact at its twisted point in the middle. Because there are no contacts in between the linked NVM cells' electrodes in the NOR-type flash array of the invention, the wordline pitch and the bitline pitch can be applied to the minimum geometrical feature of a specific technology node. The NOR-type flash array of the invention provides at least as high as those in the conventional NAND flash array in cell area density. 1. A method for forming a conducting floating gate nonvolatile memory (NVM) device , comprising the steps of:implanting an impurity of a conductivity type opposite to that of a substrate into the substrate to form a plurality of implanted strips running in a first direction;sequentially depositing a first dielectric layer and a first poly-silicon film over the substrate surface;depositing and patterning a hard mask on the first poly-silicon film;etching through the first poly-silicon film and the first dielectric layer into the substrate to a depth to form a plurality of trenches on the substrate surface so that each implanted strip is divided into a plurality of pairs of spaced-apart sub-bitlines and selectively remains unetched in a plurality of contact landing regions on the substrate surface;depositing a second dielectric layer over the substrate surface;depositing and patterning a second ploy-silicon film on the second dielectric layer to form a plurality of control gates of a memory array of NVM cells; andforming a ...

NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION

A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer in an NVM region and a polysilicon dummy gate is formed over a second thermally-grown oxygen-containing layer in a logic region. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first and second thermally-grown oxygen-containing layers are formed. The second thermally-grown oxygen-containing layer and the dummy gate are replaced by a metal gate and a high-k dielectric. The logic transistor is protected while the NVM cell is then formed including forming a charge storage layer. 1. A method of forming an NVM cell and a logic transistor using a semiconductor substrate , comprising:in a non-volatile memory (NVM) region, forming over the semiconductor substrate a first thermally-grown oxygen-containing layer, a select gate of a first material, and a first dielectric layer, wherein the select gate is on the first thermally-grown oxygen-containing layer, a top surface of the first dielectric layer is substantially aligned with a top surface of the select gate, and the first dielectric layer has a first opening in which the select gate is present in the first opening;in a logic region, forming over the semiconductor substrate a second thermally-grown oxygen-containing layer and a dummy gate of the first material and, after forming the first thermally-grown oxygen-containing layer and the select gate, forming a source and a drain in the semiconductor substrate, and a second dielectric layer, wherein the dummy gate is on the second thermally-grown oxygen-containing layer, a top surface of the second dielectric layer is substantially aligned with a top surface of the dummy gate, and the second dielectric layer has a second opening in which the dummy gate is present in the second opening;replacing the second thermally-grown oxygen- ...

MANUFACTURING METHOD OF NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND A NONVOLATILE SEMICONDUCTOR STORAGE DEVICE

A nonvolatile semiconductor storage device has a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, multiple floating gate electrodes formed on the gate insulating film, an inter-electrode insulating film formed on the multiple floating gate electrodes, and word lines formed on the inter-electrode insulating film. The word lines have lower and upper layers containing polysilicon doped with an impurity and are formed with a separating layer between the lower layer and the upper layer. A portion of the separating layer is located between multiple floating gate electrodes, and the height of the lower layer is less than the height of the upper layer. 1. A method for manufacturing a nonvolatile semiconductor storage device , comprising the steps of:forming a gate insulating film on a semiconductor substrate;forming multiple floating gate electrodes on the gate insulating film;forming an inter-electrode insulating film on the multiple floating gate electrodes; andforming word lines containing polysilicon doped with an impurity on the inter-electrode insulating film, the word lines including a lower layer, an upper layer, and a separating layer between the lower layer and the upper layer.2. The method of claim 1 , wherein the separating layer is formed between the multiple floating gate electrodes.3. The method of claim 1 , wherein the upper layer of the word line is formed to be higher than the lower layer of the word line.4. The method according to claim 1 , wherein the separating layer is an oxygen containing layer.5. The method according to claim 4 , wherein the separating layer is formed by substituting the atmosphere during the step of forming word lines with an oxygen atmosphere.6. The method according to claim 5 , wherein the atmosphere is substituted with the oxygen atmosphere halfway through the step of forming word lines.7. The method according to claim 1 , wherein the separating layer is a nitrogen containing layer.8. The ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF

A silicon nitride film, which is a second hard mask, is dry etched to be removed completely. The silicon nitride film, which is formed on a sidewall of a silicon nitride film used as a first hard mask, has a relatively low etching rate. Therefore, if the silicon nitride film is continued etching until the corresponding portion thereof is removed, polysilicon is etched in a direction of depth in trench shape. Then, floating gates in adjacent cells are separated and a step portion of the polysilicon is formed. Consequently, a remaining portion of the silicon nitride film used as the first hard mask is removed, an ONO film is laminated on a whole surface of the poly silicon having the step portion on an edge that has been etched, and then, a polysilicon for a control gate is laminated on the ONO film. 110.-. (canceled)11. A method of fabricating a semiconductor device , comprising:{'b': '1', 'forming a first mask having a first window having a size W on a conductive film that defines a floating gate of the semiconductor;'}etching a part of the conductive film in a thickness direction thereof from the first window of the first mask;{'b': 2', '1, 'forming a second mask having a second window that has a size W ( Подробнее

Methods of forming nanoscale floating gate

A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer.

ELECTROSTATIC DISCHARGE PROTECTION

A device comprising an electrostatic discharge protection structure (), an ion sensitive field effect transistor (ISFET) having a floating gate (), and a sensing layer () located above the floating gate. The device is configured such that the electrical impedance from the sensing layer to the electrostatic discharge protection structure is less than the electrical impedance from the sensing layer to the floating gate. The device can be fabricated in a standard CMOS process. 1. A device comprising an electrostatic discharge protection structure , an ion sensitive field effect transistor (ISFET) having a floating gate , and a sensing layer located above the floating gate , the device being configured such that the electrical impedance from said sensing layer to the electrostatic discharge protection structure is less than the electrical impedance from said sensing layer to the floating gate.2. A device according to claim 1 , the device having a planar claim 1 , layered structure and the electrostatic discharge protection structure being located in a plane between the sensing layer and the floating gate.3. A device according to claim 1 , wherein the sensing layer is closer to the electrostatic protection structure than to the floating gate.4. A device according claim 1 , wherein the device is configured such that claim 1 , in use claim 1 , said sensing layer contacts a fluid sample.5. A device according to claim 1 , wherein said floating gate and electrostatic discharge protection structure are each provided by one or more planar metal structures.6. A device according to claim 1 , wherein the sensing layer is a passivation layer claim 1 , preferably comprising silicon nitride.7. A device according to claim 1 , wherein the electrostatic discharge protection structure is in the form of a substantially planar closed loop track.8. A device according to claim 7 , wherein a planar width of the closed loop track is greater than a planar width of the floating gate.9. A device ...

Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor

A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.

Method of fabricating non-volatile memory device

A method of fabricating a non-volatile memory is provided. A tunneling dielectric layer and a first patterned conductive layer are sequentially formed on a substrate. A patterned inter-gate dielectric layer and a second patterned conductive layer are stacked on a first surface of the first patterned conductive layer, and a second surface of the first patterned conductive layer is exposed. The second surface is adjacent to the first surface. The substrate is covered by a passivation layer, and a first sidewall of the first patterned conductive layer is exposed. A recess is formed on the first sidewall of the first patterned conductive layer, such that the first sidewall has a sharp corner. A portion of the passivation layer on the second surface is removed, such that the sharp corner of the first patterned conductive layer is exposed.

Split-gate device and method of fabricating the same

A semiconductor device includes a substrate; a storage element disposed over the substrate in a first region; a control gate disposed over the storage element; a high-k dielectric layer disposed on the substrate in a second region adjacent the first region; and a metal select gate disposed over the high-k dielectric layer and adjacent to the storage element and the control gate.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a gate insulating film formed on the semiconductor substrate; a floating gate formed on the gate insulating film; a control gate formed on the floating gate and has a side coplanar with a side of the floating gate; a tunnel diffusion layer facing a portion of the floating gate; and a tunnel window formed in a portion of the gate insulating film between the floating gate and the tunnel diffusion layer, the tunnel window being formed to be thinner than a remaining peripheral portion of the gate insulating film. 1. A semiconductor device having a nonvolatile memory cell selectively formed on a semiconductor substrate , comprising:a gate insulating film formed on the semiconductor substrate;a floating gate selectively formed on the gate insulating film in a region for the nonvolatile memory cell;a control gate formed on the floating gate and having a side coplanar with a side of the floating gate;a select gate selectively formed on the gate insulating film in the region for the nonvolatile memory cell and having a mono-layered structure of a conductive film flush with the floating gate;a tunnel diffusion layer facing a portion of the floating gate in the semiconductor substrate; anda tunnel window formed in a portion of the gate insulating film between the floating gate and the tunnel diffusion layer, the tunnel window configured to be thinner than a remaining peripheral portion of the gate insulating film.2. The semiconductor device of claim 1 , further comprising:a drain region formed in the opposite side of the tunnel diffusion layer to the select gate in the semiconductor substrate; anda drain low concentration layer formed to be self-aligned with the select gate to correspond to the drain region in the semiconductor substrate and widened to a region deeper than the drain region, and having an impurity concentration lower than that of the drain region.3. The semiconductor device of claim 1 , wherein the depth of the drain low ...

Fabricating method of non-volatile memory

A fabricating method of a non-volatile memory is provided. A tunneling dielectric layer and a first conductive layer are sequentially formed on a substrate. Isolation structures are formed in the first conductive layer, the tunneling dielectric layer and the substrate. The first conductive layer is patterned to form protruding portions. A portion of the isolation structures is removed, so that a top surface of each isolation structure is disposed between a top surface of the first conductive layer and a surface of the substrate. An inter-gate dielectric layer is formed on the substrate. A second conductive layer is formed on the inter-gate dielectric layer. The second conductive layer is patterned to form control gates, and the first conductive layer is patterned to form floating gates. The protruding portion of each floating gate is fully covered and surrounded by the control gate in any direction.

Analog Floating-Gate Memory Manufacturing Process Implementing N-Channel and P-Channel MOS Transistors

An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

STACKED-GATE NON-VOLATILE FLASH MEMORY CELL, MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

A stacked-gate non-volatile flash memory cell, a memory device including the memory cell, and a manufacturing method thereof are provided. The memory cell includes a semiconductor structure and a movable switch (), wherein the semiconductor structure includes an extended floating gate structure, and an interlayer dielectric layer () with an opening () through which the extended floating gate structure is exposed; meanwhile, the movable switch () includes a support component () and a conductive interconnection component (), the support component () is located on the periphery of the conductive interconnection component and connected with the interlayer dielectric layer, and the conductive interconnection component is floating over the opening. When a voltage is applied to the conductive interconnection component, the conductive interconnection component is electrically connected with the extended floating gate structure, so that the advantages of simple control circuit, low manufacturing cost, high reliability, low power consumption and high efficiency are obtained. 1. A stacked-gate non-volatile flash memory cell , comprising:a semiconductor structure, comprising a substrate, a doped well in the substrate, a stacked-gate transistor in and on the doped well, wherein the stacked-gate transistor comprises a source region, a drain region, a floating gate structure disposed between the source and the drain, an isolating layer which covers the floating gate structure and a controlling gate structure disposed on the isolating layer, the semiconductor structure further comprises an extended floating gate structure which is an extended structure of the floating gate structure on the substrate, and an interlayer dielectric layer is disposed on the semiconductor structure; anda movable switch disposed above the extended floating gate structure, wherein there is an opening corresponding to the movable switch in the ILD layer, and the opening exposes the extended floating gate ...

MEMORY DEVICE AND METHOD OF MANUFACTURE THEREOF

A memory device is provided with a floating gate electrode film formed in a memory cell region, a first inter-electrode insulating film formed on the floating gate electrode film, a control gate electrode film formed on the first inter-electrode insulating film, a lower conductive film formed in a peripheral circuit region, a second inter-electrode insulating film formed on the lower conductive film, an upper conductive film formed on the second inter-electrode insulating film, and a pair of contacts that is separated from each other, is connected to the lower conductive film from the upper side, and is not connected to the upper conductive film. Materials of the lower conductive film and the floating gate electrode film are the same. Materials of the second inter-electrode insulating film and the first inter-electrode insulating film are the same. Materials of the upper conductive film and the control gate electrode film are the same. 1. A memory device , comprising:a semiconductor substrate with a memory cell region and a peripheral circuit region thereon;a lower layer insulating film formed on the semiconductor substrate;a floating gate electrode film formed on the lower layer insulating film in the memory cell region;a first inter-electrode insulating film formed on the floating gate electrode film;a control gate electrode film formed on the first inter-electrode insulating film;a lower conductive film formed on the lower layer insulating film in the peripheral circuit region;a second inter-electrode insulating film formed on the lower conductive film;an upper conductive film formed on the second inter-electrode insulating film; anda pair of contacts separated from each other, connected to the lower conductive film from above, and not connected to the upper conductive film, whereinthe lower conductive film comprises the same material as the floating gate electrode film;the second inter-electrode insulating film comprises the same as material as the first inter- ...

HAFNIUM TANTALUM TITANIUM OXIDE FILMS

Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in a transistor. An embodiment may include forming a hafnium tantalum titanium oxide film using a monolayer or partial monolayer sequencing process such as reaction sequence atomic layer deposition. 1. A method for forming a transistor , the method comprising:forming a source region in a substrate;forming a drain region in the substrate;forming a dielectric on the substrate, with a reaction sequence atomic layer deposition process, the dielectric including a hafnium tantalum titanium oxide, a hafnium oxide, a tantalum oxide, and a titanium oxide as separate entities; andforming a gate above the dielectric.2. The transistor of claim 1 , wherein forming the dielectric includes a dielectric nitride.3. The transistor of claim 1 , wherein forming the dielectric includes forming an insulating metal oxide layer claim 1 , whose metal is different from hafnium claim 1 , tantalum and titanium.4. The transistor of claim 1 , further comprising forming an interfacial material between the substrate and the dielectric.5. The transistor of claim 4 , wherein forming the interfacial material comprises forming the interfacial layer to a thickness that is less than the dielectric.6. The transistor of claim 1 , wherein forming the dielectric comprises forming a tunnel oxide contacting a channel and a floating gate in the transistor.7. The transistor of claim 1 , wherein forming the dielectric comprises forming a floating gate dielectric contacting a floating gate and the gate in the transistor.8. A method for forming a transistor claim 1 , the method comprising:forming a source region in a substrate;forming a drain region in the substrate;forming a dielectric on the substrate with a reaction sequence atomic layer deposition process, the process including doping a hafnium tantalum titanium oxide with a metal or a compound of two or ...

Dual Conducting Floating Spacer Metal Oxide Semiconductor Field Effect Transistor (DCFS MOSFET) and Method to Fabricate the Same

Dual Conducting Floating Spacer Metal Oxide Semiconductor Field Effect Transistors (DCFS MOSFETs) and methods for fabricate them using a process that is compatible with forming conventional MOSFETs are disclosed. A DCFS MOSFET can provide multi-bit storage in a single Non-Volatile Memory (NVM) memory cell. Like a typical MOSFET, a DCFS MOSFET includes a control gate electrode on top of a gate dielectric-silicon substrate, thereby forming a main channel of the device. Two electrically isolated conductor spacers are provided on both sides of the control gate and partially overlap two source/drain diffusion areas, which are doped to an opposite type to the conductivity type of the substrate semiconductor. The DCFS MOSFET becomes conducting when a voltage that exceeds a threshold is applied at the control gate and is coupled through the corresponding conducting floating spacer to generate an electrical field strong enough to invert the carriers near the source junction. By storing charge in the two independent conducting floating spacers, DCFS MOSFET can have two independent sets of threshold voltages associated with the source junctions. 1. A method for forming a dual conductive spacer memory cell , comprising:depositing and patterning a first dielectric layer on a semiconductor substrate;forming a layer of tunnel oxide on the exposed semiconductor substrate not covered by the patterned first dielectric layer;depositing a first conductive layer over the patterned first dielectric layer;etching the first conductive layer to form a first conductive spacer and a second conductive spacer above the tunnel oxide area;removing the patterned first dielectric layer;forming a channel oxide on the semiconductor substrate in selected area exposed by the removing of the first patterned dielectric layer;depositing a second dielectric layer on the semiconductor layer and enclosing the first and second conductive spacers;depositing and patterning a second conductive layer over the ...

NON-VOLATILE STORAGE HAVING A CONNECTED SOURCE AND WELL

A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact positioned in the well, a bit line that is connected to the bit line contact, and a source line that is connected to the source line contact and the well. 1. A method for fabricating non-volatile storage , comprising:forming a plurality of NAND strings on a well, said NAND strings include bit line contacts;forming a plurality of bit lines that connect to said NAND strings and terminate at said bit line contacts; andintentionally forming a source line that connects to all of said NAND strings and said well.2. A method according to claim 1 , wherein:said forming said plurality of bit lines comprises forming conductive lines that do not connect to said well.3. A method according to claim 1 , wherein:said NAND strings include source line contacts; andsaid forming said source line comprises forming a conductive line that passes through said source line contacts and protrudes into said well.4. A method according to claim 1 , wherein:said NAND strings include source line contacts; andsaid forming said source line comprises forming a conductive line that extends into said source line contacts and extends into said well.5. A method for fabricating non-volatile storage claim 1 , comprising:forming a first dielectric layer on a well;forming a first gate layer on said first dielectric layer;forming a second dielectric layer on said first gate layer;forming a second gate layer on said second dielectric layer;creating source/drain regions, bit line contacts and source line contacts in said well;creating bit lines that connect to said bit line contacts and that do not connect to said well; andcreating a source line that connects to said source line contacts and connects to said well.6. A method according to claim 5 , wherein:said creating bit lines comprises forming conductive lines that ...

NONVOLATILE MEMORY CELLS WITH A VERTICAL SELECTION GATE OF VARIABLE DEPTH

The disclosure relates to an integrated circuit comprising at least two memory cells formed in a semiconductor substrate, and a buried gate common to the selection transistors of the memory cells. The buried gate has a first section of a first depth extending in front of vertical channel regions of the selection transistors, and at least a second section of a second depth greater than the first depth penetrating into a buried source line. The lower side of the buried gate is bordered by a doped region forming a source region of the selection transistors and reaching the buried source line at the level where the second section of the buried gate penetrates into the buried source line, whereby the source region is coupled to the buried source line. 1. An integrated circuit comprising:a buried source line buried in a semiconductor substrate; andfirst and second memory cells formed in the semiconductor substrate, each including a selection transistor, the first and second memory cells including a buried gate common to the selection transistors of the memory cells, wherein:the buried gate has a first section of a first depth extending in front of vertical channel regions of the selection transistors, and a second section of a second depth greater than the first depth and penetrating into the buried source line, andthe selection transistors having a doped source region bordering a lower side of the buried gate and reaching the buried source line at a level at which the second section of the buried gate penetrates into the buried source line, whereby the source region is coupled to the buried source line.2. An integrated circuit according to claim 1 , wherein the memory cells are formed in a well of the semiconductor substrate claim 1 , said buried source line being an isolation layer that delimits the well.3. An integrated circuit according to claim 1 , comprising:a memory that includes the first and second memory cells, a first row of memory cells, and a second row of ...

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

An aspect of the present embodiment, there is provided a semiconductor device, including a semiconductor substrate, a first insulator above the semiconductor substrate, the first insulator containing tungsten, germanium and silicon, a charge storage film on the first insulator, a second insulator on the charge storage film and, a control gate electrode on the second insulator. 1. A semiconductor device , comprising:a semiconductor substrate;a first insulator above the semiconductor substrate, the first insulator containing tungsten, germanium and silicon;a charge storage film on the first insulator;a second insulator on the charge storage film anda control gate electrode on the second insulator.2. The semiconductor device of claim 1 , whereinthe first insulator has a stacked structure in which a tungsten-contained insulator, a germanium-contained insulator and a silicon-contained insulator are laminated.3. The semiconductor device of claim 2 , whereinthe tungsten-contained insulator, the germanium-contained insulator and the silicon-contained insulator are laminated in an order in the first insulator.4. The semiconductor device of claim 2 , whereinthe silicon-contained insulator includes tungsten and germanium.5. The semiconductor device of claim 4 , whereinthe silicon-contained insulator includes tungsten and germanium diffused from the tungsten-contained insulator and the germanium-contained insulator, respectively.6. The semiconductor device of claim 1 , wherein{'sup': 13', '2', '16', '2, 'area densities of both tungsten and germanium in the first insulator are not less than 1.0×10atoms/cmand not more than 1.0×10atoms/cm.'}7. The semiconductor device of claim 6 , wherein{'sup': 14', '2', '16', '2, 'area densities of both tungsten and germanium in the first insulator are not less than 1.0×10atoms/cmand not more than 1.0×10atoms/cm.'}8. The semiconductor device of claim 2 , whereinthe silicon-contained insulator is composed of a silicon oxide film including ...

Non-volatile semiconductor memory device and method of manufacturing the same

A method of manufacturing a non-volatile semiconductor memory device, comprising the steps of, forming a plurality of element regions and an element isolation region, forming a plurality of memory cell gate electrodes and two selection gate electrodes, etching the first insulating film in such a manner that the first insulating film remains at least under the selection gate electrodes, forming a second insulating film on the selection gate electrodes and under the selection gate electrodes in the element isolation region, the second insulating film having an etching rate in a first etching solution lower than that of the first insulating film, forming a third insulating film on the memory cell gate electrodes in such a manner that air gaps are formed between the memory cell gate electrodes, and forming a contact electrode.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

According to one embodiment, a semiconductor device includes a first, a second, a third, and a fourth semiconductor region, a control electrode, a floating electrode, and an insulating film. The first region contains silicon carbide. The second region is provided on the first region and contains silicon carbide. The third region is provided on the second region and contains silicon carbide. The fourth region is provided on the third region and contains silicon carbide. The control electrode is provided in a trench formed in the fourth, the third, and the second region. The floating electrode is provided between the control electrode and a bottom surface of the trench. The insulating film is provided between the trench and the control electrode, between the trench and the floating electrode, and between the control electrode and the floating electrode. 1. A semiconductor device comprising:a first semiconductor region containing silicon carbide;a second semiconductor region provided on the first semiconductor region, the second semiconductor region containing silicon carbide of a first conductivity type;a third semiconductor region provided on the second semiconductor region, the third semiconductor region containing silicon carbide of a second conductivity type;a fourth semiconductor region provided on the third semiconductor region, the fourth semiconductor region containing silicon carbide of the first conductivity type;a control electrode provided in a trench, the trench formed in the fourth semiconductor region, the third semiconductor region, and the second semiconductor region;a floating electrode provided between the control electrode and a bottom surface of the trench; andan insulating film provided between the trench and the control electrode, between the trench and the floating electrode, and between the control electrode and the floating electrode.2. The semiconductor device according to claim 1 , wherein the insulating film includes:a gate insulating film ...

Nonvolatile semiconductor memory device and method of manufacturing the same

A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; an organic molecular layer formed on the semiconductor layer, the organic molecular layer including a plurality of organic molecules, each of the organic molecules includes a tunnel insulating unit of alkyl chain having one end bonded to the semiconductor layer, a charge storing unit, and a bonding unit configured to bond the other end of the alkyl chain to the charge storing unit; a block insulating film formed on the organic molecular layer; and a gate electrode formed on the block insulating film.

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation film formed on a semiconductor substrate, a charge storage film formed on the first insulation film, a second insulation film formed on the charge storage film, and a control electrode formed on the second insulation film. The first insulation film is formed on the semiconductor substrate, and has a lower layer film containing silicon, and an upper layer film formed on the lower layer film, the upper layer film having a concentration of transition metal atoms containing at least one of hafnium, titanium, zirconium, tantalum or lanthanum from 1e13 atoms/cmto 1e16 atoms/cmand is formed by either an oxide film, a nitride film, or an oxynitride film. 1. A nonvolatile semiconductor memory device , comprising:a semiconductor substrate;a first insulation film formed on the semiconductor substrate;a charge storage film formed on the first insulation film;a second insulation film formed on the charge storage film; anda control electrode formed on the second insulation film,wherein the first insulating film includes a lower layer film containing silicon that is formed on the semiconductor substrate, and a layer of transition metal atoms are disposed between the lower layer film and the charge storage film.2. The nonvolatile semiconductor memory device of claim 1 , wherein the transition metal atoms contain at least one of hafnium claim 1 , titanium claim 1 , zirconium claim 1 , tantalum or lanthanum.3. The nonvolatile semiconductor memory device of claim 2 , wherein a concentration of the transition metal atoms between the lower film and the charge storage film is from 1e13 atoms/cmto 1e16 atoms/cm.4. The nonvolatile semiconductor memory device of claim 2 , wherein the transition metal atoms between the lower film and the charge storage film form a layer of either an oxide film claim 2 , a nitride film claim 2 , a boride film or a sulfide film.5. The ...

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

According to one embodiment, there is provided a nonvolatile semiconductor memory device including a substrate, a laminated film which has a configuration where first insulating layers and first electrode layers are alternately laminated in a first direction vertical to the substrate, a second insulating layer formed on an inner wall of a first through hole pierced in the first insulating layers and the first electrode layers along the first direction, an intermediate layer formed on a surface of the second insulating layer, a third insulating layer formed on a surface of the intermediate layer, and a pillar-like first semiconductor region which is formed on a surface of the third insulating layer and extends along the first direction. 1. A nonvolatile semiconductor memory device comprising:a substrate;a laminated film which has a configuration where first insulating layers and first electrode layers are alternately laminated in a first direction vertical to the substrate;a second insulating layer formed on an inner wall of a first through hole pierced in the first insulating layers and the first electrode layers along the first direction;an intermediate layer formed on a surface of the second insulating layer;a third insulating layer formed on a surface of the intermediate layer; anda pillar-like first semiconductor region which is formed on a surface of the third insulating layer and extends along the first direction,wherein the intermediate layer comprises: charge storage regions which mainly contain carbon at positions where the charge storage regions are adjacent to the first electrode layer in a second direction orthogonal to the first direction; and insulating regions which electrically separate the charge storage regions adjacent to each other along the first direction at positions where the insulating regions are adjacent to the first insulating layer in the second direction.2. The device according to claim 1 , further comprising a fourth insulating layer ...

Semiconductor device and method of manufacturing the same

According to one embodiment, a semiconductor device includes a semiconductor substrate, a tunnel insulating film on the semiconductor substrate, a first floating gate electrode on the tunnel insulating film, an inter-floating gate insulating film on the first floating gate electrode, a second floating gate electrode on the inter-floating gate insulating film, an inter-electrode insulating film on the second floating gate electrode, and a control gate electrode on the inter-electrode insulating film. The inter-floating gate insulating film includes a main insulating film, and a first fixed charge layer between the main insulating film and the second floating gate electrode and having negative fixed charges.

COMPACT THREE DIMENSIONAL VERTICAL NAND AND METHOD OF MAKING THEREOF

A NAND device has at least a 3×3 array of vertical NAND strings in which the control gate electrodes are continuous in the array and do not have an air gap or a dielectric filled trench in the array. The NAND device is formed by first forming a lower select gate level having separated lower select gates, then forming plural memory device levels containing a plurality of NAND string portions, and then forming an upper select gate level over the memory device levels having separated upper select gates. 1. A NAND device , comprising: each NAND string comprises a semiconductor channel, a tunnel dielectric located adjacent to the semiconductor channel, a charge storage region located adjacent to the tunnel dielectric, and a blocking dielectric located adjacent to the charge storage region;', 'at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate; and', 'the array comprises at least a 3×3 array of NAND strings;, 'an array of vertical NAND strings, wherein 'the first control gate electrode and the second control gate electrode are continuous in the array.', 'a plurality of control gate electrodes having a mesh shape extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level, wherein2. The device of claim 1 , wherein the first control gate electrode and the second control gate electrode do not have an air gap or a dielectric filled trench in the array.3. The device of claim 1 , wherein:each semiconductor channel has a pillar shape; andthe entire pillar-shaped semiconductor channel extends substantially perpendicularly to the major surface of the substrate.4. The device of claim 1 , wherein each NAND string in the ...

Semiconductor Memory Having Both Volatile and Non-Volatile Functionality and Method of Operating

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

NONVOLATILE MEMORY COMPRISING MINI WELLS AT A FLOATING POTENTIAL

The disclosure relates to an integrated circuit comprising a nonvolatile memory on a semiconductor substrate. The integrated circuit comprises a doped isolation layer implanted in the depth of the substrate, isolated conductive trenches reaching the isolation layer and forming gates of selection transistors of memory cells, isolation trenches perpendicular to the conductive trenches and reaching the isolation layer, and conductive lines parallel to the conductive trenches, extending on the substrate and forming control gates of charge accumulation transistors of memory cells. The isolation trenches and the isolated conductive trenches delimit a plurality of mini wells in the substrate, the mini wells electrically isolated from each other, each having a floating electrical potential and comprising two memory cells. 1. A method , comprising:manufacturing, on a semiconductor substrate, an integrated circuit that includes a nonvolatile memory comprising memory cells, each including a charge accumulation transistor and a selection transistor, the manufacturing including:implanting a doped first isolation layer in the substrate;forming, in the substrate, conductive trenches reaching the isolation layer, the conductive trenches forming gates of selection transistors of memory cells;forming, in the substrate, second isolation layers respectively isolating the conductive trenches from the substrate;forming, in the substrate, isolation trenches perpendicular to the conductive trenches, and reaching the isolation layer;forming, on the substrate, conductive lines parallel to the conductive trenches, the conductive lines forming control gates of charge accumulation transistors of the memory cells; andimplanting doped regions on opposite sides of the conductive trenches and on opposite sides of the conductive lines parallel to the conductive trenches, the doped regions forming drain and source regions of the charge accumulation transistors and of the selection transistors;the ...

METHOD OF MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

A method of manufacturing a non-volatile semiconductor memory device of an embodiment includes: forming, on a semiconductor substrate, an element isolation region to be filled with a first insulating film; forming memory cell gate electrodes on element regions; etching the first insulating film so that the first insulating film remains in the element isolation region of a region in which a select gate electrode is to be formed; forming a second insulating film on the memory cell gate electrodes so that an air gap is created between the memory cell gate electrodes; forming two select gate electrodes; forming carbon side walls on the select gate electrodes; implanting ions of an impurity between the two select gate electrodes with the side walls as a mask; and removing the carbon side walls. 1. A method of manufacturing a non-volatile semiconductor memory device , comprising:forming, on a semiconductor substrate, a plurality of element regions extended in a first direction and arranged in parallel with each other, and an element isolation region mutually isolates the element regions and filled with a first insulating film;forming, on the element regions, a plurality of memory cell gate electrodes extends in a second direction orthogonal to the first direction and arranged in parallel with each other;etching the first insulating film, after forming the memory cell gate electrodes, in such a manner that the first insulating film remains in at least the element isolation region of a region where select gate electrodes are to be formed;forming a second insulating film on the memory cell gate electrodes having a gap between the memory cell gate electrodes;forming two select gate electrodes extends in the second direction and arranged side by side in parallel with each other, on the element regions of the region where the select gate electrodes are to be formed;forming carbon side walls on opposing side surfaces of the select gate electrodes;implanting impurity ions into ...

NONVOLATILE SEMICONDUCTOR MEMORY TRANSISTOR AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY

A nonvolatile semiconductor memory transistor includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the silicon substrate side, a floating gate arranged so as to surround the outer periphery of the channel region with a tunnel insulating film interposed between the floating gate and the channel region, a control gate arranged so as to surround the outer periphery of the floating gate with an inter-polysilicon insulating film interposed between the control gate and the floating gate, and a control gate line electrically connected to the control gate and extending in a predetermined direction. The inter-polysilicon insulating film is arranged so as to be interposed between the floating gate and the lower and inner side surfaces of the control gate and between the floating gate and the lower surface of the control gate line. 12-. (canceled)3. A method for manufacturing a nonvolatile semiconductor memory including a floating gate arranged so as to surround an outer periphery of an island-shaped semiconductor with a tunnel insulating film interposed between the floating gate and the island-shaped semiconductor , a control gate arranged so as to surround an outer periphery of the floating gate with an inter-polysilicon insulating film interposed between the control gate and the floating gate , and a control gate line electrically connected to the control gate and extending in a predetermined direction , the method comprising:a step of forming a plurality of island-shaped semiconductors on a source line formed at a predetermined position on a substrate;a step of forming an insulating film between the island-shaped semiconductors that are adjacent to each other and on the source line;a step of forming a floating gate film by depositing a conductive material on the insulating film;a step of forming a resist on the floating gate film, the resist having a groove extending in a direction perpendicular to ...

Method of manufacturing semiconductor device and semiconductor device

A method of manufacturing a semiconductor device comprising: forming a first insulating film on a semiconductor substrate; forming an adsorption film on the first insulating film; forming a first film containing germanium on the adsorption film; forming a second insulating film on the first film; forming a floating electrode film on the second insulating film; forming a third insulating film on the floating electrode film; and forming a gate electrode on the third insulating film.

Memory array with an air gap between memory cells and the formation thereof

A method of forming a memory array includes forming a dielectric over a semiconductor, forming a charge-storage structure over the dielectric, forming an isolation region through the dielectric and the charge-storage structure and extending into the semiconductor, recessing the isolation region to a level below a level of an upper surface of the dielectric and at or above a level of an upper surface of the semiconductor, forming an access line over the charge-storage structure and the recessed isolation region, and forming an air gap over the recessed isolation region so that the air gap passes through the charge-storage structure, so that the air gap extends to and terminates at a bottom surface of the access line, and so that the entire air gap is between the bottom surface of the access line and the upper surface of the semiconductor.

SEMICONDUCTOR DEVICE FABRICATION METHOD AND SEMICONDUCTOR DEVICE

A semiconductor device fabrication method includes forming a tunnel insulating film on a substrate containing silicon, forming a floating gate on the tunnel insulating film, forming an integral insulating film on the floating gate, and forming a control gate on the integral insulating film. The floating gate is formed on the tunnel insulating film by forming a seed layer containing amorphous silicon on the tunnel insulating film, forming an impurity later containing adsorbed boron or germanium on the seed layer, and forming a cap layer containing silicon on the impurity layer. 1. A semiconductor device fabrication method comprising:forming a tunnel insulating film on a substrate containing silicon;forming a floating gate on the tunnel insulating film;forming an integral insulating film on the floating gate; andforming a control gate on the integral insulating film,wherein said forming the floating gate includes forming a seed layer containing amorphous silicon on the tunnel insulating film, forming an impurity layer containing boron on the seed layer, and forming a cap layer containing silicon on the impurity layer.2. The method according to claim 1 , wherein said forming the floating gate further includes forming an adjustment layer containing silicon.3. The method according to claim 1 , wherein said forming the floating gate further includes forming an adjustment layer containing silicon between the seed layer and the impurity cap layer.4. The method according to claim 1 , wherein the cap layer contains amorphous silicon.5. The method according to claim 1 , wherein said forming the floating gate further includes forming a region in which chlorine is adsorbed on the seed layer claim 1 , wherein the impurity layer is formed on the region.6. The method according to claim 1 , wherein the temperature under which the seed layer is formed is in the range of 400° C. to 420° C.7. The method according to claim 6 , wherein the temperature under which the impurity layer is ...

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similally to the plurality of first memory cells. 1. A nonvolatile semiconductor memory device comprising: a first columnar body provided on a substrate, a plurality of first memory cells being connected in series in the first columnar body along a first direction perpendicular to the substrate;', 'a second columnar body provided on the substrate to be adjacent to the first columnar body in a second direction perpendicular to the first direction, a plurality of second memory cells being connected in series in the second columnar body along the first direction;', 'a conductive connection body extending along the second direction and connecting one end on the substrate side of the first columnar body and one end on the substrate side of the second columnar body at both ends;', 'a first select transistor including a first channel layer of which conduction and non-conduction are controlled by a first select gate electrode, one end of the first channel layer being connected to another end of the first columnar body on an opposite side to the one end; and', 'a second select transistor including a second channel ...

Semiconductor device and method of fabricating the same

A semiconductor device includes a substrate including an active region and a field region, first gate structures disposed on the active region, first air gaps disposed between the first gate structures, second gate structures disposed on the field region, second air gaps disposed between the second gate structures, and an interlayer insulating layer disposed on the first gate structures, the first air gaps, the second gate structures, and the second air gaps. A lowermost level of the second air gaps is lower than a lowermost level of the first gate structures.

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE

According to one embodiment, a semiconductor memory device has plural memory cells arranged on a semiconductor substrate, plural select transistors for selecting the memory cell for carrying out record or read, and an insulating film arranged between adjacent memory cells and between adjacent select transistors. The memory cell and select cell transistors include gates extending the same distance from the substrate, and an insulator between adjacent select cell transistors, between the select cell transistors and the memory transistors, and between adjacent memory transistors, the height of the insulator between the select cell transistors is higher than between the select cell transistors and the memory transistors, and between adjacent memory transistors. An insulating layer deposited thereover is deposited having an in situ flatness, without further planarization. 1. A semiconductor memory device comprising:a substratea memory cell array having a plurality of memory cell transistors disposed on the substrate, a first select gate transistor disposed adjacent to one of the memory cell transistor, and a second select gate transistor disposed adjacent to the first select gate transistor opposite side said one of the memory cell transistor; andan insulating film formed between the memory cell transistors and formed between the first select gate transistor and the second select gate transistor, and the insulating film having a first surface which is between the first select transistor and the second select transistors and a second surface which is between the memory cell transistorswherein a first distance between an upper surface of the first select transistor and the first surface is smaller than a second distance between the first surface and the second surface.2. The device of further comprising claim 1 , a bit line claim 1 , anda contact electrically connected to the first select gate transistor and the bit line,wherein the memory cell transistors are electrically ...

STRINGS OF MEMORY CELLS HAVING STRING SELECT GATES, MEMORY DEVICES INCORPORATING SUCH STRINGS, AND METHODS OF ACCESSING AND FORMING THE SAME

Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and methods for accessing and forming such strings are provided. For example, non-volatile memory devices are disclosed that utilize vertical structure NAND strings of serially-connected non-volatile memory cells. One such string including two or more serially-connected non-volatile memory cells where each end of the string shares a string select gate with the other end of the string is disclosed. 1. A memory device , comprising:a string of memory cells; anda string select gate comprising a first channel structure and a second channel structure;wherein the string select gate is configured to concurrently selectively couple a first end of the string of memory cells to a data line through the first channel structure and a second end of the string of memory cells to a source line through the second channel structure.2. The memory device of claim 1 , wherein a portion of the string of memory cells is adjacent to a first vertical column and another portion of the string of memory cells is adjacent to a second vertical column.3. The memory device of claim 2 , wherein the first vertical column comprises portions of access lines respectively coupled to the memory cells of the portion of the string of memory cells adjacent to the first vertical column claim 2 , and wherein the second vertical column comprises portions of access lines respectively coupled to the memory cells of the other portion of the string of memory cells adjacent to the second vertical column.4. The memory device of claim 1 , wherein the string of memory cells is a first string of memory cells and the string select gate is a first string select gate claim 1 , and further comprising:a second string of memory cells; anda second string select gate configured to selectively couple an end of the second string to a line ...

Incorporating impurities using a mask

Methods of incorporating impurities into materials can be useful in non-volatile memory devices as well as other integrated circuit devices. Various embodiments provide for incorporating impurities into a material using a mask.

SURROUNDING STACKED GATE MULTI-GATE FET STRUCTURE NONVOLATILE MEMORY DEVICE

A method for forming a surrounding stacked gate fin FET nonvolatile memory structure includes providing a silicon-on-insulator (SOI) substrate of a first conductivity type, patterning a fin active region on a region of the substrate, forming a tunnel oxide layer on the fin active region, and depositing a first gate electrode of a second conductivity type on the tunnel oxide layer and upper surface of the substrate. The method further includes forming a dielectric composite layer on the first gate electrode, depositing a second gate electrode on the dielectric composite layer, patterning the first and second gate electrodes to define a surrounding stacked gate area, forming a spacer layer on a sidewall of the stacked gate electrode, and forming elevated source/drain regions in the fin active region on both sides of the second gate electrode. 1. A method of forming a surrounding stacked gate fin FET nonvolatile memory structure , the method comprising:providing a silicon-on-insulator substrate of a first conductivity type;patterning a fin active region on a predetermined region of the silicon-on-insulator substrate, the fin active region projecting from a surface of the substrate;forming a tunnel oxide layer on the fin active region;depositing a first gate electrode on the tunnel oxide layer and upper surface of the substrate;forming a dielectric composite layer on the first gate electrode;depositing a second gate electrode on the dielectric composite layer;patterning the first and second gate electrodes so as to define a surrounding stacked gate area;forming a spacer layer on a sidewall of the stacked gate electrodes; andforming elevated source/drain regions in the fin active region on both sides of the second gate electrode.2. The method of claim 1 , wherein the dielectric composite layer is composed of an oxide/nitride/oxide composite layer.3. The method of claim 1 , wherein the patterned fin active region is annealed at a range of about 800° C. to 1000° C. in a ...

Memory structure

A memory structure includes a substrate, a source region, a drain region, a gate insulating layer, a floating gate and a control gate. The substrate has a surface and a well extended from the surface to the interior of the substrate. The source region and the drain region are formed in the well and a channel region is formed between the source region and the drain region. The gate insulating layer is formed on the surface of the substrate between the source region and the drain region and covers the channel region. The floating gate disposed on the gate insulating layer to store a bit data. The control gate is disposed near lateral sides of the floating gate.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Provided is a method of manufacturing a semiconductor device. The method may include etching a first conductive type semiconductor substrate to form a first trench, forming a second trench extending from the first trench, diffusing impurities into inner walls of the second trench to form a second conductive type impurity region surrounding the second trench, forming a floating dielectric layer covering inner walls of the second trench and a floating electrode filling the second trench, and forming a gate dielectric layer covering inner walls of the first trench and a gate electrode filling the first trench. 1. A method of manufacturing a semiconductor device , the method comprising:etching a first conductive type semiconductor substrate to form a first trench;forming a second trench extending from the first trench;diffusing impurities into inner walls of the second trench to form a second conductive type impurity region surrounding the second trench;forming a floating dielectric layer covering inner walls of the second trench and a floating electrode filling the second trench; andforming a gate dielectric layer covering inner walls of the first trench and a gate electrode filling the first trench.2. The method of claim 1 , wherein the forming of the second trench comprises:forming a protective layer covering the inner walls of the first trench on the semiconductor substrate;removing the protective layer covering a lower surface of the first trench to expose the lower surface of the first trench; andetching the semiconductor substrate exposed at the lower surface of the first trench.3. The method of claim 2 , further comprising removing the protective layer covering sidewalls of the first trench after forming the impurity region.4. The method of claim 1 , wherein the forming of the impurity region comprises:forming a second conductive type impurity layer covering the inner walls of the second trench; andheat treating the impurity layer to diffuse impurities included ...

Semiconductor device and method of fabricating the same

A semiconductor device includes a semiconductor substrate and at least a first gate structure disposed on the semiconductor substrate. Furthermore, a spacer only disposed at a side of the first gate structure, and a material of the spacer does not comprise nitride.

DEVICES WITH NANOCRYSTALS AND METHODS OF FORMATION

Devices can be fabricated using a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites can be created on a surface of the substrate. The creation of the nucleation sites may include implanting ions with an energy and a dose selected to provide a controllable distribution of the nucleation sites across the surface of the substrate. Nano scale structures may be grown using the controllable distribution of nucleation sites to seed the growth of the nano scale structures. According to various embodiments, the nano scale structures may include at least one of nanocrystals, nanowires, or nanotubes. According to various nanocrystal embodiments, the nanocrystals can be positioned within a gate stack and function as a floating gate for a nonvolatile device. Other embodiments are provided herein. 1. A method of forming a floating gate transistor , comprising:forming at least one pair of isolated diffused regions having a first doping type and a first doping level in a top surface of a substrate having a second doping type and a second doping level;forming a gate dielectric having a first thickness disposed above the top surface of the substrate at least between the pair of isolated diffusions;forming a plurality of isolated nucleation sites in the gate dielectric;forming a plurality of isolated nanocrystals on a top surface of the gate dielectric;forming an inter-gate dielectric having a second thickness disposed over the plurality of nanocrystals; andforming a control gate electrode disposed over the inter-gate dielectric.2. The method of claim 1 , wherein the nucleation sites in the gate dielectric are substantially all in the top quarter of the gate dielectric first thickness.3. The method of claim 2 , wherein the nucleation sites in the gate dielectric are substantially all on a top surface of the gate dielectric.4. The method of claim 1 , wherein the nucleation sites are formed by ion implantation.5. The ...

Method of manufacturing semiconductor device

A semiconductor device fabrication method particularly suitable for the fabrication of a 90 nm embedded flash memory is disclosed. The method includes: forming a dielectric layer having a first thickness over a first device region and forming a dielectric layer having a second thickness different from the first thickness over a second device region, the dielectric layer having a first thickness serving as a tunnel oxide layer of a split-gate structure, the dielectric layer having a second thickness serving as a gate oxide layer of a MOS transistor. The method enables the fabrication of a MOS transistor including a gate oxide layer with a desired thickness.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

According to an embodiment, a semiconductor device, includes a semiconductor substrate, first and second transistors. The first transistor includes a first insulating film provided on the semiconductor substrate, a first conductive film provided on the first insulating film, a second insulating film provided on the first conductive film, and a second conductive film provided on the second insulating film. The second transistor is provided to be separated from the first transistor, the second transistor including a third insulating film provided on the semiconductor substrate, a third conductive film provided on the third insulating film, a fourth insulating film provided on the third conductive film, and a fourth conductive film provided on the fourth insulating film. The third conductive film is thicker than the first conductive film, and the second transistor has a through-portion piercing the fourth insulating film to connect the third conductive film and the fourth conductive film. 1. A semiconductor device , comprising:a semiconductor substrate;a first transistor including a first insulating film provided on the semiconductor substrate, a first conductive film provided on the first insulating film, a second insulating film provided on the first conductive film, and a second conductive film provided on the second insulating film; anda second transistor provided to be separated from the first transistor in the semiconductor substrate, the second transistor including a third insulating film provided on the semiconductor substrate, a third conductive film provided on the third insulating film, a fourth insulating film provided on the third conductive film, and a fourth conductive film provided on the fourth insulating film, the third conductive film being thicker than the first conductive film, the second transistor having a through-portion in the fourth insulating film to connect the third conductive film and the fourth conductive film.2. The device according to ...

NAND Memory Device Containing Nanodots and Method of Making Thereof

A method of fabricating a memory device includes providing multiple coatings of nanodots on a tunnel dielectric layer to form a floating gate layer having a high nanodot density. The memory device may have a nanodot-containing floating gate layer with a density greater than 4×10dots/cm. Further methods include forming an oxidation barrier layer, such as a silicon nitride shell, over a surface of the nanodots, and depositing a dielectric material over the nanodots to form a floating gate layer. 1. A method of fabricating a memory device , comprising:coating a first plurality of nanodots over a tunnel dielectric layer;curing the first plurality of nanodots to attach the nanodots to the tunnel dielectric layer;coating a second plurality of nanodots on the tunnel dielectric layer;curing the second plurality of nanodots to attach the second plurality of nanodots to the tunnel dielectric layer; anddepositing a dielectric material over the first plurality of nanodots and the second plurality of nanodots to form a floating gate layer.2. The method of claim 1 , wherein curing comprises UV curing and coating the second plurality of nanodots on the tunnel dielectric layer occurs prior to deposition of any permanent dielectric layer over the first plurality of nanodots.3. The method of claim 2 , wherein the first plurality of nanodots and the second plurality of nanodots comprise metal nanodots which are coated with a ligand and the tunnel dielectric is located over a channel of a NAND device.4. The method of claim 3 , further comprising:performing an additional curing step to remove ligand hydrocarbons prior to depositing the dielectric material.5. The method of claim 1 , further comprising:coating a third plurality of nanodots on the tunnel dielectric layer; andcuring the third plurality of nanodots to attach the third plurality to the tunnel dielectric layer prior to depositing a dielectric material.6. The method of claim 1 , further comprising:forming an oxidation barrier ...

NONVOLATILE SEMICONDUCTOR MEMORY TRANSISTOR, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY

A nonvolatile semiconductor memory transistor included in a nonvolatile semiconductor memory includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the substrate side, a hollow pillar-shaped floating gate arranged so as to surround the outer periphery of the channel region in such a manner that a tunnel insulating film is interposed between the floating gate and the channel region, and a hollow pillar-shaped control gate arranged so as to surround the outer periphery of the floating gate in such a manner that an inter-polysilicon insulating film is interposed between the control gate and the floating gate. The inter-polysilicon insulating film is arranged so as to be interposed between the floating gate and the upper, lower, and inner side surfaces of the control gate. 13.-. (canceled)4. A method for manufacturing a nonvolatile semiconductor memory including a plurality of nonvolatile semiconductor memory transistors each including an island-shaped semiconductor having a hard mask formed in an upper portion thereof ,each of the island-shaped semiconductors having a source region, a channel region, and a drain region formed in the order of the source region, the channel region, and the drain region from the side of a substrate, a floating gate and a control gate being arranged in the vicinity of the channel region in the order of the floating gate and the control gate from the side of the channel region, the method comprising:a step of forming a first source line on the substrate;a step of forming the island-shaped semiconductors on the first source line;a step of forming the hard masks on the island-shaped semiconductors;a step of forming insulating film side walls on outer peripheral wall surfaces of the island-shaped semiconductors;a step of forming insulating films on bottom portions of the island-shaped semiconductors and on the first source line;a step of forming a floating gate film on the ...

Semiconductor device and method of fabricating the same

Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a charge storage structure and a gate. The charge storage structure is formed on a substrate. The gate is formed on the charge storage structure. The gate includes a lower portion formed of silicon and an upper portion formed of metal silicide. The upper portion of the gate has a width greater than that of the lower portion of the gate.

SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes: a semiconductor region; a plurality of stacked structures each of which is disposed on the semiconductor region and has a tunnel insulating film, a charge storage layer, an upper insulating layer, and a control electrode stacked sequentially; an element isolation insulating layer disposed on side faces of the plurality of stacked structures; and a source-drain region disposed on the semiconductor region and among the plurality of stacked structures. The element isolation insulating layer includes at least one of SiO, SiN, and SiON, the upper insulating layer is an oxide containing at least one metal M selected from the group consisting of a rare earth metal, Y, Zr, and Hf, and Si, and respective lengths L, L, and Lof the charge storage layer, the upper insulating layer, and the control electrode in a channel length direction satisfy the relation “L Подробнее

Semiconductor device and method for making semiconductor device

One or more embodiments relate to a memory device, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a charge storage layer and a high-k dielectric layer; and a cover layer disposed over at least the sidewall surfaces of the high-k dielectric layer. 1. A method of making a memory device , said memory device including a charge storage layer , said method comprising:providing a substrate;forming a gate stack over said substrate, said gate stack comprising said charge storage layer and a high-k dielectric layer; andforming a cover layer over at least exposed surfaces of said high-k dielectric layer.2. The method of claim 1 , wherein said cover layer is formed by a deposition process.3. The method of claim 1 , wherein said cover layer comprises a dielectric material.4. The method of claim 3 , wherein said dielectric material is an oxide.5. The method of claim 4 , wherein said oxide is silicon dioxide.6. The method of claim 1 , wherein said high-k dielectric layer is between said charge storage layer and a control gate layer.7. The method of claim 1 , further comprising claim 1 , after forming said cover layer forming source/drain extension regions in said substrate.8. The method of claim 1 , further comprising claim 1 , after forming said cover layer claim 1 , forming sidewall spacers over sidewall surfaces of said cover layer.9. The method of claim 1 , further comprising claim 1 , after forming said cover layer claim 1 , annealing said cover layer.10. The method of claim 1 , wherein said charge storage layer is a floating gate layer or a charge trapping layer.11. The method of claim 1 , further comprising the step of claim 1 , after forming said gate stack and before depositing said cover layer claim 1 , exposing said gate stack to a thermal oxidation process to grow an oxide layer over at least a portion of said gate stack.12. A method of making a memory device claim 1 , comprising:providing a substrate; a first dielectric ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes an interlayer insulating layer having openings, contact plugs formed in lower parts of the openings, wherein the contact plugs include a first conductive layer, and bit lines formed in upper parts of the openings and coupled to the contact plugs, wherein the bit lines include a second conductive layer. 1. A semiconductor device , comprising:an interlayer insulating layer having openings;contact plugs formed in lower parts of the openings, wherein the contact plugs include a first conductive layer; andbit lines formed in upper parts of the openings and coupled to the contact plugs, wherein the bit lines include a second conductive layer.2. The semiconductor device of claim 1 , wherein the first conductive layer includes a tungsten layer.3. The semiconductor device of claim 1 , wherein the second conductive layer includes a copper layer.4. The semiconductor device of claim 1 , wherein the lower parts of the openings are contact holes claim 1 , and the upper parts of the openings are bit line trenches.5. The semiconductor device of claim 1 , wherein the contact plugs and the bit lines have substantially the same widths.6. The semiconductor device of claim 1 , wherein the contact plugs are coupled to a contact region of a substrate or channel layers of drain selection transistors.7. The semiconductor device of claim 1 , further comprising:drain selection lines formed over a substrate; anda contact region formed in the substrate between the drain selection lines and coupled to the contact plugs.8. The semiconductor device of claim 1 , further comprising:a channel layer protruding from a substrate;plurality of memory cells stacked along the channel layer;at least one lower selection transistor formed under the plurality of memory cells; andat least one upper selection transistor formed above the plurality of memory cells and coupled to one of the contact plugs.9. The semiconductor device of claim 1 , further comprising:a pipe gate;a pipe ...

Memory Devices Comprising Word Line Structures, At Least One Select Gate Structure, and a Plurality Of Doped Regions

Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures. 136-. (canceled)37. A memory device , comprising:a plurality of word line structures and at least one select gate structure positioned above a semiconducting substrate, the word line structures individually comprising gate insulation over the semiconducting substrate, a floating gate over the gate insulation, inter-gate insulation over the floating gate, and a control gate over the inter-gate insulation; anda plurality of doped regions formed in said substrate adjacent said word line structures and said at least one select gate structure, wherein said doped regions between said word line structures have a shallower depth than said doped region adjacent said at least one select gate structure.38. (canceled)39. The device of claim 37 , wherein said doped regions between said word line structures comprise halogen ions.40. (canceled)41. (canceled)42. The device of claim 37 , wherein said doped regions between said word line structures have a depth that is approximately 30-60% of a depth of said doped region adjacent said at least one select gate structure.43. The memory device of comprising halogen atoms in the floating gate.44. The memory device of comprising halogen atoms in the semiconducting substrate beneath the gate insulation.45. The memory ...

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

In accordance with an embodiment, a semiconductor memory device includes a substrate and a plurality of memory cells. The substrate includes a semiconductor layer on a surface thereof. Each the memory cell includes a laminated body with a tunnel insulating film and a floating gate on the tunnel insulating film, a gate insulating film on the laminated body, and a control gate on the gate insulating film. The laminated body is sequentially laminated on the semiconductor layer in a direction vertical to the surface of the substrate for N (a natural number equal to or above 2) times. A dimension of the floating gate in the lowermost layer is at least partially smaller than a dimension of the floating gate in each of second and subsequent layers in at least one of a first direction parallel to the surface of the substrate and a second direction crossing the first direction. 1. A semiconductor memory device comprising:a substrate comprising a semiconductor layer on a surface thereof; anda plurality of memory cells,wherein each the memory cell comprises:a laminated body with a tunnel insulating film and a floating gate on the tunnel insulating film being sequentially laminated on the semiconductor layer in a direction vertical to the surface of the substrate for N (a natural number equal to or above 2) times;a gate insulating film on the laminated body; anda control gate on the gate insulating film, anda dimension of the floating gate in the lowermost layer is at least partially smaller than a dimension of the floating gate in each of second and subsequent layers in at least one of a first direction parallel to the surface of the substrate and a second direction crossing the first direction.2. The device of claim 1 ,wherein opposed surfaces of the floating gate in the lowermost layer and the floating gate in the second layer have the same size.3. The device of claim 2 ,wherein a size of a surface of the floating gate in the second layer facing the substrate is smaller than ...

SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor storage device according to the present invention includes: a semiconductor substrate; an embedded insulator embedded in a trench formed in the semiconductor substrate and having an upper portion protruding above a top surface of the semiconductor substrate; a first insulating film formed on the top surface of the semiconductor substrate; a floating gate formed on the first insulating film at a side of the embedded insulator, having a side portion arching out above the embedded insulator, and having a side surface made of a flat surface and a curved surface continuing below the flat surface; a second insulating film contacting an upper surface, the flat surface and the curved surface of the floating gate; and a control gate opposing the upper surface, the flat surface and the curved surface of the floating gate across the second insulating film. 1. A method for manufacturing a semiconductor storage device including a floating gate having a laminated structure of a first conductive layer and a second conductive layer , the method comprising:a step of forming a first insulating film on a semiconductor substrate;a step of forming a first conductive material layer, made of a material of the first conductive layer, on the first insulating film;a step of forming a hard mask having an opening on the first conductive material layer;a step of forming a trench in the semiconductor substrate and the first conductive layer by etching using the hard mask to selectively remove the first conductive material layer, the first insulating film, and the semiconductor substrate;a step of forming a deposition layer by depositing an insulating material on the trench so as to completely fill the trench, interiors of respective openings of the first insulating film and the first conductive material layer formed by the etching thereof and an interior of the opening of the hard mask;a step of removing the hard mask after the forming of the deposition layer;a step of forming a ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

A semiconductor device including a first dielectric film, a floating gate portion, second and third dielectric films, a control gate portion, and a recess on the side face of the floating gate portion. The second dielectric film for element isolation is embedded between a height position of a lower portion of the side face of the floating gate portion and a height position inside the semiconductor substrate. The third dielectric film covers an upper surface and a side face portion of the floating gate portion up to a height position of an upper surface of the second dielectric film, and on the second dielectric film. A height position of an interface between the second and third dielectric films is between a height position of a center of the recess and a position in a predetermined range below the height position of the center of the recess. 1. A semiconductor device , comprising:a first dielectric film formed above a semiconductor substrate;a floating gate portion formed above the first dielectric film, a recess cutting into an inner portion of a side face of the floating gate portion being formed on the side face of the floating gate portion;a second dielectric film for element isolation of semiconductor elements arranged on a side of the side face of the floating gate portion and embedded between a height position of a lower portion of the side face of the floating gate portion and a height position inside the semiconductor substrate;a third dielectric film formed to cover an upper surface of the floating gate portion and a side face portion of the floating gate portion up to a height position of an upper surface of the second dielectric film, of the side face of the floating gate portion continuing from the upper surface of the floating gate portion, and also on the second dielectric film; anda control gate portion formed above the third dielectric film,wherein a height position of an interface between the second dielectric film and the third dielectric film is ...

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

In accordance with an embodiment, a semiconductor memory device includes a substrate with a semiconductor layer and memory cells on the semiconductor layer. Each memory cell includes a laminated body on the semiconductor layer, a gate insulating film on the laminated body, and a control gate on the gate insulating film. The laminated body includes a tunnel insulating film and a floating gate subsequently laminated in a direction vertical to a front surface of the substrate for N (a natural number equal to or above 2) times. A dimension of a top face of any floating gate in a second or subsequent layer is smaller than a dimension of a bottom surface of the floating gate in the lowermost layer in at least one of a first direction parallel to the front surface of the substrate and a second direction crossing the first direction. 1. A semiconductor memory device comprising:a substrate comprising a semiconductor layer on a front surface thereof; anda plurality of memory cells on the semiconductor layer,wherein each memory cell comprises:a laminated body with a tunnel insulating film and a floating gate on the tunnel insulating film which are laminated in a direction vertical to the front surface of the substrate for N (a natural number equal to or above 2) times;a gate insulating film on the laminated body; anda control gate on the gate insulating film, andin at least one of a first direction parallel to the front surface of the substrate and a second direction crossing the first direction, a dimension of a top face of any floating gate in a second or subsequent layer in the floating gates is smaller than a dimension of a bottom surface of the floating gate in the lowermost layer.2. The device of claim 1 ,wherein a space between arbitrary floating gates in the second or subsequent layer in the floating gates is wider than a space between the floating gates in the lowermost layer.3. The device of claim 1 ,wherein the top face of the floating gate in the lowermost layer ...

NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

A non-volatile memory device includes a tunnel insulating layer formed on an active region defined by an isolation layer, a polysilicon pattern including a first portion formed on the tunnel insulating layer on the active region and a second portion protruding from the first portion beyond the isolation layer, wherein the second portion has a narrower width than the first portion, and a doped region formed near a surface of the polysilicon pattern and including p-type dopants. 1. A non-volatile memory device , comprising:a tunnel insulating layer formed on an active region defined by an isolation layer;a polysilicon pattern including a first portion formed on the tunnel insulating layer on the active region and a second portion protruding from the first portion beyond the isolation layer, wherein the second portion has a narrower width than the first portion; anda doped region formed near a surface of the polysilicon pattern and including p-type dopants.2. The non-volatile memory device of claim 1 , wherein the polysilicon pattern includes p-type dopants.3. The non-volatile memory device of claim 2 , wherein a concentration of the p-type dopants included in the polysilicon pattern is greater on surfaces of the first and second portions than in central portions of the first and second portions.4. A method of manufacturing a non-volatile memory device claim 2 , the method comprising:forming a first polysilicon pattern on an active region of a substrate defined by an isolation layer;forming a doped region near a surface of the first polysilicon pattern by doping the surface of the first polysilicon pattern exposed above the isolation layer with p-type dopants by using a plasma method; andforming a second polysilicon pattern by removing a natural oxide layer formed due to oxygen absorbed by the p-type dopants near a surface of the doped region.5. The method of claim 4 , wherein in the formation of the doping region by using the plasma method claim 4 , a thickness of the ...

Very dense nonvolatile memory bitcell

An asymmetric non-volatile memory bitcell is described. The bitcell comprises source and drain regions comprising carriers of the same conductivity type. A floating gate rests on top of the well, and extends over a channel region, and at least a portion of the source and drain regions. The drain region comprises additional carriers of a second conductivity type, allowing band to band tunneling. The source region comprises additional carriers of a first conductivity type, thereby increasing source-gate capacitance. Thus, the bitcell incorporates a select device, thereby decreasing the overall size of the bitcell. The bitcell may be created without any additional CMOS process steps, or through the addition of a single extra mask step.

Method Of Forming A Memory Cell By Reducing Diffusion Of Dopants Under A Gate

A method of forming a memory cell includes forming a conductive floating gate over the substrate, forming a conductive control gate over the floating gate, forming a conductive erase gate laterally to one side of the floating gate and forming a conductive select gate laterally to an opposite side of the one side of the floating gate. After the forming of the floating and select gates, the method includes implanting a dopant into a portion of a channel region underneath the select gate using an implant process that injects the dopant at an angle with respect to a surface of the substrate that is less than ninety degrees and greater than zero degrees.

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

According to one embodiment, the underlying film includes a memory region including a first trench and a peripheral region including a second trench. The stacked body includes conductive layers and insulating layers alternately stacked on the underlying film. The channel body is provided in a pair of first holes and the first trench. The first holes pierce the stacked body to be connected to the first trench. The memory film includes a charge storage film provided between a side wall of the first hole and the channel body, and between an inner wall of the first trench and the channel body. The conductor is provided in a pair of second holes and the second trench. The second holes pierce the stacked body to be connected to the second trench. 1. A semiconductor memory device comprising:an underlying film including a memory region and a peripheral region, the memory region including a first trench, the peripheral region including a second trench;a stacked body including a plurality of conductive layers and a plurality of insulating layers alternately stacked on the underlying film;a channel body provided in a pair of first holes and in the first trench, the pair of first holes piercing the stacked body on the memory region to be connected to the first trench;a memory film including a charge storage film provided between a side wall of the first hole and the channel body, and between an inner wall of the first trench and the channel body; anda conductor provided in a pair of second holes and in the second trench, the pair of second holes piercing the stacked body on the peripheral region to be connected to the second trench and having a hole diameter larger than a hole diameter of the first hole.2. The device according to claim 1 , wherein the conductor has a resistance lower than a resistance of the channel body.3. The device according to claim 1 , whereinthe channel body is a non-doped silicon film andthe conductor is a silicon doped with an impurity.4. The device ...

NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

A nonvolatile memory device includes gate structures formed over a substrate, each gate structure including a tunnel insulating layer, a floating gate, an inter-gate dielectric layer, and a control gate that are sequentially stacked, a protective layer formed on sidewalls of the floating gate, and a second insulating layer covering the gate structures and having an air gap formed between the gate structures, wherein an adhesive strength between the second insulating layer and the protective layer is smaller than an adhesive strength between the second insulating layer and the gate structure. 1. A nonvolatile memory device comprising:gate structures formed over a substrate, each gate structure comprising a tunnel insulating layer, a floating gate, an inter-gate dielectric layer, and a control gate that are sequentially stacked;a protective layer formed on sidewalls of the floating gate; anda second insulating layer covering the gate structures and having an air gap formed between the gate structures,wherein an adhesive strength between the second insulating layer and the protective layer is smaller than an adhesive strength between the second insulating layer and the gate structure.2. The nonvolatile memory device of claim 1 , wherein the protective layer blocks impurities from being transferred from or to the floating gate.3. The nonvolatile memory device of claim 1 , wherein the protective layer comprises germanium (Ge).4. The nonvolatile memory device of claim 3 , wherein the second insulating layer comprises oxide.5. The nonvolatile memory device of claim 1 , wherein the protective layer and the air gap are directly contacted with each other.6. The nonvolatile memory device of claim 1 , wherein the protective layer is further formed on a part or all of the gate structure excluding the floating gate.7. A nonvolatile memory device comprising:a gate structure formed over a substrate and comprising a tunnel insulating layer, a floating gate, an inter-gate dielectric ...

Semiconductor devices and methods of fabricating the same

A semiconductor device includes a semiconductor substrate having a plurality of active regions defined by a trench. A gate electrode crosses the plurality of active regions. A plurality of charge storing cells is disposed between the gate electrode and each of the plurality of active regions. A porous insulating layer is disposed between the gate electrode and the plurality of charge storing cells. The porous insulating layer includes a portion extended over the trench. An air gap is disposed between the extended portion of the porous insulating layer and a bottom surface of the trench.

Semiconductor device and manufacturing method of the same

According to one embodiment, a nonvolatile semiconductor storage device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge accumulation film formed on the first insulating film, a second insulating film formed on the charge accumulation film, and a control electrode formed on a second insulating film, and one of the first and the second insulating film includes a layer containing nitrogen, a layer that is formed on the layer containing nitrogen and that includes a first oxygen containing aluminum atoms and oxygen atoms, and a layer that is formed on the layer including the first oxygen and that includes a second oxygen containing silicon atoms and oxygen atoms; and a concentration of the aluminum atoms is from 1E12 atoms/cm 2 to 1E16 atoms/cm 2 .

Nonvolatile memory device

A non-volatile memory includes a channel layer to extend from a substrate in a vertical direction; a plurality of interlayer dielectric layers and a plurality of gate electrodes to be alternately stacked along the channel layer; and a memory layer to be interposed between the channel layer and each of the gate electrodes, wherein the memory layer comprises a tunnel dielectric layer to contact the channel layer, a first charge trap layer to contact the tunnel dielectric layer and formed of an insulating material, a charge storage layer to contact the first charge trap layer and formed of a semiconducting material or a conductive material, a second charge trap layer to contact the charge storage layer and formed of an insulating material, and a charge blocking layer to contact the second charge trap layer.