SEMICONDUCTOR MEMORY DEVICE

[Title of the invention]

Memory device

[Brief explanation of the drawings]

Number 1 also, also number 3, and number 11 or number 14 good embodiment of the present invention memory device cross-sectional drawing describing each thereby, the cold air flows.

Number 2 or number 13 and maul grave embodiment of the present invention good device plane view describing each thereby, the cold air flows.

Number 4a degrees to number 7b or good embodiment of the present invention memory device that describes a manufacturing process drawing as the first deoxygenator, number 4a, number 5a, and cross-sectional drawing or number 7a and number 6a, also number 4b, also number 5b, number 6b and number 7b or plane view.

Number 12a and number 12b or good embodiment of the present invention memory device manufacturing method the first deoxygenator cross-sectional drawing describing.

Number 8 and number 15 or of the present invention good memory device each coarse shown in the equivalent circuit diagram.

Number 9 and number 10 or of the present invention memory device timing chart describing operation of each e.g..

Number 16 or of the present invention memory device and having coarse using PC card also block system.

Number 17 or of the present invention memory device and having coarse perspective view to explain an examples of card IC.

'' Description of the sign for major part of the drawings

1: control gate 2: floating gate

3:4 well MOSFET: word line

5, 6: MOSFET source, impurity diffusion 7, 8: column decoder

9: row driver 10: row decoder

11-44: memory cell 15: sense amplifier

16: buffer amplifier 17, 18: column address buffer

19: row address buffer 20: address input

26: row address strobe signal

27: column address strobe signal

28: write enable signal29: input data signal (D_IN)

30:an output data signal (D_OUT) 150: memory unit

151: SRAM part 152: scanning

153:154 to EXOR times: control circuit

155: CMOS type SRAM memory cell 156: common data line

157: sense amplifier 158: output buffer

159: selection switch 160, 161, 166, 167, 168: gate

162: floating gate 163 : p type MOS transistor

164 : n type MOS transistor 165, 166: CMOS inverter

169: CMOS inverter output 170, 171, 172: word line

179: board 180 : memory device

181: battery 182, 185: semiconductor laser and a light detector

183: transparent plastic package 184: optical system

186: control circuit 1001: control gate

1002: floating gate 1003: MOSFET well

1004: thin high resistivity layer region 1005, 1006: insulating layer

1007: substrate 1008 : source or drain

1009: resist layer 1010: interlayer dielectric layer

1011: SOI substrate 1012: oxide film

1013: channel portion 1016: high resistivity layer

[Detailed description of the invention]

The present invention refers to memory device relates to, in particular semiconductor a memory using inverted write-back relates to device.

Recent information and Image and a method are, development of device medium and which stores information this liveliness. surface of the lower frame according to a processing program. DRAM which wears a medical stone having thereof (dynamic random access read write memory) and SRAM (hemodialysis conductivity read write memory) a semiconductor a memory using a device a small, lightweight and low power in has the memory capacity, precision (high-accuracy) memory and reading performing a high-speed device multifaceted, as it is hereby possible to used in.

Furthermore, recent "flash memory (flash memory)", groups, or with an nickname disadvantageous with respect to a programmable and information that can be held with memory device carried out at a interest. said DRAM. present the memory device can be enhanced in-degree integrated is that Intellectual is.

Furthermore, flash memory alternatively be written only once a PROM-OT [one time PROM (programmable read-only memory)] the Japanese station call and patent disclosure number 62-188260 Japanese station patent disclosure number 62-49651 call (call patent application number 749082 a United States application user 25 June 1985) proposed to. These application main electrode of transistor in an described [MOSFET (metal oxide semiconductor field effect transistor) in the case of source or drain, or in the case of bipolar transistor emitter] of be destroyed to Si region or a-Si through the layer or layers of the wiring metal is series connection. Si Si-a region or in a high resistance state layer resistance from flow into memory by. operation is performed.

However, DRAM a semiconductor memory having a following problem a device.

1. DRAM and SRAM semiconductor memory device is added into a user to select and purchase a desired memory capacity high rising ratio cost chip, floppy disk, magnetic tape, and cost compared to CD-ROM bit (bit cost) is. Therefore, a semiconductor memory device to facilitate practical use as a memory medium using an optional yet. same.

2. under development/study current, the level of the memory capacity for processing an Image actually as 256 Mbit level insufficient to. amount of information that.

3. DRAM or to for storing information on a SRAM, by fixing the entire steering power, power application to portable device in addition there is a need attach a harmless difficult to. Current, device a driving shaft thereof, is at the battery other than such a built-in battery is is used.

Said DRAM and provides better-degree integrated than his or her to flash memory protruded to the outside of the package [...] [...] then.

1. FN tunnel current or hot electron injection and the like any charge in the floating gate to write/erase since the used, input of charge reliability layer to each other is deteriorated the user to select and purchase a desired recovery is used.

2. FN tunnel current density J said insulating layer when the field applied is E is used for measuring.

J = αE² exp (-β/E)

In formula is α, β is a coefficient and is. Type (1) when stronger field from. expansion of the aluminum and secondary chemical. The foregoing current potential variations of floating gate reduces the exponentially according to. Therefore, about period and erase period write-per-bit level 1 to 100 µm device after the longer the length becomes 10ms convenience on use of. deteriorate is (operability).

3. said FN tunnel current said insulating layer and thickness relying surface finish, which results in an suitable between each bit or between samples used for delaying an erase period and. problem in the change of period. To this end, actually be chip manufacturing after chip classification group plurality of test process performs selection, suitable each group said memory operation to timing. The inspection process state of the parking brake gear load of the rise of cost has problem.

4. capacity in with conductivity type are formed in the of the floating gate. Thus floating gate decreases proportional capacity of fine leakage current even a varies substantially potential of the floating gate. Therefore, desired capacity for ensuring the floating gate includes a pad metal comprises the steps provide large storage are present and adjusting factor is (governing factor).

Furthermore, with only one be written state after the disk when the disk is rotating said OT-PROM is permanently in which superior in that maintain stable but, every bit each a-Si layer, and said a-Si layer and wire requiring a contact area. Semiconductor process in the formation of contact hole it is difficult than forming linear pattern. Using 0.8 µm (rule process) process rule for the intact when size of about 20% increased 1 µm² (1 µm×μm) is. Line width is limited is significantly increased as compared to contact hole receives the first signals output from the, per-bit level't surface of the process chamber is achieved. Therefore, the proposed these memory mass. it is difficult to. Furthermore, Si-said a logic gate during current applied to layer, is power consumption, portable equipment applied to. bit corresponding to the read-is difficult.

The present purpose of the invention described above the memory capacity several steps techniques, that coast , write capacity, high speed insribing and/or reading, reliability and low consuming power device memory that can realize electrode 104 is provided under the.

It is another object of the present invention each bit of cell inversion instruction is low cost is information written in the window is used as an ion injection, stable memory device is permanently electrode 104 is provided under the.

Another object of the present invention and operable at a low voltage and low power consumption and a power supply such as the battery device one of the first memory without memory having high reliability electrode 104 is provided under the device.

Another object of the present invention an easy driving method which can be driven by, the high speed write, readable, high speed, operates on a low error rate, the inputted energies less operating environment of device, the system is very convenient and the memory having excellent electrode 104 is provided under the device.

Another object of the present invention less protect layer is, which can be produced, be which is an amount that is high manufacturing rate, different type memory device, a logic circuit device and a circuit integrated on the same chip peripheral circuit including the, chip or lauric design is memory electrode 104 is provided under the device.

Another object of the present invention a device for memory device as well as audio or for example of other of video data can be used as the medium information memory, using high performance a current commercially available audio tape, video tape, CD-ROM memory that can replace high-such as electrode 104 is provided under the device.

Another object of the present invention portable device an external memory device, electronic editing, control device and electronic digital signal (still video) still video for example memory, output from copier and facsimile device of the present invention memory device having such a record card having processes information such as video data in manner, the data is required and can store extraction and or transfer user system properly the applicable is seeks to provide a memory device.

Another object of the present invention overlapped with the edge of the on the substrate, the number 1 semiconductor region, said said number 1 semiconductor region and meats from being exposed to flame conductivity type device and number 2 and number 3 semiconductor region, said number 2 said number 3 semiconductor region and a source of vacuum for removing the semiconductor region which is installed through on a region number 1 electrode, and said number 1 which is installed through on a electrode number 2 electrode including memory element may have a contact surface that memory device having a unit for, said memory device said number 1 electrode on the side surface of the semiconductor region L at the same, said number 2 electrode and said number 1 the resistance value is the same in a high resistance state between can be are changed from resistance from.

For the preferred form of device memory of the present invention when briefly described, said MOSFET apparatus is provided to compensate for a well, said drain the source and is adjacent to the well layer which separates the region which is installed through on a floating gate and said floating gate which is installed through on a control gate is composed, said insulating layer can be altered in terms of resistance value configured, said floating gate and said control gate is resistance change, i.e. converted into a resistance from antiviral 2, 4-pyrimidinedione derivatives electrically connected thereby to in a structure a writing is to carry out a..

Next the described device by said purposes. can be achieved.

Of the present invention memory device on a substrate of conductivity type semiconductor region number 1, said said number 1 semiconductor region and meats from being exposed to flame conductivity type device and number 2 and number 3 semiconductor region, said number 2 said number 3 semiconductor region and a source of vacuum for removing the semiconductor region which is installed through on a region number 1 electrode, and said number 1 which is installed through on a electrode number 2 electrode, said memory device said number 2 electrode and said number 1 is the resistance value in a high resistance state between resistance from are changed from the camera means have overlaps an area that can be, that is formed between the electrodes said number 2 electrode and said number 1 main capacity value of said number 1 consists of. to dependent thickness of electrode

Furthermore, memory device on a substrate of the present invention, conductivity type of semiconductor region number 1, said said number 1 semiconductor region and meats from being exposed to flame conductivity type device and number 2 and number 3 semiconductor region, said number 2 said number 3 semiconductor region and a source of vacuum for removing the semiconductor region which is installed through on a region number 1 electrode, the electrode said number 1, said number 2 electrode and said number 1 in a high resistance state resistance value is between electrode are changed from resistance from a region, and said region including electrode number 2 mounted thereon has a memory device.

Furthermore, said number 2 a device memory of the present invention by means of an applied voltage electrode said SRAM cell and its manufacturing can be the change in value of the.

Furthermore, memory device detachably maintains the received medical device of the present invention a plurality of memory element having, said number i one of memory elements of memory device said number 2 or number 3 number 2 or number 3 of memory device number i+1 semiconductor regions is electrically semiconductor region and is adapted for connection it is preferable that the.

Furthermore, insulating layer on a substrate of semiconductor device of the present invention Si. may be the substrate having a layer of a pressure sensitive.

Furthermore, a device memory of the present invention said memory device is disposed in a matrix configuration, each wiring are common to an array of along a direction being for connection to the electrode number 2 is mounted, said wiring in the direction intersecting the rotating shaft mounted of said memory device and which is commonly connected semiconductor regions is number 1, number 1 of each array is electrically isolated semiconductor regions is in a structure it is preferable that the.

Furthermore, said number 1 electrode and a device memory of the present invention, number 1, number 2 and number 3 layer is formed on the semiconductor region formed between the number 1 electrode and said number 2 capacity capacity is formed between the electrodes consists of ., good be set greater than

Furthermore, said number 2 electrode and said number 1 of the present invention memory device in dose is formed between the electrodes employed in photolithography out to can be reduced enough to.

Furthermore, in a memory device of the present invention including the polycrystalline Si said number 1 electrode consisting of the upper material.

Furthermore, memory device of the present invention in number 1, number 2 and number 3 semiconductor region number 1 semiconductor region and between the insulating layer including Si, O and N is formed membrane made in a made, or insulating layer Si, O and N. good is formed on.

Furthermore, as a part of a memory device of the present invention memory device of the present invention memory device that is different from. is capable of having memory elements in.

Furthermore, memory device of the present invention include peripheral in CMOS circuit can be constructed.

Furthermore, a device memory of the present invention said number 1 number 2 electrode and electrode are arranged in a matrix form in matrix intersection of said number 2 electrode and said number 1 in a high resistance state value electrode is changed state resistance from further regions can be configured to contain at least.

Furthermore, a device memory of the present invention said plurality of memory element having and, the memory element that is writing information into the desired semiconductor regions is said number 1 is connected to a source of electric power not writing information into the number 1 the memory device configured to hold a floating condition in semiconductor regions is can be.

Furthermore, a semiconductor device of the present invention said number 1 electrode and said number 2 electrode are in a high resistance state may change to state resistance from an insulating layer arranged on the side surface and the end of the number 1 is configured preferably.

Furthermore, said number 2 electrode and said number 1 of the present invention memory device are electrode in a high resistance state may change to state resistance from an insulating layer in electrode said number 1 [...] a apertures arranged on the side surface is configured preferably.

Furthermore, memory device of the present invention in which information is written in memory device when said number 1 of the first electrode from a third said number 2 number 1 voltage V₁ the information is reproduced in the when read from said memory device said number 2 number 2 of the first electrode from a third voltage V₂ is larger than.

Furthermore, a device memory of the present invention that accommodates the memory elements and other write data of the structure of a memory device written to blocks and, read from the first memory element is passed between both write data, the result is read from memory device said amount (collate) combination with each other can be constructed so as to be capable.

Furthermore, said peripheral circuit of the present invention memory device through a gate floating on at least a portion of a circuit having multiple gate electrodes may be provided.

Furthermore, the formula described as in the description of the present invention memory device it is preferable that the satisfied.

{C_FG / (C_FG +C_CG)}/ V₁V_BD

{C_FG / (C_FG +C_CG)}/ V₂V_th

V₂ ' V_th

Here, V_BD said number 2 electrode and the number 1 in a high resistance state are electrode resistance from said number 1 electrode and when changed from said number 2 connected and , V_th the number 2 and number 3 semiconductor regions is main electrode region, said number 1 semiconductor region is a control electrode region, and said number 1 is a control electrode electrode a process for which the threshold value of the insulated gate transistor, C_FG said number 1 electrode and the number 1, number 2 and number 3 and capacity formed between the semiconductor region, C_CG the number 1 electrode and which capacity is formed between the electrodes said number 2, V₁, V₂ said number 2 the writing or each on reading the. electrode.

Additionally, a device memory of the present invention said collated result of writing a further region can be configured to contain at least.

Drawing of the jam according to the present invention as further described reference to..

Number 1 and number 3 or memory device of memory element (memory cell) of the present invention shown in the degree of structure cross-section of good memory device is that describes a drawing. Number 2 and plane view of a memory cell or, at 1-1 number 1 or number 2 is a cross-sectional drawing along the paper. Number 3 or number 2 degrees is a cross-sectional drawing 3-3 along the paper. Number 1 degrees to number 3 at reference number (1001) the control gate (being electrode number 2), reference number (1002) the floating gate (being electrode number 1), reference number (1003) of well the MOSFET (semiconductor region number 1), reference number (1004) comprises a thin high resistivity layer region (a highly resistive region), reference number (1005) an insulating layer, reference number (1006) the insulating layer, reference number (1007) is a substrate. Number 3 at, reference number (1008) source or drain of the MOSFET (being semiconductor region number 2 and number 3) blades, presenting a. Control gate is floating gate is configured so as to cover the substracte embodiment is but, this configuration allows adjacent always the consequential not end of the floating gate control gate is and is installed at a side high resistivity layer (1004) can be formed exclusively on the (in this regard an. same in the embodiment each refers to).

Number 2 at, insulating layer (1006) the description been well in order to simplify a omitted (1003) is outlines are shown. Filars to distinct between broken line and to avoid complexity in the drawing was is shown that. Therefore, , a portion of which is represented by number 2 at filars is no exposed in most looking away can be viewed. Between layers and said portions relationship any potential between the number 1 and number 3 from the increased data value to the storage, come to the realization of this relationship have been produced criteria for.

Now, according to the present invention control gate and the floating gate area between the periphery of the drive resistance changed from in a high resistance state from a memory cell a satisfied by conditions in which described.

Control gate and the floating gate area between the periphery of the drive resistance changed from in a high resistance state from a memory cell from composite signals thereof V_BD a low and C_CG a small it is preferable that the condition is satisfied (here, V_BD a control gate and floating gate are in a high resistance state from resistance changed from in the event of a voltage and , C_CG the floating gate is capacitance between the and the control gate).

V_BD for lowering the, an electric field with an intensity of between control gate and the floating gate to increase the spacing between control gate and the floating gate (T) smaller as it is preferable that the. Furthermore, interval (T) smaller as it is preferable that the. Furthermore, interval (T) while an installation hole rejiggered of C_CG smaller in order to make the control gate is floating gate when closest to the size of the interval superplasticity (T) preferably.

Number 1 degrees to number 3 a device memory drive the discharge lamp said condition has a structure preferable, thin high resistivity layer (1004) the float gate (1002) in addition which is partly formed on the end side thereof and of control gate (1001) is formed main capacity C_CG to form a. This arrangement makes the motor-a material layer is a opposes to a highly resistive, is as small as possible area of a hole formed at the deeper, V_BD is it is low C_CG a small may condition is satisfied.

In the embodiment is in floating gate (1002) and a control gate (1001) capacitance between the C_CG is high resistivity layer region (1004) t1 thickness of (shown in also by number 1) and areas is mainly determined by (s1). High resistivity layer region (1004) area s1 a floating gate (1002) W width of (shown in also by number 2) and film thickness (shown in also by number 1) t0 product of between (product) is determined by. For photoresist, photoresist composition containing the W width, by lithographic techniques or limited (at least current until width of 0.3 µm), LPCVD is floating gate for example by depositing a polySi removed alternate current process than if the film thickness of the floating gate, by lithographic techniques photo the current t0 bank can not be formed and an 0.01 µm (100 Å) a widths may be formed of thickness of, also change can be control appropriately to 1% hereinafter. A floating gate provided to improve durability silicide having a high melting point such as silicides can be formed. The t1 thickness range of 10 Å to 300 Å, preferably range of 200 Å to 30 Å, further preferably in the range of 50 Å to 150 Å. and associated circuitry/logic is preferably selected. Thickness flow into resistance a region according to the voltage applied to is appropriately selected. Thickness 50 Å in the perspective that securely holding the electrical isolation should equal at and, to prevent rainwater or dust from 150 Å is connected lowering, of which requires chloride, thickness of the with good scalability do.

Described, high resistivity layer region (1004) s1 determining a uniaxial stress in the area which causes a public floating gate (1002) employed in photolithography film thickness of the t0 restricted by the is so small as (accuracy) an extent quite well not can be determined since high resistivity layer region (1004) s1 area of the in addition to an extent quite well can be determined small.. High resistivity layer region (1004) t1 film thickness of set by deposition condition of the film, and can be made, not restricted by the employed in photolithography.

Therefore, high resistivity layer region (1004) s1 and areas t1 film thickness of the dosage at which mainly determined by C_CG to an extent quite well the small. can be determined.

On the other hand, control gate (1001) and a floating gate (1002) are in a high resistance state when changed from resistance from floating gate (1002) and a control gate (1001) the pre-set standard V_BD comprises a thin high resistivity layer region (1004) film thickness of is mainly determined by t1. Therefore, high resistivity layer region (1004) by. can be lowered voltage. Of the present invention high resistivity layer region (1004) upon application of a voltage the resistor is varied according an area and, is layer areas are changed from has a low resistance layer leaves no as a layer of. not have to. Conductors in between the electrodes is point is is achieved.

Forming a device memory said method is also number 7b degrees to number 4a is described by referring to. In each drawing, also number 4b, also number 5b, negative memory cell or number 7b and number 6b plane view and also number 4a, also number 5a, also number 4b or number 7a and number 6a, also number 5b, 4A-4A ray degrees number 7b and number 6b, 5A -5A, 6A-6A and 7A-A along the cross-sectional drawing is, in this case, paper.

First, p type Si substrate (1007) for preparing a. P type Si substrate (1007) semiconductor 10¹⁴ to 10¹⁷ centimeter^-3 can include a level of impurities, be divided wells in a well, width and between the capacitor arranged on the in multiple 10¹⁶ centimeter^-3 level preferably to the substrate. Furthermore, number 4A and also as shown in number 4B, of device isolation field oxide film (1006) of the silicon LOCOS (local oxidation) or silicone modified LOCOS [field to form an Si-O be Si by etching recess silicon be used as a data carrier then peak (bird ' s peak) having narrow to pass through the inside separation width for narrowing can be] is formed by. Furthermore, n well (1003) to form substrate and then patterned about 2 to 7 times greater concentration of the resultant well (1003) is formed ion implantation is given. In this case, a withstand voltage between a potential of n well n well (withstand voltage) the depth of the dn-well harvested live to preserve the a field oxide film (1006) baseband (base) is determined as a same level level and the well are conventional well, significantly made.. Furthermore, the thermal oxide film 1100 °C to 750 °C 85 Å formed and then wet oxidation NH₃ atmosphere in 90 seconds to 950 °C -1100 °C, O₂ atmosphere, or in an N₂ O 1150 °C to 90 seconds in atmosphere heat treatment in a heat-treating order to actually SiON film thickness of about 100 Å (silicon atoms, oxygen atoms atom and nitrogen atom of the-containing film) is formed on. Furthermore, reference number (1002) for displaying a polySi number 1 layer of CVD-LP (low pressure chemical vapor deposition) is formed with 4000 Å by. Above this layer layer number 1 polySi is W, Ti, Ta or Mo metal having a high melting point such as machine body frame are placed at the same polycide or silicide is annealed (polyside) and can be modified to form a, or selected from number 1 polySi refractrory metal is instead can be may be directly used. The low resistance using magnetic material floating gate the film thickness of other than flatness enables the C_FG capacity of can be reduced. This silicide (polycide or) melting point metal for example by oxidation or prenol can be structure having the insulation layer is, in particular, it is use of Ta removed alternate current oxidation Ta₂ O₅ change, and achieving improved insulation having nearly at at break but since varies the. good.

Furthermore, an ion implantation process and an annealing is performed for to said polySi that, gate electrode is number 1 polySi been formed by patterning layer. At this time, the pattern of the polySi 4A-4A ray in drawing, 5A -5A, 6A-6A and 7A-7A of connected. with each other is formed in the hose in the shape. Then the polySi by using self-alignment is source and drain regions of PMOSFET for ion implant is formed by (to be cheap without being,). Furthermore, (scale down) micronized folded back at an intermediate stage of and for forming the source and drain found to alleviate electric field to LDD structure or GOLD and a it is preferred that a.

Furthermore, on the first aluminum layer to the number 5b and 5a as shown in the, polySi layer (1002) of the 2000 Å SiO₂ layer (1005) to form a is wet oxidation in 950 °C.

Furthermore, resist layer (1009) is patterned and this layer of as masks SiO₂ layer (1005) and polySi layer (1002) is substantially anisotropically etched effective in a sequence that is after resist is removed. Furthermore, number 6a and also as shown in number 6b, surface high resistivity layer region (1004) is a cross-section that is formed by etching said is formed with. In this case, the high resistivity layer at a temperature of 800 °C dry oxidized or it is possible, , or ozone (O₃) is added is (pure water) during pure, aqueous hydrogen peroxide (hydrogen peroxide) adding acid (H₂ SO₄, Hcl) during, or alkaline (NH₄ OH) about 10 Å to 50 Å during chemical oxide film is formed on the surface 600 °C to 500 °C such as high purity inert gas atmosphere, or in an Ar N₂ 30 minutes in atmosphere is obtained by heat treatment can be. Furthermore, number 7a and also as shown in number 7b, number 2 layer of polySi LP-CVD method again by means of an wafer is formed on control gate is a word line (1001) the process in the same manner as and doping impurities is formed by patterning. When a long word line, the metal the light, for example W-polyside etc. (provided to improve durability polycide) a metal polycide (metal silicide or between) it is preferable that the using. High resistivity layer region out of materials selected from an inorganic oxide is publicly known, and e.g. silicon material including oxygen or nitrogen, silicon, oxygen and nitrogen reactants which cooperate to including material, and Ta₂ O₅ a material selected from can be.

High resistivity layer region (1004) is control gate (1001) and a floating gate (1002) between the when that are shaped in a manner said C_CG the degree of as of a plaque has a good reproducibility can be formed. However, here SiO₂ layer (1005) is a thickness less than that of a polySi layer that can be viewed.

And thereafter adsorbing conventional LSI process in the same manner as such BPSG interlayer dielectric layer (1010), contact (to be cheap without being,), metal wiring (without being, to be cheap), passivation film (passivation film) pad part is formed (not shown) a patterned is process is ended. Said used to form structure of a pixel electrode as a conductive DRAM water, SRAM, and flash E² PROM including a memory and manufacturing conventional semi and those that are necessary to is hereinafter. Each memory device thus formed per-bit level inversion instruction is, a simple process and high yield may be formed m number of third cost.

The fragments described of manufacturing method of the structure (single-side) relates well structure therefor it is not, unrestricted p wall and type n even well structure double-type well, even layer formation channel stop in separating portion, even in the event of a well as trench isolation is enabling to use.

Number 8 or operation is performed according of the present invention basic device shown an example of equivalent circuit block of wet liquid to flow down. Number 8 at reference number (11, 12, 13, 14, 21, 22, 23, 24, 31, 32, 33, 34, 41, 42, 43, 44) indicating that the portable computing device is each of the memory cell, the description for convenience the 4 × 4 cell structures described.

Memory cells in, reference number (1) the control gate (being electrode number 2), reference number (2) the floating gate (being electrode number 1), reference number (3) the MOSFET of well layers (becoming, semiconductor region number 1), reference number (4) each control gate is a word line, reference number (5, 6) and for forming the source and MOSFET each impurity diffusion (being semiconductor region number 2 and number 3) part 12 displays. Cell in each column a source and a drain is connected to each other in series. Reference number (7) heat a read column decoder selecting a, reference number (8) a write bit line column decoder selecting a, reference number (9) driving a word line in a row driver, reference number (10) a word line a row decoder, reference number (15) has a sense amplifier, reference number (16) is the buffer amplifier. Furthermore, reference number (17, 18) a reference number (20) address input from column decoder (7, 8) column address buffer is transmitted to. SW1 to SW13 the MOSFET switch and, switch SW9, SW10, SW11, SW12, SW13 the pulse1,2,3,4,5 is controlled by. Reference number (26) rows address strobeA, reference number (27) the column address photoengravingReference number (28) a write enableReference number (29) the input data (D_IN) signal, reference number (30) the output data (D_OUT). represent the signal.

Device memory process is performed is described of action with the content is to. Two types of device is the same input address signal is inputted in time division by. After assurance column address, oscillates between high and low levels and(27) by inputting. is taken to column address chip. Furthermore, after row address is fixed, high from the level memory(26) by inputting chip addressed within. is taken to. This configuration allows adjacent of address can be from the first delayer. Chip reading state or write state the lake reference number (28) represented bySignal is a first level or low level of and decides the whether.

In the case of read, valid output dataReference number after predetermined time from (30) a represented by D_OUT. may be obtained from a terminal. In the case of write, data code drawing (29) a represented by D_IN noise signal transmitted to the input terminal written in order of lines.

Number 9 an example of write operation timing coarse drive the discharge lamp degree. as further described reference to. 3.3V power supply voltage of the chip wherein power consumption is set to. reduce. Furthermore, on the first aluminum layer to the number 9 CG1, CG2, CG3, number 8 in the CG4 number 1, number 2, number 3 and number 4 exhibits stably a. BL1, BL2, BL3, BL4 of a nMOSFET SW5 to SW8 is the pulse the respective. Number 9 or a memory device cell (21) comprises the steps of pulses of a potential from is formed inside the tie. shown e.g.. The tunnel, reference number (8) column decoder represented by (1) pulses from BL1, BL2, BL3, BL4 each high level, low level, low level, low level state switches SW5 has on and the other switch SE6, SW7, SW8 is off. This written by the cell having GND signals and then the well of heat number 1, number 4 to number 2 a other the well potentials of heat is a floating state.

Furthermore, SW9, SW10, SW11, SW12, consists also SW13 n type MOSFET, pulse1,2,3,4,5 drive the discharge lamp the number 9 that present respective low level, high level, high level, method is selected to be high-level and low-level. Additionally, a MOSFET type p SW1 to SW4 consists reference number (7) represented by column decoder (2) is set to the low level all the pulses from the source and drain electrodes each cell is made the GND.

Next, reference number (9) cell write driver row represented by (21) connected to he pulse having a pulse width less than of the amplitude of 10V only word line. In this case supply voltage is 3.3V or, because of the absence of the current flowing, booster circuit by chip can be generate, among other things, easy high voltage. Cell application pulse pressure is (21) control gate (1) and the floating gate (2) the channel opens bias of between about 6.6V control gate (1) and the floating gate (2) in a high resistance state from between a region of resistance state, undergoes a change due to the ns few to ten complete a written. The same word connected to a cell (22, 23, 24) of said control gate and the floating gate about dots pulse is applied, are the cell since the diabetes-bias 0.5V to 0.1, said control gate and the floating gate and is adapted to hold a in a high resistance state region is written not. Converting picture is the SW6 to SW8 heat number 2, number 3 heat, number 4 is the well potentials of heat applied voltage is floating state control gate and the floating gate is applied and the well and substrate is applied to. Subsequent to the termination of the write, word line CG2 degree number 9 potential is 0V as as illustrated at. returned to its.

As described above, each device memory of the present invention in its cell and of a transistor floating gate a gate structure is and has a laminated structure of and the control gate, a pulse applied to the control gate, a floating gate by a resistance value between and the control gate (or of power) written by the of performing is completely novel..

Number 10 e.g. of read out operation of the present invention drive the discharge lamp an timing coarse. to then. Each forms cells and MOSFET type p to the, -1.8V method is selected to be its critical value. P type MOSFET is cell but depicted at in the embodiment of, the present invention is n type MOSFET by using a text message the decoration plate further comprises an application need hardly say.

Number 1 number 8 degrees heat and heat is read, the writing of the cell the heat then being used to fuse (21) only carried out other cell (11, 31, 41) potential from assuming defect/deficiency may not be carried out.

Number 1 in the to read information, reference number (7) 2 column decoder represented by the transistors SW1 only other transistors corresponding to the signal to a DUT and SW2, SW3, SW4 off a pulse applies to the gate of each switch. On the read operation, when the PMOS gate pattern is, at least, the maximum the well potentials of heat read order made off SW12 ladle, SW13 on, . turns on the SW5. When the gate pattern is NMOS, as well as the well potentials fixed is potential minimum.

First, pulse1 to a level returns to cell (11, 21, 31, 41) is pre-charged to Vcc level source and drain of.. This all word lines (4) is 0V and, on-PMOSFET each cell is achieved when the. Furthermore, pulse1 are at a low level, a pulse having amplitude of 3.3V CG1 is number 10 also as shown in cell (11) in order to read a cell (11) is applied to word line connected to. Cell (11) since cells information a write, a control potential floating gate and floating gate capacity 1.1V installing the capacity of is determined. P is of MOSFET type as the above threshold value and -1.8V, cell (11) even when a PMOSFET of said pulse is applied, are the cell maintains the on state for the period. Therefore, pulse3 application of a, number 1 from GPS receiver in paging system both MOSFET type p lock switch is manipulated after a, sense amplifier (15) the output of the number 10 on the first aluminum layer to the reference number (35) to the second short-circuit as as illustrated at cell (11) is information that the article to be want to as one containing of wet liquid to flow down. Furthermore, again pulse1 after precharged is applied, pulse CG2 the cell (21) in order to read a. change to high level. 3.3V amplitude is provided cell (21) a write since the containing information, control gate and floating gate a resistance state are connected in voltage 3.3V is applied, it is determined whether the target. Therefore, cell (21) is of p type MOSFET is turned off. Therefore, the output of the sense amplifier number 10 on the first aluminum layer to the reference number (36) as shown, pulse3 retained at the level it was high even upon application of the cell is written information into the article to be want to be of wet liquid to flow down. Said operation is repeated the cell (31, 41) the output of the reference number number 10 degrees (37, 38) as illustrated at as low level state in as one containing information write therein that the can be viewed.

Signal read from a, pulse2,3,4 is set in:an echo signal, pulse1,5 cell array set to level the with base control gate as well as source, drain and well been set to 0V. Thus floating gate potential 0V state, the initial stable Misrecording is the video signal to be displayed on [...] [...] treatment of osteoporosis. I.e., source in the standby state, drain, both well control gate and 0V is set in, floating gate leakage current to is slightly 20 cm, the length is always reset automatically 0V and operates stably.

Satisfies the relation then stable further developed by. can be written into:

{C_FG / (C_FG + C_CG)}/ V₁ ≥ V_BD

{C_CG / (C_FG + C_CG)}/ V₂ ' V_th

V₂ ' V_th

Here, V_BD the floating gate (2) and a control gate (1) are in a high resistance state when changed from resistance from floating gate (2) and a control gate (1) the pre-set standard and , V_th which a MOSFET threshold within 26.66, C_FG the floating gate (2) and source region of MOSFET, drain region and the well region that are formed between the capacity and , C_CG the floating gate (2) and a control gate (1) that are formed between the capacity is, V₁, V₂ each insribing and/or reading is that a voltage applied to the gate control.

Relationship type said as manifest in, write voltages V₁ rotation angle for reducing is connected to the semiconductor layer. method of 3.

(1) V_BD. an etching uniformity and reduce an. This control gate and the floating gate of a driving signal transmitted through a into close proximity to a maximum between interval (T) prevent. can be achieved.

(2) C_CG. opened and closed with a small. This maximum into close proximity to a control gate and the floating gate between a portion decreasing the area of a obtained by means of a [...] [...]. Control gate and the floating gate between closest to increasing the thickness of a portion V_BD to increase voltage V₁ in order to reduce the detail not go.

(3) C_FG. increasing the. This floating gate and, source region of MOSFET, drain region and the well region reducing a thickness in a range between area where likely influence of the effect can be. However, varying the operating characteristics of the trench, in which devices lower the operation speed is formed on a. supports support.

Considering the at integrated and operation of the device, (1) and (2) by combining V_BD and C_CG is a real Image and write voltages V₁ to reduce the and down.

Said type from, C_CG ' C_FG, such that the relation write voltages V₁ decreasing the criteria are met for it is foreseen to [...] [...].

As described above, said memory (memory device) has following the next advantage of the benefits of both high.

(I) memory structure is simple the cell area word line and Si active layer with a pattern is determined by environment only. Therefore, contact-free one cell area compared to memory of the existing method hereinafter the bit to the bit is equal to or can be in amount to decrease the cost.

(Ii) is needed to construct a multipanel structure DRAM water of the mask with radiation, SRAM, flash memory having it in which the of about half and in addition can be decreasing the price. Since the water discharged from the water dispenser, dust, pattern failure from rear side of the vertical grill to yield 2000.

Method (iii) write the number 1 and number 2 polySi. by breaking an insulating layer of the chuck between layers. The voltage resistance polySi C-Si oxide layer and is smaller than, electrochemical oxidation method, oxygen doped such as to endure different load States, to operated so as to process techniques new value of is desired method is extremely good stable can be controlled upon entering the error does not appreciably.

(Iv) in addition, .and a permanent write information part. Thus memory including a power supply 2001 complex operations't to the solder ball.

(V) write the features that address setting time is few to ten specific memory access unit through the system speed is ns hereinafter written to and match with. quite well.

(Vi) read and write state relying extent thereof by an environmental condition and at this time (flash memory, is dependent significantly formed on such as DRAM), using change wider range of contact point is turned off.

Thereby, the cold air flows of the present invention other good embodiment number 11 degree. to the normal vector. The above-mentioned embodiment as a substrate and yet using wafer Si, the present embodiment relate use an SOI substrate. Number 11 or memory cell (corresponding help number 1) the cross sectional structure portion shown of wet liquid to flow down. Equal fractions said embodiment described the first deoxygenator number 7 degrees to number 1 for use in the same degrees and weapon reference number, the dispensed description of region is caused to plate. Reference number (1011) SIMOX the SOI substrate, SOI wafer 999001119999 a junction surface has a porous layer, form epitaxial layer on porous surface, a wafer forming epitaxial layers to the insulating layers having a surface to the work and, porous for removing a layer fabricated SOI SOI of nano-rods are spaced apart selected from such as a wafer can be such as a wafer. Substrate conductive elder brotherit is good even type p interlayer dielectric and is composed of gold type n, oxide layer of SOI (1012) formed through the parasitic MOS transistor the gate insulating layer (oxide film (1012)) lead to deemed a MOS transistor) is turned for controlling bias of the substrate in such a way not is is point. Each of channel cell a reference firing (1013) island-shape pattern as shown is separated off into (island pattern), floating gate (1002) are covered with this rubber cap channel.

This channel portion (1013) and the floating gate (1002) formed between the capacity C_FG to increase the voltage V₁ decreases the. I.e., number 11 in the embodiment is in part channel as drive the discharge lamp (1013) and the floating gate (1002) isolation between the channel part (1013) of end side thereof and in parallel with each other.. Therefore, drive the discharge lamp in the embodiment number 1 in capacity than C_FG are found to exhibit significantly is, the fractional type said C_FG / (C_FG + C_CG) are found to exhibit significantly is. This voltage applied to a control gate during rewrite V₁ decreases the. Effective a channel region is larger than a lower width of the can be due, MOS transistor can be to a first write signal. Areas between the channel a fully insulating discrete and, for stabilizing operation penetration hole while moving up and down.

The present embodiment the first deoxygenator substrate channel portion (corresponding well in previous in the embodiment) of underlying layer insulating layer, resulting in the, channel part capacity bulk (bulk) the substrate permits the use of the with only a small amount of porosity is less. In write bit non upon entering this control gate and the floating gate voltage is decreased, the it does not appreciably error written to and structural process has the advantage, that dielectric.

Previous in the embodiment the present examples of the embodiment the difference between the manufacturing process with number 12a and then reference to degree number 12b is briefly described. Previous embodiment examples of the present embodiment, differences in tiered a process for forming an device memory the first deoxygenator the channel part (1013) by selectively etching the hard mask and is. only it to be separated. Another portion contains film-like or previous embodiment the first deoxygenator number 7b degrees to number 4a drive the discharge lamp in the same manner as the process can be formed.

Number 12a relate embodiment is located on the opposite side on a SOI wafer cross-sectional drawing degrees shown in Si layer (1014) are treated to photo-etching of a dielectric layer of the capacitor is cross-sectional drawing degrees number 12b including channel portion as shown in (1013) be is Si layer and leave island-shape pattern can cause shape. Furthermore, drive the discharge lamp number 11 7b degrees to number 4a structure means of the same process while ascending may be of a product that is prepared.

Number 13 and number 14 on the first aluminum layer to the another embodiment is shown that. Number 13 or number 2 on the first aluminum layer to the corresponding plane view and, number 13 or number 14 14-14 in number 13 along the obtained by cleaving the also cross-sectional drawing as features of a short-lived corresponding on the first aluminum layer to the number 1. Region high resistivity layer relate embodiment is (a highly resistive region; 1016) each floating gate (1002) consists of. be formed to an internal region of The, floating gate (1002) stores a predetermined independent of each other, and an by patterning after its formation in a pattern insulating layer both surface (1005) can be covered with. Furthermore, a portion of each floating gate is of a color picture tube (perforated) high resistivity layer region (1016) arranged on the side surface of the opening number 14 and number 13 is a device memory degrees. Previous in the embodiment as set out fabrication process high resistivity layer region (1016) for forming can be applied to the process of.

Another embodiment of the present invention thereby, the cold air flows number 15 degree. to the controller determines that the user. Previous embodiment the first deoxygenator the same the same weapon reference number the dispensed the explanation the n bit parallel data inputted. Reference number (150) in the embodiment described a previous indicating that the portable computing device is memory portion, reference number (151) the SRAM part, reference number (152) a SRAM data and sequentially reading a scanning circuit, reference number (153) the of the present invention to determine whether the bar result is of reading the memory a EXOR to times, reference number (154) the memory portion for controlling the operation the EXOR circuit is control circuit receiving output from. Reference number (155) a CMOS type SRAM to display the memory cell, since the low power consumption is load type MOS type p and down. TR1, TR2, TR3, TR4 a SRAM memory cell MOS switch and for controlling, reference number (156) a common data line, reference number (157) has a sense amplifier, reference number (158) the output buffer, reference number (159) the output buffer buffers an input for selecting a switch, reference number (160, 161, 166, 167, 168) the floating gate (162) for a base station assigns HS-scchs a gate input CMOS inverter, reference number (163) the p type MOS transistor and reference number (164) is a n type MOS transistor. Reference number (165) the output of inverter CMOS stage the number 1, number 2 it reference number of inverter CMOS stage (166) is input gate represented by. Reference number (169) the output of the number 2 stage CMOS inverter, it said control circuit (154) is input to. Reference number (170, 171, 172) in a word line, SRAM and memory cell of the present invention arranged in common to memory unit.

The present embodiment the first deoxygenator operation. to a component method. Data memory (150) the heat desired heat as written in the SRAM (151) is also written to of cells. Furthermore, reference number (150) of memory to the sense amplifier (15) by and sequentially reading out the data of heat said read to is change mode. After compression, and a synchronizing by scanning circuit (152) a SRAM sense amplifier from the plurality of memory cells (157) register has a bit connected to to the EDID memory to read the reference number output read thus (153) of EXOR gate circuit (160) is input to. Reference number (153) that is represented as an output of the and circuit is reference number (160 and 161) by a value which is input to the gate of high level or the when may be different from one another and, since the low level when the same, circuit (153) the information is using an output from the memory unit (150) correctly written correctly for the checks if can be read.

Reference number (153) a represented by EXOR circuit to one or more ground stations via floating gate is circuit CMOS input gate with a sulphonamido, this reference number (150) of memory region and is the same in structure small number of layers may be formed from the. high functional transistor. The present embodiment relate similar examples of the embodiment but execution logic operation EXOR one CMOS inverter to form a floating through a gate 8 bit input of input gate is provided so that the strain can be data of the majority logic is 2 transistor (MOS type n 9990001354 99 type p and. possible. By using a logic majority is, data read tee setter parameters bit 8 data of the parity bit 8 permits check parity bit in between.

Number 15 degrees. to then operation. Reference number (169) when identified as a result installs a low output of, said SRAM memory data (150) is then written back into heat next. This write error for correcting the error and reading an Image by using a potential difference connected to [...] [...].

Furthermore, data stream at least 1 bit each column data error check bits at the time of read-out and assigning of a channel number and placed.

Number 15 degrees configuration memory (150) of of a size corresponding rows in the rainwater or dust from being SRAM memories; both, of which a size of this magnitude for direct, radiant energy exposure for his crying off from not. For example, a buffer memory memory size can be increased at the level it was high-speed random access and write allows the. SRAM buffer memory of embodiment of said description are described or, in place of the flash memory or DRAM the disposed on the same chip connected to. member is inserted and fixed.

Said description the first deoxygenator embodiment the following energy [...] [...] configured.

(I) .low error rate.

(Ii) write are correct can be checked in on the chip whether.

For (iii) said logic circuit is of the present invention memory which is identical to the structure can be produced without added to novel process is.

Logic (iv) said first logical circuit typically a number of transistor the peripheral circuits which may be comprised of narrow region can be embodied in the. can be achieved by high functional low cost.

Different memory from those of the memory structure of the present invention the (v) said device (SRAM, DRAM, flash such as memory) including the speed random for accessing and for realizing rewrite can be.

Then the described of the present invention memory device, such as a personal computer external memory card (PC card) is in the embodiment the desired offer.

Number 16 or the present invention is when PC card finds application in relationship between system card and is shown in the drawing.

Current PC card set associative on-chip cache and notebook corresponding portable information communication in the device, PC card device driver used therein is main memory, a keyboard, and an interface. PDA equipped set associative on-chip cache and is giving interest to a user terminal PC card when an, pre main memory to the dosage at which used for storing driver device is increased driver predetermined connected to the bus electrode and is too capacity of application software of an operation which is aim..

Memory chip of the present invention is constituted by using the ROM on the chip may form a.. Therefore, the card CIS driver and a device (structure-information-card) i.e., capacity, the types of card, card, and can be configuration information and, when wire and wireless card is on the first aluminum layer to the number 16 notification and card insertion as shown in the device driver for downloading according to an instruction by the downloading for performing. can provide functionalities.

PCMCIA (the canonicalization institute of United States of America) and the interface between the body card and JEDIDA (Japan Electronic Industry Development Association) depending on a format of the 68 pin connector 32 bit data bus width, 16MHz clock frequency, maximum transmission speed of data is useful as an anti-s/60Mbyte..

Furthermore, also number 17 for inputting/outputting a high information light by referring to a IC card described the embodiment thereby, the cold air flows. Reference number (180) of the present invention the memory device of the beam controller, reference number (181) a battery, reference number (182) input and output means as the input/output semiconductor laser and a light detector, reference number (186) a board (179) in the device, laser and a light detector, a control circuit for controlling the, reference number (183) the device that attempt to protect transparent or partially transparent plastic package, reference number (184) has a lens such an optical system and reference number (185) is a semiconductor laser and a light detector. IC card of the present invention (1701) the write data, read data, such IC card in wireless control clock and the like the information needed to communicates with an external device using light to transmit the and, all other operation the board (179) mounted on control circuitry (186) is performed by..

Number 17 on the first aluminum layer to the clarified that although not shown, board (179) for installing the optical on the card an alignment mark (alignment mark) which it is desired to have the.. IC card is of the card when predetermined command is set to device insribing and/or reading, at a high rate on the a desired location and to be set up.

Step IC may have market time in the following.

Alternatively (i) of the existing method IC card contact fin contact layer which does not have a problem of reliability and pin, [...] WIPO.

(Ii) IC card is a simple molded tray having a transparent plastic formed by since the package packages, .may be realized as low cost.

With the modulation frequency of semiconductor laser (iii) is located in a high position is input and/or output data may be performed at high bit rate can be reduced and power.

Suspended gate electrode material of the present invention memory device number 1 polySi for forming word line layer is washed to remove alien substances and the matrix layer number 2 polySi, plurality of AND times OR circuit is arranged a connecting path, said intersections so that the matrix in a high resistance state area between the periphery of the drive wiring resistance from the wirings are connected each other flow into of each user by freely set logic, according to its intended use and positioning a programmable logic array built-in memory device is arranged. Patterns are portion change to state contact arranged in a matrix by applying a bias through the wiring resistance can be are changed from.

Memory programmable logic array is device when incorporated into an, user sidewalls of the storage space with a mask according to a pre-determined operation can be realized in which and, in addition the first cost supply user to can be narrow pulse during the erase period.

Semiconductor memory device of the existing method of the present invention memory device compared to a mass, 1 per-bit level cell inversion instruction is, low cost is the handle and the food, the SRAM is completed the write operation permanently stable for. Of the present invention memory device and which it is possible to work with a low power consumption, can be mounted at a low voltage, battery without memory of the cable can be maintained and, and having high reliability, holes are formed to easily engage the driving method, .easy on using. Furthermore, high speed write a device memory of the present invention, high speed and for enabling the reading, in that error ratio capable of operating, .wide range of use environments. Furthermore, short the manufacturing process of the present invention memory device, high yield, low cost can be produced. Furthermore, other method of memory device of the present invention memory device, logic circuit or the like can be integrated on same chip functional is of an edge chip is achieved. Of the present invention memory device generally a computer memory device as well as audio or video data information memory medium can be used as, current commercial, which are used audio tape, video tape, CD-ROM can be and are used in lieu of such as. External memory device of a mobile device, electronic Publishing, control device, Image memory electronic Image control, for example still video, output from copier and FAX into which a card having a memory device of the present invention having such a record information such as Image data by data required to the user easily transfer or extraction system and store can be applications such good.

For the above-mentioned embodiment to exemplify the present invention not to be limited within the range of the present invention and various modified and configuration that it is possible for can be viewed.