ТОНКОПЛЕНОЧНЫЙ ТРАНЗИСТОР ИЗ НИЗКОТЕМПЕРАТУРНОГО ПОЛИКРИСТАЛЛИЧЕСКОГО КРЕМНИЯ И СПОСОБ ЕГО ИЗГОТОВЛЕНИЯ

Настоящее изобретение относится к тонкопленочному транзистору из низкотемпературного поликристаллического кремния, который обладает определенными электрическими характеристиками и надежностью, и к способу изготовления такого тонкопленочного транзистора. Тонкопленочный транзистор из низкотемпературного поликристаллического кремния включает по меньшей мере подзатворный слой, которым является композитный изоляционный слой, включающий по меньшей мере три диэлектрических слоя, при этом плотность каждого диэлектрического слоя последовательно увеличивается в порядке их формирования в данном способе изготовления. Поскольку согласно настоящему изобретению учитывается отношение между плотностью каждого слоя композитного изоляционного слоя и плотностью других его слоев, каждый слой в композитном изоляционном слое тонкопленочного транзистора из низкотемпературного поликристаллического кремния, изготовленный способом согласно настоящему изобретению, имеет улучшенные характеристики контакта поверхности ...

Tunneldiode und Speicheranordnung mit derselben

VERFAHREN UND VORRICHTUNG ZUM ZWEIDIMENSIONALEN AUFBAU VON PARTIKELN

MISFET with minimal current - comprises diamond insulating layer between gate electrodes and semiconductor

MISFET comprises an insulating layer (4) of diamond between gate electrodes (6) and a semiconductor (2) having a larger energy gap than Si. A material chosen from GaP, GaAs, GaN, AlN, AlP, BN and SiC is used a semiconductor. The thickness of the insulating layer (4) is 0.001-10 microns, or 0.01-2 microns. The diamond layer has a protective coating. ADVANTAGE - Leaking current is kept to a min. between gate and drain.

VERFAHREN ZUR HERSTELLUNG EINES FELDEFFEKT-TRANSISTORS

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH A DOUBLE INTERCONNECTION LAYER

INSULATED GATE FIELD EFFECT TRANSISTORS AND METHODS OF MAKING THEM

... 1376492 Semi-conductor devices WESTERN ELECTRIC CO Inc 16 March 1972 [18 March 1971] 12243/72 Heading H1K An IGFET comprises (Fig. 1), a semi-insulant substrate 17 superimposed with a semi-conductor layer 14 having source and drain ohmic contacts 11, 13 separated by insulant layer 15 carrying a gate contact 12 and a channel 16 between the contacts overlying the insulant substrate 17; the source-drain current being modulated by the gate voltage. The substrate is of III-V material, e.g. gallium arsenide on which layer 14 is epitaxially grown with vapour deposited source-drain contacts; the intervening uncovered part of layer 14 being irradiated in the high energy protons from a source (Fig. 2, not shown), to increase its resistivity by crystal lattice destruction for part of its depth to form insulant layer 15, in which gate 12 is deposited by etching and vapour deposition. Plural IGFETS may be fomed on a single wafer, separated by scribing and cleaving, and enclosed in a package with thermocompression ...

Structure of the insulator - semiconductor type

Structure of the insulator-semiconductor type constituted by a semiconducting crystalline substrate formed from a III-V compound of formula (AIIIBV) coated with an insulating layer, wherein the substrate has a specific crystalline orientation and wherein the insulator is a sulphide in accordance with the formula (AIIIBV)S4. It also relates to a process for the preparation of such a structure. Applications of the invention occur in the fields of microelectronics and optoelectronics.

Semiconductor device and method for manufacturing the same

The invention provides a semiconductor device in which an insulating film or a semiconductor film is firmly bonded with a metal silicide film, and also provides a method for manufacturing the same. The semiconductor device has a semiconductor substrate with an insulating film or a semiconductor film formed thereon, a carbon layer formed on the insulating film or the semiconductor film, and a metal silicide film formed on the carbon layer. Carbon atoms are thermally diffused by heating from the carbon layer into the insulating film or the semiconductor film and into the metal silicide film.

CONTROLLING OF REGENERATING A BOUNDARY SURFACE LAYER WITH A GATE STRUCTURE WITH HIGH DIELECTRIC CONSTANT FOR FIELD-EFFECT TRANSISTORS

PROCEDURE FOR THE PRODUCTION OF SILICON DIOXIDE PASSIVATION OF HIGH QUALITY ON SILICON CARBIDE

ELECTRIC-ELECTRONIC DEVICE INCLUDING POLYIMIDE THIN FILM

An electric-electronic device including a polyimide thin film is disclosed, said polyimide thin film having a thickness of not more than 1000 A and a dielectric breakdown strength of not less than 1 x 106 V/cm, and an electric-electronic device comprising a polyimide thin film and the group III-V or II-VI compound semconductor is also disclosed. The device has excellent properties ascribed to high heat resistance, mechanical strength, chemical resistance and insulating properties of the polyimide thin film.

SEMICONDUCTOR DEVICE HAVING A PASSIVATING LAYER

Semiconductor device having a passivating layer to reduce and stabilise the surface recombination rate. The device is characterized on the one hand in that an active region is covered by a passivating layer of polycrystalline semiconductor material which has the same conductivity type as and preferably approximately the same impurity concentration as the region, and on the other hand in that the energy gap of the material of the layer is preferably at least 80 millielectron volts larger than that of the material of the region. The invention may be applied to semiconductor devices operating via injection of minority charge carriers in particular in optoelectronic devices.

METHOD FOR MANUFACTURING ION IMPLANTED INSULATED GATE FIELD EFFECT SEMICONDUCTOR TRANSISTOR CES

NON-VOLATILE MEMORY DEVICES FABRICATED FROM GRADED OR STEPPED ENERGY BAND GAP INSULATOR MIM OR MIS STRUCTURES

METHOD AND APPARATUS FOR TWO DIMENSIONAL ASSEMBLY OF PARTICLES

... ²²²A method and an apparatus (10) for making thin layers from particles, wherein ²the particles are deposited on a carrier fluid flowing by gravity along a ramp ²(12) leading to a dam (18). The particles are held back at the bottom of the ²ramp (12), thereby causing the particles to be piled up one against the other ²in a monolayer configuration.² ...

Transistron unipolaire

Verfahren zur Herstellung von Feldeffekt-Transistoren

МИКРОКРИСТАЛЛИЧЕСКИЕ И НАНОКРИСТАЛЛИЧЕСКИЕ СТРУКТУРЫ С НИЗКОЙ ДИЭЛЕКТРИЧЕСКОЙ ПРОНИЦАЕМОСТЬЮ ДЛЯ ПРИМЕНЕНИЯ В ОБЛАСТИ ВЫСОКИХ ТЕХНОЛОГИЙ

Настоящее изобретение предлагает способ получения пригодных для применения слоев неявных кристаллов (т.е. слоев микро- и нанокристаллов) с низким значением диэлектрической проницаемости на известных в технике полупроводниковых подложках, а также получения наноструктур, сформированных из этих неявных кристаллов, и относится к оптическим и электронным устройствам, которые могут быть получены из этих материалов. Полученные результаты показывают, что модифицирование структуры и химического состава матрицы монокристалла с использованием метода химического осаждения из паровой фазы обеспечивает получение высококачественных гомогенных слоев неявных кристаллов, которые образуют гладкую границу раздела с полупроводниковой подложкой. С помощью этого способа можно осуществить осаждение диэлектрических неявных кристаллов со скоростью 1 мкм/ч. Настоящее изобретение также обеспечивает способ получения микро- и нанопроволок путем преобразования неявных кристаллов в упорядоченные структуры. Настоящее изобретение ...

P-type MOSFET and its manufacturing method

Method for protecting a semiconductor device against degradation, a semiconductor device and a manufacturing method therefor

Semiconductor assembly with a high dielectric constant gate dielectric layer and producing method thereof

PUT TRANSISTOR HAS GRID AUTO-ALIGNEE AND ITS MANUFACTORING PROCESS

FLUORINATED POLYTHIADIAZOLE, THEIR PREPARATION FROM FLUORINATED AROMATIC TETRA-AMINES AND THEIR APPLICATIONS.

INSULATED GATE FIELD EFFECT TRANSISTORS AND METHODS OF MAKING THEM

PROCEEDED OF REDUCTION OF COMPOSES IN LAYER ON A SUBSTRATE AND ITS APPLICATION TO THE MANUFACTURE OF SEMICONDUCTOR STRUCTURE HAS FIELD EFFECT

DEVICE SEMICONDUCTOR PROVIDED With a PROTECTIVE FILM

ELECTRONICS COMPONENT, MANUFACTORING PROCESS AND USE OF GRAPHENE IN AN ELECTRONICS COMPONENT

METHOD OF MANUFACTURING A SPACER FOR DOUBLE-GATED ELECTRONIC MEMORY CELL AND MEMORY CELL ELECTRONICS ASSOCIATED

L'invention concerne un procédé de fabrication d'un espaceur (311, 312) pour mémoire électronique comportant : - un substrat (300) ; - une première structure de grille (301) ; - un empilement (304) comprenant plusieurs couches et dont au moins une desdites couches est apte à stocker des charges électriques. Ce procédé comporte les étapes suivantes : - dépôt d'une couche d'un matériau de l'espaceur au moins sur la zone recouverte par l'empilement (304) ; - usinage ionique de la couche du matériau de l'espaceur, ledit usinage ionique s'effectuant avec arrêt contrôlé de manière à conserver un reliquat de l'épaisseur de la couche du matériau de l'espaceur recouvrant l'empilement (304) ; - gravure plasma du reliquat de l'épaisseur de la couche du matériau de l'espaceur.

Plasma Generation Apparatus

SEMICONDUCTOR DEVICE AND A FORMING METHOD THEREOF CAPABLE OF IMPROVING INTERFACE RESISTANCE BETWEEN A POLY SILICON LAYER AND A CONDUCTIVE LAYER

PURPOSE: A semiconductor device and a forming method thereof are provided to prevent metal from being spread from an interface resistance improving layer and a poly silicon layer by making the poly silicon layer amorphous before the interface resistance improving layer is deposited. CONSTITUTION: A gate insulating layer(103) is formed on a semiconductor substrate(101). A poly silicon layer(105) for a gate electrode is formed on the upper side of the gate insulating layer. A poly silicon layer becomes amorphous. An interface resistance improving layer and a conductive layer are laminated on the amorphous poly silicon layer. A hard mask layer and a photoresist pattern are laminated on the conductive layer. COPYRIGHT KIPO 2012 ...

LOW POWER FLASH MEMORY CELL AND METHOD

Oxide semiconductor thin film transistor and Display Device and Method of manufacturing the sames

SEMICONDUCTOR MEMORY DEVICE

METHOD OF MANUFACTURING TRANSISTOR WITH ENHANCED RECESS CHANNEL FOR PREVENTING SHORT CHANNEL EFFECT

PURPOSE: A method of manufacturing a transistor is provided to prevent short channel effect by using an enhanced recess channel. CONSTITUTION: A plurality of trenches(110) for a recess channel are formed on a semiconductor substrate(100). An isolation layer is formed in the substrate. A gate dielectric film(310) is formed along an upper surface of the resultant structure. A gate(330) for filling completely the trench is formed on the gate dielectric film. A source and drain region are formed in the substrate to align the gate. © KIPO 2005 ...

비 평면형 트랜지스터용의 텅스텐 게이트

... 본 발명은 비 평면형 트랜지스터를 갖는 마이크로 전자 장치의 제조 분야에 관한 것이다. 본 설명의 실시 형태는 비 평면형 NMOS 트랜지스터 내의 게이트의 형성에 관한 것인데, 여기서 알루미늄, 티타늄 및 탄소의 조성물 등의 NMOS 일함수 물질은, 티타늄-함유 게이트 충전 장벽과 함께 사용될 수 있어서, 비 평면형 NMOS 트랜지스터 게이트의 게이트 전극의 형성 시에 텅스텐 함유 도전성 물질의 사용을 용이하게 한다.

NORMALLY OFF III-NITRIDE SEMICONDUCTOR DEVICE HAVING A PROGRAMMABLE GATE

A III-nitride semiconductor device which includes a charged gate insulation body. © KIPO & WIPO 2008 ...

PERFLUOROALKYLENEOXY GROUP SUBSTITUTED PHENYLETHYLSILANE COMPOUND WITH EXCELLENT THERMAL AND CHEMICAL STABILITIES, A PERFLUORO-POLYMER PREPARED BY POLYMERIZING THE SAME AND AN ORGANIC THIN FILM TRANSISTOR COMPRISING AN INSULATION LAYER PREPARED FROM THE POLYMER

PURPOSE: A novel phenylethylsilane compound is provided to show excellent thermal and chemical stabilities, thereby being capable of being subject to a solution process. A perfluoro-polymer prepared by thermal polymerization of the novel compound is provided to show excellent resistance to an organic solvent. An insulation film obtained from the polymer is provided to show improved thermal and physical characteristics, thereby being applied to an organic thin film transistor with excellent on off ratio. CONSTITUTION: A phenylethylsilane compound where a perfluoroalkyleneoxy group is substituted is represented by the formula(1), wherein R1, R2 and R3 are same or different from each other and are selected from the group consisting of H, F, C1-4 alkyl, and one to six fluorine atom(s) substituted C1-4 fluoroalkyl, provided that at least one of the R1, R2 and R3 is F or fluoroalkyl; Z1, Z2 and Z3 are same or different from each other and are selected from the group consisting of H and C1-4 alkyl ...

A method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode

REPLACEMENT GATE FIELD EFFECT TRANSISTOR WITH GERMANIUM OR SIGE CHANNEL AND MANUFACTURING METHOD FOR SAME USING GAS-CLUSTER ION IRRADIATION

A self-aligned MISFET transistor (500H) on a silicon substrate (502), but having a graded SiGe channel or a Ge channel. The channel (526) is formed using gas-cluster ion beam (524) irradiation and provides higher channel mobility than conventional silicon channel MISFETs. A manufacturing method for such a transistor is based on a replacement gate process flow augmented with a gas-cluster ion beam processing step or steps to form the SiGe or Ge channel. The channel may also be doped by gas-cluster ion beam processing either as an auxiliary step or simultaneously with formation of the increased mobility channel.

A MOS DEVICE ASSEMBLY

A MOS device assembly comprising at least a first transistor (110) and a second transistor (111), each having a gate region. The dimensions of the gate region of the first transistor are different from the dimensions of the gate region of the second transistor and the transconductance of the MOS device assembly is substantially uniform when the gate regions of the first and second transistors are biased using the same voltage.

MIS TRANSISTOR WITH SELF-ALIGNED GATE AND METHOD FOR MAKING SAME

The invention concerns a MIS transistor having a T-shaped gate characterized by the presence of a shape material (14) coating a solid T shape. The gate structure is housed in the envelope formed by the shape material (14). The coating of the T shape of the gate by the shape material (14) is carried out right from the beginning of the production of the gate structure and is selected such that it is resistant to all the subsequent processes for manufacturing the transistor and is maintained, thereby defining the final shape of the gate structure, thus resulting in a perfectly controlled gate shape.

IMPROVED PROCESS FOR DEPOSITION OF SEMICONDUCTOR FILMS

Chemical vapor deposition processes utilize chemical precursors that allow for the deposition of thin films to be conducted at or near the mass transport limited regime. The processes have high deposition rates yet produce more uniform films, both compositionally and in thickness, than films prepared using conventional chemical precursors. In preferred embodiments, trisilane is employed to deposit thin films containing silicon are useful in the semiconductor industry in various applications such as transistor gate electrodes.

Integrated circuit having a contact etch stop layer and method of forming the same

A method of forming an integrated circuit structure includes providing a gate stack and a gate spacer on a sidewall of the gate stack. A contact etch stop layer (CESL) is formed overlying the gate spacer and the gate stack. The CESL includes a top portion over the gate stack, a bottom portion lower than the top portion, and a sidewall portion over a sidewall of the gate spacer. The top and bottom portions are spaced apart from each other by the sidewall portion. The sidewall portion has a thickness less than a thickness of the top portion or a thickness of the bottom portion.

Method and system for utilizing Perovskite material for charge storage and as a dielectric

Memory devices and methods for providing the memory devices are provided. The memory devices utilize multiple metal oxide layers. The methods for providing the memory devices can include providing a transistor; producing a capacitor that includes metal layers and metal oxide layers; connecting the capacitor to a side of the transistor; and providing a wordline, bitline, and driveline through connection with the transistor or the capacitor.

Organic-inorganic composite insulating material for electronic element, method of producing same and field-effect transistor comprising same

A method of producing an organic-inorganic composite insulating material for electronic element comprises subjecting a mixture of an organic polymer or its solution and a metal alkoxide or its solution as a starting material to sol-gel reaction of the metal alkoxide in the presence of the organic polymer.

III-nitride semiconductor device with trench structure

A III-nitride trench device has a vertical conduction region with an interrupted conduction channel when the device is not on, providing an enhancement mode device. The trench structure may be used in a vertical conduction or horizontal conduction device. A gate dielectric provides improved performance for the device by being capable of withstanding higher electric field or manipulating the charge in the conduction channel. A passivation of the III-nitride material decouples the dielectric from the device to permit lower dielectric constant materials to be used in high power applications.

Semiconductor integrated circuit means comprising conductive protein on insulating film of calcium phosphate

A semiconductor circuit means having an electrode of a conductive protein, cytochrome C and/or mitochondria, which is attached to an insulating film of phosphate, especially calcium phosphate, deposited on a substrate of a silicon monocrystal. A small and effective integrated circuit is obtained.

High purity zirconium or hafnium, sputtering target comprising the high purity zirconium of hafnium and thin film formed using the target, and method for producing high purity zirconium or hafnium and method for producing powder of high purity zirconium or hafnium

The present invention relates to high-purity zirconium or hafnium with minimal impurities, particularly where the content of alkali metal elements such as Na, K; radioactive elements such as U, Th; transitional metals or heavy metals or high melting point metal elements such as Fe, Ni, Co, Cr, Cu, Mo, Ta, V; and gas components such as C, O, etc. is extremely reduced, as well as to an inexpensive manufacturing method of such high-purity zirconium or hafnium, thereby reducing the impurities hindering the guarantee of the operational performance of semiconductors. The present invention further relates to an inexpensive and safe manufacturing method of high-purity zirconium or hafnium powder from hydrogenated high-purity zirconium or hafnium powder.

Dielectric layer forming method and devices formed therewith

Embodiments in accordance with the present invention provide alternative materials, and methods of forming such materials, that are effective as dielectric layers. Such embodiments include forming metal-containing dielectric layers over a silicon-containing substrate where a metal-containing layer is first formed and that treated to form a dielectric layer. Dielectric layers formed by methods of the present invention have a dielectric constant greater than that of silicon dioxide, and can have an equivalent oxide thickness of less than 2 nanometers. Such dielectric layers are useful in the forming of a variety of semiconductor devices such as transistors, capacitors and the like where such devices and integrated circuits formed from such devices are encompassed by embodiments in accordance with the present invention.

METHOD FOR MAKING MOSFET AND MOSFET

A method for making a MOSFET includes forming a gate oxide layer on a substrate; depositing and forming a polysilicon layer on the gate oxide layer; removing the polysilicon layer and the gate oxide layer in a target area by means of dry etching. The remaining gate oxide layer forms a gate oxide of the MOSFET. The remaining polysilicon layer forms a gate of the MOSFET. The method further includes performing LDD implantation on the substrate at both sides of the gate, to form a first LDD area and a second LDD area respectively; and performing SD implantation to form a source and a drain in the substrate at both sides of the gate respectively. Before one of the steps after the depositing and forming a polysilicon layer on the gate oxide layer, fluorine ion implantation is performed.

ELECTRIC-ELECTRONIC DEVICE INCLUDING POLYIMIDE THIN FILM

An electric-electronic device including a polyimide thin film is disclosed, said polyimide thin film having a thickness of not more than 100 ANGSTROM and a dielectric breakdown strength of not less than 1x106 V/cm. The device has excellent performance properties ascribed to high heat resistance, mechanical strength, chemical resistance and insulating properties of the polyimide thin film.

Insulation film for a semiconductor device

A semiconductor device is provided having as an insulating oxide film a silicon oxide film containing a metal, such as iron or chromium, of an average concentration of 1x1016 atoms/cm3 to 1x1019 atoms/cm3 which can be readily trapped therein.

Semiconductor device and manufacturing method thereof

A technique capable of reducing threshold voltage and reducing high-temperature heat treatment after forming a gate electrode is provided. An n-type MIS transistor or a p-type MIS transistor is formed on an active region isolated by an element isolation region of a semiconductor substrate. In the n-type MIS transistor, a gate electrode is formed through a gate insulating film, and the gate electrode is composed of a hafnium silicide film. On the other hand, in the p-type MIS transistor, a gate electrode is formed through a gate insulating film, and the gate electrode is composed of a platinum silicide film. Also, the gate electrodes are formed after the activation annealing (heat treatment) for activating impurities implanted into a source region and a drain region.

Deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators

Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al₂O₃, Ta₂O₅, TiO₂, ZrO₂, Nb₂O₅, SrBi₂Ta₂O₃, SrTiO₃, PbTiO₃, and PbZrO₃.

Method of forming a MISFET having a schottky junctioned silicide

There is disclosed a semiconductor device in which a device isolating insulating film is formed in a periphery of a device region of a semiconductor silicon substrate device region. A side wall insulating film formed of a silicon nitride film is formed to cover the periphery of a channel region on the silicon substrate. A Ta₂O₅ film, and a metal gate electrode are formed inside a trench whose side wall is formed of the side wall insulating film. An interlayer insulating film is formed on the device isolating insulating film. A Schottky source/drain formed of silicide is formed on the silicon substrate in a bottom portion of the trench whose side wall is formed of the side wall insulating film and interlayer insulating film. A source/drain electrode is formed on the Schottky source/drain.

Method and system for forming dual work function gate electrodes in a semiconductor device

A method is provided for forming dual work function gate electrodes. A dielectric layer is provided outwardly of a substrate. A metal layer is formed outwardly of the dielectric layer. A silicon-germanium layer is formed outwardly of the metal layer. A first portion of the silicon-germanium layer is removed to expose a first portion of the metal layer, with a second portion of the silicon-germanium layer remaining over a second portion of the metal layer. A silicon-germanium metal compound layer is formed from the second portion of the silicon-germanium layer and the second portion of the metal layer. A first gate electrode comprising the first portion of the metal layer is formed. A second gate electrode comprising the silicon-germanium metal compound layer is formed.

High charge storage density integrated circuit capacitor

An integrated circuit capacitor comprising a high permittivity dielectric and a method of forming the same are disclosed herein. In one embodiment, this capacitor may be used as a DRAM storage cell. For example, a DRAM storage node electrode 22 may be formed of polysilicon. An ultrathin oxynitride passivation layer 25 (e.g. less than 1 nm) is formed on this electrode by exposure of the substrate to NO. A tantalum pentoxide layer 24 is formed over layer 25, followed by a cell plate 26. Passivation layer 25 allows electrode 22 to resist oxidation during deposition of layer 25, thus preventing formation of an interfacial oxide layer. A passivation layer formed by this method may typically be deposited with shorter exposure times and lower temperatures than nitride passivation layers.

Damascene NiSi metal gate high-k transistor

A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining a low temperature silicidation metal within a recess overlying a channel and annealing to cause the low temperature silicidation metal and its overlying silicon to interact to form the self-aligned low temperature metal silicide gate. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.

Semiconductor device with reduced time-dependent dielectric failures

An insulated gate field-effect transistor or similar semiconductor-insulator-semiconductor structure has an increased time-dependent dielectric failure lifetime due to a reduction in the field across the gate insulator. The electric field in the gate insulator is reduced without degrading device performance by limiting the field only when the gate voltage exceeds its nominal range. The field is limited by lowering the impurity concentration in a polysilicon gate electrode so that the voltage drop across the gate insulator is reduced. In order to avoid degrading the device performance when the device is operating with nominal voltage levels, a fixed charge is imposed at the interface between the gate electrode and the gate insulator, so at a gate voltage of about the supply voltage level the response changes to exhibit less increase in the drop across the gate insulator for higher voltages. Also, the impurity level in the gate electrode may be low enough so that the gate is in deep depletion ...

PROCESS FOR MANUFACTURING VERTICAL DYNAMIC RANDOM ACCESS MEMORIES

Electronic devices utilizing superconducting materials

A new type superconducting electronic device is described. In the description, a field effect semiconductor device is constructed in accordance with the present invention. A superconducting ceramic material is deposited on the source and drain regions of the semiconductor device with insulating film therebetween functioning as a tunnel current film.

Gate contact structures and self-aligned contact process

The present disclosure relates to semiconductor structures and, more particularly, to gate contact structures and self-aligned contact process and methods of manufacture. The structure includes: a gate structure having source and drain regions; a first metal contacting the source and drain regions; a second metal over the first metal in the source and drain regions; and a capping material over the first metal and over the gate structure.

Techniques for enhancing vertical gate-all-around FET performance

Techniques for enhancing VFET performance are provided. In one aspect, a method of forming a VFET device includes: patterning a fin(s) in a substrate; forming bottom source and drains at a base of the fin(s); forming bottom spacers on the bottom source and drains; forming a gate along sidewalls of the fin(s); recessing the gate to expose a top portion of the fin(s); forming an oxide layer along the sidewalls of the top portion of the fin(s); depositing a charged layer over the fin(s) in contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the fin(s) forming a dipole; forming top spacers above the gate; and forming top source and drains above the top spacers. A method of forming a VFET device having both NFETs and PFETs is also provided as are VFET devices formed by the present techniques.

Shielded Gate Trench FET with an Inter-electrode Dielectric Having a Low-k Dielectric Therein

A method for forming a shielded gate trench field effect transistor (FET) includes forming trenches in a semiconductor region, forming a shield electrode in a bottom portion of each trench, and forming an inter-electrode dielectric (IED) extending over the shield electrode. The IED may comprise a low-k dielectric. The method also includes forming a gate electrode in an upper portion of each trench over the IED.

Method of fabricating a semiconductor device comprising a gate dielectric made of high dielectric permittivity material

A process and a device for fabricating a semiconductor device having a gate dielectric made of high-k material, includes a step of depositing, directly on the gate dielectric, a first layer of Si1-xGex, where 0.5 Подробнее

Vertical slit transistor with optimized AC performance

A method forms a vertical slit transistor includes raised source, drain, and channel regions in a semiconductor substrate. Two gate electrodes are formed adjacent respective sidewalls of the semiconductor substrate. The method forms dielectric material separating the gate electrodes from the source and drain regions.

SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE

A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first silicon carbide layer of the first conductivity type, and an insulating film. In the silicon carbide semiconductor device, no fluorine or chlorine is detectable in the insulating film, at a boundary layer of the insulating film and the first silicon carbide layer, or at the surface of first silicon carbide layer where the insulating film is provided.

Silicon carbide MOSFET with integrated MOS diode

A monolithically integrated MOS channel in gate-source shorted mode is used as a diode for the third quadrant conduction path for a power MOSFET. The MOS diode and MOSFET can be constructed in a variety of configurations including split-cell and trench. The devices may be formed of silicon carbide, gallium nitride, aluminum nitride, aluminum gallium nitride, diamond, or similar semiconductor. Low storage capacitance and low knee voltage for the MOS diode can be achieved by a variety of means. The MOS diode may be implemented with channel mobility enhancement materials, and/or have a very thin/high permittivity gate dielectric. The MOSFET gate conductor and MOS diode gate conductor may be made of polysilicon doped with opposite dopant types. The surface of the MOS diode dielectric may be implanted with cesium.

Replacement gate devices with barrier metal for simultaneous processing

A method of simultaneously fabricating n-type and p type field effect transistors can include forming a first replacement gate having a first gate metal layer adjacent a gate dielectric layer in a first opening in a dielectric region overlying a first active semiconductor region. A second replacement gate including a second gate metal layer can be formed adjacent a gate dielectric layer in a second opening in a dielectric region overlying a second active semiconductor region. At least portions of the first and second gate metal layers can be stacked in a direction of their thicknesses and separated from each other by at least a barrier metal layer. The NFET resulting from the method can include the first active semiconductor region, the source/drain regions therein and the first replacement gate, and the PFET resulting from the method can include the second active semiconductor region, source/drain regions therein and the second replacement gate.

Thin-film transistor, method of manufacturing the same, and method of manufacturing backplane for flat panel display

Provided are a thin-film transistor (TFT), a method of manufacturing the same, and a method of manufacturing a backplane for a flat panel display (FPD). The method of manufacturing the TFT according to an embodiment of the present invention includes forming a gate electrode on a substrate; forming an insulating layer on the substrate to cover the gate electrode; performing a plasma treatment on an upper surface of the insulating layer using a halogen gas; forming an oxide semiconductor layer on the insulating layer and positioned to correspond to the gate electrode; and forming source and drain electrodes on the insulating layer to contact and over portions of the oxide semiconductor layer.

Non-planar FET and manufacturing method thereof

The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.

Structure and method for metal gate stack oxygen concentration control using an oxygen diffusion barrier layer and a sacrificial oxygen gettering layer

A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed.

Semiconductor structure and fabricating method thereof

A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.

LDMOS transistors and associated systems and methods

A lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistor includes a silicon semiconductor structure, a dielectric layer at least partially disposed in a trench of the silicon semiconductor structure in a thickness direction, and a gate conductor embedded in the dielectric layer and extending into the trench in the thickness direction. The dielectric layer and the gate conductor are at least substantially symmetric with respect to a center axis of the trench extending in the thickness direction, as seen when the LDMOS transistor is viewed cross-sectionally in a direction orthogonal to the lateral and thickness directions.

THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME, AND DISPLAY APPARATUS INCLUDING THE THIN FILM TRANSISTOR

A thin film transistor (TFT), a method of manufacturing the TFT, and a display apparatus including the TFT, the TFT including a substrate; a semiconductor layer on the substrate, the semiconductor layer including a channel region, a lightly doped drain (LDD) region, a source region, and a drain region; a gate insulating layer covering the semiconductor layer; a gate electrode overlapping with the channel region such that the gate insulating layer is interposed between the gate electrode and the channel region; and an organic side wall layer on a side surface of the gate electrode, wherein the organic side wall layer includes a silsesquioxane resin.

Replacement gate having work function at valence band edge

Replacement gate stacks are provided, which increase the work function of the gate electrode of a p-type field effect transistor (PFET). In one embodiment, the work function metal stack includes a titanium-oxide-nitride layer located between a lower titanium nitride layer and an upper titanium nitride layer. The stack of the lower titanium nitride layer, the titanium-oxide-nitride layer, and the upper titanium nitride layer produces the unexpected result of increasing the work function of the work function metal stack significantly. In another embodiment, the work function metal stack includes an aluminum layer deposited at a temperature not greater than 420° C. The aluminum layer deposited at a temperature not greater than 420° C. produces the unexpected result of increasing the work function of the work function metal stack significantly.

FLOATING BODY MEMORY CELL HAVING GATES FAVORING DIFFERENT CONDUCTIVITY TYPE REGIONS

A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which alloys the different oxide and gate materials to he fabricated is described.

COMPRESSIVE STRAINED III-V COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICE

A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer.

SEMICONDUCTOR DEVICE INCLUDING MOS TRANSISTOR HAVING SILICIDED SOURCE/DRAIN REGION AND METHOD OF FABRICATING THE SAME

A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

Self-Aligned Contacts for High k/Metal Gate Process Flow

A semiconductor structure is provided that includes a semiconductor substrate having a plurality of gate stacks located on a surface of the semiconductor substrate. Each gate stack includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a conductive metal. A spacer is located on sidewalls of each gate stack and a self-aligned dielectric liner is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy. A contact metal is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner. The structure also includes another contact metal having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks. Methods of forming the semiconductor structure using a replacement gate and a non-replacement gate scheme are also disclosed.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes a transistor including a gate electrode over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, and an oxide insulating film covering the transistor. The multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the oxide insulating film contains more oxygen than that in the stoichiometric composition, and in the transistor, by a bias-temperature stress test, threshold voltage does not change or the amount of the change in a positive direction or a negative direction is less than or equal to 1.0 V, preferably less than or equal to 0.5 V.

Non-planar field effect transistor devices with low-resistance metallic gate structures

Methods are provided to construct field-effect transistors comprising low-resistance metallic gate structures. A field-effect transistor includes a nanosheet stack and a metal gate which covers a gate region of the nanosheet stack. The nanosheet stack includes nanosheet channel layers and an etch stop layer disposed above an upper nanosheet channel layer. The metal gate includes a work function metal which encapsulates the nanosheet channel layers, and a gate electrode disposed above and in contact with the work function metal. An upper surface of the work function metal is recessed to be substantially coplanar with the etch stop layer. The gate electrode has a resistivity which is less than a resistivity of the work function metal. The etch stop layer protects the portion of the work function metal disposed between the etch stop layer and the upper nanosheet channel layer from being etched when recessing the work function metal.

METAL GATE STRUCTURE AND MANUFACTURING METHOD THEREOF

A method of manufacturing a semiconductor structure includes receiving a substrate; patterning a first active region, a second active region and an isolation between the first active region and the second active region over the substrate; disposing an inter-level dielectric (ILD) over the substrate; forming a first gate extended over the first active region, the isolation and the second active region; and forming a second gate over the first active region and the second active region, wherein the second gate includes a first section disposed over the first active region and a second section disposed over the second active region, a portion of the ILD is disposed between the first section and the second section.

Switching device and nonvolatile memory device

A switching device includes: a first layer including a carbon material having a six-member ring network structure; a first electrode electrically connected to a first portion of the first layer; a second electrode electrically connected to a second portion of the first layer and provided apart from the first electrode; a third electrode including a fourth portion provided opposing a third portion between the first portion and the second portion of the first layer; and a second layer provided between the third portion of the first layer and the fourth portion of the third electrode. The second layer includes: a base portion; and a functional group portion. The functional group portion is provided between the base portion and the first layer. The functional group portion is bonded to the base portion. A ratio of sp2-bonded carbon and sp3-bonded carbon of the first layer is changeable by a voltage applied between the first layer and the third electrode.

III-nitride semiconductor device with stepped gate trench and process for its manufacture

A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same.

Electric-electronic device including polyimide thin film

An electric-electronic device including a polyimide thin film is disclosed, said polyimide thin film having a thickness of not more than 1000 Å and a dielectric breakdown strength of not less than 1 x 106V/cm, and an electric-electronic device comprising a polyimide thin film and the group III-V or II-VI compound semiconductor is also disclosed. The device has excellent properties ascribed to high heat resistance, mechanical strength, chemical resistance and insulating properties of the polyimide thin film.

MANUFACTURE OF SEMICONDUCTOR DEVICE

化合物半導体装置の製造方法

SEMICONDUCTOR DEVICE

ПОЛЕВОЙ ТРАНЗИСТОР

Использование: изобретение может быть использовано в микроэлектронике. Сущность изобретения: в полевом транзисторе, содержащем электрод истока, электрод стока, изолятор затвора, электрод затвора и активный слой, активный слой содержит аморфный оксид, в котором концентрация электронных носителей ниже 1018/см3 и в котором подвижность электронов увеличивается с увеличением концентрации электронных носителей. По меньшей мере, один из электрода истока, электрода стока и электрода затвора является прозрачным для видимого света, при этом ток, протекающий между электродом истока и электродом стока, если к электроду затвора не приложено напряжение, не превышает 10 микроампер. Транзисторы согласно изобретению обладают улучшенными характеристиками в отношении, по меньшей мере, одного из свойств: прозрачность, электрические свойства тонкопленочного транзистора, свойства пленки, изолирующей затвор, предотвращение тока утечки и адгезивность между активным слоем и подложкой. 9 н. и 12 з.п. ф-лы, 12 ил ...

ПОЛЕВОЙ ТРАНЗИСТОР

... 1. Полевой транзистор, содержащий электрод истока, электрод стока, изолятор затвора, электрод затвора и активный слой, причем активный слой содержит аморфный оксид, в котором концентрация электронных носителей ниже 10/см, или аморфный оксид, в котором подвижность электронов увеличивается с увеличением концентрации электронных носителей; ипо меньшей мере, один из электрода истока, электрода стока и электрода затвора является прозрачным для видимого света.2. Полевой транзистор по п.1, дополнительно содержащий металлическую проводку соединенную, по меньшей мере, с одним из электрода истока, электрода стока и электрода затвора.3. Полевой транзистор по п.1, в котором аморфный оксид представляет собой оксид, содержащий, по меньше мере, одно из In, Zn или Sn, или оксид, содержащий In, Zn и Ga.4. Полевой транзистор, содержащий электрод истока, электрод стока, изолятор затвора, электрод затвора и активный слой, причем активный слой содержит аморфный оксид, в котором концентрация электронных носителей ...

MOSFET-Kanalzone und Herstellungsverfahren

Capacitor structure used in an electrical insulator comprises an insulating layer containing praseodymium oxide mixed with titanium or titanium nitride arranged between a first electrode and a second electrode

Capacitor structure comprises an insulating layer containing praseodymium oxide mixed with titanium or titanium nitride arranged between a first electrode and a second electrode. An independent claim is also included for a process for the production of a capacitor structure.

Transistorstruktur, Verfahren zur Herstellung einer Transistorstruktur, Kraftmesssystem

Eine Transistorstruktur umfasst einen ersten Anschlussbereich, einen zweiten Anschlussbereich und einen dazwischenliegenden Kanalbereich in einem Halbleitersubstrat. Des Weiteren umfasst die Transistorstruktur eine dem Kanalbereich zugeordnete Steuerelektrode, wobei die Steuerelektrode einen unter einer Krafteinwirkung elastisch auslenkbaren, von dem Kanalbereich beabstandeten Steuerelektrodenabschnitt aufweist. Der Abstand zwischen dem Steuerelektrodenabschnitt und dem Kanalbereich wird basierend auf der Krafteinwirkung geändert.

Halbleitereinrichtung mit MOS-Transistor und Verfahren zum Herstellen derselben

Method for manufacturing silicon carbide semiconductor device

In a silicon carbide MOSFET, interface state generated at an interface between a silicon carbide layer and a gate insulating film cannot be reduced sufficiently, and mobility of a carrier is decreased. To solve this problem, a silicon carbide semiconductor device according to this invention includes a substrate introduction step of introducing a substrate, which includes a silicon carbide layer on which a gate insulating film is formed, in a furnace, and a heating step of heating the furnace having the substrate introduced therein while introducing nitrogen monoxide and nitrogen therein, wherein, in the heating step, nitrogen is reacted to nitride an interface between the gate insulating film and the silicon carbide layer.

High-k gate dielectric oxide

A dielectric such as a gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from elements such as zirconium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.

Self-aligned silicidation for replacement gate process

A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

offset gate semiconductor device

An offset gate semiconductor device includes a substrate and an isolation feature formed in the substrate. An active region is formed in the substrate substantially adjacent to the isolation feature. An interface layer is formed on the substrate over the isolation feature and the active region. A polysilicon layer is formed on the interface layer over the isolation feature and the active region. A trench being formed in the polysilicon layer over the isolation feature. The trench extending to the interface layer. A fill layer is formed to line the trench and a metal gate formed in the trench.

Method of forming a non-volatile electron storage memory and the resulting device

The invention provides a method of forming an electron memory storage device and the resulting device. The device comprises a gate structure which, in form, comprises a first gate insulating layer formed over a semiconductor substrate, a self-forming electron trapping layer of noble metal nano-crystals formed over the first gate insulating layer, a second gate insulating layer formed over the electron trapping layer, a gate electrode formed over the second gate insulating layer, and source and drain regions formed on opposite sides of the gate structure.

Method of manufacturing semiconductor device using acid diffusion

A method of manufacturing a semiconductor device includes forming a resist pattern on a first region on a substrate, bringing a descum solution including an acid source into contact with the resist pattern and with a second region of the substrate, decomposing resist residues remaining on the second region of the substrate by using acid obtained from the acid source in the descum solution and removing the decomposed resist residues and the descum solution from the substrate.

Vapor deposition of metal oxides, silicates and phosphates, and silicon dioxide

Metal silicates or phosphates are deposited on a heated substrate by the reaction of vapors of alkoxysilanols or alkylphosphates along with reactive metal amides, alkyls or alkoxides. For example, vapors of tris(tert-butoxy)silanol react with vapors of tetrakis(ethylmethylamido)hafnium to deposit hafnium silicate on surfaces heated to 300° C. The product film has a very uniform stoichiometry throughout the reactor. Similarly, vapors of diisopropylphosphate react with vapors of lithium bis(ethyldimethylsilyl)amide to deposit lithium phosphate films on substrates heated to 250° C. Supplying the vapors in alternating pulses produces these same compositions with a very uniform distribution of thickness and excellent step coverage.

Graded high germanium compound films for strained semiconductor devices

Embodiments of an apparatus and methods for providing a graded high germanium compound region are generally described herein. Other embodiments may be described and claimed.

MOS TRANSISTORS INCLUDING SiON GATE DIELECTRIC WITH ENHANCED NITROGEN CONCENTRATION AT ITS SIDEWALLS

A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric sidewalls are revealed by the patterning. A supplemental silicon oxide layer is formed on the exposed SiON sidewalls followed by nitriding. After nitriding, a post nitridation annealing (PNA) forms an annealed N-enhanced SiON gate dielectric layer including N-enhanced SiON sidewalls, wherein along lines of constant thickness a N concentration at the N-enhanced SiON sidewalls is ≧ the N concentration in a bulk of the annealed N-enhanced SiON gate layer −2 atomic %. A source and drain region on opposing sides of the gate stack are formed to define a channel region under the gate stack.

Non-volatile memory device and sensing method for forming the same

A non-volatile memory device and a method for forming the same are disclosed, which relate to a ferroelectric memory device having non-volatile characteristics. The non-volatile memory device includes a control gate configured to receive a read voltage, an insulation film formed over the control gate, a metal layer formed over the insulation film, configured to include a channel region, and a drain region and source region at both ends of the channel region, a ferroelectric layer formed over the channel region of the metal layer, and a program and read gate formed over the ferroelectric layer. A write operation of data corresponding to a resistance state of the channel region is performed by changing polarity of the ferroelectric layer in response to a voltage applied to the program and read gate, the drain and source regions, and the control gate. A read operation of data is performed by sensing a current value changing with a polarity state of the ferroelectric layer on the condition that the read voltage is input to the control gate and a sensing bias voltage is input to one of the drain region and the source region.

Nonvolatile Semiconductor Memory Device Having Multi-Layered Oxide/(OXY) Nitride Film as Inter-Electrode Insulating Film and Manufacturing Method Thereof

A nonvolatile semiconductor memory device includes a first insulator, first conductor, element isolation insulator, second insulator and second conductor. The first insulator is formed on the main surface of a substrate and the first conductor is formed on the first insulator. The element isolation insulator is filled into at least part of both side surfaces of the first insulator in a gate width direction thereof and both side surfaces of the first conductor in a gate width direction thereof and is so formed that the upper surface thereof will be set with height between those of the upper and bottom surfaces of the first conductor. The second insulator includes a three-layered insulating film formed of a silicon oxide film, a silicon oxynitride film and a silicon oxide film formed on the first conductor and element isolation insulator. The second conductor is formed on the second insulator.

Methods of forming memory cells, memory cells, and semiconductor devices

A memory device and method of making the memory device. Memory device may include a storage transistor at a surface of a substrate. The storage transistor comprises a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source/drain region and a word line is connected to the gate structure.

Method and structure for forming high-k/metal gate extremely thin semiconductor on insulator device

A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers.

Epitaxy Silicon on Insulator (ESOI)

Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a second dielectric layer on the second epitaxial layer. A semiconductor fabrication method comprises forming a dielectric layer over a substrate and surrounding a device fabrication region in the substrate with an isolation trench extending through the dielectric layer. The method also includes filling the isolation trench with a first epitaxial layer and forming a second epitaxial layer over the device fabrication region and over the first epitaxial layer. Then a portion of the first epitaxial layer is replaced with an isolation dielectric, and then a device such as a transistor is formed second epitaxial layer within the device fabrication region.

Semiconductor device manufacturing method

A semiconductor device manufacturing method includes: removing an insulating film on a semiconductor substrate by etching and subsequently oxidizing a surface of the semiconductor substrate by using a liquid oxidation agent without exposing this surface to an atmosphere, thereby forming a first insulating film containing an oxide of a constituent element of the semiconductor substrate on the surface of the semiconductor substrate; forming a second insulating film containing an aluminum oxide on the first insulating film; forming a third insulating film containing a rare earth oxide on the second insulating film; forming a high-k insulating film on the third insulating film; introducing nitrogen into the high-k insulating film to thereby make it a fourth insulating film; and conducting heat treatment to change the first through third insulating films into a insulating film made of a mixture containing aluminum, a rare earth element, the constituent element of the semiconductor substrate, and oxygen.

Semiconductor device production method

A semiconductor device production method includes: forming a gate insulating film on the p-type region of a semiconductor substrate; forming a first aluminum oxide film with an oxygen content lower than stoichiometric composition on the gate insulating film; forming a tantalum-nitrogen-containing film that contains tantalum and nitrogen on the first aluminum oxide film; forming an electrically conductive film on the tantalum-nitrogen-containing film; patterning the electrically conductive film to form a gate electrode; injecting n-type impurities into the p-type region using the gate electrode as a mask; and carrying out heat treatment after the formation of the tantalum-nitrogen-containing film.

Nonvolatile semiconductor memory

According to one embodiment, in a nonvolatile semiconductor memory in which a charge store layer is formed on a tunnel insulating film formed on a channel region of a semiconductor substrate, a first nanoparticle layer containing first conductive nanoparticles is formed on the channel side, and a second nanoparticle layer containing a plurality of second conductive nanoparticles having an average particle size larger than the first conductive nanoparticles is formed on the charge store layer side. An average energy value ΔE 1 required for charging one electron in the first conductive nanoparticle is smaller than an average energy value ΔE required for charging one electron in the second conductive nanoparticle, and a difference between ΔE 1 and ΔE is larger than a heat fluctuation energy (k B T).

Conductive layers for hafnium silicon oxynitride

Electronic apparatus and methods of forming the electronic apparatus include HfSiON for use in a variety of electronic systems. In various embodiments, conductive material is coupled to a dielectric containing HfSiON, where such conductive material may include one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum.

Dielectric stack

A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness T FD . A capping layer is formed on the substrate having a formed thickness T FC . Forming the capping layer consumes a desired amount of the device layer to cause the thickness of the device layer to be about the target thickness T TD . The thickness of the capping layer is adjusted from T FC to about a target thickness T TC .

Methods of Manufacturing a Semiconductor Device

There is provided a method of manufacturing a semiconductor device. In the method, a gate insulation layer including a high-k dielectric material is formed on a substrate. An etch stop layer is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask including amorphous silicon is formed on the metal layer. The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern.

Methods of Forming Gates of Semiconductor Devices

Methods of forming gates of semiconductor devices are provided. The methods may include forming a first recess in a first substrate region having a first conductivity type and forming a second recess in a second substrate region having a second conductivity type. The methods may also include forming a high-k layer in the first and second recesses. The methods may further include providing a first metal on the high-k layer in the first and second substrate regions, the first metal being provided within the second recess. The methods may additionally include removing at least portions of the first metal from the second recess while protecting materials within the first recess from removal. The methods may also include, after removing at least portions of the first metal from the second recess, providing a second metal within the second recess.

Programmable Gate III-Nitride Power Transistor

A III-nitride semiconductor device which includes a charged floating gate electrode.

Strained structure of a p-type field effect transistor

In a p-type field effect transistor, a pair of spacers are formed over the top surface of a substrate. A channel recess cavity includes an indentation in the substrate top surface between the pair of spacers. A gate stack has a bottom portion in the channel recess cavity and a top portion extending outside the channel recess cavity. A source/drain (S/D) recess cavity has a bottom surface and sidewalls below the substrate top surface. The S/D recess cavity has a portion extending below the gate stack. A strained material is filled the S/D recess cavity

Methods of forming gate dielectric material

A method of forming gate dielectric material includes forming a silicon oxide gate layer over a substrate. The silicon oxide gate layer is treated with a first ozone-containing gas. After treating the silicon oxide gate layer, a high dielectric constant (high-k) gate dielectric layer is formed over the treated silicon oxide gate layer.

Method of fabricating semiconductor device

A method of fabricating a semiconductor device includes sequentially forming a first gate insulating layer and a second gate insulating layer on a substrate, implanting impurity ions into the substrate and performing a first thermal process for activating the impurity ions to form a source and drain region, and forming a third gate insulating layer on the substrate after the first thermal process has been completed.

Metal-insulator-semiconductor tunneling contacts

A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator.

Replacement Gate Having Work Function at Valence Band Edge

Replacement gate stacks are provided, which increase the work function of the gate electrode of a p-type field effect transistor (PFET). In one embodiment, the work function metal stack includes a titanium-oxide-nitride layer located between a lower titanium nitride layer and an upper titanium nitride layer. The stack of the lower titanium nitride layer, the titanium-oxide-nitride layer, and the upper titanium nitride layer produces the unexpected result of increasing the work function of the work function metal stack significantly. In another embodiment, the work function metal stack includes an aluminum layer deposited at a temperature not greater than 420° C. The aluminum layer deposited at a temperature not greater than 420° C. produces the unexpected result of increasing the work function of the work function metal stack significantly.

Semiconductor structures and methods of manufacture

Semiconductor structures and methods of manufacture semiconductors are provided which relate to transistors. The method of forming a transistor includes thermally annealing a selectively patterned dopant material formed on a high-k dielectric material to form a high charge density dielectric layer from the high-k dielectric material. The high charge density dielectric layer is formed with thermal annealing-induced electric dipoles at locations corresponding to the selectively patterned dopant material.

Metal gate transistor, integrated circuits, systems, and fabrication methods thereof

A method of forming an integrated circuit structure includes providing a gate strip in an inter-layer dielectric (ILD) layer. The gate strip comprises a metal gate electrode over a high-k gate dielectric. An electrical transmission structure is formed over the gate strip and a conductive strip is formed over the electrical transmission structure. The conductive strip has a width greater than a width of the gate strip. A contact plug is formed above the conductive strip and surrounded by an additional ILD layer.

METHOD FOR FABRICATING A GaN-BASED THIN FILM TRANSISTOR

A method for fabricating a GaN-based thin film transistor includes: forming a semiconductor epitaxial layer on a substrate, the semiconductor epitaxial layer having a n-type GaN-based semiconductor material; forming an insulating layer on the semiconductor epitaxial layer; forming an ion implanting mask on the insulating layer, the ion implanting mask having an opening to partially expose the insulating layer; ion-implanting a p-type impurity through the opening and the insulating layer to form a p-doped region in the n-type GaN-based semiconductor material, followed by removing the insulating layer and the ion implanting mask; forming a dielectric layer on the semiconductor epitaxial layer; partially removing the dielectric layer; forming source and drain electrodes; and forming a gate electrode.

Retention in nvm with top or bottom injection

Retention of charges in a nonvolatile memory (NVM) cell having a nitride-based injector (such as SiN, SIRN, SiON) for facilitating injection of holes into a charge-storage layer (for NROM, nitride) of a charge-storage stack (for NROM, ONO) may be improved by providing an insulating layer (for NROM, oxide) between the charge-storage layer and the injector has a thickness of at least 3 nm. Top and bottom injectors are disclosed. Methods of operating NVM cells are disclosed. The NVM cell may be NROM, SONOS, or other oxide-nitride technology NVM cells such as SANOS, MANOS, TANOS.

Semiconductor device

A semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes a first gate insulating film which is formed on a first active region of a semiconductor substrate and has a first high dielectric constant film, and a first gate electrode formed on the first gate insulating film. The second MIS transistor includes a second gate insulating film which is formed on a second active region of the semiconductor substrate and has a second high dielectric constant film, and a second gate electrode formed on the second gate insulating film. The second high dielectric constant film contains first adjusting metal. The first high dielectric constant film has a higher nitrogen concentration than the second high dielectric constant film, and does not contain the first adjusting metal.

Semiconductor device

A semiconductor device of one embodiment, including the semiconductor layer including a III-V group nitride semiconductor; a groove portion formed in the semiconductor layer; the gate insulating film formed at least on a bottom surface of the groove portion, the gate insulating film being a stacked film of a first insulating film and a second insulating film of which dielectric constant is higher than that of the first insulating film; the gate electrode formed on the gate insulating film; and a source electrode and a drain electrode formed on the semiconductor layer across the gate electrode, in which the second insulating film is selectively formed only under the gate electrode.

Asymmetric fet including sloped threshold voltage adjusting material layer and method of fabricating same

A method of forming a semiconductor structure is provided. The method includes providing a structure including at least one dummy gate region located on a surface of a semiconductor substrate and a dielectric material layer located on sidewalls of the at least one dummy gate region. Next, a portion of the dummy gate region is removed exposing an underlying high k gate dielectric. A sloped threshold voltage adjusting material layer is then formed on an upper surface of the high k gate dielectric, and thereafter a gate conductor is formed atop the sloped threshold voltage adjusting material layer.

Semiconductor device

A source region and a drain region are disposed in a substrate. A gate insulating film is disposed on the substrate. A gate electrode is disposed on the gate insulating film. The gate electrode may include a first gate portion adjacent to the source region and a second gate portion adjacent to the drain region. The first and second gate portions have different work functions from each other.

Semiconductor Device, An Electronic Device and an Electronic Apparatus

A semiconductor device 1 includes: a base 2 mainly formed of a semiconductor material; a gate electrode 5 ; and a gate insulating film 3 provided between the base 2 and the gate electrode 5 . The gate insulating film 3 is formed of an insulative inorganic material containing silicon, oxygen and element X other than silicon and oxygen as a main material. The gate insulating film 3 is provided in contact with the base 2 , and contains hydrogen atoms. The gate insulating film 3 has a region where A and B satisfy the relation: B/A is 10 or less in the case where the total concentration of the element X in the region is defined as A and the total concentration of hydrogen in the region is defined as B. Further, the region is at least apart of the gate insulating film 3 in the thickness direction thereof.

Lanthanide dielectric with controlled interfaces

Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film.

High-k/metal gate stack using capping layer methods, ic and related transistors

Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.

Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, and Process to Fabricate Same

A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer, selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.

High-K Metal Gate Electrode Structures Formed by a Replacement Gate Approach Based on Superior Planarity of Placeholder Materials

When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, superior process uniformity may be achieved by implementing at least one planarization process after the deposition of the placeholder material, such as the polysilicon material, and prior to actually patterning the gate electrode structures.

Methods of forming an insulating metal oxide

A dielectric containing an insulating metal oxide film having multiple metal components and a method of fabricating such a dielectric produce a reliable dielectric for use in a variety of electronic devices. Embodiments include a titanium aluminum oxide film structured as one or more monolayers. Embodiments also include structures for capacitors, transistors, memory devices, and electronic systems with dielectrics containing a titanium aluminum oxide film.

Semiconductor device and manufacturing method of the same

A semiconductor device of an embodiment at least includes: a SiC substrate; and a gate insulating film formed on the SiC substrate, wherein at an interface between the SiC substrate and the gate insulating film, some of elements of both of or one of Si and C in an outermost surface of the SiC substrate are replaced with at least one type of element selected from nitrogen, phosphorus, and arsenic.

Method of producing semiconductor device and semiconductor device

A method of producing a semiconductor device, includes: forming a semiconductor layer on a substrate; forming an a recess in the semiconductor layer by dry etching with a gas containing fluorine components, the recess having an opening portion on the surface of the semiconductor layer; forming a fluorine-containing region by heating the semiconductor layer and thus diffusing, into the semiconductor layer, the fluorine components attached to side surfaces and a bottom surface of the recess; forming an insulating film on an inner surface of the recess and on the semiconductor layer; and forming an electrode on the insulating film in a region in which the recess is formed.

Sealing structure for high-k metal gate and method of making

The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

Semiconductor device and method of manufacturing the same

A p-type MIS transistor Qp arranged in a pMIS region Rp of a silicon substrate 1 includes a pMIS gate electrode GEp formed so as to interpose a pMIS gate insulating film GIp formed of a first insulating film z 1 and a first high-dielectric film hk 1 , and an n-type MIS transistor Qn arranged in an nMIS region Rn includes an nMIS gate electrode GEn formed so as to interpose an nMIS gate insulating film GIn formed of a first insulating film z 1 and a second high-dielectric film hk 2. The first high-dielectric film hk 1 is formed of an insulating film mainly made of hafnium and oxygen with containing aluminum, titanium, or tantalum. Also, the second high-dielectric film hk 2 is formed of an insulating film mainly made of hafnium, silicon, and oxygen with containing an element of any of group Ia, group IIa, and group IIIa.

Electrical Fuse Formed By Replacement Metal Gate Process

A method is provided for fabricating an electrical fuse and a field effect transistor having a metal gate which includes removing material from first and second openings in a dielectric region overlying a substrate, wherein the first opening is aligned with an active semiconductor region of the substrate, and the second opening is aligned with an isolation region of the substrate, and the active semiconductor region including a source region and a drain region adjacent edges of the first opening. An electrical fuse can be formed which has a fuse element filling the second opening, the fuse element being a monolithic region of a single conductive material being a metal or a conductive compound of a metal. A metal gate can be formed which extends within the first opening to define a field effect transistor (“FET”) which includes the metal gate and the active semiconductor region.

Semiconductor device exhibiting reduced parasitics and method for making same

A semiconductor device includes a substrate and a gate stack disposed on the substrate. An upper layer of the gate stack is a metal gate conductor and a lower layer of the gate stack is a gate dielectric. A gate contact is in direct contact with the metal gate conductor.

Method for Metal Deposition Using Hydrogen Plasma

Methods for formation and treatment of pure metal layers using CVD and ALD techniques are provided. In one or more embodiments, the method includes forming a metal precursor layer and treating the metal precursor layer to a hydrogen plasma to reduce the metal precursor layer to form a metal layer. In one or more embodiments, treating the metal precursor layer includes exposing the metal precursor layer to a high frequency-generated hydrogen plasma. Methods of preventing a hydrogen plasma from penetrating a metal precursor layer are also provided.

Semiconductor device and manufacturing method of the semiconductor device

A semiconductor device includes a semiconductor substrate, a device region including first and second parts, first and second gate electrodes formed in the first and the second parts, first and second source regions, first and second drain regions, first, second, third, and fourth embedded isolation film regions formed under the first source, the first drain, the second source, and the second drain regions, respectively. Further, the first drain region and the second source region form a single diffusion region, the second and the third embedded isolation film regions form a single embedded isolation film region, an opening is formed in a part of the single diffusion region so as to extend to the second and the third embedded isolation film regions, and the opening is filled with an isolation film.

Manufacturing method of gate dielectric layer

A manufacturing method of a gate dielectric layer that includes a nitride layer and an oxide layer is provided. A substrate is provided. A nitridation treatment is performed to form the nitride layer on the substrate. An oxidation treatment is performed subsequent to the formation of the nitride layer to form the oxide layer between the nitride layer and the substrate.

Manufacturing method of gate dielectric layer

A manufacturing method of a gate dielectric layer is provided. An oxidation treatment is performed to form an oxide layer on a substrate. A nitridation treatment is performed to form a nitride layer on the oxide layer. An annealing treatment is performed in a mixing gas of N 2 and O 2 , where the temperature of the annealing treatment is 900° C. to 950° C., the pressure of the annealing treatment is 5 Torr to 10 Torr, and the content ratio of the N 2 to O 2 is 0.5 to 0.8.

Method of depositing gate dielectric, method of preparing mis capacitor, and mis capacitor

The present invention relates to a method of depositing a gate dielectric, a method of preparing a MIS capacitor and the MIS capacitor. In the method of depositing the gate dielectric, a semiconductor substrate surface is preprocessed with oxygen plasma and nitrogen-containing plasma to form a nitrogen-containing oxide layer thereon. Then, a high-k gate dielectric layer is grown on the nitrogen-containing oxide layer surface by a plasma-enhanced atomic layer deposition process, and the oxide layer converts during the gate dielectric layer growth process into a buffer layer of a dielectric constant higher than SiO 2 . Then, a metal electrode is formed on both an upper layer and a lower layer of the thus-formed semiconductor construction, so that a MIS capacitor is prepared. According to the present invention, the formation of the buffer layer enables the interface characteristics between semiconductor materials and high-k gate dielectric layers to be improved effectively, equivalent oxide thickness (EOT) to be reduced and electrical properties to be enhanced.

Phase transition memories and transistors

In one embodiment there is set forth a method comprising providing a semiconductor structure having an electrode, wherein the providing includes providing a phase transition material region and wherein the method further includes imparting energy to the phase transition material region to induce a phase transition of the phase transition material region. By inducing a phase transition of the phase transition material region, a state of the semiconductor structure can be changed. There is further set forth an apparatus comprising a structure including an electrode and a phase transition material region, wherein the apparatus is operative for imparting energy to the phase transition material region to induce a phase transition of the phase transition material region without the phase transition of the phase transition material region being dependent on electron transport through the phase transition material region.

Structures and Methods of Improving Reliability of Non-Volatile Memory Devices

In one example, the memory device disclosed herein includes a gate insulation layer and a charge storage layer positioned above the gate insulation layer, wherein the charge storage layer has a first width. The device further includes a blocking insulation layer positioned above the charge storage layer and a gate electrode positioned above the blocking insulation layer, wherein the gate electrode has a second width that is greater than the first width. An illustrative method disclosed herein includes forming a gate stack for a memory device, wherein the gate stack includes a gate insulation layer, an initial charge storage layer, a blocking insulation layer and a gate electrode, and wherein the initial charge storage layer has a first width. The method further includes performing an etching process to selectively remove at least a portion of the initial charge storage layer so as to produce a charge storage layer having a second width that is less than the first width of the initial charge storage layer.

Semiconductor device and method of manufacturing the same

A semiconductor device having a buried gate is provided. The semiconductor device is formed in a structure in which a plurality of contacts having small step differences are stacked without forming a metal contact applying an operation voltage to the buried gate in a single contact and a contact pad is formed between the contacts so that failure due to misalignment can be prevented without a separate additional process for forming the contacts.

Methods for Manufacturing High Dielectric Constant Films

Provided are methods for depositing a high-k dielectric film on a substrate. The methods comprise annealing a substrate after cleaning the surface to create dangling bonds and depositing the high-k dielectric film on the annealed surface.

Semiconductor device and manufacturing method thereof

A semiconductor device and its manufacturing method are disclosed. The semiconductor device comprises a gate, and source and drain regions on opposite sides of the gate, wherein a portion of a gate dielectric layer located above the channel region is thinner than a portion of the gate dielectric layer located at the overlap region of the drain and the gate. The thicker first thickness portion may ensure that the device can endure a higher voltage at the drain to gate region, while the thinner second thickness portion may ensure excellent performance of the device.

Semiconductor device having gradient doping profile

The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate over a substrate. The method includes performing a first implantation process to form a first doped region in the substrate, the first doped region being adjacent to the gate. The method includes performing a second implantation process to form a second doped region in the substrate, the second doped region being formed farther away from the gate than the first doped region, the second doped region having a higher doping concentration level than the first doped region. The method includes removing portions of the first and second doped regions to form a recess in the substrate. The method includes epitaxially growing a third doped region in the recess, the third doped region having a higher doping concentration level than the second doped region.

Communication

An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness t C ; and a dielectric film of thickness t g in contact with a surface of the channel. Further, the film comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.

Method for fabricating semiconductor device

A method for fabricating a semiconductor device includes the following steps. Firstly, a dummy gate structure having a dummy gate electrode layer is provided. Then, the dummy gate electrode layer is removed to form an opening in the dummy gate structure, thereby exposing an underlying layer beneath the dummy gate electrode layer. Then, an ammonium hydroxide treatment process is performed to treat the dummy gate structure. Afterwards, a metal material is filled into the opening.

Semiconductor device with increased channel mobility and dry chemistry processes for fabrication thereof

Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.

Gate dielectric layer forming method

A gate dielectric layer forming method is applied to a fabrication process of a metal-oxide-semiconductor field-effect transistor. The gate dielectric layer forming method includes the following steps. Firstly, a substrate is provided. Then, an interlayer is formed on the substrate. Then, a high-k dielectric layer is formed on the interlayer. A nitridation process is performed to convert the high-k dielectric layer into a nitridated high-k dielectric layer. A first low temperature post-nitridation annealing process is performed to treat the nitridated high-k dielectric layer with a first gas. Afterwards, a second low temperature post-nitridation annealing process is performed to treat the nitridated high-k dielectric layer with a second gas.

Semiconductor structures including bodies of semiconductor material, devices including such structures and related methods

Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. The bodies may be electrically coupled by one or more conductive structures, which may be used as an interconnect structure to electrically couple components of memory devices. By providing isolation between the bodies, the semiconductor structure provides the properties of a conventional SOI substrate (e.g., high speed, low power, increased device density and isolation) while substantially reducing fabrication acts and costs associated with such SOI substrates. Additionally, the semiconductor structures of the present disclosure provide reduced parasitic coupling and current leakage due to the isolation of the bodies by the intervening dielectric material.

Fabricating method of mos transistor, fin field-effect transistor and fabrication method thereof

A fabricating method of a MOS transistor includes the following steps. A substrate is provided. A gate dielectric layer is formed on the substrate. A nitridation process containing nitrogen plasma and helium gas is performed to nitride the gate dielectric layer. A fin field-effect transistor and fabrication method thereof are also provided.

Transistor, Semiconductor Device, and Method for Manufacturing the Same

The invention provides a transistor, a semiconductor device and a method for manufacturing the same. The method for manufacturing a transistor comprises: defining an active area on a semiconductor substrate, forming a dummy gate stack on the active area, primary spacers surrounding said dummy gate stack, and an insulating layer surrounding said primary spacers, and forming source/drain regions embedded in said active area; removing the dummy gate in said dummy gate stack to form a first recessed portion surrounded by the primary spacers; filling Cu simultaneously in said first recessed portion and in the source/drain contact holes penetrating said insulating layer to form a gate and source/drain contacts. By filling the gate and the source/drain contact holes with the metal Cu simultaneously in the Gate Last structure, the gate serial resistance and the source/drain contact holes resistance in the Gate Last process are decreased. Besides, the effect of metal filling is improved in small scale, and the process complexity and difficulty is efficiently decreased.

Digital oxide deposition of sio2 layers on wafers

Novel silicon dioxide and silicon nitride deposition methods are generally disclosed. In one embodiment, the method includes depositing silicon on the surface of a substrate having a temperature of between about 65° C. and about 350° C. The heated substrate is exposed to a silicon source that is substantially free from an oxidizing agent. The silicon on the surface is then oxidized with an oxygen source that is substantially free from a silicon source. As a result of oxidizing the silicon, a silicon oxide layer forms on the surface of the substrate. Alternatively, or in additionally, a nitrogen source can be provided to produce silicon nitride on the surface of the substrate.

Gate dielectric of semiconductor device

A method of fabricating a semiconductor device having a different gate structure in each of a plurality of device regions is described. The method may include a replacement gate process. The method includes forming a hard mask layer on oxide layers formed on one or more regions of the substrate. A high-k gate dielectric layer is formed on each of the first, second and third device regions. The high-k gate dielectric layer may be formed directly on the hard mask layer in a first and second device regions and directly on an interfacial layer formed in a third device region. A semiconductor device including a plurality of devices (e.g., transistors) having different gate dielectrics formed on the same substrate is also described.

Manufacturing method for metal gate

A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate.

Replacement source/drain finfet fabrication

A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.

Split-gate flash memory exhibiting reduced interference

A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.

Low Threshold Voltage And Inversion Oxide Thickness Scaling For A High-K Metal Gate P-Type MOSFET

A structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in T inv and V t of the pFET, while scaling Tiny and maintaining Vt for the nFET, resulting in the V t of the pFET becoming closer to the V t of a similarly constructed nFET with scaled T inv values.

Mosfet gate electrode employing arsenic-doped silicon-germanium alloy layer

A stack of a gate dielectric layer, a metallic material layer, an amorphous silicon-germanium alloy layer, and an amorphous silicon layer is deposited on a semiconductor substrate. In one embodiment, the amorphous silicon-germanium alloy layer is deposited as an in-situ amorphous arsenic-doped silicon-germanium alloy layer. In another embodiment, the amorphous silicon-germanium alloy layer is deposited as intrinsic semiconductor material layer, and arsenic is subsequently implanted into the amorphous silicon-germanium alloy layer. The stack is patterned and annealed to form a gate electrode.

Method for fabricating a damascene self-aligned ferroelectric random access memory (f-ram) device structure employing reduced processing steps

Disclosed is a novel non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM device structure on a planar surface using a reduced number of masks and etching steps.

Methods of Forming a Dielectric Cap Layer on a Metal Gate Structure

Disclosed herein are various methods of forming metal-containing insulating material regions on a metal layer of a gate structure of a semiconductor device. In one example, the method includes forming a gate structure of a transistor, the gate structure comprising at least a first metal layer, and forming a first metal-containing insulating material region in the first metal layer by performing a gas cluster ion beam process using to implant gas molecules into the first metal layer.

Method for Manufacturing a Low Defect Interface Between a Dielectric and a III-V Compound

The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance.

Semiconductor device

A semiconductor device comprises an MIS field effect transistor including a channel region made of p-conductive silicon, a gate insulating film including a first insulating film having dielectric constant higher than dielectric constant of silicon dioxide, and a gate electrode. The gate electrode includes a first metal film formed on the gate insulating film and having a work function greater than a work function of intrinsic semiconductor silicon, and a p-conductive silicon film formed on the first metal film and in contact with the first metal film.

Buried Gate Transistor

An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source/drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess.

Plasma cvd method, method for forming silicon nitride film and method for manufacturing semiconductor device

A plasma processing apparatus generates plasma by introducing microwaves into a processing chamber by using a planar antenna having a plurality of slots. By using the plasma processing apparatus, a nitrogen containing gas and a silicon containing gas introduced into the processing chamber are brought into the plasma state, and at the time of depositing by using the plasma a silicon nitride film on the surface of the a substrate to be processed, stress to the silicon nitride film to be formed is controlled by the combination of the type and the processing pressure of the nitrogen containing gas.

Semiconductor device

A semiconductor device including a high resistance layer formed on a substrate, the high resistance layer being formed with a semiconductor material doped with an impurity element that makes the semiconductor material highly resistant; a multilayer intermediate layer formed on the high resistance layer; an electron transit layer formed with a semiconductor material on the multilayer intermediate layer; and an electron supply layer formed with a semiconductor material on the electron transit layer, wherein the multilayer intermediate layer is formed with a multilayer film in which a GaN layer and an AlN layer are alternately laminated.

Semiconductor device and method of manufacturing the same, and power supply apparatus

A semiconductor device includes a substrate; a first nitride semiconductor layer provided over the substrate and having a nitride-polar surface; a gate electrode provided over the first nitride semiconductor layer; and a semiconductor layer provided on the first nitride semiconductor layer and only under the gate electrode, and exhibiting a polarization.

Semiconductor device

A semiconductor device according to an embodiment includes: a first transistor including a gate connected to a first interconnection, a first source, and a first drain, one of the first source and the first drain being connected to a second interconnection; and a second transistor including a gate structure, a second source, and a second drain, one of the second source and second drain being connected to a third interconnection and the other of the second source and second drain being connected to a fourth interconnection. The gate structure includes a gate insulation film, a gate electrode, and a threshold-modulating film provided between the gate insulation film and the gate electrode to modulate a threshold voltage, the other of the first source and first drain of the first transistor is connected to the gate electrode.

Compound semiconductor device and method for fabricating the same

A compound semiconductor multilayer structure is formed on a Si substrate. The compound semiconductor multilayer structure includes an electrode transit layer, an electrode donor layer formed above the electron transit layer, and a cap layer formed above the electron donor layer. The cap layer contains a first crystal polarized in the same direction as the electron transit layer and the electron donor layer and a second crystal polarized in the direction opposite to the polarization direction of the electron transit layer and the electron donor layer.

Deposited Material and Method of Formation

A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period.

TECHNIQUE FOR REDUCING TOPOGRAPHY-RELATED IRREGULARITIES DURING THE PATTERNING OF A DIELECTRIC MATERIAL IN A CONTACT LEVEL OF CLOSELY SPACED TRANSISTORS

In a dual stress liner approach, the surface conditions after the patterning of a first stress-inducing layer may be enhanced by appropriately designing an etch sequence for substantially completely removing an etch stop material, which may be used for the patterning of the second stress-inducing dielectric material, while, in other cases, the etch stop material may be selectively formed after the patterning of the first stress-inducing dielectric material. Hence, the dual stress liner approach may be efficiently applied to semiconductor devices of the 45 nm technology and beyond. 19.-. (canceled)10. A method , comprising:forming a layer stack above first and second conductive lines formed in a device level of a semiconductor device, said layer stack comprising a first stress-inducing dielectric layer and an etch stop layer formed above said first stress-inducing dielectric layer;forming a mask so as to expose said second conductive lines and cover said first conductive lines;performing an etch sequence to remove said first stress-inducing dielectric layer and said etch stop layer from above said second conductive lines and reduce a width of sidewall spacer elements formed on sidewalls of said second conductive lines, wherein reducing said width comprises removing a first thickness portion of said sidewall spacer elements while leaving a second thickness portion of said sidewall spacer elements adjacent to said sidewalls;after performing said etch sequence, forming a second stress-inducing dielectric layer above said second conductive lines and on a portion of said etch stop layer located above said first conductive lines; andselectively removing said second stress-inducing dielectric layer from above said first conductive lines by using said etch stop layer as an etch stop.11. The method of claim 10 , wherein performing said etch sequence comprises performing a first etch process to expose at least a portion of said first stress-inducing dielectric layer and ...

Gan-on-si switch devices

A low leakage current switch device ( 110 ) is provided which includes a GaN-on-Si substrate ( 11, 13 ) with one or more device mesas ( 41 ) in which isolation regions ( 92, 93 ) are formed using an implant mask ( 81 ) to implant ions ( 91 ) into an upper portion of the mesa sidewalls and the peripheral region around each elevated surface of the mesa structures exposed by the implant mask, thereby preventing the subsequently formed gate electrode ( 111 ) from contacting the peripheral edge and sidewalls of the mesa structures.

Method for manufacturing insulated-gate mos transistors

A method for defining an insulator in a semiconductor substrate includes forming a trench in the substrate, forming in the trench an insulating material having its upper surface arranged above the surface of the substrate, and forming a diffusion barrier layer in a portion of the insulating material located above the surface of the semiconductor substrate. Such insulators can be used, for example, to insulate and delineate electronic components or portions of components formed in the substrate.

Semiconductor device and method for manufacturing the same

A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device uses an aluminum alloy, rather than aluminum, for a metal gate. Therefore, the surface of the high-k metal gate after the CMP is aluminum alloy rather than pure aluminum, which can greatly reduce defects, such as corrosion, pits and damage, in the metal gate and improve reliability of the semiconductor device.

Method for fabricating oxides/semiconductor interfaces

By depositing a layer of oxidizing metal on the semiconductor surface first and then depositing a layer of the high-k oxide material over the layer of oxidizing metal by an atomic layer deposition, a high-k metal oxide is formed at the interface between the semiconductor substrate and the high-k oxide and prevents formation of the undesirable low-k semiconductor oxide layer at the semiconductor/high-k oxide interface.

Semiconductor structure and process thereof

A semiconductor structure includes a substrate, a dielectric layer and a fluoride metal layer. The dielectric layer is located on the substrate. The fluoride metal layer is located on the dielectric layer. Furthermore, the present invention also provides a semiconductor process to form said semiconductor structure.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

The present invention provides a method of manufacturing a semiconductor device comprising: providing a semiconductor substrate, on which a high-k dielectric layer and a patterned gate are formed sequentially; nitridating portions of the high-k dielectric layer on the semiconductor substrate which are not covered by the gate; and forming spacers around the gate. Accordingly, the present invention further provides a semiconductor device. Portions of the high-k dielectric layer on the semiconductor substrate, which are not covered by the gate or the spacers positioned thereon, are nitridated, such that an oxygen diffusion barrier layer is formed on the surface of the high-k dielectric layer, thereby oxygen diffusion in the lateral direction into the high-k dielectric layer under the gate is prevented, and the operation performance of the semiconductor device is optimized. 1. A method for manufacturing a semiconductor device , comprising:providing a semiconductor substrate, on which a high-k dielectric layer and a patterned gate are formed sequentially;nitridating portions of the high-k dielectric layer on the semiconductor substrate which are not covered by the gate; andforming spacers around the gate.2. The method according to claim 1 , wherein the nitrogen content in the nitridated high-k dielectric layer in the semiconductor device has an atomic percentage of nitrogen more than 10%.3. The method according to claim 1 , wherein a nitridated periphery portion of the high-k dielectric layer covered by the gate has a lateral dimension not larger than 3 nm.4. A method for manufacturing a semiconductor device claim 1 , comprising:providing a semiconductor substrate, on which a high-k dielectric layer and a patterned gate are formed sequentially;forming spacers around the gate; andnitridating portions of the high-k dielectric layer on the semiconductor substrate which are not covered by both the gate and the spacers.5. The method according to claim 4 , wherein the nitrogen ...

Transistor Performance Improving Method with Metal Gate

The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode.

Germanium oxide free atomic layer deposition of silicon oxide and high-k gate dielectric on germanium containing channel for cmos devices

A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.

Method for fabricating vertical channel type nonvolatile memory device

A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers alternately over a substrate; etching the interlayer insulating layers and the gate electrode conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over the resulting structure including the channel trench; doping the first channel layer with impurities through a plasma doping process; and filling the channel trench with a second channel layer.

Method of Forming a Semiconductor Device by Using Sacrificial Gate Electrodes and Sacrificial Self-Aligned Contact Structures

Disclosed herein are various methods of forming a semiconductor device using sacrificial gate electrodes and sacrificial self-aligned contacts. In one example, the method includes forming two spaced-apart sacrificial gate electrodes comprised of a first material, forming a sacrificial contact structure comprised of a second material, wherein the second material is selectively etchable with respect to said first material, and performing an etching process on the two spaced-apart sacrificial gate electrodes and the sacrificial contact structure to selectively remove the two spaced-apart sacrificial gate electrode structures selectively relative to the sacrificial contact structure.

Semiconductor device and method for manufacturing the same

An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.

Integrated high-k/metal gate in cmos process flow

A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first active region and a second active region, forming a first metal layer over a high-k dielectric layer, removing at least a portion of the first metal layer in the second active region, forming a second metal layer on first metal layer in the first active region and over the high-k dielectric layer in the second active region, and thereafter, forming a silicon layer over the second metal layer. The method further includes removing the silicon layer from the first gate stack thereby forming a first trench and from the second gate stack thereby forming a second trench, and forming a third metal layer over the second metal layer in the first trench and over the second metal layer in the second trench.

TRANSISTOR WITH REDUCED DEPLETION FIELD WIDTH

Devices such as transistors having an oxide layer that provide a depletion field in a conduction channel. A barrier layer is formed over the oxide layer. A gate electrode is formed over the barrier layer. The barrier layer and gate electrode are configured to reduce the width of the depletion field absent a voltage applied to the gate electrode. 1. A transistor comprising:an oxide layer configured to provide a depletion field in a conduction channel;a barrier layer formed over the oxide layer; anda gate electrode formed over and in contact with the barrier layer wherein the gate electrode comprises a conductive material selected from the group consisting of a metal and a refractory metal;wherein the barrier layer and gate electrode are configured to reduce a width of the depletion field absent a voltage applied to the gate electrode.2. The transistor of claim 1 , wherein the barrier layer includes tantalum nitride.3. The transistor of claim 2 , wherein the barrier has a resistivity of about 2500 μOhms-cm.4. The transistor of claim 2 , wherein the metal electrode comprises copper.5. The transistor of claim 1 , wherein the barrier layer includes less than 10% fluorine.6. The transistor of claim 1 , wherein the barrier layer includes silicon impurities of less than about 5%.7. The transistor of claim 1 , wherein the electrode is a metal and the barrier layer includes tantalum.8. A transistor comprising:an oxide layer configured to provide a depletion field in a conduction channel;a first barrier layer formed over the oxide layer; anda gate electrode formed over and in contact with the barrier layer wherein the gate electrode comprises a conductive material selected from the group consisting of a metal and a refractory metal;a second barrier layer formed over the gate electrode wherein the barrier layers and gate electrode are configured to reduce a width of the depletion field absent a voltage applied to the gate electrode.9. The transistor of claim 8 , wherein each of ...

Structure and method for reduction of vt-w effect in high-k metal gate devices

A substrate is provided. An STI trench is formed in the substrate. A fill material is formed in the STI trench and then planarized. The substrate is exposed to an oxidizing ambient, growing a liner at a bottom and sidewalls of the STI trench. The liner reduces the Vt-W effect in high-k metal gate devices.

HIGH-K DIELECTRICS WITH GOLD NANO-PARTICLES

A metal oxide semiconductor (MOS) structure having a high dielectric constant gate insulator layer containing gold (Au) nano-particles is presented with methods for forming the layer with high step coverage of underlying topography, high surface smoothness, and uniform thickness. The transistor may form part of a logic device, a memory device, a persistent memory device, a capacitor, as well as other devices and systems. The insulator layer may be formed using atomic layer deposition (ALD) to reduce the overall device thermal exposure. The insulator layer may be formed of a metal oxide, a metal oxycarbide, a semiconductor oxide, or semiconductor oxide oxycarbide, and the gold nano-particles in insulator layer increase the work function of the insulator layer and affect the tunneling current and the threshold voltage of the transistor. 1. A device comprising:a semiconductive substrate with a dielectric layer comprising;a first layer of an insulator material disposed on a portion of the semiconductive substrate having a first thickness;a second layer of a material disposed on the first insulator material having a second thickness and a work function higher than 5.0 eV, and;a third layer of an insulator material disposed on the second layer having a third thickness; anda conductive material disposed on the third layer of insulator material.2. The device of claim 1 , wherein the first thickness is less than 1.0 nm.3. The device of claim 1 , wherein the second material comprises gold having a second thickness less than 1.0 nm.4. The device of claim 1 , wherein the third material comprises hafnium oxide having a dielectric constant of greater than 22 claim 1 , and an equivalent silicon dioxide thickness of less than 1.0 nm.5. The device of claim 1 , wherein the device includes a non-volatile memory cell.6. The device of claim 1 , wherein the second layer includes a plurality of nano-particles of gold at an interface between the first and third layers claim 1 , having an ...