GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME

A gate structure and a method for fabricating the same are described. A substrate is provided, and a gate dielectric layer is formed on the substrate. The formation of the gate dielectric layer includes depositing a silicon nitride layer on the substrate by simultaneously introducing a nitrogen-containing gas and a silicon-containing gas. A gate is formed on the gate dielectric layer, so as to form the gate structure. 1. A method for fabricating a gate structure , comprising:providing a substrate;forming a gate dielectric layer on the substrate, comprising:depositing a silicon nitride layer on the substrate by simultaneously introducing a nitrogen-containing gas and a silicon-containing gas; andforming a gate on the gate dielectric layer.2. The method according to claim 1 , wherein the method of forming the gate dielectric layer comprises forming a silicon oxide layer on the substrate before depositing the silicon nitride layer.3. The method according to claim 2 , wherein the silicon nitride layer is thicker than the silicon oxide layer.4. The method according to claim 2 , further comprising performing a soft annealing process before depositing the silicon nitride layer but after forming the silicon oxide layer.5. The method according to claim 4 , wherein the soft annealing process is performed using the nitrogen-containing gas.6. The method according to claim 1 , further comprising performing a soft annealing process after depositing the silicon nitride layer but before forming the gate.7. The method according to claim 6 , wherein the soft annealing process is performed using the nitrogen-containing gas.8. The method according to claim 1 , further comprising performing a thermal annealing process after depositing the silicon nitride layer but before forming the gate.9. The method according to claim 8 , wherein the thermal annealing process is performed at a temperature of 600° C. to 800° C.10. The method according to claim 1 , wherein a process temperature for ...

SEMICONDUCTOR STRUCTURE WITH A MULTILAYER GATE OXIDE AND METHOD OF FABRICATING THE SAME

A semiconductor structure with a multilayer gate oxide is provided. The structure includes a substrate. A multilayer gate oxide is disposed on the substrate, wherein the multilayer gate oxide includes a first gate oxide and a second gate oxide. The first gate oxide contacts the substrate and the second gate oxide is disposed on and contacts the first gate oxide. The second gate oxide is hydrophilic. The first gate oxide is formed by a thermal oxidation process. The second gate oxide is formed by a chemical treatment. 1. A semiconductor structure with a multilayer gate oxide , comprising:a substrate; a first gate oxide contacting the substrate; and', 'a second gate oxide disposed on and contacting the first gate oxide, wherein the second gate oxide is hydrophilic and the second gate oxide is silicon oxide., 'a multilayer gate oxide disposed on the substrate, wherein the multilayer gate oxide comprises2. The semiconductor structure with a multilayer gate oxide of claim 1 , wherein a first thickness of the first gate oxide is greater than a second thickness of the second gate oxide.3. The semiconductor structure with a multilayer gate oxide of claim 2 , wherein the ratio of the first thickness to the second thickness is not smaller than 3/2.4. The semiconductor structure with a multilayer gate oxide of claim 1 , wherein the first gate oxide has a chemical formula of SiO claim 1 , the second gate oxide has a chemical formula of SiO claim 1 , and the ratio of B to A is greater than the ratio of Y to X.5. The semiconductor structure with a multilayer gate oxide of claim 1 , further comprising a high-K material disposed on and contacting the second oxide layer.6. The semiconductor structure with a multilayer gate oxide of claim 5 , further comprising a metal filling layer disposed on the high-K material.7. A method of fabricating a semiconductor structure with a multilayer gate oxide claim 5 , comprising:providing a substrate;performing a thermal oxidation process to form ...

Method for fabricating silicon dioxide layer

A method for fabricating silicon dioxide layer is disclosed. The method includes the following steps. Firstly, a semiconductor substrate is provided. Next, the semiconductor substrate is cleaned with a solution containing hydrogen peroxide to form a chemical oxide layer on the semiconductor substrate. Then, the chemical oxide layer is heated in no oxygen atmosphere, such that the chemical oxide layer forms a compact layer. Then, the semiconductor substrate is heated in oxygen atmosphere to form a silicon dioxide layer between the semiconductor substrate and the compact layer.

METHOD FOR PROCESSING HIGH-K DIELECTRIC LAYER

A method for processing a high-k dielectric layer includes the following steps. A semiconductor substrate is provided, and a high-k dielectric layer is formed thereon. The high-k dielectric layer has a crystalline temperature. Subsequently, a first annealing process is performed, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature. A second annealing process is performed, and a process temperature of the second annealing process is substantially larger than the crystalline temperature. 1. A method for processing a high-k (high dielectric constant) dielectric layer , comprising:providing a semiconductor substrate;forming a high-k dielectric layer on the semiconductor substrate, wherein the high-k dielectric layer has a crystalline temperature;performing a first annealing process, wherein a first process gas comprising a plurality of radicals is introduced during the first annealing process, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature; andperforming a second annealing process, wherein a process temperature of the second annealing process is substantially larger than the crystalline temperature.2. The method for processing a high-k dielectric layer according to claim 1 , wherein a material of the high-k dielectric layer comprises hafnium oxide (HfO) claim 1 , hafnium silicon oxide (HfSiO) claim 1 , hafnium silicon oxynitride (HfSiON) claim 1 , aluminum oxide (AlO) claim 1 , lanthanum oxide (LaO) claim 1 , tantalum oxide (TaO) claim 1 , yttrium oxide (YO) claim 1 , zirconium oxide (ZrO) claim 1 , strontium titanate oxide (SrTiO) claim 1 , zirconium silicon oxide (ZrSiO) claim 1 , hafnium zirconium oxide (HfZrO) claim 1 , strontium bismuth tantalate (SrBiTaO claim 1 , SBT) claim 1 , lead zirconate titanate (PbZrTiO claim 1 , PZT) claim 1 , barium strontium titanate (BaSrTiO claim 1 , BST) or a combination thereof.3. The method for ...

Manufacturing method for metal gate using ion implantation

A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.

MANUFACTURING METHOD FOR METAL GATE

A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function. 1. A manufacturing method for a metal gate comprising:providing a substrate having at least a semiconductor device with a conductivity type formed thereon;forming a gate trench in the semiconductor device;forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench; andperforming an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.2. The manufacturing method for a metal gate according to claim 1 , wherein the semiconductor device further comprises at least a high-k gate dielectric layer claim 1 , a bottom barrier layer claim 1 , and an etch stop layer claim 1 , and the etch stop layer is exposed in a bottom of the gate trench.3. The manufacturing method for a metal gate according to claim 1 , wherein the conductivity type of the semiconductor device is a p-type.4. The manufacturing method for a metal gate according to claim 3 , wherein the work function metal layer comprises titanium nitride (TiN) claim 3 , titanium carbide (TiC) claim 3 , tantalum nitride (TaN) claim 3 , tantalum carbide (TaC) claim 3 , tungsten carbide (WC) claim 3 , or aluminum titanium nitride (TiAlN).5. The manufacturing method for a metal gate according to claim 3 , wherein the ion implantation comprises implanting aluminum (Al) claim 3 , nitrogen (N) claim 3 , chlorine (Cl) claim 3 , oxygen (O) claim 3 , fluorine (F) claim 3 , or bromine (Br).6. The ...

SEMICONDUCTOR PROCESS

A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and an oxide layer is formed on the substrate without the fin-shaped structure forming thereon. A thermal treatment process is performed to form a melting layer on at least a part of the sidewall of the fin-shaped structure.

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

A semiconductor device includes substrate having a fin structure thereon, a gate structure overlying the fin structure, a polymer block at a corner between the gate structure and the fin structure, and a source/drain region on the fin structure. The polymer block includes a nitridation layer in proximity to a sidewall of the gate structure.

Method for fabricating gate structure

A gate structure and a method for fabricating the same are described. A substrate is provided, and a gate dielectric layer is formed on the substrate. The formation of the gate dielectric layer includes depositing a silicon nitride layer on the substrate by simultaneously introducing a nitrogen-containing gas and a silicon-containing gas. A gate is formed on the gate dielectric layer, so as to form the gate structure.

MANUFACTURING METHOD FOR METAL GATE STRUCTURE

A manufacturing method for a metal gate structure includes providing a substrate having a gate trench formed thereon, forming a work function metal layer in the gate trench, and performing an annealing process to the work function metal layer. The annealing process is performed at a temperature between 400° C. and 500° C., and in a bout 20 seconds to about 180 seconds. 1. A manufacturing method for a metal gate structure comprising:providing a substrate having a gate trench formed thereon;forming a work function metal layer in the gate trench; andperforming an annealing process to the work function metal layer, the annealing process being performed at a temperature between 400° C. and 500° C. and in about 20 seconds to about 180 seconds.2. The manufacturing method for a metal gate structure according to claim 1 , further comprising:forming a dummy gate on the substrate, wherein the dummy gate comprises at least a sacrificial layer; andremoving the sacrificial layer to form the gate trench.3. The manufacturing method for a metal gate structure according to claim 2 , wherein the dummy gate comprises an interfacial layer and a high-K dielectric constant (high-K) gate dielectric layer claim 2 , and the high-K gate dielectric layer is formed between the sacrificial layer and the interfacial layer.4. The manufacturing method for a metal gate structure according to claim 3 , wherein the high-K gate dielectric layer is exposed in the bottom of the gate trench after removing the sacrificial layer.5. The manufacturing method for a metal gate structure according to claim 2 , wherein the dummy gate further comprises a dielectric layer formed between the sacrificial layer and the substrate.6. The manufacturing method for a metal gate structure according to claim 5 , further comprising:removing the sacrificial layer and a portion of the dielectric layer to form a gate trench on the substrate;forming a high-K gate dielectric layer on the dielectric layer in the gate trench; ...

SEMICONDUCTOR PROCESS

A semiconductor process includes the following steps. A substrate is provided. An ozone saturated deionized water process is performed to form an oxide layer on the substrate. A dielectric layer is formed on the oxide layer. A post dielectric annealing (PDA) process is performed on the dielectric layer and the oxide layer.

First and second differential transmission lines where the second transmission line includes bent portions to surround the first transmission line

An exemplary transmission line system is provided. The system includes a first transmission line partially arranged on a first layer of a PCB including first structure units and partially arranged on a third layer of the PCB including second structure units, and a second transmission line arranged on a second layer of the PCB. Each first structure unit and each second structure respectively include a first connection line, a second connection line, and a first bent line; and a third connection line, a fourth connection line, and a second bent line. A second end of the first connection line and the second connection line of each of the first structure units are respectively connected to a second end of the third connection line and the fourth connection line of the adjacent second structure unit through respective vias.

Method of fabricating an epitaxial layer

A method of fabricating an epitaxial layer includes providing a substrate. The substrate is etched to form at least a recess within the substrate. A surface treatment is performed on the recess to form a Si-OH containing surface. An in-situ epitaxial process is performed to form an epitaxial layer within the recess, wherein the epitaxial process is performed in a hydrogen-free atmosphere and at a temperature lower than 800° C.

High-K metal gate process for lowering junction leakage and interface traps in NMOS transistor

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer.

Method for forming a stacked layer structure

The present invention provides a method for forming a stacked layer structure, including: first, a recess is provided, next, an oxide layer is formed in the recess, where the oxide layer has a thickness T 1 , a high-k layer is formed on the oxide layer, a barrier layer is formed on the high-k layer, a silicon layer is then formed on the barrier layer, afterwards, an annealing process is performed on the silicon layer, so as to form an oxygen-containing layer between the silicon layer and the barrier layer, where the oxide layer has a thickness T 2 after the annealing process is performed, and satisfies the relationship: (T 2 −T 1 )/T 1 ≦0.05, and the silicon layer and the oxygen-containing layer are removed.

METHOD FOR FABRICATING FIN STRUCTURE FOR FIN FIELD EFFECT TRANSISTOR

The invention provides a method for fabricating a fin structure for fin field effect transistor, including following steps. Providing a substrate, including a fin structure having a silicon fin and a single mask layer just on a top of the silicon fin, the single mask layer being as a top portion of the fin structure. Forming a stress buffer layer on the substrate and conformally covering over the fin structure. Performing a nitridation treatment on the stress buffer layer to have a nitride portion. Perform a flowable deposition process to form a flowable dielectric layer to cover over the fin structures. Annealing the flowable dielectric layer. Polishing the flowable dielectric layer, wherein the nitride portion of the stress buffer layer is used as a polishing stop.

METHOD FOR FORMING SEMICONDUCTOR DEVICE

A method of forming a semiconductor device. A substrate having a fin structure is provided. A dummy gate is formed on the fin structure. A polymer block is formed adjacent to a corner between the dummy gate and the fin structure. The polymer block is subjected to a nitrogen plasma treatment, thereby forming a nitridation layer in proximity to a sidewall of the dummy gate under the polymer block. After subjecting the polymer block to the nitrogen plasma treatment, a seal layer is formed on the sidewall of the dummy gate and on the polymer block. An epitaxial layer is then grown on a source/drain region of the fin structure. The dummy gate is then replaced with a metal gate.

Semiconductor process

A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and an oxide layer is formed on the substrate without the fin-shaped structure forming thereon. A thermal treatment process is performed to form a melting layer on at least a part of the sidewall of the fin-shaped structure.

Semiconductor structure and fabrication method thereof

A semiconductor process includes the following steps. A substrate is provided. A dielectric layer having a high dielectric constant is formed on the substrate, wherein the steps of forming the dielectric layer include: (a) a metallic oxide layer is formed; (b) an annealing process is performed to the metallic oxide layer; and the steps (a) and (b) are performed repeatedly. Otherwise, the present invention further provides a semiconductor structure formed by said semiconductor process.

FIN STRUCTURE FOR FIN FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATION THE SAME

The invention provides a fin structure for a fin field effect transistor, including a substrate. The substrate includes a plurality of silicon fins, wherein a top of each one of the silicon fins is a round-like shape in a cross-section view. An isolation layer is disposed on the substrate between the silicon fins at a lower portion of the silicon fins while an upper portion of the silicon fins is exposed. A stress buffer layer is disposed on a sidewall of the silicon fins between the isolation layer and the lower portion of the silicon fins. The stress buffer layer includes a nitride portion.

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer. 1. A method for fabricating semiconductor device , comprising:providing a substrate;forming an interfacial layer on the substrate;forming a high-k dielectric layer on the interfacial layer;forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer;performing a thermal treatment;removing the first BBM layer; andforming a second BBM layer on the high-k dielectric layer.2. The method of claim 1 , further comprising performing a pre-clean before forming the interfacial layer.3. The method of claim 1 , further comprising:forming a sacrificial layer on the second BBM layer;patterning the sacrificial layer to form a dummy gate;forming a spacer on the sidewall of the dummy gate;forming a source/drain region in the substrate adjacent to the spacer;forming a contact etch stop layer on the dummy gates;forming an interlayer dielectric layer (ILD) on the contact etch stop layer; andperforming a replacement metal gate (RMG) process to form the dummy gate into metal gate.4. The method of claim 3 , wherein the sacrificial layer comprises amorphous silicon or polysilicon.5. The method of claim 1 , wherein the interfacial layer comprises silicon oxide.6. The method of claim 1 , wherein the first BBM layer and the second BBM layer comprise TiN.7. The method of claim 1 , further comprising forming a silicon layer on the first BBM layer before performing the thermal treatment.8. The method of claim 7 , further comprising removing the silicon layer and the first BBM layer before forming the second BBM layer.9. The method of claim 7 , wherein the ...

Method for fabricating fin structure for fin field effect transistor

The invention provides a method for fabricating a fin structure for fin field effect transistor, including following steps. Providing a substrate, including a fin structure having a silicon fin and a single mask layer just on a top of the silicon fin, the single mask layer being as a top portion of the fin structure. Forming a stress buffer layer on the substrate and conformally covering over the fin structure. Performing a nitridation treatment on the stress buffer layer to have a nitride portion. Perform a flowable deposition process to form a flowable dielectric layer to cover over the fin structures. Annealing the flowable dielectric layer. Polishing the flowable dielectric layer, wherein the nitride portion of the stress buffer layer is used as a polishing stop.

GATE OXIDE FORMATION PROCESS

A gate oxide formation process includes the following steps. A first gate oxide layer is formed on a substrate. The first gate oxide layer is thinned to a first predetermined thickness. The first gate oxide layer is then thickened to a second predetermined thickness, to thereby form a second gate oxide layer. 1: A gate oxide formation process , comprising:forming a first gate oxide layer on a substrate;thinning the first gate oxide layer to a first predetermined thickness being larger than zero; andthickening the first gate oxide layer to a second predetermined thickness right after the first gate oxide layer is thinned, to thereby form a second gate oxide layer.2: The gate oxide formation process according to claim 1 , wherein the first gate oxide layer is thinned by performing an etching process.3: The gate oxide formation process according to claim 2 , wherein the etching process comprises an etchant of dilute hydrofluoric acid (DHF).4: The gate oxide formation process according to claim 3 , wherein the processing time of the etching process is in a range of 60˜80 seconds.5: The gate oxide formation process according to claim 4 , wherein the processing time of the etching process is 70 seconds.6: The gate oxide formation process according to claim 1 , wherein the first gate oxide layer is thickened by performing a non-nitrogen oxide process.7: The gate oxide formation process according to claim 1 , wherein the first gate oxide layer is thickened by performing a pure oxide process.8: The gate oxide formation process according to claim 1 , wherein the first gate oxide layer is thickened by performing a rapid thermal oxidation (RTO) process.9: The gate oxide formation process according to claim 1 , wherein the first gate oxide layer is thickened by performing an in-situ steam generation (ISSG) process.10: The gate oxide formation process according to claim 9 , wherein the in-situ steam generation (ISSG) process has imported hydrogen gas and oxygen gas.11: The gate ...

Semiconductor structure with a multilayer gate oxide and method of fabricating the same

A semiconductor structure with a multilayer gate oxide is provided. The structure includes a substrate. A multilayer gate oxide is disposed on the substrate, wherein the multilayer gate oxide includes a first gate oxide and a second gate oxide. The first gate oxide contacts the substrate and the second gate oxide is disposed on and contacts the first gate oxide. The second gate oxide is hydrophilic. The first gate oxide is formed by a thermal oxidation process. The second gate oxide is formed by a chemical treatment.

Semiconductor device and fabrication method thereof

A semiconductor device includes substrate having a fin structure thereon, a gate structure overlying the fin structure, a polymer block at a corner between the gate structure and the fin structure, and a source/drain region on the fin structure. The polymer block includes a nitridation layer in proximity to a sidewall of the gate structure.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer. 1. A method for fabricating semiconductor device , comprising:providing a substrate;forming an interfacial layer on the substrate;forming a high-k dielectric layer on the interfacial layer;forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer;performing a thermal treatment;removing the first BBM layer; andforming a second BBM layer on the high-k dielectric layer.2. The method of claim 1 , further comprising performing a pre-clean before forming the interfacial layer.3. The method of claim 1 , further comprising:forming a sacrificial layer on the second BBM layer;patterning the sacrificial layer to form a dummy gate;forming a spacer on the sidewall of the dummy gate;forming a source/drain region in the substrate adjacent to the spacer;forming a contact etch stop layer on the dummy gates;forming an interlayer dielectric layer (ILD) on the contact etch stop layer; andperforming a replacement metal gate (RMG) process to form the dummy gate into metal gate.4. The method of claim 3 , wherein the sacrificial layer comprises amorphous silicon or polysilicon.5. The method of claim 1 , wherein the interfacial layer comprises silicon oxide.6. The method of claim 1 , wherein the first BBM layer and the second BBM layer comprise TiN.7. The method of claim 1 , further comprising forming a silicon layer on the first BBM layer before performing the thermal treatment.8. The method of claim 7 , further comprising removing the silicon layer and the first BBM layer before forming the second BBM layer.9. The method of claim 7 , wherein the ...

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a gate structure thereon; forming a film stack on the substrate and covering the gate structure, wherein the film stack comprises at least an oxide layer and a nitride layer; removing a portion of the film stack for forming recesses adjacent to two sides of the gate structure and a disposable spacer on the sidewall of the gate structure; and filling the recesses with a material comprising silicon atoms for forming a faceted material layer. 1. A method for fabricating semiconductor device , comprising:providing a substrate, wherein the substrate comprises a gate structure thereon;forming a film stack on the substrate and covering the gate structure, wherein the film stack comprises at least an oxide layer and a nitride layer, wherein the oxide layer comprises a thickness between 30 to 70 Angstroms;removing a portion of the film stack for forming recesses adjacent to two sides of the gate structure and forming a disposable spacer on a sidewall of the gate structure; andfilling the recesses with a material comprising silicon atoms for forming a faceted material layer.2. The method of claim 1 , wherein the gate structure comprises a gate dielectric layer and a gate.3. The method of claim 1 , further comprising forming an offset spacer or a pad oxide layer on the sidewall of the gate structure before forming the film stack.4. The method of claim 1 , further comprising performing a treatment for forming nitrogen-contained substance between the oxide layer and the nitride layer.5. The method of claim 4 , wherein the treatment comprises a decoupled plasma nitridation process.6. The method of claim 4 , wherein the treatment comprises a rapid thermal anneal process.7. The method of claim 4 , wherein the treatment comprises a furnace anneal process.8. The method of claim 1 , further comprising forming the nitride layer with a ...

Metal gate structure and fabrication method thereof

A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.

Semiconductor process

A semiconductor process includes the following steps. A substrate is provided. An ozone saturated deionized water process is performed to form an oxide layer on the substrate. A dielectric layer is formed on the oxide layer. A post dielectric annealing (PDA) process is performed on the dielectric layer and the oxide layer.

METHOD FOR FABRICATING MOS TRANSISTOR

A method of fabricating a MOS transistor includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a first spacer on the sidewall of the gate structure and forming at least a recess within the substrate next to the first spacer; performing an oxygen-containing process to form an oxygen-containing layer on the surface of the recess; performing a cleaning process to remove the oxygen-containing layer; performing an epitaxial process to form an epitaxial layer in the recess; and removing the first spacer.

METAL GATE STRUCTURE AND FABRICATION METHOD THEREOF

A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.

Fin structure for fin field effect transistor and method for fabrication the same

The invention provides a fin structure for a fin field effect transistor, including a substrate. The substrate includes a plurality of silicon fins, wherein a top of each one of the silicon fins is a round-like shape in a cross-section view. An isolation layer is disposed on the substrate between the silicon fins at a lower portion of the silicon fins while an upper portion of the silicon fins is exposed. A stress buffer layer is disposed on a sidewall of the silicon fins between the isolation layer and the lower portion of the silicon fins. The stress buffer layer includes a nitride portion.

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

A semiconductor process includes the following steps. A substrate is provided. A dielectric layer having a high dielectric constant is formed on the substrate, wherein the steps of forming the dielectric layer include: (a) a metallic oxide layer is formed; (b) an annealing process is performed to the metallic oxide layer; and the steps (a) and (b) are performed repeatedly. Otherwise, the present invention further provides a semiconductor structure formed by said semiconductor process. 1. A semiconductor process , comprising:providing a substrate; and (a) forming a metallic oxide layer;', '(b) performing an annealing process to the metallic oxide layer., 'forming a dielectric layer having a high dielectric constant on the substrate, wherein the steps of forming the dielectric layer having a high dielectric constant comprise repeatedly performing the following steps2. The semiconductor process according to claim 1 , wherein the step of forming each metallic oxide layers comprises:performing an atomic layer deposition process.3. The semiconductor process according to claim 2 , wherein forming each metallic oxide layer comprises:performing an oxygen containing process to provide OH-bonds; andperforming a deposition process to form the metallic oxide layer.4. The semiconductor process according to claim 3 , wherein the oxygen containing process comprises a vapor importing process claim 3 , a chloridizing and water importing process claim 3 , a decoupled plasma oxidation and water importing process or an ozone importing process.5. The semiconductor process according to claim 4 , wherein the processing time of the vapor importing process is 10 seconds.6. The semiconductor process according to claim 5 , wherein the metallic oxide layer comprises a hafnium oxide layer and performing the deposition process comprises importing hafnium tetrachloride and water to form the hafnium oxide layer.7. The semiconductor process according to claim 1 , wherein the metallic oxide layer ...

METHOD OF FABRICATING AN EPITAXIAL LAYER

A method of fabricating an epitaxial layer includes providing a substrate. The substrate is etched to form at least a recess within the substrate. A surface treatment is performed on the recess to form a Si—OH containing surface. An in-situ epitaxial process is performed to form an epitaxial layer within the recess, wherein the epitaxial process is performed in a hydrogen-free atmosphere and at a temperature lower than 800° C.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure includes the following. A gate structure is formed on a substrate. A tilt implanting process is performed to implant group IV elements into the substrate to form a doped region, and the doped region is located on two sides of the gate structure and partially located under the gate structure. A part of the substrate on two sides of the gate structure is removed to form a first recess. A cleaning process is performed on the surface of the first recess. A wet etching process is performed on the first recess to form a second recess. A semiconductor layer is formed in the second recess.

Method for fabricating semiconductor device

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having gate structure thereon, wherein the gate structure comprises a high-k dielectric layer; increasing an ambient pressure around the gate structure to a predetermined pressure by injecting a first gas; reducing the ambient pressure to a base pressure; and forming a spacer around the gate structure.

Method for processing high-k dielectric layer

A method for processing a high-k dielectric layer includes the following steps. A semiconductor substrate is provided, and a high-k dielectric layer is formed thereon. The high-k dielectric layer has a crystalline temperature. Subsequently, a first annealing process is performed, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature. A second annealing process is performed, and a process temperature of the second annealing process is substantially larger than the crystalline temperature.

METAL GATE STRUCTURE AND FABRICATION METHOD THEREOF

A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer. 1. A metal gate structure located on a substrate , comprising:a gate dielectric layer located on the substrate;a metal layer located on the gate dielectric layer; anda titanium aluminum nitride metal layer having a U-shaped profile structure located on the metal layer.2. The metal gate structure according to claim 1 , wherein the metal layer comprises a titanium aluminum metal layer.3. The metal gate structure according to claim 1 , wherein the gate dielectric layer comprises a dielectric layer having a high dielectric constant.4. The metal gate structure according to claim 3 , wherein the gate dielectric layer further comprises a buffer layer located between the substrate and the dielectric layer having a high dielectric constant.5. The metal gate structure according to claim 1 , wherein the metal layer has a U-shaped profile structure.6. The metal gate structure according to claim 5 , wherein the gate dielectric layer has a U-shaped profile structure.7. The metal gate structure according to claim 1 , wherein the metal gate structure further comprises an electrode layer located on the titanium aluminum nitride metal layer.8. The metal gate structure according to claim 1 , wherein the metal gate structure can be a metal gate structure of an NMOS transistor.9. The metal gate structure according to claim 1 , wherein the metal gate structure can be a metal gate structure of a PMOS transistor and a NMOS transistor in a CMOS transistor.10. The metal gate structure according to claim 9 , wherein the metal gate structure of the PMOS transistor in the CMOS transistor further comprises a titanium nitride layer located between the gate dielectric layer and ...

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having gate structure thereon, wherein the gate structure comprises a high-k dielectric layer; increasing an ambient pressure around the gate structure to a predetermined pressure by injecting a first gas; reducing the ambient pressure to a base pressure; and forming a spacer around the gate structure. 1. A method for fabricating semiconductor device , comprising:providing a substrate having gate structure thereon, wherein the gate structure comprises a high-k dielectric layer;increasing an ambient pressure around the gate structure to a predetermined pressure by injecting a first gas in a furnace;increasing an ambient temperature around the gate structure in the furnace after increasing the ambient pressure to the predetermined pressure;reducing the ambient pressure to a base pressure in the furnace; andforming a spacer around the gate structure.2. The method of claim 1 , further comprising reducing the ambient pressure to the base pressure before increasing the ambient pressure around the gate structure.3. The method of claim 2 , wherein the base pressure is less than 0.1 Torr.4. The method of claim 1 , wherein the first gas comprises a low activity gas.5. The method of claim 4 , wherein the low activity gas is selected from the group consisting of nitrogen gas claim 4 , argon and helium.6. The method of claim 1 , wherein the predetermined pressure is between 10-760 Torr.7. The method of claim 1 , wherein the predetermined pressure is between 50-200 Torr.8. (canceled)9. The method of claim 1 , further comprising increasing the ambient temperature around the gate structure while increasing the ambient pressure.10. The method of claim 1 , wherein the ambient temperature is increased from 400° C. to a deposition temperature.11. The method of claim 10 , wherein the deposition temperature is between 500-750° C.12. The method of claim 11 , wherein the ...

SEMICONDUCTOR PROCESS

A semiconductor process includes the following steps. A substrate having an oxide layer thereon is provided. A high temperature process higher than 1000° C. is performed to form a melting layer between the substrate and the oxide layer. A removing process is performed to remove the oxide layer and the melting layer. 1. A semiconductor process , comprising:providing a substrate having an oxide layer located thereon;performing a high temperature process higher than 1000° C. to form a melting layer between the substrate and the oxide layer; andafter the high temperature process, performing a removing process to remove the oxide layer and the melting layer.2. The semiconductor process according to claim 1 , wherein the oxide layer comprises a pad oxide layer or a native oxide layer.3. The semiconductor process according to claim 1 , wherein the high temperature process comprises a rapid thermal processing (RTP) process or a laser-spike annealing (LSA) process.4. The semiconductor process according to claim 3 , wherein the processing temperature of the rapid thermal processing (RTP) process is 1000° C.˜1100° C.5. The semiconductor process according to claim 4 , wherein the rapid thermal processing (RTP) process has nitrogen gas imported and is performed at one atmosphere.6. The semiconductor process according to claim 3 , wherein a processing temperature of the laser-spike annealing (LSA) process is 1200° C.˜1300° C.7. The semiconductor process according to claim 6 , wherein the laser-spike annealing (LSA) process is performed at one atmosphere.8. The semiconductor process according to claim 1 , wherein the removing process comprises a hydrofluoric acid containing removing process.9. The semiconductor process according to claim 8 , wherein the processing time of the hydrofluoric acid containing removing process is 300 seconds.10. The semiconductor process according to claim 1 , further comprising:after performing the removing process, forming a gate dielectric layer on ...

Method for forming semiconductor device

A method of forming a semiconductor device. A substrate having a fin structure is provided. A dummy gate is formed on the fin structure. A polymer block is formed adjacent to a corner between the dummy gate and the fin structure. The polymer block is subjected to a nitrogen plasma treatment, thereby forming a nitridation layer in proximity to a sidewall of the dummy gate under the polymer block. After subjecting the polymer block to the nitrogen plasma treatment, a seal layer is formed on the sidewall of the dummy gate and on the polymer block. An epitaxial layer is then grown on a source/drain region of the fin structure. The dummy gate is then replaced with a metal gate.

SEMICONDUCTOR PROCESS AND STRUCTURE THEREOF

A semiconductor process is provided, including: a substrate is provided, a buffer layer is formed, and a dielectric layer having a high dielectric constant is formed, wherein the methods of forming the buffer layer include: (1) an oxidation process is performed; and a baking process is performed; Alternatively, (2) an oxidation process is performed; a thermal nitridation process is performed; and a plasma nitridation process is performed; Or, (3) a decoupled plasma oxidation process is performed. Furthermore, a semiconductor structure fabricated by the last process is also provided.

Metal gate structure and fabrication method thereof

A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.

SEMICONDUCTOR STRUCTURE HAVING METAL GATE AND FORMING METHOD THEREOF

A semiconductor structure having a metal gate includes a dielectric layer. The dielectric layer having a recess is disposed on a substrate, wherein the dielectric layer has a top part and a bottom part, and the tensile stress of the top part is larger than the tensile stress of the bottom part, thereby the recess having a sidewall profile tapering from bottom to top. The present invention also provides a method of forming said semiconductor structure. 1. A semiconductor structure having a metal gate , comprising:a dielectric layer having a recess disposed on a substrate, wherein the dielectric layer has a top part and a bottom part, and a density of the top part is larger than a density of the bottom part, so that a tensile stress of the top part being a constant is larger than a tensile stress of the bottom part, thereby the recess having a sidewall profile tapering from bottom to top.2. The semiconductor structure having a metal gate according to claim 1 , wherein the dielectric layer comprises an interdielectric layer.3. The semiconductor structure having a metal gate according to claim 1 , wherein the dielectric layer comprises an oxide layer.4. The semiconductor structure having a metal gate according to claim 1 , wherein the density of the top part is larger than the density of the bottom part.5. The semiconductor structure having a metal gate according to claim 1 , further comprising:a metal gate disposed in the recess.6. A method of forming a semiconductor structure having a metal gate claim 1 , comprising:forming a dielectric layer having a recess on a substrate, wherein the dielectric layer has a top part and a bottom part, and the tensile stress of the top part is larger than the tensile stress of the bottom part, thereby the recess having a sidewall profile tapering from bottom to top.7. The method of forming a semiconductor structure having a metal gate according to claim 6 , wherein the dielectric layer comprises an interdielectric layer.8. The method ...

Gate dielectric layer forming method

A gate dielectric layer forming method is applied to a fabrication process of a metal-oxide-semiconductor field-effect transistor. The gate dielectric layer forming method includes the following steps. Firstly, a substrate is provided. Then, an interlayer is formed on the substrate. Then, a high-k dielectric layer is formed on the interlayer. A nitridation process is performed to convert the high-k dielectric layer into a nitridated high-k dielectric layer. A first low temperature post-nitridation annealing process is performed to treat the nitridated high-k dielectric layer with a first gas. Afterwards, a second low temperature post-nitridation annealing process is performed to treat the nitridated high-k dielectric layer with a second gas.

Transmission line system

An exemplary transmission line system is provided. The system includes a first transmission line partially arranged on a first layer of a PCB including first structure units and partially arranged on a third layer of the PCB including second structure units, and a second transmission line arranged on a second layer of the PCB. Each first structure unit and each second structure respectively include a first connection line, a second connection line, and a first curved line; and a third connection line, a fourth connection line, and a second curved line. A second end of the first connection line and the second connection line of each of the first structure units are respectively connected to a second end of the third connection line and the fourth connection line of the adjacent second structure unit through vias.

金屬閘極之製作方法

一種金屬閘極之製作方法，該方法首先提供一基底，該基底上形成有至少一半導體元件，且該半導體元件具有一導電型式。接下來於該半導體元件內形成一閘極溝渠，在形成閘極溝渠後，係於該閘極溝渠內形成一功函數金屬層，該功函數金屬層具有該導電型式以及一對應該導電型式之預設功函數。最後進行一離子佈植製程，調整該預設功函數至一目標功函數，且該目標功函數係對應該導電型式。

Method for fabricating MOS transister

半導體製程

一種半導體製程，包含有下述步驟。首先，提供一基底。接著，進行一去離子臭氧製程，以形成一氧化層於基底上。而後，形成一介電層於氧化層上。然後，進行一介電後退火(post dielectric annealing,PDA)製程於介電層以及氧化層。

傳輸線系統

一種傳輸線系統包括：一第一傳輸線，部分設置於一PCB板的第一層上包括第一結構單元，部分設置於該PCB板的第三層上包括第二結構單元，每一第一結構單元包括一第一連接段、一第二連接段及一兩端分別與該第一連接段和第二連接段連接的第一彎折段，每一第二結構單元包括一第三連接段、一第四連接段及一兩端分別與該第三連接段和第四連接段連接的第二彎折段，每一第一連接段及第二連接段的第二端藉由一導電通孔分別與相鄰第三連接段及第四連接段的第二端連接；及一第二傳輸線，為設置於該PCB板的第二層上的直線傳輸線。

Method of fabricating an epitaxial layer

半導體結構及其製程

一種半導體製程，包含有下述步驟。首先，提供一基底。接著，形成一高介電常數介電層於基底上，其中形成高介電常數介電層包含有下列步驟：(a)形成一金屬氧化層；(b)進行一退火製程，於金屬氧化層；然後，重複步驟(a)及(b)。此外，本發明更提供一種半導體結構，其以上述之半導體製程形成。

Semiconductor device and fabrication method thereof

A semiconductor device includes a fin structure disposed on a substrate, and an epitaxial semiconductor layer disposed over an upper part of the fin structure and having an undercut. The epitaxial semiconductor layer has a right-left symmetric, concave polygonal cross-section.

半導體製程

一種半導體製程，包含有下述步驟。首先，提供一基底，具有一氧化層位於基底上。接著，進行一大於1000℃之高溫製程，以使基底與氧化層之間形成一熔融層。接續，進行一移除製程，以移除氧化層以及熔融層。