Methods for producing oil and/or gas

A method for producing oil and/or gas comprising injecting a miscible enhanced oil recovery formulation into fractures, karsts, and/or vugs of a formation for a first time period from a first well; producing oil and/or gas from the fractures, karsts, and/or vugs from a second well for the first time period; injecting a miscible enhanced oil recovery formulation into the fractures, karsts, and/or vugs for a second time period from the second well; and producing oil and/or gas from the fractures, karsts, and/or vugs from the first well for the second time period.

Cyclic steam stimulation method with multiple fractures

A cyclic steam soak (CSS) stimulation method for producing heated hydrocarbons from a viscous hydrocarbon-containing formation comprises the steps of: a) drilling a well (1) having a substantially horizontal or inclined lower section (3) into the viscous hydrocarbon-containing formation (4) substantially along the trajectory of the minimum compressive horizontal stress Sh; b) cutting at selected intervals along the length of the lower well section (3) substantially disk-shaped cavities (5A-5D) into the viscous hydrocarbon-containing formation (4) by a rotating hydraulic jet cutting device (6); c) completing the well (1); d) injecting steam into the well (1) and disk-shaped cavities (5A-5D) at such an elevated pressure that the hydraulic pressure in at least one disk-shaped cavity 5A is above the formation fracturing pressure, thereby fracturing the formation (4) and permitting the steam to invade the formation surrounding the fracture and to heat hydrocarbons in the steam invaded zone; ...

Method of forming integrated circuit having plural transistors with work function metal gate structures

The present invention provides a method of forming an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A semiconductor device is disclosed. The semiconductor device includes: a substrate having a metal-oxide semiconductor (MOS) transistor thereon, and an oxide semiconductor transistor adjacent to the MOS transistor. Preferably, the MOS transistor includes a first gate structure and a source/drain region adjacent to two sides of the gate structure, and the oxide semiconductor transistor includes a channel layer and the top surface of the channel layer is lower than the top surface of the first gate structure of the MOS transistor.

SEMICONDUCTOR DEVICE HAVING SPACER WITH TAPERED PROFILE

A semiconductor device is disclosed. The semiconductor device includes a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the bottom of the spacer includes a tapered profile and the tapered profile comprises a convex curve.

Semiconductor structure with oxide semiconductor layer

The present invention provides a semiconductor structure, including a base, a patterned oxide semiconductor (OS) layer, two source/drain regions, a protective layer, a gate layer and a gate dielectric layer. The patterned OS layer is disposed on the base. Two source/drain regions are disposed on the patterned OS layer and are separated by a recess. Each source/drain region includes an inner sidewall facing the recess and an outer sidewall opposite to the inner sidewall. The protective layer is disposed on a sidewall of the patterned OS layer but is not on the inner sidewall of the source/drain region. The gate layer is disposed on the patterned OS layer, and the gate dielectric layer is disposed between the gate layer and the patterned OS layer.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a lightly doped drain in the substrate; and performing a first implantation process for implanting fluorine ions at a tiled angle into the substrate and part of the gate structure.

SEMICONDUCTOR STRUCTURE

A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures.

Semiconductor structure having gap within gate and cap and process thereof

A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures.

CYCLIC STEAM STIMULATION METHOD WITH MULTIPLE FRACTURES

A cyclic steam soak (CSS) stimulation method for producing heated hydrocarbons from a viscous hydrocarbon-containing formation comprises the steps of: a) drilling a well (1) having a substantially horizontal or inclined lower section (3) into the viscous hydrocarbon-containing formation (4) substantially along the trajectory of the minimum compressive horizontal stress Sh; b) cutting at selected intervals along the length of the lower well section (3) substantially disk-shaped cavities (5A-5D) into the viscous hydrocarbon-containing formation (4) by a rotating hydraulic jet cutting device (6); c) completing the well (1); d) injecting steam into the well (1) and disk-shaped cavities (5A-5D) at such an elevated pressure that the hydraulic pressure in at least one disk-shaped cavity 5A is above the formation fracturing pressure, thereby fracturing the formation (4) and permitting the steam to invade the formation surrounding the fracture and to heat hydrocarbons in the steam invaded zone; ...

GROUPED EXPOSED METAL HEATERS

A system for treating a hydrocarbon containing formation is described. The system includes two or more groups of elongated heaters. The group includes two or more heaters placed in two or more openings in the formation. The heaters in the group are electrically coupled below the surface of the formation. The openings include at least partially uncased wellbores in a hydrocarbon layer of the formation. The groups are electrically configured such that current flow through the formation between at least two groups is inhibited. The heaters are configured to provide heat to the formation.

Integrated circuit having plural transistors with work function metal gate structures

The present invention provides an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF

A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures. 1. A semiconductor process , comprising:forming a metal gate strip in a trench of a dielectric layer;forming a cap layer on the metal gate strip;cutting off the cap layer and the metal gate strip to form a plurality of caps on a plurality of metal gates, and to have a gap separating adjacent caps and adjacent metal gates; andfilling an isolation material in the gap after the cap layer and the metal gate strip are cut off.2. The semiconductor process according to claim 1 , further comprising:forming the dielectric layer on a substrate before the metal gate strip is formed, wherein the substrate has a plurality of fin structures, enabling each of the metal gates to cover each of the fin structures respectively.3. The semiconductor process according to claim 1 , wherein the method of forming the metal gate strip comprises a replacement metal gate (RMG) process.4. The semiconductor process according to claim 3 , wherein the step of forming the metal gate strip comprises:forming a sacrificial gate strip;forming the dielectric layer beside the sacrificial gate strip;removing the sacrificial gate strip to form the trench; andfilling a metal gate material in the trench.5. ...

ELECTRONIC DEVICE BONDING STRUCTURE AND FABRICATION METHOD THEREOF

A fabrication method of an electronic device bonding structure includes the following steps. A first electronic component including a first conductive bonding portion is provided. A second electronic component including a second conductive bonding portion is provided. A first organic polymer layer is formed on the first conductive bonding portion. A second organic polymer layer is formed on the second conductive bonding portion. Bonding is performed on the first electronic component and the second electronic component through the first conductive bonding portion and the second conductive bonding portion, such that the first electronic component and the second electronic component are electrically connected. The first organic polymer layer and the second organic polymer layer diffuse into the first conductive bonding portion and the second conductive bonding portion after the bonding. An electronic device bonding structure is also provided.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess. 1. A method for fabricating semiconductor device , comprising:providing a substrate having an interlayer dielectric (ILD) layer thereon;forming a first recess, a second recess, and a third recess in the ILD layer;forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess;performing a first treatment on the material layer in the first recess but not on the material layer in the second recess and in the third recess; andperforming a second treatment on the material layer in the first recess and second recess.2. The method of claim 1 , wherein the material layer comprises a work function layer.3. The method of claim 1 , further comprises forming a work function layer after forming the material layer.4. The method of claim 3 , further comprising:forming a low resistance metal layer on the work function layer; andplanarizing the low resistance layer and the work function layer for forming three gate structures.5. The method of claim 4 , wherein the three gate structures comprise same conductive type.6. The method of claim 4 , wherein the work function layer of the three gate structures comprise different orientation ratio.7. The method of claim 4 , wherein the three gate structures comprise different threshold voltages (Vt).8. A method for fabricating semiconductor device claim 4 , comprising:providing a substrate having an interlayer dielectric (ILD) layer thereon;forming a first recess, a second recess, and a ...

Method for fabricating semiconductor device

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a lightly doped drain in the substrate; and performing a first implantation process for implanting fluorine ions at a tiled angle into the substrate and part of the gate structure.

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a lightly doped drain in the substrate; and performing a first implantation process for implanting fluorine ions at a tiled angle into the substrate and part of the gate structure. 1. A method for fabricating semiconductor device , comprising:providing a substrate;forming a gate structure on the substrate;forming a lightly doped drain in the substrate; andperforming a first implantation process for implanting fluorine ions at a tiled angle into the substrate and part of the gate structure.2. The method of claim 1 , further comprising:forming a stack structure on the substrate, wherein the stack structure comprises an interfacial layer on the substrate and a sacrificial layer on the interfacial layer;performing a second implantation process to implant fluorine ions into the stack structure for forming an interface layer between the substrate and the interfacial layer;patterning the stack structure for forming the gate structure;forming the lightly doped drain in the substrate; andperforming the first implantation process for implanting fluorine ions at a tilted angle into the substrate and the interface layer.3. The method of claim 2 , wherein the sacrificial layer comprises amorphous silicon or polysilicon.4. The method of claim 2 , wherein the interface layer comprise SiF.5. The method of claim 2 , further comprising performing the first implantation process for forming a first region and a second region surrounding the first region in the interface layer.6. The method of claim 5 , wherein the concentration of the second region is higher than the concentration of the first region.7. The method of claim 1 , wherein the step for forming the gate structure comprises:forming the stack structure on the substrate, wherein the stack structure comprises an interfacial layer on the substrate, a high-k ...

Condensing vaporized water in situ to treat tar sands formations

Methods for treating a tar sands formation are described herein. Methods may include heating at least a section of a hydrocarbon layer in the formation from a plurality of heaters located in the formation. Heat may be allowed to transfer from the heaters to at least a first portion of the formation. Conditions may be controlled in the formation so that water vaporized by the heaters in the first portion is selectively condensed in a second portion of the formation. At least some of the fluids may be produced from the formation.

Semiconductor structure and method of forming the same

The present invention provides a semiconductor structure, including a base, a patterned oxide semiconductor (OS) layer, two source/drain regions, a protective layer, a gate layer and a gate dielectric layer. The patterned OS layer is disposed on the base. Two source/drain regions are disposed on the patterned OS layer and are separated by a recess. Each source/drain region includes an inner sidewall facing the recess and an outer sidewall opposite to the inner sidewall. The protective layer is disposed on a sidewall of the patterned OS layer but is not on the inner sidewall of the source/drain region. The gate layer is disposed on the patterned OS layer, and the gate dielectric layer is disposed between the gate layer and the patterned OS layer. The present invention further provides a method of forming the same.

Semiconductor device and method of forming the same

The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor and the second transistor are disposed on the substrate. The first transistor includes a first channel and a first work function layer. The second transistor includes a second channel and a second work function layer, where the first channel and the second channel include different dopants, and the second work function layer and the first work function layer have a same conductive type and different thicknesses.

Method of condensing vaporized water in situ to treat tar sands formations

Methods for treating a tar sands formation are described herein. Methods may include heating at least a section of a hydrocarbon layer in the formation from a plurality of heaters located in the formation. Heat may be allowed to transfer from the heaters to at least a first portion of the formation. Conditions may be controlled in the formation so that water vaporized by the heaters in the first portion is selectively condensed in a second portion of the formation. At least some of the fluids may be produced from the formation.

Methods for producing oil and/or gas

A method for producing oil and/or gas comprising injecting a miscible enhanced oil recovery formulation into fractures, karsts, and/or vugs of a formation for a first time period from a first well; producing oil and/or gas from the fractures, karsts, and/or vugs from a second well for the first time period; injecting a miscible enhanced oil recovery formulation into the fractures, karsts, and/or vugs for a second time period from the second well; and producing oil and/or gas from the fractures, karsts, and/or vugs from the first well for the second time period.

Lightly-insitu-doped amorphous silicon applied in DRAM gates

The present invention forms a polysilicon by first forming then thermally processing a lightly in-situ doped amorphous silicon layer, thus suppressing boron penetration and lateral diffusion of N-type and P-type impurities.

METHOD FOR FORMING SEMICONDUCTOR DEVICE

The present invention provides a method of forming a semiconductor device. First, a substrate having a first insulating layer formed thereon is provided. After forming an oxide semiconductor layer on the first insulating layer, two source/drain regions are formed on the oxide semiconductor layer. A bottom oxide layer is formed to entirely cover the source/drain regions, following by forming a high-k dielectric layer on the bottom oxide layer. Next, a thermal process is performed on the high-k dielectric layer, and a plasma treatment is performed on the high-k dielectric layer in the presence of a gas containing an oxygen element

Grouped exposed metal heaters

A system for treating a hydrocarbon containing formation is described. The system includes two or more groups of elongated heaters. The group includes two or more heaters placed in two or more openings in the formation. The heaters in the group are electrically coupled below the surface of the formation. The openings include at least partially uncased wellbores in a hydrocarbon layer of the formation. The groups are electrically configured such that current flow through the formation between at least two groups is inhibited. The heaters are configured to provide heat to the formation.

High-K metal gate process for lowering junction leakage and interface traps in NMOS transistor

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer.

Semiconductor device and method for forming the same

The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device including a substrate, an oxide semiconductor layer, two source/drain regions, a high-k dielectric layer and a bottom oxide layer. The oxide semiconductor layer is disposed on a first insulating layer disposed on the substrate. The source/drain regions are disposed on the oxide semiconductor layer. The high-k dielectric layer covers the oxide semiconductor layer and the source structure and the drain regions. The bottom oxide layer is disposed between the high-k dielectric layer and the source/drain regions, wherein the bottom oxide layer covers the source/drain regions and the oxide semiconductor layer.

Memory device

A memory device includes: a substrate; a channel layer on the substrate, in which the channel layer includes a T-shape having a horizontal portion with a first end and a second end and a vertical portion having a third end; a gate structure on a side of the vertical portion; an oxide-nitride-oxide (ONO) layer between the gate structure and the vertical portion; a source region on the first end of the horizontal portion; and a drain region on the third end of the vertical portion.

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; depositing a liner on the gate structure and the substrate; and performing an etching process by injecting a gas comprising CH3F, O2, and He for forming a spacer adjacent to the gate structure.

In situ conversion process systems utilizing wellbores in at least two regions of a formation

A system for heating a subsurface formation is described. The system includes a plurality of elongated heaters located in a plurality of openings in the formation. At least two of the heaters are substantially parallel to each other for at least a portion of the lengths of the heaters. At least two of the heaters have first end portions in a first region of the formation and second end portions in a second region of the formation. A source of time-varying current is configured to apply time-varying current to at least two of the heaters. The first end portions of at least two heaters are configured to have substantially the same voltage applied to them. The second portions of at least two heaters are configured to have substantially the same voltage applied to them.

INTEGRATED CIRCUIT HAVING PLURAL TRANSISTORS WITH WORK FUNCTION METAL GATE STRUCTURES

The present invention provides an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer. 1. An integrated circuit having plural transistors with different threshold voltages , comprising:a substrate;a first transistor with a first metal gate disposed on the substrate, wherein the first metal gate comprises a first bottom barrier layer, a first work function metal (WFM) layer and a first metal layer;a second transistor with a second metal gate disposed on the substrate, wherein the second metal gate comprises a second bottom barrier layer, a second WFM layer and a second metal layer; anda third transistor with a third metal gate disposed on the substrate, wherein the third metal gate comprises a third bottom barrier layer, a third WFM layer and a third metal layer, wherein the first transistor, the second transistor and the third transistor have the same conductive type, and a nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.2. The integrated circuit according to claim 1 , wherein a titanium concentration of the first bottom barrier layer Подробнее

Semiconductor device and method of fabricating the same

A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a metal-oxide-semiconductor (MOS) transistor, a plug, a hydrogen blocking layer and an oxide semiconductor (OS) structure. The MOS transistor is disposed on the substrate, and the plug is disposed on the MOS transistor to electrically connect thereto. The hydrogen blocking layer is disposed only on sidewalls of the plug, wherein the hydrogen blocking layer includes a high-k dielectric layer. The OS structure is disposed on the substrate, wherein the OS structure includes an oxide semiconductor layer.

Manufacturing method of oxide semiconductor device

A manufacturing method of an oxide semiconductor device includes the following steps. A barrier layer is formed on a substrate. An annealing process is performed after the step of forming the barrier layer. A first oxygen treatment is performed on the barrier layer after the annealing process for forming a first oxygen provider layer on the barrier layer. An oxide semiconductor layer is then formed on the first oxygen provider layer.

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor and the second transistor are disposed on the substrate. The first transistor includes a first channel and a first work function layer. The second transistor includes a second channel and a second work function layer, where the first channel and the second channel include different dopants, and the second work function layer and the first work function layer have a same conductive type and different thicknesses. 1. A semiconductor device , comprising:a substrate;a first gate structure disposed on the substrate, the first gate structure comprising:a first channel; anda first work function layer; anda second gate structure disposed on the substrate, the second gate structure comprising:a second channel, wherein the second channel comprises different dopants from that of the first channel; anda second work function layer, wherein the second work function layer and the first work function layer have a same conductive type and different thicknesses.2. The semiconductor device according to claim 1 , wherein the first work function layer and the second work function layer comprise different materials.3. The semiconductor device according to claim 1 , further comprising:a third gate structure disposed on the substrate, wherein the third gate structure comprises:a third channel, wherein the third channel comprises different dopants from that of the first channel and the second channel; anda third work function layer, having a conductive type different from that of the first work function layer and the second work function layer.4. The semiconductor device according to claim 1 , wherein the second channel layer and the first channel layer comprise different dopant dosages.5. The semiconductor device according to claim 1 , wherein the second channel layer and the first channel ...

METHOD OF FORMING A METAL LAYER ON A PHOTOSENSITIVE RESIN

The present invention provides a method of forming a metal layer on a specific photosensitive resin. The method comprises the following steps: (i) pretreatment: cleaning and pre-activating a surface of the photosensitive resin by using an alkaline solution; (ii) surface modification: soaking the photosensitive resin in a surface modifier to form an organic modification layer; (iii) surface activation: adding catalytic metal ions to form a metal ion complex with the organic modification layer; (iv) reduction reaction: reducing the metal ion complex into a nano metal catalyst by using a reducing agent; (v) chemical plating: soaking the photosensitive resin in an chemical plating solution to form a conductive metal layer; (vi) heat treatment: baking the photosensitive resin at 100-250° C., and (vii) electroplating thickening: electroplating the baked photosensitive resin to thicken the conductive metal layer. 2. The method of claim 1 , wherein in the surface modification step (ii) claim 1 , the soaking time is 1-20 minutes claim 1 , the concentration of the amino compound in the surface modifier is 0.1-10 g/L claim 1 , and the temperature is 30-75° C.3. The method of claim 1 , wherein the catalytic metal ions added in the surface activation step (iii) is an acidic aqueous solution containing Cu claim 1 , Ni claim 1 , Ag claim 1 , Au claim 1 , or Pd ions.4. The method of claim 1 , wherein the reducing agent used in the reduction reaction step (iv) is sodium hypophosphite claim 1 , sodium borohydride claim 1 , dimethylamine borane or hydrazine aqueous solution.5. The method of claim 1 , wherein the chemical plating solution used in the chemical plating step (v) comprises copper ions claim 1 , nickel ions claim 1 , a chelating agent claim 1 , a reducing agent claim 1 , a pH buffer claim 1 , a surfactant claim 1 , and a pH adjuster.6. The method of claim 5 , wherein the source of the copper ions is copper nitrate claim 5 , copper sulfate claim 5 , copper chloride claim 5 , ...

Semiconductor device and method for fabricating the same

A semiconductor device includes an interfacial layer on a substrate and agate structure on the interfacial layer. Preferably, the gate structure includes a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a horizontal direction width of the interfacial layer are different. The semiconductor device also includes a first spacer adjacent to the gate structure and on part of the interfacial layer and contacting a top surface of the interfacial layer and a second spacer on the sidewalls of the first spacer and the interfacial layer. Preferably, a planar bottom surface of the second spacer is lower than a planar bottom surface of the first spacer and extending along a same direction as the planar bottom surface of the first spacer.

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer. 1. A method for fabricating semiconductor device , comprising:providing a substrate;forming an interfacial layer on the substrate;forming a high-k dielectric layer on the interfacial layer;forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer;performing a thermal treatment;removing the first BBM layer; andforming a second BBM layer on the high-k dielectric layer.2. The method of claim 1 , further comprising performing a pre-clean before forming the interfacial layer.3. The method of claim 1 , further comprising:forming a sacrificial layer on the second BBM layer;patterning the sacrificial layer to form a dummy gate;forming a spacer on the sidewall of the dummy gate;forming a source/drain region in the substrate adjacent to the spacer;forming a contact etch stop layer on the dummy gates;forming an interlayer dielectric layer (ILD) on the contact etch stop layer; andperforming a replacement metal gate (RMG) process to form the dummy gate into metal gate.4. The method of claim 3 , wherein the sacrificial layer comprises amorphous silicon or polysilicon.5. The method of claim 1 , wherein the interfacial layer comprises silicon oxide.6. The method of claim 1 , wherein the first BBM layer and the second BBM layer comprise TiN.7. The method of claim 1 , further comprising forming a silicon layer on the first BBM layer before performing the thermal treatment.8. The method of claim 7 , further comprising removing the silicon layer and the first BBM layer before forming the second BBM layer.9. The method of claim 7 , wherein the ...

METHOD OF FORMING INTEGRATED CIRCUIT HAVING PLURAL TRANSISTORS WITH WORK FUNCTION METAL GATE STRUCTURES

The present invention provides a method of forming an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer. 1. A method of forming an integrated circuit which has plural transistors with different threshold voltages , comprising:providing a dielectric layer having a first trench, a second trench and a third trench;forming a bottom barrier layer on the dielectric layer, wherein the bottom barrier layer comprises a first bottom barrier layer in the first trench, a second bottom barrier layer in the second trench and a third bottom barrier layer of the third trench, wherein a nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer;forming a work function metal (WFM) layer on the bottom barrier layer in the first trench, the second trench and the third trench; andforming a metal layer on the WFM layer, wherein the first trench, the second trench and the third trench are completely filled with the metal layer.2. The method of forming an integrated circuit according to claim 1 , wherein the step of forming the bottom barrier layer comprises:forming an adjust layer on the dielectric layer, wherein the ...

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device including a substrate, an oxide semiconductor layer, two source/drain regions, a high-k dielectric layer and a bottom oxide layer. The oxide semiconductor layer is disposed on a first insulating layer disposed on the substrate. The source/drain regions are disposed on the oxide semiconductor layer. The high-k dielectric layer covers the oxide semiconductor layer and the source structure and the drain regions. The bottom oxide layer is disposed between the high-k dielectric layer and the source/drain regions, wherein the bottom oxide layer covers the source/drain regions and the oxide semiconductor layer.

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a metal-oxide semiconductor (MOS) transistor thereon and a first interlayer dielectric (ILD) layer surrounding the MOS transistor; forming a source layer, a drain layer, a first opening between the source layer and the drain layer, and a second ILD layer on the MOS transistor and the first ILD layer, wherein the top surfaces of the source layer, the drain layer, and the second ILD layer are coplanar; forming a channel layer on the second ILD layer, the source layer, and the drain layer and into the first opening; and performing a first planarizing process to remove part of the channel layer so that the top surface of the channel layer is even with the top surfaces of the source layer and the drain layer.

Systems and methods for producing oil and/or gas

A system for producing oil and/or gas from an underground formation comprising a first array of wells dispersed above the formation; a second array of wells dispersed above the formation; wherein the first array of wells comprises a mechanism to inject a miscible enhanced oil recovery formulation into the formation while the second array of wells comprises a mechanism to produce oil and/or gas from the formation for a first time period; and wherein the second array of wells comprises a mechanism to inject a miscible enhanced oil recovery formulation into the formation while the first array of wells comprises a mechanism to produce oil and/or gas from the formation for a second time period.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer. 1. A method for fabricating semiconductor device , comprising:providing a substrate;forming an interfacial layer on the substrate;forming a high-k dielectric layer on the interfacial layer;forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer;performing a thermal treatment;removing the first BBM layer; andforming a second BBM layer on the high-k dielectric layer.2. The method of claim 1 , further comprising performing a pre-clean before forming the interfacial layer.3. The method of claim 1 , further comprising:forming a sacrificial layer on the second BBM layer;patterning the sacrificial layer to form a dummy gate;forming a spacer on the sidewall of the dummy gate;forming a source/drain region in the substrate adjacent to the spacer;forming a contact etch stop layer on the dummy gates;forming an interlayer dielectric layer (ILD) on the contact etch stop layer; andperforming a replacement metal gate (RMG) process to form the dummy gate into metal gate.4. The method of claim 3 , wherein the sacrificial layer comprises amorphous silicon or polysilicon.5. The method of claim 1 , wherein the interfacial layer comprises silicon oxide.6. The method of claim 1 , wherein the first BBM layer and the second BBM layer comprise TiN.7. The method of claim 1 , further comprising forming a silicon layer on the first BBM layer before performing the thermal treatment.8. The method of claim 7 , further comprising removing the silicon layer and the first BBM layer before forming the second BBM layer.9. The method of claim 7 , wherein the ...

Semiconductor device

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a lightly doped drain in the substrate; and performing a first implantation process for implanting fluorine ions at a tiled angle into the substrate and part of the gate structure.

SEMICONDUCTOR STRUCTURE WITH OXIDE SEMICONDUCTOR LAYER

The present invention provides a semiconductor structure, including a base, a patterned oxide semiconductor (OS) layer, two source/drain regions, a protective layer, a gate layer and a gate dielectric layer. The patterned OS layer is disposed on the base. Two source/drain regions are disposed on the patterned OS layer and are separated by a recess. Each source/drain region includes an inner sidewall facing the recess and an outer sidewall opposite to the inner sidewall. The protective layer is disposed on a sidewall of the patterned OS layer but is not on the inner sidewall of the source/drain region. The gate layer is disposed on the patterned OS layer, and the gate dielectric layer is disposed between the gate layer and the patterned OS layer. 1. A semiconductor structure , comprising:a patterned oxide semiconductor layer disposed on a base;two source/drain regions disposed on the patterned oxide semiconductor layer, wherein the two source/drain regions are separated by a recess, and each source/drain region respectively comprises an inner sidewall facing the recess and an outer sidewall disposed opposite to the inner sidewall;a protective layer disposed on a sidewall of the patterned oxide semiconductor layer, being not disposed on the inner sidewall of the source/drain region;a gate layer disposed on the patterned oxide semiconductor layer; anda gate dielectric layer disposed between the gate layer and the patterned oxide semiconductor layer.2. The semiconductor structure according to claim 1 , wherein the protective layer directly contacts the sidewall of the patterned oxide semiconductor layer.3. The semiconductor structure according to claim 1 , wherein the protective layer is further disposed on the outer sidewall of the source/drain region and a top surface of the source/drain region.4. The semiconductor structure according to claim 3 , wherein the protective layer has a sidewall vertically aligned with the inner sidewall of the source/drain region.5. The ...

Image sensor pixel structure

A back side illumination image sensor pixel structure includes a substrate having a front side and a back side opposite to the front side, a sensing device formed in the substrate to receive an incident light through the back side of the substrate, two oxide-semiconductor field effect transistor (OS FET) devices formed on the front side of the substrate, and a capacitor formed on the front side of the substrate. The two OS FET devices are directly stacked on the sensing device and the capacitor is directly stacked on the OS FET devices. The two OS FET devices overlap the sensing device, and the capacitor overlaps both of the OS FET devices and the sensing device.

SYSTEMS AND METHODS FOR PRODUCING OIL AND/OR GAS

A system for producing oil and/or gas from an underground formation comprising a first array of wells dispersed above the formation; a second array of wells dispersed above the formation; wherein the first array of wells comprises a mechanism to inject a miscible enhanced oil recovery formulation into the formation while the second array of wells comprises a mechanism to produce oil and/or gas from the formation for a first time period; and wherein the second array of wells comprises a mechanism to inject a miscible enhanced oil recovery formulation into the formation while the first array of wells comprises a mechanism to produce oil and/or gas from the formation for a second time period.

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, an interconnect structure, and an oxide semiconductor structure. The substrate has a first region and a second region. The interconnect structure is disposed on the substrate, in the first region. The oxide semiconductor structure is disposed over a hydrogen blocking layer, in the second region of the substrate.

METHOD OF FORMING A DIELECTRIC LAYER

A method of forming a dielectric layer includes the following steps. First of all, a high-k dielectric layer is formed on a substrate. Next, a nitridation process is performed on the high-k dielectric layer immediately after the high-k dielectric layer is formed. Then, a post-nitridation process is performed on the high-k dielectric layer after the nitridation process is performed. 1. A method of forming a dielectric layer comprising:forming a high-k dielectric layer on a substrate;performing a nitridation process on the high-k dielectric layer immediately after forming the high-k dielectric layer, wherein the whole nitridation process is performed at room temperature; andperforming a post-nitridation process after performing the nitridation process, wherein the post-nitridation process is performed under oxygen diluted with inert gas.2. The method of forming the dielectric layer according to claim 1 , wherein the nitridation process is performed in an oxygen free environment.3. (canceled)4. The method of forming the dielectric layer according to claim 1 , wherein the nitridation process is performed substantially between 20° C. and 25° C.5. The method of forming a dielectric layer according to claim 1 , wherein the nitridation process is a decoupled plasma nitridation process.6. (canceled)7. The method of forming the dielectric layer according to claim 1 , wherein the post-nitridation process is performed under oxygen diluted with nitrogen conditions.8. The method of forming the dielectric layer according to claim 1 , wherein the post-nitridation process is performed under oxygen diluted with argon conditions.9. The method of forming the dielectric layer according to claim 1 , wherein the post-nitridation process is performed with less than 10% oxygen.10. The method of forming the dielectric layer according to claim 9 , wherein the post-nitridation process is performed with less than 1% oxygen in nitrogen.11. The method of forming the dielectric layer according to ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a stack structure on the interfacial layer; patterning the stack structure to form a gate structure on the interfacial layer; forming a liner on the interfacial layer and the gate structure; and removing part of the liner and part of the interfacial layer for forming a spacer. 1. A method for fabricating semiconductor device , comprising:providing a substrate;forming an interfacial layer on the substrate;forming a stack structure on the interfacial layer;patterning the stack structure to form a gate structure on the interfacial layer;forming a liner on the interfacial layer and the gate structure; andremoving part of the liner and part of the interfacial layer for forming a spacer.2. The method of claim 1 , wherein the interfacial layer comprises silicon dioxide.3. The method of claim 1 , wherein the stack structure comprises a high-k dielectric layer claim 1 , a bottom barrier metal (BBM) layer on the high-k dielectric layer claim 1 , a silicon layer on the BBM layer claim 1 , and a hard mask on the silicon layer.4. The method of claim 3 , wherein the BBM layer comprises TiN.5. The method of claim 3 , wherein the silicon layer comprises amorphous silicon or polysilicon.6. The method of claim 1 , wherein the liner comprises silicon dioxide or silicon nitride.7. The method of claim 1 , further comprising etching back part of the liner and part of the interfacial layer for forming the spacer sitting on the interfacial layer.8. The method of claim 1 , further comprising etching back part of the liner and part of the interfacial layer for forming the spacer so that the edge of the interfacial layer is aligned with the edge of the spacer.9. A semiconductor device claim 1 , comprising:a substrate;an interfacial layer on the substrate;a gate structure on the interfacial layer; anda spacer adjacent to the ...

METHOD OF FABRICATING AN OPTICAL MODULE INCLUDING A LENS ATTACHED TO A PLATFORM OF THE OPTICAL MODULE

A method of fabricating an optical module includes attaching a lens to a platform of the optical module such that the lens remains in precise alignment with a light source (e.g., a laser diode) and a target optical fiber even after the lens is attached or fixed to the platform. The optical module includes a micro-lens assembly, comprising a bridge and a micro-lens holder holding a micro-lens. The micro-lens holder is initially to the light source to substantially optimize coupling of light into the input aperture of the optical fiber. Next, the bridge is inserted beneath the micro-lens holder on the platform. Subsequently, the bridge is fixedly attached to the platform. The micro-lens holder is realigned to the light source to substantially optimize coupling of light into the input aperture of the optical fiber and then the micro-lens holder is fixedly attached to the bridge.

Semiconductor having isolated gate structure

A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A semiconductor device includes an interfacial layer on a substrate and agate structure on the interfacial layer. Preferably, the gate structure includes a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a horizontal direction width of the interfacial layer are different. The semiconductor device also includes a first spacer adjacent to the gate structure and on part of the interfacial layer and contacting a top surface of the interfacial layer and a second spacer on the sidewalls of the first spacer and the interfacial layer. Preferably, a planar bottom surface of the second spacer is lower than a planar bottom surface of the first spacer and extending along a same direction as the planar bottom surface of the first spacer. 1. A semiconductor device , comprising:an interfacial layer on a substrate;a gate structure on the interfacial layer, wherein the gate structure comprises a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a horizontal direction width of the interfacial layer are different, wherein the horizontal direction width of the patterned high-k dielectric layer is taken in a horizontal direction from the substrate;a first spacer adjacent to the gate structure and on part of the interfacial layer and contacting a top surface of the interfacial layer; anda second spacer on the sidewalls of the first spacer and the interfacial layer, wherein a planar bottom surface of the second spacer is lower than a planar bottom surface of the first spacer and extending along a same direction as the planar bottom surface of the first spacer.2. The semiconductor device of claim 1 , wherein the interfacial layer comprises silicon dioxide.3. The semiconductor device of claim 1 , wherein the gate structure ...

In situ conversion process systems utilizing wellbores in at least two regions of a formation

A system for heating a subsurface formation is described. The system includes a plurality of elongated heaters located in a plurality of openings in the formation. At least two of the heaters are substantially parallel to each other for at least a portion of the lengths of the heaters. At least two of the heaters have first end portions in a first region of the formation and second end portions in a second region of the formation. A source of time-varying current is configured to apply time-varying current to at least two of the heaters. The first end portions of at least two heaters are configured to have substantially the same voltage applied to them. The second portions of at least two heaters are configured to have substantially the same voltage applied to them.

Semiconductor device and method of forming the same

The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor and the second transistor are disposed on the substrate. The first transistor includes a first channel and a first work function layer. The second transistor includes a second channel and a second work function layer, where the first channel and the second channel include different dopants, and the second work function layer and the first work function layer have a same conductive type and different thicknesses.

Grouped exposed metal heaters

A system for treating a hydrocarbon containing formation is described. The system includes two or more groups of elongated heaters. The group includes two or more heaters placed in two or more openings in the formation. The heaters in the group are electrically coupled below the surface of the formation. The openings include at least partially uncased wellbores in a hydrocarbon layer of the formation. The groups are electrically configured such that current flow through the formation between at least two groups is inhibited. The heaters are configured to provide heat to the formation.

Grouped exposed metal heaters

A system for treating a hydrocarbon containing formation is described. The system includes two or more groups of elongated heaters. The group includes two or more heaters placed in two or more openings in the formation. The heaters in the group are electrically coupled below the surface of the formation. The openings include at least partially uncased wellbores in a hydrocarbon layer of the formation. The groups are electrically configured such that current flow through the formation between at least two groups is inhibited. The heaters are configured to provide heat to the formation.

Semiconductor device having spacer with tapered profile

A semiconductor device is disclosed. The semiconductor device includes a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the bottom of the spacer includes a tapered profile and the tapered profile comprises a convex curve.

METHODS FOR PRODUCING OIL AND/OR GAS

A method for producing oil and/or gas comprising injecting a miscible enhanced oil recovery formulation into fractures, karsts, and/or vugs of a formation for a first time period from a first well; producing oil and/or gas from the fractures, karsts, and/or vugs from a second well for the first time period; injecting a miscible enhanced oil recovery formulation into the fractures, karsts, and/or vugs for a second time period from the second well; and producing oil and/or gas from the fractures, karsts, and/or vugs from the first well for the second time period.

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a stack structure on the interfacial layer; patterning the stack structure to form a gate structure on the interfacial layer; forming a liner on the interfacial layer and the gate structure; and removing part of the liner and part of the interfacial layer for forming a spacer.

Semiconductor device and method of fabricating the same

A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, an interconnect structure, and an oxide semiconductor structure. The substrate has a first region and a second region. The interconnect structure is disposed on the substrate, in the first region. The oxide semiconductor structure is disposed over a hydrogen blocking layer, in the second region of the substrate.

Method for forming semiconductor device

The present invention provides a method of forming a semiconductor device. First, a substrate having a first insulating layer formed thereon is provided. After forming an oxide semiconductor layer on the first insulating layer, two source/drain regions are formed on the oxide semiconductor layer. A bottom oxide layer is formed to entirely cover the source/drain regions, following by forming a high-k dielectric layer on the bottom oxide layer. Next, a thermal process is performed on the high-k dielectric layer, and a plasma treatment is performed on the high-k dielectric layer in the presence of a gas containing an oxygen element.

Method of fabricating an optical module including a lens attached to a platform of the optical module

A method of fabricating an optical module includes attaching a lens to a platform of the optical module such that the lens remains in precise alignment with a light source (e.g., a laser diode) and a target optical fiber even after the lens is attached or fixed to the platform. The optical module includes a micro-lens assembly, comprising a bridge and a micro-lens holder holding a micro-lens. The micro-lens holder is initially to the light source to substantially optimize coupling of light into the input aperture of the optical fiber. Next, the bridge is inserted beneath the micro-lens holder on the platform. Subsequently, the bridge is fixedly attached to the platform. The micro-lens holder is realigned to the light source to substantially optimize coupling of light into the input aperture of the optical fiber and then the micro-lens holder is fixedly attached to the bridge.

Method of Forming High-K Gates Dielectrics

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; injecting a first precursor and forming an interfacial layer on the substrate; and injecting a second precursor and performing a thermal treatment for forming an interface layer on the interfacial layer.

Semiconductor device and method for fabricating the same

A semiconductor device is disclosed. The semiconductor device includes: a substrate having a metal-oxide semiconductor (MOS) transistor thereon, and an oxide semiconductor transistor adjacent to the MOS transistor. Preferably, the MOS transistor includes a first gate structure and a source/drain region adjacent to two sides of the gate structure, and the oxide semiconductor transistor includes a channel layer and the top surface of the channel layer is lower than the top surface of the first gate structure of the MOS transistor.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor and the second transistor are disposed on the substrate. The first transistor includes a first channel and a first work function layer. The second transistor includes a second channel and a second work function layer, where the first channel and the second channel include different dopants, and the second work function layer and the first work function layer have a same conductive type and different thicknesses. 1. A method of forming a semiconductor device , comprising:providing a substrate;forming a dielectric layer on the substrate, wherein the dielectric layer comprises a first gate trench and a second gate trench formed therein;performing a first threshold voltage implantation process in the first gate trench;forming a first work function layer in the first gate trench after the first threshold voltage implantation process; andforming a second work function layer in the second gate trench, and on the first work function layer in the first gate trench, wherein the first work function layer and the second work function layer have a same conductive type.2. The method of forming a semiconductor device according to claim 1 , further comprising:performing a second threshold voltage implantation process in the second gate trench before forming the first work function layer, wherein the second threshold voltage implantation process is performed by implanting different dopants from that of the first threshold voltage implantation process.3. The method of forming a semiconductor device according to claim 1 , further comprising:forming a first dummy gate structure and a second dummy gate structure on the substrate, wherein each of the first dummy gate structure and the second dummy gate structure comprises a dummy gate electrode and an interfacial layer;removing the dummy ...

METHODS FOR PRODUCING OIL AND/OR GAS

A method for producing oil and/or gas comprising injecting a miscible enhanced oil recovery formulation into fractures, karsts, and/or vugs of a formation for a first time period from a first well; producing oil and/or gas from the fractures, karsts, and/or vugs from a second well for the first time period; injecting a miscible enhanced oil recovery formulation into the fractures, karsts, and/or vugs for a second time period from the second well; and producing oil and/or gas from the fractures, karsts, and/or vugs from the first well for the second time period. 1. A method for producing oil from an oil-bearing formation comprising:injecting an enhanced oil recovery formulation and a gas having a density less than the enhanced oil recovery formulation into a first well in the formation;forming a mixture comprising the enhanced oil recovery formulation and the oil in a bottom portion of the formation;forming a gas cap with the injected gas in a top portion of the formation; andproducing the mixture of enhanced oil recovery formulation and oil from the bottom portion of the formation through a second well.2. The method of claim 1 , wherein the first well further comprises a first array of wells claim 1 , and the second well comprises a second array of wells claim 1 , wherein a well in the first array of wells is at a distance of 10 meters to 1 kilometer from one or more adjacent wells in the second array of wells.3. The method of wherein the first array of wells comprises from 5 to 500 wells and the second array of wells comprises from 5 to 500 wells.4. The method of wherein the enhanced oil recovery formulation comprises a miscible enhanced oil recovery formulation claim 1 , further comprising the step of injecting an immiscible enhanced oil recovery formulation into the formation after injecting the miscible enhanced oil recovery formulation into the formation.5. The method of wherein the immiscible enhanced oil recovery formulation is selected from the group ...

Brush container

A brush container includes a box and two support members. The box has a U-shaped frame with two ends each having an end cover; hence, a storage space for containing a brush is defined between the U-shaped frame and two end covers. An upper cover for sealing the storage space is disposed on the top surface of the U-shaped frame. The U-shaped frame has an inner panel, an outer panel corresponding in position to the inner panel, and rib panels disposed between the inner and outer panels to allow a hollowed-out region to be defined between the inner and outer panels and two adjacent rib panels. Hence, despite being lightweight, the box has high structural strength. The two support members are slidably disposed in the storage space. Since their positions are adjustable according to the length of the brush, the two support members provide optimal support to the brush.

BRISTLE BAND WITH DIFFERENT TYPES OF BRISTLES

A bristle band with different types of bristles is provided. The bristle band winds around a rotating shaft and is driven by the rotating shaft to rotate. The bristle band includes: a cord having a receiving slot; a first bristle having a portion disposed in the receiving slot and fixedly connected to the cord; and a second bristle having a portion disposed in the receiving slot and fixedly connected to the cord. With the first bristle and the second bristle being disposed in the cord and a rotating shaft rotating at a constant rotation speed, the bristles passing a cleaning target come in more types than ever, thereby enhancing cleaning efficiency. 1. A bristle band with different types of bristles , the bristle band winding around a rotating shaft and being driven by the rotating shaft to rotate , the bristle band comprising:a cord wound around the rotating shaft and having a receiving slot;a first bristle having a portion disposed in the receiving slot and fixedly connected to the cord; anda second bristle having a portion disposed in the receiving slot and fixedly connected to the cord.2. The bristle band with different types of bristles according to claim 1 , further comprising a batten disposed in the receiving slot claim 1 , with the cord forming a first sidewall and a second sidewall on two opposing sides of the receiving slot claim 1 , such that the first sidewall and the second sidewall correspond in position to each other to clamp the first bristle claim 1 , the second bristle and the batten.3. The bristle band with different types of bristles according to claim 1 , wherein the receiving slot is divided into a first zone and a second zone along the cord lengthwise claim 1 , with the first bristle disposed in the first zone and fixedly connected to the cord claim 1 , and the second bristle disposed in the second zone and fixedly connected to the cord.4. The bristle band with different types of bristles according to claim 1 , wherein the cord forms a first ...

Systems and processes for use in treating subsurface formations

Methods for producing oil and/or gas

A method for producing oil and/or gas comprising injecting a miscible enhanced oil recovery formulation into fractures, karsts, and/or vugs of a formation for a first time period from a first well; producing oil and/or gas from the fractures, karsts, and/or vugs from a second well for the first time period; injecting a miscible enhanced oil recovery formulation into the fractures, karsts, and/or vugs for a second time period from the second well; and producing oil and/or gas from the fractures, karsts, and/or vugs from the first well for the second time period.

A showerhead clean rack and a ultrasonic cleaning method thereof

Systems and processes for use in treating subsurface formations

Systems, methods, and/or heaters for treating subsurfaces formations are described. Some systems and methods generally relate to heaters and heating systems for subsurface formations. Some systems and methods generally relate to novel components used for these heaters and heating systems. Some systems and methods generally relate to barriers and components associated with barriers used in treating subsurface formations. Some systems and methods generally relate to production wells and novel components for producing fluids from subsurface formations.

Grouped exposed metal heaters

Heating system for a subsurface formation

A heating system for a subsurface formation comprising: an electrical conductor; an insulation layer at least partially surrounding the electrical conductor; and a jacket comprising ferromagnetic material, the jacket at least partially surrounding the insulation layer, wherein the jacket is configured to generate a majority of the heat in the heating system when a time-varying electrical current is applied to the heating system.

In situ conversion process systems utilizing wellbores in at least two regions of a formation

In situ conversion process systems utilizing wellbores in at least two regions of a formation

Methods for producing oil and/or gas

A method for producing oil and/or gas comprising injecting a miscible enhanced oil recovery formulation into fractures, karsts, and/or vugs of a formation for a first time period from a first well; producing oil and/or gas from the fractures, karsts, and/or vugs from a second well for the first time period; injecting a miscible enhanced oil recovery formulation into the fractures, karsts, and/or vugs for a second time period from the second well; and producing oil and/or gas from the fractures, karsts, and/or vugs from the first well for the second time period.

Method for producing oil and / or gas

MÉTODO PARA PRODUZIR àLEO E/OU GÁS. Um método para produzir óleo e/ou gás compreendendo injetar uma formulação de recuperação de óleo intensificada miscível em fraturas, carsos e/ou drusas de uma formação, por um primeiro perído de tempo, a partir de um primeiro poço; produzir óleo e/ou gás de fraturas, carsos e/ou drusas de um segundo poço, pelo primeiro período de tempo; injetar uma formulação de recuperação de óleo intensificada miscível nas fraturas, carsos e/ou drusas, por um segundo período de tempo, a partir do segundo poço; e produzir óleo e/ou gás de fraturas, carsos e/ou drusas do primeiro poço, pelo segundo período de tempo. METHOD FOR PRODUCING OIL AND / OR GAS. A method for producing oil and / or gas comprising injecting a miscible intensified oil recovery formulation into fractures, cars and / or druses of a formation for a first period of time from a first well; produce oil and / or gas from fractures, cars, and / or druses from a second well for the first period of time; inject a miscible intensified oil recovery formulation into fractures, cars and / or druses for a second time from the second well; and produce oil and / or gas from fractures, cars, and / or druses from the first well for the second time period.

Methods for producing oil and/or gas

A method for producing oil and/or gas comprising injecting a miscible enhanced oil recovery formulation into fractures, karsts, and/or vugs of a formation for a first time period from a first well; producing oil and/or gas from the fractures, karsts, and/or vugs from a second well for the first time period; injecting a miscible enhanced oil recovery formulation into the fractures, karsts, and/or vugs for a second time period from the second well; and producing oil and/or gas from the fractures, karsts, and/or vugs from the first well for the second time period.

A heating system for a subsurface formation

Systems and methods for producing oil and/or gas

A system for producing oil and/or gas from an underground formation comprising a first array of wells (202) dispersed above the formation; a second array of wells (204) dispersed above the formation; wherein the first array of wells comprises a mechanism to inject a miscible enhanced oil recovery formulation into the formation while the second array of wells comprises a mechanism to produce oil and/or gas from the formation (306) for a first time period; and wherein the second array of wells comprises a mechanism to inject a miscible enhanced oil recovery formulation into the formation (306) while the first array of wells comprises a mechanism to produce oil and/or gas from the formation (306) for a second time period.

Bohrlícher in mindestens zwei bereichen einer formation verwendende in-situ- umwandlungsprozesssysteme