Integrierte Schaltung mit einem Eingangstransistor einschließlich einer Ladungsspeicherstruktur

Eine elektronische Schaltung (100) umfasst einen Eingangsfeldeffekttransistor (102) mit isoliertem Gate. Der Eingangsfeldeffekttransistor (102) mit isoliertem Gate umfasst erste und zweite Lastanschlüsse und einen Steueranschluss. Der Steueranschluss ist elektrisch gekoppelt mit einem Eingangssignalanschluss der elektronischen Schaltung. Die elektronische Schaltung umfasst weiterhin eine Steuerschaltung. Ein Eingangsanschluss der Steuerschaltung ist elektrisch gekoppelt mit dem zweiten Lastanschluss. Der Steueranschluss ist elektrisch verbunden mit einer Steuerstruktur, die eine Steuerelektrode und eine Ladungsspeicherstruktur umfasst.

Floating gate transistors

MOS TRANSISTOR AND MEMORY CELL WITH A-TOTALLY ENCLOSED TUNGSTEN GATES, AND MANUFACTURING PROCESSES

MEMORY CELL UTILIZING NEGATIVE DIFFERENTIAL RESISTANCE FIELD-EFFECT TRANSISTORS

Non-volatile SRAM memory cell and non-volatile semiconductor storage device

A memory structure and a method for manufacture that same

Non-volatile semiconductor memory, and production method for non-volatile semiconductor memory

Provided is a non-volatile semiconductor memory with which process charging damage is eliminated. This non-volatile semiconductor memory is characterized in that: said memory includes a silicon substrate, a first silicon oxide film, a second silicon oxide film, a first silicon nitride film, and a second silicon nitride film; the first silicon oxide film is layered upon the silicon substrate; the first silicon nitride film is layered upon the first silicon oxide film; the second silicon oxide film is layered upon the first silicon nitride film; and the second silicon nitride film is layered such that a first section thereof is in contact with the first silicon nitride film, and a second section thereof is in contact with the silicon substrate.

Semiconductor device, storage device and electronic device

Semiconductor device and manufacturing method thereof

Memory unit and a method of storing information

SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE

3차원 반도체 장치 및 그 제조 방법

... 3차원 반도체 장치 및 그 제조 방법이 제공된다. 이 장치는 수직하게 차례로 적층된 주형막들, 적층된 주형막들 사이에 배치되는 도전 패턴, 적층된 주형막들을 수직하게 관통하는 플러깅 패턴, 도전 패턴과 플러깅 패턴 사이에 배치되는 중간개재 패턴, 그리고 중간개재 패턴에 의해 수직하게 분리되면서 주형막들과 플러깅 패턴 사이에 배치되는 보호막 패턴들을 포함한다.

MULTI-BIT NONVOLATILE MEMORY DEVICE OF NAND STRUCTURE AND MANUFACTURING METHOD THEREOF CAPABLE OF IMPROVING OPERATION SPEED

PURPOSE: A multi-bit nonvolatile memory device of an NAND structure and its manufacturing method are provided to improve operation speed by controlling area of a channel region through a controlling of a height of each fin. CONSTITUTION: A semiconductor substrate(110) includes a body(102) at least one pair of fins(105a,105b) projected upwardly from the body. A first dielectric(125) is formed on the body to gap-fill a spacer between the pair of fins of the semiconductor substrate. Plural control gate electrodes(155a,155b) are extended by crossing the first dielectric and the pair of fins of the semiconductor substrate, cover at least upper portion of an external wall of the fins, and are insulated from the semiconductor substrate. Plural storage nodes(150a,150b) are disposed between the control gate electrodes and the fins of the semiconductor substrate and insulated from the semiconductor substrate. The control gate electrodes are sequentially formed to become two pairs. The control gate ...

SEMICONDUCTOR MEMORY DEVICE

기판 스트레서 영역을 갖는 스플릿 게이트 메모리 셀, 및 이를 제조하는 방법

... 제1 도전형의 반도체 물질의 기판, 기판 내의 제2 도전형의 이격된 제1 영역 및 제2 영역 - 이들 사이의 기판 내에 채널 영역이 있음 -, 기판 위에 있으면서 그로부터 절연되는 도전성 플로팅 게이트 - 플로팅 게이트는 적어도 부분적으로 제1 영역 및 채널 영역의 제1 부분 위에 배치됨 -, 플로팅 게이트에 측방향으로 인접하면서 그로부터 절연되는 도전성 제2 게이트 - 제2 게이트는 적어도 부분적으로 채널 영역의 제2 부분 위에 배치되면서 그로부터 절연됨 -, 및 제2 게이트 아래의 기판 내에 형성되는 임베디드된 탄화규소의 스트레서 영역을 포함하는 메모리 디바이스 및 이를 형성하는 방법.

메모리 셀 및 불휘발성 반도체 기억 장치

... 메모리 게이트 전극(MG) 및 제1 선택 게이트 전극(DG) 간이나, 메모리 게이트 전극(MG) 및 제2 선택 게이트 전극(SG) 간을 이격하도록 하여 하나의 측벽 스페이서(28a) 내 및 다른 측벽 스페이서(28b) 내에 질화 측벽층(32a, 32b)을 각각 형성한 것에 의해, 하나의 측벽 스페이서(28a) 및 다른 측벽 스페이서(28b)를 단순히 절연성 산화막으로 형성한 경우에 비해, 종래보다도 메모리 게이트 전극(MG) 주변에 있어서의 파괴 내압을 향상시킬 수 있고, 또한 전하 축적층(EC)보다도 질화 측벽층(32a, 32b)을 메모리 웰(MW)로부터 멀리 떨어지게 한 것에 의해, 메모리 웰(MW)로부터 전하 축적층(EC)에 전하를 주입할 때, 질화 측벽층(32a, 32b)에 전하가 주입되기 어려워져, 전하 축적층(EC) 이외의 개소에 전하가 축적되어 버리는 것에 의한 동작 문제(failure)를 방지할 수 있는, 메모리 셀 및 불휘발성 반도체 기억 장치를 제안한다.

SEMICONDUCTOR DEVICE INCLUDING A FLOATING GATE AND A CONTROL GATE AND MANUFACTURING METHOD THEREOF

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to improve the electric reliability of a semiconductor device by preventing the metal of a second conductive pattern from being diffused to a dielectric pattern by a first conductive pattern. CONSTITUTION: A charge storage pattern is formed on a substrate. A dielectric pattern(128) is formed on the charge storage pattern. A first conductive pattern(126) is arranged on the dielectric pattern and includes silicon doped with a first impurity of the first density. A second conductive pattern(142) is arranged on the first conductive pattern. The second conductive pattern includes metal silicide doped with a second impurity of the second density. The first density is higher than the second density. COPYRIGHT KIPO 2012 ...

SEMICONDUCTOR DEVICE

SEMICONDUCTOR CHIP, STACK MODULE, AND MEMORY CARD CAPABLE OF EFFICIENTLY ARRANGING PENETRATION ELECTRODES IN A LIMITED SPACE

PURPOSE: A semiconductor chip, stack module, and memory card are provided to increase the capacity of a decoupling capacitor inserted into a semiconductor chip, thereby stabilizing the power in the semiconductor chip. CONSTITUTION: A semiconductor layer includes a first side(106) and a second side which face each other. A conductive layer(130) is arranged on the first side of the semiconductor layer. A penetration electrode(140) penetrates the semiconductor layer and the conductive layer. A sidewall insulating layer electrically insulates the semiconductor layer and the conductive layer from the penetration electrode. COPYRIGHT KIPO 2011 ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

메모리 셀, 반도체 집적 회로 장치 및 반도체 집적 회로 장치의 제조 방법

... 제1 선택 게이트 전극(DG)과 제2 선택 게이트 전극(SG)을 메모리 게이트 구조체(4)의 측벽을 따라서 사이드 월 형상으로 형성하였기 때문에, 제1 선택 게이트 전극(DG) 및 제2 선택 게이트 전극(SG)이 메모리 게이트 구조체(4) 상에 올라타지 않아, 메모리 게이트 구조체(4), 제1 선택 게이트 구조체(5) 및 제2 선택 게이트 구조체(6)의 높이를 고르게 할 수 있어, 그만큼, 종래보다도 소형화를 도모할 수 있고, 또한 제1 선택 게이트 전극(DG) 상의 실리사이드층(S1)이나, 제2 선택 게이트 전극(SG) 상의 실리사이드층(S2)을 캡막(CP1)의 막 두께분만큼 메모리 게이트 전극(MG)으로부터 멀어지게 할 수 있으므로, 메모리 게이트 전극(MG)에 대하여 제1 선택 게이트 전극(DG) 상 및 제2 선택 게이트 전극(SG) 상의 실리사이드층(S1, S2)이 접촉되기 어려워져, 그만큼, 메모리 게이트 전극(MG)의 쇼트 불량을 방지할 수 있는, 반도체 집적 회로 장치 및 반도체 집적 회로 장치의 제조 방법을 제안한다.

INTER-STACK PLUG IN THREE-DIMENSIONAL MEMORY ELEMENT AND METHOD OF FORMING SAME

Erasable programmable nonvolatile memory

NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF

Semiconductor devices and methods of fabricating the same

A semiconductor device includes a semiconductor substrate having a plurality of active regions defined by a trench. A gate electrode crosses the plurality of active regions. A plurality of charge storing cells is disposed between the gate electrode and each of the plurality of active regions. A porous insulating layer is disposed between the gate electrode and the plurality of charge storing cells. The porous insulating layer includes a portion extended over the trench. An air gap is disposed between the extended portion of the porous insulating layer and a bottom surface of the trench.

Method for manufacturing semiconductor integrated circuit device, and semiconductor integrated circuit device

Proposed are a semiconductor integrated circuit device production method and a semiconductor integrated circuit device in which when forming, in a production process, first selection gate electrodes (G2a, G2b) and second selection gate electrodes (G3a, G3b) that can be independently controlled, there is no need to further separately add an extra dedicated photomask step for electrically separating the first selection gate electrodes (G2a, G2b) and the second selection gate electrodes (G3a, G3b) in addition to a conventional dedicated photomask process for processing only a memory circuit area, thereby making it possible to reduce production costs.

Integrated chip and formation method thereof

Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct-strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

SILICON NITRIDE ETCHING LIQUID COMPOSITION

Semiconductor device

Flash memory structure and method of making the same

SINGLE-GATE NON-VOLATILE FLASH MEMORY CELL, MEMORY DEVICE, AND MANUFACTURING METHOD THEREOF

A single-gate non-volatile flash memory cell, a memory device including the memory cell, and a manufacturing method thereof are provided. The memory cell includes a semiconductor structure and a movable switch(200), wherein the semiconductor structure includes a floating-gate structure, and an interlayer dielectric layer(130) with an opening(1204) through which the floating-gate structure is exposed; the movable switch(200) includes a support component(210) and a conductive interconnection component(220),the support component(210) is located on the periphery of the conductive interconnection component(220) and connected with the interlayer dielectric layer(130), and the conductive interconnection component(220) is floating over the opening(1024). When a voltage is applied to the conductive interconnection component(220), the conductive interconnection component(220) is electrically connected with the floating-gate structure, so that the advantages of simple control circuit, low manufacturing ...

Scalable two transistor memory device

A Scalable Two-Transistor Memory (STTM) cell array having a 4F2 unit cell area, where F is the minimum feature size. The data lines and the bit lines alternate and are adjacent to each other along the Y-axis direction, and the word lines are laid out along the X-axis direction. Each STTM cell consists of a floating gate MOS sensing transistor at the surface of a semiconductor substrate, with a vertical double sidewall gate multiple tunnel junction barrier programming MOS transistor on top of the sensing transistor. A data line connects all source regions of the programming transistors and a bit line connects all the source/drain regions of the sensing transistors in a column direction. A word line connects all double sidewall gate regions of programming transistors in a row direction. This invention also deals with a column addressing circuit as well as the driving method for the circuit.

Method and apparatus for producing a single polysilicon flash EEPROM having a select transistor and a floating gate transistor

Accordingly, exemplary embodiments of the present invention are directed to single poly flash EEPROM cells which avoid the drawbacks of conventional two poly stacked gate cells, and which are easily integrated with high performance logic technologies. An exemplary two transistor flash-EEPROM memory cell array comprises a plurality of these flash EEPROM cells, each having a select transistor with a bit line and a word line, where the select transistor is in series with a floating gate transistor. The floating gate transistor has a thin tunneling oxide formed on a textured monocrystalline substrate. The floating gate is also formed over a heavily doped region in the substrate which forms a coupling line capacitively coupled to the floating gate, and which performs a tunneling function.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICE

A semiconductor device includes first and second gate electrodes, a semiconductor layer between the first and second gate electrodes and extending along a first direction, a first gate insulating layer between the first gate electrode and the semiconductor layer, a second gate insulating layer between the second gate electrode and the semiconductor layer, a first insulating layer including a first region adjacent to the first gate electrode in the first direction and contacting the semiconductor layer, and a second insulating layer extending including a second region adjacent to the second gate electrode in the first direction and contacting the semiconductor layer. An interface between the first region and the semiconductor layer in a direction crossing the first direction is adjacent to the first gate electrode in the first direction.

Nonvolatile semiconductor memory device and method of manufacturing the same

A nonvolatile semiconductor memory device, wherein a poly-silicon film is formed on the entire surface of a memory cell region and a peripheral circuit region, and the poly-silicon film on an element isolating insulation film between the gate insulation films of the memory cell region is selectively removed to form a floating gate base layer. Subsequently, an ONO film is formed on the entire surface, and the poly-silicon film and the ONO film is removed from the peripheral circuit region. A conductive film is then formed on the entire surface, a control gate and a floating gate patterned, and a gate electrode then patterned, although at this point, the ONO film and the poly-silicon film are removed from a boundary region, and when the gate electrode is formed, the element isolating insulation film is carved out and a groove is formed in the region where the conductive film is removed by etching.

Method for integrating a non-volatile memory (NVM)

A feature is formed in the NVM isolation region during the patterning and etching of an NVM device and a logic device such that the feature is of substantially equal height to the logic device and is well-defined so that it does not cause defect signals. A first conductive layer is formed over a substrate. The first conductive layer is patterned to expose at least a portion of the substrate in an NVM region and at least a portion of an isolation region. An NVM dielectric stack is formed over the first conductive layer, the exposed substrate, and the exposed isolation region, and a second conductive layer is formed over the NVM dielectric stack. The first and second conductive layers and the NVM dielectric stack are patterned to form a first gate and a second gate of an NVM cell in the NVM region and a feature over the isolation region. The feature comprises a portion of the first conductive layer, a portion of the NVM dielectric stack adjacent a first sidewall of the portion of the first ...

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similarly to the plurality of first memory cells.

HIGH PERFORMANCE MOSFET

The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first ...

Non-volatile memories and methods of fabrication thereof

Non-volatile memories and methods of fabrication thereof are described. In one embodiment, a method of fabricating a semiconductor device includes forming an oxide layer over a semiconductor substrate, and exposing the oxide layer to a first nitridation step to form a first nitrogen rich region. The first nitrogen rich region is disposed adjacent an interface between the oxide layer and the semiconductor substrate. After the first nitridation step, the oxide layer is exposed to a second nitridation step to form a second nitrogen rich region. A first gate electrode is formed on the oxide layer, wherein the second nitrogen rich region is disposed adjacent an interface between the oxide layer and the first gate electrode.

SINGLE-POLY NONVOLATILE MEMORY UNIT

A single-poly non-volatile memory unit includes: a semiconductor substrate having a first conductivity type; first, second and third OD regions disposed on the semiconductor substrate and separated from each other by an isolation region, wherein the first OD region and the second OD region are formed in a first ion well, and the first ion well has a second conductivity type; a first memory cell disposed on the first OD region, a second memory cell disposed on the second OD region. The first memory cell and the second memory cell exhibit an asymmetric memory cell layout structure with respect to an axis. An erase gate is disposed in the third OD region.

MEMORY CELL HAVING CLOSED CURVE STRUCTURE

A memory cell for a printhead includes a substrate with a source and a drain. The substrate further includes a channel located between the source and the drain and surrounding the drain. The drain can include a first rounded closed curved structure. The memory cell can include a floating gate and a control gate. The floating gate can include a second rounded closed curve structure located above the channel and below the control gate. The control gate is capacitively coupled to the floating gate.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Reliability of a semiconductor device is improved. In a method of manufacturing a semiconductor device, nitrogen is introduced into a surface of a substrate and a sacrificial film is formed on the surface in a field effect transistor formation region different from a memory transistor formation region. Subsequently, the sacrificial film is removed to remove the nitrogen introduced in the surface of the substrate in the field effect transistor formation region.

Non-volatile memory device

The present invention includes a method of fabricating a non-volatile memory device having two transistors for two-bit operations to improve electron trapping efficiency and integration degree of the non-volatile memory device, and a method of driving the non-volatile memory device. The EEPROM device acccording to the present invention comprises a silicon substrate including a first and a second channel area, a first and a second conductive gate on the first and the second channel area, respectively, facing each other, a first and a second insulation layer in the bottom of the first and the second gate, and a first and a second junction area of a second conductive type between the first and the second channel area overlapping with the first and the second conductive gate.

CONVEX SHAPED THIN-FILM TRANSISTOR DEVICE HAVING ELONGATED CHANNEL OVER INSULATING LAYER

The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines and in a groove in the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed.

FLASH MEMORY STRUCTURE

Semiconductor structures are provided. The semiconductor structure includes a substrate and a first gate electrode formed over the substrate. The semiconductor structure further includes a dielectric layer formed on a sidewall of the first gate electrode and a second gate electrode formed over the substrate and separated from the first gate electrode by the dielectric layer. The semiconductor structure further includes a contact formed over the second gate electrode. In addition, the contact has a first extending portion and a second extending portion extending along opposite sidewalls of the second gate electrode.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

To improve the reliability of a semiconductor device. In particular, the reading of incorrect information from a memory cell is suppressed. A first low-concentration region is formed in a well, and is located under a side wall insulating film in a planar view. The first low-concentration region has a second conductivity type, and the second conductivity-type impurity concentration is lower than the impurity concentration in a drain. A second low-concentration region is formed in the well, and is located under a spacer insulating film in a planar view. In addition, a second conductivity type impurity concentration in the second low-concentration region is lower than the second conductivity-type impurity concentration in the first low-concentration region, and is higher than the second conductivity-type impurity concentration in a portion located under the insulating film of the well.

Semiconductor Device Having Features to Prevent Reverse Engineering

An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the first layer; a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device.

Three-dimensional semiconductor devices including vertical structures

A three-dimensional semiconductor device is provided including a gate electrode disposed on a substrate and having a pad region, a cell vertical structure passing through the gate electrode, a dummy vertical structure passing through the pad region, and a gate contact plug disposed on the pad region. The cell vertical structure includes a cell pad layer disposed on a level higher than that of the gate electrode and a cell channel layer opposing the gate electrode, the dummy vertical structure includes a buffer region formed of a material different from that of the cell pad layer and a dummy channel layer formed of a material the same as that of the cell channel layer, and at least a portion of the buffer region is located on the same plane as at least a portion of the cell pad layer.

Contact-to-gate monitor pattern and fabrication thereof

A method includes forming a shallow trench isolation (STI) region in a semiconductor substrate, the STI region bordering an active region in the semiconductor substrate; forming a plurality of gate structures over the semiconductor substrate; and forming a plurality of conductive contacts between the gate structures and in contact with the STI region, wherein a portion of the active region is between the conductive contacts.

Semiconductor device having features to prevent reverse engineering

It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.

Flash memory structure with enhanced floating gate

In some embodiments, the present disclosure relates to a flash memory structure. The flash memory structure has a source region and a drain region disposed within a substrate. A select gate is disposed over the substrate between the source region and the drain region, and a floating gate is disposed over the substrate between the select gate and the source region. A control gate is disposed over the floating gate. The floating gate has sidewalls that define protrusions extending downward from a lower surface of the floating gate to define a recess within a bottom of the floating gate.

Semiconductor device

A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a first dielectric layer covering on the oxide-semiconductor layer and the source/drain regions, a second gate between the two source/drain regions and partially covering the oxide-semiconductor layer, and a charge storage structure between the first gate electrode and the oxide-semiconductor layer.

FINFET stack gate memory and method of forming thereof

A method of forming a FinFET stack gate memory includes a nitride film forming step, a nitride film is formed on a memory cell area with a shallow trench isolation (STI) structure; a stripping step, a portion of the nitride film is stripped, the other portion of the nitride film is remained at the STI structure, and a STI oxide is disposed in the STI structure; a floating gate (FG) structure forming step, a tunnel oxide is disposed, and a first polysilicon is disposed to form a FG structure; an oxide-nitride-oxide (ONO) layer disposing step, a portion of the STI oxide is stripped, and an ONO layer is disposed; a removing step, a portion of the ONO layer is removed; a control gate (CG) structure forming step, a portion of the FG structure is removed, and a second polysilicon is disposed to form a CG structure.

Charge trapping devices with field distribution layer over tunneling barrier

A memory cell (100) comprising: a semiconductor substrate (104) with a surface with a source region (102) and a drain region (103) disposed below the surface of the substrate and separated by a channel region 'L'; a tunnelling barrier dielectric structure (105) with an effective oxide thickness of greater than 3 nanometers disposed above the channel region; a conductive layer (101) disposed above the tunnelling barrier dielectric structure (105) and above the channel region 'L'; a charge trapping structure (106) disposed above the conductive layer (101) and above the channel region 'L'; a top dielectric structure (107) disposed above the charge trapping structure (106) and above the channel region 'L'; and a top conductive layer (108) disposed above the top dielectric structure (107) and above the channel region 'L' are described along with devices thereof and methods for manufacturing.

VARIABLE NEGATIVE DIFFERENTIAL RESISTANCE DEVICE COMPATIBLE WITH CMOS, AND ITS OPERATION METHOD

PROBLEM TO BE SOLVED: To provide a new NDR device which is similar to a tunnel diode showing negative differential resistance(NDR) and in which a tunneling between bands is not the only physical mechanism to negative differential resistance characteristic. SOLUTION: This semiconductor transistor device is a semiconductor transistor device including a threshold voltage which is dynamically changed and inverted. The threshold voltage can be controlled by using a control signal received with the semiconductor transistor device. The semiconductor transistor device can be operated by a negative differential resistance mode. COPYRIGHT: (C)2002,JPO ...

Halbleiterspeichervorrichtungen

Eine Halbleiterspeichervorrichtung weist eine Stapelstruktur (SS) auf, welche eine Mehrzahl von Schichten (L1 - L4) aufweist, welche vertikal auf einem Substrat (100) gestapelt sind. Jede der Mehrzahl von Schichten (L1 - L4) weist eine erste dielektrische Schicht (ILD1), eine Halbleiterschicht (SL) und eine zweite dielektrische Schicht (ILD2) auf, welche aufeinanderfolgend gestapelt sind, und eine erste leitfähige Leitung (CL1) in der zweiten dielektrischen Schicht (ILD2) und sich in einer ersten Richtung (D1) erstreckend. Die Vorrichtung weist ebenso eine zweite leitfähige Leitung (CL2) auf, welche sich vertikal durch die Stapelstruktur (SS) erstreckt und einen Kondensator in der Stapelstruktur (SS) und beabstandet von der zweiten leitfähigen Leitung (CL2). Die Halbleiterschicht (SL) weist Halbleiterstrukturen (SP) auf, welche sich in einer zweiten Richtung (D2) erstrecken, welche die erste Richtung (D1) zwischen der ersten leitfähigen Leitung (CL1) und dem Substrat (100) schneidet. Die ...

Halbleiterbauelement, bei dem die Tunnelgateelektrode und die Kanalgateelektrode an der Grenzfläche zum Tunneldielektrikum bzw. Gatedielektrikum durch eine Isolationsstruktur unterbrochen sind

MOS-TRANSISTOR UND SPEICHERZELLE MIT EINGEKAPSELTER WOLFRAM-GATE, UND HERSTELLUNGSVERFAHREN

NICHTFLÜCHTIGE SPEICHERANORDNUNG MIT SCHWEBENDEM GATE UND VERFAHREN ZUR HERSTELLUNG

A flash memory device having a bipolar transistor associated therewith and a method of manufacture therefore

SEMICONDUCTOR DEVICE

... 1423449 Semiconductor devices STANDARD TELEPHONES & CABLES Ltd 27 July 1973 35831/73 Heading H1K An IGFET having an additional region 3 (Fig. 2) between the source and drain regions 4, 2, all three regions 2-4 being of p-type conductivity (in an n-type substrate 1), has a first externally contacted gate electrode 10 between the regions 4 and 3 and a second floating gate electrode 13 between the regions 3 and 2. Both the gate electrodes 10, 13 are embedded in the gate insulation 5.

Methods of forming semiconductor structures

Nonvolatile memory device and method for fabricating the same

The present invention discloses a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device includes gate structures formed over a substrate, each gate structure including a tunnel insulating layer, a floating gate, an inter-gate dielectric layer, and a control gate that are sequentially stacked, a protective layer formed on sidewalls of the floating gate, and a second insulating layer covering the gate structures and having an air gap formed between the gate structures, wherein an adhesive strength between the second insulating layer and the protective layer is smaller than an adhesive strength between the second insulating layer and the gate structure.

Integrated memory circuit for binary data incorporating a single transistor and with hybrid performance alternating between conventional DRAM and flash memory cells

Le circuit intégré de mémoire comprend au moins une cellule-mémoire formée d'un seul transistor dont la grille (GR) possède une face inférieure isolée de la région de canal (RC) par une couche d'isolation (CIS) comportant une succession de puits de potentiels (ND) sensiblement disposés à distance de la grille et de la région de canal dans un plan sensiblement parallèle à la face inférieure de la grille. Les puits de potentiel (ND) sont aptes à contenir une charge électrique confinée dans ledit plan et déplaçable sur commande dans ledit plan vers une première région de confinement voisine de la région de source (RS) ou vers une deuxième région de confinement voisine de la région de drain (RD), de façon à définir deux états mémoire pour la cellule.

MEMORY CELL CONTROL GATES COMPRISING HORIZONTAL AND VERTICAL NON-SELF-ALIGNED

L'invention concerne une cellule mémoire (C31) comprenant une grille de sélection verticale (SG) s'étendant dans une tranchée (10) pratiquée dans un substrat, une grille flottante (FG) s'étendant au-dessus du substrat, et une grille de contrôle horizontale (CG) s'étendant au-dessus de la grille flottante (FG), dans laquelle la grille flottante (FG) s'étend également au-dessus d'une partie de la grille de sélection verticale (SCG) sur une distance de recouvrement (Dov) non nulle. Application notamment à la réalisation d'une cellule mémoire à grille divisée programmable par injection d'électrons chauds.

전압 검출기, 기준 전압 설정 방법 및 프로그램

... 입력 전압이 미리 정해진 역치 전압 이상인지 여부를 검출하는 전압 검출기이며, 기준 전압을 생성하는 기준 전압 생성부와, 입력 전압 및 기준 전압이 입력되고, 입력 전압이, 기준 전압에 의해 정해지는 역치 전압 이상인지 여부를 검출하는 비교기를 구비하고, 기준 전압 생성부는, 컨트롤 게이트 및 플로팅 게이트를 갖는 제1 기입 MOS 트랜지스터와, 제2 기입 MOS 트랜지스터와, 제1 출력 MOS 트랜지스터와, 제2 출력 MOS 트랜지스터를 갖는 전압 검출기를 제공한다.

기억 회로

... 단시간의 전원 정지에 의해 소비 전력을 억제할 수 있고, 전원 재개 시에 있어서 오동작을 일으키지 않고 초기화할 수 있는 신호 처리 장치의 기억 회로의 제공을 목적 중 하나로 한다. 기억 회로에 전원이 공급되지 않는 사이에는, 휘발성 기억부에 기억하고 있었던 데이터 신호를 불휘발성 기억부에 유지한다. 불휘발성 기억부에서는 오프 전류가 극히 작은 트랜지스터를 사용함으로써, 용량 소자에 유지된 데이터 신호는 장기간에 걸쳐 유지한다. 이렇게 하여 불휘발성 기억부는 전원의 공급이 정지한 사이에도 논리 상태를 유지한다. 또한, 전원 정지 시에 용량 소자에서 유지된 데이터 신호는, 전원 재개 시에는 리셋 회로를 도통 상태로 함으로써, 오동작을 일으키는 일이 없는 전위로 한다.

Method of manufacturing a split gate non-volatile flash memory cell

반도체 기억 장치 및 반도체 기억 소자

... (과제) 소자의 면적을 증대시키지 않고, 또한 컨트롤 게이트 전압을 제어하지 않아도, 저전압으로 기록량을 대폭으로 늘리는 것이 가능하고, 또 안정적으로 충분한 기록을 실시하는 것이 가능한 불휘발성 반도체 장치를 제공하는 것. (해결 수단) 드레인 애벌란시 핫 일렉트론에 의해 기록을 실시하는 반도체 기억 소자로서, 제 1 도전형의 반도체 기판에 형성된 제 2 도전형의 제 1 반도체층과, 상기 제 1 반도체층 상에 절연막을 개재하여 형성된 플로팅 게이트와, 상기 플로팅 게이트 하부의 상기 제 1 반도체층의 표면에 형성된 채널 영역과, 상기 채널 영역에 접촉하도록 상기 제 1 반도체층 상에 형성된 제 1 도전형의 소스 영역 및 드레인 영역을 갖는 MOS 트랜지스터로서, 상기 채널 영역이 2 종류 이상의 캐리어 농도의 분포를 갖는 반도체 기억 소자로 하였다.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING METHOD

... [PROBLEMS] A semiconductor device and semiconductor device manufacturing method free of a problem attributed to the residue of the conductive material. [MEANS FOR SOLVING PROBLEMS] A semiconductor device comprises a semiconductor substrate having a first region and a second region, an STI element isolation region formed of an element isolation groove formed in the semiconductor substrate and an insulation film with which the element isolation groove is filled in and defining a plurality of active regions of the first region and the second region, a first structure formed over the active region of the first region and the surrounding STI element isolation region and having a first height, and a second structure formed over the active region of the second region and the surrounding STI element isolation region and having a second height smaller than the first height. The surface of the STI element isolation region of the first region is lower than that of the STI element isolation region ...

UNIT PIXEL OF IMAGE SENSOR

Provided by the present invention is a unit pixel which is formed on a substrate and converts incident light into an electrical signal. The unit pixel comprises: a source which is applied with a power voltage and has a silicide layer formed for a metal contact in the upper part; a drain which is formed to be separated from the source and has a silicide layer formed for a metal contact in the upper part; a channel where a current flows by being formed between the source and the drain; an insulation layer which is formed in the upper part of the channel; and a floating gate which has a Nonsal structure having no silicide layer in the upper part in order to facilitate light absorption, is formed in the upper part of the insulation layer in order to be positioned between the source and the drain, and controls the quantity of the current flowing in the channel by an electric field by electron-hole pairs generated by incident light. The body of the unit pixel is floated and the electric field ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

별개의 워드 라인 및 소거 게이트들을 갖는 플래시 메모리를 형성하는 방법

... 비휘발성 메모리 셀을 형성하는 방법은, 기판 내에, 채널 영역을 사이에 한정하는 이격된 제1 및 제2 영역들을 형성하는 단계를 포함한다. 플로팅 게이트가 채널 영역의 제1 부분 위에 그리고 제1 영역의 일부분 위에 형성되는데, 여기서 플로팅 게이트는 제1 영역 위에 배치되는 날카로운 에지를 포함한다. 터널 산화물 층이 날카로운 에지 주위에 형성된다. 소거 게이트가 제1 영역 위에 형성되는데, 여기서 소거 게이트는 날카로운 에지와 면하는 노치를 포함하고, 노치는 터널 산화물 층에 의해 상기 날카로운 에지로부터 절연된다. 워드 라인 게이트가 제2 영역에 인접한 채널 영역의 제2 부분 위에 형성된다. 워드 라인 게이트의 형성은 터널 산화물 층 및 소거 게이트의 형성 이후에 수행된다.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes first gate structures with a first width on a substrate. Second gate structures with a second width which is wider than the first width and one sidewall facing each other are provided on the substrate. First capping insulation patterns are arranged to cover the first gate structures and the second gate structures and to include a first opening part between the second gate structures facing each other. First spacer structures including first spacers and second spacers are provided on the sidewalls of the first capping insulation patterns and one sidewall of the second gate structure exposed on the sidewall of the first opening part. A first impurity region is provided on the substrate between the first spacer structures. The semiconductor device can obtain excellent electrical characteristics. COPYRIGHT KIPO 2018 (AA) First direction (BB) Second direction ...

Etching method and semiconductor manufacturing method

3-D IC device with enhanced contact area

A device includes a substrate with a recess, having a bottom and sides, extending into the substrate from the substrate's upper surface. The sides include first and second sides oriented transversely to one another. A stack of alternating active and insulating layers overlie the substrate's surface and the recess. At least some of the active layers have an upper and lower portions extending along upper and lower planes over and generally parallel to the upper surface and to the bottom, respectively. The active layers have first and second upward extensions positioned along the first and second sides to extend from the lower portions of their respective active layers. Conductive strips adjoin the second upward extensions of the said active layers. The conductive strips can comprise sidewall spacers on the sides of the second upward extensions, the conductive strips connected to overlying conductors by interlayer conductors.

Floating gate non-volatile memory transistor device and intermediate structure for use in making the same

Non-volatile memory transistors have a semiconductor substrate with spaced apart source and drain regions defining a channel, a layer of tunnel oxide over the channel and a conductive layer of carbon nanotubes over the tunnel oxide. In patterning, mesas are formed retaining desired locations of nanotubes as floating gates. The mesas are used for self-aligned implantation of source and drain electrodes. The nanotubes, being deposited as a porous randomly arranged matted layer, allow for etch removal of the support layer so that the nanotubes rest directly on tunnel oxide. The nanotubes are protected with insulative material and a conductive control gate is placed over the nanotube floating gate layer.

Semiconductor device and method of formation

A semiconductor device includes a channel region between a source region and a drain region, a gate over the channel region, a dielectric layer over the gate, a capacitive field plate over the dielectric layer, and a word line electrically coupled to the capacitive field plate.

Semiconductor device

Multi-time programming non-volatile memory

Charge pump apparatus

INTERPENETRATING NETWORKS OF CRYSTALLINE CARBON AND NANO-SCALE ELECTROACTIVE MATERIALS

An interpenetrating network assembly with a network of connected flakes of nano-scale crystalline carbon and nano-scale particles of an electroactive material interconnected with the carbon flakes is provided. The network assemblies are particularly suited for energy storage applications that use metal oxide electroactive materials and a single charge collector or a source and drain. Interpenetrating networks of graphene flakes and metal oxide nanosheets can form independent pathways between source and drain. Nano-scale conductive materials such as metal nanowires, carbon nanotubes, activated carbon or carbon black can be included as part of the conductive network to improve charge transfer.

EEPROM CORE STRUCTURE EMBEDDED WITH BCD PROCESS AND FORMING METHOD THEREOF

Provided are an EEPROM core structure embedded with Bipolar-CMOS-DMOS (BCD) process and a forming method thereof. The EEPROM core structure includes a selection tube and a storage tube connected in series, wherein the selection tube is an LDNMOS transistor. The forming method includes: forming an N trap (12), a P trap (13) and an active area in a semiconductor substrate (10); forming a tunnel injection layer (14) in an active area of a storage tube; forming a gate medium layer (15) on an active area of a selection tube and forming a tunneling medium layer (16) on the active area of the storage area; forming a selection tube gate (17) on the gate medium layer (15) and forming a float gate (18) on the tunneling medium layer (16); successively forming a float gate medium layer (19) and a control gate (20) on the float gate (18); and forming a source area and a drain area (21) of the selection tube and forming a source area (23) and a drain area of the storage tube.

MEMORY DEVICE USING GRAPHENE AND METHOD FOR MANUFACTURING SAME

Provided are a memory device using graphene and a method for manufacturing same. The memory device using graphene comprises: at least one programming electrode arranged so as to intersect with a graphene layer; and a ferroelectric layer interposed between the graphene layer and the programming electrode. Thus, the memory device may have non-volatile properties using a difference in resistances of the graphene layer due to the polarity of a polling voltage applied through the at least one programming electrode. Further, two or more programming electrodes are arranged, and polling voltages of the same polarity or different polarities are applied to each programming electrode, thereby achieving multi-bits. In addition, the method for manufacturing the memory device using graphene involves forming only one ferroelectric layer capable of maintaining polarization through polling, thus enabling an electric field to be continuously applied to the graphene layer contacting the ferroelectric layer ...

FLOATING GATE TRANSISTORS

A floating gate MOS transistor comprises one or more control gates, an active channel, and at least one floating gate disposed between the control gate(s) and the active channel. First and second non-linear resistances couple the floating gate to first and second control voltage sources respectively, the non-linear resistances forming a voltage divider network which sets the operating voltage of the floating gate.

PROGRAMMABLE MEMORY ARRAY STRUCTURE INCORPORATING SERIES-CONNECTED TRANSISTOR STRINGS AND METHODS FOR FABRICATION AND OPERATION OF SAME

A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer, preferably connected together by way of vertical stacked vias.

High voltage transistor with reduced isolation breakdown

Devices and methods for forming a device are disclosed. The device includes a substrate with a device region having a length and a width direction. An isolation region surrounds the device region of which an isolation edge abuts the device region. A transistor is disposed in the device region. The transistor includes a gate disposed between first and second source/drain (S/D) regions. A silicide block is disposed on the transistor. The silicide block covers at least the isolation edge adjacent to the gate. The silicide block prevents formation of a silicide contact at least at the isolation edge adjacent to the gate.

NON-VOLATILE MEMORY DEVICES INCLUDING BLOCKING INSULATION PATTERNS WITH SUB-LAYERS HAVING DIFFERENT ENERGY BAND GAPS

A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.

THERMALLY ASSISTED FLASH MEMORY WITH DIODE STRAPPING

A memory includes an array of memory cells including rows and columns. The memory includes circuitry coupled to the word lines applying a first bias voltage to a first set of spaced-apart locations on a word line or word lines in the array, while applying a second bias voltage different than the first bias voltage, to a second set of spaced-apart locations on the word line or word lines, locations in the first set of spaced-apart locations being interleaved among locations in the second set of spaced-apart locations, whereby current flow is induced between locations in the first and second sets of locations that cause heating of the word line or word lines.

Semiconductor device with floating gate and electrically floating body

Techniques for providing floating body memory devices are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor device comprising a floating gate, a control gate disposed over the floating gate, a body region that is electrically floating, wherein the body region is configured so that material forming the body region is contained under at least one lateral boundary of the floating gate, and a source region and a drain region adjacent the body region.

Semiconductor device and method for fabricating semiconductor device

A semiconductor device including a first dielectric film, a floating gate portion, second and third dielectric films, a control gate portion, and a recess on the side face of the floating gate portion. The second dielectric film for element isolation is embedded between a height position of a lower portion of the side face of the floating gate portion and a height position inside the semiconductor substrate. The third dielectric film covers an upper surface and a side face portion of the floating gate portion up to a height position of an upper surface of the second dielectric film, and on the second dielectric film. A height position of an interface between the second and third dielectric films is between a height position of a center of the recess and a position in a predetermined range below the height position of the center of the recess.

String floating gates with air gaps in between

A method of manufacturing a semiconductor device includes forming a plurality of strings spaced a first distance from each other, each string including first preliminary gate structures spaced a second distance, smaller than the first distance, between second preliminary gate structures, forming a first insulation layer to cover the first and second preliminary gate structures, forming an insulation layer structure to fill a space between the strings, forming a sacrificial layer pattern to partially fill spaces between first and second preliminary gate structures, removing a portion of the first insulation layer not covered by the sacrificial layer pattern to form a first insulation layer pattern, reacting portions of the first and second preliminary gate structures not covered by the first insulation layer pattern with a conductive layer to form gate structures, and forming a capping layer on the gate structures to form air gaps between the gate structures.

Methods of forming a memory structure

A semiconductor device includes memory cells, a first dielectric liner material overlying side surfaces of the memory cells, a high-k dielectric material overlying side surfaces of the first dielectric liner material, a second dielectric liner material overlying side surfaces of the high-k dielectric material, and an additional dielectric material overlying side surfaces of the second dielectric liner material. A memory structure, an electronic system, and a method of forming a memory structure are also described.

SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF SEMICONDUCTOR DEVICE

A semiconductor device having high on-state current and high reliability is provided. The semiconductor device includes, a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; a first conductor and a second conductor over the second oxide; a third oxide over the second oxide; a second insulator over the third oxide; a third conductor located over the second insulator and overlapping with the third oxide; a third insulator in contact with a top surface of the first insulator, a side surface of the first oxide, a side surface of the second oxide, a side surface of the first conductor, a top surface of the first conductor, a side surface of the second conductor, and a top surface of the second conductor; a fourth insulator over the third insulator; a fifth insulator over the fourth insulator; and a sixth insulator over the third conductor, the second insulator, the third oxide and the fifth insulator. The sixth insulator is in contact with a top surface ...

Cobalt titanium oxide dielectric films

Electronic apparatus and methods of forming the electronic apparatus include a cobalt titanium oxide film on a substrate for use in a variety of electronic systems. The cobalt titanium oxide film may be structured as one or more monolayers. The cobalt titanium oxide film may be formed by atomic layer deposition.

Integrated Circuitry and Methods of Forming Transistors

Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped.

SONOS flash cells for embedded memory logic, free of drain turn-on and over-erase

A non-volatile memory apparatus and method of manufacturing the same is disclosed, which uses a silicon-oxide-nitride-oxide-silicon (SONOS) memory cell. The SONOS cell comprises the silicon substrate (S), the dielectric layers of stacked oxide-nitride-oxide (ONO), the gate electrode (S) and the source and drain terminals separated by the gate length. The programming of the cell is done by the injection of channel hot electrons into trap sites in between the oxide and the nitride layer, while erasing is done by discharging those trapped electrons via F-N tunneling. This B/L contacted SONOS cell combines both the inherent advantages of memory operation, free of drain turn-on and over-erase and the ability to harness without modification the existing flash EEPROM technology for mass production. Additionally, this B/L contacted SONOS memory apparatus has practically an identical vertical structure to that of the standard MOSFET, which makes it possible to manufacture high density as well as ...

Methods of Forming Nonvolatile Memory Devices Having Vertically Integrated Nonvolatile Memory Cell Sub-Strings Therein and Nonvolatile Memory Devices Formed Thereby

Methods of forming nonvolatile memory devices according to embodiments of the invention include techniques to form highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.

Semiconductor device and method for manufacturing same

According to one embodiment, a method is disclosed for manufacturing a semiconductor device. A side face parallel to a channel direction of a plurality of gate electrodes provided above a semiconductor substrate is included as a part of an inner wall of an isolation groove provided between the adjacent gate electrodes. The method can include forming a first isolation groove penetrating through a conductive film serving as the gate electrode to reach the semiconductor substrate. The method can include forming a protection film covering a side wall of the first isolation groove including a side face of the gate electrode. The method can include forming a second isolation groove by etching the semiconductor substrate exposed to a bottom surface of the first isolation groove. The method can include oxidizing an inner surface of the second isolation groove provided on each of both sides of the gate electrode to form first insulating films, which are connected to each other under the gate electrode. In addition, the method can include filling an inside of the first isolation groove and an inside of the second isolation groove with a second insulating film.

Semiconductor device and method of manufacturing semiconductor device

A conductive film having a first width in a first direction, an ONO film, and a control gate are formed above a tunnel gate insulating film. With the control gate as a mask, the conductive film is etched to form a floating gate. Then, an inter-layer insulating film is formed. A contact hole whose width in the first direction is larger than the first width is formed in the inter-layer insulating film. Then, sidewall spacer is formed on an inside wall of the contact hole.

Method of forming a non-volatile electron storage memory and the resulting device

The invention provides a method of forming an electron memory storage device and the resulting device. The device comprises a gate structure which, in form, comprises a first gate insulating layer formed over a semiconductor substrate, a self-forming electron trapping layer of noble metal nano-crystals formed over the first gate insulating layer, a second gate insulating layer formed over the electron trapping layer, a gate electrode formed over the second gate insulating layer, and source and drain regions formed on opposite sides of the gate structure.

Nonvolatile Memory Devices, Channel Boosting Methods Thereof, Programming Methods Thereof, And Memory Systems Including The Same

Non-volatile memory device channel boosting methods in which at least two strings are connected to one bit line, the channel boosting methods including applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings each having an un-programmed cell among the strings, and boosting channels of the floated inhibit strings.

Memory device having three-dimensional gate structure

Subject matter disclosed herein relates to a memory device, and more particularly to a nonvolatile memory device having a recess structure and methods of fabricating same.

Patterning a gate stack of a non-volatile memory (nvm) with simultaneous etch in non-nvm area

Forming a gate stack of a non-volatile memory (NVM) over a substrate having an NVM region and non-NVM region which does not overlap the NVM region includes forming a select gate layer over the substrate in the NVM and non-NVM regions; simultaneously etching the select gate layer in the NVM and non-NVM regions; forming a charge storage layer over the substrate in the NVM and non-NVM regions; forming a control gate layer over the charge storage layer in the NVM and non-NVM regions; and simultaneously etching the charge storage layer in the NVM and the non-NVM regions. Etching the select gate layer in the NVM region results in a portion of the charge storage layer over a portion of the select gate layer and overlapping a sidewall of the select gate layer and results in a portion of the control gate layer over the portion of the charge storage layer.

Field effect transistor and method for manufacturing the same

A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A channel layer may be formed on a portion of the gate electrode, with source and drain regions formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions of the FET may be perpendicular to a surface of the semiconductor substrate.

Methods and Apparatus for Detecting Molecular Interactions Using FET Arrays

Methods and apparatuses relating to large scale FET arrays for analyte detection and measurement are provided. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes.

Conductive layers for hafnium silicon oxynitride

Electronic apparatus and methods of forming the electronic apparatus include HfSiON for use in a variety of electronic systems. In various embodiments, conductive material is coupled to a dielectric containing HfSiON, where such conductive material may include one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum.

EEPROM-based, data-oriented combo NVM design

A nonvolatile memory device has a combination of FLOTOX EEPROM nonvolatile memory arrays. Each FLOTOX-based nonvolatile memory array is formed of FLOTOX-based nonvolatile memory cells that include at least one floating gate tunneling oxide transistor such that a coupling ratio of the control gate to the floating gate of the floating gate tunneling oxide transistor is from approximately 60% to approximately 70% and a coupling ratio of the floating gate to the drain region of the floating gate tunneling oxide transistor is maintained as a constant of is from approximately 10% to approximately 20% and such that a channel length of the channel region is decreased such that during the programming procedure a negative programming voltage level is applied to the control gate and a moderate positive programming voltage level is applied to the drain region to prevent the moderate positive programming voltage level from exceeding a drain-to-source breakdown voltage.

Memory arrays where a distance between adjacent memory cells at one end of a substantially vertical portion is greater than a distance between adjacent memory cells at an opposing end of the substantially vertical portion and formation thereof

Memory arrays and their formation are disclosed. One such memory array has a string of series-coupled memory cells with a substantially vertical portion. A distance between adjacent memory cells at one end of the substantially vertical portion is greater than a distance between adjacent memory cells at an opposing end of the substantially vertical portion. For other embodiments, thicknesses of respective control gates of the memory cells and/or thicknesses of the dielectrics between successively adjacent control gates may increase as the distances of the respective control gates/dielectrics from the opposing end of the substantially vertical portion increase.

Integrated non-volatile memory (nvm) and method therefor

A feature is formed in the NVM isolation region during the patterning and etching of an NVM device and a logic device such that the feature is of substantially equal height to the logic device and is well-defined so that it does not cause defect signals. A first conductive layer is formed over a substrate. The first conductive layer is patterned to expose at least a portion of the substrate in an NVM region and at least a portion of an isolation region. An NVM dielectric stack is formed over the first conductive layer, the exposed substrate, and the exposed isolation region, and a second conductive layer is formed over the NVM dielectric stack. The first and second conductive layers and the NVM dielectric stack are patterned to form a first gate and a second gate of an NVM cell in the NVM region and a feature over the isolation region. The feature comprises a portion of the first conductive layer, a portion of the NVM dielectric stack adjacent a first sidewall of the portion of the first conductive layer, and a portion of the second conductive layer adjacent the portion of the NVM dielectric stack.

System comprising a semiconductor device and structure

A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.

Semiconductor storage device and manufacturing method of semiconductor storage device

According to one embodiment, a columnar semiconductor, a floating gate electrode formed on a side surface of the columnar semiconductor via a tunnel dielectric film, and a control gate electrode formed to surround the floating gate electrode via a block dielectric film are provided.

Method of removing nanocrystals

A method for forming a semiconductor structure includes providing a semiconductor layer, forming nanocrystals over the semiconductor layer, and using a solution comprising pure water, hydrogen peroxide, and ammonium hydroxide to remove at least a portion of the nanocrystals. A ratio by volume of pure water to ammonium hydroxide of the solution may be equivalent to or less than a ratio by volume of 10:1 of pure water to ammonium hydroxide when ammonium hydroxide has a concentration of 29% ammonia by weight. The step of using the solution to remove the at least a portion of the nanocrystals may be performed at a temperature of 50 degrees Celsius or more.

Non-volatile memory and fabricating method thereof

A non-volatile memory having a tunneling dielectric layer, a floating gate, a control gate, an inter-gate dielectric layer and a first doping region and a second doping region is provided. The tunneling dielectric layer is disposed on a substrate. The floating gate is disposed on the tunneling dielectric layer, and has a protruding portion. The control gate is disposed over the floating gate to cover and surround the protruding portion. The protruding portion of the floating gate is fully covered and surrounded by the control gate in any direction, including extending directions of bit lines, word lines and an included angle formed between the word line and the bit line. The inter-gate dielectric layer is disposed between the floating gate and the control gate. The first doping region and the second doping region are respectively disposed in the substrate at two sides of the control gate.

Vertical channel type non-volatile memory device and method for fabricating the same

A method for fabricating a vertical channel type non-volatile memory device including forming a source region, alternately forming a plurality of interlayer dielectric layers and a plurality of conductive layers for a gate electrode over a substrate with the source region formed therein, forming a trench exposing the source region by etching the plurality of interlayer dielectric layers and the plurality of conductive layers for a gate electrode, and siliciding the conductive layers for a gate electrode and the source region that are exposed through the trench.

Nonvolatile semiconductor memory device and method of manufacturing the same

According to one embodiment, a nonvolatile semiconductor memory device includes an element region, a gate insulating film, a first gate electrode, an intergate insulating film, a second gate electrode and an element isolation region. The gate insulating film is formed on the element region. The first gate electrode is formed on the gate insulating film. The intergate insulating film is formed on the first gate electrode and has an opening. The second gate electrode is formed on the intergate insulating film and in contact with the first gate electrode via the opening. The element isolation region encloses a laminated structure formed by the element region, the gate insulating film, and the first gate electrode. The air gap is formed between the element isolation region and side surfaces of the element region, the gate insulating film and the first gate electrode.

Ultrahigh density vertical nand memory device and method of making thereof

Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

Ultrahigh density vertical nand memory device and method of making thereof

Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

Floating gate flash cell device and method for partially etching silicon gate to form the same

A method for forming a split gate flash cell memory device provides for establishing a floating gate region then using spacers or other hard mask materials that cover opposed edges of a gate electrode material in the gate region, to serve as hard masks during an etching operation that partially etches the gate electrode material which may be polysilicon. The gate electrode so produced serves as a floating gate electrode and includes a recessed central portion flanked by a pair of opposed upwardly extending fins which may terminate upwardly at an apex. A floating gate oxide is then formed by thermal oxidation and/or oxide deposition techniques.

Twin-Drain Spatial Wavefunction Switched Field-Effect Transistors

A field-effect transistor is provided and includes source, gate and drain regions, where the gate region controls charge carrier location in the transport channel, the transport channel includes a asymmetric coupled quantum well layer, the asymmetric quantum well layer includes at least two quantum wells separated by a barrier layer having a greater energy gap than the wells, the transport channel is connected to the source region at one end, and the drain regions at the other, the drain regions include at least two contacts electrically isolated from each other, the contacts are connected to at least one quantum well. The drain may include two regions that are configured to form the asymmetric coupled well transport channel. In an embodiment, two sources and two drains are also envisioned.

Flash cell with floating gate transistors formed using spacer technology

Methods for forming split gate flash cell structures provide for symmetrical cells that are immune to misalignment of the photoresist pattern when forming the control gates. Spacers are utilized to form the floating gates in the floating gate transistors used in the flash cells. The spacers may be oxide spacers used to mask a polysilicon layer that will form the floating gates or the spacers may be polysilicon spacers that will themselves form the floating gates. The inter-gate oxide of the floating gate transistors may be formed using HTO or may be deposited. Hard mask spacers are used in conjunction with the control gate photoresist patterning operation to control the size and configuration of the control gate and the channel length.

Logic-Based Multiple Time Programming Memory Cell

A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell comprises a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further comprises two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor.

Non-volatile memory cell

The non-volatile memory cell includes a coupling device and a first select transistor. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region. An electrode of the coupling device and a gate of the first floating gate transistor are a monolithically formed floating gate; wherein the first conductivity region and the second conductivity region are formed in a third conductivity region; wherein the first conductivity region, the second conductivity region, and the third conductivity region are wells.

Low Leakage Capacitor for Analog Floating-Gate Integrated Circuits

An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

Split-gate non-volatile memory cells having improved overlap tolerance

Embodiments include a split-gate non-volatile memory cell that is formed having a control gate and a select gate, where at least a portion of the control gate is formed over the select gate. A charge storage layer is formed between the select gate and the control gate. The select gate is formed using a first conductive layer and a second conductive layer. The second conductive layer is formed over the first conductive layer and has a lower resistivity than the first conductive layer. In one embodiment, the first conductive layer is polysilicon and the second conductive layer is titanium nitride (TiN). In another embodiment, the second conductive layer may be a silicide or other conductive material, or combination of conductive materials having a lower resistivity than the first conductive layer.

Nonvolatile memory device and method for fabricating the same

A nonvolatile memory device includes a substrate having active regions that are defined by an isolation layer and that have first sidewalls extending upward from the isolation layer, floating gates adjoining the first sidewalls of the active regions with a tunnel dielectric layer interposed between the active regions and the floating gates and extending upward from the substrate, an intergate dielectric layer disposed over the floating gates, and control gates disposed over the intergate dielectric layer.

Non-volatile memory devices and methods of forming the same

A non-volatile may include a plurality of device isolation patterns disposed in a substrate to define an active region extending in a first direction, a gate pattern disposed on the substrate to extend in a second direction crossing the first direction, a charge storing pattern disposed between the active region and the gate pattern, a blocking dielectric layer disposed between the charge storing pattern and the gate pattern, and a tunnel dielectric layer disposed between the active region and the charge storing pattern. A center area of a top surface of the active region includes one of a rounded surface or a tip, and the center area of the top surface of the active region corresponds to an uppermost portion of the active region and the uppermost portion of the active region is disposed at a level lower than a lowermost portion of the gate pattern.

Structures and Methods of Improving Reliability of Non-Volatile Memory Devices

In one example, the memory device disclosed herein includes a gate insulation layer and a charge storage layer positioned above the gate insulation layer, wherein the charge storage layer has a first width. The device further includes a blocking insulation layer positioned above the charge storage layer and a gate electrode positioned above the blocking insulation layer, wherein the gate electrode has a second width that is greater than the first width. An illustrative method disclosed herein includes forming a gate stack for a memory device, wherein the gate stack includes a gate insulation layer, an initial charge storage layer, a blocking insulation layer and a gate electrode, and wherein the initial charge storage layer has a first width. The method further includes performing an etching process to selectively remove at least a portion of the initial charge storage layer so as to produce a charge storage layer having a second width that is less than the first width of the initial charge storage layer.

Semiconductor device having controllable transistor threshold voltage

In an embodiment, a semiconductor device includes a single-layer gate nonvolatile memory in which a floating gate is formed on a semiconductor substrate. The floating gate is formed above a diffusion layer serving as a control gate of the nonvolatile memory. The diffusion layer may be insulated from the semiconductor substrate by an insulating film such as a silicon oxide film. A pair of diffusion layers may be formed in surface regions of the semiconductor substrate on the two sides of the floating gate extending on a tunnel oxide film in an embodiment. The configuration described herein may realize a reliable semiconductor device in a low-cost process, may have a control gate which may withstand a high voltage applied when data is erased or written, and may prevent an operation error by minimizing variations in the threshold value, in some embodiments.

Semiconductor device and method of manufacturing semiconductor device

A conductive film having a first width in a first direction, an ONO film, and a control gate are formed above a tunnel gate insulating film. With the control gate as a mask, the conductive film is etched to form a floating gate. Then, an inter-layer insulating film is formed. A contact hole whose width in the first direction is larger than the first width is formed in the inter-layer insulating film. Then, sidewall spacer is formed on an inside wall of the contact hole.

Semiconductor structures including bodies of semiconductor material, devices including such structures and related methods

Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. The bodies may be electrically coupled by one or more conductive structures, which may be used as an interconnect structure to electrically couple components of memory devices. By providing isolation between the bodies, the semiconductor structure provides the properties of a conventional SOI substrate (e.g., high speed, low power, increased device density and isolation) while substantially reducing fabrication acts and costs associated with such SOI substrates. Additionally, the semiconductor structures of the present disclosure provide reduced parasitic coupling and current leakage due to the isolation of the bodies by the intervening dielectric material.

Nand type flash memory for increasing data read/write reliability

A NAND type flash memory for increasing data read/write reliability includes a semiconductor substrate unit, a base unit, and a plurality of data storage units. The semiconductor substrate unit includes a semiconductor substrate. The base unit includes a first dielectric layer formed on the semiconductor substrate. The data storage units are adjacent to each other and formed on the first dielectric layer. Each data storage unit includes at least two floating gates formed on the first dielectric layer, a second dielectric layer formed on the first dielectric layer and between the two floating gates, an inter-gate dielectric layer formed on the two floating gates and the second dielectric layer, at least one control gate formed on the inter-gate dielectric layer, and a third dielectric layer formed on the first dielectric layer and surrounding and tightly connecting with the two floating gates, the inter-gate dielectric layer, and the control gate.

Methods and apparatuses including memory cells with air gaps and other low dielectric constant materials

Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. A charge storage element, such as a floating gate or charge trap, is between the first dielectric material and the second dielectric material and adjacent to the conductive material. The charge storage element has a first surface and a second surface. The first and second surfaces are substantially separated from the first dielectric material and the second dielectric material, respectively, by a first air gap and a second air gap. Additional apparatuses and methods are disclosed.

Memory including transistors with double floating gate structures

In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.

ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF

Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. 1. A method of making a monolithic three dimensional NAND string , comprising:forming at least one sacrificial feature over a substrate;forming a stack of alternating layers of a first material and a second material over the at least one sacrificial feature, wherein the first material comprises a conductive or semiconductor control gate material;forming a cut area in the stack to separate the control gate material in a direction substantially perpendicular to a major surface of the substrate, wherein the cut area extends in a first direction substantially parallel to the major surface of the substrate and in a second direction substantially parallel to the major surface of the substrate, wherein the first direction is perpendicular to the second direction;etching the stack to form at least two openings in the stack;forming a blocking dielectric in the at least two openings;forming a charge storage region in the at least two openings over the blocking dielectric;removing the at least one sacrificial feature to form a hollow region extending substantially parallel to a major surface of the substrate which connects the at least two openings to form a hollow U-shaped pipe space comprising the first and the second openings extending substantially perpendicular to the major surface of the substrate connected by the hollow region;forming a tunnel dielectric over a side wall of the ...

HIGH DENSITY SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Provided are a high density semiconductor memory device capable of precisely reading data by suppressing the occurrence of a leakage current due to the high-integration of the semiconductor memory device, and a method for manufacturing the semiconductor memory device. The high density semiconductor memory device includes: source and drain electrodes disposed over a substrate, and forming a Schottky junction with a channel region; and a floating gate disposed over the substrate of the channel region, and configured with a plurality of nanodots. The nanodots may be formed of a silicon compound or any material that can be charged. 1. A high density semiconductor memory device , comprising:source and drain electrodes disposed over a substrate, and forming a Schottky junction with a channel region; anda floating gate disposed over the substrate of the channel region, and configured with a plurality of nanodots.28-. (canceled)9. The high density semiconductor memory device of claim 1 , wherein the source and drain electrodes comprise a material selected from the group consisting of platinum (Pt) claim 1 , lead (Pb) and iridium (Ir) when a hole is used as a majority carrier.10. (canceled)11. A method for manufacturing a high density semiconductor memory device claim 1 , the method comprising the steps of:a) forming a channel region and source and drain electrodes in a substrate, the source and drain electrodes forming a Schottky junction with the channel region;b) forming a tunneling dielectric layer over the substrate;c) forming a floating gate over the tunneling dielectric layer, the floating gate comprising a plurality of nanodots;d) forming a control gate over the floating gate; ande) etching the control gate, the floating gate and the tunneling dielectric layer to expose the source and drain electrodes.1217-. (canceled)18. The method of claim 11 , wherein the source and drain electrodes are formed of a material selected from the group consisting of platinum (Pt) claim ...

THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICES INCLUDING INTERPOSED FLOATING GATES

Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers. 1. A three-dimensional nonvolatile memory device , comprising:semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate;floating gates electrically isolated by the interlayer insulating layers and locally interposed between the semiconductor pillars and the conductive layers;first insulating layers interposed between the floating gates and adjacent sidewalls of the conductive layers; andsecond insulating layers interposed between the floating gates and the semiconductor pillars.2. The three-dimensional nonvolatile memory device of claim 1 , wherein the floating gates are interposed between the interlayer insulating layers adjacent to each other claim 1 , and the first insulating layers are disposed between the floating gates and the interlayer insulating layers by extending from the floating gates and the sidewalls of the conductive layers.3. The three-dimensional nonvolatile memory device of claim 1 , wherein the second insulating layers surround the semiconductor pillars by vertically extending to sidewalls of the interlayer insulating layers from sidewalls of the floating gates.4. The three-dimensional nonvolatile memory device of claim 1 , wherein the conductive layers include selection line conductive layers claim 1 , the second insulating layers are interposed between the selection line conductive layers and the semiconductor pillars claim 1 , and the selection line conductive layers come in directly contact ...

Semiconductor memory device and semiconductor memory element

A semiconductor memory element for writing by a drain-avalanche hot electron includes a MOS transistor having a first semiconductor layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type; a floating gate provided on the first semiconductor layer through intermediation of an insulating film; a channel region formed in a surface of the first semiconductor layer under the floating gate; and a source region and a drain region of the first conductivity type provided on the first semiconductor layer so as to be in contact with the channel region in which the channel region has a distribution of at least two kinds of carrier densities.

Semiconductor device and capacitor

The present invention relates to a semiconductor device including nanodots and a capacitor. A semiconductor device includes a channel layer, a tunnel insulating layer formed on the channel layer, a memory layer formed on the tunnel insulating layer and including first nanodots, a charge blocking layer formed on the memory layer, a gate electrode conductive layer formed on the charge blocking layer, and a buffer layer located, at least one of, inside the tunnel insulating layer, inside the charge blocking layer, at an interface between the tunnel insulating layer and the memory layer and at the interface between the charge blocking layer and the memory layer, wherein the buffer layer includes second nanodots.

FLASH MEMORY CELL WITH FLAIR GATE

An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width. 120.-. (canceled)21. A method of forming a memory cell , the method comprising:etching a trench in a substrate;filling the trench with an oxide to form a shallow trench isolation (STI) region, wherein a portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge;forming a gate structure over the active region of the substrate and over the STI region wherein the gate structure comprises a charge trapping layer; andforming a wordline structure having first and second widths and having portions of the wordline structure of the first width centered above a bit line and portions of the wordline structure of the second width centered above the STI region and formed to extend across the STI region over the bitline-STI edge, wherein the second width is greater than the first width and wherein portions of adjacent wordline structures of the second width extend across separate portions of the same bitline.22. The method as recited in wherein said forming of the gate structure comprises:forming a preliminary gate structure over the substrate;applying a mask over the memory cell, wherein the mask has the first width substantially over the center of the active region of the substrate and the second width substantially over the bitline-STI edge; andetching the ...

Non-volatile memory devices having vertical drain to gate capacitive coupling

Vertically fabricated non-volatile memory devices having capacitive coupling between a drain region and a floating gate. A two terminal programmable non-volatile device includes a floating gate disposed vertically about a substrate, wherein the floating gate comprises a first side, a second side, and a bottom portion. A source region is coupled to a first terminal and formed adjacent to the first side of the floating gate. A drain region is coupled to a second terminal and formed adjacent to the second side of the floating gate. The non-volatile device includes a channel coupling the source region and drain region for programming and erasing operations. The drain region is capacitively coupled to the floating gate.

SEMICONDUCTOR DEVICE

The performance of a semiconductor device including a nonvolatile memory is enhanced. Each of nonvolatile memory cells arranged over a silicon substrate includes: a first n-well; a second n-well formed in a place different from the place thereof; a selection transistor formed in the first n-well; and an electric charge storage portion having a floating gate electrode and a storage portion p-well. The floating gate electrode is so placed that it overlaps with part of the first n-well and the second n-well. The storage portion p-well is placed in the first n-well so that it partly overlaps with the floating gate electrode. In this nonvolatile memory cell, memory information is erased by applying positive voltage to the second n-well to discharge electrons in the floating gate electrode to the second n-well. 111-. (canceled)12. A semiconductor device comprising nonvolatile memory cells arranged over a semiconductor substrate ,wherein each of the nonvolatile memory cells comprises:a first semiconductor region of a first conductivity type formed in the semiconductor substrate and extending along a first direction in plan view;a first gate electrode of a selection transistor formed over the first semiconductor region;a floating gate electrode formed over the first semiconductor region;a third semiconductor region of a second conductivity type opposite to the first conductivity type formed in the first semiconductor region and arranged at one side of the first gate electrode;a fourth semiconductor region of the second conductivity type formed in the first semiconductor region and arranged between another side of the first gate electrode and one side of the floating gate electrode; anda fifth semiconductor region of the second conductivity type formed in the first semiconductor region and arranged at another side of the floating gate electrode,wherein a second semiconductor region of the first conductivity type is formed in the semiconductor substrate and electrically ...

NON-VOLATILE MEMORY SEMICONDUCTOR DEVICE

A technique capable of improving the reliability of a non-volatile memory semiconductor device is provided and, in particular, a technique capable of supplying electricity without fail to a memory gate electrode of split gate transistor is provided. 120-. (canceled)21. A non-volatile memory semiconductor device , comprising:a first memory cell array region;a second memory cell array region; andan electricity supply region sandwiched by the first memory cell array region and the second memory cell array region over a semiconductor substrate,wherein the first memory cell array region, the second memory cell array region, and the electricity supply region are arranged side by side in a first direction,wherein the device includes(a) a first control gate electrode extending along the first direction from the first memory cell array region to the electricity supply region and having a first terminal end disposed within the electricity supply region;(b) a first memory gate electrode formed on a sidewall of the first control gate electrode via a first insulating film and extending in the first direction;(c) a second control gate electrode extending along the first direction from the second memory cell array region to the electricity supply region and having a second terminal end disposed within the electricity supply region; and(d) a second memory gate electrode formed on a sidewall of the second control gate electrode via a second insulating film and extending in the first direction,wherein the first control gate electrode and the second control gate electrode are arranged in a straight line and the first terminal end and the second terminal end are arranged separated from each other,wherein the device further comprises(e) an electricity supply line with one end arranged over the first terminal end and the other end arranged over the second terminal end; and(f) a plug electrically connected with the electricity supply line,wherein the electricity supply line is formed by ...

Logic and non-volatile memory (nvm) integration

A method includes forming a gate dielectric over a substrate in an NVM region and a logic region; forming a first conductive layer over the gate dielectric in the NVM region and the logic region; patterning the first conductive layer in the NVM region to form a select gate; forming a charge storage layer over the select gate in the NVM region and the first conductive layer in the logic region; forming a second conductive layer over the charge storage layer in the NVM region and the logic region; removing the second conductive layer and the charge storage layer from the logic region; patterning the first conductive layer in the logic region to form a first logic gate; and after forming the first logic gate, patterning the second conductive layer in the NVM region to form a control gate which overlaps a sidewall of the select gate.

THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern. 1. A three dimensional semiconductor device comprising:sequentially stacked mold layers;a conductive pattern between the mold layers;a plugging pattern vertically penetrating the mold layers;an intermediate pattern between the conductive pattern and the plugging pattern; andprotective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.2. The three dimensional semiconductor device of claim 1 , wherein the protective layer patterns are different from the mold layers in at least one of a chemical composition claim 1 , a density claim 1 , or an impurity concentration.3. The three dimensional semiconductor device of claim 1 , wherein the protective layer patterns are different from the respective adjacent mold layers in an average vertical thickness.4. The three dimensional semiconductor device of claim 1 , wherein the protective layer patterns and the mold layers are formed of silicon oxide and wherein discontinuous interfaces are respectively formed between sidewalls of the protective layer patterns and the mold layers.5. The three dimensional semiconductor device of claim 1 , wherein the intermediate pattern horizontally extends from between the conductive pattern and the plugging pattern to cover a top surface and a bottom surface of the conductive pattern.6. The three dimensional semiconductor device of claim 1 , wherein the plugging pattern is formed of a semiconductor material claim 1 , and ...

METHODS OF FORMING NON-VOLATILE MEMORY

Methods of forming non-volatile memory is described. The non-volatile memory includes a substrate having a source region, a drain region and a channel region. The channel region separates the source region and the drain region. An electrically insulating layer is adjacent to the source region, drain region and channel region. A floating gate electrode is adjacent to the electrically insulating layer. The electrically insulating layer separates the floating gate electrode from the channel region. The floating gate electrode has a floating gate major surface. A control gate electrode has a control gate major surface and the control gate major surface opposes the floating gate major surface. A vacuum layer or gas layer at least partially separates the control gate major surface from the floating gate major surface. 1. A non-volatile memory unit , comprising:a substrate having a source region, a drain region and a channel region, the channel region separates the source region and the drain region;an electrically insulating layer disposed on the substrate and adjacent to the channel region layer, the electrically insulating layer having a thickness value in a range from 1 to 5 nm;a floating gate electrode disposed on the electrically insulating layer, the electrically insulating layer separating the floating gate electrode from the substrate, the floating gate electrode having a floating gate major surface comprising a first electron field emitter;a control gate electrode having a control gate major surface comprising a second electron field emitter, the control gate major surface opposing the floating gate major surface and defining a void space separating the control gate major surface from the floating gate major surface.2. A non-volatile memory unit according to claim 1 , wherein the void space comprise a vacuum layer having a pressure of 1000 Pa or less.3. A non-volatile memory unit according to claim 2 , wherein the vacuum layer has a thickness value in a range ...

Integrated Circuit Device, System, and Method of Fabrication

A semiconductor device, comprising a first semiconductor portion having a first end, a second end, and a slit portion, wherein the width of the slit portion is less than the width of at least one of the first end and the second end; a second portion that is a different material than the first semiconductor portion, a third portion that is a different material than the first semiconductor portion, wherein the second and third portions are on opposite sides of the slit portion, and at least three terminals selected from a group consisting of a first terminal connected to the first end, a second terminal connected to the second end, a third terminal connected to the second portion, and a fourth terminal connected to the third portion.

Methods of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes forming first auxiliary patterns, alternately forming first material layers and second material layers on the sidewalls of the first auxiliary patterns so that a gap region between the first auxiliary patterns adjacent to each other is filled, removing the second material layers, and forming charge storage layers in respective regions from which the second material layers have been removed.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

The present application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device comprises an SOI substrate; a semiconductor fin formed on the SOI substrate, the semiconductor fin having a first side and a second side which are opposite to each other and stand upward on a surface of the SOI substrate, and a trench which is opened at a central portion of the second side and opposite to the first side; a channel region formed in the fin and being between the first side and the trench at the second side; source and drain regions formed in the fin and sandwiching the channel region; and a gate stack formed on the SOI substrate and being adjacent to the first side of the fin, wherein the gate stack comprises a first gate dielectric extending away from the first side and being adjacent to the channel region, a first conductor layer extending away from the first side and being adjacent to the first gate dielectric, a second gate dielectric extending away from the first side and being adjacent laterally to one side of the first conductor layer, and a second conductor layer extending away from the first side and being adjacent laterally to one side of the second gate dielectric. The embodiments of the invention can be applied in manufacturing an FinFET. 1. A semiconductor device , comprising an SOI substrate;a semiconductor fin formed on the semi-conductor-on-insulator “SOI” substrate, the semiconductor fin having a first side and a second side which are opposite to each other and stand upward on a surface of the SOI substrate, and a trench which is opened at a central portion of the second side and opposite to the first side;a channel region formed in the fin and being between the first side and the trench at the second side;source and drain regions formed in the fin and sandwiching the channel region; anda gate stack formed on the SOI substrate and being adjacent to the first side of the fin,wherein the gate stack comprises a first ...

Integrated Nanostructure-Based Non-Volatile Memory Fabrication

Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.

EEPROM CELL

A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor. 1. A device comprising: the first transistor includes a first gate with a second sub-gate surrounding a first sub-gate, the first and second sub-gates of the first gate are separated by a first intergate dielectric layer, and', 'the second transistor includes a second gate with a second sub-gate surrounding a first sub-gate, the first and second sub-gates of the second gate are separated by a second intergate dielectric layer;, 'a cell having first and second transistors coupled in series, wherein the first and second transistors are disposed between first and second cell terminals, wherein'}a first gate terminal coupled to the second sub-gate of the first gate; anda second gate terminal coupled to at least the first sub-gate of the second gate.2. The device of wherein:the first transistor serves as a control gate;the second transistor serves as a select gate;the first cell terminal is coupled to a first junction of the first transistor and serves as a bitline; andthe second gate terminal serves as a wordline.3. The device of wherein the first intergate dielectric layer comprises multiple dielectric layers.4. The device of wherein the second ...

EEPROM CELL

A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor. 1. A device comprising: the first transistor includes a first gate with first and second sub-gates separated by a first intergate dielectric layer, and', 'the second transistor includes a second gate with first and second sub-gates separated by a second intergate dielectric layer, the second sub-gate surrounds the first sub-gate of the second transistor;, 'a cell having first and second transistors coupled in series, wherein the first and second transistors are disposed between first and second cell terminals, wherein'}a first gate terminal coupled to the second sub-gate of the first gate; anda second gate terminal coupled to at least the first sub-gate of the second gate.2. The device of wherein:the first transistor serves as a control gate;the second transistor serves as a select gate;a first junction of the second transistor serves as the second cell terminal, wherein the second cell terminal is coupled to a bitline; andthe second gate terminal is coupled to a wordline.3. The device of comprising:a first gate dielectric layer below the first gate, wherein the first gate dielectric layer includes a tunneling window under the first sub-gate of the first gate; anda second gate ...

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME

A semiconductor device may include a gate structure on a substrate, the gate structure including a first metal; an insulating interlayer covering the gate structure on the substrate; a resistance pattern in the insulating interlayer, the resistance pattern having a top surface lower than a top surface of the insulating interlayer and including a second metal different from the first metal at least at an upper portion thereof; and/or a first contact plug through a first portion of the insulating interlayer, the first contact plug making direct contact with the upper portion of the resistance pattern. 1. A semiconductor device , comprising:a gate structure on a substrate, the gate structure including a first metal;an insulating interlayer covering the gate structure on the substrate;a resistance pattern in the insulating interlayer, the resistance pattern having a top surface lower than a top surface of the insulating interlayer and including a second metal different from the first metal at least at an upper portion thereof; anda first contact plug through a first portion of the insulating interlayer, the first contact plug making direct contact with the upper portion of the resistance pattern.2. The semiconductor device of claim 1 , wherein the substrate is divided into an active region and a field region claim 1 , and further comprising:at least one second contact plug through a second portion of the insulating interlayer, the at least one second contact plug being electrically connected to the active region; anda shared contact plug through the insulating interlayer, the shared contact plug making contact with a top surface of the gate structure and a top surface of the second contact plug.3. The semiconductor device of claim 2 , wherein the first contact plug and the shared contact plug have top surfaces substantially coplanar with each other.4. The semiconductor device of claim 2 , wherein the insulating interlayer includes an etch stop layer having a bottom ...

Electronic Device Including a Tunnel Structure

An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region.

NON-VOLATILE STORAGE SYSTEM WITH THREE LAYER FLOATING GATE

A non-volatile storage system includes memory cells with floating gates that comprises three layers separated by two dielectric layers (an upper dielectric layer and lower dielectric layer). The dielectric layers may be an oxide layers, nitride layers, combinations of oxide and nitride, or some other suitable dielectric material. The lower dielectric layer is close to the bottom of the floating gate (near interface between floating gate and tunnel dielectric), while the upper dielectric layer is close to top of the floating gate (near interface between floating gate and inter-gate dielectric). 1. A non-volatile storage device , comprising:a floating gate comprising three separate charge storage layers separated by floating gate dielectric layers;a tunnel dielectric layer on a surface of a substrate, between the substrate and the floating gate;a control gate; andan inter-gate dielectric between the floating gate and the control gate.2. The non-volatile storage device according to claim 1 , wherein:two or more of the three separate charge storage layers include a dosage of heavy atoms.3. The non-volatile storage device according to claim 1 , wherein:one or more of the three separate charge storage layers are doped with Carbon.4. The non-volatile storage device according to claim 1 , wherein:one or more of the three separate charge storage layers are doped with Nitrogen.5. The non-volatile storage device according to claim 1 , wherein:the floating gate dielectric layers comprise an upper dielectric layer and a lower dielectric layer;the upper dielectric layer is close to a top of the floating gate such that it is less than one third of the height of the floating gate down from the top of the floating gate; andthe lower dielectric layer is close to a bottom of the floating gate such that it is less than one third of the height of the floating gate up from the bottom of the floating gate.6. The non-volatile storage device according to claim 1 , wherein:the three separate ...

Manufacturing method of flash memory structure with stress area

In a manufacturing method of a flash memory structure with a stress area, a better stress effect can be achieved by controlling the manufacturing process of a tunneling oxide layer formed in a gate structure and contacted with a silicon substrate, so that an L-shaped spacer (or a first stress area) and a contact etch stop layer (or a second stress area) of each L-shaped spacer are formed between two gate structures and aligned towards each other to enhance the carrier mobility of the gate structure, so as to achieve the effects of improving a read current, obtaining the required read current by using a lower read voltage, reducing the possibility of having a stress-induced leakage current, and enhancing the data preservation of the flash memory.

Nonvolatile semiconductor memory device and method of manufacturing the same

According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure having memory cells, and a beam connected to an end portion of the structure. Each of the structure and the beam includes semiconductor layers stacked in a perpendicular direction. The beam includes a contact portion provided at one end of the beam, and a low resistance portion provided between the contact portion and the end portion of the structure.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes, a semiconductor substrate, a plurality of memory cells being provided on the semiconductor substrate in a memory cell region. Each of the plurality of memory cells having a first gate electrode disposed on the semiconductor substrate with a first gate insulating film, and the first gate electrode having a first charge storage layer, a first inter-electrode insulating film and a first control gate electrode film, and a cavity is interposed between an upper surface of the charge storage layer and the inter-electrode insulating film. 1. A semiconductor device comprising:a semiconductor substrate;a plurality of memory cells being provided on the semiconductor substrate in a memory cell region; andwherein each of the plurality of memory cells having a first gate electrode disposed on the semiconductor substrate with a first gate insulating film, and the first gate electrode having a first charge storage layer, a first inter-electrode insulating film and a first control gate electrode film, andwherein a cavity is interposed between an upper surface of the charge storage layer and the inter-electrode insulating film.2. The semiconductor device of claim 1 , wherein the first inter-electrode insulating film on the first charge storage layer has a pointed portion.3. The semiconductor device of claim 2 , wherein the upper surface of the first charge storage layer is flat.41. The semiconductor device of claim. claim 2 , further comprising:a peripheral transistor disposed in a peripheral circuit region differed from the memory cell regionwherein the peripheral transistor having a second gate electrode disposed on the semiconductor substrate in the peripheral circuit region with a second gate insulating film, and the second gate electrode having a second charge storage layer, a second inter-electrode insulating film and a second control gate electrode film, andwherein a second cavity interposed between an upper surface of the second charge storage ...

MANUFACTURING METHOD OF NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND A NONVOLATILE SEMICONDUCTOR STORAGE DEVICE

A nonvolatile semiconductor storage device has a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, multiple floating gate electrodes formed on the gate insulating film, an inter-electrode insulating film formed on the multiple floating gate electrodes, and word lines formed on the inter-electrode insulating film. The word lines have lower and upper layers containing polysilicon doped with an impurity and are formed with a separating layer between the lower layer and the upper layer. A portion of the separating layer is located between multiple floating gate electrodes, and the height of the lower layer is less than the height of the upper layer. 1. A method for manufacturing a nonvolatile semiconductor storage device , comprising the steps of:forming a gate insulating film on a semiconductor substrate;forming multiple floating gate electrodes on the gate insulating film;forming an inter-electrode insulating film on the multiple floating gate electrodes; andforming word lines containing polysilicon doped with an impurity on the inter-electrode insulating film, the word lines including a lower layer, an upper layer, and a separating layer between the lower layer and the upper layer.2. The method of claim 1 , wherein the separating layer is formed between the multiple floating gate electrodes.3. The method of claim 1 , wherein the upper layer of the word line is formed to be higher than the lower layer of the word line.4. The method according to claim 1 , wherein the separating layer is an oxygen containing layer.5. The method according to claim 4 , wherein the separating layer is formed by substituting the atmosphere during the step of forming word lines with an oxygen atmosphere.6. The method according to claim 5 , wherein the atmosphere is substituted with the oxygen atmosphere halfway through the step of forming word lines.7. The method according to claim 1 , wherein the separating layer is a nitrogen containing layer.8. The ...

Methods of forming nanoscale floating gate

A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer.

NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

Provided is a P-channel non-volatile semiconductor memory device with improved write characteristics. In the P-channel non-volatile semiconductor memory device, a resistive element is formed and connected to a control gate. A delay effect of the resistive element connected to the control gate is utilized to increase a potential of the control gate so as to cancel out a decrease in floating gate potential caused by hot electrons injected by writing. This can prevent the weakening of an electric field between a pinch-off point and a drain, which leads to a decrease in amount of generated DAHEs in writing. Thus, write characteristics can be improved. 1. A non-volatile semiconductor memory device , comprising:a semiconductor substrate;an element isolation region disposed in a surface of the semiconductor substrate;an N-type well region disposed along one principal surface of the semiconductor substrate;a P-type source region and a P-type drain region both arranged in the N-type well region;a gate oxide film arranged on the surface of the semiconductor substrate between the P-type source region and the P-type drain region;a floating gate disposed on the gate oxide film;a second insulating film disposed on a surface of the floating gate;a control gate capacitively coupled to the floating gate disposed through intermediation of the second insulating film; anda resistive element serially connected to the control gate.2. A non-volatile semiconductor memory device according to claim 1 , wherein the resistive element connected to the control gate is used to generate a constant potential difference between a potential of the floating gate and a threshold potential of the non-volatile semiconductor memory device in writing. 1. Field of the InventionThe present invention relates to a P-channel non-volatile semiconductor memory device capable of electrical writing and reading.2. Description of the Related ArtIn recent years, there is known a semiconductor integrated circuit ...

Thin films organized in nanodomains on the basis of copolymers having polysaccharide blocks for applications in nanotechnology

A material (M) includes a substrate one of the surfaces of which is covered with a layer based on a block copolymer having a block (B) consisting of a polysaccharide and to its uses for electronics, in order to prepare organic electroluminescent diodes (OLEDs) or organic photovoltaic cells (OPV) or for designing detection devices (nanobiosensors, biochips).

Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor

A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

According to one embodiment, a semiconductor device includes a substrate, a plurality of interconnects, and a plurality of gap control units. The substrate includes silicon. The plurality of interconnects is provided above the substrate. The plurality of gap control units is provided respectively on the plurality of interconnects to have width dimensions greater than width dimension of the plurality of interconnects. A gap is provided between adjacent interconnects of the plurality of interconnects. An apical portion of the gap is provided between adjacent gap control units of the plurality of gap control units and between a lower surface position and an upper surface position of each of the adjacent gap control units. 1. A semiconductor device , comprising:a substrate including silicon;a plurality of interconnects provided above the substrate; anda plurality of gap control units provided respectively on the plurality of interconnects to have width dimensions greater than width dimensions of the plurality of interconnects,a gap being provided between adjacent interconnects of the plurality of interconnects,an apical portion of the gap being provided between adjacent gap control units of the plurality of gap control units and between a lower surface position and an upper surface position of each of the adjacent gap control units.2. The device according to claim 1 , wherein angles of side surfaces of the plurality of gap control units with respect to lower surfaces of the plurality of gap control units are not more than 86°.3. The device according to claim 1 , wherein thickness dimensions of the plurality of gap control units are not less than 5 nm and not more than 50 nm.4. The device according to claim 1 , wherein the width dimensions of the plurality of gap control units are not less than 1.05 times the width dimensions of the plurality of interconnects.5. The device according to claim 1 , wherein each of the plurality of gap control units includes a plurality of ...

Semiconductor structure and manufacturing method of the same

A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first stacked structure, and a first conductive layer. The first stacked structure is formed on the substrate and includes a conductive structure and an insulating structure, and the conductive structure is disposed adjacent to the insulating structure. The first conductive layer is formed on the substrate and surrounds two side walls and a part of the top portion of the first stacked structure for exposing a portion of the first stacked structure.

NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURE THEREOF

A nonvolatile semiconductor storage device includes a semiconductor substrate including a protruding active area, a gate insulating layer on the active area, floating gate electrodes on the gate insulating layer, an insulating layer on the floating gate electrodes extending in a row direction, and a control gate electrode on the insulating layer extending in the row direction. The floating gate electrodes include a semiconductor layer on the gate insulating layer and a metal layer on the semiconductor layer. The width of the semiconductor layer of the floating gate electrodes in the row direction is narrower than the width of the metal layer in the row direction.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a gate insulating film formed on the semiconductor substrate; a floating gate formed on the gate insulating film; a control gate formed on the floating gate and has a side coplanar with a side of the floating gate; a tunnel diffusion layer facing a portion of the floating gate; and a tunnel window formed in a portion of the gate insulating film between the floating gate and the tunnel diffusion layer, the tunnel window being formed to be thinner than a remaining peripheral portion of the gate insulating film. 1. A semiconductor device having a nonvolatile memory cell selectively formed on a semiconductor substrate , comprising:a gate insulating film formed on the semiconductor substrate;a floating gate selectively formed on the gate insulating film in a region for the nonvolatile memory cell;a control gate formed on the floating gate and having a side coplanar with a side of the floating gate;a select gate selectively formed on the gate insulating film in the region for the nonvolatile memory cell and having a mono-layered structure of a conductive film flush with the floating gate;a tunnel diffusion layer facing a portion of the floating gate in the semiconductor substrate; anda tunnel window formed in a portion of the gate insulating film between the floating gate and the tunnel diffusion layer, the tunnel window configured to be thinner than a remaining peripheral portion of the gate insulating film.2. The semiconductor device of claim 1 , further comprising:a drain region formed in the opposite side of the tunnel diffusion layer to the select gate in the semiconductor substrate; anda drain low concentration layer formed to be self-aligned with the select gate to correspond to the drain region in the semiconductor substrate and widened to a region deeper than the drain region, and having an impurity concentration lower than that of the drain region.3. The semiconductor device of claim 1 , wherein the depth of the drain low ...

Fabricating method of non-volatile memory

A fabricating method of a non-volatile memory is provided. A tunneling dielectric layer and a first conductive layer are sequentially formed on a substrate. Isolation structures are formed in the first conductive layer, the tunneling dielectric layer and the substrate. The first conductive layer is patterned to form protruding portions. A portion of the isolation structures is removed, so that a top surface of each isolation structure is disposed between a top surface of the first conductive layer and a surface of the substrate. An inter-gate dielectric layer is formed on the substrate. A second conductive layer is formed on the inter-gate dielectric layer. The second conductive layer is patterned to form control gates, and the first conductive layer is patterned to form floating gates. The protruding portion of each floating gate is fully covered and surrounded by the control gate in any direction.

STACKED-GATE NON-VOLATILE FLASH MEMORY CELL, MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

A stacked-gate non-volatile flash memory cell, a memory device including the memory cell, and a manufacturing method thereof are provided. The memory cell includes a semiconductor structure and a movable switch (), wherein the semiconductor structure includes an extended floating gate structure, and an interlayer dielectric layer () with an opening () through which the extended floating gate structure is exposed; meanwhile, the movable switch () includes a support component () and a conductive interconnection component (), the support component () is located on the periphery of the conductive interconnection component and connected with the interlayer dielectric layer, and the conductive interconnection component is floating over the opening. When a voltage is applied to the conductive interconnection component, the conductive interconnection component is electrically connected with the extended floating gate structure, so that the advantages of simple control circuit, low manufacturing cost, high reliability, low power consumption and high efficiency are obtained. 1. A stacked-gate non-volatile flash memory cell , comprising:a semiconductor structure, comprising a substrate, a doped well in the substrate, a stacked-gate transistor in and on the doped well, wherein the stacked-gate transistor comprises a source region, a drain region, a floating gate structure disposed between the source and the drain, an isolating layer which covers the floating gate structure and a controlling gate structure disposed on the isolating layer, the semiconductor structure further comprises an extended floating gate structure which is an extended structure of the floating gate structure on the substrate, and an interlayer dielectric layer is disposed on the semiconductor structure; anda movable switch disposed above the extended floating gate structure, wherein there is an opening corresponding to the movable switch in the ILD layer, and the opening exposes the extended floating gate ...

MEMORY DEVICE AND METHOD OF MANUFACTURE THEREOF

A memory device is provided with a floating gate electrode film formed in a memory cell region, a first inter-electrode insulating film formed on the floating gate electrode film, a control gate electrode film formed on the first inter-electrode insulating film, a lower conductive film formed in a peripheral circuit region, a second inter-electrode insulating film formed on the lower conductive film, an upper conductive film formed on the second inter-electrode insulating film, and a pair of contacts that is separated from each other, is connected to the lower conductive film from the upper side, and is not connected to the upper conductive film. Materials of the lower conductive film and the floating gate electrode film are the same. Materials of the second inter-electrode insulating film and the first inter-electrode insulating film are the same. Materials of the upper conductive film and the control gate electrode film are the same. 1. A memory device , comprising:a semiconductor substrate with a memory cell region and a peripheral circuit region thereon;a lower layer insulating film formed on the semiconductor substrate;a floating gate electrode film formed on the lower layer insulating film in the memory cell region;a first inter-electrode insulating film formed on the floating gate electrode film;a control gate electrode film formed on the first inter-electrode insulating film;a lower conductive film formed on the lower layer insulating film in the peripheral circuit region;a second inter-electrode insulating film formed on the lower conductive film;an upper conductive film formed on the second inter-electrode insulating film; anda pair of contacts separated from each other, connected to the lower conductive film from above, and not connected to the upper conductive film, whereinthe lower conductive film comprises the same material as the floating gate electrode film;the second inter-electrode insulating film comprises the same as material as the first inter- ...

NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

A nonvolatile memory device includes a plurality of interlayer dielectric layers and conductive layers for gate electrodes alternately stacked over a substrate, a channel trench passing through the interlayer dielectric layers and the conductive layers and exposing the substrate, a charge blocking layer and a charge trap or charge storage layer formed on sidewalls of the trench, a coupling prevention layer formed at the surface of the charge trap or charge storage layer, and a tunnel insulation layer formed over the coupling prevention layer. 1. A nonvolatile memory device comprising:a plurality of interlayer dielectric layers and conductive layers for gate electrodes alternately stacked over a substrate;a channel trench formed through the interlayer dielectric layers and the conductive layers to expose the substrate;a charge blocking layer and a charge trap or charge storage layer formed on sidewalls of the trench;a coupling prevention layer formed at the surface of the charge trap or charge storage layer; anda tunnel insulation layer formed over the coupling prevention layer.2. The nonvolatile memory device of claim 1 , wherein the charge trap or charge storage layer comprises a Si-rich nitride layer in which the composition ratio of silicon is higher than that of nitrogen.3. The nonvolatile memory device of claim 2 , wherein the composition ratio of silicon to nitrogen is 1.33 or less.4. The nonvolatile memory device of claim 1 , wherein the coupling prevention layer is formed by performing any one treatment selected from nitration claim 1 , oxidation claim 1 , and nitrification on the surface of the charge trap or charge storage layer.511-. (canceled)12. A nonvolatile memory device comprising:a plurality of interlayer dielectric layers and gate electrode layers alternately stacked over a substrate;a channel conductive layer formed vertically protruded from the substrate; anda charge blocking layer, a charge trap or charge storage layer, a coupling prevention ...

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

A nonvolatile semiconductor memory device includes: forming a stacked body by alternately stacking a plurality of interlayer insulating films and a plurality of control gate electrodes; forming a through-hole extending in a stacking direction in the stacked body; etching a portion of the interlayer insulating film facing the through-hole via the through-hole to remove the portion; forming a removed portion; forming a first insulating film on inner faces of the through-hole and the portion in which the interlayer insulating films are removed; forming a floating gate electrode in the portion in which the interlayer insulating films are removed; forming a second insulating film so as to cover a portion of the floating gate electrode facing the through-hole; and burying a semiconductor pillar in the through-hole. 1. A nonvolatile semiconductor memory device comprising:a stacked body in which a plurality of interlayer insulating films and a plurality of control gate electrodes are alternately stacked and a through-hole extending in a stacking direction is formed;a semiconductor pillar buried in the through-hole;a floating gate electrode provided between the control gate electrodes;a first insulating film provided between the semiconductor pillar and the floating gate electrode, and the control gate electrodes; anda second insulating film provided between the semiconductor pillar and the floating gate electrode.2. The device according to claim 1 , wherein a diameter of the through-hole is larger than a thickness of each of the interlayer insulating films.3. The device according to claim 1 , wherein the floating gate electrode has a circular shape surrounding the semiconductor pillar.4. The device according to claim 1 , wherein the floating gate electrode is formed of silicon.5. The device according to claim 1 , wherein the control gate electrodes are formed of a metal or silicon doped with an impurity.6. The device according to claim 1 , wherein the semiconductor pillar ...

SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor storage device includes a semiconductor substrate. A first insulating film is provided on the semiconductor substrate. A charge storage layer includes a first part provided on the first insulating film, an intermediate insulating film provided on the first part, and a second part provided on the intermediate insulating film, and is capable of storing electric charges. A second insulating film is provided on an upper surface and a side surface of the charge storage layer. A control gate is opposed to the upper surface and the side surface of the charge storage layer via the second insulating film, and is configured to control a voltage of the charge storage layer. The intermediate insulating film is recessed in comparison with side surfaces of the first and second parts on the side surface of the charge storage layer. 1. A semiconductor storage device comprising:a semiconductor substrate;a first insulating film on the semiconductor substrate;a charge storage layer including a first part on the first insulating film, an intermediate insulating film on the first part, and a second part on the intermediate insulating film, the charge storage layer being capable of storing electric charges;a second insulating film on an upper surface and a side surface of the charge storage layer; anda control gate opposed to the upper surface and the side surface of the charge storage layer via the second insulating film, the control gate controlling a voltage of the charge storage layer, whereinthe intermediate insulating film is recessed in comparison with side surfaces of the first and the second parts on the side surface of the charge storage layer.2. The device of claim 1 , wherein the control gate is provided at a position lower than a position of the intermediate insulating film and higher than a position of the first insulating film on the side surface of the charge storage layer.3. The device of claim 1 , whereinthe second insulating film is recessed together ...

Nonvolatile memory device and method of fabricating the same

A nonvolatile memory device includes a memory gate pattern on a substrate, and a non-memory gate pattern on the substrate, the non-memory gate pattern being spaced apart from the memory gate pattern, wherein the non-memory gate pattern includes an ohmic layer, and the memory gate pattern is provided without an ohmic layer.

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

A nonvolatile semiconductor memory device according to an embodiment includes a plurality of cell array layers, each cell array layer including: a plurality of semiconductor layers that extends in a first direction; gate insulating layers; a plurality of floating gates arranged in the first direction; inter-gate insulating layers; and a plurality of control gates that extends in a second direction intersecting semiconductor layers, and faces the floating gates via the inter-gate insulating layers, in which, in the cell array layers adjacent each other in a stacking direction, the control gates of a lower cell array layer and the control gates of the an upper cell array layer are intersecting each other, and the floating gates within the lower cell array layer and the semiconductor layers within the upper cell array layer are aligned in position with each other. 1. A nonvolatile semiconductor memory device comprising a plurality of memory cell array layers being stacked , each memory cell array layer including:a plurality of semiconductor layers, each extending in a first direction and being in parallel to each other;gate insulating layers formed on the semiconductor layers;a plurality of floating gates formed on the gate insulating layers and arranged in the first direction;inter-gate insulating layers adjacent to the floating gates; anda plurality of control gates that face the floating gates via the inter-gate insulating layers at both sides of the floating gates in the first direction and that extend in a second direction intersecting the first direction,in the cell array layers adjacent to each other in a stacking direction, the control gates of the cell array layer in a lower cell array layer and the control gates of the cell array layer in an upper cell array layer intersecting each other, the floating gates in the lower cell array layer and the semiconductor layers on the floating gates being aligned in position with each other.2. The nonvolatile ...

NONVOLATILE MEMORY CELLS WITH A VERTICAL SELECTION GATE OF VARIABLE DEPTH

The disclosure relates to an integrated circuit comprising at least two memory cells formed in a semiconductor substrate, and a buried gate common to the selection transistors of the memory cells. The buried gate has a first section of a first depth extending in front of vertical channel regions of the selection transistors, and at least a second section of a second depth greater than the first depth penetrating into a buried source line. The lower side of the buried gate is bordered by a doped region forming a source region of the selection transistors and reaching the buried source line at the level where the second section of the buried gate penetrates into the buried source line, whereby the source region is coupled to the buried source line. 1. An integrated circuit comprising:a buried source line buried in a semiconductor substrate; andfirst and second memory cells formed in the semiconductor substrate, each including a selection transistor, the first and second memory cells including a buried gate common to the selection transistors of the memory cells, wherein:the buried gate has a first section of a first depth extending in front of vertical channel regions of the selection transistors, and a second section of a second depth greater than the first depth and penetrating into the buried source line, andthe selection transistors having a doped source region bordering a lower side of the buried gate and reaching the buried source line at a level at which the second section of the buried gate penetrates into the buried source line, whereby the source region is coupled to the buried source line.2. An integrated circuit according to claim 1 , wherein the memory cells are formed in a well of the semiconductor substrate claim 1 , said buried source line being an isolation layer that delimits the well.3. An integrated circuit according to claim 1 , comprising:a memory that includes the first and second memory cells, a first row of memory cells, and a second row of ...

TFT Floating Gate Memory Cell Structures

A device having thin-film transistor (TFT) floating gate memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N polysilicon layer on a diffusion barrier layer which is on a first conductive layer. The N polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P polysilicon layer overlying the co-planar surface and a floating gate on the P polysilicon layer. The floating gate is a low-pressure CVD-deposited silicon layer sandwiched by a bottom oxide tunnel layer and an upper oxide block layer. Moreover, the device includes at least one control gate made of a P polysilicon layer overlying the upper oxide block layer. A method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally. 1. A device with thin-film transistor (TFT) floating gate memory cell structure , the device comprising:a substrate;a dielectric layer on the substrate, the dielectric layer being associated with a first surface;{'sup': +', '+', '+, 'one or more source or drain regions being embedded in the dielectric layer, each of the one or more source or drain regions including an N polysilicon layer, a diffusion barrier layer, and a first conductive layer, the N polysilicon layer being located on the diffusion barrier layer, the diffusion barrier layer overlying the first conductive layer, the N polysilicon layer having a second surface substantially co-planar with the first surface;'}{'sup': '−', 'a P polysilicon layer overlying the first surface and the second surface;'}{'sup': '−', 'a silicon layer on the P polysilicon layer, the silicon layer being sandwiched by an upper oxide block layer and a bottom oxide tunnel layer;'} ...

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

According to one embodiment, a nonvolatile semiconductor memory includes a gate insulating film, a floating gate, first and second silicon oxide films, an insulating film and a control gate. The floating gate is formed on the gate insulating film. The first silicon oxide film is formed on an upper surface of the floating gate. The insulating film is formed on the first silicon oxide film on the upper surface of the floating gate and has a dielectric constant higher than that of the silicon oxide film. The second silicon oxide film is formed on the insulating film on the upper surface of the floating gate and on a side surface of the floating gate. The control gate is formed on the second silicon oxide film formed on the upper and side surfaces of the floating gate. 1. A nonvolatile semiconductor memory device comprising:a gate insulating film formed on a semiconductor substrate;a floating gate electrode formed on the gate insulating film;a first silicon oxide film formed on an upper surface of the floating gate electrode;an insulating film which is formed on the first silicon oxide film on the upper surface of the floating gate electrode and which has a dielectric constant higher than that of the silicon oxide film;a second silicon oxide film formed on the insulating film on the upper surface of the floating gate electrode and on a side surface of the floating gate electrode; anda control gate electrode formed on the second silicon oxide film formed on the upper surface and side surface of the floating gate electrode.2. The nonvolatile semiconductor memory device according to claim 1 , further comprising a first silicon nitride film formed on the second silicon oxide film on the upper surface and side surface of the floating gate electrode.3. The nonvolatile semiconductor memory device according to claim 1 , further comprising a second silicon nitride film disposed between the upper surface of the floating gate electrode and the first silicon oxide film and between ...

Novel Structure for Flash Memory Cells

A flash memory cell structure is provided. A semiconductor structure includes a semiconductor substrate, a floating gate overlying the semiconductor substrate, a word-line adjacent to the floating gate, an erase gate adjacent to a side of the floating gate opposite the word-line, a first sidewall disposed between the floating gate and the word-line, and a second sidewall disposed between the floating gate and the erase gate. The first sidewall has a first characteristic and the second sidewall has a second characteristic. The first characteristic is different from the second characteristic. 1. A semiconductor structure comprising:a semiconductor substrate;a first floating gate disposed on the semiconductor substrate;a first conductive line adjacent to the first floating gate;a second conductive line adjacent to a side of the first floating gate opposite the first conductive line;a first control gate disposed on the first floating gate;a first separation layer disposed between the first control gate and the first floating gate; anda first spacer extending up a side of the first floating gate and the first control gate, the first spacer comprising a first plurality of first spacer layers disposed between the first floating gate and the first conductive line and a second plurality of first spacer layers disposed between the first control gate and the first conductive line, wherein the first plurality of first spacer layers has fewer layers than the second plurality of first spacer layers.2. The semiconductor structure of claim 1 , wherein the first plurality of first spacer layers comprises:a first oxide layer disposed between the first floating gate and the first conductive line; anda first isolation layer disposed between the first conductive line and the first oxide layer.3. The semiconductor structure of claim 2 , wherein the second plurality of first spacer layers comprises:the first oxide layer and the first isolation layer disposed between the first control gate ...

SINGLE POLY ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY (SINGLE POLY EEPROM) DEVICE

A single poly electrically erasable programmable read only memory (single poly EEPROM) device is provided, including: a semiconductor on insulator (SOI) substrate having a P-type semiconductor layer over an insulator layer; a P-well region formed in a portion of the P-type semiconductor layer; a trench isolation formed in the P-type semiconductor layer, surrounding the P-well region; an NMOS transistor formed over a portion of the P-type semiconductor layer of the P-well region; a P+ doping region formed over another portion of the P-type semiconductor layer of the P-well region; and a control gate formed in another portion of the P-type semiconductor layer, adjacent to the trench isolation. 1. A single poly electrically erasable programmable read only memory (single poly EEPROM) device , comprising:a semiconductor on insulator (SOI) substrate having a P-type semiconductor layer over an insulator layer;a P-well region formed in a portion of the P-type semiconductor layer;a trench isolation formed in the P-type semiconductor layer, surrounding the P-well region;an NMOS transistor formed over a portion of the P-type semiconductor layer of the P-well region;a P+ doping region formed over another portion of the P-type semiconductor layer of the P-well region; anda control gate formed in another portion of the P-type semiconductor layer, adjacent to the trench isolation.2. The single poly EEPROM device as claimed in claim 1 , wherein the SOI substrate further comprises a semiconductor layer claim 1 , and the insulating layer and the P-type semiconductor are sequentially formed over the semiconductor layer.3. The single poly EEPROM device as claimed in claim 1 , wherein the trench isolation encircles the P-type well region claim 1 , and a bottom surface of the trench isolation physically contacts the insulating layer.4. The single poly EEPROM device as claimed in claim 1 , further comprising a field oxide disposed over a portion of the P-type semiconductor layer in the P- ...

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACURING THE SAME

A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array in which a plurality of NAND cell units are arranged, the NAND cell units including a plurality of memory cells, and select gate transistors, the memory cell including a semiconductor layer, a gate insulating film, a charge accumulation layer, and a control gate; and a control circuit. The control circuit adjusts a write condition of each of the memory cells in accordance with write data to each of the memory cells and memory cells adjacent to the memory cells within the data to be written. 1. A nonvolatile semiconductor memory device comprising:a memory cell array in which a plurality of NAND cell units are arranged in a second direction intersecting a first direction, the NAND cell units including a plurality of memory cells connected in series in the first direction, source line side select gate transistors which are connected between the plurality of memory cells and the source line, and bit line side select gate transistors which are connected between the plurality of memory cells and the bit line, the memory cell including a semiconductor layer, a gate insulating film formed on the semiconductor layer, a charge accumulation layer formed on the gate insulating film, and a control gate which extends in the second direction and which faces the charge accumulation layer via an inter-gate insulating film; anda control circuit for writing data to the memory cell in units of pages, the plurality of memory cells being arranged in the second direction as a page,during write operation to the plurality of memory cells in units of pages, the control circuit adjusts a write condition of each of the memory cells in accordance with write data to each of the memory cells and write data to a memory cell adjacent to each of the memory cells in a page to be written.2. The nonvolatile semiconductor memory device according to claim 1 , whereinthe control circuit further includes a ...

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a floating gate electrode formed on the gate insulating film, made of polysilicon containing a p-type impurity as a group XIII element, and having a lower film and an upper film stacked on the lower film, an inter-electrode insulating film formed on the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film. One of a concentration and an activation concentration of the p-type impurity in the upper film is higher than one of a concentration and an activation concentration of the p-type impurity in the lower film. 1. A nonvolatile semiconductor memory device comprising:a semiconductor substrate;a gate insulating film formed on the semiconductor substrate;a floating gate electrode formed on the gate insulating film, made of polysilicon containing a p-type impurity as a group XIII element, and having a lower film and an upper film stacked on the lower film;an inter-electrode insulating film formed on the floating gate electrode; anda control gate electrode formed on the inter-electrode insulating film,wherein one of a concentration and an activation concentration of the p-type impurity in the upper film is higher than one of a concentration and an activation concentration of the p-type impurity in the lower film.2. The device according to claim 1 , whereinthe floating gate electrode contains at least one of a diffusion inhibitor and an activation promoter for the p-type impurity,the diffusion inhibitor contains at least one element selected from the group consisting of carbon, nitrogen, and fluorine, andthe activation promoter contains germanium.3. The device according to claim 2 , wherein the diffusion inhibitor is distributed in at least one of the upper film and the lower film.4. The device according to claim 3 , wherein the activation promoter is ...

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

An aspect of the present embodiment, there is provided a semiconductor device, including a semiconductor substrate, a first insulator above the semiconductor substrate, the first insulator containing tungsten, germanium and silicon, a charge storage film on the first insulator, a second insulator on the charge storage film and, a control gate electrode on the second insulator. 1. A semiconductor device , comprising:a semiconductor substrate;a first insulator above the semiconductor substrate, the first insulator containing tungsten, germanium and silicon;a charge storage film on the first insulator;a second insulator on the charge storage film anda control gate electrode on the second insulator.2. The semiconductor device of claim 1 , whereinthe first insulator has a stacked structure in which a tungsten-contained insulator, a germanium-contained insulator and a silicon-contained insulator are laminated.3. The semiconductor device of claim 2 , whereinthe tungsten-contained insulator, the germanium-contained insulator and the silicon-contained insulator are laminated in an order in the first insulator.4. The semiconductor device of claim 2 , whereinthe silicon-contained insulator includes tungsten and germanium.5. The semiconductor device of claim 4 , whereinthe silicon-contained insulator includes tungsten and germanium diffused from the tungsten-contained insulator and the germanium-contained insulator, respectively.6. The semiconductor device of claim 1 , wherein{'sup': 13', '2', '16', '2, 'area densities of both tungsten and germanium in the first insulator are not less than 1.0×10atoms/cmand not more than 1.0×10atoms/cm.'}7. The semiconductor device of claim 6 , wherein{'sup': 14', '2', '16', '2, 'area densities of both tungsten and germanium in the first insulator are not less than 1.0×10atoms/cmand not more than 1.0×10atoms/cm.'}8. The semiconductor device of claim 2 , whereinthe silicon-contained insulator is composed of a silicon oxide film including ...

Non-volatile semiconductor memory device and method of manufacturing the same

A method of manufacturing a non-volatile semiconductor memory device, comprising the steps of, forming a plurality of element regions and an element isolation region, forming a plurality of memory cell gate electrodes and two selection gate electrodes, etching the first insulating film in such a manner that the first insulating film remains at least under the selection gate electrodes, forming a second insulating film on the selection gate electrodes and under the selection gate electrodes in the element isolation region, the second insulating film having an etching rate in a first etching solution lower than that of the first insulating film, forming a third insulating film on the memory cell gate electrodes in such a manner that air gaps are formed between the memory cell gate electrodes, and forming a contact electrode.

SPLIT-GATE TYPE NONVOLATILE MEMORY DEVICE, SEMICONDUCTOR DEVICE HAVING SPLIT-TYPE NONVOLATILE MEMORY DEVICE EMBEDDED THEREIN, AND METHODS OF FORMING THE SAME

A split-gate type nonvolatile memory device includes a semiconductor substrate having a first conductivity type, a deep well having a second conductivity type in the semiconductor substrate, a pocket well having the first conductivity type in the deep well, a source line region having the second conductivity type in the pocket well, an erase gate on the source line region, and a first floating gate and a first control gate stacked sequentially on the pocket well on a side of the erase gate. The pocket well is electrically isolated from the substrate by the deep well, so that a negative voltage applied to the pocket well may not adversely affect operation of other devices formed on the substrate. 1. A split-gate type nonvolatile memory device comprising:a semiconductor substrate having a first conductivity type;a deep well having a second conductivity type in the semiconductor substrate;a pocket well having the first conductivity type in the deep well, wherein the pocket well is isolated from the substrate by the deep well;a source line region having the second conductivity type in the pocket well;an erase gate on the source line region; anda first floating gate and a first control gate stacked sequentially on the pocket well on a first side of the erase gate.2. The nonvolatile memory device of claim 1 , wherein the erase gate claim 1 , the first floating gate and the first control gate are on a top surface of the pocket well claim 1 , and opposing side surfaces and a bottom surface of the pocket well are surrounded by the deep well.3. The nonvolatile memory device of claim 1 , wherein the pocket well is configured to receive a negative voltage during a program operation of the nonvolatile memory device.4. The nonvolatile memory device of claim 3 , wherein the pocket well is configured to receive a negative voltage in a range of 0.1 to 2 V.5. The nonvolatile memory device of claim 3 , wherein the pocket well is configured to receive a ground voltage during an erase ...

Floating gate flash cell device and method for partially etching silicon gate to form the same

A method for forming a split gate flash cell memory device provides for establishing a floating gate region then using spacers or other hard mask materials that cover opposed edges of a gate electrode material in the gate region, to serve as hard masks during an etching operation that partially etches the gate electrode material which may be polysilicon. The gate electrode so produced serves as a floating gate electrode and includes a recessed central portion flanked by a pair of opposed upwardly extending fins which may terminate upwardly at an apex. A floating gate oxide is then formed by thermal oxidation and/or oxide deposition techniques.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

According to one embodiment, a semiconductor device includes a first, a second, a third, and a fourth semiconductor region, a control electrode, a floating electrode, and an insulating film. The first region contains silicon carbide. The second region is provided on the first region and contains silicon carbide. The third region is provided on the second region and contains silicon carbide. The fourth region is provided on the third region and contains silicon carbide. The control electrode is provided in a trench formed in the fourth, the third, and the second region. The floating electrode is provided between the control electrode and a bottom surface of the trench. The insulating film is provided between the trench and the control electrode, between the trench and the floating electrode, and between the control electrode and the floating electrode. 1. A semiconductor device comprising:a first semiconductor region containing silicon carbide;a second semiconductor region provided on the first semiconductor region, the second semiconductor region containing silicon carbide of a first conductivity type;a third semiconductor region provided on the second semiconductor region, the third semiconductor region containing silicon carbide of a second conductivity type;a fourth semiconductor region provided on the third semiconductor region, the fourth semiconductor region containing silicon carbide of the first conductivity type;a control electrode provided in a trench, the trench formed in the fourth semiconductor region, the third semiconductor region, and the second semiconductor region;a floating electrode provided between the control electrode and a bottom surface of the trench; andan insulating film provided between the trench and the control electrode, between the trench and the floating electrode, and between the control electrode and the floating electrode.2. The semiconductor device according to claim 1 , wherein the insulating film includes:a gate insulating film ...

EPITAXIAL SILICON GROWTH

Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon growth. The method includes providing a silicon layer on a substrate. A dielectric layer is provided on the silicon layer. A trench is formed in the dielectric layer to expose the silicon layer, the trench having trench walls in the <100> direction. The method includes epitaxially growing silicon between trench walls formed in the dielectric layer. 1. An array of memory cells , comprising:a number of memory cells having floating gates formed over epitaxially (epi) grown single crystalline semiconductor material, wherein the epi grown single crystalline semiconductor material is formed between dielectric walls oriented in a <100> direction relative to the epi grown single crystalline semiconductor material; andwherein the array has a feature size of not more than approximately 20 nanometers (nm).2. The array of claim 1 , wherein the epi grown single crystalline semiconductor material is epi grown single crystalline silicon and is substantially defect free having dislocations pinned between the epi grown single crystalline silicon and the dielectric walls.3. The array of claim 1 , wherein the array is a NAND array of memory cells.4. The array of claim 1 , wherein the number of memory cells are non-volatile memory cells.5. The array of claim 1 , wherein a high vacuum oxide is formed over the floating gates of the number of memory cells.6. A memory cell array claim 1 , comprising:a number of devices located above a dielectric isolation material, wherein the devices are formed from epitaxially (epi) grown single crystalline semiconductor material, the epi grown single crystalline semiconductor material having a number of fins of silicon connecting the epi grown single crystalline semiconductor material through the dielectric isolation material to a substrate;a wall surface of the number of fins oriented in a <100> ...

Nonvolatile semiconductor memory device and method of manufacturing the same

A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; an organic molecular layer formed on the semiconductor layer, the organic molecular layer including a plurality of organic molecules, each of the organic molecules includes a tunnel insulating unit of alkyl chain having one end bonded to the semiconductor layer, a charge storing unit, and a bonding unit configured to bond the other end of the alkyl chain to the charge storing unit; a block insulating film formed on the organic molecular layer; and a gate electrode formed on the block insulating film.

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation film formed on a semiconductor substrate, a charge storage film formed on the first insulation film, a second insulation film formed on the charge storage film, and a control electrode formed on the second insulation film. The first insulation film is formed on the semiconductor substrate, and has a lower layer film containing silicon, and an upper layer film formed on the lower layer film, the upper layer film having a concentration of transition metal atoms containing at least one of hafnium, titanium, zirconium, tantalum or lanthanum from 1e13 atoms/cmto 1e16 atoms/cmand is formed by either an oxide film, a nitride film, or an oxynitride film. 1. A nonvolatile semiconductor memory device , comprising:a semiconductor substrate;a first insulation film formed on the semiconductor substrate;a charge storage film formed on the first insulation film;a second insulation film formed on the charge storage film; anda control electrode formed on the second insulation film,wherein the first insulating film includes a lower layer film containing silicon that is formed on the semiconductor substrate, and a layer of transition metal atoms are disposed between the lower layer film and the charge storage film.2. The nonvolatile semiconductor memory device of claim 1 , wherein the transition metal atoms contain at least one of hafnium claim 1 , titanium claim 1 , zirconium claim 1 , tantalum or lanthanum.3. The nonvolatile semiconductor memory device of claim 2 , wherein a concentration of the transition metal atoms between the lower film and the charge storage film is from 1e13 atoms/cmto 1e16 atoms/cm.4. The nonvolatile semiconductor memory device of claim 2 , wherein the transition metal atoms between the lower film and the charge storage film form a layer of either an oxide film claim 2 , a nitride film claim 2 , a boride film or a sulfide film.5. The ...

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

According to one embodiment, there is provided a nonvolatile semiconductor memory device including a substrate, a laminated film which has a configuration where first insulating layers and first electrode layers are alternately laminated in a first direction vertical to the substrate, a second insulating layer formed on an inner wall of a first through hole pierced in the first insulating layers and the first electrode layers along the first direction, an intermediate layer formed on a surface of the second insulating layer, a third insulating layer formed on a surface of the intermediate layer, and a pillar-like first semiconductor region which is formed on a surface of the third insulating layer and extends along the first direction. 1. A nonvolatile semiconductor memory device comprising:a substrate;a laminated film which has a configuration where first insulating layers and first electrode layers are alternately laminated in a first direction vertical to the substrate;a second insulating layer formed on an inner wall of a first through hole pierced in the first insulating layers and the first electrode layers along the first direction;an intermediate layer formed on a surface of the second insulating layer;a third insulating layer formed on a surface of the intermediate layer; anda pillar-like first semiconductor region which is formed on a surface of the third insulating layer and extends along the first direction,wherein the intermediate layer comprises: charge storage regions which mainly contain carbon at positions where the charge storage regions are adjacent to the first electrode layer in a second direction orthogonal to the first direction; and insulating regions which electrically separate the charge storage regions adjacent to each other along the first direction at positions where the insulating regions are adjacent to the first insulating layer in the second direction.2. The device according to claim 1 , further comprising a fourth insulating layer ...

Semiconductor device and method of manufacturing the same

According to one embodiment, a semiconductor device includes a semiconductor substrate, a tunnel insulating film on the semiconductor substrate, a first floating gate electrode on the tunnel insulating film, an inter-floating gate insulating film on the first floating gate electrode, a second floating gate electrode on the inter-floating gate insulating film, an inter-electrode insulating film on the second floating gate electrode, and a control gate electrode on the inter-electrode insulating film. The inter-floating gate insulating film includes a main insulating film, and a first fixed charge layer between the main insulating film and the second floating gate electrode and having negative fixed charges.

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

According to one embodiment, a nonvolatile semiconductor memory device includes a first memory cell on the first fin-type active area, and a second memory cell on the second fin-type active area. Each of widths of charge storage layers of the first and second memory cells becomes narrower upward from below. Each of inter-electrode insulating layers of the first and second memory cells has a contact portion through which both are in contact with each other. 1. A nonvolatile semiconductor memory device comprising:a semiconductor substrate;first and second fin-type active areas arranged on the semiconductor substrate, aligned in a first direction, and extending in a second direction perpendicular to the first direction;a first memory cell on the first fin-type active area; anda second memory cell on the second fin-type active area,wherein the first memory cell includes a first gate insulating layer on the first fin-type active area, a first charge storage layer arranged on the first gate insulating layer and in which a width thereof in the first direction becomes narrower upward from below, a first inter-electrode insulating layer covering an upper portion of the first charge storage layer, and a control gate electrode arranged on the first inter-electrode insulating layer and extending in the first direction,the second memory cell includes a second gate insulating layer on the second fin-type active area, a second charge storage layer arranged on the second gate insulating layer and in which the width thereof in the first direction becomes narrower upward from below, a second inter-electrode insulating layer covering an upper portion of the second charge storage layer, and the control gate electrode arranged on the second inter-electrode insulating layer,the first and second inter-electrode insulating layers have a contact portion through which both are in contact with each other in the first direction, andthicknesses of the first and second inter-electrode insulating ...

COMPACT THREE DIMENSIONAL VERTICAL NAND AND METHOD OF MAKING THEREOF

A NAND device has at least a 3×3 array of vertical NAND strings in which the control gate electrodes are continuous in the array and do not have an air gap or a dielectric filled trench in the array. The NAND device is formed by first forming a lower select gate level having separated lower select gates, then forming plural memory device levels containing a plurality of NAND string portions, and then forming an upper select gate level over the memory device levels having separated upper select gates. 1. A NAND device , comprising: each NAND string comprises a semiconductor channel, a tunnel dielectric located adjacent to the semiconductor channel, a charge storage region located adjacent to the tunnel dielectric, and a blocking dielectric located adjacent to the charge storage region;', 'at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate; and', 'the array comprises at least a 3×3 array of NAND strings;, 'an array of vertical NAND strings, wherein 'the first control gate electrode and the second control gate electrode are continuous in the array.', 'a plurality of control gate electrodes having a mesh shape extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level, wherein2. The device of claim 1 , wherein the first control gate electrode and the second control gate electrode do not have an air gap or a dielectric filled trench in the array.3. The device of claim 1 , wherein:each semiconductor channel has a pillar shape; andthe entire pillar-shaped semiconductor channel extends substantially perpendicularly to the major surface of the substrate.4. The device of claim 1 , wherein each NAND string in the ...

Semiconductor Memory Having Both Volatile and Non-Volatile Functionality and Method of Operating

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

NONVOLATILE MEMORY COMPRISING MINI WELLS AT A FLOATING POTENTIAL

The disclosure relates to an integrated circuit comprising a nonvolatile memory on a semiconductor substrate. The integrated circuit comprises a doped isolation layer implanted in the depth of the substrate, isolated conductive trenches reaching the isolation layer and forming gates of selection transistors of memory cells, isolation trenches perpendicular to the conductive trenches and reaching the isolation layer, and conductive lines parallel to the conductive trenches, extending on the substrate and forming control gates of charge accumulation transistors of memory cells. The isolation trenches and the isolated conductive trenches delimit a plurality of mini wells in the substrate, the mini wells electrically isolated from each other, each having a floating electrical potential and comprising two memory cells. 1. A method , comprising:manufacturing, on a semiconductor substrate, an integrated circuit that includes a nonvolatile memory comprising memory cells, each including a charge accumulation transistor and a selection transistor, the manufacturing including:implanting a doped first isolation layer in the substrate;forming, in the substrate, conductive trenches reaching the isolation layer, the conductive trenches forming gates of selection transistors of memory cells;forming, in the substrate, second isolation layers respectively isolating the conductive trenches from the substrate;forming, in the substrate, isolation trenches perpendicular to the conductive trenches, and reaching the isolation layer;forming, on the substrate, conductive lines parallel to the conductive trenches, the conductive lines forming control gates of charge accumulation transistors of the memory cells; andimplanting doped regions on opposite sides of the conductive trenches and on opposite sides of the conductive lines parallel to the conductive trenches, the doped regions forming drain and source regions of the charge accumulation transistors and of the selection transistors;the ...

DOUBLE-GATE ELECTRONIC MEMORY CELL AND METHOD OF MANUFACTURING SUCH A CELL

An electronic memory cell includes a first selection transistor gate surmounting a first part of the channel and a lateral spacer disposed against a lateral flank of the selection transistor gate, a part of the lateral spacer forming a memory transistor gate surmounting a second part of the channel. The memory transistor gate includes a stack of the ONO type and a conductive zone including a lateral face inclined at an angle α strictly between 0 and 90° with respect to the plane of the substrate. 1. An electronic memory cell comprisinga substrate on which there is formed an active channel zone produced in a semiconductor material and comprising a channel disposed between a drain extension region and a source extension region;a first gate structure surmounting a first part of said channel; a stack of layers, wherein one of said layers is arranged to store electrical charges, said stack including a first stack zone in contact with said second part of said channel and a second stack zone in contact with said lateral flank of said first gate structure;', a first lateral face in contact with said second stack zone in such a way that the latter separates said lateral flank of the first gate structure and said first lateral face;', 'a lower face essentially plane and parallel to the plane of the substrate, said lower face being in contact with said first stack zone in such a way that said first stack zone separates said second part of said channel and said lower face;', 'an upper face essentially plane and parallel to the plane of the substrate;', 'a second lateral face, said first and second lateral faces connecting said lower face to said upper face, said second lateral face being inclined at an angle α strictly between 0 and 90° with respect to the plane of the substrate, in such a way that the length of said upper face is strictly greater than the length of said lower face, said lengths being measured as the distance between said first and second lateral faces over the ...