Semiconductor device, storage device and electronic device

Brief description of the drawings

[FIG. 1]A is a block diagram showing a structural example DOSRAM of the circuit diagram, B, and FIG. C is a circuit diagram, illustrating an example of a configuration of a memory cell and a sense amplifier array.

[And 2]A to D are diagrams illustrating a structure example of a bit line. FIGS.

[. 3]A And B are circuit diagrams, illustrating a layered example of a local cell array and a sense amplifier block.

[FIG. 4] is a circuit diagram, illustrating a configuration example of a local cell array and a sense amplifier block.

[FIG. 5] is a circuit diagram, illustrating a layered example of a local cell array and a sense amplifier block.

[FIG. 6] is a circuit diagram NOSRAM illustrating a configuration example of a memory cell.

[And 7] are block diagrams (AP) showing a configuration example of an application processor. chip.

[FIG. 8] is a diagram, illustrating an electronic device.

[FIG. 9] is a sectional view showing a structural example DOSRAM of the present invention, and FIG. is a cross-sectional view showing an example of the structure.

[FIG. 10] is a sectional view showing a structural example DOSRAM of the present invention, and FIG. is a cross-sectional view showing an example of the structure.

Mode of carrying out the invention

Embodiment. to which the present invention is illustrated may be appropriately combined with Embodiment, of the present invention, and it will be readily understood by those of ordinary skill in the art to which Embodiment. of Embodiment, may be appropriately combined, and thus (the present invention should not be construed as being limited to various forms, by a person skilled in the art to which the present invention pertains without departing from the spirit and scope . of the present invention. FIGS,). may be easily understood by one of ordinary skill in the art, in which. pertains without departing from the spirit and scope of the present invention as set forth in the following embodiments . in various forms.

In the drawings, it is sometimes exaggerated for clarity of, to illustrate the thickness and area of, layers and the like . and thus, the present invention is not limited to the shapes or numerical values and the like, shown in the drawings, and for example, may include a signal, voltage or current unevenness due to noise or timing deviation and the,like.

In the present specification, for convenience, the positional relationship " of the constituent elements is sometimes used "", for convenience, and the positional relationship of the components " is appropriately changed, in accordance with the directions in which the elements are described with reference to the drawings, and therefore, is not limited to the phrase. described, in the specification, and accordingly the phrases, may be appropriately changed.

The arrangement of the circuit blocks in the block diagram shown in the drawings is not limited to, and FIG. is not limited to the case, in which different functions are implemented for the sake of convenience of description . The function of each circuit block is not limited to the case, in which the circuit blocks realize different functions, although the block diagram shows that the circuit blocks are processed by one circuit block . and, are shown in a block diagram for the sake of convenience in the description and the circuit blocks are shown in a, block diagram.

(Embodiment 1)

In the present embodiment, as an example, of the oxide semiconductor memory device, DOSRAM( register trademark) is illustrated ."DOSRAM", which means Dynamic Oxide Semiconductor Random Access Memory."DOSRAM" that the storage device: memory cell is 1T1C( transistor and one capacitor) type cell; writing transistor is OS transistor.

'Example of DOSRAM'.

1 Is a functional block DOSRAM showing a configuration example . and 1 of FIG. DOSRAM100 includes a control circuit 102, row circuit 104, column circuits 105, and a sense amplifier (MC) array (SA) row circuit 120. including a decoder 104 word line driver 111, column selector 112, and a sense amplifier driver 113 column circuit 114. including a global sense amplifier block 105 and an input output 115 116. (I/O) circuit.

DOSRAM100 Inputted voltage VDDD, VDH, VSSS, Vbg1, clock signal CLK, address signal ADDR, signal CE, GW, BW. may be appropriately selected by DOSRAM100 or, in, and other circuits or signals, may be added to the input signal and output signal of other circuits, and . for example, DOSRAM100 bit long (according to an operation, circuit configuration) DOSRAM100, of a circuit board, or the like.

Control circuit 102 is a logic circuit DOSRAM100 capable of controlling all operations, of control circuit 102 to have a function CE, GW, BW for performing a logic operation on signal 104 and a control signal generating row circuit 105 and column circuit, to perform a decision operation, and, additional signal CE, GW, BW is a chip enable signal, global write enable signal, byte write enable signal . respectively.

DOSRAM100 Uses hierarchical bit line structure .MC and SA array 120 including a plurality of blocks 130 and a plurality of global bit line, blocks 130 including a plurality of memory cells, and a plurality of word lines. where, divides block 130 by N.₀ (N₀ An integer 1 of). or more further, uses symbols 130 when one of the particular blocks 130 is required.<0>The, when intended to refer to an arbitrary unit, uses the symbol 130. or the like as well, in order to distinguish a plurality of constituent elements.<1>Equal sign.

To FIG. 1B, the structures MC and SA of the 120, and 130 array .MC blocks SA, the array 120 having a structure 121 in which the memory cell array 125 is stacked on the sense amplifier array, includes 121 sense amplifier arrays N.₀ Memory cell array 131, of read amplifier block 125 includes N.₀ A local cell array 135. block 130 has a structure 131 in which a local cell array 135 is stacked at a sense amplifier block.

The local cell array 135 includes a plurality of memory cells 20. as shown 1C, memory cells 20 including a transistor Tw1, capacitor C1, and a WL, transistor BL( having a back gate, and a voltage BLB), wiring BGL. VSSS. The transistor, is electrically connected Tw1 to the word line OS bit line, and the line BGL by a voltage . e.g. by the input voltage BGL to the memory cell Vbg1. in the memory cell array Vbg1 20 135 in the form of a memory BL, BLB cell WL, line Tw1, BGL. and the wiring.

Since the band gap of the metal oxide is 2.5eV or more, OS transistor has extremely small off-state current, as an example, and the off-state current having a voltage of 3.5V at room temperature (25 °C) and at room temperature of 1 μ m may be set to be lower 1 × 10.^-20 A, Is preferably lower than 1 × 10.^-22 A, Is more preferably less 1 × 10.^-24 A. That is, drain current may be 20 or more and 150 or less . and thus, memory cell 20 may be used as nonvolatile memory device Tw1 since the amount of charge leakage from the holding node via transistor, is at least, DOSRAM100.

As the metal oxide OS applied to, transistors, an oxide of Zn oxide, Zn-Sn oxide, Ga-Sn oxide, In-Ga and, In-Zn oxide In-M-Zn is (M or Ti, Ga, Y, Zr, La, Ce, Nd, Sn and Hf) additionally, contains indium and zinc and one or more, selected from aluminum, gallium, yttrium, copper, vanadium, titanium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and, magnesium and the like are also included.

In order to improve the reliability of OS transistor and electric characteristics, metal oxide CAAC-OS, CAC-OS, nc-OS for a semiconductor layer is preferably .CAAC-OS, for short, c-axis-aligned crystallinemetal oxide semiconductor of .CAC-OS and short Cloud-Aligned Composite metal oxidesemiconductor of .nc-OS is referred to as short nanocrystalline metal oxide semiconductor of, for short.

CAAC-OS Has c-axis orientation, whose crystal structure is bonded in a-b-plane direction and the crystal structure has distortion . and, distortion refers to a portion, of lattice arrangement in a region in which lattice alignment is uniform among regions in which a plurality of nanocrystals are joined to another lattice arrangement.

CAC-OS Has a function (for allowing electrons) or holes, to be used as carriers to flow therethrough or not to allow electrons to flow therethrough, that is, can achieve both high-state current and extremely low off-state current by dividing, the channel formation region, for CAC-OS transistors, so OS. transistors are very suitable for a write transistor . OS, for a memory cell.

The sense amplifier block 131 is provided with a function and the sense amplifier 132. sense amplifier 132 has a function of comparing the voltage between bit line BL and bit line BLB as well as amplifying bit line BL and bit line BLB voltage difference function. additionally, in the example of FIG. 132 using sense amplifier. 1B and, BL are bit line pair BLB sometimes referred to herein as bit line pair. (BL,BLB).

Since transistor Tw1 is OS transistor, local cell array 135 can be stacked on sense amplifier block 131 by employing this stacked structure to shorten bit line. below, to FIG. 2A illustrating the structure example 2D of a bit line in accordance with an aspect of the present invention and FIG. to FIG. 2A show comparative example, 2D. 2B

In the comparative example of FIG. 2D, sense amplifier array and memory cell array do not have a stack structure, sense amplifier disposed in the column circuit, and thus, bit line length in the comparison example of FIG. 2D is almost the same, as the length of the memory cell array.

In the comparison example of FIG. 2C, the memory cell array is divided into a plurality of local cell arrays, and a local cell array is stacked on the sense amplifier block. whereby, can shorten the bit line by, as well as, smaller (below CPB) per bit line in this comparison example as the bit line capacitance .CPB becomes smaller as the bit line incidental capacitance, is reduced (.).

Si Of the capacitor DRAM of the memory cell, as in 20 also C1 of the conventional Cs transistor is less, which facilitates DOSRAM100 operation speed, power consumption, manufacture yield, etc. by, bit line capacitance reduction capacitor Cs, which can simplify the structure of capacitor, and its manufacturing process Cs, and further, in capacitor C1 hours. DOSRAM100 may be facilitated by a capacitor .

2B Is an enlarged display of bit lines 2C of FIG. showing a portion of the local cell array and sense amplifier block 2B of FIG. for connecting the bit lines, of the sense amplifier and sense amplifier block (BL,BLB) to the sense amplifier bank, for this purpose, that is, in the present embodiment, the bit line in the sense amplifier and the bit line within the local cell array,are shown in the embodiment shown, 2A for this purpose, respectively.

First, to FIG. 4, the circuit configuration example 131, of the local cell array 135 of the sense amplifier block, is illustrated in FIG. 4 showing eight of the local cell array 135 and an example CPB of the pair (GBL,GBLB) of pair of global bit lines pairs (BL,BLB).

The sense amplifier block 131 is input to the signal EQ, EQB, SEN, SENB, CSEL[ 3:0] and the voltage Vpre. signal EQB, SENB as the inverted signal EQ, SEN of the signal . respectively.

The sense amplifier 132 includes an equalizer 31, sense amplifier 32 and a selector 33. signal EQ, EQB that signal 31 the equalizer, to an active state to signal SEN, SENB the sense amplifier 32 to an active state by the sense amplifier driver, to generate EQ, EQB, SEN, SENB. the local cell array 135 114.<j>(j Is 0 through N.₀ The integer -1 of) is the access object and, reads the amplifier driver 114 to sense amplifier block 131.<j>In an active state, the other sense amplifier block 131 generates a signal EQ, EQB, SEN, SENB. in an inactive state so that power, consumption DOSRAM100 of can be reduced by performing control as described above.

Signal CSEL[ 3:0] is generated 113 by column selector, using signal CSEL[ 3:0] to turn any one of four sets of bit line pairs (BL,BLB) with global bit line pair (GBL,GBLB).

Each global bit line pair 115 in global read amplifier block, is provided with a global sense amplifier (GBL,GBLB) having a function 140. for writing data to global bit line pair 116 in input output circuit, and read circuit (GBL,GBLB) write circuit 142 143. having a function of holding data input to global bit line (GBL,GBLB) pair 143. and output held data. 142. (GBL,GBLB)

In the circuit diagram 4 of FIG. although the sense amplifier block 131 and the local cell array 135 are shown with the bit lines BL as shown, the sense amplifier block 3A and the local cell array 131 may be arranged 135 such that, FIG. BL corresponds to the circuit diagram 135 of FIG. as a comparative example, and FIG. 3A, shows the circuit diagram 2B 2A of. 3B FIG.

In the comparative example 3B of FIG. a portion 135 of bit line Tw1 provided above transistor BL in the local cell array, indicates that bit line, is shortened as compared 3A to FIG. 135 in FIG. and the connection structure example of bit line 3A and memory cell, of BL in FIG. will be described 3A. in Embodiment BL BL. The comparison 1/2 example will be described 3 below with 3B dotted line 20 portions of FIGS.

The larger, the voltage difference, by the bit line capacitance (Cbit) as an index Cs affecting the read performance as the bit line capacitance .Cs/Cbit and the capacitance, can reduce the capacitance 20 of the capacitor, by reducing the bit line capacitance, Cs/Cbit is as large as, and thus, has more excellent readout performance as compared, to the conventional Cbit, using C transistors at the same time as the capacitance value Cs. of the storage cell, is equalized to the readout performance can be achieved, by decreasing Si the bit line capacitance. DOSRAM100 DRAM. C1. The higher the readout, performance is possible Cs.

Since the transistor Tw1 is OS transistor, having a very small off-state current, even when its capacitance Cs is smaller DRAM capacitance, DOSRAM100 has excellent retention characteristics DRAM compared to the conventional . so, DOSRAM100 can make the capacitance C1 of the capacitor Cs smaller, so it is preferable.

DOSRAM100 In, the local cell array 135 may have a multilayer structure, and FIG. 5 illustrates an example 135a of the local cell array 135c formed by three layers of cell arrays 135 through, in which the routing portion, of the bit line 135b is electrically connected BL to the transistor, of the cell array 135c. Tw1.

Although the sense amplifier 132 is illustrated as an example Si of, transistors, it may be composed OS of transistors.

The bit line structure disclosed in this embodiment may also be used for another oxide semiconductor memory device, such as, of NOSRAM( transistors for).NOSRAM-type or Nonvolatile Oxide Semiconductor RAM-type gain cells, for example, of the memory cell 2T including the transistor 3T and the write word line, NOSRAM. OS. The memory cell, may also be provided with the bit line, and the bit line 6 . 22. The read-out bit lines Tw2, Tr2, Ts2 and, may be formed by Tw2, Tr2, Ts2 × OS transistors, of the memory cell of the memory cell of the present embodiment or both of the read bit line 22 WBL, and the read-out bit SL line WL . respectively WBL RBL Tr2 of the RBL memory cell may be implemented, in any of the above-described embodiments of the present disclosure and WBL the read RBL-only memory cell, are connected 22 to one or both of the, bit lines WWL, of the memory cell. RWL.

The bit line structure disclosed in this embodiment can be used for a semiconductor device, composed of a stacked transistor, and the parasitic capacitance of the wiring, wiring becomes smaller, whereby the performance, of the semiconductor device can be improved.

(Embodiment 2)

In the present embodiment, includes an electronic device including the above-described oxide semiconductor memory device, an electronic device,and the like.

The above-described oxide semiconductor memory device can be mounted to various processor chips such as CPU chip, GPU chip, FPGA chip and application processor (AP) chip. and, here as an example shows a structure example AP. chip.

7 Shown in FIG. AP includes 600 a central computing device CPU(, a memory controller)610, GPU(, a memory controller)612, an audio processing unit 614, a video processing unit 615, and a display control unit 616, which are arranged on a die 621, to note 622, AP the oxide semiconductor memory device 600 623 described above, as appropriate depending on the purpose and, the like of the 614 IC chip 624. of the device.

The AP-video processor 600 is provided with a display controller, and a multi-display controller, such as 621 memory control unit, DRAM for controlling various peripheral devices, such as memory controller 622 using controller, and audio processing unit 623 of flash memory for processing, video data, such as video decoder, and video encoder. 624. The control unit, is provided with various functions.

The memory chip 630 constituted by the above-described oxide semiconductor memory device and the processor chip 640 on which the above-described oxide semiconductor memory device is mounted may be mounted in various electronic devices such as, in an electronic device, memory chip, may replace 630 chips or flash memory chips DRAM, and an example, of several electronic devices mounted with memory chips 8 640 and 630 or processor chip, is shown.

The robot 7100 includes an illuminance sensor, microphone, camera, speaker, display, various sensors (infrared sensor, ultrasonic sensor, acceleration sensor, optical sensor, gyro sensor, and a moving mechanism-like) processor chip, that controls the peripheral device 640 such as, memory chip, to store data 630 acquired by the sensor.

The microphone has a function, that detects audio signals such as voice and ambient sound of a user, and the robot, may analyze the audio signal, input from the speaker through the microphone and the robot 7100 may communicate,with the user through the use 7100 of a microphone and a speaker.

The camera has a function 7100 of capturing an image around the robot . and the robot, has a function 7100 moving using a moving mechanism, and the robot, may analyze the image 7100 to determine the presence or absence of an obstacle when moving by using the camera to capture surrounding images .

The flying object 7120 includes a propeller, camera and a battery or the like, and has an autonomous flight function, processor chip 640 that controls the peripheral device.

For example, camera photographed image data may be stored to the memory chip 630. processor chip 640, may estimate the remaining charge, of the battery by analyzing the change in the storage capacity of the battery by the processor chip, by analyzing the image data 640. photographed by the camera.

Although the floor sweeping robot 7140 includes a plurality of cameras, brush, operating buttons disposed on the side surface, various sensors and the like, are not shown . of the floor sweeping robot 7140 mounted with a tire, suction port may automatically walk, to detect the garbage 7140 from sucking the garbage, from the suction port of the bottom surface.

For example, processor chip 640 may determine whether, additional, of the obstacle such as wall, furniture or step by analyzing the image, captured by the camera may stop rotation, of the brush in the event that a wiring or the like may be detected by image analysis or the like.

The automobile 7160 includes an engine, tire, brake, steering device, camera and the like, such as, processor chip 640 for storing image data captured by a control, such as, camera optimized for driving state of automobile, 7160 to memory chip . in order to optimize the, driving state of automobile (s 630.) .

Memory chips 630 and/or processor chip 640 may be installed in TV( television reception) device 7200, smart phone 7210, PC( personal computer)7220, 7230, gaming machine 7240, 7260, or the like.

For example, processor chip TV disposed within 7200 device 640 may be used as image engine . such as, processor chip 640 for noise removal, resolution up-conversion (up-conversion) image processing.

The smartphone 7210 is an example, of a portable information terminal, and the smartphone 7210 includes a microphone, camera, speaker, and various sensors and a display portion, processor chip 640 that controls the peripheral device.

PC7220, 7230 Is an example PC, of notebook PC desktop, and display device 7232 may be wireless or wired connected to 7233 gaming machine PC7230. as an example 7260 gaming machine, of a portable gaming machine to wirelessly or wirelessly connect 7260 to controller 7262 to mount memory chips, and 7262 or processor chip 630 in controller/640.

(Embodiment 3)

Embodiment DOSRAM100 FIG. shows a cross-section 9 of a typical block 130, as described above, in block, sense amplifier block 130 of, sense amplifier block array 131, and FIG. 135. corresponds to a cross-sectional view, 3A of the circuit diagram of FIG. 9.

9 Shown in, sense amplifier block 131 is provided with bit line BL, Si transistor Ta10, Ta11.Si transistor Ta10, Ta11 including semiconductor layer .Si transistor Ta10, Ta11 in a single crystal silicon chip to form sense amplifier 132 and electrically connected BL to bit line.

In the local cell array 135, two transistors Tw1 share the semiconductor layer, and the bit line BL sharing a plurality of electrical conductors, through which the transistor, and the bit line Tw1 conduct BL through the connection structure, to sense the bit line, between the amplifier block 131 and the local cell array 135 in the local cell array 135 BL.

Thus, bit line BL is shortened and bit line BL does not have cross section WL with word line, whereby Cbit. can reduce bit line parasitic capacitance, such that capacitor Cs of small capacitance C1 can reduce area 20. of memory cell, by reducing area C1, of capacitor 20 10, thereby, allowing. to. DOSRAM100 be miniaturized C1.

9, And 10, the connection structure of the semiconductor layer and the wiring can be used for stacking a plurality of semiconductor devices, formed by a plurality of circuits having a group of transistors.

9, And 10, the metal oxide, insulator, conductor and the like can be a single layer or a stack . and various film forming methods, such as a sputtering method, molecular beam epitaxy (MBE) method, pulse laser ablation (PLA) method, CVD atomic layer deposition method, can be used for manufacturing the layers (ALD.). The method includes plasma .CVD method CVD, thermal CVD, method CVD.

, Shows a semiconductor layer of the transistor Tw1 composed of 3 layers of a metal oxide layer, and these metal oxide layers are preferably composed, of the above-described metal oxide layer, and, and In, Ga Zn of, the metal oxide layer are more preferable.

The low resistance, for example . may set the source region and the drain region, in the semiconductor layer by selectively lowering the carrier density of the metal oxide forming element or the element, metal oxide bonded to the oxygen defect by, for example, selectively using a, semiconductor layer using a metal oxide.

In addition, boron or phosphorus, typically used as the element, for low resistance of the metal oxide may be helium, neon, argon, krypton and xenon, as a typical example, rare gas such as hydrogen, carbon, nitrogen, fluoro. sulfur, chlorine, titanium, rare gas.

For example, a dummy gate, may be selectively low-resistance, specifically, by using a dummy gate, and the element, is added to the semiconductor layer via an insulating layer and added thereto by the ion implantation method, in, where the ionized source gas is not mass-separated by a method, such as ion doping method: in which the ionized source gas is not mass-separated by the following method ; and.

As the conductive material, for the conductor, an indium tin oxide: containing tungsten oxide; such as a semiconductor; nickel silicide typified by a polycrystalline silicon doped with an impurity element such as phosphorus or tungsten, molybdenum, tantalum, aluminum, copper, chromium, or molybdenum, such as indium tin oxide, containing titanium oxide may be used ; (, The conductive material is a, metal, containing, tungsten oxide, or a metal, nitride) titanium, or the like containing, tungsten oxide, as an active component, or the like, or, the like.

As the insulating material, usable for the insulator, oxynitride, aluminum oxynitride, aluminum oxynitride, oxynitride, oxide, silicon, oxynitride, yttria, oxide, yttria- oxynitride, oxynitride is a compound, oxynitride of which the oxygen content, is greater, than the nitrogen, content and refers, to, a compound, having a nitrogen content greater than the oxygen content.

[Symbol description]

20,Memory cell ;31:32: equalizer ;33: sense, 100:DOSRAM;102: amplifier ;104: selector ;105: control circuit ;111:112: column circuit ;113: decoder ;114: sense amplifier ;115: driver sense amplifier ;116: memory control ;120: portion sense amplifier array (MC SA) memory control ;121: portion ;125: sense amplifier bank ;130:131: intelligence mobile phone ;132: keyboard ;135: display device game ;135a, 135b, 135c:140: machine game machine ;142, 143: 600:AP( controller) read out ;614:615: amplifier ;616: bank memory ;621: control ;622: portion, memory ;623: control unit ;624: array sense amplifier ;630: bank select ;640: 7100: memory control ;7120: unit ;7140:7160: memory control ;7200:TV portion ;7200: sense amplifier ;7210: bank portion sense amplifier bank select signal sense amplifier circuit memory control portion sub array memory device memory control portion (IC) memory control portion (FIGS. and ;7220, 7230:PC;7232:7233:7240:) memory chip memory control portion.7260: 22:7262: