Настройки

Укажите год
-

Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

Подробнее
-

Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

Подробнее

Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Укажите год
Укажите год

Применить Всего найдено 9681. Отображено 200.
20-12-2012 дата публикации

МОДУЛЬ ОПЕРАТИВНОЙ ПАМЯТИ

Номер: RU123203U1

Модуль памяти, содержащий множество микросхем памяти размещенных на одной поверхности печатной платы и соединенных с соединительным разъемом, расположенным на печатной плате, отличающийся тем, что множество микросхем памяти образуют канал памяти, при этом центры микросхем памяти канала расположены на одной прямой линии, параллельной внешней поверхности соединительного разъема, который размещен на поверхности платы противоположной поверхности, на которой размещены микросхемы памяти, один канал памяти соединен с одним соединительным разъемом, длина соединительных элементов, соединяющих микросхемы памяти канала памяти с соединительным разъемом, одинакова, а в каждом углу печатной платы расположены крепления, улучшающие прижим модуля памяти к единому радиатору вычислительного модуля.

Подробнее
01-12-2023 дата публикации

ПОЛУПРОВОДНИКОВОЕ ЗАПОМИНАЮЩЕЕ УСТРОЙСТВО

Номер: RU2808680C1

Изобретение относится к полупроводниковым запоминающим устройствам. Полупроводниковое запоминающее устройство согласно изобретению содержит множество массивов хранения данных; по меньшей мере один модуль проверки, каждый из которых соответствует множеству массивов хранения данных и приспособлен для проверки наличия ошибки в информации в виде данных соответствующего массива хранения данных, причем каждый модуль проверки подключен к группе глобальных шин данных; и содержит множество схем пропускания, соответственно подключенных к массивам хранения данных и глобальным шинам данных и приспособленных для управления открыванием-закрыванием канала передачи данных между глобальными шинами данных и массивами хранения данных, которые подключены друг к другу. Изобретение обеспечивает высокую надежность считывания-записи данных. 10 з.п. ф-лы, 7 ил.

Подробнее
07-07-1983 дата публикации

Устройство для контроля матриц памяти

Номер: SU1027780A2
Принадлежит:

... 1. УСТРОЙСТВО ДЛЯ КОНТРОЛЯ МАТРИЦ ПАМЯТИ по авт. св. 89в507, отличайте.вся тем, что. с целью повыиения достоверности контроля, в него введен селектор строк, входы которого соединены соответственно с одними из выходов генератора синхросигналов и формирователя тестовых сигналов, а выход подключен к одному из входов блока мест ного управле н ия. 2. Устройство по п. 1, о т л ичающе еся тем, что селектор строк содержит коммутатор и 5Rтриггер , S- и R-входы которого соединены с выходами коммутатора, счетный вход OR -триггера и входы коммутатора являются входами селектора строк, выходом Которого является выход SR-триггера.

Подробнее
01-01-1959 дата публикации

Матрица для запоминающих устройств

Номер: SU120044A1
Принадлежит:

Подробнее
20-10-1966 дата публикации

Постоянное запоминающее устройство

Номер: SU187836A1
Автор: Макаров А.П.
Принадлежит:

Подробнее
15-04-1969 дата публикации

ЛОГИЧЕСКОЕ ЗАПОМИНАЮЩЕЕ УСТРОЙСТВО

Номер: SU229609A1
Принадлежит:

Подробнее
11-11-1969 дата публикации

Диодно-матричный коммутатор

Номер: SU256821A1
Принадлежит:

Подробнее
05-05-1969 дата публикации

Запоминающее устройство

Номер: SU242974A1
Принадлежит:

Подробнее
15-03-1987 дата публикации

Формирователь импульсов записи

Номер: SU1297114A1
Принадлежит:

Изобретение относится к вычислительной технике и предназначено для использования в электрически программируемых полупостоянных ЗУ, использующих инжек- цию горячих носителей для записи информации в ячейки памяти накопителя. Цель изобретения - повышение надежности устройства . Поставленная цель достигается тем, что в формирователь введены третий ключевой транзистор 13 и запоминающий транзистор 12 с соответствующими связями . При достижении напряжения на щине записи необходимого уровня открывается транзистор 13 и через транзистор 4 тока смещения поддерживает на затворе транзистора записи 1 необходимый уровень. 1 з. п. ф-лы 1 ил. к ...

Подробнее
30-07-1987 дата публикации

Способ изготовления контактной колодки

Номер: SU1327181A1
Принадлежит:

Изобретение относится к приборостроению , в частности к контактным соединениям. Цель изобретения - снижение трудоемкости изготовления.Прессуют диэлектрическое основание с коническими отверстиями. Из листового материала вырубают соединенные перемычками контактные лепестки. Лепестки свободными концами устанавливают в конические отверстия диэлектрического основания. Лепестки в отверстиях фиксируют, после чего перемычки удаляют, например, обрубкой на штампе .

Подробнее
05-05-1980 дата публикации

Запоминающее устройство с самоконтролем

Номер: SU733034A1
Принадлежит:

Подробнее
30-11-1989 дата публикации

Номер: DE0003730095C2
Принадлежит: MITSUBISHI DENKI K.K., TOKIO/TOKYO, JP

Подробнее
21-01-2010 дата публикации

Halbleiterspeichervorrichtung

Номер: DE0019652870B4

Halbleiterspeichervorrichtung, umfassend: ein Speicherfeld (100) mit einem ersten, zweiten, dritten und vierten Feldblock (10–40), wobei die Feldblöcke in Form einer 2×2-Matrix angeordnet sind und dadurch zwei Zeilen und zwei Spalten von Feldblöcken bilden; eine Vielzahl von zwischen den Zeilen der Feldblöcke angeordneten Anschlußflächen; einen in einem Zentrumsbereich (70) des Speicherfelds angeordneten Datenpfadschaltkreis (50, 112, 114, 122, 124, 212, 214, 222, 224): eine Vielzahl von Datenleitungen (DL), die die Anschlußflächen mit dem Datenpfadschaltkreis verbinden; und eine Vielzahl von Haupteingangs/Ausgangsleitungen (MIO), die die Feldblöcke mit dem Datenpfadschaltkreis verbinden, dadurch gekennzeichnet, daß die Halbleiterspeichervorrichtung ferner einen zwischen den Spalten der Feldblöcke angeordneten Datenpfadsteuerschaltkreis (60) umfaßt; und die Vielzahl der Haupteingangs/Ausgangsleitungen lediglich zwischen den Zeilen der Feldblöcke angeordnet sind.

Подробнее
13-05-2015 дата публикации

Speicherbaustein

Номер: DE112006004263B4
Принадлежит: GOOGLE INC, GOOGLE, INC.

Speicherbaustein (700), aufweisend: mehrere industriestandardisierte integrierte dynamische Direktzugriffsspeicher(DRAM)-Schaltkreise (720), die in einer vertikalen Richtung gestapelt sind, wobei die mehreren integrierten DRAM-Schaltkreise einen Arbeitspool (885, 886) von integrierten DRAM-Schaltkreisen und einen Ersatzpool (895) von integrierten DRAM-Schaltkreisen aufweisen; und einen integrierten Pufferschaltkreis (710) zum Bilden einer Schnittstelle zwischen den integrierten DRAM-Schaltkreisen und einem Speicherbus (730) durch Puffer von Adress- und/oder Steuer- und/oder Datensignalen, um elektrische Lasten der integrierten DRAM-Schaltkreise von dem Speicherbus elektrisch zu isolieren, wobei der integrierte Pufferschaltkreis konfiguriert ist, um zumindest einen integrierten DRAM-Schaltkreis von dem Arbeitspool von integrierten DRAM-Schaltkreisen durch zumindest einen integrierten DRAM-Schaltkreis von dem Ersatzpool von integrierten DRAM-Schaltkreisen zu ersetzen.

Подробнее
10-12-1970 дата публикации

Magnetspeicher

Номер: DE0001549086A1
Принадлежит:

Подробнее
29-09-2005 дата публикации

Arrangement of semiconductor elements on a wafer has capacitors near sawing edge and fuse elements near chips for testing

Номер: DE102004012238A1
Автор: ZIMEK BERND, ZIMEK, BERND
Принадлежит:

An arrangement of semiconductor elements comprises a semiconductor wafer (1) for chips (2) with sawing frames (3) between chips for dicing and with capacitors and fuse elements for chip testing. The fuses are for producing or breaking electrical connections by using the charging/discharging of the capacitors.

Подробнее
07-02-1991 дата публикации

STATISCHE HALBLEITERSPEICHERANLAGE.

Номер: DE0003177237D1

Подробнее
24-07-2008 дата публикации

Halbleiterspeicher vom wahlfreien Zugriffstyp (DRAM)

Номер: DE0019960558B4
Принадлежит: QIMONDA AG

Halbleiterspeicher (1) vom wahlfreien Zugriffstyp, mit Speicherzellen, die in mindestens vier matrixförmigen Speicherzellenarrays (A1, ..., A4) eines Speicherfeldes (A) angeordnet sind, bei dem die Speicherzellen in adressierbaren Einheiten von Spaltenleitungen (BL) und Zeilenleitungen (WL) zusammengefaßt sind, wobei jeweils einem Speicherzellenarray (A1, ..., A4) ein Zeilen-Decoder (RD) zur Auswahl einer der Zeilenleitungen (WL) des Speicherzellenarrays und ein Spalten-Decoder (CD) zur Auswahl einer der Spaltenleitungen (BL) des Speicherzellenarrays zugeordnet ist, wobei die Zeilen-Decoder (RD) der mindestens vier Speicherzellenarrays (A1, ..., A4) zur Auswahl einer der Zeilenleitungen (WL) mit einer Zeilen-Auswahlsignal-Leitung (RL), welche zur Übertragung eines Zeilen-Auswahlsignals (RADR) vörgesehen ist, verbunden sind, – wobei jedes der Speicherzellenarrays (A1, ..., A4) je zwei Seiten aufweist, die einer Seite eines anderen der Speicherzellenarrays (A1, ..., A4) gegenüberliegen, – ...

Подробнее
28-09-1978 дата публикации

SPEICHERSYSTEM

Номер: DE0002812657A1
Автор: ITOH KIYOO, ITOH,KIYOO
Принадлежит:

Подробнее
01-07-1993 дата публикации

Halbleiterspeichervorrichtung

Номер: DE0004244085A1
Принадлежит:

Подробнее
07-09-1972 дата публикации

Номер: DE0002054296A1
Автор:
Принадлежит:

Подробнее
29-12-1967 дата публикации

A rod memory array

Номер: GB0001096840A
Автор:
Принадлежит:

... 1,096,840. Magnetic storage apparatus. NATIONAL CASH REGISTER CO. July 8, 1966 [Aug. 6, 1965], No. 30799/66. Heading H3B. In a rod memory array insulated conductive wire is woven perpendicular to the axes of the magnetic rods so that the wire passes by opposite sides of adjacent rods to produce a plurality of half-turn solenoids each coupled to a respective one of the rods. A plate 10, Fig. 1, provided with apertures 10a is first positioned over dummy rods 15a on a support 15 which rods protrude through the apertures 10a to act as mandrels about which the solenoid weaving pattern 18 is formed. After the solenoids have been formed the pins 15a are formed and the magnetic rods 12 comprising an inner conductive substrate on which is deposited a thin bi-stable magnetic film, Fig. 2 (not shown), are inserted in their place. In the weaving pattern of Fig. 1 of a particular row or column a conductive wire starts at a guide pin 19, is woven back and forth between the pins 15a until the end of the ...

Подробнее
26-03-1969 дата публикации

Improvements in or relating to methods of manufacturing magnetic matrix arrangements

Номер: GB0001146615A
Автор:
Принадлежит:

... 1,146,615. Magnetic storage apparatus. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 16 March, 1966 [19 March, 1965], No. 11525/66. Heading H3B. A magnetic storage matrix is made from a semi-conductor wafer, the peripheral areas of the wafer having transistors and diodes formed on insulated islands and the magnetic storage elements being formed by magnetically coating a network of grooves surrounded by the islands. A silicon wafer has an appropriately doped layer for the initial stages of the manufacture of diodes and transistors grown epitaxially thereon. This layer is then removed as far as the areas to be occupied by the diodes and transistors and coated with a silicon insulating layer, Figs. 1, 2 (not shown). The insulating layer has grown on to it a polycrystalline layer and the opposite side of the block is removed by grinding so that a semi-conductor wafer is obtained which has insulated islands (I) for the formation of the transistors and diodes, the finished wafer being in the ...

Подробнее
24-11-2004 дата публикации

Memory stick enclosures

Номер: GB0002401828A
Принадлежит:

A memory stick 10 has a memory module 11 which has an interface 14 connectable to an I/O port of an electronic apparatus, and a container 41 accommodating the memory module 11, the container having a clip 42 at the periphery for fastening, an end cap 21 detachably fastened to one end to protect the interface 14, and a tie hole 20 for cord, etc, or connector 46 at the other end. This connector may be used to attach a tool, for example an envelope knife (50, figure 8), key ring, screwdriver, pen (figure 9), laser pointer, lipstick, flash lamp, etc. The memory module may be removed from the container for use. The tool is useable without the memory module.

Подробнее
07-08-1968 дата публикации

Improvements relating to magnetic storage arrangements

Номер: GB0001122385A
Принадлежит:

... 1,122,385. Circuits employing bi-stable magnetic elements. PLESSEY UK Ltd. 3 Dec., 1965 [7 Dec.. 1964], No. 49628/64. Heading H3B. A magnetic storage element comprises a thin film F of isotropic material having a rectangular hysteresis characteristic, parallel first and second word conductors U, V and an orthogonal digit conductor D being positioned in operative proximity. All three conductors are energized to write a binary " 1." The film may be of nickel-iron alloy which is deposited on to a glass or copper cylindrical former by evaporation, chemical deposition or electroplating, the first and second word conductors being subsequently threaded through the cylindrical former. A matrix store is shown in Fig. 3 in which a binary word may be stored magnetically along any of the cylindrical films F1-F9. To write a word a first and a second word conductor U, V common to a selected cylindrical film are pulsed at the same time as digit conductors D1, D2 are selectively energized. Coincident energization ...

Подробнее
03-07-1991 дата публикации

SEMICONDUCTOR MEMORY DEVICE SIGNAL LINE LAYOUT

Номер: GB0002239556A
Принадлежит:

High density memory devices generally include a plurality of word line devices connected to a plurality of word lines, a plurality of bit lines, and various decoders. In such memory devices, capacitances between adjacent lines can cause unwanted coupling noise and consequent mis-routing of signals. A memory device aimed at overcoming some of these problems includes in a memory cell array a plurality of bit lines BL, a plurality of word lines WL, and a plurality of sense amplifiers SA. The word lines are twisted in groups of four such that lines which are adjacent over part of their length become non-adjacent over another part of their length and are arranged in such a way as to reduce the coupling capacitances between the lines. ...

Подробнее
02-06-1966 дата публикации

A method of inserting wires into parallel slots

Номер: GB0001031410A
Принадлежит:

... 1,031,410. Magnetic storage apparatus. STANDARD TELEPHONES & CABLES Ltd. Nov. 12, 1964, No. 46120/64. Heading H3B. Wires are inserted into parallel slots 28 of a ferrite plate 27 of a waffle-iron memory by winding a continuous piece of wire around two spaced parallel rods 10, 11 so that successive upper 25 and lower 26 lengths of the wire between the rods are spaced from one another along the lengths of the rods by the distance between the slots 28, and inserting the successive lengths of wire into the slots. The rods 10 and 11 are provided with a helical thread having twice the pitch of the slots, and after winding the wire on the jig the latter is lowered so that the lower half 26 of the wire is lowered into alternate slots 28 and followed by the upper half 26. Alternatively, the two halves may be clamped coplanar before insertion. After anchoring the wires they are severed along rod 10 and rod 11 withdrawn. A polished substrate coated with an isotropic magnetic film is placed over the ...

Подробнее
26-10-1966 дата публикации

Improvements relating to magnetic data storage matrices

Номер: GB0001046454A
Принадлежит:

... 1,046,454. Magnetic storage apparatus. ELECTRIC & MUSICAL INDUSTRIES Ltd. Feb. 6, 1963 [Nov. 10, 1961], No. 40262/61. Heading H3B. A magnetic matrix store is constructed by bonding two sheets of copper together by means of an insulating resin, etching the copper sheets so as to form row and column conductors A, B supported by a resin sheet, bonding the assembly into a frame C, dissolving the resin sheet other than that immediately between the row and column conductors, insulating the conductors with a suspension of glass powder in resin followed by a lacquer coating, and finally depositing a film of magnetic alloy over the lacquer coating. The row and column conductors may be arranged either as shown in Fig. 1 or in Fig. 2. Alternatively the conductors may be positioned as shown in Fig. 3. In a modification the manufacturing stage of dissolving the resin sheet is omitted, and both sides of the sheet with the affixed conductors are coated with magnetic alloy with or without the lacquer coating ...

Подробнее
11-01-1967 дата публикации

Номер: GB0001054722A
Автор:
Принадлежит:

Подробнее
01-10-1969 дата публикации

Memory matrices.

Номер: GB0001165513A
Автор:
Принадлежит:

... 1,165,513. Magnetic storage apparatus. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 24 May, 1968 [27 May, 1967], No. 24909/68. Heading H3B. A magnetic storage matrix is formed by inserting annular cores 1, into circular recesses 3 in a metal plate 2, each recess containing at least one plate projection 5 which extends through the associated core and above the plate surface, and the plate having grooves 7 of greater depth then the recesses. Subsequently, the recesses, grooves, and the plate are coated with a layer of insulating material e.g. epoxy resin, the extremities of the plate projections being exposed. The plate projections are then interconnected by wiring such as printed conductors, and the bases of the plate projections electrically separated from each other by removing material from the surface of the plate opposite the recesses to an extent such as to expose the grooves. The recesses and grooves may be formed either by etching or a compression and extrusion process, and the ...

Подробнее
18-11-1981 дата публикации

INTEGRATED SEMICONDUCTOR MEMORY DEVICE

Номер: GB0001602948A
Автор:
Принадлежит:

Подробнее
15-07-2010 дата публикации

EXCHANGEABLE CONNECTING ARRAYS FOR DOUBLE-SIDED DIMM PLACING

Номер: AT0000472801T
Принадлежит:

Подробнее
15-11-2008 дата публикации

MODULAR MEMORY MODULE

Номер: AT0000412241T
Принадлежит:

Подробнее
15-11-1989 дата публикации

SEMICONDUCTOR MEMORY.

Номер: AT0000047928T
Принадлежит:

Подробнее
15-03-1994 дата публикации

SEMICONDUCTOR MEMORY.

Номер: AT0000101746T
Принадлежит:

Подробнее
06-10-1994 дата публикации

Memory cartridge and data processing apparatus

Номер: AU0000653578B2
Принадлежит:

Подробнее
22-05-1973 дата публикации

FLEXIBLE FERRITE KEEPERS FOR PLATED WIRE MEMORY ARRAYS

Номер: CA0000926997A1
Автор: DAVIDIAN R, APICELLA A JR
Принадлежит:

Подробнее
31-08-1960 дата публикации

Procédé de fabrication d'un réseau de mémoire à noyaux magnétiques

Номер: CH0000348426A
Автор:
Принадлежит: NCR CO, THE NATIONAL CASH REGISTER COMPANY

Подробнее
15-01-1967 дата публикации

Magnetischer Informationsspeicher

Номер: CH0000427904A
Принадлежит: SPERRY RAND CORP, SPERRY RAND CORPORATION

Подробнее
15-02-1966 дата публикации

Informationsspeicher

Номер: CH0000407229A
Принадлежит: SPERRY RAND CORP, SPERRY RAND CORPORATION

Подробнее
15-03-1966 дата публикации

Magnetschichtspeicher-Anordnung

Номер: CH0000409014A

Подробнее
15-11-1968 дата публикации

Magnetische Speichermatrix

Номер: CH0000465014A

Подробнее
31-01-1963 дата публикации

Mémoire matricielle à trois dimensions

Номер: CH0000366854A
Автор:
Принадлежит: NCR CO, THE NATIONAL CASH REGISTER COMPANY

Подробнее
30-11-1967 дата публикации

Assemblage de mémoire à tiges et procédé de fabrication de cet assemblage

Номер: CH0000447283A
Автор:
Принадлежит: NCR CO, THE NATIONAL CASH REGISTER COMPANY

Подробнее
15-07-1975 дата публикации

Номер: CH0000564242A5
Автор:

Подробнее
31-03-1977 дата публикации

Номер: CH0000586447A5
Автор:

Подробнее
30-11-1978 дата публикации

Номер: CH0000607232A5
Принадлежит: IBM, INTERNATIONAL BUSINESS MACHINES CORP.

Подробнее
15-02-2004 дата публикации

НАКОПИЧУВАЧ ДЛЯ БЛОКІВ ПАМ'ЯТІ

Номер: UA0000064127 A

Накопичувач для блоків пам'яті включає до свого складу прямокутну пластину, на обидві поверхні якої нанесено групи електродів з провідного матеріалу. Пластину виконано із сегнетоелектрика, а електроди, що входять до групи та розташовані на одній із сторін пластини, паралельні між собою.

Подробнее
15-09-2003 дата публикации

БЛОК ПАМ'ЯТІ

Номер: UA0000060116 A

Блок пам'яті, що включає до свого складу накопичувач, дешифратор та регістр адреси. До блока включено додатковий накопичувач, дві схеми генерації контрольних розрядів та схему контролю. Входи першої схеми генерації контрольних розрядів підключені до відповідних входів інформаційного каналу, а виходи підключені до відповідних входів додаткового накопичувача, виходи якого у свою чергу підключені до входів схеми контролю. Входи другої схеми генерації контрольних розрядів підключені до виходів основного накопичувача, а виходи другої схеми генерації контрольних розрядів підключені до відповідних входів схеми контролю.

Подробнее
26-12-2012 дата публикации

3d array storage apparatus and operation method thereof

Номер: CN0102842339A
Автор: LUE HANG-TING
Принадлежит:

Подробнее
16-11-2016 дата публикации

Memory arrays and methods of forming memory arrays

Номер: CN0106133840A
Принадлежит:

Подробнее
21-04-2020 дата публикации

Semiconductor device, storage device and electronic device

Номер: CN0111052350A
Автор:
Принадлежит:

Подробнее
06-04-2011 дата публикации

Three dimensional structure memory

Номер: CN0102005453A
Автор: Glenn J. Leedy
Принадлежит:

A Three-Dimensional Structure (3DS) Memory (100) allows for physical separation of the memory circuits (103) and the control logic circuit onto different layers (103) such that each layer may be separately optimized. One control logic (101) circuit suffices for several memory circuits (103), reducing cost. Fabrication of 3DS memory ((100) involves thinning of the memory circuit (103) to less than 50 mum in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density interlayer vertical bus connections are used. The 3DS memory (100) manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Подробнее
22-06-2005 дата публикации

Magnetic resistance memory module device

Номер: CN0001207717C
Принадлежит: INFINEON TECHNOLOGIES AG

Подробнее
19-05-1978 дата публикации

MODULE DE MEMOIRE A SEMICONDUCTEURS MOS

Номер: FR0002368783A
Автор:
Принадлежит:

L'invention concerne un module de mémoire à semi-conducteurs MOS. Dans ce module de mémoire comportant des champs ZF de cellules de mémoire SZ, des colonnes LS de transistors de charge ML, des colonnes DZ de cellules de compensation MD, CD et des circuits d'évaluation DW, qui sont interconnectés par des conducteurs de bits BL, BR relies à des conducteurs de mots X1, X2 ainsi qu'à des conducteurs de données DA1, DA2, tous les champs de cellules de mémoire sont disposés dans le module d'un côté de la colonne des circuits d'évaluation BW. Application notamment aux modules de mémoire comportant des cellules de mémoire à un transistor MOS.

Подробнее
27-11-2020 дата публикации

3D RESISTIVE MEMORY

Номер: FR0003079656B1
Автор: ANDRIEU FRANCOIS
Принадлежит:

Подробнее
10-10-1975 дата публикации

MEMORY CORE SUBMODULE

Номер: FR0002068690B1
Автор:
Принадлежит:

Подробнее
30-08-1968 дата публикации

Magnetic storage

Номер: FR0001537999A
Автор:
Принадлежит:

Подробнее
05-12-2008 дата публикации

DEVICE OF MEMORY AT the STATE SOLID AND PROCEEDED Of FITTING OF CELLS Of a MEMORY AT the SOLID STATE

Номер: FR0002869446B1
Автор: MOTOYOSHI
Принадлежит: SONY CORPORATION

Подробнее
03-03-1961 дата публикации

Magnetic matrix for the setting in data memory

Номер: FR0001255127A
Принадлежит:

Подробнее
06-03-1964 дата публикации

Memory with self-resetting

Номер: FR0001354319A
Автор:
Принадлежит:

Подробнее
27-11-1970 дата публикации

Номер: FR0002032363A1
Автор:
Принадлежит:

Подробнее
28-10-2005 дата публикации

MEMORY DEVICE AND SOLID STATE METHOD OF ARRANGING CELLS OF [...] SOLID STATE

Номер: FR0002869446A1
Автор: MOTOYOSHI MAKOTO
Принадлежит:

Ce dispositif de mémoire à l'état solide présente un agencement bidimensionnel qui correspond à un motif à symétrie de translation sous la forme d'un réseau d'éléments de mémoire magnétiques (10) dont chacun est une structure stratifiée formée d'une couche à aimantation fixe, d'une couche formant barrière pour l'effet tunnel et d'une couche sans aimantation, dont la direction d'aimantation est variable, la structure étant commandée par un premier câblage (11) qui lui est connecté électriquement et par un second câblage (12) qui en est isolé électriquement. Application notamment aux différentes mémoires RAM, ROM, PROM et EPROM.

Подробнее
28-04-1978 дата публикации

RANDOM ACCESS MEMORY MOSFET

Номер: FR0002366663A1
Автор:
Принадлежит:

Подробнее
20-10-1972 дата публикации

HIGH?DENSITY MAGNETIC MEMORY

Номер: FR0002128089A5
Автор:
Принадлежит:

Подробнее
02-01-1970 дата публикации

IMPROVEMENTS IN OR RELATING TO FERRITE KEEPERS FOR MAGNETIC STORES

Номер: FR0002007293A5
Автор:
Принадлежит:

Подробнее
02-02-2012 дата публикации

Semiconductor memory apparatus having sense amplifier

Номер: US20120026773A1
Автор: Myoung Jin LEE
Принадлежит: Hynix Semiconductor Inc

Disclosed is a semiconductor memory apparatus comprising an upper mat and a lower mat with a sense amplifier array region in between, where the sense amplifier array region includes a plurality of sense amplifiers. There is also a plurality of bit lines configured to extend toward the sense amplifier array region from the upper mat, and a plurality of complementary bit lines configured to extend toward the sense amplifier array region from the lower mat. Bit lines of the upper mat and complementary bit lines of the lower mat are configured to be alternately disposed at a predetermined interval in the sense amplifier array region, and the sense amplifier is configured to be formed between a bit line and a corresponding complementary bit line.

Подробнее
15-03-2012 дата публикации

Semiconductor memory device having stacked structure including resistor-switched based logic circuit and method of manufacturing the same

Номер: US20120063194A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.

Подробнее
22-03-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120069530A1
Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor device includes a stacked chip includes semiconductor chips which are stacked, the semiconductor chips comprises semiconductor substrates and through electrodes formed in the semiconductor substrates, respectively, the through electrodes being electrically connected, and deactivating circuits provided in the semiconductor chips, respectively, and configured to deactivate a failed semiconductor chip.

Подробнее
19-04-2012 дата публикации

Semiconductor package

Номер: US20120096322A1
Принадлежит: Hynix Semiconductor Inc

A semiconductor package includes a memory controller chip, a plurality of first memory chips configured to store normal data, a second memory chip configured to store error information for correcting or detecting error of the normal data, and an interface unit configured to interface the memory controller chip, the plurality of first memory chips, and the second memory chip.

Подробнее
10-05-2012 дата публикации

Semiconductor device

Номер: US20120114086A1
Автор: Junichi Hayashi
Принадлежит: Elpida Memory Inc

A semiconductor device includes: an interface chip including a read timing control circuit that outputs, in response to a command signal and a clock signal supplied from the outside, a plurality of read control signals that are each in synchronization with the clock signal and have different timings; and core chips including a plurality of internal circuits that are stacked on the interface chip and each perform an operation indicated by the command signal in synchronization with the read control signals. According to the present invention, it is unnecessary to control latency in the core chips and therefore to supply the clock signal to the core chips.

Подробнее
31-05-2012 дата публикации

Memory Modules and Devices Supporting Configurable Core Organizations

Номер: US20120134084A1
Принадлежит: RAMBUS INC

Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey width selection information to configurable memory apparatus and support point-to-point data interfaces for multiple width configurations.

Подробнее
14-06-2012 дата публикации

Continuous mesh three dimensional non-volatile storage with vertical select devices

Номер: US20120147644A1
Автор: Roy E. Scheuerlein
Принадлежит: SanDisk 3D LLC

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Подробнее
14-06-2012 дата публикации

Three dimensional non-volatile storage with multi block row selection

Номер: US20120147689A1
Принадлежит: SanDisk 3D LLC

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Подробнее
19-07-2012 дата публикации

Memory System with Multi-Level Status Signaling and Method for Operating the Same

Номер: US20120182780A1
Автор: Steven Cheng
Принадлежит: SanDisk Technologies LLC

A memory system includes a status circuit having a common status node electrically connected to a respective status pad of each of a plurality of memory chips. The memory system also includes a plurality of resistors disposed within the status circuit to define a voltage divider network for generating different voltage levels at the common status node. Each of the different voltage levels indicates a particular operational state combination of the plurality of memory chips. Also, each of the plurality of memory chips is either in a first operational state or a second operational state. Additionally, the different voltage levels are distributed within a voltage range extending from a power supply voltage level to a reference ground voltage level.

Подробнее
30-08-2012 дата публикации

Magnetic memory device

Номер: US20120218804A1
Автор: Shota Okayama
Принадлежит: Renesas Electronics Corp

The present invention provides a magnetic memory device capable of providing high-speed access without increasing an array area. Gate word lines are respectively linearly disposed between source impurity regions and drain impurity regions within a memory cell array area. Gate word line protrusions are respectively provided at boundary regions of memory cell forming regions. Contacts relative to the gate word line protrusions are respectively provided at boundary regions of memory cells at adjacent columns. The drain impurity regions are respectively disposed with being shifted from the centers of the memory cell forming regions in such a manner that spaces between the drain impurity regions become large in the regions in which the protrusions are disposed.

Подробнее
06-09-2012 дата публикации

Three dimensional memory system with intelligent select circuit

Номер: US20120224410A1
Автор: Tianhong Yan
Принадлежит: SanDisk 3D LLC

A three dimensional monolithic memory array of non-volatile storage elements includes a plurality of word lines and a plurality of bit lines. The plurality of bit lines are grouped into columns. Performing memory operation on the non-volatile storage elements includes selectively connecting bit lines to sense amplifiers using selection circuits that include a storage device, a select circuit connected to the storage device and one or more level shifters providing two or more interfaces to the respective selection circuit.

Подробнее
06-09-2012 дата публикации

Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit

Номер: US20120226924A1
Принадлежит: Google LLC

A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to perform a power management operation in association with only a portion of the memory circuits.

Подробнее
13-09-2012 дата публикации

Sense operation in a stacked memory array device

Номер: US20120230116A1
Автор: Akira Goda, Zengtao Liu
Принадлежит: Micron Technology Inc

Methods for sensing and memory devices are disclosed. One such method for sensing includes changing a sense condition of a particular layer responsive to a programming rate of that particular layer (e.g., relative to other layers).

Подробнее
08-11-2012 дата публикации

Memory module and layout method therefor

Номер: US20120281348A1
Принадлежит: Elpida Memory Inc

The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.

Подробнее
31-01-2013 дата публикации

Apparatuses and methods including memory array and data line architecture

Номер: US20130028023A1
Автор: Toru Tanzawa
Принадлежит: Individual

Some embodiments include apparatus and methods having memory cells located in different device levels of a device, at least a portion of a transistor located in a substrate of the device, and a data line coupled to the transistor and the memory cells. The data line can be located between the transistor and the memory cells. Other embodiments including additional apparatus and methods are described.

Подробнее
04-04-2013 дата публикации

Novel semiconductor device and structure

Номер: US20130083589A1
Принадлежит: Monolithic 3D Inc

A semiconductor device, including: a first semiconductor layer including first transistors, wherein the first transistors are interconnected by at least one metal layer including aluminum or copper; and a second mono-crystallized semiconductor layer including second transistors and overlaying the at least one metal layer, wherein the at least one metal layer is in-between the first semiconductor layer and the second mono-crystallized semiconductor layer, wherein the second mono-crystallized semiconductor layer is less than 100 nm in thickness, and wherein the second transistors include horizontally oriented transistors.

Подробнее
16-05-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130121073A1
Принадлежит:

According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate. 1. A semiconductor device comprising:a substrate comprising a multi-layer structure with a wiring pattern, and comprising a substantially rectangular shape in a plan view;a connector to be connectable to a host device;a volatile semiconductor memory element provided on a front surface layer side of the substrate;a first nonvolatile semiconductor memory element provided on the front surface layer side of the substrate;a second nonvolatile semiconductor memory element provided on the front surface layer side of the substrate;a third nonvolatile semiconductor memory element provided on the front surface layer side of the substrate; anda controller provided on the front surface layer side of the substrate to control the volatile semiconductor memory element and the nonvolatile semiconductor memory elements,wherein the wiring pattern includes a signal line formed between the connector and the controller to connect the connector to the controller, andwherein the first nonvolatile semiconductor memory element and the second nonvolatile semiconductor memory element are aligned along the longitudinal direction of the substrate, on the opposite side of the controller to the third nonvolatile semiconductor memory element.2. A semiconductor device comprising:a substrate comprising a multi-layer structure with a wiring pattern, and comprising a substantially rectangular shape in a plan view;a connector provided on a short side of the substrate to be connectable to a ...

Подробнее
16-05-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130121074A1
Принадлежит:

According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate. 1. A semiconductor system comprising:a host device including a CPU; anda semiconductor device; wherein the semiconductor device comprises:a substrate comprising a multi-layer structure with a wiring pattern, and comprising a substantially rectangular shape in a plan view;a connector to be connectable to the host device;a volatile semiconductor memory element provided on a front surface layer side of the substrate;a first nonvolatile semiconductor memory element provided on the front surface layer side of the substrate;a second nonvolatile semiconductor memory element provided on the front surface layer side of the substrate;a third nonvolatile semiconductor memory element provided on the front surface layer side of the substrate; anda controller provided on the front surface layer side of the substrate to control the volatile semiconductor memory element and the nonvolatile semiconductor memory elements,wherein the wiring pattern includes a signal line formed between the connector and the controller to connect the connector to the controller, andwherein the first nonvolatile semiconductor memory element and the second nonvolatile semiconductor memory element are aligned along the longitudinal direction of the substrate, on the opposite side of the controller to the third nonvolatile semiconductor memory element,wherein the CPU writes information on the first nonvolatile semiconductor memory element and the second nonvolatile semiconductor memory element ...

Подробнее
30-05-2013 дата публикации

Semiconductor storage device

Номер: US20130135919A1
Автор: Makoto Hamada
Принадлежит: Individual

According to one embodiment, a semiconductor storage device includes a stripe, a sense amplifier, a global signal line, and a controller. Blocks are in the stripe. The blocks are formed in a first direction. Each of blocks is made a read unit of data and includes a memory cell capable of holding the data provided along a row and a column. The sense amplifier is provided just under each of the blocks, and reads the data. The global signal line is formed so as to penetrate through the stripe in the first direction, and transfers the data read from the block to the sense amplifier. The controller controls a value of a reference current applied to the sense amplifier according to positional relationship between each area in which the sense amplifier is arranged and the block, which is made a read target of the data, out of the blocks.

Подробнее
13-06-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20130148399A1
Автор: Murooka Kenichi
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A semiconductor memory device in accordance with an embodiment includes a plurality of first word lines, a plurality of bit lines, a resistance varying material, a plurality of second word lines and an insulating film. The bit lines intersect the first word lines. The resistance varying material is disposed at respective intersections of the first word lines and the bit lines. The second word lines intersect the bit lines. The insulating film is disposed at respective intersections of the second word lines and the bit lines. One of the first word lines and one of the second word lines are disposed so as to sandwich the bit lines. The second word lines, the bit lines, and the insulating film configure a field-effect transistor at respective intersections of the second word lines and the bit lines. The field-effect transistor and the resistance varying material configure one memory cell. 17-. (canceled)8. A semiconductor memory device , comprising:a semiconductor substrate;a plurality of first word lines extending in a stacking direction perpendicular to the semiconductor substrate, the first word lines being arranged having a certain pitch in a first direction parallel to a surface of the semiconductor substrate and being arranged having a certain pitch in a second direction parallel to the surface of the semiconductor substrate and orthogonal to the first direction;a plurality of bit lines extending in the first direction and arranged having a certain pitch in the second direction and the stacking direction, the bit lines being configured to intersect the first word lines such that a first surface of the bit lines faces the first word lines;a resistance varying material disposed at respective intersections of the first word lines and the bit lines;a plurality of second word lines extending in the stacking direction and arranged having a certain pitch in the first direction and the second direction, the second word lines being configured to intersect the bit lines so ...

Подробнее
20-06-2013 дата публикации

SEMICONDUCTOR STORAGE DEVICE

Номер: US20130155750A1
Автор: MAEJIMA Hiroshi
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A semiconductor storage device includes: a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a rectifier element and a variable resistance element connected in series; and a control circuit selectively driving the first and second wirings. The plurality of first wirings that are specified and selectively driven at the same time by one of a plurality of address signals are separately arranged with other first wirings interposed therebetween within the memory cell array when a certain potential difference is applied to a selected memory cell positioned at an intersection between the first and second wirings by the control circuit. 1. A semiconductor storage device comprising:a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a variable resistance element; anda control circuit selectively driving the first and second wirings,in applying, by the control circuit, a certain potential difference to a selected memory cell positioned at an intersection between the first and second wirings,the plurality of first wirings specified and selectively driven at the same time by one of a plurality of address signals being separately arranged with other first wirings interposed therebetween within the memory cell array,the first wirings being arranged such that a first set of the plurality of first wirings specified and selectively driven at the same time by a first address signal are positioned apart from a second set of the plurality of first wirings specified and selectively driven at the same time by the first address signal, with other first wirings interposed between the first and second set in the memory cell array, anda plurality of sets of the first wirings being repeatedly arranged in the memory cell array, each of ...

Подробнее
20-06-2013 дата публикации

MEMORY DEVICES HAVING BREAK CELLS

Номер: US20130155751A1

A representative memory device includes a cell array, at least one break cell that subdivides the cell array into bit cell arrays, and one or more power switches that are electrically coupled to the bit cell. In one embodiment, the break cell separates a connectivity of a first voltage and a second voltage between at least two bit cell arrays so that the bit cell arrays can be selectively coupled to either the first voltage or the second voltage using the power switches. The power switches control the connection of each separated bit cell array of the cell array to either the first voltage or second voltage. 1. A semiconductor memory , comprising:a first break cell electrically separating a first subset of bit cells from a second subset of bit cells of a cell array; anda first power switch configured to connect the first subset of bit cells to a first voltage during a first operating mode and to a second voltage that is different from the first voltage during a second operating mode.2. The semiconductor memory of claim 1 , wherein the first operational mode is a data retention mode claim 1 , and the second operational mode is a write mode.3. The semiconductor memory of claim 1 , further comprising a section decoder that is coupled to the first power switch claim 1 , wherein the section decoder instructs the first power switch to connect the first subset of bit cells to either the first voltage or to the second voltage.4. The semiconductor memory of claim 1 , further comprising a second power switch configured to connect the second subset of bit cells to the first voltage during the first operating mode and to the second voltage that is different from the second voltage during the second operating mode claim 1 , wherein the second power switch is configured to operate independently of the first power switch.5. The semiconductor memory of claim 4 , further comprising a section decoder that is coupled to the first and second power switches claim 4 , wherein the section ...

Подробнее
11-07-2013 дата публикации

Layout to minimize fet variation in small dimension photolithography

Номер: US20130175631A1
Принадлежит: International Business Machines Corp

A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.

Подробнее
11-07-2013 дата публикации

STACKED MEMORY WITH REDUNDANCY

Номер: US20130176763A1
Принадлежит: RAMBUS INC.

A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and stacked with a second integrated circuit memory chip. A redundant memory is shared by the first and second integrated circuit memory chips and has redundant storage locations that selectively replace corresponding storage locations in the first or second integrated circuit memory chips. The stacked memory also includes a pin interface for coupling to an external integrated circuit memory controller and respective first and second signal paths. The first signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface. The second signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface via the first signal path. 1. A stacked memory comprising:a first integrated circuit memory chip having first storage locations;a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip, the second integrated circuit memory chip having second storage locations;a redundant memory shared by the first and second integrated circuit memory chips, the redundant memory having redundant storage locations that selectively replace corresponding storage locations in the first or second integrated circuit memory chips;a pin interface for coupling to an external memory controller;a first signal path formed through the first and second integrated circuit memory chips and coupled to the redundant memory, the first signal path coupled to the pin interface; anda second signal path formed through the first and second integrated circuit memory chips and coupled to the redundant memory, the second signal path coupled to the pin interface via the first signal path.2. The stacked memory according to wherein the redundant memory comprises a redundant integrated ...

Подробнее
18-07-2013 дата публикации

Discrete Three-Dimensional Memory Comprising Off-Die Address/Data Translator

Номер: US20130182483A1
Автор: ZHANG Guobiao
Принадлежит:

The present invention discloses a discrete three-dimensional memory (3D-M). Its 3D-M arrays are located on at least one 3D-array die, while its address-data translator (A/D-translator) is located on a separate peripheral-circuit die. The A/D-translator converts at least an address and/or data between logical space and physical space for the 3D-array die. A single A/D-translator die can support multiple 3D-array dies. 1. A discrete three-dimensional memory (3D-M) , comprising:a first 3D-array die comprising at least a first 3D-M array including a plurality of vertically stacked memory levels;a first peripheral-circuit die comprising an address/data translator for converting at least an address and/or data between logical space and physical space for said first 3D-array die;a second peripheral-circuit die comprising a read/write-voltage generator for providing said first 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply;wherein said first 3D-array die, said first peripheral-circuit die and said second peripheral-circuit die are separate dies.2. The memory according to claim 1 , further comprising a second 3D-array die comprising at least a second 3D-M array including a plurality of vertically stacked memory levels claim 1 , wherein:said address/data translator converts at least an address and/or data between logical space and physical space for said second 3D-array die;said read/write-voltage generator provides said second 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply;said first 3D-array die, said second 3D-array die, said first peripheral-circuit die and said second peripheral-circuit die are separate dies.3. The memory according to claim 1 , wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).4. The memory according to claim 1 , wherein said 3D-M comprises a three-dimensional mask-programmed read- ...

Подробнее
01-08-2013 дата публикации

High current capable access device for three-dimensional solid-state memory

Номер: US20130194855A1
Автор: Luiz M. Franca-Neto
Принадлежит: Individual

The present invention generally relates to three-dimensional arrangement of memory cells and methods of addressing those cells. The memory cells can be arranged in a 3D orientation such that macro cells that are in the middle of the 3D arrangement can be addressed without the need for overhead wiring or by utilizing a minimal amount of overhead wiring. An individual macro cell within a memory cell can be addressed by applying three separate currents to the macro cell. A first current is applied to the memory cell directly. A second current is applied to the source electrode of the MESFET, and a third current is applied to the gate electrode of the MESFET to permit the current to travel through the channel of the MESFET to the drain electrode which is coupled to the memory element.

Подробнее
08-08-2013 дата публикации

Three-Dimensional Memory Comprising an Integrated Intermediate-Circuit Die

Номер: US20130201743A1
Автор: ZHANG Guobiao
Принадлежит:

The present invention discloses a discrete three-dimensional memory (3D-M). It comprises at least a 3D-array die and at least an integrated intermediate-circuit die comprising both a read/write-voltage generator (V/V-generator) and an address/data translator (A/D-translator). The intermediate-circuit die performs voltage, address and/or data conversion between the 3D-M core region and the host. Discrete 3D-M support multiple 3D-array dies. 1. A discrete three-dimensional memory (3D-M) , comprising:a 3D-array die comprising at least a 3D-M array including a plurality of vertically stacked memory levels;an intermediate-circuit die comprising a read/write-voltage generator and an address/data translator, wherein said read/write-voltage generator provides said 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply, and said address/data translator converts at least an address and/or data of a host to an address/data of said 3D-array die and vice versa;wherein said 3D-array die and said intermediate-circuit die are separate dies.2. The memory according to claim 1 , further comprising another 3D-array die comprising at least a 3D-M array including a plurality of vertically stacked memory levels claim 1 , wherein:said read/write-voltage generator provides said another 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply;said address/data translator converts at least an address and/or data of a host to an address/data of said second 3D-array die and vice versa;both of said 3D-array dies and said intermediate-circuit die are separate dies.3. The memory according to claim 1 , wherein said read/write-voltage generator comprises a DC-to-DC converter.4. The memory according to claim 1 , wherein said address/data translator is an address translator comprising at least one of an address mapping table claim 1 , a faulty block table and a wear management table.5. The memory according to claim 1 , ...

Подробнее
22-08-2013 дата публикации

LOAD REDUCED MEMORY MODULE AND MEMORY SYSTEM INCLUDING THE SAME

Номер: US20130215659A1
Принадлежит: ELPIDA MEMORY, INC.

A device includes a printed circuit board, a clock connector provided on the printed circuit board and configured to be supplied with a first clock signal, a first register buffer provided on the printed circuit board, coupled to the clock connector and, including a first clock generator that produces a second clock signal in response to the first clock signal, a plurality of data connectors, provided on the printed circuit board, a plurality of memory chips each provided on the printed circuit board and including a first data terminal, and a plurality of second register buffers each provided on the printed circuit board independently of the first register buffer. 1. A device comprising:a printed circuit board;a clock connector provided on the printed circuit board and configured to be supplied with a first clock signal;a first register buffer provided on the printed circuit board, coupled to the clock connector and including a first clock generator that produces a second clock signal in response to the first clock signal;a plurality of data connectors provided on the printed circuit board;a plurality of memory chips each provided on the printed circuit board and including a first data terminal; anda plurality of second register buffers each provided on the printed circuit board independently of the first register buffer; a clock terminal configured to receive the second crock signal;', 'a second date terminal coupled to the first data terminal of an associated one of the memory chips;', 'a third data terminal coupled to an associated one of the data connectors;', 'a second clock generator configured to produce a third clock signal in response to the second clock signal; and', 'a data transfer circuit coupled between the second and third data terminals and configured to perform a data transfer therebetween in response to the third clock signal., 'wherein each of the second register buffers comprises2. The device as claimed in claim 1 , wherein the first clock ...

Подробнее
05-09-2013 дата публикации

Memories with Cylindrical Read/Write Stacks

Номер: US20130229846A1
Принадлежит: SanDisk 3D LLC

A three-dimensional memory is formed as an array of memory elements across multiple layers positioned at different distances above a semiconductor substrate. Cylindrical stacks of memory elements are formed where a cylindrical opening has read/write material deposited along its wall, and a cylindrical vertical bit line formed along its central axis. Memory elements formed on either side of such a cylinder may include sheet electrodes that extend into the read/write material. 1. A three-dimensional array of read/write elements comprising:a plurality of horizontal line stacks, each horizontal line stack comprising a plurality of electrically-conductive horizontal lines that extend in a first direction and are separated from each other by insulating material, individual stacks separated from adjacent stacks in a second direction that is perpendicular to the first direction;a plurality of cylinders of read/write material located between a first horizontal line stack and a second horizontal line stack so that each cylinder of the plurality of cylinders is in electrical contact with horizontal lines of the first and second horizontal line stacks; anda plurality of vertical lines, each vertical line extending through a corresponding cylinder of read/write material to form read/write elements between the vertical line and horizontal lines of the first and second horizontal line stacks.2. The three-dimensional array of wherein the electrically-conductive horizontal lines of the first and second horizontal line stacks include sheet electrodes that extend towards the vertical lines claim 1 , a sheet electrode having a vertical thickness that is less than the total vertical thickness of a horizontal line.3. The three-dimensional array of wherein the sheet electrode extends into a cylinder of read/write material.4. The three-dimensional array of claim three wherein the sheet electrode is formed of Titanium Nitride (TiN).5. The three-dimensional array of wherein the electrically- ...

Подробнее
05-09-2013 дата публикации

MEMORY DIES, STACKED MEMORIES, MEMORY DEVICES AND METHODS

Номер: US20130229847A1
Принадлежит: MICRON TECHNOLOGY, INC.

Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node. 1. A memory die configured to be arranged in a stack of memory dies , wherein the stack comprises an external select connection node , the memory die comprising:a plurality of detection circuits, each detection circuit being configured to determine if it is coupled to the external select connection node; anda decoder configured to receive detection signals from at least a portion of the plurality of detection circuits and to output an identification of the memory die responsive to which, if any, of the detection circuits is coupled to the external select connection node using the received ones of the detection signals.2. The memory die of claim 1 , further comprising an input buffer configured to receive a signal from the external select connection node.3. The memory die of claim 2 , further comprising a delay circuit claim 2 , wherein the delay circuit is configured to delay a signal received from the external select connection node responsive to the identification.4. The memory die of claim 1 , wherein the memory die is configured to be coupled to another memory die in the stack via four select related connection nodes claim 1 , wherein the plurality of detection circuits comprise at least three detection circuits claim 1 , wherein each of the at least three detection circuits is configured to be coupled to a respective one of the select related connection nodes when the die is arranged in the stack.5. A method comprising:determining an identification ...

Подробнее
12-09-2013 дата публикации

MAGNETIC RANDOM ACCESS MEMORY (MRAM)LAYOUT WITH UNIFORM PATTERN

Номер: US20130235639A1
Принадлежит: QUALCOMM INCORPORATED

A large scale memory array includes a. uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects. 1. A memory array , comprising:a pattern of adjacent uniformly sized bit cells; andsignal distribution circuitry occupying an area having a size coinciding with an integer multiple of a size of the uniformly sized bit cells.2. The memory array of claim I. in which the adjacent uniformly sized bit cells comprise a plurality of active bit cells outside of a footprint of the signal distribution circuitry area.3. The memory array of claim 2 , comprising:a resistive memory element configured in each of the active bit cells.4. The memory array of claim 2 , comprising:a magnetic tunnel junction configured in each of the active bit cells.5. The memory array of claim 2 , in which the adjacent uniformly sized bit cells comprise a plurality of dummy bit cells within the footprint of the signal distribution circuitry area.6. The memory array of claim 2 , in which the signal distribution circuitry is coupled to the active bit cells.7. The memory array of claim 1 , in which the signal distribution circuitry comprises:word line strapping extending in a first dimension of the pattern.8. The memory array of claim 1 , in which the signal distribution circuitry comprises:at least one substrate tie extending in a second dimension of the pattern.9. The memory array of claim 1 , further comprising a plurality of edge dummy cells extending ...

Подробнее
03-10-2013 дата публикации

SEMICONDUCTOR DEVICE HAVING MULTIPORT MEMORY

Номер: US20130258741A1
Принадлежит: RENESAS ELECTRONICS CORPORATION

A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA, WLB, WLB, WLA, WLA. Further, a pitch d between WLA-WLA and between WLB-WLB is made smaller than a pitch d between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d on the other. 1a plurality of word line groups respectively including a first word line for a first port and a second word line for a second port and the first word line and the second word line being disposed in juxtaposition with one another;a plurality of bit line groups respectively extending in a direction orthogonal to an extension direction of the word line groups and including a first bit line for the first port and a second bit line for the second port and the first word line and the second word line being disposed in juxtaposition with one another; anda plurality of memory cells disposed at respective intersections between the word line groups and the bit line groups,wherein the first word line and the second word line included in one of the word line groups are disposed at a first pitch;wherein the first word line included in one of the word line groups is disposed adjacent to the first word line included in a word line group disposed on one neighboring side of the one word line group concerned at a second pitch;wherein the second word line included in one of the word line groups is disposed adjacent to the second word line included in a word line group disposed on the other neighboring side of the one word line group concerned at the second pitch; andwherein a first shield line extending in juxtaposition with the first word line and the ...

Подробнее
03-10-2013 дата публикации

SEMICONDUCTOR DEVICE HAVING MEMORY CELL ARRAY DIVIDED INTO PLURAL MEMORY MATS

Номер: US20130258742A1
Принадлежит:

A semiconductor device includes a plurality of memory mats arranged in an X direction and a mat selecting circuit that activates a part of the memory mats based on a row address and maintains the rest of the memory mats inactivated. The memory mats are divided into a plurality of memory mat groups each including the same number of memory mats arranged in the X direction. The mat selecting circuit activates at least one of the memory mats included in each of the memory mat groups, while maintaining the rest of memory mats inactivated. With this operation, a portion of discontinuity does not occur in the memory mats arranged in the X direction, and thus the necessity of arranging two sub-word driver areas in the portion of discontinuity is eliminated. 1. A semiconductor device comprising:first, second, third, fourth, fifth, sixth, seventh and eighth memory mats that are arranged in line in that order, each of the first to eighth memory mats including a plurality of memory cells; anda selection circuit that is configured to respond to a first bit of a row address including a plurality of bits and to activate the first, second, fifth and sixth memory mats in parallel to one another with deactivating the third, fourth, seventh and eighth memory mats when the first bit of the row address is one of logic-1 and logic-0 and to activate the third, fourth, seventh and eighth memory mats in parallel to one another with deactivating the first, second, fifth and sixth memory mats when the first bit of the row address is the other of logic-1 and logic-0.2. The device as claimed in claim 1 ,wherein each of the first to eighth memory mats further includes a plurality of word lines; andwherein the device further comprises first, second, third and fourth word drivers, the first word driver being between the first and second memory mats to be connected to the word lines of each of the first and second memory mats, the second word driver being between the third and fourth memory mats to ...

Подробнее
31-10-2013 дата публикации

Memory Modules and Devices Supporting Configurable Data Widths

Номер: US20130286706A1
Принадлежит:

Described are memory apparatus organized in physical banks and including configurable data control circuit to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey configuration value to configurable memory apparatus and support point-to-point data buffers for multiple width configurations. 1. (canceled)2. An integrated-circuit memory device comprising:an input to receive memory-width configuration value;data terminals to exchange data with another device;a plurality of physical banks, each physical bank including columns of memory cells coupled to corresponding sense amplifiers; anda data control circuit coupling the physical banks with the data terminals, the data control circuit supporting first and second width configurations responsive to the configuration value; in the first width configuration, the data control circuit conveys data of a first data width between a first integer number of the physical banks per read operation and the data terminals, and the plurality of physical banks collectively provide a first memory depth, and', 'in the second width configuration, the data control circuit conveys data of a second data width between a second integer number of the physical banks per read operation and the data terminals, the second data width wider than the first data width, the second integer number larger than the first integer number, and the plurality of physical banks collectively provide a second memory depth; and', 'wherein the memory device loads a first page of sense amplifiers in the first number of the physical banks for activate operation in the first width configuration and loads a second page of sense amplifiers in the second number of physical banks for activate operations in the second width configuration, the first page smaller than the second page., 'wherein3 ...

Подробнее
07-11-2013 дата публикации

Memory Arrays

Номер: US20130294132A1
Автор: Zengtao T. Liu
Принадлежит: Micron Technology Inc

Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F 2 .

Подробнее
28-11-2013 дата публикации

MEMORY HAVING BURIED DIGIT LINES AND METHODS OF MAKING THE SAME

Номер: US20130314967A1
Принадлежит: MICRON TECHNOLOGY, INC.

A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4Farchitecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device. 1. A memory cell comprising:a storage device;a vertical access device electrically coupled to the storage device;a word line electrically coupled to the vertical access device; anda buried digit line electrically coupled to the vertical access device and disposed below the storage device, the word line, and the vertical access device.2. The memory cell of claim 1 , wherein the word line and the buried digit line are orthogonal to each other.3. The memory cell of claim 1 , wherein the storage device is disposed above the vertical access device.4. The memory cell of claim 1 , wherein the storage device is disposed above the word line.5. The memory cell of claim 1 , wherein the storage device comprises a capacitor.6. The memory cell of claim 1 , wherein the vertical access device comprises a finFET.7. The memory cell of claim 6 , wherein the finFET comprises a fin claim 6 , and the vertical height of the word line is greater than two times the thickness of the fin.8. The memory cell of claim 1 , wherein the memory cell comprises at least two vertical access devices claim 1 , each of which is disposed above the buried digit line.9. The memory cell of claim 8 , wherein the memory cell comprises at least two word lines electrically coupled to the vertical access devices.10. A memory array comprising:a memory cell having two vertical access devices electrically coupled to and disposed below a storage device;a word line ...

Подробнее
28-11-2013 дата публикации

OFFSETTING CLOCK PACKAGE PINS IN A CLAMSHELL TOPOLOGY TO IMPROVE SIGNAL INTEGRITY

Номер: US20130314968A1
Принадлежит:

The disclosed embodiments relate to the design of a memory system which includes a set of one or more memory modules, wherein each memory module in the set has a clamshell configuration, wherein pairs of opposing memory packages containing memory chips are located on opposite sides of the memory module. The memory system also includes a multi-drop path containing signal lines which pass through the set of memory modules, and are coupled to memory packages in the set of memory modules. For a given signal line in the multi-drop path, a first memory package and a second memory package that comprise a given pair of opposing memory packages are coupled to the given signal line at a first location and a second location, respectively, wherein the first location and the second location are separated from each other by a distance d along the given signal line. 1. A memory system , comprising:a circuit board having one or more pairs of opposing memory chips which are located on opposite sides of the circuit board in a clamshell configuration; anda multi-drop path for at least one signal line coupled to each memory chip;{'sub': '1', 'wherein a first memory chip and a second memory chip are coupled to the at least one signal line at a first location and a second location on the signal line, respectively, wherein the first location and the second location are separated from each other by a distance dalong the signal line.'}2. The memory system of claim 1 , wherein the distance dis substantially half of a spacing dbetween successive pairs of opposing memory chips along the given signal line claim 1 , whereby coupling locations and associated loads for individual memory chips are distributed along the signal line.3. (canceled)4. The memory system of claim 1 ,wherein the first and second memory chips are contained within a first and a second memory package, respectively; andwherein for another signal line in the multi-drop path, the first and second memory chips in each pair of ...

Подробнее
28-11-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130314991A1
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate. 119-. (canceled)20. A semiconductor device comprising:a substrate portion comprising a first layer portion with a first wiring pattern, a second layer portion with a second wiring pattern, and a third layer portion with a third wiring pattern, and the substrate portion comprising a substantially rectangular shape in a plan view;a connector to be connectable to a host device;a first nonvolatile semiconductor memory element provided on a surface of the first layer portion of the substrate portion;a second nonvolatile semiconductor memory element provided on the surface of the first layer portion of the substrate portion;a third nonvolatile semiconductor memory element provided on the surface of the first layer portion of the substrate portion;a controller provided on the substrate portion and electrically connected to the first nonvolatile semiconductor memory element, the second nonvolatile semiconductor memory element, and the third nonvolatile semiconductor memory element; anda signal line provided on a surface of the second layer portion of the substrate portion and formed between the connector and the controller to electrically connect the connector to the controller,wherein the first nonvolatile semiconductor memory element and the second nonvolatile semiconductor memory element are aligned along the longitudinal direction of the substrate portion.21. The semiconductor device according to claim 20 , further comprising:resistive elements provided on ...

Подробнее
05-12-2013 дата публикации

CONFIGURABLE MODULE AND MEMORY SUBSYSTEM

Номер: US20130322173A1
Принадлежит: MOSAID TECHNOLOGIES INCORPORATED

A configurable memory subsystem includes a memory module with a circuit board having a first and a second memory-containing device (MCD) pair mounted thereto. Each MCD pair has a first MCD in communication with a second MCD. Each MCD has an input port, an output port, and a memory each communicating with a bridge. In response to a command, the bridge transfers at least one of a portion of a data packet from the input port to the output port or to the memory, or transfers a portion of a memory packet from the memory to the output port. A loop-back device receives the command and the data packet form the first MCD pair and transmits the command and data packet to the second MCD pair. 1. A memory module comprising:a plurality of devices each including an input port, an output port, a semiconductor chip and a non-volatile memory contained in the semiconductor chip or in a separate memory chip, and the semiconductor chip being configured to receive a command and a data packet on the input port and being further configured to execute, in response to the command: a transfer of a portion of the data packet from the input port to the non-volatile memory; a transfer of a portion of the data packet from the input port to the output port; or a transfer of a portion of a memory packet from the non-volatile memory to the output port; anda circuit board including the plurality of devices mounted thereto and having a plurality of conducting paths for serial communication between a first device of the plurality of devices and a second device of the plurality of devices, the first device being on a first side of the circuit board and the second device being on a second side of the circuit board.2. The memory module of wherein the semiconductor chip is a bridge.3. The memory module of wherein each of the plurality of devices is a stacked multi-chip device with the non-volatile memory contained in the separate memory chip.4. The memory module of wherein each of the plurality of devices ...

Подробнее
12-12-2013 дата публикации

Arrays Of Nonvolatile Memory Cells And Methods Of Forming Arrays Of Nonvolatile Memory Cells

Номер: US20130329479A1
Автор: Liu Jun
Принадлежит: MICRON TECHNOLOGY, INC.

An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first plurality of horizontally oriented first electrode lines and a second plurality of horizontally oriented second electrode lines crossing relative to the first electrode lines. Individual of the memory cells include a crossing one of the first electrode lines and one of the second electrode lines and material there-between. Specifically, programmable material, a select device in series with the programmable material, and current conductive material in series between and with the programmable material and the select device are provided in series with such crossing ones of the first and second electrode lines. The material and devices may be oriented for predominant current flow in defined horizontal and vertical directions. Method and other implementations and aspects are disclosed. 122-. (canceled)23. An array of nonvolatile memory cells , comprising: a first plurality of horizontally oriented first electrode lines;', 'a second plurality of horizontally oriented second electrode lines crossing relative to the first electrode lines; and', a crossing one of the first electrode lines and one of the second electrode lines;', 'programmable material, a select device in series with the programmable material, and current conductive material in series between and with the programmable material and the select device; the programmable material and the select device being in series with such crossing ones of the first and second electrode lines; and', 'the programmable material and the select device are oriented for predominant current flow into or out of the crossing one first electrode line out of or into, respectively, one of the programmable material or select device in a first direction, and for predominant current flow into or out of the crossing one second electrode line out of or into, respectively, the other of the ...

Подробнее
19-12-2013 дата публикации

NON-VOLATILE MEMORY HAVING 3D ARRAY ARCHITECTURE WITH BIT LINE VOLTAGE CONTROL AND METHODS THEREOF

Номер: US20130336036A1
Автор: Cernea Raul Adrian
Принадлежит: SanDisk 3D LLC

In a 3D memory with vertical local bit lines, each local bit line is switchably connected to a node on a global bit line having first and second ends, the local bit line voltage is maintained at a predetermined reference level in spite of being driven by a bit line driver from a first end of the global bit line that constitutes variable circuit path length and circuit serial resistance. This is accomplished by a feedback voltage regulator comprising a voltage clamp at the first end of the global bit line controlled by a bit line voltage comparator at the second end of the global bit line. The comparator compares the bit line voltage sensed from the second end with the predetermined reference level and outputs a control voltage to control the voltage clamp In this way the voltage at the local bit line is regulated at the reference voltage. 1. A non-volatile memory , comprising:a local bit line;a global bit line of finite resistance having first and second ends;a switch for switchably connecting said local bit line to a node on said global bit line;a voltage supply for supply a first voltage to the first end of said global bit line; so that a local bit line voltage appears at the node connecting to said local bit line;a bit line voltage control circuit having a voltage clamp and a comparator;the comparator responsive to a comparison between a predetermined reference voltage and a second voltage sensed from the second end to output a control voltage; andthe voltage clamp, responsive to the control voltage, controls the first voltage at the first end such that the local bit line is maintained at the predetermined reference voltage irrespective of the resistance in said global bit line.2. The non-volatile memory as in claim 1 , further comprising:a sense amplifier for providing said voltage supply.3. The non-volatile memory as in claim 1 , wherein:said voltage clamp is a transistor connected in series between said voltage sum ly and the first end; andthe transistor has a ...

Подробнее
19-12-2013 дата публикации

NON-VOLATILE MEMORY HAVING 3D ARRAY ARCHITECTURE WITH STAIRCASE WORD LINES AND VERTICAL BIT LINES AND METHODS THEREOF

Номер: US20130336038A1
Принадлежит: SanDisk 3D LLC

In a 3D nonvolatile memory with memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes from a bottom plane to a top plane stacked in the z-direction over a semiconductor substrate; a plurality of local bit lines elongated in the z-direction through the plurality of layers and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; the 3D nonvolatile memory further having a plurality of staircase word lines spaced apart in the y-direction and between and separated from the plurality of bit line pillars at a plurality of crossings, individual staircase word lines each having a series of alternating steps and risers elongated respectively in the x-direction and z-direction traversing across the plurality of planes in the z-direction with a segment in each plane. 1. A non-volatile memory , comprising:memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes from a bottom plane to a top plane stacked in the z-direction over a semiconductor substrate;a plurality of local bit lines elongated in the z-direction through the plurality of parallel planes and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction;a plurality of staircase word lines spaced apart in the y-direction and between and separated from the plurality of bit line pillars at a plurality of crossings, individual staircase word lines each having a series of alternating steps and risers elongated respectively in the x-direction and z-direction traversing across the plurality of planes in the z-direction with a segment in each plane; anda plurality of non-volatile re-programmable memory elements individually connected through circuits between the bit line ...

Подробнее
19-12-2013 дата публикации

MEMORY BANDWIDTH AGGREGATION USING SIMULTANEOUS ACCESS OF STACKED SEMICONDUCTOR MEMORY DIE

Номер: US20130336039A1
Автор: Frans Yohan
Принадлежит: RAMBUS INC.

A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin. 1. A packaged semiconductor memory device , comprising:a data pin; a first data interface coupled to the data pin, and', 'a first memory core having a plurality of banks; and, 'a first memory die comprisinga second memory die stacked with the first memory die and comprising a second memory core having a plurality of banks; wherein:a respective bank of the first memory core and a respective bank of the second memory core are to perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal; andthe first data interface is to provide aggregated data from the parallel column access operations to the data pin.2. The packaged semiconductor memory device of claim 1 , wherein:the respective bank of the first memory core and the respective bank of the second memory core are to perform a series of parallel column access operations in response to a series of column access commands; andthe first data interface is to provide aggregated data from the series of parallel column access operations to the data pin.3. The packaged semiconductor memory device of claim 1 , wherein:the first memory die further comprises a first data path, coupled between the first ...

Подробнее
19-12-2013 дата публикации

3d memory with vertical bit lines and staircase word lines and vertical switches and methods thereof

Номер: US20130339571A1
Принадлежит: SanDisk 3D LLC

A 3D memory with vertical local bit lines global bit lines has an in-line vertical switch in the form of a thin film transistor (TFT) formed as a vertical structure, to switch a local bit line to a global bit line. The TFT is implemented to switch a maximum of current carried by the local bit line by a strongly coupled select gate which must be fitted within the space around the local bit line. Maximum thickness of the select gate is implemented with the select gate exclusively occupying the space along the x-direction from both sides of the local bit line. The switches for odd and even bit lines of the row are staggered and offset in the z-direction so that the select gates of even and odd local bit lines are not coincident along the x-direction. The switching is further enhanced with a wrap-around select gate.

Подробнее
16-01-2014 дата публикации

SEMICONDUCTOR DEVICE, ADJUSTMENT METHOD THEREOF AND DATA PROCESSING SYSTEM

Номер: US20140016388A1
Принадлежит: ELPIDA MEMORY, INC.

A system includes a first device, a second device, and a bus interconnecting the first and second devices to each other, wherein the first device includes a first semiconductor chip that includes a first memory cell array including a plurality of first memory cells, a first control logic circuit accessing the first memory cell array and producing a first data signal in response to data stored in a selected one of the first memory cells, the first control logic circuit being configured to store first timing adjustment information and to produce a first output timing signal that is adjustable in timing of change from an inactive level to an active level by the first timing adjustment information, a first data electrode, and a first data control circuit coupled to the first control logic circuit and the first data electrode. 1. A system comprising:a first device;a second device; anda bus interconnecting the first and second devices to each other; [ a first memory cell array including a plurality of first memory cells,', 'a first control logic circuit accessing the first memory cell array and producing a first data signal in response to data stored in a selected one of the first memory cells, the first control logic circuit being configured to store first timing adjustment information and to produce a first output timing signal that is adjustable in timing of change from an inactive level to an active level by the first timing adjustment information,', 'a first data electrode, and', 'a first data control circuit coupled to the first control logic circuit and the first data electrode, the first data control circuit receiving the first data signal and responding to change from the inactive level to the active level of the first output timing signal to initiate driving the first data electrode to a logic level related to the first data signal;, 'a first semiconductor chip that comprises,'}, a second memory cell array including a plurality of second memory cells,', 'a ...

Подробнее
30-01-2014 дата публикации

Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules

Номер: US20140029325A1
Принадлежит: Micron Technology Inc

A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector.

Подробнее
06-02-2014 дата публикации

NON-VOLATILE MEMORY DEVICE WITH CLUSTERED MEMORY CELLS

Номер: US20140036564A1
Принадлежит:

An embodiment of a non-volatile memory device includes: a memory array, having a plurality of non-volatile logic memory cells arranged in at least one logic row, the logic row including a first row and a second row sharing a common control line; and a plurality of bit lines. Each logic memory cell has a direct memory cell, for storing a logic value, and a complementary memory cell, for storing a second logic value, which is complementary to the first logic value in the corresponding direct memory cell. The direct memory cell and the complementary memory cell of each logic memory cell are coupled to respective separate bit lines and are placed one in the first row and the other in the second row of the respective logic row. 111-. (canceled)12. An integrated circuit , comprising:first and second rows;first and second data lines;a portion of a memory cell disposed in one of the first and second rows and coupled to one of the first and second data lines; anda complementary portion of the memory cell disposed in the other of the first and second rows and coupled to the other of the first and second data lines.13. The integrated circuit of wherein the first and second data lines include first and second bit lines.14. The integrated circuit of wherein the memory cell includes a non-volatile memory cell.15. The integrated circuit of wherein the memory cell includes a differential memory cell.16. The integrated circuit of claim 12 , further comprising a select line coupled to the portion and the complementary portion of the memory cell.17. The integrated circuit of claim 12 , further comprising:a cluster of more than two memory cells each having a respective portion coupled to one of the first and second data lines and having a respective complementary portion coupled to the other of the first and second data lines; andwherein the memory cell is disposed in the cluster.18. The integrated circuit of claim 12 , further comprising:a cluster of more than two memory cells each ...

Подробнее
06-02-2014 дата публикации

Memory module with distributed data buffers and method of operation

Номер: US20140040568A1
Автор: Hyun Lee, Jayesh R. Bhakta
Принадлежит: Netlist Inc

A memory module is operable to communicate with a memory controller via a data bus and a control/address bus and comprises a module board; a plurality of memory devices mounted on the module board; and multiple sets of data pins along an edge of the module board. Each respective set of the multiple sets of data pins is operatively coupled to a respective set of multiple sets of data lines in the data bus. The memory module further comprises a control circuit configured to receive control/address information from the memory controller via the control/address bus and to produce module control signals. The memory module further comprises a plurality of buffer circuits each being disposed proximate to and electrically coupled to a respective set of the multiple sets of data pins. Each buffer circuit is configured to respond to the module control signals by enabling data communication between the memory controller and at least one first memory device among the plurality of memory devices and by isolating at least one second memory device among the plurality of memory devices from the memory controller.

Подробнее
13-02-2014 дата публикации

Three dimensional structure memory

Номер: US20140043883A1
Автор: Leedy Glenn J.
Принадлежит:

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. 1. A stacked memory integrated circuit comprising:a plurality of circuit layers comprising at least one control circuit layer and at least one memory circuit layer arranged in a stacked relationship;wherein the control and memory circuit layers of the stacked memory integrated circuit are partitioned into a plurality of vertically interconnected circuit blocks and configured for a plurality of said vertically interconnected circuit blocks to independently perform memory operations.2. The stacked memory integrated circuit of claim 1 , wherein each of the plurality of vertically interconnected circuit blocks comprises a memory array and an array of vertical interconnects interconnecting the vertically interconnected circuit block with the at least one control circuit layer.3. The stacked memory integrated circuit of claim 1 , wherein the control circuit layer is configured to perform functional testing of at least part of the stacked memory integrated circuit.4. The stacked memory integrated circuit of claim 1 , wherein the control circuit layer is configured to perform reconfiguration of at least part of the stacked memory integrated circuit.5. A stacked memory integrated circuit comprising:a plurality of circuit layers comprising at least one control circuit layer and at least ...

Подробнее
27-02-2014 дата публикации

Nonvolatile semiconductor memory device

Номер: US20140056048A1
Автор: Masayuki Ichige
Принадлежит: Toshiba Corp

This nonvolatile semiconductor memory device comprises a memory cell array configured having a plurality of memory mats arranged therein, each of the memory mats having a memory cell disposed therein at an intersection of a first line and a second line, the memory cell including a first variable resistance element. A third line extends through a plurality of the memory mats. A second variable resistance element is connected between the third line and the second line of each of the plurality of memory mats.

Подробнее
06-03-2014 дата публикации

STACKED DRAM DEVICE AND METHOD OF MANUFACTURE

Номер: US20140063887A1
Автор: Vogelsang Thomas
Принадлежит: RAMBUS INC.

A memory stack includes a number of memory dies including a master die and one or more slave dies. The slave die can be converted to a master die by further processing. The slave die includes a memory core having memory cell arrays. The slave die also includes first and second metal layers that form first and second distribution lines in the memory core, respectively. An interface circuit in the slave die is decoupled from the first and second metal layers. 1. A memory die for use in a memory device comprising:a memory core having memory cell arrays interconnected by first and second distribution lines;a first metal layer including the first distribution linesa second metal layer including the second distribution lines; andan interface circuit that is not coupled to the first or second distribution lines via any conductors on the memory die.2. The memory die according to wherein the memory die comprises a slave memory die configured to communicate with a memory controller via a master memory die claim 1 , and wherein the memory die is incapable of communicating command or data with the memory controller without the master memory die.3. The memory die according to wherein the slave memory die comprises at least one through-silicon-via (TSV) formed to couple the memory core of the slave memory die to an interface circuit of the master memory die.4. (canceled)5. The memory die according to wherein the slave memory die receives power via the at least one TSV.6. (canceled)7. The memory die according to wherein the memory die comprises a slave memory die configured to communicate with a memory controller via a buffer die claim 1 , and wherein the memory die is incapable of communicating command or data with the memory controller without the buffer die.813-. (canceled)14. The memory die according to wherein the memory die is of a predetermined width claim 1 , and is formed with a number of through-silicon-vias claim 1 , wherein the number of through-silicon-vias is based ...

Подробнее
13-03-2014 дата публикации

STACKED SEMICONDUCTOR DEVICES INCLUDING A MASTER DEVICE

Номер: US20140071729A1
Автор: KIM Jin-Ki
Принадлежит: MOSAID TECHNOLOGIES INCORPORATED

A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s). 1. (canceled)2. A system , comprising: a first memory chip comprising circuitry for generating one or more of voltage signals and control signals; and', 'a second memory chip lacking circuitry for generating one or more of voltage signals and control signals; and, 'a stack includinga plurality of Through-Silicon Vias extending between the first memory chip and the second memory chip, the Through-Silicon Vias connecting one or more of the voltage signals and the control signals generated by the first memory chip from the first memory chip to the second memory chip.3. The system of claim 1 , wherein the first and second memory chips are non-volatile memory chips.4. The system as claimed in wherein the first memory chip is a master device and the second memory chip is a slave device.5. The system of claim 2 , wherein only the first non-volatile memory chip includes a high voltage generator.6. The system of claim 1 , wherein:the first memory chip comprises circuitry for generating voltage signals; andthe generated voltage signals comprise high voltage signals for program and erase operations.7. The system of claim 1 , further comprising a third memory chip lacking circuitry for generating one or more of voltage signals and control signals claim 1 , wherein one or more of the voltage signals and the control signals generated by the first memory chip are communicated from the first memory chip to the third memory chip.8. The system of claim 1 , further comprising a package printed circuit board claim 1 , the stack connected to the package printed circuit board by flip chip and bumping.9. The system of claim 7 , wherein:the first memory device is larger dimensioned than the second memory device; andthe first memory device is positioned adjacent the package printed circuit ...

Подробнее
13-03-2014 дата публикации

Buffer die in stacks of memory dies and methods

Номер: US20140071771A1
Автор: Timothy M. Hollis
Принадлежит: Micron Technology Inc

Memory devices and methods of making and operating them are shown. Memory devices shown include stacked memory dies with one or more buffer dies included. In one such memory device, a command die communicates with one or more downstream memory dies through the one or more buffer dies. The one or more buffer dies function to repeat signals, and can potentially improve performance for higher numbers of memory dies in the stack.

Подробнее
20-03-2014 дата публикации

Apparatuses and methods including memory array and data line architecture

Номер: US20140078827A1
Автор: Toru Tanzawa
Принадлежит: Micron Technology Inc

Some embodiments include apparatus and methods having memory cells located in different device levels of a device, at least a portion of a transistor located in a substrate of the device, and a data line coupled to the transistor and the memory cells. The data line can be located between the transistor and the memory cells. Other embodiments including additional apparatus and methods are described.

Подробнее
20-03-2014 дата публикации

Continuous mesh three dimensional non-volatile storage with vertical select devices

Номер: US20140080272A1
Автор: Roy E. Scheuerlein
Принадлежит: SanDisk 3D LLC

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Подробнее
01-01-2015 дата публикации

CLOCK ADJUSTING CIRCUIT, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT UNIT

Номер: US20150003139A1
Автор: Chen Wei-Yung, Lin Yan-An
Принадлежит: PHISON ELECTRONICS CORP.

A memory storage device, a memory control circuit unit, and a clock adjusting circuit disposed on a plurality of layers are provided. The clock adjusting circuit includes a detection circuit, a control voltage generating circuit, and a voltage-controlled oscillator (VCO). The detection circuit detects a signal characteristic difference between an input signal and an output signal to generate a first signal. The control voltage generating circuit is coupled to the detection circuit and generates a control voltage according to the first signal. The VCO is coupled to the control voltage generating circuit and includes an inductor and a capacitor. The VCO receives the control voltage and starts oscillating according to an impedance characteristic of the inductor and the capacitor to generate the output signal. The inductor is disposed on a pad layer among the layers. Thereby, the manufacturing cost is reduced. 1. A clock adjusting circuit , disposed on a die , wherein the die has a plurality of layers , the clock adjusting circuit comprising:a detection circuit, configured to detect a signal characteristic difference between an input signal and an output signal to generate a first signal;a control voltage generating circuit, coupled to the detection circuit, and configured to generate a control voltage according to the first signal; anda voltage-controlled oscillator (VCO), coupled to the control voltage generating circuit, and comprising a inductor and a capacitor, wherein the VCO is configured to receive the control voltage and oscillate according to an impedance characteristic of the inductor and the capacitor to generate the output signal,wherein the inductor is disposed on a pad layer among the layers.2. The clock adjusting circuit according to further comprising:a filter, coupled between the control voltage generating circuit and the VCO, wherein the filter comprises a filter capacitor, the filter capacitor is disposed on a first layer among the layers, the first ...

Подробнее
01-01-2015 дата публикации

SEMICONDUCTOR DEVICE HAVING MULTIPORT MEMORY

Номер: US20150003140A1
Принадлежит:

A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA, WLB, WLB, WLA, WLA. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other. 1first and second static memory cells, first, second, third and fourth word lines, and first and second pairs of bit lines,wherein each of the first and second static memory cells includes a latch circuit having a first inverter and a second inverter, a first access transistor and a second access transistor coupled to the first latch circuit, and a third access transistor and a fourth access transistor coupled to the second latch circuit,wherein the first inverter has a first driver transistor and a first load transistor, and the second inverter has a second driver transistor and a second load transistor,wherein the first word line is electrically coupled to the first and third access transistors of the first static memory cell, the second word line is electrically coupled to the second and fourth access transistors of the first static memory cell, the third word line is electrically coupled to the second and fourth access transistors of the second static memory cell, and the fourth word line is electrically coupled to the first and third access transistors of the second static memory cell,wherein one of the first pair of bit lines is electrically coupled to the first access transistor of each of the first and second static memory cells, the other of the first pair of bit lines is electrically coupled to the third access transistor ...

Подробнее
13-01-2022 дата публикации

METHODS AND APPARATUS FOR MANAGING THERMAL BEHAVIOR IN MULTICHIP PACKAGES

Номер: US20220013505A1
Принадлежит:

An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors. 1. An integrated circuit , comprising:an interface circuit to communicate with an external die stack having a plurality of vertically stacked dies; andcontrol circuitry to receive one or more parameters of the associated with the external die stack and to distribute accesses among the plurality of vertically stacked dies based at least upon the one or more parameters.2. The integrated circuit of claim 1 , wherein the one or more parameters comprise a memory bandwidth utilization metric.3. The integrated circuit of claim 1 , wherein the one or more parameters comprise a memory bank status claim 1 , a number of commands claim 1 , at least one threshold value claim 1 , a number of page openings and closures claim 1 , or any combination thereof.4. The integrated circuit of claim 1 , wherein the one or more parameters comprise a memory error threshold value.5. The integrated circuit of claim 1 , wherein the one or more parameters comprise a frequently accessed region pattern of a given die in the external die stack.6. The integrated circuit of claim 1 , wherein the one or more parameters comprise temperature data associated with more than one of the vertically stacked dies in the external die stack.7. The integrated circuit of claim 6 , wherein the temperature data includes a first temperature sensor measurement from a topmost die in the ...

Подробнее
07-01-2021 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20210005623A1
Автор: KIM Jae Taek
Принадлежит: SK HYNIX INC.

A semiconductor memory device according to the present technology includes a stack body including a lower conductive pattern and an upper conductive pattern stacked apart from each other in a first direction, and at least one intermediate conductive pattern disposed between the lower conductive pattern and the upper conductive pattern, a contact plug connected to the lower conductive pattern and extending in the first direction, and at least one lower dummy plug overlapping the lower conductive pattern. 1. A semiconductor memory device comprising:a stack body including a lower conductive pattern and an upper conductive pattern stacked apart from each other in a first direction, and at least one intermediate conductive pattern disposed between the lower conductive pattern and the upper conductive pattern;a first contact plug connected to the lower conductive pattern and extending in the first direction; andat least one lower dummy plug overlapping the lower conductive pattern and extending in the first direction.2. The semiconductor memory device of claim 1 , wherein the at least one lower dummy plug is formed to be narrower than the first contact plug in a plane orthogonal to the first direction.3. The semiconductor memory device of claim 1 , wherein the at least one lower dummy plug is formed to be shorter than the first contact plug in the first direction.4. The semiconductor memory device of claim 1 , wherein the lower dummy plug is spaced apart from the lower conductive pattern in the first direction.5. The semiconductor memory device of claim 1 , further comprising:a second contact plug connected to the upper conductive pattern and extending in the first direction; andat least one upper dummy plug formed to be narrower than the second contact plug in the plane perpendicular to the first direction and overlapping the upper conductive pattern.6. The semiconductor memory device of claim 5 , further comprising:a third contact plug connected to the intermediate ...

Подробнее
03-01-2019 дата публикации

COMPUTER MEMORY

Номер: US20190005996A1
Принадлежит: Intel Corporation

Computer memory technology is disclosed. In one example, a method for isolating computer memory blocks in a memory array from one another can include forming an opening between adjacent blocks of memory structures. The method can also include forming a protective liner layer on at least the memory structures. The method can further include disposing isolating material in the opening and on the protective liner layer. The method can even further include removing the isolating material on the protective liner layer. The method can additionally include removing the protective liner layer on the memory structures. Associated devices and systems are also disclosed. 1. A computer memory device , comprising:a conductive structure;memory structures in communication with the conductive structure, the memory structures being disposed in a semiconductor composite material;an isolating material disposed between adjacent blocks of the memory structures; anda protective liner layer disposed between and in contact with the semiconductor composite material and the isolating material.2. The computer memory device of claim 1 , wherein the protective liner layer is in contact with a bottom surface of the isolating material.3. The computer memory device of claim 1 , wherein the isolating material comprises a wall configuration.4. The computer memory device of claim 1 , wherein the semiconductor composite material comprises a plurality of conductive layers claim 1 , each conductive layer being separated from an adjacent conductive layer by an insulating layer.5. The computer memory device of claim 4 , wherein the conductive layers comprise polysilicon claim 4 , tungsten claim 4 , nickel claim 4 , titanium claim 4 , platinum claim 4 , aluminum claim 4 , gold claim 4 , tungsten nitride claim 4 , tantalum nitride claim 4 , titanium nitride claim 4 , or a combination thereof.6. The computer memory device of claim 4 , wherein the insulating layer comprises an oxide material claim 4 , a ...

Подробнее
20-01-2022 дата публикации

Integrated Circuitry, A Method Used In Forming Integrated Circuitry, And A Method Used In Forming A Memory Array Comprising Strings Of Memory Cells

Номер: US20220020759A1
Автор: Purnima Narayanan
Принадлежит: Micron Technology Inc

A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The first tiers comprise doped silicon dioxide and the second tiers comprise undoped silicon dioxide. Horizontally-elongated trenches are formed into the stack. Through the trenches, the doped silicon dioxide that is in the first tiers is etched selectively relative to the undoped silicon dioxide that is in the second tiers. Conducting material is formed in the void space in the first tiers that is left by the etching. Structure independent of method is disclosed.

Подробнее
08-01-2015 дата публикации

SELF-REFRESH ADJUSTMENT IN MEMORY DEVICES CONFIGURED FOR STACKED ARRANGEMENTS

Номер: US20150009737A1
Автор: JR. Michael C., Stephens
Принадлежит:

Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal. 1. A semiconductor memory device , comprising:a) a stack position identifier for identifying a position of the semiconductor memory device in an aligned vertical stack of a plurality of semiconductor memory devices;b) a self-refresh oscillator configured to generate an oscillating signal to control a rate of self-refresh operations for the semiconductor memory device; andc) an oscillator adjustor configured to change a frequency of the oscillating signal in response to the stack position identifier.2. The semiconductor memory device of claim 1 , further comprising a self-refresh counter configured to count a number of oscillations of the oscillating signal to determine when to initiate the self-refresh operations.3. The semiconductor memory device of claim 1 , wherein the self-refresh oscillator comprises an odd-numbered plurality of inverting stages.4. The semiconductor memory device of claim 3 , wherein at least one of the odd-numbered plurality of inverting stages comprises a pull-up transistor configured to charge a node that is coupled to another of the inverting stages.5. The semiconductor memory device of claim 4 , further ...

Подробнее
08-01-2015 дата публикации

PAD SELECTION IN MEMORY DEVICES CONFIGURED FOR STACKED ARRANGEMENTS

Номер: US20150009738A1
Автор: JR. Michael C., Stephens
Принадлежит:

Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal. 1. A semiconductor memory device , comprising:a plurality of pads allocated to a data input/output (DQ) signal on the semiconductor memory device;a stack position identifier configured to identify a position of the semiconductor memory device in an aligned vertical stack of a plurality of semiconductor memory devices; anda pad selector configured to select one of the plurality of pads to be connected to the DQ signal on the semiconductor memory device in response to the stack position identifier, wherein the pad selector is further configured to disconnect each of a remaining of the plurality of pads from the DQ signal based on the stack position identifier.2. The semiconductor memory device of claim 1 , wherein the pad selector comprises a plurality of pass gates corresponding to the plurality of pads claim 1 , and wherein each of the pass gates is configured to be controlled by a decoded version of the stack position identifier.3. The semiconductor memory device of claim 1 , wherein the selected one of the plurality of pads is different for each of the plurality of semiconductor memory devices in the aligned vertical stack.4. The ...

Подробнее
08-01-2015 дата публикации

MEMORY DEVICES WITH SERIALLY CONNECTED SIGNALS FOR STACKED ARRANGEMENTS

Номер: US20150009739A1
Автор: JR. Michael C., Stephens
Принадлежит:

Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal. 1. A semiconductor memory device , comprising:a) a stack position identifier for identifying a position of the semiconductor memory device in an aligned vertical stack of a plurality of semiconductor memory devices;b) a first pad coupled to a first signal and a first through-silicon via (TSV);c) a second pad coupled to a second signal and a second TSV; andd) a pad signal path determiner configured to determine a signal path direction between the first pad and the second pad in response to the stack position identifier.2. The semiconductor memory device of claim 1 , wherein a first state of the stack position identifier indicates an odd-numbered memory device claim 1 , and a second state of the stack position identifier indicates an even-numbered memory device.3. The semiconductor memory device of claim 2 , wherein a least significant bit (LSB) of the stack position identifier is used to determine whether the memory device is an even-numbered memory device or an odd-numbered memory device.4. The semiconductor memory device of claim 1 , wherein the first and second pads comprise different interconnect positions on the semiconductor ...

Подробнее
27-01-2022 дата публикации

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SEMICONDUCTOR DEVICE

Номер: US20220028431A1
Принадлежит:

A semiconductor device includes a cell area in which a plurality of memory cells are arranged in an array structure, and a peripheral area in which circuits configured to drive the memory cells are arranged, the peripheral area being next to the cell area. The cell area is divided into a plurality of banks, and the plurality of banks comprise first banks having a base size and second banks having a size of 1/(2*n) (wherein n is an integer greater than or equal to 1) of the base size. The plurality of banks are arranged in a first direction and a second direction perpendicular to the first direction, and the semiconductor device has a shape of a rectangular chip which is elongated in the second direction. 1. A semiconductor device comprising:a cell area in which a plurality of memory cells are arranged in an array structure;at least two peripheral areas in which circuits configured to drive the memory cells are arranged, the at least two peripheral areas being arranged next to the cell area,wherein:the cell area is divided into a plurality of banks,the plurality of banks comprise first banks having a first size and second banks having a size of 1/(2*n) (wherein n is an integer greater than or equal to 1) of the first size, andthe at least two peripheral areas each extend in a first direction and are directly adjacent to the plurality of banks; andchip pads arranged in an “L” shape adjacent to an outer edge of a chip,wherein the semiconductor device has a shape of a rectangular chip which is elongated in a second direction perpendicular to the first direction.2. The semiconductor device of claim 1 , wherein:each of the second banks has a size of ½ of the first size,the cell area comprises fifteen first banks and two second banks,five first banks are arranged in each of three sequentially-arranged rows, each row extending in the first direction, and three first banks are arranged in each of five columns, each column extending in the second direction, andthe two second ...

Подробнее
14-01-2016 дата публикации

STACKED SEMICONDUCTOR PACKAGE

Номер: US20160012864A1
Автор: KU Young Jun, PARK Min Su
Принадлежит:

A stacked semiconductor package includes a package substrate, an interposer mounted on the package substrate, a plurality of semiconductor chips stacked on the interposer, and a control unit provided in the interposer, that stores in advance data to be written in the plurality of semiconductor chips, and that outputs the data stored in advance according a test mode signal. 1. A stacked semiconductor package comprising:a package substrate;an interposer mounted on the package substrate;a plurality of semiconductor chips stacked on the interposer; anda control unit provided in the interposer, that stores in advance data to be written in the plurality of semiconductor chips, and outputs the data stored in advance according to a test mode signal.2. The stacked semiconductor package according to claim 1 , wherein the control unit is configured to output the data stored in advance when the test mode signal is enabled claim 1 , and to output data input from the package substrate or the plurality of semiconductor chips when the test mode signal is not enabled.3. The stacked semiconductor package according to claim 1 , wherein claim 1 , when the test mode signal is enabled claim 1 , the control unit is configured to selectively output the data stored in advance according to a minimum time tRTW for which write data is applied after a read operation.4. The stacked semiconductor package according to claim 3 , wherein the control unit outputs the data stored in advance when the minimum time tRTW claim 3 , for which write data is applied after a read operation claim 3 , is shorter than a preset time.5. The stacked semiconductor package according to claim 3 , wherein the control unit outputs data input from the plurality of semiconductor chips or the package substrate claim 3 , when the minimum time tRTW claim 3 , for which write data is applied after a read operation claim 3 , is equal to or more than a preset time.6. A stacked semiconductor package comprising:a package substrate; ...

Подробнее
14-01-2016 дата публикации

SEMICONDUCTOR DEVICE HAVING INTERCONNECTION IN PACKAGE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20160012865A1
Принадлежит:

A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip. 1. A semiconductor device comprising:a first die connected to a first channel, the first die comprising a first memory chip; anda second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die,wherein the first and second dies are disposed in one package; andwherein the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.2. The semiconductor device of claim 1 , wherein:the first channel is a channel dedicated to the first memory chip for receiving a first type of signal from outside the semiconductor device;the second channel is a channel dedicated to the second memory chip for receiving the first type of signal from outside the semiconductor device; andthe interconnection circuit comprises a common channel shared by the first and second memory chips for receiving a second type of signal different from the first type of signal at one of the first and second memory chips and applying the second type of signal to both the first memory chip and the second memory chip.3. The semiconductor device of claim 2 , wherein:the first type of signal is an address, data, ...

Подробнее
10-01-2019 дата публикации

MEMORY DEVICE INCLUDING PAGE BUFFERS

Номер: US20190013050A1
Принадлежит:

A memory device includes a memory cell array; bit lines including even and odd bit lines extending in a first direction and alternately disposed; cache latches including even cache latches which exchange data with the memory cell array through the even bit lines and odd cache latches which exchange data with the memory cell array through the odd bit lines; 2̂k data lines, where k is a natural number equal to or greater than 2, respectively corresponding to 2̂k input/output pins; and column merge units respectively allocated to the input/output pins, and each suitable for coupling any one of the even cache latches or any one of the odd cache latches to a data line corresponding to an input/output pin to which it is allocated. A pitch of the column merge units in a second direction intersecting the first direction is greater than a pitch of the cache latches. 1. A memory device comprising:a memory cell array;bit lines including a plurality of even bit lines and a plurality of odd bit lines, which extend in a first direction and are alternately disposed;cache latches including a plurality of even cache latches which exchange data with the memory cell array through the even bit lines and a plurality of odd cache latches which exchange data with the memory cell array through the odd bit lines;2̂k number of data lines, where k is a natural number equal to or greater than 2, respectively corresponding to 2̂k number of input/output pins; anda plurality of column merge units respectively allocated to the input/output pins, and each suitable for coupling any one of the even cache latches or any one of the odd cache latches to a data line corresponding to the allocated input/output pin,wherein a pitch of the column merge units in a second direction intersecting the first direction is greater than a pitch of the cache latches.2. The memory device according to claim 1 , wherein the cache latches are disposed in the first direction and the second direction claim 1 , and have a ...

Подробнее
10-01-2019 дата публикации

INTERCONNECTION FOR MEMORY ELECTRODES

Номер: US20190013052A1
Принадлежит:

Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level. 1. (canceled)2. An apparatus , comprising:a first access line and a second access line extending in a same direction, wherein at least a portion of the first access line extends beyond a portion of the second access line, and wherein the first access line comprises a first jog segment and the second access line comprises a second jog segment; anda connector coupled with the first jog segment, or the second jog segment, or both.3. The apparatus of claim 2 , further comprising:a socket region comprising a first socket coupled with the first access line and a second socket coupled with the second access line, wherein the first access line extends beyond a boundary of the socket region, and wherein the second access line is located entirely within the boundary of the socket region.4. The apparatus of claim 2 , wherein a distance between the first jog segment and the second jog segment is greater than a distance between another portion of the first access line and another portion of the second access line.5. The apparatus of claim 2 , further comprising:a third access line extending in a different direction than the first access line and the second access line, wherein at least a portion of the third access line intersects at least a portion of the first access line, at least a portion of the second access line, or both.6. The apparatus of claim 2 , wherein the first access line and the second access line are formed at a first vertical level of a stack.7. The apparatus of claim 6 , further comprising:a second vertical level of the stack comprising a fourth access line and a fifth access line extending in a second direction.8. ...

Подробнее
10-01-2019 дата публикации

MEMORY DEVICE ARCHITECTURE

Номер: US20190013068A1
Принадлежит:

Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array. 1. A method , comprising:forming a memory array of memory cells occupying a footprint; andforming a plurality of word line drivers in a circuit level, the plurality of word line drivers within the footprint of the memory array; andforming a plurality of digit line drivers in the circuit level, the plurality of digit line drivers within the footprint of the memory array,wherein the circuit level comprises a plurality of word line driver connection points and digit line driver connection points distributed across the footprint.2. The method of claim 1 , further comprising:forming a plurality of word lines each coupled with and laterally traversing at least one of the plurality of word line drivers at a different vertical level from the plurality of word line drivers.3. The method of claim 2 , wherein each word line driver connection point of the plurality of word line driver connection points is centered along a word line direction within a word line driver region of a plurality of word line driver regions.4. The method of claim 1 , further comprising:forming a plurality of digit lines each coupled with and laterally traversing at least one of the plurality of digit line drivers at a different vertical level from the plurality of digit line drivers.5. The method of claim 4 , wherein each of the digit line driver connection points is centered along a digit line direction within a digit line driver region of a plurality of digit line driver regions.6. The method of claim 1 , wherein at least two word line drivers of the plurality of word line drivers are positioned along a first direction and at least two digit line drivers of the plurality of digit line drivers are positioned along a second direction orthogonal to the first direction.7. The method of claim 1 , wherein the memory array of memory cells comprises two word lines positioned ...

Подробнее
10-01-2019 дата публикации

MEMORY DEVICE ARCHITECTURE

Номер: US20190013069A1
Принадлежит:

Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array. 1. A device , comprising:a plurality of memory cells within a footprint of the device; anda plurality of word line drivers and digit line drivers in a circuit level positioned below the plurality of memory cells, wherein the circuit level comprises a plurality of word line driver connection points and digit line driver connection points within the footprint.2. The device of claim 1 , wherein the plurality of word line drivers are distributed across and within the footprint in a plurality of word line driver regions claim 1 , and wherein the plurality of digit line drivers are distributed across and within the footprint in a plurality of digit line driver regions.3. The device of claim 2 , wherein word line electrodes connecting the plurality of word line drivers to the plurality of memory cells of the device are staggered relative to one another by shifting the word line electrodes relative to one another along their axis of elongation.4. The device of claim 3 , wherein digit line electrodes connecting the plurality of digit line drivers to the plurality of memory cells of the device are staggered relative to one another by shifting the digit line electrodes relative to one another along their axis of elongation.5. The device of claim 1 , wherein the plurality of memory cells comprises word lines positioned along a first direction and digit lines positioned along a second direction different from the first direction.6. The device of claim 1 , further comprising:a plurality of word lines each coupled with at least one of the plurality of word line drivers at a different vertical level from the plurality of word line drivers.7. The device of claim 6 , wherein each word line driver connection point of the plurality of word line driver connection points is positioned along a word line direction within a word line driver region of a ...

Подробнее
15-01-2015 дата публикации

QUERY OPERATIONS FOR STACKED-DIE MEMORY DEVICE

Номер: US20150016172A1
Принадлежит:

An integrated circuit (IC) package includes a stacked-die memory device. The stacked-die memory device includes a set of one or more stacked memory dies implementing memory cell circuitry. The stacked-die memory device further includes a set of one or more logic dies electrically coupled to the memory cell circuitry. The set of one or more logic dies includes a query controller and a memory controller. The memory controller is coupleable to at least one device external to the stacked-die memory device. The query controller is to perform a query operation on data stored in the memory cell circuitry responsive to a query command received from the external device. 1. An integrated circuit (IC) package comprising: a set of one or more stacked memory dies implementing memory cell circuitry; and', 'a set of one or more logic dies electrically coupled to the memory cell circuitry, the set of one or more logic dies comprising a query controller and a memory controller, wherein the memory controller is coupleable to at least one device external to the stacked-die memory device, and wherein the query controller is to perform a query operation on data stored in the memory cell circuitry responsive to a query command received from the external device., 'a stacked-die memory device comprising2. The IC package of claim 1 , wherein:the set of one or more stacked memory dies comprises a memory die having a memory bank, a bank row buffer, and row buffer search logic to search the bank row buffer based on a search criterion provided by the query controller.3. The IC package of claim 1 , wherein:the memory cell circuitry implements a key-value store;the query command comprises a key search command; andthe query operation comprises searching the key-value store for a key specified by the key search command and outputting a data object stored in the key-value store in association with the key.4. The IC package of claim 3 , wherein:the key-value store implements a cache;the key search ...

Подробнее
21-01-2016 дата публикации

THREE-DIMENSIONAL THREE-PORT BIT CELL AND METHOD OF ASSEMBLING SAME

Номер: US20160019946A1
Принадлежит:

A three-port, three-dimensional bit cell generally comprises a read portion of a cell disposed on a first tier. The read portion comprises a plurality of read port elements. The three-port bit cell further comprises a write portion of the cell disposed on a second tier that is vertically stacked with respect to the first tier. The first and second tiers are coupled using at least one via. The write portion comprises a plurality of write port elements.

Подробнее
21-01-2016 дата публикации

ELECTRONIC DEVICE

Номер: US20160019956A1
Принадлежит:

This patent document relates to memory circuits or devices and their applications in electronic devices or systems. The disclosed technology in this patent document includes memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device in which an electronic device capable of reducing an area, improving device characteristics due to a reduction in the resistance of a switching transistor, simplifying the process, and reducing a cost is provided. In accordance with the electronic device of this patent document, an area can be reduced, device characteristics can be improved due to a reduction in the resistance of the switching transistor, the process can be simplified, and a cost can be reduced.

Подробнее
03-02-2022 дата публикации

METHOD OF PERFORMING INTERNAL PROCESSING OPERATIONS WITH PRE-DEFINED PROTOCOL INTERFACE OF MEMORY DEVICE

Номер: US20220036929A1
Принадлежит:

A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode. 1. A memory device comprising:a memory cell array including a first memory region and a second memory region;a processing-in-memory (PIM) engine configured to perform an internal processing operation on the first memory region;a mode selector circuit configured to activate a processing mode selection signal for controlling the memory device to enter the internal processing operation based on a PIM mode entering code, the PIM mode entering code being stored in the mode selector circuit and corresponding to a first back-to-back address sequence along with sequential write commands; anda command converter circuit configured to convert a received command into a PIM command in response to the activation of the processing mode selection signal.2. The memory device of claim 1 , wherein the mode selector circuit is further configured to receive first addresses sequentially claim 1 , compare the PIM mode entering code with the first addresses claim 1 , and activate the processing mode selection signal when the sequential first addresses coincide with the PIM mode entering code.3. The memory device of claim 1 , wherein the command converter circuit is further configured ...

Подробнее
16-01-2020 дата публикации

SEMICONDUCTOR APPARATUS INCLUDING A PLURALITY OF DIES OPERATING AS A PLURALITY OF CHANNELS

Номер: US20200019344A1
Автор: LIM Soo Bin
Принадлежит: SK HYNIX INC.

A semiconductor apparatus includes a substrate, a first die, and a second die. The substrate includes first and second byte pads of a first channel and first and second byte pad of a second channel. First byte pads of the first die are respectively coupled to the first byte pads of the first channel, and second byte pads of the first die are respectively coupled to the second byte pads of the first channel. The second die, as disposed, is rotated by 180° with respect to the first die. First byte pads of the second die are respectively coupled to the second byte pads of the second channel, and second byte pads of the second die are respectively coupled to the first byte pads of the second channel. 1. A semiconductor apparatus comprising:a substrate comprising first byte pads of a first channel, first byte pads of a second channel, second byte pads of the first channel, and second byte pads of the second channel, wherein the first byte pads of the first channel and the first byte pads of the second channel are sequentially disposed on a first side of the substrate, and wherein the second byte pads of the first channel and the second byte pads of the second channel are sequentially disposed on a second side of the substrate opposite the first side of the substrate;a first die comprising first byte pads of the first die and second byte pads of the first die, wherein the first byte pads of the first die are sequentially disposed on a first side of the first die and the second byte pads of the first die are sequentially disposed on a second side of the first die opposite the first side of the first die, and wherein the first byte pads of the first die are respectively coupled to the first byte pads of the first channel and the second byte pads of the first die are respectively coupled to the second byte pads of the first channel; anda second die comprising first byte pads of the second die and second byte pads of the second die, wherein the second die, as disposed, is ...

Подробнее
17-04-2014 дата публикации

SEMICONDUCTOR DEVICE HAVING MEMORY CELL ARRAY DIVIDED INTO PLURAL MEMORY MATS

Номер: US20140104916A1
Принадлежит:

A semiconductor device includes a plurality of memory mats arranged in an X direction and a mat selecting circuit that activates a part of the memory mats based on a row address and maintains the rest of the memory mats inactivated. The memory mats are divided into a plurality of memory mat groups each including the same number of memory mats arranged in the X direction. The mat selecting circuit activates at least one of the memory mats included in each of the memory mat groups, while maintaining the rest of memory mats inactivated. With this operation, a portion of discontinuity does not occur in the memory mats arranged in the X direction, and thus the necessity of arranging two sub-word driver areas in the portion of discontinuity is eliminated. 1. A semiconductor device comprising:a plurality of memory mats each including a plurality of memory cells, the memory mats being arranged in a first direction;a mat selecting circuit that activates at least first to fourth memory mats among the plurality of memory mats based on a part of bits of a row address signal that designates a row address of a memory cell, while maintaining a rest of the memory mats inactivated; anda communication circuit that performs communication of data of the first to fourth memory mats with outside, whereinthe memory mats are divided into a plurality of memory mat groups each including a same number of memory mats arranged in the first direction,the first and second memory mats that are adjacent to each other and a part of the rest of the memory mats are included in a first memory mat group,the third and fourth memory mats that are adjacent to each other and a part of the rest of the memory mats are included in a second memory mat group,the first and third memory mats are allocated with a same first I/O data bit group and a first column address,the second and fourth memory mats are allocated with a same second I/O data bit group and a second column address,each of memory cells of the first ...

Подробнее
16-01-2020 дата публикации

STORAGE DEVICE

Номер: US20200020411A1
Принадлежит:

A storage device according to the present disclosure includes: a plurality of first wiring lines extending in a first direction and including a plurality of first selection lines and a plurality of second selection lines; a plurality of second wiring lines extending in a second direction and including a plurality of third selection lines and a plurality of fourth selection lines, the second direction intersecting the first direction; a plurality of first memory cells; a first driver including a first selection line driver that drives the plurality of first selection lines on a basis of a first selection control signal and a second selection line driver that drives the plurality of second selection lines on a basis of the first selection control signal, the first and second selection line drivers being arranged side-by-side in the first direction; and a second driver including a third selection line driver that drives the plurality of third selection lines on a basis of a second selection control signal and a fourth selection line driver that drives the plurality of fourth selection lines on a basis of the second selection control signal, the third and fourth selection line drivers being arranged side-by-side in the second direction. 1. A storage device , comprising:a plurality of first wiring lines provided in a first region, the plurality of first wiring lines extending in a first direction and including a plurality of first selection lines and a plurality of second selection lines;a plurality of second wiring lines provided in the first region, the plurality of second wiring lines extending in a second direction and including a plurality of third selection lines and a plurality of fourth selection lines, the second direction intersecting the first direction;a plurality of first memory cells each inserted between a corresponding one of the plurality of first wiring lines and a corresponding one of the plurality of second wiring lines;a first driver including a ...

Подробнее
21-01-2021 дата публикации

SEMICONDUCTOR DEVICES INCLUDING STACK STRUCTURE HAVING GATE REGION AND INSULATING REGION

Номер: US20210020648A1
Принадлежит:

A semiconductor device includes a lower structure and a stack structure that extends into a connection region on the lower structure, where the stack structure includes gate pads and mold pads. The mold pads include intermediate mold pads that include first intermediate mold pads and a second intermediate mold pad between a pair of the first intermediate mold pads, each of the first intermediate mold pads has a first length in a first direction, the second intermediate mold pad has a second length in the first direction, greater than the first length, one of the intermediate mold pads includes a mold pad portion and an insulating protrusion portion on the mold pad portion, one of the first intermediate mold pads includes the mold pad portion and the insulating protrusion portion, and a central region of the second intermediate mold pad does not include the insulating protrusion portion. 1. A semiconductor device , comprising:a lower structure comprising a lower substrate, an upper substrate on the lower substrate, a peripheral circuit region between the lower substrate and the upper substrate and comprising peripheral wirings, and a gap-fill insulating layer penetrating the upper substrate;a stack structure in a memory cell array region on the lower structure and extending into a connection region on the lower structure, wherein the stack structure has a staircase structure in the connection region, wherein the stack structure comprises a gate region and a first insulating region, wherein the gate region is in the memory cell array region and extends into the connection region, and wherein the first insulating region is in the connection region;a capping insulating layer on the stack structure; anda memory cell vertical structure in the gate region in the memory cell array region,wherein the stack structure comprises a plurality of first layers and a plurality of second layers alternately stacked on the lower structure,wherein the plurality of second layers comprise ...

Подробнее
25-01-2018 дата публикации

Memory Module for a Data Center Compute Sled

Номер: US20180024864A1
Принадлежит:

Examples may include a sled for a rack of a data center including physical compute resources. The sled comprises a processor component and a unitary memory module comprising a memory controller and a quantity of memory based on the processor component. The unitary memory module can comprise a quantity of memory based on a number of cores of processor component to which the unitary memory module is communicably coupled. 1. An apparatus for a sled to house physical compute resources of a data center , the apparatus comprising:a substrate;a first socket to receive a processor component, the first socket disposed on a first surface of the substrate; anda first memory socket to receive a memory module, the first memory socket disposed on a second surface of the substrate different than the first surface of the substrate, the first memory socket to couple the memory module to the processor component.2. The apparatus of claim 1 , wherein the first memory socket is configured to receive a unitary memory module.3. The apparatus of claim 2 , comprising the processor component and the unitary memory module.4. The apparatus of claim 3 , the unitary memory module comprising a quantity of memory based in part on a number of cores of the processor component.5. The apparatus of claim 3 , comprising:a processor component heat sink mechanically coupled to the substrate and thermally coupled to the processor component; anda unitary memory module heat sink mechanically coupled to the substrate and thermally coupled to the near memory unitary module.6. The apparatus of claim 5 , comprising the unitary memory module heat sink removably mechanically coupled to the substrate.7. The apparatus of claim 6 , comprising a hinge coupled to the substrate and a frame coupled to the hinge claim 6 , the frame and hinge to removably mechanically couple the unitary memory module to the substrate.8. The apparatus of claim 7 , the frame and hinge to removably mechanically couple the unitary memory ...

Подробнее
28-01-2016 дата публикации

INTERLEAVED GROUPED WORD LINES FOR THREE DIMESIONAL NON-VOLATILE STORAGE

Номер: US20160027477A1
Автор: Petti Christopher J.
Принадлежит:

A three dimensional non-volatile storage system includes a substrate and a plurality of memory cells arranged in a monolithic three dimensional memory array (or other 3D structure) positioned above and not in the substrate. The system includes a plurality of vertical bit lines and a plurality of word lines. Each group of three neighboring word lines on a common level of the three dimensional memory array are electrically isolated from each other and at least a subset of the three neighboring word lines of each group are connected to other word lines. 1. A non-volatile storage device , comprising:a substrate;a plurality of memory cells arranged in a three dimensional structure positioned above and not in the substrate;a plurality of vertical bit lines;a plurality of word lines, each group of three neighboring word lines on a common level of the three dimensional structure are electrically isolated from each other and at least a subset of the three neighboring word lines of each group are connected to other word lines, each memory cell of the plurality is connected to one of the bit lines and one of the word lines.2. The non-volatile storage device of claim 1 , further comprising:a plurality of vertical select devices connected to the vertical bit lines, the vertical select devices comprise a transistor that includes a gate electrode that is shared by two neighboring vertical select devices.3. The non-volatile storage device of claim 3 , further comprising:a set of global bit lines, the vertical select devices are positioned above and not in the substrate, the vertical select devices selectively connect the vertical bit lines to the global bit lines.4. The non-volatile storage device of claim 1 , wherein:the three neighboring word lines are part of three different groups of connected word lines that are interleaved on the common level of the three dimensional structure, the three different groups of connected word lines each have multiple connected word lines on the ...

Подробнее
28-01-2016 дата публикации

STACK BANK TYPE SEMICONDUCTOR MEMORY APPARATUS CAPABLE OF IMPROVING ALIGNMENT MARGIN

Номер: US20160027478A1
Принадлежит:

A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks. 1. A semiconductor memory apparatus comprising:a plurality of stack bank structures, the plurality of stack bank structures being spaced apart from each other at a predetermined interval and including a plurality of sub-banks;a plurality of control blocks, wherein each control block configured to control all column-related signals of the sub-banks constituting each stack bank structures; anda plurality of global input/output lines arranged between the stack bank structures.2. The semiconductor memory apparatus of claim 1 , wherein the stack bank structure includes a plurality of sub-banks continuously stacked without disconnection of signal lines.3. The semiconductor memory apparatus of claim 1 , wherein a predetermined number of global input/output lines are provided to each stack bank structure claim 1 , and wherein the global input/output lines are used for data input/output of the sub-banks constituting the stack bank structure.4. The semiconductor memory apparatus of claim 3 , wherein the global input/output lines are arranged between the control blocks in parallel to the control blocks.5. The semiconductor memory apparatus of claim 1 , wherein each control block is arranged at one side of the stack bank structure.6. The semiconductor memory apparatus of claim 5 , wherein a part of the control block is arranged between the sub banks constituted in the stack bank structure.7. The semiconductor memory apparatus of claim 6 , wherein each control block includes an address control block and an Input/Output control ...

Подробнее
26-01-2017 дата публикации

Three-Dimensional Mask-Programmed Read-Only Memory With Reserved Space

Номер: US20170025389A1
Автор: Guobiao Zhang
Принадлежит: CHENGDU HAICUN IP TECHNOLOGY LLC

The present invention discloses a 3D-MPROM with reserved level (3D-MPROM RL ). Versions of the 3D-MPROM RL , including an original 3D-MPROM RL and at least an updated 3D-MPROM RL , collectively form a 3D-MPROM RL family. Within a 3D-MPROM RL family, 3D-MPROM RL 's of different versions are same except for at least a reserved level, which is absent in the original 3D-MPROM RL but present in the updated 3D-MPROM RL .

Подробнее
10-02-2022 дата публикации

Processing-in-memory (pim) devices

Номер: US20220043632A1
Автор: Choung Ki Song
Принадлежит: SK hynix Inc

A processing-in-memory (PIM) device includes first to Lth multiplication/accumulation (MAC) operators, first to Lth memory banks, and a plurality of data input/output (I/O) circuits. The first to Lth MAC operators include first to Lth left MAC operators and first to Lth right MAC operators. The plurality of data I/O circuits include left data I/O circuits and right data I/O circuits. A Uth MAC operator among the first to Lth MAC operators is configured to output one of the first to Mth MAC result data through a Uth left MAC operator among the first to Lth left MAC operators or a Uth right MAC operator among the first to Lth right MAC operators. The PIM device is configured to output the MAC result data outputted through the left MAC operators through the left data I/O circuits, and output the MAC result data outputted through the right MAC operators through the right data I/O circuits.

Подробнее
24-01-2019 дата публикации

ACCESS PROCESSOR

Номер: US20190026037A1
Автор: Van Lunteren Jan
Принадлежит:

A reconfigurable computing device having a plurality of reconfigurable partitions and that is adapted to perform parallel processing of operand data by the partitions is provided. The computing system includes a memory device that is adapted to store configuration data to configure the partitions of the computing device, to store operand data to be processed by the configured partitions and to store processing results of the operand data. A programmable memory access processor having a predefined program is provided. The access processor performs address generation, address mapping and access scheduling for retrieving the configuration data from the memory unit, for retrieving the operand data from the memory unit and for storing the processing results in the memory unit. The access processor also transfers the configuration data from the memory unit to the computing device and transfers the operand data from the memory unit to the computing device. 1. A computing system comprising:at least one reconfigurable computing device, the reconfigurable computing device having a plurality of reconfigurable partitions and being adapted to perform parallel processing of operand data by the partitions; and receive a preset configuration time for configuring one or more of the partitions for a processing operation, the preset configuration time is an amount of time that is required for configuring the one or more of the partitions for the processing operation;', 'schedule a transfer time for a transfer of the operand data to the reconfigurable computing device for the processing operation in accordance with the preset configuration time; and', 'transfer the operand data to the reconfigurable computing device at the transfer time., 'a programmable memory access processor comprising a predefined program, the access processor being adapted to2. A computing system according to claim 1 , wherein the reconfigurable computing device is a field programmable gate array (FPGA).3. A ...

Подробнее
10-02-2022 дата публикации

STORAGE DEVICE HAVING MULTIPLE STORAGE DIES AND IDENTIFICATION METHOD

Номер: US20220044708A1
Автор: ZOU Gaoxiang

A storage device having multiple storage dies is disclosed. The storage device comprises: a printed circuit board having a main surface, a plurality of universal input/output pins, placed on the main surface of the printed circuit board, and a plurality of random access storage dies, corresponding to the plurality of universal input/output pins, placed on the plurality of universal input/output pins. 1. A storage device having multiple storage dies , the storage device comprising:a printed circuit board, having a main surface;a plurality of universal input/output pins, placed on the main surface of the printed circuit board; anda plurality of random access storage dies, corresponding to the plurality of universal input/output pins, placed on the plurality of universal input/output pins.2. The storage device of claim 1 , wherein a number of the plurality of universal input/output pins is not less than 2.32. The storage device of claim 1 , wherein a number of the plurality of random access storage dies is not less than and is corresponding to a number of the plurality of universal input/output pins.4. The storage device of claim 1 , wherein the plurality of random access storage dies have a same material removal rate.5. The storage device of claim 1 , wherein the plurality of random access storage dies comprise dies having a same memory timing claim 1 , dies having different memory dies claim 1 , or any combination.6. An identification method claim 1 , used in an embedded equipment having a storage device having multiple storage dies claim 1 , the embedded equipment comprising a processing unit and a synchronous dynamic random access memory device claim 1 , the identification method comprising:establishing a memory timing look-up table and storing the memory timing look-up table in the synchronous dynamic random access memory device;establishing a dynamic random access memory type mapping table, and storing the dynamic random access memory type mapping table in the ...

Подробнее
24-04-2014 дата публикации

CONFIGURABLE BANDWIDTH MEMORY DEVICES AND METHODS

Номер: US20140112046A1
Автор: Jeddeloh Joe M.
Принадлежит: MICRON TECHNOLOGY, INC.

Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed. 1. A memory device , comprising:a stack of memory dies, including a number of memory portions;a logic die coupled to the stack of memory dies;a memory fabric control register selectably coupled to the number of memory portions to select a number of memory portions that operate synchronously for a single memory request.2. The memory device of claim 1 , wherein the logic die is located apart from the stack of memory dies.3. The memory device of claim 1 , wherein the logic die is stacked with the stack of memory dies.4. The memory device of claim 1 , wherein the memory portions include memory vaults.5. A memory device claim 1 , comprising:a stack of memory dies, including a number of memory portions;a logic die coupled to the stack of memory dies;a memory fabric control register selectably coupled to the number of memory portions to select a number of memory portions that operate synchronously for a single memory request;a buffered connection between an originating and/or destination device and the stack of memory dies.6. The memory device of claim 5 , wherein each memory portion includes both a direct connection to the originating and/or destination device claim 5 , and a buffered connection to the originating and/or destination device.7. The memory device of claim 5 , wherein the fabric control register is adapted to configure bandwidth in the memory device upon reset of the memory device.8. The memory device of claim 5 , wherein the fabric control register is adapted to configure bandwidth in the memory device upon startup of the memory device.9. The memory device of claim 5 , wherein the memory portions include memory vaults.10. A system claim 5 , comprising:a stack of memory dies, ...

Подробнее
10-02-2022 дата публикации

Integrated Assemblies and Methods of Forming Integrated Assemblies

Номер: US20220045075A1
Принадлежит: MICRON TECHNOLOGY, INC.

Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies. 1. An integrated assembly , comprising:a source structure;a stack of alternating conductive levels and insulative levels over the source structure;cell-material-pillars passing through the stack; the cell-material-pillars being arranged within a configuration which includes a first memory-block-region and a second memory-block-region; the cell-material-pillars including channel material; the channel material being electrically coupled with the source structure;memory cells along the conductive levels and comprising regions of the cell-material-pillars; anda panel between the first and second memory-block-regions; the panel having a first material configured as a container shape; the container shape, along a cross-section, defining opposing sides and a bottom of an interior cavity; the panel having a second material within the interior cavity, with the second material being compositionally different from the first material.2. The integrated assembly of wherein the first material comprises conductive material.3. The integrated assembly ...

Подробнее
10-02-2022 дата публикации

Integrated Assemblies, and Methods of Forming Integrated Assemblies

Номер: US20220045086A1
Принадлежит: MICRON TECHNOLOGY, INC.

Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies. 1. An integrated assembly , comprising:a first deck having first memory cell levels alternating with first insulative levels; the first memory cell levels comprising first conductive regions; the first insulative levels comprising first insulative material;a second deck over the first deck; the second deck having second memory cell levels alternating with second insulative levels; the second memory cell levels comprising second conductive regions; the second insulative levels comprising second insulative material;a cell-material-pillar passing through the first and second decks; memory cells being along the first and second memory cell levels and comprising regions of the cell-material-pillar; andan intermediate level between the first and second decks; the intermediate level comprising a buffer region adjacent the cell-material-pillar; said buffer region including a composition different from the first and second insulative materials, and different from the first and second conductive regions; the buffer region having a vertical thickness which is approximately equivalent to at least a combined vertical thickness of two of the first memory cell levels ...

Подробнее
29-01-2015 дата публикации

CONTEXT PROTECTION FOR A COLUMN INTERLEAVED MEMORY

Номер: US20150029773A1
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

A semiconductor memory cell includes a set of circuit structures, each having column input/output circuits. The semiconductor memory cell further includes a set of replicas corresponding to the column input/output circuits. The set of replicas are non-functional and fills an empty space next to the column input/output circuits and hence, provides context protection for the column input/output circuits. 1. A semiconductor memory cell comprising:a set of circuit structures, each comprising column input/output circuits; anda set of replicas, that are non-functional, corresponding to the column input/output circuits, the set of replicas configured to fill an empty space next to the column input/output circuits, wherein the set of replicas provide context protection for the column input/output circuits.2. The semiconductor memory cell of claim 1 , wherein the column input/output circuits comprises one of a sense amplifier claim 1 , a set of input/output latches and a set of input/output drivers.3. The semiconductor memory cell of claim 1 , wherein the empty space is created when a given MUX factor for the semiconductor memory cell is reused for a higher MUX factor.4. The semiconductor memory cell of claim 1 , wherein each replica of the set of replicas is configured to fill the empty space of the corresponding column input/output circuit.5. The semiconductor memory cell of claim 1 , wherein each replica of the set of replicas provides identical context effects to the corresponding column input/output circuit that reduces unpredictable proximity effect for all MUX factors.6. The semiconductor memory cell of claim 1 , wherein each of the set of replicas is configured to be non-functional by removing respective poly contacts and metal connections.7. A semiconductor memory layout comprising:a memory cell array having a plurality of semiconductor memory cells being arranged in rows and columns;a plurality of bit lines coupled to the semiconductor memory cells arranged in ...

Подробнее
29-01-2015 дата публикации

STACKED DEVICE IDENTIFICATION ASSIGNMENT

Номер: US20150029774A1
Автор: Keeth Brent
Принадлежит:

Some embodiments include apparatus and methods having dice arranged in a stack. The dice include at least a first die and a second die, and a connection coupled to the dice. The connection may be configured to transfer control information to the first die during an assignment of a first identification to the first die and to transfer the control information from the first die to the second die during an assignment of a second identification to the second die. 1dice arranged in a stack, the dice including at least a first die and a second die; and. An apparatus comprising: This application is a continuation of U.S. application Ser. No. 13/412,367, filed Mar. 5, 2012, which is a continuation of U.S. application Ser. No. 12/209,048, filed Sep. 11, 2008, now issued as U.S. Pat. No. 8,130,527, all of which are incorporated herein by reference in their entirety.Computers and other electronic products, e.g., televisions, digital cameras, and cellular phones, often use memory devices to store data and other information. Some memory devices may have multiple semiconductor dice arranged in a stack. Each of these dice may have its own identification (ID) to allow appropriate communication. Assigning an ID to a die in some conventional techniques may include performing either wire bond programming or fuse programming. Some stacked dice may not have wire bonds, and therefore wire bond programming may be unsuitable. Fuse programming may involve individually assigning an ID to the die before it is arranged in the stack with other dice. Fuse programming may also use some kind of record keeping to track the die and its assigned ID. Record keeping, however, may create additional work.is a block diagram of an apparatus including dice , , , , and , and connections and , according to an embodiment of the invention. Apparatus may include or be included in a memory device, a processor, a computer, a television, a digital camera, a cellular phone, or another electronic device or system. ...

Подробнее
29-01-2015 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20150029805A1
Принадлежит: SK HYNIX INC.

A semiconductor memory device includes a plurality of first regions formed in a line-type and extending in a first direction, and a plurality of second regions and a plurality of third regions arranged between adjacent first regions in a zigzag manner. 1. A semiconductor memory device comprising:a plurality of first regions formed in a line shape and extending in a first direction; anda plurality of second regions and a plurality of third regions arranged to form a zigzag pattern between adjacent first regions.2. The semiconductor memory device according to claim 1 , wherein each first region corresponds to a power region configured to provide a power-supply voltage.3. The semiconductor memory device according to claim 2 , wherein at least one second region includes a drive region having one or more drive elements receiving the power-supply voltage claim 2 , and at least one third region includes a dummy region into which the at least one second region is extended.4. The semiconductor memory device according to claim 3 , wherein the at least one third region includes a first dummy region adjacent to the at least one second region in the first direction claim 3 , and a second dummy region adjacent to the at least one second region in a second direction different from the first direction.5. The semiconductor memory device according to claim 3 , wherein extending the at least one second region includes increasing a number of the drive elements.6. The semiconductor memory device according to claim 3 , wherein extending the at least one second region includes increasing a gate width of at least one of the drive elements.7. The semiconductor memory device according to claim 4 , wherein the second direction is orthogonal to the first direction.8. The semiconductor memory device according to claim 1 , wherein at least one of the first regions claim 1 , second regions claim 1 , or third regions is connected to an external part through a bump.9. A semiconductor memory device ...

Подробнее
24-01-2019 дата публикации

Storage system and method for die-based data retention recycling

Номер: US20190027193A1
Принадлежит: Western Digital Technologies Inc

The subject technology performs the following in a storage system including memory dies, where each memory die includes its own temperature sensor. The subject technology determines a temperature of each of the memory dies based on a temperature reading from each memory die's temperature sensor. The subject technology determines whether data is hot data or cold data, where hot data is more likely to be changed after it is written than cold data. In response to determining that the data is hot data, the subject technology stores the data in a memory die with a relatively higher temperature than another one of the memory dies. Further, in response to determining that the data is cold data, the subject technology stores the data in a memory die with a relatively cooler temperature than another one of the memory dies.

Подробнее
01-02-2018 дата публикации

STACKED MEMORY DEVICE AND A MEMORY CHIP INCLUDING THE SAME

Номер: US20180032252A1
Принадлежит:

A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process. 1. A stacked memory device , comprising:a logic semiconductor die;a plurality of memory semiconductor dies stacked with the logic semiconductor die;a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies;a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process;a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process; anda plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.2. The stacked memory device of claim 1 , wherein the global processor and the local processors perform the data process instead of an external device.3. The stacked memory device of claim 2 , wherein the global processor performs the global sub process in response to external data provided from the external device or internal data provided from the memory integrated circuits and the local processors perform the local sub processes in response to a ...

Подробнее
02-02-2017 дата публикации

Electronic device

Номер: US20170032834A1
Принадлежит: Renesas Electronics Corp

The number of terminals included in a semiconductor device which is included in an electronic device is reduced. The electronic device includes: a first semiconductor device having first and second input terminals; a second semiconductor device having a first output terminal and a first driver circuit to drive the first output terminal; and a wiring substrate over which the first and second semiconductor devices are mounted. The first and second input terminals are commonly coupled to the first output terminal via a first line formed on the wiring substrate. A composite resistance value of first and second termination resistors coupled to the first and second input terminals, respectively, is equivalent to a drive impedance of the first driver circuit.

Подробнее
02-02-2017 дата публикации

Connections for memory electrode lines

Номер: US20170033042A1
Принадлежит: Micron Technology Inc

Subject matter disclosed herein may relate to word line electrodes and/or digit line electrodes in a cross-point array memory device. One or more word line electrodes may be configured to form a socket area to provide connection points to drivers and/or other circuitry that may be located within a footprint of an array of memory cells.

Подробнее
04-02-2016 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20160035396A1
Принадлежит:

According to an embodiment, a semiconductor device includes a plurality of wiring patterns of wiring lines disposed in parallel in a line-and-space pattern in a predetermined pitch and extend in a first direction in a first region, first bending patterns that extend pairs of the wiring lines in a second in a second region adjacent to the first region, second bending patterns extend the pairs of wiring lines in opposite directions along the orientation of the first direction in the second region, and dummy patterns separated from the two second bending patterns at a predetermined distance. 1. A semiconductor device comprising:a plurality of conductive lines formed into wiring patterns wherein the lines are disposed in parallel in a line-and-space pattern having a predetermined pitch and extend in a first direction in a first region, wherein;first bending patterns, in which adjacent pairs of lines in the wiring pattern are bent in a second direction and extend into a second region adjacent to the first region from the first region;second bending patterns, in which adjacent pairs of lines in the wiring pattern are bent so as to extend away from each other in the first direction in the second region; anddummy patterns spaced from, and adjacent to, the two second bending patterns at a predetermined distance.2. The semiconductor device according to claim 1 , whereinthe dummy pattern is a first dummy pattern having a line shape.3. The semiconductor device according to claim 1 , whereinthe dummy pattern includes:a first dummy pattern having a line shape, andsecond dummy patterns that are connected to both sides of the first dummy pattern and extend in the second direction.4. The semiconductor device according to claim 1 , whereinthe dummy pattern includes:a first dummy pattern having a line shape, anda third dummy pattern, having a line shape, that is separated from the first dummy pattern at a predetermined interval in the second direction and is disposed to extend in the ...

Подробнее
04-02-2016 дата публикации

Memory device architecture

Номер: US20160035418A1
Принадлежит: Micron Technology Inc

Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.

Подробнее
05-02-2015 дата публикации

Memory Devices

Номер: US20150036405A1
Автор: Mouli Chandra
Принадлежит:

Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage. 161-. (canceled)62. A memory device comprising:a wordline;a bitline;a memory element between the wordline and the bitline; anda diode between the wordline and the bitline, the diode comprising at least one undoped layer.63. The memory device of wherein the at least one undoped layer comprises an undoped dielectric layer.64. The memory device of wherein the at least one undoped layer comprises at least two undoped dielectric layers.65. The memory device of wherein the at least one undoped layer comprises an electrode.66. The memory device of wherein the diode is between the wordline and the memory element.67. The memory device of wherein the diode is only at a cross-point of the bitline and the wordline.68. A memory device comprising:a wordline;a bitline;a memory element between the wordline and the bitline; anda diode between the wordline and the bitline, the diode comprising at least two staked and discrete dielectric layers.69. The memory device of wherein the diode is between the bitline and the memory element.70. The memory device of wherein the diode is between the wordline and the memory element.71. The ...

Подробнее
05-02-2015 дата публикации

DATA PROCESSING DEVICE

Номер: US20150036406A1
Принадлежит:

A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board. 1. A semiconductor chip comprising:a semiconductor board having a surface comprised of a quadrangle in plan view, the surface having a first side, a second side facing the first side, a third side crossing the first and second sides, and a fourth side facing the third side and crossing the first and second sides;a plurality of first pads for a first memory interface circuit formed over the surface of the semiconductor board, the first pads being arranged along the first side of the surface of the semiconductor board in plan view, the first pads being arranged closer to the first side of the surface of the semiconductor board than the second side of the surface of the semiconductor board in plan view; anda plurality of second pads for a second memory interface circuit formed over the surface of the semiconductor board, the second pads being arranged along the third side of the surface of the semiconductor board in plan view, the second pads being arranged closer to the third side of the surface of the semiconductor board than the fourth side of the surface of the semiconductor board in plan view.2. The semiconductor chip according to claim 1 ,wherein the semiconductor board has first and second memory interface circuits,wherein the first memory interface circuit has a first data ...

Подробнее