УСТРОЙСТВО ПОЛУПРОВОДНИКОВОЙ ПАМЯТИ ДЛЯ ДОСТИЖЕНИЯ ВЫСОКОЙ ПРОИЗВОДИТЕЛЬНОСТИ И СПОСОБ РАСПОЛОЖЕНИЯ В НЕМ СИГНАЛЬНЫХ ШИН

Изобретение относится к устройству полупроводниковой памяти. Техническим результатом является высокая производительность указанного устройства без использования отдельной локальной шины ввода-вывода для соединения битовой шины и главных шин ввода-вывода. Устройство содержит банки памяти, множество битовых шин, шин ввода-вывода данных (сигнальных шин), шин выбора столбца (сигнальных шин), словных шин, главную шину ввода-вывода данных, транзисторы считывания, транзисторы для записи, мультиплексор. Способ описывает расположение в нем сигнальных шин. 2 с. и 1 з.п. ф-лы, 13 ил.

ANORDNUNG VERFLOCHTENER UND VERSCHLUNGENER WORTLEITUNGEN FUER HALBLEITERSPEICHER

SPEICHERMODULBAUGRUPPE, DIE TEILWEISE DEFEKTE CHIPS VERWENDET

NAN-Flash-Speicher mit hierarchischer Bitleitungs-und-Wortleitungs-Architektur

Vorrichtung, die umfasst: eine Vielzahl von Flash-Speicheranordnungen; einen globalen Wortleitungs-Treiber, der mit jeder Flash-Speicheranordnung verbunden ist, wobei jeder globale Wortleitungs-Treiber mit einer Vielzahl von Auswählleitungen gekoppelt ist; eine Vielzahl von Leseverstärkern, die mit einer Vielzahl von Bitleitungen gekoppelt sind; eine Vielzahl von Teilanordnungen in jeder Flash-Speicheranordnung, wobei jede Teilanordnung eine Vielzahl von NAND-Flash-Speicherzellen enthält, die mit lokalen Wortleitungen und lokalen Bitleitungen gekoppelt sind; einen lokalen Wortleitungs-Treiber, der mit jeder Teilanordnung verbunden ist und mit der Vielzahl von Auswahlleitungen gekoppelt und so konfiguriert ist, dass er diejenigen der lokalen Wortleitungen in seiner Teilanordnung ansteuert, die mit ausgewählten der Vielzahl von NAND-Flash-Speicherzellen in seiner Teilanordnung verbunden sind; und einen lokalen Bitleitungs-Treiber, der zwischen ausgewählte der lokalen Bitleitungen in jeder ...

Halbleitervorrichtung und Verfahren zum Betreiben derselben

Eine Halbleitervorrichtung enthält eine Source-Schicht; eine Mehrzahl an Kanalstrukturen; eine Mehrzahl an Gate-Elektroden; und eine gemeinsame Source-Leitung. Mindestens eine der Mehrzahl an Gate-Elektroden sieht eine GIDL-Leitung vor. Für eine Löschoperation erreicht eine an die gemeinsame Source-Leitung angelegte Löschspannung eine Zielspannung und, nachdem die Löschspannung die Zielspannung erreicht hat, wird eine Schrittweitenspannung an die Löschspannung angelegt, sodass die Löschspannung einen Spannungspegel aufweist, der höher ist als ein Spannungspegel der Zielspannung. Nachdem die Schrittweitenspannung für einen gewünschten Zeitraum angelegt worden ist, wird der Spannungspegel der Löschspannung für den verbleibenden Verlauf der Löschspannung auf den Zielspannungspegel gesenkt.

Integrierte Vorrichtung in Halbleiterscheibengrösse.

REFORMING DIGITAL SIGNALS IN INTEGRATED CIRCUITS

Halbleiterspeicheranordnung

Speichersystem mit zwei Taktsignalleitungen und einer Speichervorrichtung

Speichersystem, umfassend: – eine Vielzahl von Speichervorrichtungen (2), wobei jede Speichervorrichtung (2) jeweils einen Taktanschluss (5) und jeweils einen Datenanschluss (15) aufweist; – eine Speichersteuereinheit (4) zum Steuern des Betriebs der Vielzahl von Speichervorrichtungen (2), wobei die Speichersteuereinheit (4) jeweils einen Schreibtaktausgang (6) und jeweils einen Lesetakteingang (9) für die jeweilige Speichervorrichtung (2) umfasst; – jeweils eine erste Taktsignalleitung (7) zwischen einem entsprechenden Schreibtaktausgang (6) der Speichersteuereinheit (4) und einem entsprechenden Taktanschluss (5) der jeweiligen Speichervorrichtung (2), um ein Taktsignal an die entsprechende Speichervorrichtung (2) weiterzuleiten; – jeweils eine zweite Taktsignalleitung (8) zwischen dem entsprechenden Taktanschluss (5) der jeweiligen Speichervorrichtung (2) und dem entsprechenden Lesetakteingang (9) der Speichersteuereinheit (4), um das an den jeweiligen Taktsignal-Eingang (5) der entsprechenden ...

Elektrische Signalversorgungsschaltung und Halbleiterspeicheranordnung

Dynamisches Multipegelspeicherbauelement und Verfahren zum Treiben eines dynamischen Multipegelspeicherbauelements

Die Erfindung bezieht sich auf ein dynamisches Multipegelspeicherbauelement, das eine offene Bitleitungsstruktur aufweist, und auf ein Verfahren zum Treiben desselben. Das dynamische Multipegelspeicherbauelement umfasst eine Mehrzahl von Wortleitungen (WL), eine Mehrzahl von Bitleitungen (BL), die in einer offenen Bitleitungsstruktur angeordnet sind, eine Mehrzahl von Speicherzellen, wobei jede Speicherzelle mit einer der Wortleitungen (WL) und mit einer der Bitleitungen (BL) verbunden ist und dazu konfiguriert ist, wenigstens zwei Daten-Bits zu speichern, und eine Mehrzahl von Abtastverstärkern (SA_M, SA_S), die jeweils eine Spannungsdifferenz zwischen den Bitleitungen (BL) verstärken, wobei die Bitleitungen (BL) auf gegenüberliegenden Seiten eines jeweiligen Abtastverstärkers der Mehrzahl von Abtastverstärkern (SA_M, SA_S) angeordnet sind. Verwendung z. B. in der Speichertechnologie.

SEMICONDUCTOR MEMORY DEVICE SIGNAL LINE LAYOUT

High density memory devices generally include a plurality of word line devices connected to a plurality of word lines, a plurality of bit lines, and various decoders. In such memory devices, capacitances between adjacent lines can cause unwanted coupling noise and consequent mis-routing of signals. A memory device aimed at overcoming some of these problems includes in a memory cell array a plurality of bit lines BL, a plurality of word lines WL, and a plurality of sense amplifiers SA. The word lines are twisted in groups of four such that lines which are adjacent over part of their length become non-adjacent over another part of their length and are arranged in such a way as to reduce the coupling capacitances between the lines. ...

ZIRKULATOR CHAIN MEMORY INSTRUCTION AND - ADDRESS BUS TOPOLOGY

MRAM ARCHITECTURE WITH A WITH MASS CONNECTION WRITE BIT ORGANIZATION AND AN ELECTRICALLY INSULATING READ BIT ORGANIZATION

CONTROLLING OF THE WORD LINE TRANSISTOR STRENGTH FOR READING AND WRITING IN A MAGNETORESISTIVEN STT-RAM

INTEGRATED MONOLITH ELEMENT

MODULAR MEMORY MODULE

ZIRKULATOR CHAIN MEMORY INSTRUCTION AND - ADDRESS BUS TOPOLOGY

ZIRKULATOR CHAIN MEMORY INSTRUCTION AND - ADDRESS BUS TOPOLOGY

ZIRKULATOR CHAIN MEMORY INSTRUCTION AND - ADDRESS BUS TOPOLOGY

ZIRKULATOR CHAIN MEMORY INSTRUCTION AND - ADDRESS BUS TOPOLOGY

ZIRKULATOR CHAIN MEMORY INSTRUCTION AND - ADDRESS BUS TOPOLOGY

ZIRKULATOR CHAIN MEMORY INSTRUCTION AND - ADDRESS BUS TOPOLOGY

ZIRKULATOR CHAIN MEMORY INSTRUCTION AND - ADDRESS BUS TOPOLOGY

ZIRKULATOR CHAIN MEMORY INSTRUCTION AND - ADDRESS BUS TOPOLOGY

ZIRKULATOR CHAIN MEMORY INSTRUCTION AND - ADDRESS BUS TOPOLOGY

ZIRKULATOR CHAIN MEMORY INSTRUCTION AND - ADDRESS BUS TOPOLOGY

ZIRKULATOR CHAIN MEMORY INSTRUCTION AND - ADDRESS BUS TOPOLOGY

ZIRKULATOR CHAIN MEMORY INSTRUCTION AND - ADDRESS BUS TOPOLOGY

A biasing technique for a high density sram

Low latency multi-level communication interface

SHARED QUIET LINE FLIP-FLOP

SHARED QUIET LINE FLIP-FLOP A quiet line flip-flop is connected to a plurality of lines (12, 14) for reducing the effect of capacitive coupling between the lines (12, 14) and a line (18). node (26) is precharged by a transistor (34) to render conductive transistors (30, 32) which connect the respective lines (12, 14) to a ground node (24). When either of the lines (12, 14) is forced to a voltage above a preset voltage the corresponding transistors (22, 28) are respectively rendered conductive to discharge the node (26) which causes the transistors (30, 32) to be rendered nonconductive thereby disconnecting the lines (12, 14) from the ground node (24).

LOGIC ARRAY HAVING IMPROVED SPEED CHARACTERISTICS

An integrated circuit Read-Only Memory (ROM) with improved speed of operation is disclosed as generally representative of similarly improved logic arrays. The ROM includes parallel rows of conductors oriented normal to parallel doped regions which form column conductors. The ROM is implemented with field-effect transistors and comprises two decoder fields and a data field. The transistors of the decoder fields serve to define open circuits between adjacent column conductors in accordance with binary input signals applied to the decoder fields. In the illustrative ROM, a first column conductor is connected to a return terminal of a power supply and a second column conductor is connected to a "pull-up" circuit. The illustrative circuit provides for the connection of power supply return connections to both ends of the one column conductor and provides for the connection of pull-up circuits to both ends of the second column conductor. The row conductors are connected to gates of transistors ...

INTERLEAVED WORDLINE ARCHITECTURE

A high-density folded bitline memory array architecture is disclosed. High memory cell packing density is achieved by dividing polysilicon wordlines into short individual segments in the folded bitline scheme. Each wordline segment forms the gate of one or two DRAM memory cell transistors, and each segment is connected to a metal wordline, or conductor having low resistivity. By eliminating spaces between the memory cells due to passing wordlines, a cell arrangement and density similar to open bitline schemes is achieved. Further packing is obtained by arranging two columns of memory cells parallel to each bitline, each column offset with the other by a predetermined pitch. Therefore, by increasing the number of memory cells connected to each complementary bitline pair, each bitline pair can be cut in half and connected to its own bitline sense amplifier to reduce the bitline capacitance. Hence the memory cell architecture of the present invention occupies less area, and operates with faster ...

SEMICONDUCTOR MEMORY

Monolithische, integrierte Halbleiteranordnung

Semiconductor memory devices having signal delay controller and methods performed therein

Semiconductor Devices Having Initialization Circuits And Semiconductor Systems Including The Same

2 INTEGRATED CIRCUIT CHIP HAVING TWO TYPES OF MEMORY CELLS

SOPHISTICATED READ-ONLY STORAGE

STRUCTURE OF LOGICAL MEMORY, IN PARTICULAR FOR MRAM OR PCRAM OR RRAM.

La présente invention concerne une architecture et un procédé de lecture en parallèle et d'écriture en parallèle ou en série d'un composant électronique de mémoire basé sur une matrice bidimensionnelle de cellules unitaires de mémoire binaire à deux bornes, intégrées au sein d'une architecture de type « crossbar ». Selon l'invention, ce composant comporte des moyens logiques de sélection de colonne extérieurs à la matrice, qui activent au moins une colonne dont une ou plusieurs cellules doivent subir un traitement de lecture ou écriture. Elle concerne aussi un tel composant et procédé avec lecture de l'état des cellules par détection différentielle à partir de deux cellules de deux rangées différentes, soit entre une colonne de stockage et une colonne de référence constante, soit entre deux rangées ou deux colonnes de stockage se correspondant deux à deux. L'invention concerne aussi un tel composant dans lequel certains moyens de sélection sont dédiés exclusivement à des opérations de lecture ...

INTERGRATED CIRCUIT DEVICE AND ELECTRONIC INSTRUMENT

SEMICONDUCTOR DEVICE

2가지 타입의 메모리 셀을 가지는 집적 회로 칩

... 집적 회로 칩은 제 1 타입 메모리 셀 및 제 2 타입 메모리 셀을 포함한다. 제 1 타입 메모리 셀은 제 1 기준 라인 랜딩 패드 및 제 1 워드 라인 랜딩 패드를 포함한다. 제 1 타입 메모리 셀의 제 1 기준 라인 랜딩 패드 및 제 1 타입 메모리 셀의 제 1 워드 라인 랜딩 패드는 제 1 방향을 따라 정렬된다. 제 2 타입 메모리 셀은 제 1 방향을 따라 연장되는 제 1 기준 라인 세그먼트 및 제 1 워드 라인 랜딩 패드를 포함한다. 제 2 타입 메모리 셀의 제 1 워드 라인 랜딩 패드 및 제 2 타입 메모리 셀의 제 1 기준 라인 세그먼트는 제 1 방향과 다른 제 2 방향을 따라 이격된다.

MEMORY MODULE INCLUDING VOLTAGE SENSE MONITORING INTERFACE

... 메모리 디바이스 및 시스템은 가변 부하를 가로지르는 전압 공차를 처리하기 위한 전압 감지 라인을 포함한다. 메모리 디바이스 및 시스템은 메모리 모듈 상의 회로에 결합된 제 1 복수의 핀 및 메모리 모듈의 외부로부터 전력 레일의 모니터링을 가능화하는 메모리 모듈 상의 전력 레일에 결합된 제 2 복수의 핀을 갖는 메모리 모듈 커넥터를 포함한다.

Electrical signal supply circuit and semiconductor memory device

Semiconductor memory device and method for layout of the same

CARD TYPE RECORDING MEDIUM AND PRODUCTION METHOD THEREFOR

마이크로 전자 패키지

... 마이크로 전자 패키지(100)는 기판(102)과 마이크로 전자 요소(130)를 포함하며, 마이크로 전자 요소는 면(134)과 이 면에서 노출되는 컨택(132)의 하나 이상의 컬럼(138, 139)을 가지며, 컨택(132)이 기판의 표면(120)에서 노출되는 대응하는 컨택을 바라보고 이 컨택에 연결된다. 축면(140)은 제1 방향(142)으로 연장하는 라인을 따라 마이크로 전자 요소의 면을 교차하고, 요소 컨택(132)의 컬럼에 대하여 센터링될 수 있다. 패키지 단자의 컬럼(104A, 104B)은 제1 방향으로 연장할 수 있다. 제2 표면의 중앙 영역(112)에서 노출된 제1 단자는 마이크로 전자 요소 내의 어드레스 가능 메모리 지점을 결정하기 위해 이용할 수 있는 어드레스 정보를 전달하도록 구성될 수 있다. 중앙 영역(112)은 패키지 단자의 컬럼들 간의 최소 피치(150)의 3.5배보다 크지 않은 폭(152)을 가질 수 있다. 축면은 중앙 영역을 교차할 수 있다.

SEMICONDUCTOR MEMORY DEVICE

MEMORY DEVICE AND A MEMORY SYSTEM INCLUDING OF THE SAME, CAPABLE OF SECURING A CONTACT AREA OF BIT LINE AND A BUTTER UNIT

PURPOSE: A memory device and a memory system including of the same are provided to connect a bit line and a page buffer unit through a sub-line by forming the sub-line at a connection part between the cell array and the page buffer unit. CONSTITUTION: A memory device(100) comprises a memory cell connected to a bit line, page buffer units(131,133), and a connection unit. The connection unit is located between the memory cell and the page buffer. The connection unit connected to a bit line comprises a sub-line connecting the memory cell and page buffer unit. The memory device comprises first contacts which are formed between the memory cell and the bit line and also includes second contacts(51-56) which are formed between the bit line and the subs line. COPYRIGHT KIPO 2010 ...

이중 전압 비대칭 메모리 셀

... 메모리 내의 키퍼 셀들에 대한 비대칭 전력 전달을 가진 메모리가 제공된다. 일부 실시예들에서, 제1 및 제2 전력 전달 회로들은 별개의 제1 및 제2의 독립적으로 조정된 전력 공급들을 사용한다. 제1 공급은 메모리 구조를 위해 명목상 사용되는 공급일 수 있는 반면, 제2 공급은 제1 공급보다 낮을 수 있다. 일부 실시예들에서, 기입 동작 동안에, 제1(더 높은) 공급은 키퍼 셀 내의 논리 요소들 중 하나의 논리 요소를 위해 사용되는 반면, 제2(더 낮은) 공급은 다른 키퍼 논리 요소를 위해 사용된다.

SEMICONDUCTOR DEVICE FOR IMPROVING POWER DISTRIBUTION NETWORK

Disclosed is a semiconductor device using a part of a memory cell array region as a reservoir capacitor region. According to an embodiment of the present invention, the semiconductor device comprises: a bit line extended in a first direction; a plurality of memory cells commonly connected to the bit line; at least one reservoir cell located between the memory cells, and electrically separated from the bit line; and a first power line electrically connected to the reservoir cell. COPYRIGHT KIPO 2018 (AA) R-CAP area ...

FIRM WORDLINE ACTIVATION DELAY MONITORING CIRCUIT USING PLURALITY OF SAMPLE WORDLINES

PURPOSE: A firm wordline activation delay monitoring circuit using a plurality of sample wordlines is provided to reflect actual delay more previously in case that a wordline in a semiconductor memory is activated and to achieve a sample wordline delay monitoring circuit using a decoding circuit intimately complied with a decoding circuit of a specific selection wordline. CONSTITUTION: A multiple bank memory(10), such as a DRAM, comprises a couple of memory units(12) provided with column decoder/sense amplifiers(19). Each memory unit(12) is determined as a memory domain comprising a memory array accessed by a set of row decoder/row control circuit in a rib(14) of the multiple bank memory(10). A first memory unit(12) comprises 4 banks(16a-16d) and a second memory unit(12) and 4 banks(16e-16h). Each bank has a plurality of sub arrays(18) and is determined as a memory domain which provides access to a plurality of data words. Each sub array(18) is determined as a bank array domain divided ...

SEMICONDUCTOR MEMORY DEVICE, HAVING IMPROVED INPUT SIGNAL RECOGNITION CHARACTERISTICS

PURPOSE: A semiconductor memory device is provided to perform calibration operation by using a reference voltage outside of a chip. CONSTITUTION: A reference voltage pad(401) receives a reference voltage from the outside of a chip. Calibration resistance portions(403,411) are connected to a calibration node. The calibration resistance portion has resistance which is determined according to a calibration code. A calibration node is connected to an external resistance. Calibration code generation areas(405,417) compare a voltage with a reference voltage of the calibration node. The calibration code generation area generates the calibration code. COPYRIGHT KIPO 2010 ...

NONVOLATILE MEMORY DEVICE OF A VERTICAL STRUCTURE INCLUDING A MEASUREMENT STRUCTURE

PURPOSE: A nonvolatile memory device of a vertical structure is provided to improve reliability by accurately controlling a position of the end of a gate line of a memory cell string. CONSTITUTION: A nonvolatile memory device(1000) includes a cell array region and a connection region. A cell array region is defined on a substrate(100). A dummy pattern is located in the edge of the cell array region. A plurality of conductive lines cover the dummy pattern and are vertically laminated on the substrate. The conductive lines are extended to expose the position of the dummy pattern in at least one extension direction. COPYRIGHT KIPO 2012 ...

SEMICONDUCTOR MEMORY

PURPOSE: To provide a semiconductor memory in which power consumption can be reduced while reducing wiring regions. CONSTITUTION: This semiconductor memory is constituted by arranging blocks 10 having a plurality of sections operated independently mutually in the direction of X (column) and Y (row) of a chip respectively. Each section 1 has a cell group consisting of a plurality of memory cells 11, a section selecting circuit 12, a word line selecting circuit 13, a column selecting circuit 14, a sense amplifier 15, a write circuit 16. As at least part of signals transmitted and received between a decoder control circuit 3 and each section 1 is transmitted to each section 1 using a wiring W1 extending in the direction of X from the decoder control circuit 3 and a wiring W2 orthogonally intersecting with this wiring W1 and passing over the section, the number of wirings arranged between sections 1 in Y direction can be reduced, while adjacent sections 1 can be arranged near the Y direction ...

Circuit structure and method of manufacturing the same

System in package structure, electroplating module thereof and memory storage device

A system in package (SIP) structure, an electroplating module thereof and a memory storage device are provided. The SIP structure includes a first layout layer, a second layout layer and a rewritable non-volatile memory module. The first layout layer includes a first pad and a wire. The first pad is close to a first side of the first layout layer, and the first pad is configured to couple to a grounding voltage. One terminal of the wire is coupled to the first pad, and another terminal of the wire is coupled to an opening of the SIP structure, wherein the opening is located at a second side of the first layout layer opposite to the first side, and the opening is configured to couple to an external voltage.

Reservoir capacitor and semiconductor memory device including the same

A reservoir capacitor includes a first power supply unit and a second power supply unit, and at least two large-capacity capacitors connected in series between the first and second power supply units.

Array structural design of magnetoresistive random access memory (MRAM) bit cells

Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cells are disclosed. The bit cells include a source line formed in a first plane and a bit line formed in a second plane. The bit line has a longitudinal axis that is parallel to a longitudinal axis of the source line, and the source line overlaps at least a portion of the bit line.

Pyridinyl amides for the treatment of CNS and metabolic disorders

The present invention relates to novel pyridinyl derivatives of Formula wherein Y, Z, L, R1 through R11, n, m, p, q, t are as defined herein, that are 5-HT receptor ligands, particularly the 5-HT6 subtype, and as such are useful for treating diseases wherein modulation of 5-HT activity is desired. The present invention relates to novel pyridinyl derivatives including their pharmaceutically acceptable salts. The invention also relates to processes for the preparation of, intermediates used in the preparation of, pharmaceutical compositions containing and the uses of such compounds in treating diseases of the central nervous system such as schizophrenia.

Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate

A microelectronic package 100 includes a microelectronic element 101 having a memory storage array. Terminals 104 on a surface 110 of a substrate 102 are configured for connection to an external component. Substrate contacts 121 exposed at an opposite surface 108 of the substrate 102 face and are joined to element contacts 111 of the microelectronic element 101. The terminals can include first terminals 104 arranged at positions within first and second sets 114, 124 thereof disposed on respective opposite sides of a theoretical axis 132. Each set of first terminals 104 can be configured to carry address information usable by circuitry within the microelectronic package 100 to determine an addressable memory location in the memory storage array. The signal assignments of the first terminals 104 in the first set 114 can be a mirror image of the signal assignments of the first terminals in the second set 124.

Memory system design for signal integrity crosstalk reduction with asymmetry

An integrated circuit is described. The integrated circuit (IC) may include a printed circuit board (PCB). The IC may also include a system on chip (SoC) die on the PCB. The IC may further include a memory device coupled to a parallel memory interface of the SoC die. The memory device may be coupled to a parallel memory interface through parallel signal traces arranged in an asymmetric routing. In the asymmetric routing of the parallel signal traces, the signal traces are arranged according to a variable spacing is between the parallel signal traces for a majority portion of the parallel signal traces.

Semiconductor device

Memory circuits and routing of conductive layers thereof

Stub minimization for multi-die wirebond assemblies with parallel windows

HIGH ENDURANCE NON-VOLATILE STORAGE

A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.

DRAM MEMORY INTERFACE

It is proposed a DRAM memory interface (40) for transmitting signals between a memory controller device (50) and a DRAM memory device (52). The DRAM memory interface comprises: data lines (44) for transmitting data signals; one or more control line(s) for transmitting control signals; one or more address line(s) for transmitting address signals; for each line, a transmitter device (41) connected to a first end of the line and a receiver device (42) connected to a second end of the line; wherein: each line is a single ended line wherein a signal transmitted on the line is referenced to a first reference voltage line (46); and - each line has an termination (Z1, Z2) on both the first and second ends of the line by connecting a first impedance (Z1) to the first end of the line and a second impedance (Z2) to the second end of the line.

256 Meg DYNAMIC RANDOM ACCESS MEMORY

Abstract not available! Abstract of correspondent: US6710630 A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded ...

MULTIPLE TURN FOR CONDUCTIVE LINE PROGRAMMING MRAM

A conductive line (20) for programming a magnetoresistive memory element (10) comprising N metal layers (17,19) separated by an electrically insulator layer (21), wherein the bit conductive is positioned proximate to a magnetoresistive memory device and flows a current that induces a magnetic field for programming the magnetoresistive memory device. The current needed to induce a given magnetic field is reduced by a factor of N, wherein N is a whole number greater than or equal to two. To further decrease the current, the conductive line is cladded with a ferromagnetic region (24) to increase the magnetic field proximate to the magnetoresistive random access memory device.

STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE

A microelectronic package (100) can include a substrate (102) and a microelectronic element (130) having a face (134) and one or more columns (138, 139) of contacts (132) exposed thereat which face and are joined to corresponding contacts exposed at a surface (120) of the substrate. An axial plane (140) may intersect the face along a line in a first direction (142) and centered relative to the columns of element contacts (132). Columns (104A, 104B) of package terminals can extend in the first direction. First terminals exposed at a central region (112) of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region (112) may have a width (152) not more than three and one-half times a minimum pitch (150) between the columns of package terminals. The axial plane can intersect the central region.

SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

Provided is a semiconductor device which can achieve a reduction in its area, reduction in power consumption, and operation at a high speed. A semiconductor device 10 has a structure in which a circuit 31 including a memory circuit and a circuit 32 including an amplifier circuit are stacked. With this structure, the memory circuit and the amplifier circuit can be mounted on the semiconductor device 10 while the increase in the area of the semiconductor device 10 is suppressed. Thus, the area of the semiconductor device 10 can be reduced. Further, the circuits are formed using OS transistors, so that the memory circuit and the amplifier circuit which have low off-state current and which can operate at a high speed can be formed. Therefore, a reduction in power consumption and improvement in operation speed of the semiconductor device 10 can be achieved.

MEMORY ARRAY WITH GRADED MEMORY STACK RESISTANCES

Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.

Operations with logical states from a four voltage level signal

Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.

VHSA-VDDSA generator merging scheme

A memory device is provided including physical block circuitry including a first lateral network arrangement and a second lateral network arrangement. Each of the first and second lateral network arrangements includes a single generator configured to output both a sense amplifier voltage VHSA and a data latch voltage VDDSA, in each of a first mode and a second mode. In the first mode, during which read and program verify and other operations may occur, the generator receives VHSA as a feedback signal and in the second mode, during which programming, POR, and EVFY operations may occur, the generator receives VDDSA as a feedback signal.

System and method for optimizing interconnections of memory devices in a multichip module

An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have the same propagation time regardless of which device is involved. The hub receives memory signals from a controller over a high speed data link which the hub translates into electrical data, command and address signals. These signals are applied to the memory devices over busses having equivalent path lengths. The busses may also be used by the memory devices to apply data signals to the memory hub. Such data signals can be converted by the memory hub into memory signals and applied to the controller over the high speed data link. In one example, the memory hub is located in the center of the memory module.

MEMORY SYSTEM

A memory system includes a first substrate including a first signal terminal and a second signal terminal electrically connected to a bus, a first circuit in which a first switching element and a first resistor are connected in series between a first terminal and a second terminal, the first terminal connected to the first signal terminal, a second circuit in which a second switching element and a second resistor are connected in series between a third terminal and a fourth terminal, the third terminal connected to the second signal terminal, a first memory electrically connected to the second terminal, a second memory electrically connected to the fourth terminal, and a controller electrically connected to the bus and configured to control the first and second switching elements.

MEMORY CARD AND SD CARD

According to one embodiment, there are provided a memory which is provided on a circuit board, a controller which is provided on the circuit board and controls the memory, and a signal line which is formed on the circuit board and configured to perform data transmission between the controller and the memory, in which a width of the signal line in the place where the signal line is led out from the memory is large compared with a place disposed under the memory.

NONVOLATILE SEMICONDUCTOR MEMORY HAVING A WORD LINE BENT TOWARDS A SELECT GATE LINE SIDE

A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.

Memory module and memory configuration with stub-free signal lines and distributed capacitive loads

In a memory module for a memory configuration having a bus system made up of a plurality of signal lines, each signal line has respectively been produced essentially without any stub continuously from a supplying contact device to a discharging contact device, disposed close to the supplying contact device, in order to increase a maximum data transmission rate within the memory configuration. Between the supplying contact device and the discharging contact device, each of the signal lines is routed in succession at minimum distances via connection elements associated with the signal line on memory chips associated with the signal line.

Semiconductor integrated circuit

In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. An imbalance in data line-word line means generation of large noise when the data lines are subjected to amplification, which is highly likely invite deterioration of very small signals on the data lines and erroneous amplification of data. One or a few each of a plurality of word lines connected to a plurality of memory cells connected to one data line are alternately connected to subword driver arrays arranged on the opposing sides of a memory array. Positive and negative word line noise components cancel each other in the subword drivers when the data lines are subjected to amplification, so that the word line noise can be reduced. Therefore, signals read out by sense amplifiers can be prevented from deterioration thereby to increase the reliability of memory operation.

MEMORY SYSTEM INCLUDING A POWER DIVIDER ON A MULTI MODULE MEMORY BUS

A memory system includes a memory controller, a transmission bus, a power divider, a first memory chip, and a second memory chip. The transmission bus is coupled from the memory controller to a first node of the power divider for transferring signals. The first node of the power divider is coupled to a second node of the power divider via a first line, and the first node is also coupled to a third node of the power divider via a second line. The first memory chip is coupled to the second node via a first branch bus and the second memory chip is coupled to the third node via a second branch bus. Accordingly, reflected wave due to an impedance mismatching can be reduced to enhance the signal integrity.

Integrated circuit device

The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data ...

Method and apparatus providing non-volatile memory with reduced cell capacitive coupling

A flash memory architecture that provides a mechanism for reducing floating gate to floating gate coupling. The floating gates of the memory cells are shifted, either vertically or horizontally thereby offsetting the floating gates of the memory cells to an intervening space between the gates of adjacent memory cells. The shift of the floating gates decreases the floating gate to floating gate coupling.

Semiconductor memory device including memory cells connected to a ground line

A memory cell array in a static random access memory (SRAM) includes an improved circuit. Memory cells in one row are connected to a ground line. The memory cells in another row are connected to the ground line. Word lines each are connected alternately to the memory cells of two rows column by column. In a read operation, when one of the word lines is activated, a current flows from the memory cell to the two ground lines. Since a total of currents flowing through one ground line is reduced, the rise of potentials of the ground lines is prevented, so that destruction of data can be prevented.

Semiconductor memory

A semiconductor memory having a structure wherein each of data lines intersecting word lines is divided into a plurality of sub lines in its lengthwise direction, memory cells are arranged at the points of intersection between the divided sub lines and the word lines, common input/output lines are disposed in common to a plurality of such sub lines, the common input/output lines and the plurality of sub lines are respectively connected by switching elements, and the switching elements are connected to a decoder through control lines and are selectively driven by control signals generated from the decoder.

Semiconductor integrated circuit device with oblique metallization lines over memory bit and word lines

The present invention discloses a semiconductor integrated circuit device. This semiconductor integrated circuit has metal wiring layers of four levels including peripheral circuits of a memory module which are formed by word and bit lines in a lattice arrangement. The word lines are provided in the first-level metal wiring layer and the bit lines are provided in the second-level metal wiring layer. Provided in the third-level metal wiring layer is a first over-memory wire without direct access to any memory cell. A second over-memory wire without direct access to any memory cell is provided in the fourth-level metal wiring layer. The first and second over-memory wires for establishing connections between functional circuit blocks, are arranged in such a way that they extend across the word lines and the bit lines at an angle of 45 degrees.

Wafer scale integration device with dummy chips and relay pads

A wafer scale integration device comprises a plurality of real chips formed in the center portion of a wafer and a plurality of dummy chips formed in the circumference of the wafer. The dummy chips only include relay pads, some of the relay pads are used for relaying bonding wires of power supply lines. Consequently, the power supply lines do not short-circuit at edge portions of the wafer, since a length of the bonding wire at the edge portion of the wafer becomes short due to the relay pad connected to the bonding wire.

Electronic apparatus with an oxide-only tunneling structure by a select gate tier, and related methods

A vertical structure extends through a tiered structure of alternating conductive and insulative materials. The vertical structure includes a channel structure and a tunneling structure. At least one of the conductive materials of the tiered structure provides a select gate tier (e.g., including a control gate for a select gate drain (SGD) transistor). Adjacent the select gate tier of the tiered structure, the tunneling structure consists of or consists essentially of an oxide-only material. Adjacent the word line tiers of the tiered structure, the tunneling structure comprises at least one material that is other than an oxide-only material, such as a nitride or oxynitride. The oxide-only material adjacent the select gate tier may inhibit unintentional loss of charge from a neighboring charge storage structure, which may improve the stability of the threshold voltage (Vth) of the select gate tier.

Architecture of three-dimensional memory device and methods regarding the same

Architectures of 3D memory arrays, systems, and methods regarding the same are described. An array may include a substrate arranged with conductive contacts in a geometric pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, a sacrificial layer may be deposited in a trench that forms a serpentine shape. Portions of the sacrificial layer may be removed to form openings, into which cell material is deposited. An insulative material may be formed in contact with the sacrificial layer. The conductive pillars extend substantially perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. A chalcogenide material may be formed in the recesses partially around the conductive pillars.

Semiconductor integrated circuit having a unit cell including NMOS and PMOS transistors

A semiconductor integrated circuit having a core region and an I/O region includes a clock signal line for transferring a clock signal, basic unit cells and pull-up unit cells. The basic unit cells are arranged in rows and columns within the core region. Each of the basic unit cells has a PMOS active region and an NMOS active region. The pull-up unit cells are arranged at predetermined intervals between the basic unit cells. The pull-up unit cells are coupled to the signal line for pulling up an electric level of the clock signal line in response to the clock signal.

DUAL PORT MEMORY CELL WITH IMPROVED ACCESS RESISTANCE

The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

Synchronous DRAM modules including multiple clock out signals for increasing processing speed

Additional clock-outs are included on DRAMs in a multiple Dual In-Line Module Memory (DIMM) system having DRAMs of different data widths. The additional clock-outs balance the loads seen by the DRAM clock-out and data-out, thereby reducing signal skew between the DRAM data and clock lines. Additionally, in a second embodiment, every other clock line in a series of DRAMs comprising a DIMM are left unconnected. The data from the non connected DRAMs is clocked using the clock line of its neighbor.

Semiconductor integrated circuit device

The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

Method and apparatus for read bitline clamping for gain cell DRAM devices

A dynamic random access memory (DRAM) storage device includes a storage cell having a plurality of transistors arranged in a gain cell configuration, the gain cell coupled to a read bitline and a write bitline. A dummy cell is configured as a clamping device for the read bitline, wherein the dummy cell opposes a read bitline voltage swing during a read operation of the storage cell.

Signal propagating device for a plurality of memory cells

There is provided a signal propagating device for receiving an input signal at an input end thereof and supplying the input signal to a plurality of memory cells arranged in one row. The signal propagating device includes a word line connected to transmit the input signal and having a plurality of line segments electrically coupled to the memory cells. A preceding one of the line segments is formed to have a larger average width than a succeeding one of the line segments.

Dynamic impedance control for input/output buffers

A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.

Semiconductor memory apparatus having sense amplifier

Disclosed is a semiconductor memory apparatus comprising an upper mat and a lower mat with a sense amplifier array region in between, where the sense amplifier array region includes a plurality of sense amplifiers. There is also a plurality of bit lines configured to extend toward the sense amplifier array region from the upper mat, and a plurality of complementary bit lines configured to extend toward the sense amplifier array region from the lower mat. Bit lines of the upper mat and complementary bit lines of the lower mat are configured to be alternately disposed at a predetermined interval in the sense amplifier array region, and the sense amplifier is configured to be formed between a bit line and a corresponding complementary bit line.

Semiconductor device and method for driving semiconductor device

A semiconductor device with a novel structure is provided, in which the operation voltage is reduced or the storage capacity is increased by reducing variation in the threshold voltages of memory cells after writing. The semiconductor device includes a plurality of memory cells each including a transistor including an oxide semiconductor and a transistor including a material other than an oxide semiconductor, a driver circuit that drives the plurality of memory cells, and a potential generating circuit that generates a plurality of potentials supplied to the driver circuit. The driver circuit includes a data buffer, a writing circuit that writes one potential of the plurality of potentials into each of the plurality of memory cells as data, a reading circuit that reads the data written into the memory cells, and a verifying circuit that verifies whether the read data agrees with data held in the data buffer or not.

Sub word line driver and apparatuses having the same

A sub word line driver is provided. The sub word line driver includes a first layer including a plurality of first pads disposed in a first line of a first direction, a plurality of second pads arranged in a second line of the first direction, and two first word lines arranged twisted twice in the first direction between the plurality of first pads and the plurality of second pads, each of the two first word lines being connected to a corresponding pad among the plurality of second pads; and a second layer, which is formed at a lower part of the first layer, and includes the second layer including a plurality of third pads, each the plurality of third pads each being embodied disposed at each corresponding a position corresponding to a pad from among one of the plurality of first pads and the plurality of second pads.

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device includes: a memory cell array including plural first lines, plural second lines, and plural memory cells each including a variable resistance element; a first decoder connected to at least one ends of the plurality of first lines and configured to select at least one of the first lines; at least one pair of second decoders connected to both ends of the plurality of second lines and configured such that one of the pair of second decoders is selected for selecting the second lines according to a distance between the one of the first lines selected by the first decoder and the both ends of the second lines; and a voltage application circuit configured to apply a certain voltage between the first line and the second line selected by the first decoder and the second decoder.

Semiconductor device

A semiconductor device includes: an interface chip including a read timing control circuit that outputs, in response to a command signal and a clock signal supplied from the outside, a plurality of read control signals that are each in synchronization with the clock signal and have different timings; and core chips including a plurality of internal circuits that are stacked on the interface chip and each perform an operation indicated by the command signal in synchronization with the read control signals. According to the present invention, it is unnecessary to control latency in the core chips and therefore to supply the clock signal to the core chips.

Semiconductor device having pull-up circuit and pull-down circuit

To reduce power supply noises occurring in a control circuit unit for controlling an output buffer. A semiconductor device includes unit buffers for driving a data output terminal, impedance control circuits for controlling the unit buffers, and a control circuit unit for controlling the impedance control circuits. The impedance control circuits and the control circuit unit operate by mutually-different power supplies, the control circuit unit supplies pull-up data and pull-down data in mutually reverse phase to the impedance control circuits, and the impedance control circuits convert the pull-up data and the pull-down data from reverse phase to in-phase and supply the same to the unit buffers. Thereby, a noise is difficult to occur in a power supply VDD used for the control circuit unit.

Semiconductor memory device

A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.

Semiconductor device having data bus

A semiconductor device is disclosed which comprises a first wiring layer, a second wiring layer formed over the first wiring layer, data input/output terminals, and a data bus formed in the first and second wiring layers. The data bus includes N data lines transmitting data between a predetermined circuit and the input/output terminals. M first data lines among the N data lines have a length shorter than a predetermined length and residual N-M second data lines have a length longer than the predetermined length. Shield lines adjacent to the N data lines are formed in the first and second layers. The N data lines are arranged at positions at which the data lines do not overlap one another in a stacking direction of the first and second wiring layers.

Memory Modules and Devices Supporting Configurable Core Organizations

Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey width selection information to configurable memory apparatus and support point-to-point data interfaces for multiple width configurations.

Semiconductor device

A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array area including a cell area including nonvolatile semiconductor memory cells, linear wirings extending from inside of the cell area to an area outside the cell area, and lower layer wirings in a lower layer than the linear wirings in the boundary area and electrically connected to the linear wirings, and wiring widths of the lower layer wirings being larger than widths of the linear wirings, the peripheral circuit area including a patterns electrically connected to the linear wirings via the lower layer wirings, the boundary area failing to be provided with the linear wirings and a wiring in same layer as the linear wirings.

Nonvolatile semiconductor memory having a word line bent towards a select gate line side

A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.

Semiconductor device including plural chips stacked to each other

Such a device is disclosed that includes first and second chips stacked to each other, and a third chip controlling the first and second chips, stacked on the first and second chips, and including first, second and third output circuits. The first output circuit supplies a first command signal to the first chip. The second output circuit supplies the first command signal to the second chip. The third output circuit supplies a second command signal to the first and second chips.

Utilizing two algorithms to determine a delay value for training ddr3 memory

A method for training an electronic memory may include receiving a first delay value and a second delay value. The first delay value and the second delay value may be associated with a first data strobe indicating when to sample data on a first memory lane of the electronic memory. The method may also include determining a difference between the first delay value and the second delay value. The method may further include receiving a third delay value associated with a second data strobe indicating when to sample data on a second memory lane of the electronic memory. The method may also include determining a fourth delay value for the second memory lane of the electronic memory utilizing the third delay value and the determined difference between the first delay value and the second delay value.

Field side sub-bitline nor flash array and method of fabricating the same

Field Side Sub-bitline NOR-type (FSNOR) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor Non-Volatile Memory (NVM) cells in a NOR-type flash array of the invention. Each field side sub-bitline is connected to a main metal bitline through a contact at its twisted point in the middle. Because there are no contacts in between the linked NVM cells' electrodes in the NOR-type flash array of the invention, the wordline pitch and the bitline pitch can be applied to the minimum geometrical feature of a specific technology node. The NOR-type flash array of the invention provides at least as high as those in the conventional NAND flash array in cell area density.

Semiconductor memory device

A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

Fly-over conductor segments in integrated circuits with successive load devices along a signal path

The propagation delay of a signal through multiple load devices coupled sequentially along a conductor is improved by separating a subset of the load devices that is more distant from the signal source, and coupling the more distant subset to the signal through a fly-over conductor that bypasses the subset that is nearer to the signal source. The technique is applicable to subsets of bit cells in a random access memory (SRAM) coupled to a given word line, or to word line decoder gates coupled sequentially to a strobe signal, as well as other circuits wherein load devices selectable as a group can be divided into subsets by proximity to the signal source. In an SRAM layout with multiple levels, different metal deposition layers carry the conductor legs between the load devices versus the fly-over conductor bypassing the nearer subset.

Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate

A microelectronic package can include a microelectronic element having a face and a plurality of element contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with at least one external component. The substrate can have substrate contacts on the first surface facing the element contacts of the microelectronic element and joined thereto. The terminals can include first terminals arranged at positions within first and second parallel grids. The first terminals of each grid can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. The signal assignments of the first terminals in the first grid can be a mirror image of the signal assignments of the first terminals in the second grid.

Novel semiconductor device and structure

A semiconductor device, including: a first semiconductor layer including first transistors, wherein the first transistors are interconnected by at least one metal layer including aluminum or copper; and a second mono-crystallized semiconductor layer including second transistors and overlaying the at least one metal layer, wherein the at least one metal layer is in-between the first semiconductor layer and the second mono-crystallized semiconductor layer, wherein the second mono-crystallized semiconductor layer is less than 100 nm in thickness, and wherein the second transistors include horizontally oriented transistors.

Semiconductor device

Memory cells adjacent to each other in a second direction are formed in a first p-type well region, a first n-type well region, and a second p-type well region arranged in a first direction. Each memory cell includes a first transfer transistor and a first driver transistor formed in the first p-type well region, a second transfer transistor and a second driver transistor formed in the second p-type well region, and first and second load transistors formed in the first n-type well region. In an SRAM, gate electrodes of the first and second transfer transistors of the memory cells adjacent to each other in the second direction are electrically connected to first and second word lines, respectively. The first and second word lines are electrically connected to the first and second p-type well regions, respectively.

Device

A semiconductor device includes a first controlled chip and a control chip stacked therewith. The first controlled chip includes a first circuit outputting a data signal in response to a synchronization signal, an input/output circuit outputting the data signal to a data terminal in synchronization with a delayed synchronization signal, and a replica circuit replicating an output circuit and outputting a replica signal to a first replica terminal in synchronization with the delayed synchronization signal. The control chip includes a first control circuit outputting a synchronization signal and receiving a data signal, a delay adjustment circuit delaying the synchronization signal and outputting the same as a delayed synchronization signal, a phase comparator circuit comparing the phases of the replica signal and the synchronization signal, and a delay control circuit controlling the delay amount of the delay adjustment circuit based on a comparison result of the phase comparator circuit.

Semiconductor storage device

According to one embodiment, a semiconductor storage device includes a stripe, a sense amplifier, a global signal line, and a controller. Blocks are in the stripe. The blocks are formed in a first direction. Each of blocks is made a read unit of data and includes a memory cell capable of holding the data provided along a row and a column. The sense amplifier is provided just under each of the blocks, and reads the data. The global signal line is formed so as to penetrate through the stripe in the first direction, and transfers the data read from the block to the sense amplifier. The controller controls a value of a reference current applied to the sense amplifier according to positional relationship between each area in which the sense amplifier is arranged and the block, which is made a read target of the data, out of the blocks.

Method for implementing spare logic of semiconductor memory apparatus and structure thereof

A method for implementing a spare logic of a semiconductor memory apparatus includes the steps of: forming one or more contact conductive layers, which are independent, in a power line and an active area, respectively; and performing metal programming on the contact conductive layers formed in the power line and the active area to electrically couple the independent contact conductive layers formed in the power line and the active area.

SEMICONDUCTOR DEVICE HAVING MULTI-LEVEL WIRING STRUCTURE

Disclosed herein is a device that includes a multi-level wiring structure including a first wiring layer and a second wiring layer formed over the first wiring layer; a memory cell array area including a plurality of memory cells, a plurality of sense amplifiers and a plurality of sub amplifiers; a main amplifier area including a plurality of main amplifiers, the memory cell array area and the main amplifier area being arranged in line in a first direction; and a plurality of first I/O lines each connecting an associated one of the sub amplifiers to an associated one of the main amplifiers, each of the first I/O lines including first and second wiring portions that are elongated in the first direction, the first wiring portion being formed as the first wiring layer and the second wiring portion being formed as the second wiring layer. 1. A semiconductor device comprising:a memory mat including a plurality of memory cells;a sense amplifier located in a sense amplifier area and amplifying data supplied from the memory cells to generate first amplified data;a main amplifier that amplifies the first amplified data supplied from the sense amplifier;a main I/O line extends in a first direction to connect the sense amplifier to the main amplifier, the main I/O line including a first section provided over the memory mat as a first wiring layer and the second section provided over the sense amplifier area as a third wiring layer different from the first wiring layer; anda power-supply line provided as the third wiring layer such that the power-supply line overlaps with the first section of the main I/O line.2. The semiconductor device as claimed in claim 1 , wherein the third wiring layer is over the first wiring layer.3. The semiconductor device as claimed in claim 2 , further comprising a local I/O line provided over the sense amplifier area and extending in a second direction crossing the first direction to connect the sense amplifier to the main I/O line claim 2 ,wherein ...

Memory having isolation units for isolating storage arrays from a shared i/o during retention mode operation

A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.

MEMORY DEVICE COMPRISING PROGRAMMABLE COMMAND-AND-ADDRESS AND/OR DATA INTERFACES

A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins. 1. A memory device , comprising:a first and second command-and-address (CA) interface; and select an operational mode, wherein both the first and second CA interfaces are active in a first operational mode, and wherein only one of the first or second CA interface is active in a second operational mode, and', 'select the first or second CA interface as the active CA interface in the second operational mode., 'circuitry to2. The memory device of claim 1 , wherein the memory device is capable of supporting multiple microthreads in the first operational mode claim 1 , and wherein the memory device is capable of supporting only a single microthread in the second operational mode.3. The memory device of claim 1 , wherein the circuitry is capable of selecting the operational mode based on:one or more bits in one or more registers,one or more signals received on one or more pins, ora combination of one or more bits in one or more registers and one or more signals received on one or more pins.4. The memory device of claim 1 , wherein the circuitry is capable of selecting the first or second CA interface as the active ...

High current capable access device for three-dimensional solid-state memory

The present invention generally relates to three-dimensional arrangement of memory cells and methods of addressing those cells. The memory cells can be arranged in a 3D orientation such that macro cells that are in the middle of the 3D arrangement can be addressed without the need for overhead wiring or by utilizing a minimal amount of overhead wiring. An individual macro cell within a memory cell can be addressed by applying three separate currents to the macro cell. A first current is applied to the memory cell directly. A second current is applied to the source electrode of the MESFET, and a third current is applied to the gate electrode of the MESFET to permit the current to travel through the channel of the MESFET to the drain electrode which is coupled to the memory element.

Variable resistance memory device having equal resistances between signal paths regardless of location of memory cells within the memory array

A memory device including variable resistance elements comprises a plurality of memory cells configured to store data; a first signal transmission/reception unit and a second signal transmission/reception unit configured to transmit a signal to the memory cells or receive a signal from the memory cells; a first transmission line arranged to couple first ends of the memory cells to the first signal transmission/reception unit; and a second transmission line configured to couple second ends of the memory cells to the second signal transmission/reception unit, wherein a first resistance of a first signal path coupled between the first and second signal transmission/reception units through a first memory cell of the memory cells is substantially equal to a second electrical resistance of a second signal path coupled between a second memory cell and the first and second signal transmission/reception units through a second memory cell of the memory cells.

SEMICONDUCTOR DEVICE

Disclosed herein is a semiconductor device including a multi-level wiring structure that includes a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level and upper-level wirings. The device further includes a plurality of bit lines for a plurality of memory cells, and each of the bit lines includes a first portion that is formed as the lower-level wiring and a second portion that is electrically connected in series to the first portion and formed as the upper-level wiring. 1. A semiconductor device comprising:a first memory mat comprising a plurality of first memory cells;a second memory mat comprising a plurality of second memory cells;a first global bit line extending over the first memory mat and the second memory mat; anda multi-level wiring structure comprising a lower-level wiring, an upper-level wiring, and an interlayer insulation film between the lower-level wiring and the upper-level wiring;the first global bit line comprising a first portion over the first memory mat and a second portion over the second memory mat, the first portion being formed as the lower-level wiring, and the second portion being formed as the upper-level wiring.2. The semiconductor device as recited in claim 1 , wherein the first memory mat comprises a first local bit line connected to the plurality of first memory cells and a first switching element connected between the first local bit line and the first global bit line claim 1 , andthe second memory mat comprises a second local bit line connected to the plurality of second memory cells and a second switching element connected between the second local bit line and the first global bit line.3. The semiconductor device as recited in claim 1 , wherein the first global bit line comprises a contact plug penetrating the interlayer insulation film to connect the first portion and the second portion to each other.4. The semiconductor device as recited in claim 1 , wherein:the first memory mat ...

Apparatus for High Speed ROM Cells

A ROM cell comprises a first first-level contact formed on a first active region of a transistor of a memory cell, a second first-level contact formed on a second active region of the transistor of the memory cell, wherein the second first-level contact is coupled to a first VSS line and a second VSS line formed in a first interconnect layer, wherein the second VSS line is electrically coupled to the first VSS line, and wherein the second VSS line is of a direction orthogonal to a direction of the first VSS line. The ROM cell further comprises a first bit line formed in the first interconnect layer, wherein the first bit line is formed in parallel with the second VSS line and a second bit line formed in the first interconnect layer, wherein the second bit line is formed in parallel with the second VSS line.

Semiconductor device having auxiliary power-supply wiring

Disclosed herein is a semiconductor device that includes a signal wiring arranged on a first layer and extending over the circuit block or blocks in the first direction so as to reach the first circuit block and produce a free space above the first circuit block, the signal wiring being electrically connected to the first circuit block, a power-supply wiring arranged on a second layer and extending over the circuit block or blocks in the first direction so as to reach the first circuit block, the power-supply wiring supplying an operating voltage to the first circuit block and an auxiliary power-supply wiring being configured to enhance the operating voltage supplied by the power supply line, and the auxiliary power-supply wiring being formed in the free space produced by the arrangement of the signal wiring.

Memory device from which dummy edge memory block is removed

A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.

Wordline Coupling Reduction Technique

A semiconductor memory includes a memory array having memory cells coupled to wordlines and bitlines. Each wordline has a left end and an opposing right end. A first wordline in every two adjacent wordlines has its left end connected to a left row driver and its right end connected to a right clamp circuit, and a second wordline in every two adjacent wordlines has its right end connected to a right row driver and its left end connected to a left clamp circuit, such that when the right clamp circuits are activated, the right clamp circuits clamp the corresponding wordline ends to a predetermined potential, and when the left clamp circuits are activated, the left clamp circuits clamp the corresponding wordline ends to the predetermined potential.

Interlayer communications for 3d integrated circuit stack

Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.

Memory Arrays

Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F 2 .

SEMICONDUCTOR DEVICE HAVING BIT LINE HIERARCHICALLY STRUCTURED

Disclosed herein is a semiconductor device that includes a plurality of memory cells; a local bit line coupled to the memory cells; a global bit line; and a first switch circuit coupled between the global bit line and the local bit line, the first switch circuit electrically connecting the local bit line to the global bit line when at least one of first and second control signals is in an active state, and the first switch circuit electrically disconnecting the local bit line to the global bit line when both of the first and second control signals are in an inactive state. 1. A semiconductor device comprising:a plurality of memory cells;a local bit line coupled to the memory cells;a global bit line; anda first switch circuit coupled between the global bit line and the local bit line, the first switch circuit electrically connecting the local bit line to the global bit line when at least one of first and second control signals is in an active state, and the first switch circuit electrically disconnecting the local bit line to the global bit line when both of the first and second control signals are in an inactive state.2. The semiconductor device as claimed in claim 1 , further comprising first and second switch drivers respectively generating the first and second control signals.3. The semiconductor device as claimed in claim 2 , wherein the first and second switch drivers are commonly controlled based on a third control signal.4. The semiconductor device as claimed in claim 2 , wherein the first switch circuit includes first and second transistors coupled in parallel between the global bit line and the local bit line claim 2 , and the first and second control signals are respectively supplied to control electrodes of the first and second transistors.5. The semiconductor device as claimed in claim 2 , wherein the first switch circuit includes a third transistor coupled between the global bit line and the local bit line claim 2 , and the first and second control ...

SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE

A semiconductor device having hierarchical bit lines is disclosed, which comprises: a first global bit line; first and second local bit lines coupled in common to the first global bit line; first and second power lines; a first transistor coupled between the first local bit line and the first power line; a second transistor coupled between the second local bit line and the second power line; a third transistor coupled between the first and second power lines. 1. A device comprising:a first global bit line;first and second local bit lines coupled in common to the first global bit line;first and second power lines;a first transistor coupled between the first local bit line and the first power line;a second transistor coupled between the second local bit line and the second power line; anda third transistor coupled between the first and second power lines.2. The device as claimed in claim 1 , wherein the third transistor receives a test signal at a control electrode thereof.3. The device as claimed in claim 1 , further comprising first and second power generators coupled respectively to the first and second power lines.4. The device as claimed in claim 3 , wherein each of the first and second power generators is supplied with first and second power supply voltages claim 3 , configured to generate a precharge voltage and configured to supply one of the first and second power supply voltages and the precharge voltage to a corresponding one of the first and second power lines.5. The device as claimed in claim 4 , further comprising a reference voltage generator configured to produce a reference voltage and to supply the reference voltage in common to the first and second power generator claim 4 , and wherein each of the power generators generates the precharge voltage in response to the reference voltage.6. The device as claimed in claim 4 , wherein the precharge voltage is substantially half level between the first and second power supply voltages.7. The device as ...

SEMICONDUCTOR DEVICE AND DRIVING METHOD OF SEMICONDUCTOR DEVICE

To provide a semiconductor device including a volatile memory which achieves high speed operation and lower power consumption. For example, the semiconductor device includes an SRAM provided with first and second data holding portions and a non-volatile memory provided with third and fourth second data holding portions. The first data holding portion is electrically connected to the fourth data holding portion through a transistor. The second data holding portion is electrically connected to the third data holding portion through a transistor. While the SRAM holds data, the transistor is on so that both the SRAM and the non-volatile memory hold the data. Then, the transistor is turned off before supply of power is stopped, so that the data becomes non-volatile. 1. A semiconductor device comprising a plurality of memory elements arranged in matrix: a first memory, the first memory comprising a first data holding portion and a second data holding portion; and', 'a second memory, the second memory comprising a third data holding portion and a fourth data holding portion,', 'wherein the first data holding portion is electrically connected to a first bit line through a first transistor,', 'wherein the second data holding portion is electrically connected to a first inverted bit line through a second transistor,', 'wherein a first word line is electrically connected to each of a gate of the first transistor and a gate of the second transistor,', 'wherein the third data holding portion is electrically connected to the second data holding portion through a third transistor,', 'wherein the fourth data holding portion is electrically connected to the first data holding portion through a fourth transistor,', 'wherein a second word line is electrically connected to each of a gate of the third transistor and a gate of the fourth transistor,', 'wherein the third data holding portion is electrically connected to one electrode of a first capacitor,', 'wherein the fourth data ...

SEMICONDUCTOR DEVICE

To provide a semiconductor device with high reliability in operation, in which data in a volatile memory can be saved to a non-volatile memory. For example, the semiconductor device includes an SRAM provided with first and second data storage portions and a non-volatile memory provided with third and fourth data storage portions. The first data storage portion is electrically connected to the fourth data storage portion through a transistor, and the second data storage portion is electrically connected to the third data storage portion through a transistor. The transistors are turned off when the SRAM operates, and the transistors are turned on when the SRAM does not operate, so that data in the SRAM is saved to the non-volatile memory. Precharge is performed when the SRAM is restored. 1. A semiconductor device comprising a plurality of memory elements arranged in a matrix , each memory element including:a first memory circuit comprising a first data storage portion and a second data storage portion; anda second memory circuit comprising a third data storage portion and a fourth data storage portion,wherein the first data storage portion is electrically connected to a bit line through a first transistor;wherein the second data storage portion is electrically connected to an inverted bit line through a second transistor;wherein the first transistor and the second transistor are electrically connected to a first word line;wherein the third data storage portion is electrically connected to the second data storage portion through a third transistor;wherein the fourth data storage portion is electrically connected to the first data storage portion through a fourth transistor;wherein the third transistor and the fourth transistor are electrically connected to a second word line;wherein the third data storage portion is electrically connected to one electrode of a first capacitor;wherein the fourth data storage portion is electrically connected to one electrode of a second ...

Three dimensional non-volatile storage with interleaved vertical select devices above and below vertical bit lines

A three-dimensional array of memory elements reversibly change a level of electrical conductance/resistance in response to one or more voltage differences being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Local bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. Vertically oriented select devices are used to connect the local bit lines to global bit lines. A first subset of the vertically oriented select devices are positioned above the vertically oriented bit lines and a second subset of the vertically oriented select devices (interleaved with the first subset of the vertically oriented select devices) are positioned below the vertically oriented bit lines.

Semiconductor device having enhanced signal integrity

A semiconductor includes a first signal line commonly connected to a plurality of semiconductor devices and a second signal line commonly connected to one or more of the plurality of semiconductor devices. The first signal line has a first impedance per unit length, the second signal line has a second impedance per unit length, the second impedance per unit length is greater than the first impedance per unit length, and the first signal line has a longer routing length than the first signal line. Widths of the signal lines may be set to reduce a difference in the impedances.

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

Each of m word lines is connected to n memory cells in a corresponding one of rows of m×n memory cells. Each of n bit lines is connected to m memory cells in a corresponding one of columns of m×n memory cells, and each of n source lines is connected to m memory cells in a corresponding one of columns of m×n memory cells. N first switching elements switch connection states between a reference node and the n bit lines, and n second switching elements switch connection states between the reference node and the n source lines. N third switching elements switch connection states between the write driver and the n bit lines, and n fourth switching elements switch connection states between the write driver and the n source lines. 1. A nonvolatile semiconductor memory device comprising:m×n memory cells disposed in m rows and n columns, where m and n are integers greater than or equal to 2;m word lines each connected to n memory cells in a corresponding one of the rows of the m×n memory cells;n bit lines and n source lines each connected to m memory cells in a corresponding one of the columns of the m×n memory cells;a word line drive circuit configured to selectively activate the m word lines;a write driver configured to supply a rewrite voltage; n first switching elements each configured to switch a connection state between a reference node to which a reference voltage is applied and a corresponding one of the n bit lines, and', 'n second switching elements each configured to switch a connection state between the reference node and a corresponding one of the n source lines; and, 'a first selection circuit including'} n third switching elements each configured to switch a connection state between the write driver and a corresponding one of the n bit lines; and', 'n fourth switching elements each configured to switch a connection state between the write driver and a corresponding one of the n source lines., 'a second selection circuit including'}2. The nonvolatile ...

SEMICONDUCTOR STORAGE DEVICE

According to one embodiment, a semiconductor storage device of an embodiment of the present disclosure is provided with peripheral circuits, a memory cell array, upper bit lines, and first and second connecting parts. The memory cell array is disposed above the peripheral circuit, and includes at least first and second regions. The upper bit lines extend in a first direction and are above the memory cell array. The first and second connecting parts are respectively provided with contact plugs, and one of these connecting parts is formed between first and second regions. The upper bit lines includes a first group of upper bit lines which are connected to the peripheral circuits via the first connecting part, and a second group of upper bit lines which are connected to the peripheral circuits via the second connecting part. 1. A semiconductor storage device , comprising:a plurality of peripheral circuits on a semiconductor substrate;a memory cell array having a plurality of semiconductor layers above the peripheral circuits, the memory cell array including two or more regions;a plurality of upper bit lines disposed in one or more layers above the memory cell array and extending in a first direction, each of the upper bit lines electrically connected to at least one of the peripheral circuits;a plurality of lower bit lines disposed in one or more layers below the memory cell array and extending in the first direction, each of the lower bit lines corresponding to a respective upper bit line; anda plurality of connection parts including contact plugs connecting upper bit lines to corresponding lower bit lines,wherein a first group of the upper bit lines are connected to the peripheral circuits via a first connecting part and respective lower bit lines, the first connecting part disposed between two regions of the memory cell array, and a second group of the upper bit lines are connected to the peripheral circuits via a second connecting part and respective lower bit ...

SEMICONDUCTOR DEVICE

A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier. 2. The semiconductor device according to claim 1 ,wherein a gate length of the second MIS transistor is longer than a gate length of the first MIS transistor.3. The semiconductor device according to further comprising:a word line driving circuit including a third MIS transistor and operable to drive the word line,wherein a gate length of the second MIS transistor is longer than a gate length of the third MIS transistor.4. The semiconductor device according to claim 1 ,wherein the first wiring forms at least one both-way wiring and includes a first dummy bit line used as an outward wiring and a second dummy bit line used as a homeward wiring, wherein both of the source and the drain of a part of the second MIS transistors are coupled to the first dummy bit line, and both of the source and the drain of the other part of the second MIS transistors are coupled to the second dummy bit line.5. The semiconductor device according to claim 1 ,wherein the first wiring forms at least one both-way wiring and includes a first dummy bit line used as an outward wiring and a second dummy bit line used as a ...

Memory Having Isolation Units For Isolating Storage Arrays From A Shared I/O During Retention Mode Operation

A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths. 1. A memory comprising:a plurality of storage arrays each configured to provide data on a respective plurality of bit lines;a plurality of isolation units, each coupled to provide a data path between the respective plurality of bit lines of a corresponding respective one of the plurality of storage arrays and a plurality of data output signal paths when the corresponding respective storage array is operating in a normal operational mode;wherein in response to a given storage array of the plurality of storage arrays being placed in a low-voltage operational mode, the corresponding respective isolation unit is configured to isolate the respective plurality of bit lines from the plurality of data output signal paths.2. The memory as recited in claim 1 , wherein each bitline of each plurality of bit lines comprises a differential bit line pair claim 1 , and wherein each isolation unit comprises a plurality of pass transistor pairs claim 1 , each pass transistor of a pass transistor pair is coupled to a respective bit line of the differential bit line pair.3. The memory as recited in claim 2 , further comprising an input/output (I/O) unit configured to output via the plurality of data output signal paths claim 2 , the data received from the plurality of storage arrays.4. The memory as recited in claim 3 , wherein each isolation unit ...

VERTICAL TYPE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A vertical type semiconductor device includes a pillar structure protruding from a top surface of a substrate of a cell array region. Word lines extend while surrounding the pillar structure. Word line contacts contact edges of the word lines functioning as pad portions. An insulating interlayer pattern is provided on the substrate of a peripheral circuit region, which is disposed at an outer peripheral portion of the cell array region. A first contact plug contacts the substrate of the peripheral circuit region. A second contact plug contacts a top surface of the first contact plug and has a top surface aligned on the same plane with the top surfaces of the word line contacts. The first and second contact plugs are stacked in the peripheral circuit region, so the failure of the vertical type semiconductor device is reduced. 1. A vertical type semiconductor device , comprising:a pillar structure protruding in a vertical direction from a surface of a substrate in a cell array region and including a channel pattern;word lines surrounding the pillar structure, wherein the word lines are stacked and spaced apart from each other in the vertical direction;word line contacts having first top surfaces higher than an uppermost word line, the word line contacts contacting edges of the word lines, respectively;an insulating interlayer pattern provided on the substrate in a peripheral circuit region disposed at a peripheral portion of the cell array region, the insulating interlayer pattern having a second top surface lower than a top surface of the pillar structure;a first contact plug passing through the insulating interlayer pattern and contacting the surface of the substrate in the peripheral circuit region; anda second contact plug contacting a top surface of the first contact plug, the second contact plug having a third top surface aligned with the first top surfaces of the word line contacts.2. The vertical type semiconductor device of claim 1 , wherein the insulating ...

SEMICONDUCTOR DEVICE

In a semiconductor device of a stacked structure type having a control chip and a plurality of controlled chips, wherein the control chip allocates different I/O sets to the respective controlled chips and processes the I/O sets within the same access cycle, the controlled chip close to the control chip and positioned to a lower position in the stacked structure has I/O penetrating through substrate vias connected to penetrating through interconnections. The penetrating through interconnections are extended to an upper one of the controlled chips that not use the penetrating through interconnections and, as a result, all of the penetrating through interconnections have the same lengths as each other. 1. A device comprising:a first memory chip and a third memory chip that belong to a first group;a second memory chip and a fourth memory chip that belong to a second group, one of the first and second chips being stacked higher than the other of the first and second chips; anda first terminal configured to indicate which one of the first and second groups is accessed, the first and second groups being different from each other.2. The device of claim 1 , wherein the first terminal is configured to provide a first control signal taking one of first and second levels claim 1 , the first level of the first control signal being taken to access the first group to which the first and third memory chips belong claim 1 , and the second level of the first control signal being taken to access the second group to which the second and fourth memory chips belong.3. The device of claim 1 , wherein the third memory chip is stacked higher than the fourth memory chip when the first memory chip is stacked higher than the second memory chip.4. The device of claim 1 , further comprising:a second terminal configured to indicate which one of first and second sets is accessed, the first and second memory chips belonging to the first set, and the third and fourth memory chips belonging to the ...

STACKED DRAM DEVICE AND METHOD OF MANUFACTURE

A memory stack includes a number of memory dies including a master die and one or more slave dies. The slave die can be converted to a master die by further processing. The slave die includes a memory core having memory cell arrays. The slave die also includes first and second metal layers that form first and second distribution lines in the memory core, respectively. An interface circuit in the slave die is decoupled from the first and second metal layers. 1. A memory die for use in a memory device comprising:a memory core having memory cell arrays interconnected by first and second distribution lines;a first metal layer including the first distribution linesa second metal layer including the second distribution lines; andan interface circuit that is not coupled to the first or second distribution lines via any conductors on the memory die.2. The memory die according to wherein the memory die comprises a slave memory die configured to communicate with a memory controller via a master memory die claim 1 , and wherein the memory die is incapable of communicating command or data with the memory controller without the master memory die.3. The memory die according to wherein the slave memory die comprises at least one through-silicon-via (TSV) formed to couple the memory core of the slave memory die to an interface circuit of the master memory die.4. (canceled)5. The memory die according to wherein the slave memory die receives power via the at least one TSV.6. (canceled)7. The memory die according to wherein the memory die comprises a slave memory die configured to communicate with a memory controller via a buffer die claim 1 , and wherein the memory die is incapable of communicating command or data with the memory controller without the buffer die.813-. (canceled)14. The memory die according to wherein the memory die is of a predetermined width claim 1 , and is formed with a number of through-silicon-vias claim 1 , wherein the number of through-silicon-vias is based ...

STACKED SEMICONDUCTOR DEVICES INCLUDING A MASTER DEVICE

A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s). 1. (canceled)2. A system , comprising: a first memory chip comprising circuitry for generating one or more of voltage signals and control signals; and', 'a second memory chip lacking circuitry for generating one or more of voltage signals and control signals; and, 'a stack includinga plurality of Through-Silicon Vias extending between the first memory chip and the second memory chip, the Through-Silicon Vias connecting one or more of the voltage signals and the control signals generated by the first memory chip from the first memory chip to the second memory chip.3. The system of claim 1 , wherein the first and second memory chips are non-volatile memory chips.4. The system as claimed in wherein the first memory chip is a master device and the second memory chip is a slave device.5. The system of claim 2 , wherein only the first non-volatile memory chip includes a high voltage generator.6. The system of claim 1 , wherein:the first memory chip comprises circuitry for generating voltage signals; andthe generated voltage signals comprise high voltage signals for program and erase operations.7. The system of claim 1 , further comprising a third memory chip lacking circuitry for generating one or more of voltage signals and control signals claim 1 , wherein one or more of the voltage signals and the control signals generated by the first memory chip are communicated from the first memory chip to the third memory chip.8. The system of claim 1 , further comprising a package printed circuit board claim 1 , the stack connected to the package printed circuit board by flip chip and bumping.9. The system of claim 7 , wherein:the first memory device is larger dimensioned than the second memory device; andthe first memory device is positioned adjacent the package printed circuit ...

SELECTED GATE DRIVER CIRCUIT IN MEMORY CIRCUITS, AND CONTROL DEVICE AND CONTROL METHOD THEREOF

The present disclosure provides a selected gate (SG) driver circuit, including a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, and a second PMOS transistor. A gate electrode of the first NMOS transistor is connected to a gate electrode of the first PMOS transistor, a source electrode of the first NMOS transistor being connected to a drain electrode of the third NMOS transistor, and a drain electrode of the first NMOS transistor being connected to a drain electrode of the first PMOS transistor and a gate electrode of the second NMOS transistor. A source electrode of the second NMOS transistor is connected to a source electrode of the third NMOS transistor, and a drain electrode of the second NMOS transistor being connected to a drain electrode of the second PMOS transistor and a gate electrode of the third NMOS transistor. 1. A selected gate (SG) driver circuit used in a memory circuit , comprising:a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, and a second PMOS transistor, wherein:a gate electrode of the first NMOS transistor is connected to a gate electrode of the first PMOS transistor, a source electrode of the first NMOS transistor being connected to a drain electrode of the third NMOS transistor, and a drain electrode of the first NMOS transistor being connected to a drain electrode of the first PMOS transistor and a gate electrode of the second NMOS transistor;a source electrode of the second NMOS transistor is connected to a source electrode of the third NMOS transistor, and a drain electrode of the second NMOS transistor being connected to a drain electrode of the second PMOS transistor and a gate electrode of the third NMOS transistor;a source electrode of the first PMOS transistor is connected to a gate electrode of the second PMOS transistor; anda logic high voltage level is connected to a source electrode of the second PMOS transistor.2. The SG ...

Systems and Methods of Sectioned Bit Line Memory Arrays, Including Hierarchical and/or Other Features

A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described, including embodiments having sectioned bit lines with hierarchical aspects. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. Further, in some embodiments, the sectioned bit lines are arranged in hierarchical arrays. In other implementations, SRAM memory devices may be configured involving sectioned bit lines (including hierarchical) and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line. 1. An SRAM memory device comprising: [ a local bit line;', 'one or more memory cells connected to the local bit line;', 'a local complement bit line connected to the memory cell; &', 'a pass gate coupled to the local bit line;, 'a plurality of sectioned bit lines (SBLs), each comprising, 'a local sense amplifier;', 'a local shared data driver;', 'a global bit line;, 'a local section bit line includingwherein the local sense amplifier is configured to amplify a signal on a local sense line and provide an output to the global bit line.2. The device of wherein the pass gates are configured to connect and/or isolate the sectioned bit line and local sense line.3. A local section bit line (LSBL) of an SRAM including: a local bit line;', 'one or more memory cells connected to the local bit line;', 'a local complement bit line connected to the memory cell; and', 'a pass gate coupled to the local bit line;, 'a plurality of sectioned bit lines (SBLs), each comprisinga local shared sense amplifier;a local shared data driver;a global bit line;wherein the local sense amplifier is configured to amplify a signal on a local sense line and provide an output to the global bit ...

Reduced Size Semiconductor Device And Method For Manufacture Thereof

A nonvolatile semiconductor device is provided that includes a substrate and a plurality of blocks forming a string. Each block is positioned on the substrate and includes a plurality of word lines disposed on the substrate. The string includes a single ground select line disposed at one side of the plurality of blocks, and a single string select line is disposed at another side of the plurality of blocks. In some embodiments, the word lines of the plurality of blocks define gaps separating each block of the string from neighboring blocks of the string. One or more dummy word lines may be disposed in each gap between blocks of the string. Corresponding methods of manufacturing the nonvolatile semiconductor device and manipulating the nonvolatile semiconductor device are provided. 1. A nonvolatile semiconductor device comprising:a substrate;a plurality of blocks forming a string, wherein each block is positioned on the substrate and includes a plurality of word lines disposed on the substrate;a single ground select line associated with the string, wherein the single ground select line is disposed at one side of the plurality of blocks; anda single string select line associated with the string, wherein the single string select line is disposed at another side of the plurality of blocks.2. The nonvolatile semiconductor device of claim 1 , wherein the word lines of the plurality of blocks define gaps separating each block of the string from neighboring blocks of the string.3. The nonvolatile semiconductor device of claim 1 , wherein a dummy word line is disposed in a gap between a first block and a second block of the plurality of blocks of the string.4. The nonvolatile semiconductor device of claim 3 , wherein the dummy word line is a floating dummy word line.5. The nonvolatile semiconductor device of claim 3 , wherein the dummy word line has a voltage bias.6. The nonvolatile semiconductor device of claim 3 , wherein the dummy word line is connected to a ground.7. The ...

CENTRALIZED PLACEMENT OF COMMAND AND ADDRESS IN MEMORY DEVICES

Memory devices, memory systems, and systems, include memory devices with a bonding pad region including two or more bonding pads for operably coupling to external signals and a number of command-and-address (CA) input signals. The memory device also includes centralized CA interface region including two or more CA input circuits operably coupled to the number of input signals. One of the tow or more CA input circuits for each CA input signal may border at least two other CA input circuits coupled to different CA input signals. 1. A device , comprising:a bonding pad region including a number of bonding pads for operably coupling to external signals and a number of command-and-address (CA) input signals; anda centralized CA interface region including two or more CA input circuits operably coupled to the number of CA input signals, wherein one of the two or more CA input circuits for each CA input signal borders at least two other CA input circuits coupled to different CA input signals.2. The device of claim 1 , further comprising a memory cell region claim 1 , wherein the centralized CA interface region is positioned between the bonding pad region and the memory cell region.3. The device of claim 1 , wherein the two or more CA input circuits are arranged with:a first pair of CA input circuits arranged in a first direction; andat least one additional pair of CA input circuits arranged in a second direction relative to the first pair of CA input circuits.4. The device of claim 1 , wherein each of the two or more CA input circuits comprise:a buffer circuit operably coupled to one of the number of CA input signals;a latch circuit for receiving one or more clock signals; anda delay circuit arranged between the buffer circuit and the latch circuit.5. The device of claim 1 , further comprising a clock buffer circuit adjacent to at least one of the two or more CA input circuits and configured to supply one or more clock signals to each of the two or more CA circuits.6. The ...

Techniques for programming a memory cell

Techniques are provided for programming a self-selecting memory cell that stores a first logic state. To program the memory cell, a pulse having a first polarity may be applied to the cell, which may result in the memory cell having a reduced threshold voltage. During a duration in which the threshold voltage of the memory cell may be reduced (e.g., during a selection time), a second pulse having a second polarity (e.g., a different polarity) may be applied to the memory cell. Applying the second pulse to the memory cell may result in the memory cell storing a second logic state different than the first logic state.

FORMATION METHOD FOR AIR SPACER LAYER AND SEMICONDUCTOR STRUCTURE

The present application relates to a formation method for an air spacer layer and a semiconductor structure. The formation method for an air spacer layer includes: forming a first structure on a substrate and forming a second structure on the substrate, the second structure being located on a side surface of the first structure, a first trench being formed between the second structure and the first structure, and the second structure being exposed in the first trench; and growing, by an epitaxial growth process, an epitaxial layer on the second structure exposed in the first trench, the epitaxial layer not filling up the first trench, and an unfilled portion of the first trench forming the air spacer layer. 1. A formation method for an air spacer layer , comprising:forming a plurality of parallel spaced first structures on a substrate;forming a second structure on the substrate, the second structure being located between adjacent first structures, and a first trench being formed between the second structure and the first structure; andgrowing an epitaxial layer on a surface of the second structure by an epitaxial growth process, and filling part of the first trench with the epitaxial layer, an unfilled portion of the first trench forming the air spacer layer.2. The method according to claim 1 , wherein the first structure comprises a conductive structure and an isolation sidewall located on each of two sides of the conductive structure.3. The method according to claim 2 , wherein the first structure comprises a conductive structure and an isolation sidewall located on a side surface of the conductive structure claim 2 , and the step of forming a plurality of parallel spaced first structures on a substrate comprises:forming a plurality of parallel spaced conductive structures on the substrate;forming an isolation layer on exposed surfaces of the conductive structure and the substrate by a deposition process; andetching back the isolation layer, removing the isolation ...

MEMORY HAVING MEMORY CELL STRING AND COUPLING COMPONENTS

Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described. 1. An apparatus comprising:a memory device; and a first pillar;', 'first memory cells and associated control gates located in different levels of the memory device and along a first portion of the first pillar;', 'a first select gate, a control line, and a second select gate located in different levels of the memory device and along a second portion of the first pillar;', 'a second pillar, and second memory cells located in different levels of the memory device and along a first portion of the second pillar;', 'third memory cells located in different levels of the memory device and located along a third pillar;', 'a first conductive material coupled to the first pillar and the second pillar, wherein the first select gate, the control line, and the second select gate are between the first conductive material and the first memory cells;', 'a second conductive material coupled to the third memory cells; and', 'a first coupling component located along the second portion of the first pillar, the first coupling component being between the first select gate and the second select gate;', 'a second coupling component located along a second portion of the second pillar; and', 'a third coupling component coupled to the second conductive material and the third memory cells and located between the second conductive material and the third memory cells., 'an external device coupled to the memory device, the memory device including2. The apparatus of claim 1 , wherein the external device includes a memory controller.3. The apparatus of claim 1 , wherein the external device includes a processor.4. The ...

Valid command detection based on stack position identifiers in memory devices configured for stacked arrangements

Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

TSV Check Circuit With Replica Path

Disclosed herein is an apparatus that includes a first semiconductor chip, first and second TSVs penetrating the first semiconductor chip, a first path including the first TSV, a second path including the second TSV, a first charge circuit configured to charge the first path, a second charge circuit configured to charge the second path, a first discharge circuit configured to discharge the first path, a second discharge circuit configured to discharge the second path, and a comparator circuit configured to compare a potential of the first path with a potential of the second path.

METHODS OF MANUFACTURING DYNAMIC RANDOM ACCESS MEMORY

A method of manufacturing a dynamic random access memory including the following steps is provided. A bit line is formed on a substrate. A sidewall structure is formed on a sidewall of the bit line. The sidewall structure includes a first insulation layer, a second insulation layer, and a shield conductor layer. The first insulation layer is disposed on the sidewall of the bit line. The second insulation layer is disposed on the first insulation layer. The shield conductor layer is disposed between the first insulation layer and the second insulation layer. An interconnection structure electrically connected to the shield conductor layer is formed. 1. A method of manufacturing a dynamic random access memory , comprising:forming a bit line on a substrate; a first insulation layer, disposed on the sidewall of the bit line;', 'a second insulation layer, disposed on the first insulation layer; and', 'a shield conductor layer, disposed between the first insulation layer and the second insulation layer; and, 'forming a sidewall structure on a sidewall of the bit line, wherein the sidewall structure comprisesforming an interconnection structure electrically connected to the shield conductor layer.2. The method of manufacturing the dynamic random access memory according to claim 1 , wherein a method of forming the sidewall structure comprises:conformally forming a first insulation material layer and a shield conductor material layer on the bit line in sequence;performing an etch back process on the shield conductor material layer and the first insulation material layer to form the shield conductor layer and the first insulation layer respectively;conformally forming a second insulation material layer covering the shield conductor layer and the first insulation layer on the bit line; andremoving a portion of the second insulation material layer to form the second insulation layer.3. The method of manufacturing the dynamic random access memory according to claim 1 , wherein a ...

SEMICONDUCTOR MEMORY STRUCTURE HAVING DRAIN STRESSOR, SOURCE STRESSOR AND BURIED GATE

The present disclosure provides a semiconductor memory structure. The semiconductor memory structure includes a substrate, a gate structure, a drain stressor and a source stressor. The gate structure is disposed in the substrate. Each of the source stressor and the drain stressor includes a strained part disposed in the substrate. 1. A semiconductor memory structure , comprising:a substrate;a drain stressor, having a strained part disposed in the substrate;a source stressor, having a strained part disposed in the substrate; anda gate structure disposed in the substrate, between the drain stressor and the source stressor.2. The semiconductor memory structure of claim 1 , wherein the substrate comprises silicon germanium claim 1 , and the drain stressor and the source stressor comprise silicon.3. The semiconductor memory structure of claim 1 , further comprising a bit line connected to the drain stressor.4. The semiconductor memory structure of claim 3 , further comprising a bit line contact disposed between the drain stressor and the bit line.5. The semiconductor memory structure of claim 1 , further comprising a storage capacitor connected to the source stressor.6. The semiconductor memory structure of claim 5 , further comprising a storage node contact disposed between the storage capacitor and the source stressor.7. The semiconductor memory structure of claim 1 , wherein the drain stressor comprises a first drain layer claim 1 , a second drain layer and a third drain layer claim 1 , and the source stressor comprises a first source layer claim 1 , a second source layer claim 1 , and a third source layer.8. The semiconductor memory structure of claim 1 , wherein the gate structure comprises a gate electrode claim 1 , a gate dielectric layer claim 1 , and a gate seal.9. The semiconductor memory structure of claim 1 , further comprising a shallow trench isolation. This application is a divisional application of U.S. Non-Provisional application Ser. No. 16/520,569 ...

Semiconductor memory device that can stably perform writing and reading without increasing current consumption even with a low power supply voltage

Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

SEMICONDUCTOR DEVICE HAVING INTERCONNECTION IN PACKAGE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip. 1. A semiconductor device comprising:a first die connected to a first channel, the first die comprising a first memory chip; anda second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die,wherein the first and second dies are disposed in one package; andwherein the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.2. The semiconductor device of claim 1 , wherein:the first channel is a channel dedicated to the first memory chip for receiving a first type of signal from outside the semiconductor device;the second channel is a channel dedicated to the second memory chip for receiving the first type of signal from outside the semiconductor device; andthe interconnection circuit comprises a common channel shared by the first and second memory chips for receiving a second type of signal different from the first type of signal at one of the first and second memory chips and applying the second type of signal to both the first memory chip and the second memory chip.3. The semiconductor device of claim 2 , wherein:the first type of signal is an address, data, ...

SYSTEM AND METHOD FOR DETERMINING A CAUSE OF NETWORK CONGESTION

A method and apparatus of a device that determines a cause and effect of congestion in this device is described. In an exemplary embodiment, the device measures a queue group occupancy of a queue group for a port in the device, where the queue group stores a plurality of packets to be communicated through that port. In addition, the device determines if the measurement indicates a potential congestion of the queue group, where the congestion prevents a packet from being communicated within a time period. If potential congestion exists on that queue group, the device further gathers information regarding packets to be transmitted through that port. For example, the device can gather statistics packets that are stored in the queue group and/or new enqueue packets. 1. A non-transitory machine-readable medium having executable instructions to cause one or more processing units to perform a method to determine a cause of congestion in a network element , the method comprising:configuring a queue group corresponding to a port of the network element with a sample new enqueue threshold and a sample occupants threshold, wherein the sample new enqueue threshold is a threshold when new enqueue packets are sampled for characteristics of a subset of the new enqueue packets to be enqueued to that queue group, the sample occupants threshold is a threshold when a subset of a plurality of packets stored in the queue group are sampled for characteristics, and the sample new enqueue and sample occupants thresholds are different;measuring a queue group occupancy of the queue group for a port in the network element, wherein the queue group stores the plurality of packets to be communicated through that port;gathering information of the subset of new enqueue packets for that queue group when the queue group occupancy measurement is above the sample new enqueue threshold;gathering information of the subset of the plurality of packets for that queue group when the queue group occupancy ...

MEMORY CONTROLLER

A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM. 120-. (canceled)21. A memory controller component comprising: first circuitry to transmit a write command to a dynamic random access memory device (DRAM), the write command to be sampled by the DRAM in response to a first timing signal; and', 'second circuitry to transmit first write data to the DRAM, the first write data to be sampled by the DRAM in response to a second timing signal; and, 'a signaling interface, includingadjustment circuitry to offset the first and second timing signals from one another at the signaling interface to compensate for skew between their arrival times at the DRAM.22. The memory controller of wherein the adjustment circuitry to offset the first and second timing signals from one another comprises circuitry to offset a phase of the second timing signal from a phase of the first timing signal.23. The memory controller of wherein the adjustment circuitry to offset the first and second timing signals from one another comprises circuitry to offset the first and second timing signals at the signaling interface by a time interval that corresponds to a difference in respective propagation times claim 21 , from the memory controller component to the DRAM claim 21 , of the first and second timing signals.24. The memory controller of wherein the second circuitry to transmit the first write data to the DRAM comprises circuitry to output at least part of the first write data onto an external data signaling link at one or more times indicated by the second timing signal.25. The memory controller of wherein the circuitry to ...

ELECTRONIC DEVICE

An electronic device includes a substrate including an upper surface, a clock output pad formed in a control device mounting area of the upper surface, a command/address output pad formed in the control device mounting area, a clock signal main wiring connected to the clock output pad, a command/address signal main wiring connected to the command/address output pad, a first clock signal branch wiring branched from the clock signal main wiring at a first branch point of the clock signal main wiring, and a second clock signal branch wiring branched from the clock signal main wiring at a second branch point of the clock signal main wiring, which is located at a downstream side of the clock signal main wiring than the first branch point of the clock signal main wiring. 1. An electronic device , comprising:a substrate including an upper surface, a clock output pad formed in a control device mounting area of the upper surface, a command/address output pad formed in the control device mounting area, a clock signal main wiring connected to the clock output pad, a command/address signal main wiring connected to the command/address output pad, a first clock signal branch wiring branched from the clock signal main wiring at a first branch point of the clock signal main wiring, a second clock signal branch wiring branched from the clock signal main wiring at a second branch point of the clock signal main wiring, which is located at a downstream side of the clock signal main wiring than the first branch point of the clock signal main wiring, a first command/address signal branch wiring branched from the command/address signal main wiring at a first branch point of the command/address signal main wiring, a second command/address signal branch wiring branched from the command/address signal main wiring at a second branch point of the command/address signal main wiring, which is located at a downstream side of the command/address signal main wiring than the first branch point of ...

INTERCONNECTION FOR MEMORY ELECTRODES

Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level. 1. (canceled)2. An apparatus , comprising:a first access line and a second access line extending in a same direction, wherein at least a portion of the first access line extends beyond a portion of the second access line, and wherein the first access line comprises a first jog segment and the second access line comprises a second jog segment; anda connector coupled with the first jog segment, or the second jog segment, or both.3. The apparatus of claim 2 , further comprising:a socket region comprising a first socket coupled with the first access line and a second socket coupled with the second access line, wherein the first access line extends beyond a boundary of the socket region, and wherein the second access line is located entirely within the boundary of the socket region.4. The apparatus of claim 2 , wherein a distance between the first jog segment and the second jog segment is greater than a distance between another portion of the first access line and another portion of the second access line.5. The apparatus of claim 2 , further comprising:a third access line extending in a different direction than the first access line and the second access line, wherein at least a portion of the third access line intersects at least a portion of the first access line, at least a portion of the second access line, or both.6. The apparatus of claim 2 , wherein the first access line and the second access line are formed at a first vertical level of a stack.7. The apparatus of claim 6 , further comprising:a second vertical level of the stack comprising a fourth access line and a fifth access line extending in a second direction.8. ...

APPARATUSES AND METHODS FOR CONTROLLING REFRESH OPERATIONS

An apparatus includes, a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a fast detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional. 1. A method comprising:receiving a first command to enter a target-row refresh mode;receiving a second command and a third command during the target-row refresh mode, wherein the second command is accompanied by first address information designating a first word line of a plurality of word lines in a memory array, wherein the third command is accompanied by the first address information designating the first word line, and wherein the plurality of word lines further includes a second word line that is proximate to the first word line; and responsive to the second command, activating the first word line; and', 'responsive to the third command, activating the second word line if the second word line is functional and not activating the second word line if the second word line is not functional., 'performing, responsive to the second command and the third command, a refresh operation on the memory array by2. The method of claim 1 , further comprising:before entering the target-row refresh mode, storing detective address information, 'responsive, at least in part, to the first address information accompanying the third command, providing ...

MEMORY DEVICE ARCHITECTURE

Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array. 1. A method , comprising:forming a memory array of memory cells occupying a footprint; andforming a plurality of word line drivers in a circuit level, the plurality of word line drivers within the footprint of the memory array; andforming a plurality of digit line drivers in the circuit level, the plurality of digit line drivers within the footprint of the memory array,wherein the circuit level comprises a plurality of word line driver connection points and digit line driver connection points distributed across the footprint.2. The method of claim 1 , further comprising:forming a plurality of word lines each coupled with and laterally traversing at least one of the plurality of word line drivers at a different vertical level from the plurality of word line drivers.3. The method of claim 2 , wherein each word line driver connection point of the plurality of word line driver connection points is centered along a word line direction within a word line driver region of a plurality of word line driver regions.4. The method of claim 1 , further comprising:forming a plurality of digit lines each coupled with and laterally traversing at least one of the plurality of digit line drivers at a different vertical level from the plurality of digit line drivers.5. The method of claim 4 , wherein each of the digit line driver connection points is centered along a digit line direction within a digit line driver region of a plurality of digit line driver regions.6. The method of claim 1 , wherein at least two word line drivers of the plurality of word line drivers are positioned along a first direction and at least two digit line drivers of the plurality of digit line drivers are positioned along a second direction orthogonal to the first direction.7. The method of claim 1 , wherein the memory array of memory cells comprises two word lines positioned ...

MEMORY DEVICE ARCHITECTURE

Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array. 1. A device , comprising:a plurality of memory cells within a footprint of the device; anda plurality of word line drivers and digit line drivers in a circuit level positioned below the plurality of memory cells, wherein the circuit level comprises a plurality of word line driver connection points and digit line driver connection points within the footprint.2. The device of claim 1 , wherein the plurality of word line drivers are distributed across and within the footprint in a plurality of word line driver regions claim 1 , and wherein the plurality of digit line drivers are distributed across and within the footprint in a plurality of digit line driver regions.3. The device of claim 2 , wherein word line electrodes connecting the plurality of word line drivers to the plurality of memory cells of the device are staggered relative to one another by shifting the word line electrodes relative to one another along their axis of elongation.4. The device of claim 3 , wherein digit line electrodes connecting the plurality of digit line drivers to the plurality of memory cells of the device are staggered relative to one another by shifting the digit line electrodes relative to one another along their axis of elongation.5. The device of claim 1 , wherein the plurality of memory cells comprises word lines positioned along a first direction and digit lines positioned along a second direction different from the first direction.6. The device of claim 1 , further comprising:a plurality of word lines each coupled with at least one of the plurality of word line drivers at a different vertical level from the plurality of word line drivers.7. The device of claim 6 , wherein each word line driver connection point of the plurality of word line driver connection points is positioned along a word line direction within a word line driver region of a ...

Non-volatile semiconductor memory device and method for driving the same

The non-volatile semiconductor memory device comprises a non-volatile semiconductor memory, a controller for controlling the non-volatile semiconductor memory, the controller includes a reset terminal capable of receiving a reset signal from a host, an interface circuit capable of receiving a sleep command, and a data storing circuit, when the reset signal is received in a state which the interface circuit is being supplied with power, the data storing circuit is reset, when a sleep command is received in a state which the interface circuit is being supplied with power, the data necessary for communication with the host or the non-volatile semiconductor memory device is stored into the data storing circuit and power to the interface circuit is interrupted and when the reset signal is received in a state which power to the interface circuit is interrupted, the data is read from the data storing circuit.

NON-VOLATILE MEMORY WITH CAPACITORS USING METAL UNDER PADS

A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the I/O pads. 1. A non-volatile storage apparatus , comprising:a non-volatile memory structure;a plurality of I/O pads in communication with the non-volatile memory structure, the I/O pads include a power I/O pad; anda capacitor connected to the power I/O pad, the capacitor is positioned in one or more metal interconnect layers below at least one of the I/O pads.2. The non-volatile storage apparatus of claim 1 , wherein:the capacitor is positioned above electrical components located on a substrate.3. The non-volatile storage apparatus of claim 1 , wherein:the plurality of I/O pads further includes a ground I/O pad and data/control I/O pads;the capacitor is connected to the ground I/O pad; andthe capacitor is positioned directly below one of the data/control pads.4. The non-volatile storage apparatus of claim 1 , wherein:the capacitor includes two metal components in a single metal interconnect layer.5. The non-volatile storage apparatus of claim 4 , wherein:the two metal components are shaped as interleaved combs.6. The non-volatile storage apparatus of claim 4 , wherein:the two metal components have interdigitated fingers.7. The non-volatile storage apparatus of claim 1 , wherein:the capacitor includes a first metal component in a first metal interconnect layer below a first I/O pad and a second metal component in a second metal interconnect layer below the first I/O pad.8. The non-volatile storage apparatus of claim 7 , wherein:the first metal component is a mesh.9. The non-volatile storage apparatus of claim 7 , wherein:the first ...

Semiconductor memory device

A semiconductor memory device includes n interconnect layers above a substrate; and a first interconnect region between an end of a control circuit and an end of the substrate in a direction of a first axis beside a first pad region in a direction of a second axis. The n interconnect layers are located at different levels from the substrate. Each of the n interconnect layers includes an interconnect. The first interconnect region includes no transistor, and no contact coupled to the substrate. The first interconnect region includes an interconnect extending along the second axis in m (m is a natural number equal to or larger than 3, larger than n/2, and equal to or smaller than n) interconnect layers of the n interconnect layers.

MULTI-DECK MEMORY DEVICE WITH ACCESS LINE AND DATA LINE SEGREGATION BETWEEN DECKS AND METHOD OF OPERATION THEREOF

Some embodiments include apparatuses and methods using a substrate, a first memory cell block including first memory cell strings located over the substrate, first data lines coupled to the first memory cell strings, a second memory cell block including second memory cell strings located over the first memory cell block, second data lines coupled to the second memory cell strings, first conductive paths located over the substrate and coupled between the first data lines and buffer circuitry of the apparatus, and second conductive paths located over the substrate and coupled between the second data lines and the buffer circuitry. No conductive path of the first and second conductive paths is shared by the first and second memory cell blocks. 1. An apparatus comprising:a substrate;a first memory cell block including first memory cell strings located over the substrate, and first data lines coupled to the first memory cell strings;a second memory cell block including second memory cell strings located over the first memory cell block, and second data lines coupled to the second memory cell strings;first conductive paths located over the substrate and coupled between the first data lines and buffer circuitry of the apparatus; andsecond conductive paths located over the substrate and coupled between the second data lines and the buffer circuitry, wherein no conductive path of the first and second conductive paths is shared by the first and second memory cell blocks.2. The apparatus of claim 1 , further comprising:first access lines coupled to the first memory cell strings; andsecond access lines coupled to the second memory cell strings, wherein the first memory cell block shares no access line with the second memory cell block.3. The apparatus of claim 2 , further comprising:first transistors, each of the first transistors coupled to a respective access line of the first access lines; andsecond transistors, each of the second transistors coupled to a respective access ...

APPARATUS INCLUDING BARRIER MATERIALS WITHIN ACCESS LINE STRUCTURES, AND RELATED METHODS AND ELECTRONIC SYSTEMS

An apparatus comprising a memory array comprising access lines. Each of the access lines comprises an insulating material adjacent a bottom surface and sidewalls of a base material, a first conductive material adjacent the insulating material, a second conductive material adjacent the first conductive material, and a barrier material between the first conductive material and the second conductive material. The barrier material is configured to suppress migration of reactive species from the second conductive material. Methods of forming the apparatus and electronic systems are also disclosed. 1. An apparatus , comprising: an insulating material adjacent a bottom surface and sidewalls of a base material;', 'a first conductive material adjacent the insulating material;', 'a second conductive material adjacent the first conductive material; and', 'a barrier material between the first conductive material and the second conductive material, the barrier material configured to suppress migration of reactive species from the second conductive material., 'a memory array comprising access lines, each of the access lines comprising2. The apparatus of claim 1 , wherein the first conductive material comprises a first metal nitride material and the second conductive material comprises a second metal nitride material.3. The apparatus of claim 2 , wherein each of the first metal nitride material and the second metal nitride material comprises titanium nitride claim 2 , and the barrier material is configured to suppress migration of chlorine from the second metal nitride material.4. The apparatus of claim 1 , wherein the first conductive material comprises titanium nitride and the second conductive material comprises tungsten claim 1 , the barrier material configured to suppress migration of fluorine from the tungsten.5. The apparatus of claim 1 , wherein the barrier material is directly adjacent upper surfaces and sidewalls of the first conductive material and the second conductive ...

APPARATUS INCLUDING ACCESS LINE STRUCTURES AND RELATED METHODS AND ELECTRONIC SYSTEMS

An apparatus comprising a memory array comprising wordlines, bit lines, and memory cells. Each memory cell is coupled to an associated one of the wordlines and an associated one of the bit lines. Each of the wordlines is buried in a substrate and comprises a lower conductive material, an upper conductive material, and an oxidation material of the lower conductive material between the lower conductive material and the upper conductive material. In additional embodiments, the apparatus comprises access lines, digit lines, and memory cells. The access lines comprise an oxidized material between a first conductive material and a second conductive material, the oxidized material comprising an oxide of the first conductive material. Methods of forming the apparatus and electronic systems are also disclosed. 1. An apparatus comprising: a lower conductive material;', 'an upper conductive material; and', 'an oxidation material of the lower conductive material between the lower conductive material and the upper conductive material., 'a memory array comprising wordlines, bit lines, and memory cells, each memory cell coupled to an associated one of the wordlines and an associated one of the bit lines, each of the wordlines buried in a substrate and comprising2. The apparatus of claim 1 , wherein the lower conductive material and the upper conductive material are different in work function from each other.3. The apparatus of claim 1 , wherein the lower conductive material and the upper conductive material are the same in work function as each other.4. The apparatus of claim 1 , wherein the lower conductive material comprises titanium nitride claim 1 , tungsten claim 1 , or ruthenium and the upper conductive material comprises titanium nitride claim 1 , tungsten claim 1 , ruthenium claim 1 , or polysilicon.5. The apparatus of claim 1 , wherein the oxidation material comprises a thickness of from about 1 nm to about 3 nm.6. An apparatus claim 1 , comprising: 'an oxidized material ...

Semiconductor devices including dummy patterns

A semiconductor device including a substrate having a cell, peripheral, and boundary area; a stack structure on the cell area and including insulating and interconnection layers that are alternately stacked; a molding layer on the peripheral area boundary areas; a selection line isolation pattern extending into the stack structure; a cell channel structure passing through the stack structure; and first dummy patterns extending into the molding layer on the peripheral area, wherein upper surfaces of the first dummy patterns, an upper surface of the selection line isolation pattern, and an upper surface of the cell channel structure are coplanar, and at least one of the first dummy patterns extends in parallel with the selection line isolation pattern or cell channel structure from upper surfaces of the first dummy patterns, the upper surface of the selection line isolation pattern, and the upper surface of the cell channel structure toward the substrate.

MTP-Thyristor Memory Cell Circuits and Methods of Operation

An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.

THREE-DIMENSIONAL THREE-PORT BIT CELL AND METHOD OF ASSEMBLING SAME

A three-port, three-dimensional bit cell generally comprises a read portion of a cell disposed on a first tier. The read portion comprises a plurality of read port elements. The three-port bit cell further comprises a write portion of the cell disposed on a second tier that is vertically stacked with respect to the first tier. The first and second tiers are coupled using at least one via. The write portion comprises a plurality of write port elements.

ELECTRONIC DEVICE

This patent document relates to memory circuits or devices and their applications in electronic devices or systems. The disclosed technology in this patent document includes memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device in which an electronic device capable of reducing an area, improving device characteristics due to a reduction in the resistance of a switching transistor, simplifying the process, and reducing a cost is provided. In accordance with the electronic device of this patent document, an area can be reduced, device characteristics can be improved due to a reduction in the resistance of the switching transistor, the process can be simplified, and a cost can be reduced.

Integrated Assemblies Having Void Regions Between Digit Lines and Conductive Structures, and Methods of Forming Integrated Assemblies

Some embodiments include an integrated assembly having a memory array, and having digit lines extending along a first direction through the memory array. Insulative spacers are along sidewalls of the digit lines. The insulative spacers extend continuously along the digit lines through the memory array. Conductive regions are laterally spaced from the digit lines by intervening regions. The conductive regions are configured as segments spaced apart from one another along the first direction. The intervening regions include regions of the insulative spacers and include void regions adjacent the regions of the insulative spacers. The void regions are configured as void-region-segments which are spaced apart from one another along the first direction by insulative structures. Storage-elements are associated with the conductive regions. Some embodiments include methods of forming integrated assemblies. 1. A method of forming an integrated assembly , comprising:forming a construction to include, along a cross-section, a pair of digit lines spaced from one another by a spacing region; each of the digit lines having a top surface, and a pair of opposing sidewall surfaces extending downwardly from the top surface; the construction including first insulative material over the top surfaces; the first insulative material and digit lines together forming beams which extend along a first direction perpendicular to the cross-section; the beams having sidewall surfaces; the digit lines having metal-containing regions; the construction including a storage-element-contact below the metal-containing regions of the digit lines and within the spacing region;forming rails along the sidewall surfaces; each of the rails comprising a film sandwiched between a pair of panels, and comprising an insulative cap over the film and the panels; the pair of panels being an inner panel proximate one of the sidewall surfaces of the digit lines and an outer panel on an opposing side of the film from ...

MEMORY DEVICE

A memory device that operates at high speed is provided. 1. A semiconductor device comprising: 'a circuit, the circuit comprises a plurality of silicon transistors, and', 'a first layer, the first layer comprising a first memory cell comprising a first transistor comprising an oxide semiconductor in a channel region; and', 'a second memory cell comprising a second transistor comprising an oxide semiconductor in a channel region,, 'a second layer over the first layer, the second layer comprisingwherein each of the first transistor and the second transistor comprises a front gate and a back gate,wherein the back gate of the first transistor is electrically connected to the back gate of the second transistor,wherein one of a source and a drain of the first transistor is electrically connected to a first electrode of a first capacitor,wherein one of a source and a drain of the second transistor is electrically connected to a first electrode of a second capacitor, andwherein a second electrode of the first capacitor and a second electrode of the second capacitor are electrically connected to a first wiring which is supplied with GND.2. The semiconductor device according to claim 1 , further comprising a third memory cell claim 1 ,wherein a part of the first wiring functioning as the second electrode of the first capacitor functions as a second electrode of a third capacitor whose first electrode is electrically connected to a third transistor comprised in the third memory cell.3. The semiconductor device according to claim 1 , wherein the first memory cell and the second memory cell are part of different memory cell arrays.4. The semiconductor device according to claim 1 , wherein the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor are electrically connected to the circuit via a second wiring functioning as a bit line.5. The semiconductor device according to claim 4 , wherein the bit line is ...

SEMICONDUCTOR MEMORY DEVICE

According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The first memory cell faces the second memory cell. When reading data from the first memory cell, the semiconductor memory device is configured to perform the first operation in which a first voltage is applied to the first word line and a second voltage higher than the first voltage is applied to the second word line, and perform the second operation in which a third voltage higher than the first voltage and a fourth voltage different from the third voltage are applied to the first word line and a fifth voltage lower than the second to the fourth voltage is applied to the second word line. 1. A memory system connectable to a host , comprising:a semiconductor memory device including a first memory cell, a second memory cell, a first word line, a second word line and a first bit line, the first word line being coupled to the first memory cell, the second word line being coupled to the second memory cell, the first bit line being capable of being electrically coupled to both the first memory cell and the second memory cell, the first memory cell facing the second memory cell with a first semiconductor layer interposed therebetween; anda controller electrically connected to the semiconductor memory device and configured to read data from the semiconductor memory device in response to a read command from the host, whereinthe semiconductor memory device is configured to perform a data read operation including a first operation and a second operation, and perform the first operation in which a first voltage is applied to the first word line and a second voltage higher than the first voltage is applied to the second word line, and', 'perform, after the first operation, the second operation in which a third voltage higher than the first voltage and a fourth voltage different from the third voltage are ...

SEMICONDUCTOR DEVICE

A semiconductor device including an SRAM capable of sensing a defective memory cell that does not satisfy desired characteristics is provided. The semiconductor device includes a memory cell, a bit line pair being coupled to the memory cell and having a voltage changed towards a power-supply voltage and a ground voltage in accordance with data of the memory cell in a read mode, and a specifying circuit for specifying a bit line out of the bit line pair. In the semiconductor device, a wiring capacitance is coupled to the bit line specified by the specifying circuit and a voltage of the specified bit line is set to a voltage between a power voltage and a ground voltage in a test mode. 1. A semiconductor device comprising:a memory cell;a bit line pair on which a voltage is changed towards a first voltage and a second voltage that is different from the first voltage in a read mode in accordance with data of the memory cell, the bit lines being coupled to the memory cell; anda specifying circuit for specifying a bit line out of the bit line pair,wherein a capacitative element is coupled to the bit line specified by the specifying circuit and a voltage of the specified bit line is set to a voltage between the first voltage and the second voltage in a test mode.2. The semiconductor chip according to claim 1 ,wherein the capacitative element has a wiring capacitance that is determined depending on a length of the bit line pair.3. The semiconductor device according to claim 2 , further comprisinga write circuit for supplying a potential in accordance with data to be written to the bit line pair in a write mode,wherein the write circuit includes a specifying circuit and supplies a third voltage that is different from the first voltage and the second voltage to the bit line specified by the specifying circuit in the write mode.4. The semiconductor device according to claim 3 ,wherein the specifying circuit specifies a bit line out of the bit line pair in accordance with the ...

DIGIT LINE FORMATION FOR HORIZONTALLY ORIENTED ACCESS DEVICES

Systems, methods, and apparatuses are provided for digit line formation for horizontally oriented access devices. One example method includes forming layers of a first dielectric material, a low doped semiconductor material, and a second dielectric material, in repeating iterations vertically to form a vertical stack, forming a vertical opening in the vertical stack, selectively etching the second dielectric material to form a horizontal opening in the second dielectric material, gas phase doping a dopant on a top surface of the low doped semiconductor material in the horizontal opening to form a source/drain region, forming a high doped semiconductor material in the horizontal opening, selectively etching the high doped semiconductor material formed in the horizontal opening such that a portion of the high doped semiconductor material remains, and converting the remaining high doped semiconductor material to a conductive material having a different characteristic from the remaining high doped semiconductor material. 1. A method for forming arrays of vertically stacked memory cells , having horizontally oriented access devices and vertically oriented access lines , comprising:forming layers of a first dielectric material, a low doped semiconductor material, and a second dielectric material, in repeating iterations vertically to form a vertical stack;forming a vertical opening in the vertical stack;selectively etching the second dielectric material to form a horizontal opening in the second dielectric material;gas phase doping a dopant into a top surface of the low doped semiconductor material in the horizontal opening to form a source/drain region;forming a high doped semiconductor material in the horizontal opening;selectively etching the high doped semiconductor material formed in the horizontal opening such that a portion of the high doped semiconductor material remains; andconverting the remaining high doped semiconductor material to a conductive material having ...

INTEGRATED CIRCUIT INCLUDING MEMORY CELL AND METHOD OF DESIGNING THE SAME

An integrated circuit includes: a first wiring layer on which a first bit line pattern and a positive power supply pattern, a first power supply line landing pad, and a first word line landing pad are formed; a second wiring layer on which a first negative power supply pattern connected to the first power supply line landing pad, and a first word line pattern connected to the first word line landing pad are formed; a third wiring layer on which a second negative power supply pattern connected to the first negative power supply pattern, and a second word line landing pad connected to the first word line pattern are formed; and a fourth wiring layer on which a second word line pattern, connected to the second word line landing pad, are formed. 1. An integrated circuit comprising a plurality memory cells , the integrated circuit comprising: a first bit line pattern and a positive power supply pattern extending in a first direction, the positive power supply pattern being configured to provide a positive supply voltage; and', 'a plurality of first power supply line landing pads configured to provide a negative supply voltage, and a plurality of first word line landing pads configured to provide a word line voltage;, 'a first wiring layer comprising a first negative power supply pattern extending in a second direction, and connecting first power supply line landing pads, which are adjacent to each other in the second direction among the plurality of first power supply line landing pads, to each other, and configured to provide the negative supply voltage; and', 'a plurality of first word line patterns extending in the second direction, connected to the plurality of first word line landing pads, and configured to provide the word line voltage;, 'a second wiring layer comprising a second negative power supply pattern connected to the first negative power supply pattern; and', 'a plurality of second word line landing pads connected to the plurality of first word line ...

FABRICATION METHOD OF BURIED WORDLINE STRUCTURE

A buried wordline structure fabrication method includes: providing a first trench in a semiconductor substrate, wherein the first trench has a tip on its bottom; performing epitaxial growth within the first trench to reduce the depth of the tip on the bottom of the first trench; and forming a gate dielectric layer on an inner wall of the first trench and filling a gate conductive layer within the first trench to form the buried wordline structure. 1. A fabrication method for a buried wordline structure , comprising:providing a first trench in a semiconductor substrate, wherein the first trench has a tip on its bottom;performing epitaxial growth within the first trench to reduce the depth of the tip on the bottom of the first trench; andforming a gate dielectric layer on an inner wall of the first trench and filling a gate conductive layer within the first trench to form the buried wordline structure.2. The fabrication method according to claim 1 , wherein a trench isolation structure is formed in the semiconductor substrate claim 1 , and a surface layer of the semiconductor substrate is divided into a plurality of independent regions by the trench isolation structure; and before performing epitaxial growth within the first trench claim 1 , the method further comprises:providing a second trench in the trench isolation structure, wherein the second trench and the first trench are connected with each other, and the depth of the first trench is less than that of the second trench.3. The fabrication method according to claim 1 , wherein the second trench has a tip on its bottom.4. The fabrication method according to claim 1 , wherein a width of an opening of the first trench ranges from 30 nm to 50 nm claim 1 , and a depth of the first trench ranges from 60 nm to 80 nm.5. The fabrication method according to claim 1 , whereinsaid providing a first trench in the semiconductor substrate comprises:forming a mask layer on the semiconductor substrate and defining an etching ...

Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal. 1. A semiconductor device , comprising:a memory device from a plurality of memory devices aligned in a vertical stack; anda latency determiner configured to determine a signal latency;wherein the signal latency is configured to be adjusted based on a position of the memory device within the vertical stack.2. The semiconductor device of claim 1 , wherein a programmed latency is stored in a register.3. The semiconductor device of claim 2 , further comprising a latency adjustor configured to adjust the signal latency claim 2 , as appropriate claim 2 , based on the programmed latency.4. The semiconductor device of claim 3 , wherein the latency adjustment is configured to be performed using a data strobe on a common vertical connection.5. The semiconductor device of claim 1 , wherein the latency adjustment is configured to even out latency differences at a memory interface chip or substrate.6. The semiconductor device of claim 1 , wherein a stack position identifier is used to identify the position of the memory device within the vertical stack.7. A semiconductor device claim 1 , comprising:a memory device from a plurality of ...

SEMICONDUCTOR DEVICE

A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier. 2. The semiconductor device according to claim 1 ,wherein a gate length of the second MIS transistor is longer than a gate length of the first MIS transistor.3. The semiconductor device according to further comprising:a word line driving circuit including a third MIS transistor and operable to drive the word line,wherein a gate length of the second MIS transistor is longer than a gate length of the third MIS transistor.4. The semiconductor device according to claim 1 ,wherein the first wiring forms at least one both-way wiring and includes a first dummy bit line used as an outward wiring and a second dummy bit line used as a homeward wiring. This application is a Continuation of U.S. application Ser. No. 15/367,829, filed Dec. 2, 2016, which is a Continuation of U.S. application Ser. No. 14/981,195, filed Dec. 28, 2015, now patented as U.S. Pat. No. 9,542,999, which is a Continuation of U.S. application Ser. No. 14/321,169, filed Jul. 1, 2014, now patented as U.S. Pat. No. 9,281,017, which is a Continuation of U.S. application Ser. No. 14/026,575, filed Sep. 13, 2013, now patented as U.S. Pat. No ...

Non-volatile (nv) memory (nvm) matrix circuits employing nvm matrix circuits for performing matrix computations

Non-volatile (NV) memory (NVM) matrix circuits employing NVM circuits for performing matrix computations are disclosed. In exemplary aspects disclosed herein, an NVM matrix circuit is provided that has a plurality of NVM storage string circuits each comprising a plurality of NVM bit cell circuits each configured to store a memory state. Each NVM bit cell circuit has a stored memory state represented by a resistance, and includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector of 1×m size for example. Activation of the gate of a given NVM bit cell circuit controls whether its resistance is contributed to a respective source line. This causes a summation current to be generated on each source line based on the weighted summed contribution of each NVM bit cell circuit's resistance to its respective source line.

SEMICONDUCTOR MEMORY DEVICE

The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern. 1. A semiconductor memory device comprising:a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other;a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction;a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction;a first memory pattern disposed between each of the conductive patterns and the first channel pattern; anda second memory pattern disposed between each of the conductive patterns and the second channel pattern.2. The semiconductor memory device of claim 1 , further comprising:a first bit line spaced apart from the stack in the vertical direction, connected to one end of the first channel pattern, and extending in a first direction not parallel to the vertical direction; anda second bit line extending parallel to the first bit line, spaced apart from the first bit line in a second direction not parallel to the first direction, and connected to one end of the second channel pattern.3. The semiconductor memory ...

INTERCONNECTIONS FOR 3D MEMORY

Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step. 120-. (canceled)21. An apparatus , comprising:a memory array comprising a plurality of access lines; and select a first access line or a second access line for performance of a memory operation;', 'cause performance of the memory operation; and', 'cause the first access line and the second access line of the memory array to be equalized subsequent to performance of the memory operation., 'a controller coupled to the memory array, the controller to22. The apparatus of claim 21 , wherein claim 21 , when the memory operation comprises a program operation claim 21 , the controller is to cause the first access line to be selected and the second access line to be deselected.23. The apparatus of claim 21 , wherein claim 21 , when the memory operation comprises a read operation claim 21 , the controller is to cause the first access line to be deselected and the second access line to be selected.24. The apparatus of claim 21 , wherein the first access line and the second access line of the memory array are equalized to a potential that is different than a ground reference potential.25. The apparatus of claim 21 , wherein the controller is claim 21 , subsequent to causing the first access line and the second access line of the memory array to be equalized claim 21 , to cause the first access line or the second access line claim 21 , or both claim 21 , to be discharged to ...

APPARATUSES AND METHODS INVOLVING ACCESSING DISTRIBUTED SUB-BLOCKS OF MEMORY CELLS

Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. Additional embodiments are described. 1. (canceled)2. A memory device comprising:an array of memory cells comprising multiple blocks of memory cells, wherein individual blocks of memory cells include multiple respective sub-blocks of memory cells; accessing a first sub-block of memory cells and a second sub-block of memory cells at the same time, wherein the first and second sub-blocks of memory cells are part of a first block of memory cells,', 'wherein the first and second sub-blocks within the first block are enabled to be accessed simultaneously, and wherein the sub-blocks in a second block of memory cells are not enabled to be accessed when the first and second sub-blocks of the first block are being accessed; and', 'wherein the first sub-block of the block of memory cells and the second sub-block of the block of memory cells are not in the same row or the same column of the block of memory cells., 'a controller comprising control circuitry and configured to support operations of the memory device; when the controller is operable to perform operations comprising3. The memory device of claim 2 , wherein accessing a first sub-block of memory cells and a second sub-block of memory cells at the same time comprises accessing the first sub-block having a first coordinate and a second coordinate at the same time as accessing the second sub-block having a first coordinate and a second coordinate claim 2 , wherein the first and second coordinates of the first sub-block are not the same as the first and second coordinates of the second sub-block.4. The memory device of claim 2 , wherein accessing a first sub-block of memory cells and a second sub-block of memory cells at the same time comprises accessing the first sub-block according to an x-coordinate ...

Functional signal line overdrive

Devices and techniques are disclosed herein to provide a number of different bias signals to each of multiple signal lines of an array of memory cells, each bias signal having an overdrive voltage above a target voltage by a selected increment and an overdrive period, to determine settling times of each of the multiple signal lines to the target voltage for the number of different bias signals, to determine a functional compensation profile for an array of memory cells comprising a relationship between the different bias signals and the determined settling times of the multiple signal lines.

SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME

A semiconductor device includes a plurality of word lines; a plurality of bit lines; and a plurality of bit line node contacts. The plurality of word lines extend in a first direction in or on a substrate. The plurality of bit lines crosses over the plurality of word lines. Each of the plurality of bit line node contacts connects a corresponding bit line to the substrate, and each of the plurality of bit line node contacts has a width substantially equal to a width of the corresponding bit line. 1. A semiconductor device comprising:a plurality of word lines extending in a first direction in or on a substrate;a plurality of bit lines crossing over the plurality of word lines; anda plurality of bit line node contacts, each of the plurality of bit line node contacts connecting a corresponding bit line to the substrate, and each of the plurality of bit line node contacts having a width substantially equal to a width of the corresponding bit line.2. The semiconductor device of claim 1 , wherein a sidewall of each bit line node contact is aligned with a sidewall of the corresponding bit line.3. The semiconductor device of claim 1 , further comprising:a plurality of storage node contacts between the plurality of bit lines and connected to the substrate, a distance between a first sidewall of a first of the plurality of storage node contacts and a corresponding first bit line adjacent to the first sidewall is substantially equal to a distance between a second sidewall of the first storage node contact and a second bit line adjacent to the second sidewall.4. The semiconductor device of claim 3 , wherein a distance between a first of the plurality of bit line node contacts and the first storage node contact is substantially equal to a distance between the first storage node contact and the corresponding first bit line.5. The semiconductor device of claim 3 , further comprising:a plurality of storage node pads, each of the plurality of storage node pads being between the ...

NOVEL 3D NAND MEMORY DEVICE AND METHOD OF FORMING THE SAME

In a method for forming a semiconductor device, a channel structure is formed that extends from a side of a substrate, where the channel structure includes sidewalls and a bottom region. The channel structure further includes a bottom channel contact that is positioned at the bottom region and a channel layer that is formed along the sidewalls and over the bottom channel contact. A high-k layer is formed over the channel layer along the sidewalls of the channel structure and over the bottom channel contact. 1. A method for forming a semiconductor device , comprising:forming a channel structure that extends from a side of a substrate, the channel structure having sidewalls and a bottom region, the channel structure further including a bottom channel contact that is positioned at the bottom region and a channel layer that is formed along the sidewalls and over the bottom channel contact; andforming a high-k layer over the channel layer along the sidewalls of the channel structure and over the bottom channel contact.2. The method of claim 1 , further comprising:forming a plurality of word lines that are positioned over the substrate; andforming a plurality of insulating layers that are positioned over the substrate, the plurality of word lines and the plurality of insulating layers being alternatingly stacked so that the plurality of word lines are spaced apart from one another by the plurality of the insulating layers.3. The method of claim 2 , wherein the forming the channel structure comprises:forming a channel opening that extends through the plurality of word lines and the plurality of insulating layers, and further extends into the substrate, the channel opening having sidewalls and a bottom region to expose the substrate;forming the bottom channel contact at the bottom region of the channel opening, the bottom channel contact being formed along the sidewalls of the channel opening and further extending into the substrate;forming a blocking layer along the ...

INTEGRATED CIRCUIT DEVICES AND METHODS OF MANUFACTURING THE SAME

Integrated circuit devices may include a plurality of word line structures and a plurality of insulating films that are stacked alternately. Sides of the plurality of word line structures and the plurality of insulating films define a side of a channel hole extending through the plurality of word line structures and the plurality of insulating films. The devices may also include a blocking dielectric film on the side of the channel hole, and a plurality of charge storage films on the blocking dielectric film and on the sides of the plurality of word line structures, respectively. Each of the plurality of charge storage films may include a first charge storage film and a second charge storage film sequentially stacked on a respective one of the sides of the plurality of word line structures. A surface of the second charge storage film may include a recess in a middle portion thereof. 1. A method of manufacturing an integrated circuit device , the method comprising:forming, on a substrate, a structure comprising a plurality of first films and a plurality of second films alternately stacked with the plurality of first films;forming a channel hole that extends through the structure;forming, in the channel hole, a plurality of indented spaces by removing portions of the plurality of first films through the channel hole;forming, in the channel hole, a blocking dielectric film comprising a plurality of first grooves that are on the plurality of indented spaces, respectively, a preliminary charge storage film comprising a plurality of second grooves that are on the plurality of first grooves, respectively, and a first cover sacrificial layer comprising a plurality of third grooves that are on the plurality of second grooves, respectively, a plurality of first cover layers in the plurality of third grooves, respectively, and a second cover layer on the first cover sacrificial layer;exposing portions of the first cover sacrificial layer by removing the plurality of first ...

INTERCONNECTIONS FOR 3D MEMORY

Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step. 1. An apparatus , comprising:a memory array including a plurality of access lines;an equalization circuit coupled to the array; and a first voltage to be applied to a selected one of the access lines;', 'a second voltage to be applied to a non-selected one of the access lines; and', 'the selected one of the access lines and the non-selected one of the access lines to be discharged to an equalization potential subsequent to performance of a program operation., 'a controller coupled to the memory array, wherein the controller is configured to cause2. The apparatus of claim 1 , wherein the controller is further configured to cause the selected access line and the non-selected access line to be discharged to a ground reference potential subsequent to discharge of the selected access line and the non-selected access line to the equalization potential.3. The apparatus of claim 1 , wherein the equalization potential is different than a ground reference potential.4. The apparatus of claim 1 , wherein the controller is further configured to cause the equalization circuit to be enabled while discharging the selected access line and the non-selected access line to the equalization potential.5. The apparatus of claim 1 , further comprising:a first global control line coupled to the selected access line; anda second global control line coupled to the non-selected access line ...

A 3d semiconductor device and system

A 3D semiconductor device, the device including: a first crystalline silicon layer including a plurality of first transistors; a first metal layer interconnecting the first transistors, a portion of the first transistors forming a plurality of first logic gates; a first array of memory cells including second transistors; a second metal layer overlying the first and second transistors; a second crystalline silicon layer overlaying the second metal layer and the second crystalline silicon layer including a plurality of third transistors; a third metal layer interconnecting the third transistors, a portion of the third transistors forming a plurality of second logic gates; a second array of memory cells including fourth transistors and overlaying the second crystalline silicon layer; a fourth metal layer overlying the third and fourth transistors, where at least one of the fourth transistors is overlaying at least another one of the fourth transistors such that they are self-aligned, having been processed following the same lithography step, where the second array of memory cells include NAND flash type memory cells.

NAND String Utilizing Floating Body Memory Cell

NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described. 123-. (canceled)24. A NAND string configuration comprising:a plurality of semiconductor memory cells serially connected to one another to form a string of semiconductor memory cells;a select gate drain device connecting one end of said string of semiconductor memory cells to a bit line, wherein said select gate drain device is not a semiconductor memory cell; anda select gate source device connecting an opposite end of said string of semiconductor memory cells to a common source line, wherein said select gate source device is not a semiconductor memory cell;wherein at least one of said plurality of semiconductor memory cells each comprise a substrate and a floating body region formed as part of said substrate and configured to store data as charge therein to define a state of said semiconductor memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a third region in electrical contact with said floating body region and spaced apart from said first and second regions;wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said floating body region;wherein each said at least one of said plurality of semiconductor memory cells has only one gate; andwherein serial connections between at least two of said semiconductor memory cells are not connected to any terminals.25. The NAND string configuration of claim 24 , wherein all serial connections between said semiconductor memory cells are not connected to any terminals claim 24 , so that only said select gate drain device and said select gate source device are connected ...

SEMICONDUCTOR STORAGE DEVICE

A semiconductor storage device includes a first semiconductor extending above a substrate and including a first part and a second part, a first word line at a first level above the substrate and facing the first part of the first semiconductor, a second word line at the first level above the substrate and facing the second part of the first semiconductor, a first cell transistor including a first area of the first part of the first semiconductor that faces the first word line, and a second cell transistor including a second area of the second part of the first semiconductor that faces the second word line, wherein during an operation of reading data from the first cell transistor, a first voltage that is less than a threshold voltage of the second cell transistor and greater than or equal to zero voltage is applied to the second word line. 1. A semiconductor storage device comprising:a first semiconductor extending above a substrate and including a first part that extends above the substrate and a second part that extends above the substrate;a first word line at a first level above the substrate and facing the first part of the first semiconductor;a second word line at the first level above the substrate and facing the second part of the first semiconductor, such that the first semiconductor is between the second word line and the first word line, and the second word line is separate from the first word line;a first cell transistor including a first area of the first part of the first semiconductor that faces the first word line; anda second cell transistor including a second area of the second part of the first semiconductor that faces the second word line, wherein during an operation of reading data from the first cell transistor, a first voltage that is less than a threshold voltage of the second cell transistor and greater than or equal to zero voltage is applied to the second word line.2. The semiconductor storage device according to claim 1 , further ...