СПОСОБ ПРОИЗВОДСТВА СТРУКТУРЫ ЕДИНИЧНОЙ ЯЧЕЙКИ СИЛИКОНОВО-КАРБИДНОГО МОП-ТРАНЗИСТОРА

Изобретение относится к способам изготовления одноячеечной структуры карбидокремниевого полевого МОП-транзистора. Согласно изобретению предложен способ изготовления структуры карбидокремниевого полевлшл МОП транзистора, в котором область проводящего канала имеет изогнутую форму и состоит из трех областей, при этом между первыми смежными областями расположены четвертые области, благодаря чему общая длина области вертикального проводящего канала может существенно увеличиваться, снижая, таким образом, отношение сопротивления канала к сопротивлению во включенном состоянии. 7 з.п. ф-лы, 9 ил.

ТОНКОПЛЕНОЧНЫЙ ТРАНЗИСТОР ИЗ НИЗКОТЕМПЕРАТУРНОГО ПОЛИКРИСТАЛЛИЧЕСКОГО КРЕМНИЯ И СПОСОБ ЕГО ИЗГОТОВЛЕНИЯ

Настоящее изобретение относится к тонкопленочному транзистору из низкотемпературного поликристаллического кремния, который обладает определенными электрическими характеристиками и надежностью, и к способу изготовления такого тонкопленочного транзистора. Тонкопленочный транзистор из низкотемпературного поликристаллического кремния включает по меньшей мере подзатворный слой, которым является композитный изоляционный слой, включающий по меньшей мере три диэлектрических слоя, при этом плотность каждого диэлектрического слоя последовательно увеличивается в порядке их формирования в данном способе изготовления. Поскольку согласно настоящему изобретению учитывается отношение между плотностью каждого слоя композитного изоляционного слоя и плотностью других его слоев, каждый слой в композитном изоляционном слое тонкопленочного транзистора из низкотемпературного поликристаллического кремния, изготовленный способом согласно настоящему изобретению, имеет улучшенные характеристики контакта поверхности ...

МДП-ТРАНЗИСТОР НА СТРУКТУРЕ КРЕМНИЙ НА САПФИРЕ

Полезная модель относится к области микроэлектроники и может быть использована при изготовлении интегральных схем на базе структур кремний на сапфире (КНС), широко используемых для создания цифровых, цифроаналоговых и аналого-цифровых КМОП БИС, а также КМОП БИС повышенной надежности и устойчивых к радиационным воздействиям. Технический результат от использования предлагаемой полезной модели - усовершенствование конструкции МДП-транзистора на КНС, обеспечивающее повышение технологичности его изготовления и эксплуатационного ресурса указанного транзистора за счет выигрышной замены материала диэлектрика между электродом затвора и каналом с диоксида кремния на сапфир подложки в результате монтажа электрода затвора на обратной поверхности подложки из сапфира и исключения из конструкции транзистора отдельного конструктивного элемента - тонкого диэлектрика и допускающего нежелательный эффект туннелирования электронов в упомянутом диэлектрике между электродом затвора и каналом в сверхмалогабаритных МДП-транзисторах. В МДП-транзисторе на структуре кремний на сапфире, содержащем сформированные планарно в островке слоя кремния на лицевой поверхности подложки из сапфира исток и сток и расположенный между ними канал с изолированным электродом затвора, смонтированным на поверхности диэлектрика, расположенного между затвором и каналом, электрод затвора смонтирован с его размещением на протяжении канала на обратной поверхности подложки из сапфира, выполняющей функцию упомянутого диэлектрика. 2 з.п. ф-лы, 1 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 170 578 U1 (51) МПК H01L 29/78 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ФОРМУЛА ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ РОССИЙСКОЙ ФЕДЕРАЦИИ (21)(22) Заявка: 2016148017, 07.12.2016 (24) Дата начала отсчета срока действия патента: 07.12.2016 (72) Автор(ы): Кривулин Николай Олегович (RU) Дата регистрации: 28.04.2017 Приоритет(ы): (22) Дата подачи заявки: 07.12.2016 Адрес для переписки: 603950, г. Нижний Новгород, ГСП-20, пр. ...

МОЩНЫЙ ПОЛЕВОЙ ТРАНЗИСТОР СВЧ НА ПОЛУПРОВОДНИКОВОЙ ГЕТЕРОСТРУКТУРЕ

Согласно изобретению мощный полевой транзистор СВЧ на полупроводниковой гетероструктуре содержит полупроводниковую подложку, буферный слой, последовательность слоев широкозонного и слоя узкозонного материалов типа AlGaAs-InGaAs-GaAs с заданными характеристиками, при этом группы проводящих слоев, формирующих канал, содержат по меньшей мере один слой InуGa1-уAs с разными значениями y химического элемента, по меньшей мере два легированных донорной примесью δn-слоя, по меньшей мере два спейсерных i-слоя, попарно расположенных по обе стороны канального слоя, две группы барьерных слоев AlхGa1-хAs, каждая в виде системы барьерных слоев, одна из которых расположена с одной стороны группы проводящих слоев над подложкой - подложечная, другая – с противоположной стороны – затворная, при этом подложечная выполнена в виде акцепторно-донорной системы барьерных слоев AlхGa1-хAs, электроды истока, затвора, стока расположены на наружной поверхности полупроводниковой гетероструктуры. Затворная группа барьерных ...

ДАТЧИК, СПОСОБ ЕГО ИЗГОТОВЛЕНИЯ И ЭЛЕКТРОННОЕ УСТРОЙСТВО

Датчик, способ его изготовления и электронное устройство. Датчик (100) включает в себя: несущую подложку (101), тонкопленочный транзистор (102) (TFT), расположенный на несущей подложке и включающий в себя электрод (1025) истока, первый изоляционный слой (106), расположенный на TFT (102) и содержащий первое сквозное отверстие (1071), проходящее через первый изоляционный слой (106), проводящий слой (1031), расположенный в первом сквозном отверстии (1071) и на части первого изоляционного слоя (106) и электрически соединенный с электродом (1025) истока через первое сквозное отверстие (1071), смещающий электрод (1032), расположенный на первом изоляционном слое (106) и отдельный от проводящего слоя (1031), активный считывающий слой (1033), соответственно, соединенный с проводящим слоем (1031) и смещающим электродом (1032), и вспомогательный проводящий слой (1034), расположенный на проводящем слое (1031). Датчик и способ его изготовления улучшают проводимость и обеспечивают нормальную передачу ...

ПОЛЕВОЙ ТРАНЗИСТОР, ОТОБРАЖАЮЩИЙ ЭЛЕМЕНТ, УСТРОЙСТВО ОТОБРАЖЕНИЯ ИЗОБРАЖЕНИЯ И СИСТЕМА

Изобретение относится к полевым транзисторам и устройствам отображения изображения. Полевой транзистор включает в себя электрод затвора, электрод истока и электрод стока, активный слой, который сформирован между электродом истока и электродом стока, и изолирующий слой затвора, который сформирован между электродом затвора и активным слоем, активный слой включает в себя по меньшей мере два вида оксидных полупроводниковых слоев, в том числе слой A и слой B, причем активный слой включает в себя три или более оксидных полупроводниковых слоев, в том числе два или более слоев A, и при этом активный слой является многослойной структурой АВА из трех слоев, которые представляют собой слой А, слой В и слой А, размещенные друг над другом в этом порядке, один из слоев А находится в контакте с изолирующим слоем затвора, и другой из слоев А находится в контакте с электродом истока и электродом стока. 4 н. и 14 з.п. ф-лы, 13 ил., 2 табл.

ТОНКОПЛЕНОЧНЫЙ ТРАНЗИСТОР С НИЗКИМ КОНТАКТНЫМ СОПРОТИВЛЕНИЕМ

Изобретение относится к тонкопленочному транзистору (TFT), содержащему подложку (100) со слоем (101) электрода затвора, наложенным и структурированным на ней, и изолирующим слоем (102) затвора, наложенным на слой электрода затвора и подложку. Транзистор дополнительно содержит (i) несущий инжекционный слой (103), расположенный выше изолирующего слоя (102) затвора, (ii) слой (104) электрода истока/стока (И/С), наложенный на несущий инжекционный слой, и (iii) полупроводниковый слой (106), который непосредственно контактирует с изолирующим слоем затвора, несущим инжекционным слоем и слоем электрода истока/стока. Предложены способ производства таких транзисторов, устройства, содержащие такие TFT, и применение таких TFT. Изобретение обеспечивает получение полупроводникового слоистого материала, который обладает улучшенными проводящими свойствами. 4 н. и 24 з.п. ф-лы, 12 ил.

ВЫРАВНИВАЮЩИЙ СЛОЙ

ЖИДКОСТЬ ДЛЯ НАНЕСЕНИЯ ПОКРЫТИЯ ДЛЯ ОБРАЗОВАНИЯ МЕТАЛЛООКСИДНОЙ ТОНКОЙ ПЛЕНКИ, МЕТАЛЛООКСИДНАЯ ТОНКАЯ ПЛЕНКА, ПОЛЕВОЙ ТРАНЗИСТОР И СПОСОБ ПОЛУЧЕНИЯ ПОЛЕВОГО ТРАНЗИСТОРА

... 1. Жидкость для нанесения покрытия для образования металлооксидной тонкой пленки, включающая:неорганическое соединение индия;по меньшей мере, одно из неорганического соединения магния и неорганического соединения цинка; ипростой гликолевый эфир.2. Жидкость для нанесения покрытия для образования металлооксидной тонкой пленки по п.1,в которой неорганическим соединением индия является, по меньшей мере, одно, выбранное из группы, состоящей из нитрата индия, сульфата индия и хлорида индия;в которой неорганическим соединением магния является, по меньшей мере, одно, выбранное из группы, состоящей из нитрата магния, сульфата магния и хлорида магния; ив которой неорганическим соединением цинка является, по меньшей мере, одно, выбранное из группы, состоящей из нитрата цинка, сульфата цинка и хлорида цинка.3. Жидкость для нанесения покрытия для образования металлооксидной тонкой пленки по п.1, причем жидкость для нанесения покрытия для образования металлооксидной тонкой пленки удовлетворяет следующему ...

HERSTELLUNG ELEKTRONISCHER ANORDNUNGEN MIT DÜNNSCHICHT-TRANSISTOREN

ANZEIGEVORRICHTUNG UND VERFAHREN ZUR HERSTELLUNG VON ANZEIGEVORRICHTUNGEN

Anzeigevorrichtung mit einem Transistor und einem Anzeigeelement über dem Transistor, wobei der Transistor eine Gate-Elektrode auf einer isolierenden Oberfläche, eine Gate-Isolierschicht auf der Gate-Elektrode und Source/Drain-Elektroden auf der Oxidhalbleiterschicht und der Gate-Isolierschicht enthält, die jeweils eine erste leitende Schicht, die Stickstoff enthält, und eine zweite leitende Schicht auf der ersten leitenden Schicht und eine isolierende Schicht, die Sauerstoff auf der Oxidhalbleiterschicht und den Source-/Drain-Elektroden enthält, aufweisen.

Aktivmatrixsubstrat und Verfahren zu dessen Herstellung

Ein Aktivmatrix-Substrat (100) weist auf: ein Substrat (12); einen ersten Dünnfilmtransistor (10A), der auf dem Substrat (12) getragen ist und eine erste Halbleiterschicht (13A) mit kristallinem Silizium aufweist; einen zweiten Dünnfilmtransistor (10B), der auf dem Substrat (12) getragen ist und eine zweite Halbleiterschicht (17) mit einem Oxid-Halbleiter aufweist; und eine dritte Halbleiterschicht (13B), welche Silizium beinhaltet, die auf der Substratseite (12) der zweiten Halbleiterschicht (17) des zweiten Dünnfilmtransistors (10B) angeordnet ist, wobei eine erste Isolierschicht (14) zwischen der dritten Halbleiterschicht und der zweiten Halbleiterschicht angeordnet ist.

Dünnfilmtransistor vom Silizium-auf-Isolator-Typ

Polymerverbindung und Polymerlichtemittervorrichtung unter Verwendung derselben

Polymerverbindung, umfassend eine Struktur der folgenden Formel (1): (wobei Ring A und Ring B jeweils unabhängig voneinander einen aromatischen Kohlenwasserstoffring, gegebenenfalls mit einem Substituenten, darstellen, Ring C einen alicyclischen Kohlenwasserstoffring mit mindestens einem Substituenten darstellt, und der alicyclische Kohlenwasserstoffring ein Heteroatom enthalten kann.).

Dünnfilmtransistor und Flüssigkristallanzeige, die diesen verwendet

PIXELSTRUKTUR, ARRAYSUBSTRAT FÜR EINE FLÜSSIGKRISTALLANZEIGE UND FLÜSSIGKRISTALLANZEIGEFELD

Eine Pixelstruktur, umfassend:eine Mehrzahl von nebeneinander in einer ersten Richtung angeordneten Datenleitungen (101, 102, 103, 104, 105, 106, 107, 201, 202, 203, 204, 205, 206, 207, 301, 302, 303, 304, 401, 501, 502, 503, 504, 505, 506, 507, 601, 602, 603, 604, 605, 606, 607, 701, 702, 703, 704, 705, 706, 707); undeine Mehrzahl von nebeneinander in einer zweiten Richtung angeordneten Gate-Leitungen (150, 250, 350, 451, 452, 453, 454, 550, 650, 750),wobei sich die Mehrzahl von Datenleitungen mit der Mehrzahl von Gate-Leitungen schneidet, um eine Mehrzahl von Subpixeln zu definieren, jedes aus der Mehrzahl von Subpixeln umfassend einen Dünnschichttransistor (140, 240, 340, 440, 540, 640, 740) und eine Pixelelektrode (130, 230, 330, 430, 530, 630, 730), die Mehrzahl von Subpixeln umfassend erste Reihen von Subpixeln (110, 210, 310, 410a, 410b, 510a, 510b, 610, 710) und zweite Reihen von Subpixeln (120, 220, 320, 420a, 420b, 520a, 520b, 620, 720), wobei die ersten Reihen von Subpixeln und ...

Semicoductor devices with germanium-rich active layers & doped transition layers

Semiconductor device comprising a plurality of germanium rich nanowires 508 aligned vertically over a silicon substrate 504. A silicon germanium transition layer 507C is disposed between the Ge nanowires and the Si substrate. A p-type delta-doped SiGe layer 507B is disposed below the SiGE transition layer and an n-type doped layer 507A between the δ-doped layer and substrate. A gate stack is disposed over the nanowires completely surrounding a length of each of the nanowires. Spacers 516 are disposed at the end of the gate stack and source and drain regions 514 are disposed on opposite sides of the gate stack and in contact with the plurality of nanowires. The nanowires may be vertically separated by an intervening sacrificial semiconductor layer, wherein the first nanowire is deposited on a first sacrificial layer which is disposed directly on the transition layer. The transition layer may be intrinsic whilst the delta doped layer is doped with boron and the n-type doped layer is doped ...

Polymeric compound, thin polymer film, and thin polymer film element including the same

A structured strained substrate for forming strained transistors with reduced thickness of active layer

Gate insulation layers for thin film transistors

A thin film transistor comprises a gate electrode 11, an active layer 13, and a gate insulating layer 12 comprising a diamond-like carbon layer 12-1, formed between the gate electrode and the active layer. Diamond-like carbon with a good insulating property is used as a gate insulating layer of the TFT, so a production yield of a TFT employing the diamond-like carbon increases. The carbon layer 12-1 is deposited by plasma enhanced C.V.D of a gas such as CH 4 , C 2 H 6 , C 2 H 2 or C 3 H 8 . A silicon nitride layer 12-2 is also deposted on the carbon layer enhanced C.V.D and the active layer of hydrogenated amorphous silicon, amorphous silicon or polysilicon is deposited on the silicon nitride layer.

A conjugated polymer having a phenoxazine structure and a phenothiazine structure as substituents and use of the polymer as a luminescent element

A structured strained substrate for forming strained transistors with reduced thickness of active layer

Solid state embossing of polymer devices

Gate insulating layer having diamond-like carbon and thin film transistor employing the same and process for manufacturing gate insulating layer

Crystallizing amorphous silicon using an align key

A method of fabricating polycrystalline silicon comprises forming a layer of amorphous silicon 512 on a substrate 514, forming flat align keys (524) in the corners of a peripheral region (II) of the substrate 514, applying a selective etch to the flat align keys (524) to form raised align keys 526, and crystallizing the amorphous silicon layer in a display region (I) of the substrate 514. The flat align keys (524) are made of polycrystalline silicon and are formed by irradiating a laser beam onto the amorphous silicon layer 512 through a mask (520). Crystallization of amorphous silicon in the display region (I) is carried out using a second mask 570. A method of forming an align key, a switching device and a display device are also disclosed.

Method of fabricating polycrystalline silicon and switching device using polycrystalline silicon

Manufacturing method of a thin film transistor array substrate

Display device

Manufacturing method and device for thin flim transistor substrate

Disclosed are a method and equipment for manufacture of a thin film transistor substrate. In the method, after grids (31a, 31b) and a grid insulation layer (32) of a thin film transistor are formed, a semiconductor layer (33) and a first protection layer (34) are sequentially deposited; and after a first protection layer (34) is patterned, the patterned first protection layer (34) is used as a photomask to pattern the semiconductor layer (33), in order to form the semiconductor channel of the thin film transistor. In this way, the number of photomasks can be reduced, and the method and device is conducive to lower cost.

Method for manufacturing a graphene thin-film transistor

Manufacture of electronic devices comprising thin -film transistors

Method for fabricating thin film transistor

Preparation method for graphene thin film transistor

Provided is a preparation method for a graphene thin film transistor, comprising:depositing a graphene layer (22) on the surface of a copper foil (21);depositing a metal layer (23) on the surface of the graphene layer (22);attaching a supporting layer (24) on the surface of the metal layer (23) to form a graphene film sheet;placing the graphene film sheet into a corrosive solution until the copper foil (21) is fully dissolved, transferring the graphene film sheet to a target substrate, and removing the supporting layer (24); anddefining source and drain electrode patterns on the surface of the metal layer (23), preparing the source electrode and the drain electrode, and preparing a gate electrode on the target substrate.

PROCEDURE FOR THE PRODUCTION OF A THIN FILM TRANSISTOR STRUCTURE

PRODUCTION OF AN ELECTRONIC ELEMENT WITH THIN FILM TRANSISTOR

INTEGRATED CIRCUIT FOR A SIMILAR SYSTEM

PROCEDURE FOR THE PRODUCTION OF AN ELECTRONIC CIRCUIT MODULE WITH HIGH DEVICE COMPLEXITY

PROCEDURE FOR THE PRODUCTION OF PICTURE ELEMENT ELECTRODES IN AN ACTIVE MATRIX

Halbleitervorrichtung mit mindestens einer auf einem Halbleitermaterial vom Typ AIIBVI angebrachten Elektrode und Verfahren zur Herstellung einer derartigen Vorrichtung

Substrate assembly and manufacturing method thereof and display device

ACTIVE MATRIX SUBSTRATE AND METHOD FOR MANUFACTURING SAME

Oxide semiconductor film, thin film transistor, oxide sintered body and sputtering target

Thin film transistor as well as production method thereof, array substrate and display device

The invention relates to the technical field of the display, and discloses a production method of a thin film transistor. The method comprises the steps of forming patterns containing a grid electrode, a grid insulation layer, an oxide semiconductor layer and a source-drain electrode layer on a substrate, and forming a pattern of an etching barrier layer of a metal oxide on the surface of the oxide semiconductor layer after the oxide semiconductor layer pattern is formed. According to the production method of the thin film transistor, the metal oxide is formed on the oxide semiconductor layer to be used as the etching barrier layer, the metal oxide can effectively prevent external vapor from influencing the oxide thin film transistor, no harm is produced on the oxide semiconductor layer in production, and the performance of the oxide thin film transistor is not influenced.

Thin film transistor, GOA circuit, display substrate and display device

Active matrix substrate and display device using the same

Liquid crystal display panel and manufacturing method thereof

Semiconductor device, storage device and electronic device

Manufacturing method of TFT substrate and manufactured TFT substrate

Amorphous oxide semiconductor film, oxide sintered body and thin film transistor

METHOD FOR PRODUCING CONDUCTIVE FILM, METHOD FOR PRODUCING FIELD EFFECT TRANSISTOR USING SAME, AND METHOD FOR PRODUCING WIRELESS COMMUNICATION DEVICE

Thin film transistor and its manufacturing method

Semiconductor device and mfg. method therefor

FIELD EFFECT TRANSISTOR

DEVICE AND PROCESS OF TREATMENT OF ELECTRONICS COMPONENTS IN THIN LAYERS OF AMORPHOUS SILICON, IN PARTICULAR OF TRANSISTORS FOR FLAT PANEL DISPLAYS HAVE ACTIVE MATRICES HAS LIQUID CRYSTALS

L'invention concerne le domaine des traitements, par apport énergétique, de couches minces déposées de silicium amorphe hydrogéné en vue de modifier une propriété physico-chimique choisie des couches. Selon l'invention, il est prévu d'éclairer les couches par une source de lumière qui émet un rayonnement de longueur d'onde comprise dans une bande d'absorption optique du silicium amorphe, et apte à délivrer au moins une impulsion de traitement, de durée comprise entre 50ns et 500ns, ce qui permet d'élever la mobilité électronique (µ) de la couche mince d'un facteur compris entre 1, 5 et 10.

터널 전계 효과 트랜지스터에 의한 집적회로 및 그의 제조 방법

... 본 발명은 2개의 터널 전계 효과 트랜지스터를 전기적으로 접속한 회로의 형성에 필요한 면적 및 비용을 감소시키고, 또한, 기생 용량·기생 저항도 감소시킨다. 터널 전계 효과 트랜지스터에 의한 집적회로는, 제 1 P형 영역 및 제 1 N형 영역 중 한쪽이 소스 영역, 다른쪽이 드레인 영역으로서 동작하는 제 1 터널 전계 효과 트랜지스터와, 제 2 P형 영역 및 제 2 N형 영역 중 한쪽이 소스 영역, 다른쪽이 드레인 영역으로서 동작하는 제 2 터널 전계 효과 트랜지스터가, 동일 극성으로 하나의 활성 영역에 형성되는 동시에 상기 제 1 P형 영역과 상기 제 2 N형 영역이 인접하도록 형성되고, 인접하는 상기 제 1 P형 영역과 상기 제 2 N형 영역이 금속 반도체 합금막에 의해 전기적으로 접속되어 있는 것을 특징으로 한다.

게르마늄이 풍부한 활성층들 및 도핑된 천이층들을 갖는 반도체 디바이스 스택, 반도체 디바이스 및 그 제조방법

Ge가 풍부한 디바이스층들을 갖는 반도체 디바이스 스택들 및 그로부터 제조되는 디바이스들. Ge가 풍부한 디바이스층이 기판 위에 배치되고, p-타입 도핑된 Ge 에치 억제층(예를 들어, p-타입 SiGe)가 그 사이에 배치되어, 디바이스층보다 Si가 풍부한 희생 반도체층의 제거 동안 Ge가 풍부한 디바이스층의 에치를 억제한다. 수성 하이드록사이드 화학반응들과 같은, 웨트 에칭제들에서의 Ge의 용해의 속도는, 반도체막 스택에 매립형 p-타입 도핑된 반도체층을 도입하는 것에 의해 극적으로 감소될 수 있어, Ge가 풍부한 디바이스층들에 대한 에칭제의 선택성을 향상시킨다.

DONOR SUBSTRATE HAVING CONDUCTIVE HEATING LAYER AND HYDROPHOBIC THIN FILM PATTERN, DONOT SUBSTRATE HAVING CONDUCTIVE HEATING PATTERN AND HYDROPHOBIC THIN FILM PATTERN, METHOD OF FORMING LIGHT EMITTING PATTERN USING DONOR SUBSTRATE, AND LIGHT EMITTING DIODE

The present invention relates to a method of forming a pixel of a light emitting diode such as an organic light emitting diode, a quantum dot light emitting diode, and a perovskite light emitting diode and a donor substrate for forming the same. The donor substrate having a conductive heating layer and a hydrophobic thin film pattern to form a precise and uniform light emission pattern on a target substrate comprises: a base substrate; a conductive heating layer positioned on an upper surface of the base substrate; a groove pattern layer positioned on the upper surface of the conductive heating layer and having a groove pattern and a protruding pattern adjacent to the groove pattern and defining the groove pattern; and a hydrophobic thin film positioned on an upper surface of the protruding pattern of the groove pattern layer. COPYRIGHT KIPO 2019 ...

산화물 소결체 및 반도체 디바이스

... 인듐과, 텅스텐과, 아연 및 주석 중 적어도 하나를 포함하는 산화물 소결체이며, 결정상으로서 텅스텐과, 아연 및 주석 중 적어도 하나를 포함하는 복산화물 결정상을 포함하는 산화물 소결체, 그리고 이 산화물 소결체를 타겟으로서 이용하여 스퍼터법에 의해 형성한 산화물 반도체막(14)을 포함하는 반도체 디바이스(10)가 제공된다.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

네거티브형 감광성 수지 조성물, 수지 경화막, 격벽 및 광학 소자

... 격벽 상면이 양호한 발잉크성을 가짐과 함께 개구부에 있어서의 잔사의 저감이 가능한 광학 소자 (유기 EL 소자, 양자 도트 디스플레이, TFT 어레이, 박막 태양 전지) 등의 제조에 사용하는 네거티브형 감광성 수지 조성물, 상면에 양호한 발잉크성을 갖는 광학 소자용의 수지 경화막, 미세하고 정밀도가 높은 패턴의 형성이 가능한 광학 소자용의 격벽, 및 그 격벽을 갖는 상기 광학 소자의 제공. 광 경화성을 갖는 알칼리 가용성 수지 또는 알칼리 가용성 단량체와, 광 중합 개시제와, 산 발생제와, 산 경화제와, 발잉크제를 함유하는 것을 특징으로 하는 네거티브형 감광성 수지 조성물, 그 네거티브형 감광성 수지 조성물을 사용하여 형성되는 경화막 및 격벽, 및 기판 표면에 복수의 도트와 인접하는 도트 사이에 위치하는 그 격벽을 갖는 상기 광학 소자.

DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

Disclosed is a display device capable of improving the performance of a transistor device. The disclosed display device comprises: an active pattern; a first insulating layer covering at least a part of the active pattern; a first gate electrode disposed on the first insulating layer; and a second gate electrode. The active pattern includes a first channel region, a first active region in contact with the first channel region and including an N doped region doped with N type impurity, and a second active region including the second channel region and in contact with the second channel region and including a P doped region doped with P type impurity. The first gate electrode overlaps the first channel region. The second gate electrode overlaps the second channel region and has a larger taper angle than the first gate electrode. COPYRIGHT KIPO 2019 ...

에칭 마스크, 에칭 마스크 전구체 및 산화물층의 제조 방법 및 박막 트랜지스터의 제조 방법

... 본 발명의 하나의 스크린 인쇄용의 에칭 마스크(80)는, 지방족 폴리카보네이트를 포함한다. 또한, 본 발명의 하나의 산화물층(채널(44))의 제조 방법은, 지방족 폴리카보네이트를 포함하는 에칭 마스크(80)의 패턴을 형성하는 에칭 마스크 형성 공정과, 그 에칭 마스크 형성 공정 후에, 에칭 마스크(80)에 의해 보호되어 있지 않은 산화물층(채널(44))을 용해시키는 용액에 접촉시키는 접촉 공정과, 그 접촉 공정 후에, 산화물층(채널(44)) 및 에칭 마스크(80)를 에칭 마스크(80)가 분해되는 온도 이상으로 가열하는 가열 공정을 포함한다.

ARRAY SUBSTRATE, LIQUID CRYSTAL DISPLAY DEVICE INCLUDING SAME, AND MANUFACTURING METHOD THEREOF

An array substrate, a liquid crystal display device including the same, and a manufacturing method thereof are provided. The array substrate according to an embodiment of the present invention includes a first substrate, a protruding pattern which is arranged on the first substrate and includes an upper surface protruding from the upper side of the first substrate and a lateral surface extended toward the upper side of the first substrate from the outside of the upper surface, a gate electrode arranged on the protruding pattern, a source electrode and a drain electrode which are insulated from the gate electrode and are separately arranged, and a semiconductor pattern layer which is arranged between the source electrode and the drain electrode. Any one of the source electrode and the drain electrode is arranged on the upper surface of the protruding pattern. Accordingly, the present invention can improve an aperture ratio of each pixel of the array substrate. COPYRIGHT KIPO 2017 ...

NANO STRUCTURE AND NANO DEVICE INCLUDING THE SAME

THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY DEVICE USING SAME

The present invention relates to a thin film transistor substrate on which different types of thin film transistors are arranged on the same substrate and a display device using the same. The display device includes a first thin film transistor, a second thin film transistor, a middle insulating film, and an etch-stopper layer. The first thin film transistor includes a polycrystal semiconductor layer, a first gate electrode disposed on the polycrystal semiconductor layer, a first source electrode, and a first drain electrode. The second thin film transistor includes a second gate electrode, an oxide semiconductor layer disposed on the second gate electrode, a second source electrode, and a second drain electrode. The middle insulating film is disposed on the first gate electrode and the second gate electrode and under the oxide semiconductor layer and includes a nitride film and an oxide film on the nitride film. The etch-stopper layer is disposed on the oxide semiconductor layer. COPYRIGHT ...

터널 전계 효과 트랜지스터에 의한 집적회로 및 그의 제조 방법

... 본 발명은 2개의 터널 전계 효과 트랜지스터를 전기적으로 접속한 회로의 형성에 필요한 면적 및 비용을 감소시키고, 또한, 기생 용량·기생 저항도 감소시킨다. 터널 전계 효과 트랜지스터에 의한 집적회로는, 제 1 P형 영역 및 제 1 N형 영역 중 한쪽이 소스 영역, 다른쪽이 드레인 영역으로서 동작하는 제 1 터널 전계 효과 트랜지스터와, 제 2 P형 영역 및 제 2 N형 영역 중 한쪽이 소스 영역, 다른쪽이 드레인 영역으로서 동작하는 제 2 터널 전계 효과 트랜지스터가, 동일 극성으로 하나의 활성 영역에 형성되는 동시에 상기 제 1 P형 영역과 상기 제 2 N형 영역이 인접하도록 형성되고, 인접하는 상기 제 1 P형 영역과 상기 제 2 N형 영역이 금속 반도체 합금막에 의해 전기적으로 접속되어 있는 것을 특징으로 한다.

수지 조성물, 내열성 수지막의 제조 방법, 및 표시 장치

... 200℃ 내지 350℃의 범위 내의 어느 온도에서의 가열 처리 후의 두께가 3.0㎛가 되도록 수지 조성물 막을 형성했을 때, 상기 가열 처리 전의 파장 365㎚ 내지 436㎚의 각 파장에 있어서의 광투과율이 50% 이상이며, 상기 가열 처리 후의 파장 365㎚ 내지 436㎚의 각 파장에 있어서의 광투과율이 10% 이하가 되는 내열성 수지막을 형성하는 수지 조성물. 유기 발광 장치나 표시 소자에 사용되는 평탄화막, 절연층, 또는 격벽 형성에 적합한, 자외광 및 가시광 단파장 영역을 흡수하는 기능을 갖는 수지 조성물을 제공한다.

Imaging device and electronic apparatus

POLARIZER, THIN FILM TRANSISTOR SUBSTRATE COMPRISING SAME, AND MANUFACTURING METHOD THEREOF

Provided is a polarizer with an improved transmission rate and enhanced processability. According to an embodiment of the present invention, the polarizer comprises: a substrate; and a conductive pattern layer including a first pattern having linear structures spaced from each other with an interval shorter than a frequency of incident light, transmitting first polarization light of the incident light, and reflecting second polarization light which is vertical to the first polarization light; and a second pattern arranged on an outside of the first pattern with a space therebetween to be insulated and including a stem unit and a branch unit configured to protrude from the stem unit to the first pattern. COPYRIGHT KIPO 2016 ...

Organic thin-film transistor, method for manufacturing organic thin-film transistor, material for manufacturing organic thin-film transistor, material for organic thin-film transistor, composition for organic thin-film transistor, organic semiconductor f

Process for producing high-performance and electrically stable, semiconductive metal oxide layers, layers produced by the process and use thereof

The present invention relates to a process for producing a semiconductor laminate comprising a first and a second metal oxide layer and a dielectric layer, the first metal oxide layer being arranged between the second metal oxide layer and the dielectric layer. The first and second metal oxide layers are formed correspondingly from a first and a second liquid phase. The present invention likewise relates to a semiconductor laminate which is obtainable by such a process and to electronic components comprising such a semiconductor laminate.

Method for manufacturing semiconductor device

In a transistor including an oxide semiconductor film, a metal oxide film which has a function of preventing electrification and covers a source electrode and a drain electrode is formed in contact with the oxide semiconductor film, and then, heat treatment is performed. Through the heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor film, whereby the oxide semiconductor film is highly purified. By providing the metal oxide film, generation of a parasitic channel on the back channel side of the oxide semiconductor film in the transistor can be prevented.

Sealing film, organic electroluminescent display, and organic semiconductor device

A sealing film comprising a base film, a sealing layer, and an adhesive layer, in that order. The Young's modulus of said sealing film is at least 1,000 MPa, and after sealing, the layer section on the sealing-layer side of the base film of said sealing film exhibits a retardation of at most 20 nm.

Semiconductor device and manufacturing method thereof

A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle [theta]1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle [theta]2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20 DEG and less than 90 DEG, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

Thin-film transistor and method for manufacturing it

Semiconductor device and method of production thereof

An operating semiconductor layer is formed in such a manner that amorphous silicon layer is formed to be shaped so that it has a wide region and a narrow region and the narrow region is connected to the wide region at a position asymmetric to the wide region, and the amorphous silicon layer is crystallized by scanning a CW laser beam from the wide region toward the narrow region in a state that a polycrystalline silicon layer as a heat-retaining layer encloses the narrow region from a side face through the silicon oxide layer.

Method of manufacturing thin film transistor panel having protective film of channel region

A protective film for protecring the channel region of a thin film transistor is formed by a dry etching treatment. Therefore, even if there is a defect in a semiconductor film, pin holes are not formed in a gate insulating film. It follows that the breakdown voltage of the gate insulating film is not lowered even if a scanning signal line, etc. including a gate electrode is formed of only an A-based metal film having an anodic oxide film not formed on the surface.

Thin film transistor, active matrix type display device, and their process

THIN FILM FORMING METHOD, SEMICONDUCTOR SUBSTRATE PRODUCED BY EMPLOYING SAME, AND ELECTRONIC DEVICE

This thin film forming method comprises: a step for preparing a first substrate (1), on the surface of which a thin film (2) is formed; a step for forming a plurality of openings (4) in the thin film (2); a step for forming a hollow part (5) between the first substrate (1) and the thin film (2) by etching the first substrate (1) through the openings (4); a step for having the thin film (2) to closely adhere to a second substrate (10) by interposing a liquid between the thin film (2) and the second substrate (10); and a step for heating the first substrate (1) and/or the second substrate (10). In the heating step, the liquid interposed between the thin film (2) and the second substrate (10) is dried, so that the thin film (2) is separated from the first substrate (1) and transferred to the second substrate (10).

ORGANIC SEMICONDUCTOR COMPOSITION, ORGANIC THIN-FILM TRANSISTOR, ELECTRONIC PAPER, AND DISPLAY DEVICE

The present invention addresses the problem of providing an organic semiconductor composition for improving the insulation reliability of an organic thin-film transistor without greatly reducing the mobility of the organic thin-film transistor, an organic thin-film transistor fabricated by using such an organic semiconductor composition, and an electronic paper and a display device using the organic thin-film transistor. This organic semiconductor composition includes an organic semiconductor material (A) and a polymer (B) containing a repeating unit represented by the general formula (B) below.

CHROMATOGRAPHY APPARATUS DIGITAL MONITORING SENSOR USING PRINTED THIN FILM TRANSISTOR ARRAY, CHROMATOGRAPHY APPARATUS INCLUDING SAME, AND METHOD FOR MANUFACTURING CHROMATOGRAPHY APPARATUS DIGITAL MONITORING SENSOR

The present invention relates to: a sensor capable of monitoring, by using a thin film transistor array capable of being manufactured by a roll-to-roll gravure printing process for enabling low priced mass production, an organic matter analysis by a digital value in chromatography for separating and analyzing a mixture containing two or more kinds of organic matter mixed therein; a chromatography apparatus including the same; and a method for manufacturing the same. The sensor according to the present invention is arranged in a column for the chromatography so as to track the separation of organic matter, and comprises: a substrate; and a thin film transistor array formed on the substrate, including a gate layer, a dielectric layer, an active layer, an insulating layer, and a source/drain layer, and having an array of M×N number of thin film transistors formed through the printing process, wherein the thin film transistor array has a passivation layer formed on the surface thereof so as ...

TRANSISTOR MANUFACTURING METHOD AND TRANSISTOR

A transistor manufacturing method includes: forming a first insulator layer of which formation material is a fluorine-containing resin, on a substrate having a source electrode, a drain electrode, and a semiconductor layer so as to cover the semiconductor layer; forming a second insulator layer to cover the first insulator layer; forming a base film on at least part of a surface of the second insulator layer; and after depositing a metal which is an electroless plating catalyst on a surface of the base film, forming a gate electrode on the surface of the base film by electroless plating, wherein the forming of the base film is performed by applying a liquid substance which is a formation material of the base film to the surface of the second insulator layer, and the second insulator layer has a higher lyophilic property with respect to the liquid substance than the first insulator layer.

Method of fabricating poly-crystalline silicon thin film and method of fabricating transistor using the same

A method of fabricating a poly-Si thin film and a method of fabricating a poly-Si TFT using the same are provided. The poly-Si thin film is formed at a low temperature using ICP-CVD. After the ICP-CVD, ELA is performed while increasing energy by predetermined steps. A poly-Si active layer and a SiO₂ gate insulating layer are deposited at a temperature of about 150° C. using ICP-CVD. The poly-Si has a large grain size of about 3000 Å or more. An interface trap density of the SiO₂ can be as high as 10¹¹/cm². A transistor having good electrical characteristics can be fabricated at a low temperature and thus can be formed on a heat tolerant plastic substrate.

Thin film transistor and manufacturing method thereof

The disclosure is related to a thin film transistor and a method of manufacturing the thin film transistor. The thin film transistor comprises a substrate, a first semiconductor layer, an etch stop layer and a second semiconductor layer stacked on a surface of the substrate, and a first via and a second via formed on the etch stop layer; a source and a drain formed separating from each other and the source and the drain overlapping two ends of the second semiconductor layer respectively, wherein the source connects the first semiconductor layer through the first via, and the drain connects the first semiconductor layer through the second via, a gate insulation layer formed on the source and the drain; and a gate formed on the gate insulation layer. The thin film transistor of the disclosure have a higher on-state current of the thin film transistor and a faster switching speed.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a pixel electrode and a transistor which includes a first gate electrode, a first insulating layer over the first gate electrode, a semiconductor layer over the first insulating layer, a second insulating layer over the semiconductor layer, and a second gate electrode. The pixel electrode and the second gate electrode are provided over the second insulating layer. The first gate electrode has a region overlapping with the semiconductor layer with the first insulating layer provided therebetween. The second gate electrode has a region overlapping with the semiconductor layer with the second insulating layer provided therebetween. A first region is at least part of a region where the second gate electrode overlaps with the semiconductor layer. A second region is at least part of a region where the pixel electrode is provided. The second insulating layer is thinner in the first region than in the second region.

Semiconductor device and method for manufacturing the same

The present invention provides a semiconductor device formed over an insulating substrate, typically a semiconductor device having a structure in which mounting strength to a wiring board can be increased in an optical sensor, a solar battery, or a circuit using a TFT, and which can make it mount on a wiring board with high density, and further a method for manufacturing the same. According to the present invention, in a semiconductor device, a semiconductor element is formed on an insulating substrate, a concave portion is formed on a side face of the semiconductor device, and a conductive film electrically connected to the semiconductor element is formed in the concave portion.

Single crystal silicon arrayed devices for display panels

A display panel is formed using essentially single crystal thin-film material that is transferred to substrates for display fabrication. Pixel arrays form light valves or switches that can be fabricated with control electronics in the thin-film material prior to transfer. The resulting circuit panel is than incorporated into a display panel with a light emitting or liquid crystal material to provide the desired display.

Color filter system for light emitting display panels

A display panel is formed using a single crystal thin-film material that may be transferred to substrates for display fabrication. Pixel arrays form light valves or switches that can be fabricated with control electronics in the thin-film material prior to transfer. The resulting circuit panel is then incorporated into a display panel with a light emitting or liquid crystal material to provide the desired display.

Method for manufacturing thin film transistor, liquid crystal display and electronic device both produced by the method

PCT No. PCT/JP97/01891 Sec. 371 Date Feb. 4, 1998 Sec. 102(e) Date Feb. 4, 1998 PCT Filed Jun. 4, 1997 PCT Pub. No. WO97/47046 PCT Pub. Date Dec. 11, 1997A method for making a highly reliable non-single-crystal silicon thin film transistor, in which an underlying SiO2 film 15 is formed on a glass substrate 14 and then a polycrystalline silicon layer 17 is formed thereon. After patterning the polycrystalline silicon layer 17, a gate SiO2 film 18 is formed by an ECR-PECVD process or a TEOS-PECVD process. A gate electrode 19 is formed and source and drain regions 20, 20 are formed by an ion doping process. After forming a SiO2 insulating interlevel film 21 and providing a contact hole 22, an electrode 23 composed of an Al-Si-Cu film is formed. Finally, it is subjected to wet annealing at a temperature of 350 DEG C. for 3 hours.

Liquid crystal display substrate having TFTS in both an image display area and in a peripheral circuit area

A liquid crystal display substrate including gate and drain bus lines that are electrically insulated from each other at cross areas, pixel electrodes between the cross areas, and first thin film transistors connecting corresponding drain bus lines and pixel electrodes. Each first thin film transistor includes a channel region where current flows in a first direction, and first and second impurity doped regions of, respectively, first and second impurity concentrations. The first and second doped regions sandwich the channel region. The second impurity concentration is higher than the first. Also, a second thin film transistor is formed in the peripheral circuit area, and includes a channel region where current flows in a second direction that is perpendicular to the first direction. Third impurity doped regions, disposed on both sides of the channel region, have a third impurity concentration.

Method of manufacturing transistor array

According to the present invention, a gate insulation film, a silicon film and silicon nitride film are laminated on a gate backing pad made of a gate metal film, and etching is carried out on the silicon nitride film such that it remains on the gate backing pad as a protective insulation film. Thus, the corrosion of the gate backing pad, which is caused as the etching solution penetrate the silicon film in defect, can be prevented. Further, a protective semiconductor layer formed by patterning the protective insulation film and the silicon film, is formed above the gate backing pad. Thus, the gate backing pad can be protected from the etching solution during the patterning of the pixel electrode made of ITO. Therefore, the disconnection of the gate backing pad can be prevented.

Thin-film transistor

A thin-film transistor includes a substrate, and a gate including a double-layered structure having first and second metal layers provided on the substrate, the first metal layer being wider than the second metal layer by 1 to 4 mum. A method of making such a thin-film transistor includes the steps of: depositing a first metal layer on a substrate, depositing a second metal layers directly on the first metal layer; forming a photoresist having a designated width on the second metal layer; patterning the second metal layer via isotropic etching using the photoresist as a mask; patterning the first metal layer by means of an anisotropic etching using the photoresist as a mask, the first metal layer being etched to have the designated width, thus forming a gate having a laminated structure of the first and second metal layers; and removing the photoresist.

Thin-film transistor and method of manufacturing thin-film transistor with tapered gate of 20 degrees or less

On a substrate, there is disposed a gate electrode having a section of a trapezoidal configuration expanded toward the substrate. The gate electrode is covered with a silicon nitride film having a thickness T1 of 400 Å, and a silicon oxide film having a thickness T2 of 1200 Åis formed on the silicon nitride film. A polycrystalline silicon film constructing an active region is formed on a gate insulating film constituted of the silicon nitride film and the silicon oxide film. By forming the silicon oxide film in a sufficient thickness of 1200 Åor more, and further forming the silicon nitride film 23 of 400 Åor more, a thin-film transistor cannot easily be influenced by a stepped portion formed by the gate electrode, and withstanding voltage of the gate insulating film of the thin-film transistor can be enhanced.

High Density electronic circuit modules

The invention relates to device processing, packaging and interconnects that will yield integrated electronic circuitry of higher density and complexity than can be obtained by using conventional multi-chip modules. Processes include the formation of complex multi-function circuitry on common module substrates using circuit tiles of silicon thin-films which are transferred, interconnected and packaged. Circuit modules using integrated transfer/interconnect processes compatible with extremely high density and complexity provide large-area active-matrix displays with on-board drivers and logic in a complete glass-based modules. Other applications are contemplated, such as, displays, microprocessor and memory devices, and communication circuits with optical input and output.

Thin film transistor structure and method for manufacturing the same

A thin film transistor (TFT) structure includes a metal oxide semiconductor layer, a gate, a source, a drain, a gate insulation layer, and a passivation layer. The metal oxide semiconductor layer has a crystalline surface which is constituted by a plurality of grains separated from one another. An indium content of the grains accounts for at least 50% of all metal elements of the metal oxide semiconductor layer. The gate is disposed on one side of the metal oxide semiconductor layer. The source and the drain are disposed on the other side of the metal oxide semiconductor layer. The gate insulation layer is disposed between the gate and the metal oxide semiconductor layer. The passivation layer is disposed on the gate insulation layer, and the crystalline surface of the metal oxide semiconductor layer is in direct contact with the gate insulation layer or the passivation layer.

Heating method, film forming method, semiconductor device manufacturing method, and film forming apparatus

There is provided heating method for heating a substrate having a germanium film or a silicon germanium film formed on a surface of the substrate, the method including: loading the substrate kept in an air atmosphere at least a predetermined time into a processing container; and heating the substrate in a state in which an interior of the processing container is kept in a hydrogen gas-containing atmosphere.

Semiconductor device and method of manufacturing the same

An object of the present invention is to provide a semiconductor device having high operation characteristic and reliability. The measures taken are: A pixel capacitor is formed between an electrode comprising anodic capable material over an organic resin film, an anodic oxide film of the electrode and a pixel electrode above. Since the anodic oxide film is anodically oxidized by applied voltage per unit time at 15V/min, there is no wrap around on the electrode, and film peeling can be prevented.

Transistor with asymmetric silicon germanium source region

The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.

Area Sensor and Display Apparatus Provided With An Area Sensor

An area sensor of the present invention has a function of displaying an image in a sensor portion by using light-emitting elements and a reading function using photoelectric conversion devices. Therefore, an image read in the sensor portion can be displayed thereon without separately providing an electronic display on the area sensor. Furthermore, a photoelectric conversion layer of a photodiode according to the present invention is made of an amorphous silicon film and an N-type semiconductor layer and a P-type semiconductor layer are made of a polycrystalline silicon film. The amorphous silicon film is formed to be thicker than the polycrystalline silicon film. As a result, the photodiode according to the present invention can receive more light.

Display device and electronic device including the same

One embodiment of the present invention provides a highly reliably display device in which a high mobility is achieved in an oxide semiconductor. A first oxide component is formed over a base component. Crystal growth proceeds from a surface toward an inside of the first oxide component by a first heat treatment, so that a first oxide crystal component is formed in contact with at least part of the base component. A second oxide component is formed over the first oxide crystal component. Crystal growth is performed by a second heat treatment using the first oxide crystal component as a seed, so that a second oxide crystal component is formed. Thus, a stacked oxide material is formed. A transistor with a high mobility is formed using the stacked oxide material and a driver circuit is formed using the transistor.

Semiconductor device and a method of manufacturing the same

A pixel TFT formed in a pixel region is formed on a first substrate by a channel etch type reverse stagger type TFT, and patterning of a source region and a drain region, and patterning of a pixel electrode are performed by the same photomask. A driver circuit formed by using TFTs having a crystalline semiconductor layer, and an input-output terminal dependent on the driver circuit, are taken as one unit. A plurality of units are formed on a third substrate, and afterward the third substrate is partitioned into individual units, and the obtained stick drivers are mounted on the first substrate.

Light emitting device

A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film. This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving.

Soi mos device having bts structure and manufacturing method thereof

The present invention discloses a SOI MOS device having BTS structure and manufacturing method thereof. The source region of the SOI MOS device comprises: two heavily doped N-type regions, a heavily doped P-type region formed between the two heavily doped N-type regions, a silicide formed above the heavily doped N-type regions and the heavily doped P-type region, and a shallow N-type region which is contact to the silicide; an ohmic contact is formed between the heavily doped P-type region and the silicide thereon to release the holes accumulated in body region of the SOI MOS device and eliminate floating body effects thereof without increasing the chip area and also overcome the disadvantages such as decreased effective channel width of the devices in the BTS structure of the prior art. The manufacturing method comprises steps of: forming a heavily doped P-type region via ion implantation, forming a metal layer above the source region and forming a silicide via the heat treatment between the metal layer and the Si underneath. The device in the present invention could be fabricated via simplified fabricating process with great compatibility with traditional CMOS technology.

Semiconductor device and method for fabricating the same

A semiconductor device includes a memory block including a transistor region and a memory region. A variable resistance layer of the memory region acts as a gate insulating layer in the transistor region.

Display substrate and method of manufacturing the same

A display substrate includes a gate line extending in a first direction on a base substrate, a data line on the base substrate and extending in a second direction crossing the first direction, a gate insulating layer on the gate line, a thin-film transistor and a pixel electrode. The thin-film transistor includes a gate electrode electrically connected the gate line, an oxide semiconductor pattern, and source and drain electrodes on the oxide semiconductor pattern and spaced apart from each other. The oxide semiconductor pattern includes a first semiconductor pattern including indium oxide and a second semiconductor pattern including indium-free oxide. The pixel electrode is electrically connected the drain electrode.

Semiconductor-on-insulator (soi) structure with selectively placed sub-insulator layer void(s) and method of forming the soi structure

Disclosed is a semiconductor-on-insulator (SOI) structure having sub-insulator layer void(s) selectively placed in a substrate so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device on an insulator layer and the second section may contain a second device on the insulator layer. Alternatively, the first and second sections may comprise different regions of the same device on an insulator layer. For example, in an SOI field effect transistor (FET), sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate. Also, disclosed is an associated method of forming such an SOI structure.

Method of fabricating display device

To improve the use efficiency of materials and provide a technique of fabricating a display device by a simple process. The method includes the steps of providing a mask on a conductive layer, forming an insulating film over the conductive layer provided with the mask, removing the mask to form an insulating layer having an opening; and forming a conductive film in the opening so as to be in contact with the exposed conductive layer, whereby the conductive layer and the conductive film can be electrically connected through the insulating layer. The shape of the opening reflects the shape of the mask. A mask having a columnar shape (e.g., a prism, a cylinder, or a triangular prism), a needle shape, or the like can be used.

Semiconductor integrated device

To reduce power consumption of a semiconductor integrated circuit and to reduce delay of the operation in the semiconductor integrated circuit, a plurality of sequential circuits included in a storage circuit each include a transistor whose channel formation region is formed with an oxide semiconductor, and a capacitor whose one electrode is electrically connected to a node that is brought into a floating state when the transistor is turned off. By using an oxide semiconductor for the channel formation region of the transistor, the transistor with an extremely low off-state current (leakage current) can be realized. Thus, by turning off the transistor in a period during which power supply voltage is not supplied to the storage circuit, the potential in that period of the node to which one electrode of the capacitor is electrically connected can be kept constant or almost constant. Consequently, the above objects can be achieved.

Diamond semiconductor element and process for producing the same

A process of producing a diamond thin-film includes implanting dopant into a diamond by an ion implantation technique, forming a protective layer on at least part of the surface of the ion-implanted diamond, and firing the protected ion-implanted diamond at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C. A process of producing a diamond semiconductor includes implanting dopant into each of two diamonds by an ion implantation technique and superimposing the two ion-implanted diamonds on each other such that at least part of the surfaces of each of the ion-implanted diamonds makes contact with each other, and firing the ion implanted diamonds at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C.

Contacts for Nanowire Field Effect Transistors

A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate stack around a portion of the nanowire, forming a capping layer on the gate stack, forming a spacer adjacent to sidewalls of the gate stack and around portions of nanowire extending from the gate stack, forming a hardmask layer on the capping layer and the first spacer, forming a metallic layer over the exposed portions of the device, depositing a conductive material over the metallic layer, removing the hardmask layer from the gate stack, and removing portions of the conductive material to define a source region contact and a drain region contact.

Thin film transistor and method for manufacturing thin film transistor

(1) Disclosed is a thin film transistor comprising elements, namely a source electrode, a drain electrode, a gate electrode, a channel layer and a gate insulating film, said thin film transistor being characterized in that the channel layer is formed of an indium oxide film that is doped with tungsten and zinc and/or tin. (2) Disclosed is a bipolar thin film transistor comprising elements, namely a source electrode, a drain electrode, a gate electrode, a channel layer and a gate insulating film, said bipolar thin film transistor being characterized in that the channel layer is a laminate of an organic material film and a metal oxide film that contains indium doped with at least one of tungsten, tin or titanium and has an electrical resistivity that is controlled in advance. (3) Disclosed is a method for manufacturing a thin film transistor comprising elements, namely a source electrode, a drain electrode, a gate electrode, a channel layer and a gate insulating film, said method for manufacturing a thin film transistor being characterized in that at least the channel layer or a part of the channel layer is formed by forming a metal oxide film by a sputtering process using an In-containing target without heating the substrate, and a heat treatment is carried out after forming the above-described elements on the substrate.

Visible sensing transistor, display panel and manufacturing method thereof

A display device includes an infrared sensing transistor and a visible sensing transistor. The visible sensing transistor includes a semiconductor on a substrate; an ohmic contact on the semiconductor; an etch stopping layer on the ohmic contact; a source electrode and a drain electrode on the etch stopping layer; a passivation layer on the source electrode and the drain electrode; and a gate electrode on the passivation layer. The etch stopping layer may be composed of the same material as the source electrode and the drain electrode. The infrared sensing transistor is similar to the visible sensing transistor except the etch stopping layer is absent.

Process to make metal oxide thin film transistor array with etch stopping layer

The present invention generally relates to thin film transistors (TFTs) and methods of making TFTs. The active channel of the TFT may comprise one or more metals selected from the group consisting of zinc, gallium, tin, indium, and cadmium. The active channel may also comprise nitrogen and oxygen. To protect the active channel during source-drain electrode patterning, an etch stop layer may be deposited over the active layer. The etch stop layer prevents the active channel from being exposed to the plasma used to define the source and drain electrodes. The etch stop layer and the source and drain electrodes may be used as a mask when wet etching the active material layer that is used for the active channel.

Semiconductor device, method for manufacturing same, and display device

The present invention provides a semiconductor device capable of suppressing a contact failure due to an increase in contact resistance, a production method of the semiconductor device, and a display device. The present invention provides a semiconductor device which includes a thin-film diode including a crystalline semiconductor layer which includes a cathode region and an anode region, a cathode electrode connected to the cathode region, and an anode electrode connected to the anode region, the thin-film diode, the cathode electrode, and the anode electrode being disposed on a substrate, and which is featured in that the crystalline semiconductor layer includes a first low-impurity-concentration region having an impurity concentration lower than the impurity concentration of the cathode region, in that the first low-impurity-concentration region is arranged adjacent to the cathode region, and in that the cathode electrode is in contact with an area of the cathode region, the area being within 3 μm from the boundary at which the cathode region is in contact with the first low-impurity-concentration region.

Ultra-thin body transistor and method for manufcturing the same

An ultra-thin body transistor and a method for manufacturing an ultra-thin body transistor are disclosed. The ultra-thin body transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source region and a drain region in the semiconductor substrate and on either side of the gate structure; in which the gate structure comprises a gate dielectric layer, a gate embedded in the gate dielectric layer, and a spacer on both sides of the gate; the ultra-thin body transistor further comprises: a body region and a buried insulated region located sequentially under the gate structure and in a well region; two ends of the body region and the buried insulated region are connected with the source region and the drain region respectively; and the body region is isolated from other regions in the well region by the buried insulated region under the body region. The ultra-thin body transistor has a thinner body region, which decreases the short channel effect. In the method for manufacturing an ultra-thin body transistor together with the replacement-gate process, the forming of the buried insulated region is self-aligned with the gate, which reduces the parasitic resistance under the spacer.

Electronic device, manufacturing method of electronic device, and sputtering target

A film formation is performed using a target in which a material which is volatilized more easily than gallium when heated at 400° C. to 700° C., such as zinc, is added to gallium oxide by a sputtering method with high mass-productivity which can be applied to a large-area substrate, such as a DC sputtering method or a pulsed DC sputtering method. This film is heated at 400° C. to 700° C., whereby the added material is segregated in the vicinity of a surface of the film. Another portion of the film has a decreased concentration of the added material and a sufficiently high insulating property; therefore, it can be used for a gate insulator of a semiconductor device, or the like.

Semiconductor device and method of manufacturing the same

It is an object to manufacture a semiconductor device in which a transistor including an oxide semiconductor has normally-off characteristics, small fluctuation in electric characteristics, and high reliability. First, first heat treatment is performed on a substrate, a base insulating layer is formed over the substrate, an oxide semiconductor layer is formed over the base insulating layer, and the step of performing the first heat treatment to the step of forming the oxide semiconductor layer are performed without exposure to the air. Next, after the oxide semiconductor layer is formed, second heat treatment is performed. An insulating layer from which oxygen is released by heating is used as the base insulating layer.

High Voltage Semiconductor Devices

In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.

Method for designing semiconductor device

A semiconductor device may be designed in the following manner. A stacked layer of a silicon oxide film and an organic film is provided over a substrate, deuterated water is contained in the organic film, and then a conductive film is formed in contact with the organic film. Next, an inert conductive material that does not easily generate a deuterium ion or a deuterium molecule is selected by measuring the amount of deuterium that exists in the silicon oxide film.

Modified graphene structures and methods of manufacture thereof

The present invention is directed to a modified graphene structure comprising at least one graphene sheet ( 1 ) and a self-assembled monolayer ( 2 ) of functional organic molecules ( 3 ) non-covalently bonded to the top and/or bottom basal planes of the graphene sheet and methods of manufacture thereof. The present invention is also directed to devices comprising the modified graphene structures, including but not limited to field-effect devices and biosensors, and to methods using the modified graphene structures.

Method for manufacturing semiconductor device

Electrical characteristics of transistors using an oxide semiconductor are greatly varied in a substrate, between substrates, and between lots, and the electrical characteristics are changed due to heat, bias, light, or the like in some cases. In view of the above, a semiconductor device using an oxide semiconductor with high reliability and small variation in electrical characteristics is manufactured. In a method for manufacturing a semiconductor device, hydrogen in a film and at an interface between films is removed in a transistor using an oxide semiconductor. In order to remove hydrogen at the interface between the films, the substrate is transferred under a vacuum between film formations. Further, as for a substrate having a surface exposed to the air, hydrogen on the surface of the substrate may be removed by heat treatment or plasma treatment.

Field effect transistor and method for manufacturing the same

A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A channel layer may be formed on a portion of the gate electrode, with source and drain regions formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions of the FET may be perpendicular to a surface of the semiconductor substrate.

Diketopyrrolopyrrole polymers for use in organic semiconductor devices

The present invention relates to polymers comprising one or more (repeating) unit(s) of the formula (I) which are characterized in that Ar 1 and Ar 1 ′ are independently of each other are an annulated (aromatic) heterocyclic ring system, containing at least one thiophene ring, which may be optionally substituted by one, or more groups, and their use as organic semiconductor in organic devices, especially in organic photovoltaics (solar cells) and photodiodes, or in a device containing a diode and/or an organic field effect transistor. The polymers according to the invention have excellent solubility in organic solvents and excellent film-forming properties. In addition, high efficiency of energy conversion, excellent field-effect mobility, good on/off current ratios and/or excellent stability can be observed, when the polymers according to the invention are used in organic field effect transistors, organic photovoltaics (solar cells) and photodiodes.

Semiconductor on insulator (xoi) for high performance field effect transistors

Semiconductor-on-insulator (XOI) structures and methods of fabricating XOI structures are provided. Single-crystalline semiconductor is grown on a source substrate, patterned, and transferred onto a target substrate, such as a Si/SiO 2 substrate, thereby assembling an XOI substrate. The transfer process can be conducted through a stamping method or a bonding method. Multiple transfers can be carried out to form heterogenous compound semiconductor devices. The single-crystalline semiconductor can be II-IV or III-V compound semiconductor, such as InAs. A thermal oxide layer can be grown on the patterned single crystalline semiconductor, providing improved electrical characteristics and interface properties. In addition, strain tuning is accomplished via a capping layer formed on the single-crystalline semiconductor before transferring the single-crystalline semiconductor to the target substrate.

Manufacturing method of semiconductor device

An object is to provide a technique by which a semiconductor device including a high-performance and high-reliable transistor is manufactured. A protective conductive film which protects an oxide semiconductor layer when a wiring layer is formed from a conductive layer is formed between the oxide semiconductor layer and the conductive layer, and an etching process having two steps is performed. In a first etching step, an etching is performed under conditions that the protective conductive film is less etched than the conductive layer and the etching selectivity of the conductive layer to the protective conductive film is high. In a second etching step, etching is performed under conditions that the protective conductive film is more easily etched than the oxide semiconductor layer and the etching selectivity of the protective conductive film to the oxide semiconductor layer is high.

Semiconductor device having decreased contact resistance

Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.

Graphene nanoribbons, method of fabrication and their use in electronic devices

The present disclosure provides a semiconductor structure including a nanoribbon-containing layer of alternating graphene nanoribbons separated by alternating insulating ribbons. The alternating graphene nanoribbons are parallel to a surface of an underlying substrate and, in some embodiments, might be oriented along crystallographic directions of the substrate. The alternating insulating ribbons may comprise hydrogenated graphene, i.e., graphane, fluorinated graphene, or fluorographene. The semiconductor structure mentioned above can be formed by selectively converting portions of an initial graphene layer into alternating insulating ribbons, while the non-converted portions of the initial graphene form the alternating graphene nanoribbons. Semiconductor devices such as, for example, field effect transistors, can be formed atop the semiconductor structure provided in the present disclosure.

Liquid crystal display device

A method of manufacturing, with high mass productivity, liquid crystal display devices having highly reliable thin film transistors with excellent electric characteristics is provided. In a liquid crystal display device having an inverted staggered thin film transistor, the inverted staggered thin film transistor is formed as follows: a gate insulating film is formed over a gate electrode; a microcrystalline semiconductor film which functions as a channel formation region is formed over the gate insulating film; a buffer layer is formed over the microcrystalline semiconductor film; a pair of source and drain regions are formed over the buffer layer; and a pair of source and drain electrodes are formed in contact with the source and drain regions so as to expose a part of the source and drain regions.

Semiconductor device and manufacturing method thereof

A semiconductor device having high operating performance and reliability, and a manufacturing method thereof are provided. An LDD region 207 provided in an n-channel TFT 302 forming a driving circuit enhances the tolerance for hot carrier injection. LDD regions 217 - 220 provided in an n-channel TFT (pixel TFT) 304 forming a pixel portion greatly contribute to the decrease in the OFF current value. Here, the LDD region of the n-channel TFT of the driving circuit is formed such that the concentration of the n-type impurity element becomes higher as the distance from an adjoining drain region decreases.

Semiconductor device and method for manufacturing the same

As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, there occurs a problem that it is difficult to mount an IC chip including a driver circuit for driving the gate and signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. The pixel portion and the driver portion are provided over the same substrate, whereby manufacturing cost can be reduced.

Oxide semiconductor, thin film transistor including the same and thin film transistor display panel including the same

An oxide semiconductor including: (A) at least one element of zinc (Zn) and tin (Sn); and (B) at least one element of arsenic (As), antimony (Sb), chromium (Cr), cerium (Ce), tantalum (Ta), neodymium (Nd), niobium (Nb), scandium (Sc), yttrium (Y), and hafnium (Hf), is provided.

Solution processed thin films and laminates, devices comprising such thin films and laminates, and method for their use and manufacture

Devices having a thin film or laminate structure comprising hafnium and/or zirconium oxy hydroxy compounds, and methods for making such devices, are disclosed. The hafnium and zirconium compounds can be doped, typically with other metals, such as lanthanum. Examples of electronic devices or components that can be made include, without limitation, insulators, transistors and capacitors. A method for patterning a device using the materials as positive or negative resists or as functional device components also is described. For example, a master plate for imprint lithography can be made. An embodiment of a method for making a device having a corrosion barrier also is described. Embodiments of an optical device comprising an optical substrate and coating also are described. Embodiments of a physical ruler also are disclosed, such as for accurately measuring dimensions using an electron microscope.

Semiconductor device and method of fabricating the same

There is provided a high quality liquid crystal panel having a thickness with high accuracy, which is designed, without using a particulate spacer, within a free range in accordance with characteristics of a used liquid crystal and a driving method, and is also provided a method of fabricating the same. The shape of a spacer for keeping a substrate interval constant is made such that it is a columnar shape, a radius R of curvature is 2 μm or less, a height H is 0.5 μm to 10 μm, a diameter is 20 μm or less, and an angle α is 65° to 115°. By doing so, it is possible to prevent the lowering of an opening rate and the lowering to of light leakage due to orientation disturbance.

Display device and manufacturing method of the same

A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a channel formation region, and an impurity region containing an impurity element of one conductivity type is selectively provided in a region which is not overlapped with source and drain electrodes, in the channel formation region of the microcrystalline semiconductor film.

Semiconductor film, semiconductor element, semiconductor device, and method for manufacturing the same

One of objects is to provide a semiconductor film having stable characteristics. Further, one of objects is to provide a semiconductor element having stable characteristics. Further, one of objects is to provide a semiconductor device having stable characteristics. Specifically, a structure which includes a seed crystal layer (seed layer) including crystals each having a first crystal structure, one of surfaces of which is in contact with an insulating surface, and an oxide semiconductor film including crystals growing anisotropically, which is on the other surface of the seed crystal layer (seed layer) may be provided. With such a heterostructure, electric characteristics of the semiconductor film can be stabilized.

Semiconductor device, manufacturing method thereof, and electronic device

In a thin film transistor, a gate insulating layer is formed on a gate electrode formed on an insulating substrate. Formed on the gate insulating layer is a semiconductor layer. Formed on the semiconductor layer are a source electrode and a drain electrode. A protective layer covers them, so that the semiconductor layer is blocked from an atmosphere. The semiconductor layer (active layer) is made of, e.g., a semiconductor containing polycrystalline ZnO to which, e.g., a group V element is added. This allows practical use of a semiconductor device which has an active layer made of zinc oxide and which includes an protective layer for blocking the active layer from an atmosphere.

Method for manufacturing soi wafer

A method for manufacturing an SOI wafer includes performing a flattening heat treatment on an SOI wafer under an atmosphere containing an argon gas, in which conditions of SOI wafer preparation are set so that a thickness of an SOI layer of the SOI wafer to be subjected to the flattening heat treatment is 1.4 or more times thicker than that of a BOX layer, and the thickness of the SOI layer is reduced to less than a thickness 1.4 times the thickness of the BOX layer by performing a sacrificial oxidation treatment on the SOI layer of the SOI wafer after the flattening heat treatment.

Oxide semiconductor film and semiconductor device

An oxide semiconductor film which has more stable electric conductivity is provided. Further, a semiconductor device which has stable electric characteristics and high reliability is provided by using the oxide semiconductor film. An oxide semiconductor film includes a crystalline region, and the crystalline region includes a crystal in which an a-b plane is substantially parallel with a surface of the film and a c-axis is substantially perpendicular to the surface of the film; the oxide semiconductor film has stable electric conductivity and is more electrically stable with respect to irradiation with visible light, ultraviolet light, and the like. By using such an oxide semiconductor film for a transistor, a highly reliable semiconductor device having stable electric characteristics can be provided.

Thin film transistor, method for manufacturing same, active matrix substrate, display panel and display device

The present invention provides a thin film transistor including an oxide semiconductor layer ( 4 ) for electrically connecting a signal electrode ( 6 a ) and a drain electrode ( 7 a ), the an oxide semiconductor layer being made from an oxide semiconductor; and a barrier layer ( 6 b ) made from at least one selected from the group consisting of Ti, Mo, W, Nb, Ta, Cr, nitrides thereof, and alloys thereof, the barrier layer ( 6 b ) being in touch with the signal electrode ( 6 a ) and the oxide semiconductor layer ( 4 ) and separating the signal electrode ( 6 a ) from the oxide semiconductor layer ( 4 ). Because of this configuration, the thin film transistor can form and maintain an ohmic contact between the first electrode and the channel layer, thereby being a thin film transistor with good properties.

Semiconductor device and fabrication method thereof

According to one embodiment, a fabrication method of a semiconductor device comprising forming a dummy gate with a gate length direction set to a [111] direction perpendicular to a [110] direction on a surface of a supporting substrate having Si 1-x Ge x (0≦x<0.5) with a crystal orientation perpendicular to the surface set to the [110] direction on the surface, forming source/drain regions and forming insulating films on side portions of the dummy gate. Next, the dummy gate is etched with using the insulating films as a mask, and a surface portion of the substrate between the source/drain regions is further etched. Next, a channel region formed of a III-V group semiconductor or Ge is grown between the source/drain regions by using the edge portions of the source/drain regions as seeds. Then, a gate electrode is formed above the channel region via a gate insulating film.

Mosfet and method for manufacturing the same

The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET comprises an SOI wafer, which comprises a bottom semiconductor substrate, a first buried insulating layer on the bottom semiconductor substrate, and a first semiconductor layer on the first buried insulating layer; a source region and a drain region which are formed in a second semiconductor layer over the SOI wafer, wherein there is a second buried insulating layer between the second semiconductor layer and the SOI wafer; a channel region, which is formed in the second semiconductor layer and located between the source region and the drain regions; and a gate stack, which comprises a gate dielectric layer on the second semiconductor layer and a gate conductor on the gate dielectric layer, wherein the MOSFET further comprises a backgate formed in a portion of the first semiconductor substrate below the channel region, the backgate having a non-uniform doping profile, and the second buried insulating layer serving as a gate dielectric layer of the backgate. The MOSFET has an adjustable threshold voltage by changing the polarity of dopants and/or the doping profile in the backgate. Leakage in the semiconductor device can be reduced.

Method of manufacturing display apparatus

Provided is a method of manufacturing a display apparatus, including forming a drive circuit and a light-emitting portion on a substrate in which the forming the light-emitting portion includes forming a transparent anode electrode for applying a charge to an emission layer, forming a first coating layer and a second coating layer on the transparent anode electrode, removing the first coating layer by etching using the second coating layer as a mask, and forming a layer including the emission layer on a part of the transparent anode electrode from which the first coating layer is removed. A surface of the transparent anode electrode becomes as clean as a surface cleaned with ultraviolet irradiation.

Thin film transistor (tft) having copper electrodes

A TFT structure is provided in which an oxidic semiconductor is used in combination with an electrode material based on a Cu alloy.

Pseudo Butted Junction Structure for Back Plane Connection

Butted p-n junctions interconnecting back gates in an SOI process, methods for making butted p-n junctions, and design structures. The butted junction includes an overlapping region formed in the bulk substrate by overlapping the mask windows of the ion-implantation masks used to form the back gates. A damaged region may be selectively formed to introduce mid-gap energy levels in the semiconductor material of the overlapping region employing one of the implantation masks used to form the back gates. The damage region causes the butted junction to be leaky and conductively couples the overlapped back gates to each other and to the substrate. Other back gates may be formed that are floating and not coupled to the substrate.

Insulating region for a semiconductor substrate

An insulating region for a semiconductor wafer and a method of forming same. The insulating region can include a tri-layer structure of silicon oxide, boron nitride and silicon oxide. The insulating region may be used to insulate a semiconductor device layer from an underlying bulk semiconductor substrate. The insulating region can be formed by coating the sides of a very thin cavity with silicon oxide, and filling the remainder of the cavity between the silicon oxide regions with boron nitride.

Semiconductor device

A semiconductor device receiving as input a radio frequency signal having a frequency of 500 MHz or more and a power of 20 dBm or more is provided. The semiconductor device includes: a silicon substrate; a silicon oxide film formed on the silicon substrate; a radio frequency interconnect provided on the silicon oxide film and passing the radio frequency signal; a fixed potential interconnect provided on the silicon oxide film and placed at a fixed potential; and an acceptor-doped layer. The acceptor-doped layer is formed in a region of the silicon substrate. The region is in contact with the silicon oxide film. The acceptor-doped layer is doped with acceptors.

Channel-etch type thin film transistor and method of manufacturing the same

A channel layer is formed on a substrate by using an oxide semiconductor and then a sacrificial layer of an oxide containing In, Zn and Ga and representing an etching rate greater than the etching rate of the oxide semiconductor is formed on the channel layer. Thereafter, a source electrode and a drain electrode are formed on the sacrificial layer and the sacrificial layer exposed between the source electrode and the drain electrode is removed by means of wet etching.

Semiconductor device and manufacturing method thereof

A semiconductor device capable of high speed operation is provided. Further, a highly reliable semiconductor device is provided. An oxide semiconductor having crystallinity is used for a semiconductor layer of a transistor. A channel formation region, a source region, and a drain region are formed in the semiconductor layer. The source region and the drain region are formed in such a manner that one or more of elements selected from rare gases and hydrogen are added to the semiconductor layer by an ion doping method or an ion implantation method with the use of a channel protective layer as a mask.

Thin-film transistor substrate and method of manufacturing the same

A thin-film transistor (“TFT”) substrate includes a metal wiring including copper or a copper alloy on a substrate, an inorganic layer on an upper surface and side surfaces of the metal wiring to surround the metal wiring, the inorganic layer in direct contact with the metal wiring, and a planarization layer on the inorganic layer and in direct contact with the inorganic layer.

Transistor and Method for Manufacturing the Same

The invention relates to a transistor and a method for manufacturing the transistor. The transistor according to an embodiment of the invention may comprise: a substrate which comprises at least a back gate of the transistor, an insulating layer and a semiconductor layer stacked sequentially, wherein the back gate of the transistor is used for adjusting the threshold voltage of the transistor; a gate stack formed on the semiconductor layer, wherein the gate stack comprises a gate dielectric and a gate electrode formed on the gate dielectric; a spacer formed on sidewalls of the gate stack; and a source region and a drain region located on both sides of the gate stack, respectively, wherein the height of the gate stack is lower than the height of the spacer. The transistor enables the height of the gate stack to be reduced and therefore the performance of the transistor is improved.

Method and Apparatus for Use in Improving Linearity of MOSFETs Using an Accumulated Charge Sink

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOT MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Transistor including multiple reentrant profiles

A transistor includes a substrate. A first electrically conductive material layer is positioned on the substrate. A second electrically conductive material layer is in contact with and positioned on the first electrically conductive material layer. The second electrically conductive material layer includes a reentrant profile. The second electrically conductive material layer also overhangs the first electrically conductive material layer.

Manufacturing method of the semiconductor device

The semiconductor device is manufactured through the following steps: after first heat treatment is performed on an oxide semiconductor film, the oxide semiconductor film is processed to form an oxide semiconductor layer; immediately after that, side walls of the oxide semiconductor layer are covered with an insulating oxide; and in second heat treatment, the side surfaces of the oxide semiconductor layer are prevented from being exposed to a vacuum and defects (oxygen deficiency) in the oxide semiconductor layer are reduced.

Method of Fabricating Silicon Quantum Dot Layer and Device Manufactured Using the Same

Disclosed are a method of fabricating a silicon quantum dot layer and a device manufactured using the same. A first capping layer is formed on a substrate, and a silicon-containing precursor layer is formed on the first capping layer. A second capping layer is formed on the silicon-containing precursor layer. The first capping layer, the silicon-containing precursor layer, and the second capping layer are irradiated to convert the silicon-containing precursor layer into a stack including a first poly-crystalline silicon layer, a silicon quantum dot layer on the first poly-crystalline silicon layer, and a second poly-crystalline silicon layer on the silicon quantum dot layer.

Graphene Devices and Silicon Field Effect Transistors in 3D Hybrid Integrated Circuits

A three dimensional integrated circuit includes a silicon substrate, a first source region disposed on the substrate, a first drain region disposed on the substrate, a first gate stack portion disposed on the substrate, a first dielectric layer disposed on the first source region, the first drain region, the first gate stack portion, and the substrate, a second dielectric layer formed on the first dielectric layer, a second source region disposed on the second dielectric layer, a second drain region disposed on the second dielectric layer, and a second gate stack portion disposed on the second dielectric layer, the second gate stack portion including a graphene layer.

Thin film transistor array panel

A thin film transistor array panel includes: an substrate; a gate line positioned on the substrate; a data line intersecting the gate line; a thin film transistor connected to the gate line and the data line; a gate insulating layer between the gate electrode of the thin film transistor and the semiconductor of the thin film transistor; a pixel electrode connected to the thin film transistor; and a passivation layer positioned between the pixel electrode and the thin film transistor, wherein at least one of the gate insulating layer and the passivation layer includes a silicon nitride layer, and the silicon nitride layer includes hydrogen content at less than 2×10 22 cm 3 or 4 atomic %.

Vertical channel type non-volatile memory device and method for fabricating the same

A method for fabricating a vertical channel type non-volatile memory device including forming a source region, alternately forming a plurality of interlayer dielectric layers and a plurality of conductive layers for a gate electrode over a substrate with the source region formed therein, forming a trench exposing the source region by etching the plurality of interlayer dielectric layers and the plurality of conductive layers for a gate electrode, and siliciding the conductive layers for a gate electrode and the source region that are exposed through the trench.

Display device and method for manufacturing thereof

An object is to provide a system-on-panel display device including a display portion and a peripheral circuit for controlling display on the display portion over one substrate, which can operate more accurately. The display device has a display portion provided with a pixel portion including a plurality of pixels and a peripheral circuit portion for controlling display on the display portion, which are provided over a substrate. Each of the display portion and the peripheral circuit portion includes a plurality of transistors. For semiconductor layers of the transistors, single crystal semiconductor materials are used.

Field effect device provided with a localized dopant diffusion barrier area and fabrication method

The field effect device comprises a sacrificial gate electrode having side walls covered by lateral spacers formed on a semiconductor material film. The source/drain electrodes are formed in the semiconductor material film and are arranged on each side of the gate electrode. A diffusion barrier element is implanted through the void left by the sacrificial gate so as to form a modified diffusion area underneath the lateral spacers. The modified diffusion area is an area where the mobility of the doping impurities is reduced compared with the source/drain electrodes.

Semiconductor device and method for manufacturing same

A semiconductor device includes: a gate electrode ( 3 ) arranged on a substrate ( 1 ); a gate insulating layer ( 5 ) deposited over the gate electrode ( 3 ); an island of an oxide semiconductor layer ( 7 ) formed on the gate insulating layer ( 5 ) and including a channel region ( 7 c ) and first and second contact regions ( 7 s , 7 d ) located on right- and left-hand sides of the channel region ( 7 c ); a source electrode ( 11 ) electrically connected to the first contact region ( 7 s ); a drain electrode ( 13 ) electrically connected to the second contact region ( 7 d ); and a protective layer ( 9 ) which is arranged on, and in contact with, the oxide semiconductor layer ( 7 ). The protective layer ( 9 ) covers the channel region ( 7 c ) on the surface of the oxide semiconductor layer ( 7 ), the sidewalls ( 7 e ) thereof located in a channel width direction with respect to the channel region ( 7 c ), and other portions ( 7 f ) thereof between the channel region ( 7 c ) and the sidewalls ( 7 e ). As a result, the hysteresis characteristic of a TFT that uses an oxide semiconductor can be improved and its reliability can be increased.

Semiconductor device including high field regions and related method

A semiconductor device is disclosed. In an embodiment, a semiconductor device includes a N-well within a P-well in a silicon layer, the silicon layer positioned atop a buried oxide layer of a silicon-on-insulator (SOI) substrate; a first source region and a second source region within a portion of the P-well; a first drain region and a second drain region within a portion of the P-well and within a portion of the N-well; and a gate positioned atop the N-well, wherein a lateral high field region is generated between the N-well and the P-well and a vertical high field region is generated between the gate and the N-well. A related method is disclosed.

Method and apparatus for fabricating or altering microstructures using local chemical alterations

A method and apparatus for fabricating or altering a microstructure use means for heating to facilitate a local chemical reaction that forms or alters the submicrostructure.

Design Structure for High Density Stable Static Random Access Memory

A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit includes a plurality of bit line structures, a plurality of word line structures intersecting said plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at said plurality of cell locations, each of said cells being selectively coupled to a corresponding bit line structure under control of a corresponding word line structure, each of said cells comprising a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor, wherein said at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of said bit line structures, and said at least first p-type field effect transistor is formed with a relatively thin buried oxide layer.

Semiconductor device, liquid crystal display device having semiconductor device, and method for producing semiconductor device

Disclosed is an electrode film which does not exfoliate from, or diffuse into, an oxide semiconductor or an oxide thin film. An electrode layer comprises a highly adhesive barrier film being a Cu—Mg—Al thin film and a copper thin film; and an oxide semiconductor and an oxide thin film contact with the highly adhesive barrier film. With the highly adhesive barrier film having magnesium in a range of at least 0.5 at % but at most 5 at % and aluminum at least 5 at % but at most 15 at % when the total number of atoms of copper, magnesium, and aluminum is 100 at %, the highly adhesive barrier film has both adhesion and barrier properties. The electrode layer is suitable because a source electrode layer and a drain electrode layer contact the oxide semiconductor layer. A stopper layer having an oxide may be provided on a layer under the electrode layer.

Semiconductor device having a metal oxide channel

A semiconductor device includes a metal oxide channel and methods for forming the same. The metal oxide channel includes indium, gallium, and zinc.

Semiconductor device

It is an object to reduce concentration of an electric field on an end of a drain electrode of a semiconductor device. A semiconductor device includes an oxide semiconductor film including a first region and a second region; a pair of electrodes which is partly in contact with the oxide semiconductor film; a gate insulating film over the oxide semiconductor film; and a gate electrode that overlaps with part of one of the pair of electrodes and the first region with the gate insulating film provided therebetween. At least part of the first region and part of the second region are between the pair of electrodes. The gate electrode does not overlap with the other of the pair of electrodes.

MOSFET with a Nanowire Channel and Fully Silicided (FUSI) Wrapped Around Gate

Nanowire-channel metal oxide semiconductor field effect transistors (MOSFETs) and techniques for the fabrication thereof are provided. In one aspect, a MOSFET includes a nanowire channel; a fully silicided gate surrounding the nanowire channel; and a raised source and drain connected by the nanowire channel. A method of fabricating a MOSFET is also provided.

Graphene-encapsulated nanoparticle-based biosensor for the selective detection of biomarkers

A field effect transistor (FET) with a source electrode and a drain electrode distanced apart from each other on a semi-conductor substrate, and a gate electrode consisting of a uniform layer of reduced graphene oxide encapsulated semiconductor nanoparticles (rGO-NPs), wherein the gate electrode is disposed between and contacts both the source and drain electrodes. Methods of making and assay methods using the FETs are also disclosed, including methods in which the rGO-NPs are functionalized with binding partners for biomarkers.

Display device and manufacturing method of the same

Disclosed is a display device including: a gate electrode; a semiconductor layer formed into an island shape on an upper side of the gate electrode; a side wall oxide film formed on a lateral surface of the semiconductor layer; and a drain electrode and a source electrode formed on an upper side of the semiconductor layer extending from a lateral side of the semiconductor layer, wherein the side wall oxide film has a thickness of 2.1 nm or more.

Semiconductor device and method for manufacturing the same

A semiconductor device includes an oxide semiconductor film including a pair of first regions, a pair of second regions, and a third region; a pair of electrodes in contact with the oxide semiconductor film; a gate insulating film over the oxide semiconductor film; and a gate electrode provided between the pair of electrodes with the gate insulating film interposed therebetween. The pair of first regions overlap with the pair of electrodes, the third region overlaps with the gate electrode, and the pair of second regions are formed between the pair of first regions and the third region. The pair of second regions and the third region each contain nitrogen, phosphorus, or arsenic. The pair of second regions have a higher element concentration than the third region.

Fully-depleted son

A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a semiconductor substrate, an insulating layer, a first semiconductor layer, a dielectric layer, a second semiconductor layer, a source and drain junction, a gate, and a spacer. The method includes the steps of forming a semiconductor substrate, forming a shallow trench isolation layer, growing a first epitaxial layer, growing a second epitaxial layer, forming a gate, forming a spacer, performing a reactive ion etching, removing a portion of the first epitaxial layer, filling the void with a dielectric, etching back a portion of the dielectric, growing a silicon layer, implanting a source and drain junction, and forming an extension.

Semiconductor device

Solved is a problem of attenuation of output amplitude due to a threshold value of a TFT when manufacturing a circuit with TFTs of a single polarity. In a capacitor ( 105 ), a charge equivalent to a threshold value of a TFT ( 104 ) is stored. When a signal is inputted thereto, the threshold value stored in the capacitor ( 105 ) is added to a potential of the input signal. The thus obtained potential is applied to a gate electrode of a TFT ( 101 ). Therefore, it is possible to obtain the output having a normal amplitude from an output terminal (Out) without causing the amplitude attenuation in the TFT ( 101 ).

Oxide semiconductor film and semiconductor device

Provided is an oxide semiconductor film which has more stable electric characteristics and essentially consists of indium zinc oxide. In addition, provided is a highly reliable semiconductor device which has stable electric characteristics by using the oxide semiconductor film. The oxide semiconductor film essentially consisting of indium zinc oxide has a hexagonal crystal structure in which the a-b plane is substantially parallel to a surface of the oxide semiconductor film and a rhombohedral crystal structure in which the a-b plane is substantially parallel to the surface of the oxide semiconductor film.

Semiconductor device and method for manufacturing the same

In the transistor including an oxide semiconductor film, a gate insulating film of the transistor including an oxide semiconductor film has a stacked-layer structure of the hydrogen capture film and the hydrogen permeable film. At this time, the hydrogen permeable film is formed on a side which is in contact with the oxide semiconductor film, and the hydrogen capture film is formed on a side which is in contact with a gate electrode. After that, hydrogen released from the oxide semiconductor film is transferred to the hydrogen capture film through the hydrogen permeable film by the heat treatment.

Thin film transistor

A thin film transistor (TFT) and a fabricating method thereof are provided. The TFT includes a channel layer, an ohmic contact layer, a dielectric layer, a source, a drain, a gate, and a gate insulating layer. The channel layer has an upper surface and a sidewall. The ohmic contact layer is disposed on a portion of the upper surface of the channel layer. The dielectric layer is disposed on the sidewall of the channel layer, and does not overlap with the ohmic contact layer. The source and the drain are disposed on portions of the ohmic contact layer and the dielectric layer. A portion of dielectric layer is not covered by the source or the drain. The gate is above or below the channel layer. The gate insulating layer is disposed between the gate and the channel layer.

Thin film transistor substrate, method for manufacturing the same, and display device

An active matrix substrate ( 20 a ) includes a gate electrode ( 11 aa ), a gate insulating layer ( 12 ) covering the gate electrode ( 11 aa ), an oxide semiconductor layer ( 13 a ) provided on the gate insulating layer (12) and having a channel region (C), a source electrode ( 16 aa ) and a drain electrode ( 16 b ) provided on the oxide semiconductor layer ( 13 a ), an interlayer insulating film ( 17 ) covering the oxide semiconductor layer ( 13 a ), the source electrode ( 16 aa ), and the drain electrode ( 16 b ), and a planarization film ( 18 ) provided on the interlayer insulating film ( 17 ). An opening (Ca) reaching the interlayer insulating film ( 17 ) is formed at a portion of the planarization film ( 18 ) which is located over the channel region (C).

Electro-optical device and electronic device

An object of the present invention is to provide an EL display device, which has a high operating performance and reliability. A third passivation film 45 is disposed under an EL element 203 which comprises a pixel electrode (anode) 46 , an EL layer 47 and a cathode 48 , to make a structure in which heat generated by the EL element 203 is radiated. Further, the third passivation film 45 prevents alkali metals within the EL element 203 from diffusing into the TFTs side, and prevents moisture and oxygen of the TFTs side from penetrating into the EL element 203 . More preferably, heat radiating effect is given to a fourth passivation film 50 to make the EL element 203 to be enclosed by heat radiating layers.

Method for controlling the electrical conduction between two metallic portions and associated device

A method for controlling the electrical conduction between two electrically conductive portions may include placing of an at least partially ionic crystal between the two electrically conductive portions. The crystal may include at least one surface region coupled to the two electrically conductive portions. The surface region is insulating under the application of an electrical field to the surface region, and electrically conductive in the absence of the electrical field. An application or not of an electrical field to the at least one surface region reduces or establishes the electrical conduction.

Graphene electronic device and method of fabricating the same

The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.

Thin film transistor, organic luminescence display including the same, and method of manufacturing the organic luminescence display

A thin film transistor (TFT) including a substrate; a gate electrode formed over the substrate, an active layer insulated from the gate electrode by using a gate insulation film; an etch stop layer which is formed over the active layer and includes first and second holes for exposing the active layer; a first electrode; and a second electrode including a first part and a second part. The first part is formed over the etch stop layer, and the second part is received in the second hole, contacts the active layer directly, and connects the first part to the active layer. At least one portion of the first part of the second electrode overlaps with the gate electrode. The second part of the second electrode does not overlap with and is separated from the gate electrode.

Manufacturing method of semiconductor device

To provide a highly reliable semiconductor device manufactured by giving stable electric characteristics to a semiconductor device including an oxide semiconductor. In a manufacturing process of a transistor, an oxide semiconductor layer, a source electrode layer, a drain electrode layer, a gate insulating film, a gate electrode layer, and an aluminum oxide film are formed in this order, and then heat treatment is performed on the oxide semiconductor layer and the aluminum oxide film, whereby an oxide semiconductor layer from which an impurity containing a hydrogen atom is removed and which includes a region containing oxygen more than the stoichiometric proportion is formed. In addition, when the aluminum oxide film is formed, entry and diffusion of water or hydrogen into the oxide semiconductor layer from the air due to heat treatment in a manufacturing process of a semiconductor device or an electronic appliance including the transistor can be prevented.

Oxide thin film transistor and method of fabricating the same

An oxide thin film transistor (TFT) and its fabrication method are disclosed. In a TFT of a bottom gate structure using amorphous zinc oxide (ZnO)-based semiconductor as an active layer, source and drain electrodes are formed, on which the active layer made of oxide semiconductor is formed to thus prevent degeneration of the oxide semiconductor in etching the source and drain electrodes.

Semiconductor device and method for manufacturing semiconductor device

A semiconductor device having a transistor including an oxide semiconductor film is disclosed. In the semiconductor device, the oxide semiconductor film is provided along a trench formed in an insulating layer. The trench includes a lower end corner portion and an upper end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, the upper end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the upper end corner portion.

Thin film transistor substrate, method of manufacturing the same, and display apparatus having the same

In a method of manufacturing a thin film transistor substrate, a semiconductor pattern is formed on a substrate, a first etch stop layer and a second etch stop layer are sequentially formed on the semiconductor pattern, and the second etch stop layer and the first etch stop layer are sequentially patterned to form a second etch stop pattern and a first etch stop pattern. Thus, when the second etch stop layer is patterned using an etchant, the first etch stop layer covers the semiconductor pattern, thereby preventing the semiconductor pattern from being etched by the etchant.

Semiconductor device

To provide a highly reliable semiconductor device. To provide a semiconductor device which prevents a defect and achieves miniaturization. An oxide semiconductor layer in which the thickness of a region serving as a source region or a drain region is larger than the thickness of a region serving as a channel formation region is formed in contact with an insulating layer including a trench. In a transistor including the oxide semiconductor layer, variation in threshold voltage, degradation of electric characteristics, and shift to normally on can be suppressed and source resistance or drain resistance can be reduced, so that the transistor can have high reliability.

Photomask and Method for Fabricating Source/Drain Electrode of Thin Film Transistor

A method is provided for fabricating source/drain electrodes of a thin film transistor. The method generally provides a substrate having a first gate electrode and a second gate electrode adjacent and electrically connected. The method further provides coating a photoresist layer on the metal layer, and performing an exposure process on the photoresist layer by a photomask. The method further performs a development process on the exposed photoresist layer to form a photoresist pattern layer with different thicknesses on the metal layer, and then etches the metal layer using the photoresist pattern layer as an etch mask, to form a pair of first source/drain electrodes on the first gate electrode and a pair of second source/drain electrodes on the second gate electrode.

Nanowire Tunnel Field Effect Transistors

A nanowire tunnel field effect transistor (FET) device includes a channel region including a silicon portion having a first distal end and a second distal end, the silicon portion is surrounded by a gate structure disposed circumferentially around the silicon portion, a drain region including an doped silicon portion extending from the first distal end, a portion of the doped silicon portion arranged in the channel region, a cavity defined by the second distal end of the silicon portion and an inner diameter of the gate structure, and a source region including a doped epi-silicon portion epitaxially extending from the second distal end of the silicon portion in the cavity, a first pad region, and a portion of a silicon substrate.

Manufacturing method of semiconductor device

A semiconductor device using an oxide semiconductor is provided with stable electric characteristics to improve the reliability. In a manufacturing process of a transistor including an oxide semiconductor film, an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a first crystalline oxide semiconductor film) is formed; oxygen is added to the oxide semiconductor film to amorphize at least part of the oxide semiconductor film, so that an amorphous oxide semiconductor film containing an excess of oxygen is formed; an aluminum oxide film is formed over the amorphous oxide semiconductor film; and heat treatment is performed thereon to crystallize at least part of the amorphous oxide semiconductor film, so that an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a second crystalline oxide semiconductor film) is formed.

Contacts for Nanowire Field Effect Transistors

A nanowire field effect transistor (FET) device includes a channel region including a silicon nanowire portion having a first distal end extending from the channel region and a second distal end extending from the channel region, the silicon portion is partially surrounded by a gate stack disposed circumferentially around the silicon portion, a source region including the first distal end of the silicon nanowire portion, a drain region including the second distal end of the silicon nanowire portion, a metallic layer disposed on the source region and the drain region, a first conductive member contacting the metallic layer of the source region, and a second conductive member contacting the metallic layer of the drain region.

Method of manufacturing semiconductor device

A highly reliable transistor which includes an oxide semiconductor and has high field-effect mobility and in which a variation in threshold voltage is small is provided. By using the transistor, a high-performance semiconductor device, which has been difficult to realize, is provided. The transistor includes an oxide semiconductor film which contains two or more kinds, preferably three or more kinds of elements selected from indium, tin, zinc, and aluminum. The oxide semiconductor film is formed in a state where a substrate is heated. Further, oxygen is supplied to the oxide semiconductor film with an adjacent insulating film and/or by ion implantation in a manufacturing process of the transistor, so that oxygen deficiency which generates a carrier is reduced as much as possible. In addition, the oxide semiconductor film is highly purified in the manufacturing process of the transistor, so that the concentration of hydrogen is made extremely low.

Semiconductor device and manufacturing method thereof

In a transistor including a wide band gap semiconductor layer as a semiconductor layer, a wide band gap semiconductor layer is separated into an island shape by an insulating layer with passivation properties for preventing atmospheric components from permeating. The edge portion of the island shape wide band gap semiconductor layer is in contact with the insulating film; thus, moisture or atmospheric components can be prevented from entering from the edge portion of the semiconductor layer to the wide band gap semiconductor layer.

Display device and electronic device

An object is, in a structure where switch circuits in a signal line driver circuit is placed over the same substrate as a pixel portion, to reduce the size of transistors in the switch circuits and to reduce load in the circuits during charging and discharging of signal lines due to the supply of data. A display device is provided which includes a pixel portion receiving a video signal, and a signal line driver circuit including a switch circuit portion configured to control output of the video signal to the pixel portion. The switch circuit portion includes a transistor over an insulating substrate. The transistor has a field-effect mobility of at least 80 cm 2 /Vs or more. The transistor includes an oxide semiconductor layer.

Amorphous oxide thin film, thin film transistor using the same, and method for manufacturing the same

A thin film transistor using an amorphous oxide thin film for an active layer, wherein: the amorphous oxide thin film includes, as main components, indium (In), oxygen (O), and a metal element (M) selected from the group consisting of silicon (Si), aluminum (Al), germanium (Ge), tantalum (Ta), magnesium (Mg) and titanium (Ti); an atomic ratio of M to In in this amorphous oxide thin film is 0.1 or more and 0.4 or less; and carrier density in the amorphous oxide thin film is 1×10 15 cm −3 or more and 1×10 19 cm −1 or less.

Method for manufacturing semiconductor device

Stable electrical characteristics and high reliability are provided to a semiconductor device including an oxide semiconductor. In a process of manufacturing a transistor including an oxide semiconductor film, an amorphous oxide semiconductor film is formed, and oxygen is added to the amorphous oxide semiconductor film, so that an amorphous oxide semiconductor film containing excess oxygen is formed. Then, an aluminum oxide film is formed over the amorphous oxide semiconductor film, and heat treatment is performed thereon to crystallize at least part of the amorphous oxide semiconductor film, so that a crystalline oxide semiconductor film is formed.

Method of Manufacturing Thin Film Transistor

The object of the present invention is to form a low-concentration impurity region with good accuracy in a top gate type TFT. Phosphorus is added to a semiconductor layer by using a pattern made of a conductive film as a mask to form an N-type impurity region in a self-alignment manner. A positive photoresist is applied to a substrate so as to cover the pattern and then is exposed to light applied to the back of the substrate and then is developed, whereby a photoresist 110 is formed. The pattern is etched by using the photoresist pattern as an etching mask to form a gate electrode. A channel forming region, a source region, a drain region, and low-concentration impurity regions, are formed in the semiconductor layer in a self-alignment manner by using the gate electrode as a doping mask.

Semiconductor device and method of producing the same

It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor. The object is achieved by a semiconductor device production method which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate; forming a sidewall-shaped dielectric film on a sidewall of the gate; and forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer and on the second-conductive-type semiconductor layer formed underneath the pillar-shaped first-conductive-type semiconductor layer.