Etchant composition, and method of fabricating metal pattern and thin film transistor array panel using the same

An etchant composition is provided. The etchant composition includes about 40 to about 65 wt % of phosphoric acid, about 2 to about 5 wt % of nitric acid, about 2 to about 20 wt % of acetic acid, about 0.1 to about 2 wt % of a compound containing phosphate, about 0.1 to about 2 wt % of a compound simultaneously containing an amino group and a carboxyl group, and a remaining weight percent of water for the total weight of the composition.

Display substrate and method of manufacturing the same

A display substrate includes; a gate pattern including a gate electrode disposed on a substrate, a gate insulation layer disposed on the substrate and the gate pattern, an insulation pattern including; a first thickness part disposed on a first area of the gate insulation layer overlapping the gate electrode and a second thickness part disposed on a second area of the gate insulation layer adjacent to the first area, an oxide semiconductor pattern disposed on the first thickness part of the first area, an etch stopper disposed on the oxide semiconductor pattern, a source pattern including a source electrode and a drain electrode which contact the oxide semiconductor pattern, and a pixel electrode which contacts the drain electrode.

Thin film transistor panel having an etch stopper on semiconductor

A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

METHOD OF MANUFACTURING COLOR FILTER SUBSTRATE AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE

A method of manufacturing a color filter substrate includes forming a plurality of trenches having a predetermined depth by etching a surface of a transparent substrate, disposing a color filter material in the plurality of trenches to form a color filter layer, and forming a transparent electrode on the transparent substrate including the color filter layer therein.

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

A display device includes a gate pattern, a semiconductor pattern, a source pattern and a pixel electrode are provided. The gate pattern is formed on a base substrate and includes a gate line and a gate electrode. The semiconductor pattern is formed on the base substrate having the gate pattern and includes an oxide semiconductor. The source pattern is formed from a data metal layer and formed on the base substrate having the semiconductor pattern, and includes a data line, a source electrode and a drain electrode. The data metal layer includes a first copper alloy layer, and a lower surface of the data metal layer substantially coincides with an upper surface of the semiconductor pattern. The pixel electrode is formed on the base substrate having the source pattern and electrically connected to the drain electrode. Thus, manufacturing processes may be simplified, and reliability may be improved.

Thin film transistor panel having an etch stopper on semiconductor

A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Display substrate and method of manufacturing the same

A display substrate includes a gate line extending in a first direction on a base substrate, a data line on the base substrate and extending in a second direction crossing the first direction, a gate insulating layer on the gate line, a thin-film transistor and a pixel electrode. The thin-film transistor includes a gate electrode electrically connected the gate line, an oxide semiconductor pattern, and source and drain electrodes on the oxide semiconductor pattern and spaced apart from each other. The oxide semiconductor pattern includes a first semiconductor pattern including indium oxide and a second semiconductor pattern including indium-free oxide. The pixel electrode is electrically connected the drain electrode.

DISPLAY SUBSTRATE AND METHOD OF FABRICATING THE SAME

A display substrate including a lower common electrode disposed on a substrate, an insulating layer disposed on the lower common electrode, a gate pattern including a gate electrode disposed on the insulating layer and a common electrode contact part and a direct contact part spaced apart from the gate electrode, a gate insulating layer disposed on the gate pattern, a semiconductor layer disposed on the gate insulating layer, an etch stopping layer disposed on the gate insulating layer, source and drain electrodes disposed on the etch stopping layer, pixel part extending from the source and drain electrodes, a first conductive layer connected to the common electrode contact part, a second conductive layer connected to the direct contact part, and a passivation layer disposed on the source and drain electrodes, the first conductive layer, and the second conductive layer. 1. A display substrate , comprising:a lower common electrode disposed on a substrate;an insulating layer disposed on the lower common electrode; a gate electrode disposed on the insulating layer; and', 'a common electrode contact part and a direct contact part spaced apart from the gate electrode;, 'a gate pattern comprisinga gate insulating layer disposed on the gate pattern;a semiconductor layer disposed on the gate insulating layer;an etch stopping layer disposed on the gate insulating layer;source and drain electrodes disposed on the etch stopping layer;a pixel part extending from the source and drain electrodes;a first conductive layer connected to the common electrode contact part;a second conductive layer connected to the direct contact part; anda passivation layer disposed on the source and drain electrodes, the first conductive layer, and the second conductive layer.2. The display substrate of claim 1 , wherein the lower common electrode is deposited on the substrate covering the entire substrate without being patterned.3. The display substrate of claim 1 , wherein the lower common electrode ...

Display substrate and method of fabricating the same

Disclosed are a display substrate, of which productivity is improved by decreasing five mask (M) processes utilized for fabricating the display substrate used in a liquid crystal display device in a horizontal field (Plane to Line Switching (PLS)) mode to four mask processes, and a method of fabricating the same.

Thin film transistor panel having an etch stopper on semiconductor

A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

METHOD OF REFORMING A METAL PATTERN, ARRAY SUBSTRATE, AND METHOD OF MANUFACTURING THE ARRAY SUBSTRATE

A method of reforming a metal pattern for improving the productivity and reliability of a manufacturing process, an array substrate and a method of manufacturing the array substrate are disclosed. In the method, a first wiring pattern is formed on an insulation substrate. The first wiring pattern is removed. A second wiring pattern is formed on an embossed pattern by using the embossed pattern as an alignment mask. The embossed pattern is defined by a recess formed on a surface of the insulation substrate. Accordingly, the insulation substrate having the recess formed thereon may not be discarded, and may be reused in forming the first wiring pattern. In addition, the embossed pattern defined by the recess is used as an alignment mask, so that the alignment reliability of a metal pattern may be improved.

Display substrate including direct contact part and method of fabricating the same

A display substrate including a lower common electrode disposed on a substrate, an insulating layer disposed on the lower common electrode, a gate pattern including a gate electrode disposed on the insulating layer and a common electrode contact part and a direct contact part spaced apart from the gate electrode, a gate insulating layer disposed on the gate pattern, a semiconductor layer disposed on the gate insulating layer, an etch stopping layer disposed on the gate insulating layer, source and drain electrodes disposed on the etch stopping layer, pixel part extending from the source and drain electrodes, a first conductive layer connected to the common electrode contact part, a second conductive layer connected to the direct contact part, and a passivation layer disposed on the source and drain electrodes, the first conductive layer, and the second conductive layer.

Display device and method of manufacturing the same

A display device includes a gate pattern, a semiconductor pattern, a source pattern and a pixel electrode are provided. The gate pattern is formed on a base substrate and includes a gate line and a gate electrode. The semiconductor pattern is formed on the base substrate having the gate pattern and includes an oxide semiconductor. The source pattern is formed from a data metal layer and formed on the base substrate having the semiconductor pattern, and includes a data line, a source electrode and a drain electrode. The data metal layer includes a first copper alloy layer, and a lower surface of the data metal layer substantially coincides with an upper surface of the semiconductor pattern. The pixel electrode is formed on the base substrate having the source pattern and electrically connected to the drain electrode. Thus, manufacturing processes may be simplified, and reliability may be improved.

Method of manufacturing thin film transistor substrate having etched trenches with color filter material disposed therein

A method of manufacturing a color filter substrate includes forming a plurality of trenches having a predetermined depth by etching a surface of a transparent substrate, disposing a color filter material in the plurality of trenches to form a color filter layer, and forming a transparent electrode on the transparent substrate including the color filter layer therein.

Thin film transistor panel having an etch stopper on semiconductor

A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Display substrate and method of manufacturing the same

A display substrate includes a gate wire formed on an insulating substrate, a semiconductor pattern formed on the gate wire and containing a metal oxynitride compound, and a data wire formed on the semiconductor pattern to cross the gate wire. The semiconductor pattern has a carrier number density ranging from 1016/cm3 to 1019/cm3.

THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME

A thin film transistor array panel and a method of manufacturing the same are provided according to one or more embodiments. In an embodiment, a method includes: forming a gate line on an insulation substrate; stacking a gate insulating layer, an oxide semiconductor layer, a first barrier layer, and a first copper layer on the gate line; performing a photolithography process on the oxide semiconductor layer, the first barrier layer, and the first copper layer and forming a data line including a source electrode, a drain electrode, and an oxide semiconductor pattern; forming a passivation layer having the contact hole that exposes the drain electrode on the data line and the drain electrode; and forming a pixel electrode that is connected to the drain electrode through the contact hole on the passivation layer, wherein the forming of a data line, a drain electrode, and an oxide semiconductor pattern includes wet etching the first copper layer and then wet etching the first barrier layer ...

Composition for photoresist stripper and method of fabricating thin film transistor array substrate

A composition for a photoresist stripper and a method of fabricating a thin film transistor array substrate are provided according to one or more embodiments. In one or more embodiments, the composition includes about 5-30 weight % of a chain amine compound, about 0.5-10 weight % of a cyclic amine compound, about 10-80 weight % of a glycol ether compound, about 5-30 weight % of distilled water, and about 0.1-5 weight % of a corrosion inhibitor.

DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

A display substrate includes a gate wire formed on an insulating substrate, a semiconductor pattern formed on the gate wire and containing a metal oxynitride compound, and a data wire formed on the semiconductor pattern to cross the gate wire. The semiconductor pattern has a carrier number density ranging from 10/cmto 10/cm. 1. A display substrate , comprising:a gate wire disposed on a substrate;a semiconductor pattern disposed on the gate wire and comprising a metal oxynitride and one of a heat treated semiconductor or a plasma treated semiconductor; anda data wire disposed on the semiconductor pattern and crossing the gate wire.2. The display substrate of claim 1 , wherein the semiconductor pattern has a carrier number density ranging from 10/cmto 10/cm.3. The display substrate of claim 2 , wherein the metal oxynitride comprises at least one metal of gallium (Ga) claim 2 , indium (In) claim 2 , zinc (Zn) claim 2 , tin (Sn) claim 2 , hafnium (Hf) claim 2 , and tantalum (Ta).4. The display substrate of claim 3 , wherein the metal oxynitride is GaInZnON or HfInZnON.5. The display substrate of claim 2 , wherein a band gap of the semiconductor pattern is greater than or equal to 3.0 eV.6. The display substrate of claim 2 , wherein the gate wire comprises a gate electrode;wherein a thin film transistor of the display substrate comprises a portion of each of the data wire, the semiconductor pattern, and the gate electrode; andthe thin film transistor turns on when a voltage applied to the gate electrode is greater than or equal to 0 V.7. The display substrate of claim 2 , wherein the gate wire comprises a gate electrode;wherein a thin film transistor of the display substrate comprises a portion of each of the data wire, the semiconductor pattern, and the gate electrode;the thin film transistor has a first turn on voltage corresponding to a first voltage applied to the gate electrode and has a subsequent turn on voltage corresponding to a second voltage applied to the ...

Display substrate and method of fabricating the same

A display substrate and its fabricating method have been disclosed. In a horizontal-field-mode liquid crystal display device, while maintaining five mask processes, additional direct contact has been formed to implement a narrow bezel.

Method of manufacturing color filter substrate wherein a transparent substrate is etched to form a plurality of trenches to receive color filter material

A method of manufacturing a color filter substrate includes forming a plurality of trenches having a predetermined depth by etching a surface of a transparent substrate, disposing a color filter material in the plurality of trenches to form a color filter layer, and forming a transparent electrode on the transparent substrate including the color filter layer therein.

THIN FILM TRANSISTOR PANEL HAVING AN ETCH STOPPER ON SEMICONDUCTOR

A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper. 1. A panel comprising a thin film transistor , the panel comprising:a substrate;a first electrode on the substrate;a first insulating layer on the first electrode;an oxide semiconductor pattern on the first insulating layer;an etch stopper on the oxide semiconductor pattern;a second electrode and a third electrode on the etch stopper and the oxide semiconductor pattern,wherein a pattern of the etch stopper is contained entirely within a perimeter of the oxide semiconductor pattern, and distances between corresponding sidewalls of the etch stopper and the oxide semiconductor pattern are substantially the same.2. The panel of claim 1 , wherein at least one of the second electrode and the third electrode is disposed directly on a sidewall and an upper surface of the oxide semiconductor pattern.3. The panel of claim 2 , wherein the at least one of the second electrode and the third electrode is further disposed directly on a sidewall and an upper surface of the etch stopper. This application is a divisional of U.S. patent application Ser. No. 14/230,787, filed on Mar. 31, 2014, which is a divisional of U.S. patent application Ser. No. 12/957,743, filed on Dec. 1, 2010, now issued as U.S. Pat. No. 8,723,179, and claims priority from and the benefit of Korean Patent Application No. 10-2010-0012957, filed on Feb. 11, 2010, each of which is hereby incorporated by reference for all purposes as if fully set forth herein.1. Field of the InventionExemplary embodiments of the present invention relate to a thin film transistor panel and a method for fabricating a thin film transistor panel.2. Discussion of the BackgroundA flat panel display, such as a liquid ...

Thin film transistor array substrate and method of fabricating the same

A thin film transistor array substrate capable of reducing degradation of a device due to degradation of an oxide semiconductor pattern and a method of fabricating the same are provided. The thin film transistor array substrate may include an insulating substrate on which a gate electrode is formed, a gate insulating film formed on the insulating substrate, an oxide semiconductor pattern disposed on the gate insulating film, an anti-etching pattern formed on the oxide semiconductor pattern, and a source electrode and a drain electrode formed on the anti-etching pattern. The oxide semiconductor pattern may include an edge portion positioned between the source electrode and the drain electrode, and the edge portion may include at least one conductive region and at least one non-conductive region.

Display substrate and method of manufacturing the same

A display substrate includes a gate line extending in a first direction on a base substrate, a data line on the base substrate and extending in a second direction crossing the first direction, a gate insulating layer on the gate line, a thin-film transistor and a pixel electrode. The thin-film transistor includes a gate electrode electrically connected the gate line, an oxide semiconductor pattern, and source and drain electrodes on the oxide semiconductor pattern and spaced apart from each other. The oxide semiconductor pattern includes a first semiconductor pattern including indium oxide and a second semiconductor pattern including indium-free oxide. The pixel electrode is electrically connected the drain electrode.

THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME

A thin film transistor array substrate capable of reducing degradation of a device due to degradation of an oxide semiconductor pattern and a method of fabricating the same are provided. The thin film transistor array substrate may include an insulating substrate on which a gate electrode is formed, a gate insulating film formed on the insulating substrate, an oxide semiconductor pattern disposed on the gate insulating film, an anti-etching pattern formed on the oxide semiconductor pattern, and a source electrode and a drain electrode formed on the anti-etching pattern. The oxide semiconductor pattern may include an edge portion positioned between the source electrode and the drain electrode, and the edge portion may include at least one conductive region and at least one non-conductive region. 1. A thin film transistor array substrate , comprising:a gate electrode disposed on a substrate;a gate insulating film disposed on the substrate;an oxide semiconductor pattern disposed on the gate insulating film;an anti-etching pattern disposed on the oxide semiconductor pattern; anda source electrode and a drain electrode disposed on the anti-etching pattern,wherein the oxide semiconductor pattern comprises an edge portion, andwherein the edge portion comprises a conductive region and a non-conductive region.2. The thin film transistor array substrate of claim 1 , further comprising:a passivation film disposed on the anti-etching pattern, the source electrode, and the drain electrode; anda column spacer formed through the gate insulating film,wherein the column spacer overlaps at least a portion of the non-conductive region.3. The thin film transistor array substrate of claim 2 , wherein the column spacer comprises:a first sidewall in contact with the passivation film, the anti-etching pattern, the oxide semiconductor pattern, and the gate insulating film; anda second sidewall in contact with the passivation film and the gate insulating film.4. The thin film transistor ...

DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

A display substrate includes; a gate pattern including a gate electrode disposed on a substrate, a gate insulation layer disposed on the substrate and the gate pattern, an insulation pattern including; a first thickness part disposed on a first area of the gate insulation layer overlapping the gate electrode and a second thickness part disposed on a second area of the gate insulation layer adjacent to the first area, an oxide semiconductor pattern disposed on the first thickness part of the first area, an etch stopper disposed on the oxide semiconductor pattern, a source pattern including a source electrode and a drain electrode which contact the oxide semiconductor pattern, and a pixel electrode which contacts the drain electrode. 1. A display substrate comprising:a gate pattern comprising a gate electrode disposed on a substrate;a gate insulation layer disposed on the substrate and the gate pattern; a first thickness part disposed on a first area of the gate insulation layer overlapping the gate electrode; and', 'a second thickness part disposed on a second area of the gate insulation layer adjacent to the first area,', 'wherein the first thickness part has a greater thickness than the second thickness part;, 'an insulation pattern comprisingan oxide semiconductor pattern disposed on the first thickness part of the first area;an etch stopper disposed on the oxide semiconductor pattern;a source pattern comprising a source electrode and a drain electrode which contact the oxide semiconductor pattern; anda pixel electrode which contacts the drain electrode.2. The display substrate of claim 1 , wherein the etch stopper comprises a first end portion and a second end portion disposed opposite to each other on the oxide semiconductor pattern so that two end portions of the oxide semiconductor pattern respectively adjacent to the first end portion of the etch stopper and the second end portion of the etch stopper are exposed by the etch stopper claim 1 , andeach of the ...

THIN FILM TRANSISTOR ARRAY PANEL

A thin film transistor array panel includes an insulating substrate, a gate line disposed on the insulating substrate having a gate electrode, a first gate insulating layer disposed on the gate line and made of silicon nitride, a second gate insulating layer disposed on the first gate insulating layer and made of silicon oxide, an oxide semiconductor disposed on the second gate insulating layer, a data line disposed on the oxide semiconductor and having a source electrode, a drain electrode disposed on the oxide semiconductor and facing the source electrode, and a pixel electrode that is connected to the drain electrode. A thickness of the second gate insulating layer may range from 200 Å to less than 500 Å. 1. A thin film transistor array panel , comprising:a substrate;a gate line disposed on the substrate and comprising a gate electrode;a first gate insulating layer disposed on the gate line and comprising silicon nitride;a second gate insulating layer disposed on the first gate insulating layer and comprising silicon oxide;an oxide semiconductor disposed on the second gate insulating layer;a data line disposed on the oxide semiconductor and comprising a source electrode;a drain electrode disposed on the oxide semiconductor and facing the source electrode; anda pixel electrode that is connected to the drain electrode,wherein a thickness of the second gate insulating layer is greater than or equal to 200 Å and less than 500 Å.2. The thin film transistor array panel of claim 1 , wherein a thickness of the second gate insulating layer is 300 Å.3. The thin film transistor array panel of claim 2 , wherein a thickness of the first gate insulating layer ranges from 2000 Å to 5000 Å.4. The thin film transistor array panel of claim 3 , wherein planar shapes and boundaries of the second gate insulating layer and the oxide semiconductor are the same as each other.5. The thin film transistor array panel of claim 4 , further comprising a channel passivation layer disposed on ...

METHOD OF MANUFACTURING A PACKAGE FOR EMBEDDING ONE OR MORE ELECTRONIC COMPONENTS

The present invention relates to the field of integrating electronic systems that operate at mm-wave and THz frequencies. A monolithic multichip package, a carrier structure for such a package as well as manufacturing methods for manufacturing such a package and such a carrier structure are proposed to obtain a package that fully shields different functions of the mm-wave/THz system. The package is poured into place by polymerizing photo sensitive monomers. It gradually grows around and above the MMICs (Monolithically Microwave Integrated Circuit) making connection to the MMICs but recessing the high frequency areas of the chip. The proposed approach leads to functional blocks that are electromagnetically completely shielded. These units can be combined and cascaded according to system needs. 1. A method of manufacturing a carrier structure of a package for embedding one or more electronic components , in particular microwave integrated circuits and discrete passive components , comprising the steps of:forming a back-side metallization layer,forming a polymer profile in layers on top of said backside metallization layer by subsequently forming two or more polymer layers by photo polymerisation, wherein one or more cavities are formed in said polymer profile for placing one or more electronic components therein, said electronic components having a back-side terminal and one or more front-side terminals,forming a front-side metallization layer on top of said polymer profile.2. The method of manufacturing as claimed in claim 1 ,wherein said polymer profile is formed such that a polymer-free groove is formed around single cavities or groups of cavities so that the front-side metallization layer contacts the back-side metallization layer when formed on top of said polymer profile.3. The method of manufacturing claimed in claim 2 ,wherein a polymer-free groove is formed at least around each single cavity or groups of cavities provided for embedding a microwave integrated ...

FEEDING STRUCTURE FOR CAVITY RESONATORS

The present invention relates to a feeding structure for coupling a feedline to a cavity. To increase the coupling, which can contribute to achieving a broad bandwidth, a feeding structure is proposed comprising a carrier substrate, a top conductor plane of a cavity formed in said carrier substrate, a feedline substrate covering said top conductor plane, a signal conductor of a feedline, said signal conductor being formed in or on said feedline substrate opposite said top conductor plane, a via probe connected to said signal conductor and leading through said feedline substrate and said top conductor plane into said cavity, a ring-shaped aperture formed in said top conductor plane around said via probe, and at least one slot-shaped aperture formed in said top conductor plane starting at said ring-shaped aperture and leading away from said via probe. 1. A feeding structure for coupling a feedline to a cavity , said feeding structure comprising:a carrier substrate,a top conductor plane of a cavity formed in said carrier substrate,a feedline substrate covering said top conductor plane,a signal conductor of a feedline, said signal conductor being formed in or on said feedline substrate opposite said top conductor plane,a via probe connected to said signal conductor and leading through said feedline substrate and said top conductor plane into said cavity,a ring-shaped aperture formed in said top conductor plane around said via probe, andat least one slot-shaped aperture formed in said top conductor plane starting at said ring-shaped aperture and leading away from said via probe.2. The feeding structure as claimed in claim 1 ,comprising two slot-shaped apertures formed in said top conductor plane starting at said ring-shaped aperture and leading away from said via probe in different directions, in particular in opposite directions.3. The feeding structure as claimed in claim 1 ,wherein said at least one slot-shaped aperture is arranged in a direction perpendicular to the ...

POWER SUPPLY APPARATUS FOR ON-LINE ELECTRIC VEHICLE, METHOD FOR FORMING SAME AND MAGNETIC FIELD CANCELATION APPARATUS

A power supply apparatus is for supplying power to an electric vehicle by a magnetic induction mechanism. The apparatus includes a power supply structure including a multiple number of power supply rail modules connected in a forward road direction, each power supply rail module including at least one power supply line passage elongated in the forward road direction, a power supply core of a lattice structure provided below the power supply line passage, and a concrete structure incorporating the power supply line passage and the power supply core; at least one power supply line accommodated in the power supply line passage in the forward road direction and surrounded by an insulating pipe; and at least one common line provided in the forward road direction and surrounded by an insulating pipe, for supplying power to the power supply apparatus. 1. A power supply apparatus for supplying power to an electric vehicle by a magnetic induction mechanism , the apparatus comprising:a power supply structure including a multiple number of power supply rail modules connected in a forward road direction, each power supply rail module including at least one power supply line passage elongated in the forward road direction, a power supply core of a lattice structure provided below the power supply line passage, and a concrete structure incorporating the power supply line passage and the power supply core;at least one power supply line accommodated in the power supply line passage in the forward road direction and surrounded by an insulating pipe; andat least one common line provided in the forward road direction and surrounded by an insulating pipe, for supplying power to the power supply apparatus.2. The power supply apparatus of claim 1 , wherein the power supply core of the lattice structure includes a plurality of core blades arranged in a lattice pattern claim 1 , anda thickness of each core blade in the forward road direction is equal to or less than about ⅓ of a distance ...

MODULAR ELECTRIC-VEHICLE ELECTRICITY SUPPLY DEVICE AND ELECTRICAL WIRE ARRANGEMENT METHOD

The present invention relates to a modular electric-vehicle electricity supply device and an electrical wire arrangement method, and more particularly, to an electric-vehicle electricity supply device and electrical wire arrangement method which use a modular approach such that respective modules can be controlled so as to be either ON or OFF; in which a plurality of a magnets disposed at right angles to the direction of travel on a road area provided spaced at predetermined intervals in the direction of travel on the road, and which comprises electricity supply cores formed such that the widths at right angles to the direction of travel on the road are very narrow, and comprises electricity supply wires arranged such that the magnets of electricity supply cores which neighbor each other in the direction of travel on the road have different polarities. 1. A modular electric-vehicle electricity supply device for supplying electricity to an electric vehicle in an inductive coupling manner , comprising:an electricity supply core comprising a plurality of electricity supply core modules connected to each other along a direction of travel on a road, the electricity supply core modules each comprising one or more magnetic poles and an electricity supply wire coupling portion on both front and rear ends;an electricity supply wire arranged so that magnetic poles of the electricity supply core neighboring each other have different polarities along the direction of travel; anda common line to individually control the electricity supply core modules to be either ON or OFF.2. The modular electric-vehicle electricity supply device of claim 1 , wherein the electricity supply wire is arranged such that the electricity supply wire is wound around each magnetic pole by at least two times.3. The modular electric-vehicle electricity supply device of claim 1 , wherein a width of the electricity supply core at right angles to the direction of travel on the road is at most a half of a ...

THIN FILM TRANSISTOR ARRAY PANEL

A thin film transistor array panel includes: a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, and a data wire layer disposed on the substrate and including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode. In addition, at least one of the data line, the source electrode or the drain electrode of the data wire layer includes a barrier layer and a main wiring layer disposed on the barrier layer. The main wiring layer includes copper or a copper alloy. Also, the barrier layer includes a metal oxide, and the metal oxide includes zinc. 1. A thin film transistor array panel comprising:a gate line disposed on a substrate and including a gate electrode;a semiconductor layer including an oxide semiconductor disposed on the substrate; anda data wire layer disposed on the substrate and including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode,wherein at least one of the data line, the source electrode or the drain electrode of the data wire layer includes a barrier layer, a main wiring layer disposed on the barrier layer, and a capping layer disposed on the main wiring layer,wherein the main wiring layer includes one of copper or a copper alloy, wherein the barrier layer and the capping layer includes a metal oxide, andwherein the metal oxide includes zinc.2. The thin film transistor array panel of claim 1 , wherein:the barrier layer includes one of indium-zinc oxide (IZO), gallium-zinc oxide (GZO), or aluminum-zinc oxide (AZO).3. The thin film transistor array panel of claim 2 , wherein{'sub': 2', '3, 'the barrier layer includes gallium-zinc oxide (GZO), and wherein an amount of gallium oxide (GaO) included in gallium-zinc oxide (GZO) is in a range from about 2.5 mol % to about 10 mol %.'}4. The thin ...

THIN FILM TRANSISTOR ARRAY PANEL HAVING IMPROVED APERTURE RATIO AND METHOD OF MANUFACTURING SAME

A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate line positioned on the substrate; a gate insulating layer positioned on the gate line; a semiconductor layer positioned on the gate insulating layer and having a channel portion; a data line including a source electrode and a drain electrode, the source and drain electrodes both positioned on the semiconductor layer; a passivation layer positioned on the data line and the drain electrode and having a contact hole formed therein; and a pixel electrode positioned on the passivation layer, wherein the pixel electrode contacts the drain electrode within the contact hole, and the channel portion of the semiconductor layer and the contact hole both overlap the gate line in a plan view of the substrate. 1. A thin film transistor array panel comprising:a substrate;a gate line positioned on the substrate;a gate insulating layer positioned on the gate line;a semiconductor layer positioned on the gate insulating layer and having a channel portion;a data line including a source electrode and a drain electrode, the source and drain electrodes both positioned on the semiconductor layer;a passivation layer positioned on the data line and the drain electrode, and having a contact hole formed therein; anda pixel electrode positioned on the passivation layer;wherein the pixel electrode is connected to the drain electrode through the contact hole; andthe channel portion of the semiconductor layer and the contact hole both overlap the gate line in a plan view of the substrate.2. The thin film transistor array panel of claim 1 , whereinthe gate line includes a gate electrode protruding from the gate line.3. The thin film transistor array panel of claim 2 , wherein:the source electrode overlaps the gate line in a plan view of the substrate.4. The thin film transistor array panel of claim 3 , wherein:the drain electrode overlaps the gate line in a plan view of the ...

Display device and method of manufacturing the same

A display device according to an exemplary embodiment of the present invention includes a semiconductor layer; a data line disposed on the semiconductor layer, and a source electrode as well as a drain electrode disposed on the semiconductor layer and facing the source electrode. The semiconductor layer is made of an oxide semiconductor including indium, tin, and zinc. An atomic percent of indium in the oxide semiconductor is equal to or larger than about 10 at % and equal to or smaller than about 90 at %, an atomic percent of zinc in the oxide semiconductor is equal to or larger than about 5 at % and equal to or smaller than about 60 at %, and an atomic percent of tin in the oxide semiconductor is equal to or larger than about 5 at % and equal to or smaller than about 45 at %, and the data line and the drain electrode comprise copper.

ETCHANT COMPOSITION AND MANUFACTURING METHOD FOR THIN FILM TRANSISTOR USING THE SAME

An etchant composition includes ammonium persulfate (((NH))SO), an azole-based compound, a water-soluble amine compound, a sulfonic acid-containing compound, a nitrate-containing compound, a phosphate-containing compound, a chloride-containing compound, and residual water. 1. An etchant composition comprising:{'sub': 4', '2', '2', '8, 'ammonium persulfate (((NH))SO), an azole-based compound, a water-soluble amine compound, a sulfonic acid-containing compound, a nitrate-containing compound, a phosphate-containing compound, a chloride-containing compound, and residual water.'}2. The etchant composition of claim 1 , further comprising:an assistance oxidizer.3. The etchant composition of claim 2 , whereina content of the assistance oxidizer is about 0.1 wt % to about 2 wt %.4. The etchant composition of claim 3 , wherein{'sub': 3', '4', '3', '3', '4', '2', '2, 'the assistance oxidizer includes one selected from a group consisting of phosphoric acid (HPO), nitric acid (HNO), acetic acid (CHCOOH), perchloric acid (HClO), and hydrogen peroxide (HO).'}5. The etchant composition of claim 1 , whereinthe ammonium persulfate content is about 0.1 wt % to about 20 wt %, the azole-based compound content is about 0.01 wt % to about 2 wt %, the water-soluble amine compound content is about 0.1 wt % to about 5 wt %, the sulfonic acid-containing compound content is about 0.1 wt % to about 10 wt %, and the nitrate-containing compound content is about 0.1 wt % to about 10 wt %.6. The etchant composition of claim 5 , whereinthe phosphate-containing compound content is about 0.1 wt % to about 5 wt %.7. The etchant composition of claim 6 , whereinthe chloride-containing compound content is about 0.001 wt % to about 1 wt %.8. The etchant composition of claim 1 , whereinthe azole-based compound includes one selected from the group consisting of benzotriazole, aminotetrazole, imidazole, and pyrazole.9. The etchant composition of claim 1 , whereinthe water-soluble amine compound includes one ...

Electrode, battery cell and use thereof

The invention relates to an electrode of a battery cell, in particular a positive electrode of a lithium-ion battery cell, in the present case in the form of an electrode layer (102, 202, 302) and comprising an active material having a plurality of active material particles (106, 206, 306), characterised in that a thickness of the electrode layer (102, 202, 302) is at least twice as large as a maximum diameter of the active material particles (106, 206, 306).

NON-CONTACT POWER TRANSMISSION DEVICE, MAGNETIC INDUCTION-TYPE POWER SUPPLY DEVICE, MAGNETIC INDUCTION-TYPE POWER COLLECTOR, AND MOVING OBJECT USING SAME

Embodiments of the present invention relate to a non-contact power transmission device, a magnetic induction-type power supply device, a magnetic induction-type power collector, and a moving object using same. Embodiments of the present invention provide a non-contact power transmission device, a magnetic induction-type power supply device, a magnetic induction-type power collector, and a moving object using same, the non-contact power transmission device comprising: a power collector having a power collector core, and a boob power collector cable that winds around the power collector core; and a power supply unit comprising a power supply core having a holder section and protrusions on the center portion of the holder section and around the perimeter of the holder section, and a power supply cable wound in such a manner that electric currents flow in two different directions with respect to the protruding center portion, wherein the power collector is located in the opposite direction from the protruding portion.

DISPLAY SUBSTRATE AND METHOD OF FABRICATING THE SAME

Disclosed are a display substrate, of which productivity is improved by decreasing five mask (M) processes utilized for fabricating the display substrate used in a liquid crystal display device in a horizontal field (Plane to Line Switching (PLS)) mode to four mask processes, and a method of fabricating the same. 1. A display substrate , comprising:a common electrode formed on a substrate;an insulating layer formed on the lower common electrode;a gate pattern formed on the insulating layer including a gate electrode and a common electrode contact part spaced apart from the gate electrode;a gate insulating layer formed on the gate pattern;a semiconductor layer disposed on the gate insulating layer;a source electrode and a drain electrode formed on the semiconductor layer;a passivation layer formed on the source electrode and the drain electrode;a pixel electrode formed on the passivation layer; anda common electrode contact connection part spaced apart from the pixel electrodewherein the common electrode contact part is in side-contact with the common electrode.2. The display substrate of claim 1 , wherein the common electrode is deposited on entire surface of the substrate claim 1 , and is not patterned.3. The display substrate of claim 1 , wherein the common electrode and the pixel electrode are made of Transparent Conductive Oxide (TCO) based material.4. The display substrate of claim 1 , wherein the insulating layer and the gate insulating layer are made of Si-based material.5. The display substrate of claim 1 , wherein the gate electrode and the source/drain electrodes are made of a material selected from a group consisting of copper claim 1 , aluminum claim 1 , molybdenum claim 1 , tungsten claim 1 , titanium claim 1 , and chrome claim 1 , in a single form or alloy form.6. A method of fabricating a display substrate claim 1 , comprising:depositing a common electrode on entire surface of a substrate;depositing an insulating layer on the common electrode; ...

Display substrate and method of fabricating the same

A display substrate and its fabricating method have been disclosed. In a horizontal-field-mode liquid crystal display device, while maintaining five mask processes, additional direct contact has been formed to implement a narrow bezel.

Fan-out semiconductor package

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; and an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip. The first interconnection member includes a first insulating layer in contact with the second interconnection member, a first redistribution layer disposed on a surface of the first insulating layer in contact with the second interconnection member and electrically connected to the connection pads, and a blocking layer disposed on the surface of the first insulating layer on which the first redistribution layer is disposed and surrounding the through-hole.

THIN FILM TRANSISTOR PANEL HAVING AN ETCH STOPPER ON SEMICONDUCTOR

A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper. 1. A method for forming a panel comprising a thin film transistor , the method comprising:forming an oxide semiconductor pattern comprising a channel region;forming an etch stopper at a position corresponding to the channel region; andforming a first electrode and a second electrode spaced apart from the first electrode, the channel region configured to connect the first electrode to the second electrode,wherein the etch stopper and the oxide semiconductor pattern are formed using a first mask.2. The method of claim 1 , further comprising:disposing a first conductive layer on a substrate;disposing a first insulating layer on the first conductive layer;disposing an oxide semiconductor layer on the first insulating layer; anddisposing an etch stop layer on the oxide semiconductor layer;wherein the etch stopper and the oxide semiconductor pattern are formed by patterning the etch stop layer and the oxide semiconductor layer using the first mask.3. The method of claim 2 , wherein patterning the etch stop layer and the oxide semiconductor layer comprises forming a photoresist pattern using the first mask.4. The method of claim 3 , wherein patterning the etch stop layer and the oxide semiconductor layer further comprises etching the etch stop layer having the photoresist pattern thereon to form an interim etch stopper.5. The method of claim 4 , wherein patterning the etch stop layer and the oxide semiconductor layer further comprises etching the oxide semiconductor layer having the interim etch stopper thereon to form the oxide semiconductor pattern.6. The method of claim 5 , wherein patterning the etch stop layer and the oxide semiconductor layer ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a connection member having a first surface and a second surface opposing each other and including a first redistribution layer on the second surface and at least one second redistribution layer on a level different from a level of the first redistribution layer; a semiconductor chip on the first surface of the connection member; a passivation layer on the second surface of the connection member, and including openings; UBM layers connected to the first redistribution layer through the openings; and electrical connection structures on UBM layers. An interface between the passivation layer and the UBM layers has a first unevenness surface, an interface between the passivation layer and the first redistribution layer has a second unevenness surface, connected to the first unevenness surface, and the second unevenness surface has a surface roughness greater than a surface roughness of the second redistribution layer. 1. A semiconductor package comprising:a connection member having a first surface and a second surface opposing each other and including a plurality of redistribution layers on different levels, the plurality of redistribution layers including a first redistribution layer on the second surface and at least one second redistribution layer on a level different from a level of the first redistribution layer;a semiconductor chip disposed on the first surface of the connection member and including a connection pad connected to the second redistribution layer;an encapsulant disposed on the first surface of the connection member and sealing the semiconductor chip;a passivation layer disposed on the second surface of the connection member, and including a plurality of openings respectively exposing portions of the first redistribution layer;a plurality of underbump metallurgy (UBM) layers connected to the portions of the first redistribution layer through the plurality of openings, respectively; anda plurality of electrical ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a connection member having first and second surfaces opposing each other and including at least one insulating layer and redistribution layer, the redistribution layer including a via penetrating through the insulating layer and a RDL pattern connected to the via while being located on an upper surface of the insulating layer; a semiconductor chip disposed on the first surface and including a connection pad connected to the redistribution layer; and an encapsulant disposed on the first surface and encapsulating the semiconductor chip. The redistribution layer includes a seed layer disposed on a surface of the insulating layer and a plating layer disposed on the seed layer. An interface between the insulating layer and a portion of the seed layer constituting the via includes a first uneven surface with a surface roughness of 30 nm or more. 1. A semiconductor package comprising:a connection member having a first surface and a second surface opposing each other, and including at least one insulating layer and at least one redistribution layer, a first surface of the insulating layer corresponding to the first surface of the connection member, the at least one redistribution layer including a via penetrating through the at least one insulating layer and a RDL pattern connected to the via while being disposed on a second surface of the at least one insulating layer opposing the first surface of the insulating layer;a semiconductor chip disposed on the first surface of the connection member, and including a connection pad connected to the at least one redistribution layer; andan encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip,wherein the at least one redistribution layer includes a seed layer disposed on the first surface of the at least one insulating layer, and a plating layer disposed on the seed layer, andan interface between the at least one insulating layer and a portion of ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes: a semiconductor chip including a passivation film disposed on an active surface and having a first opening exposing at least a portion of a connection pad and a protective film disposed on the passivation film, filling at least a portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening; an encapsulant covering at least a portion of the semiconductor chip; and the connection structure including an insulating layer having a via hole connected to the second opening to expose at least a portion of the connection pad, a redistribution layer, and a connection via connecting the connection pad to the redistribution layer while filling at least a portion of each of the via hole and the second opening. The second opening and the via hole are connected to have a stepped portion. 1. A semiconductor package , comprising:a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposite to the active surface, and including a passivation film disposed on the active surface and having a first opening exposing at least a portion of the connection pad and a protective film disposed on the passivation film, filling at least a portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening;an encapsulant covering at least a portion of the semiconductor chip; anda connection structure including an insulating layer disposed on the protective film, and having a via hole connected to the second opening to expose at least a portion of the connection pad, a redistribution layer disposed on the insulating layer, and a connection via connecting the connection pad to the redistribution layer while filling at least a portion of each of the via hole and the second opening,wherein the second opening and the via hole are connected to have a stepped portion.2. The semiconductor ...

THIN FILM TRANSISTOR PANEL HAVING AN ETCH STOPPER ON SEMICONDUCTOR

A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper. 1. A method for forming a panel comprising a thin film transistor , the method comprising:forming an oxide semiconductor pattern comprising a channel region;forming an etch stopper at a position corresponding to the channel region; andforming a first electrode and a second electrode spaced apart from the first electrode, the channel region configured to connect the first electrode to the second electrode,wherein the oxide semiconductor pattern, the first electrode, and the second electrode are formed using a first mask.2. The method of claim 1 , further comprising:disposing a first conductive layer on a substrate;disposing a first insulating layer on the first conductive layer;disposing an oxide semiconductor layer on the first insulating layer;disposing a second conductive layer on the etch stopper and the oxide semiconductor layer;wherein the oxide semiconductor layer and the second conductive layer are patterned using the first mask to form the oxide semiconductor pattern, the first electrode, and the second electrode.3. The method of claim 2 , further comprising:forming a second insulating layer on the first electrode and the second electrode;patterning the second insulating layer to form a contact hole exposing the first electrode; andforming a third conductive layer on the second insulating layer;patterning the third conductive layer to form a third electrode,wherein the third electrode is connected to the first electrode via the contact hole.4. The method of claim 3 , wherein the second insulating layer comprises a passivation layer.5. The method of claim 3 , wherein the second insulating layer comprises a color filter.6. The method of ...

FAN-OUT SEMICONDUCTOR PACKAGE

A fan-out semiconductor package includes: a core member including a support layer, a first wiring layer, a second wiring layer, and through-vias and having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant covering the core member and the semiconductor chip and filling at least portions of the through-hole; a connection member including an insulating layer disposed on the first wiring layer and the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and a passivation layer disposed on the insulating layer and covering the redistribution layer, wherein a thickness of the passivation layer is within half a distance from an inactive surface of the semiconductor chip to a lower surface of the encapsulant. 1. A fan-out semiconductor package comprising:a core member including a support layer and a first wiring layer disposed on an upper surface of the support layer, and having a through-hole penetrating through the support layer;a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;an encapsulant covering the core member and the inactive surface of the semiconductor chip and filling at least portions of the through-hole;a connection member including an insulating layer disposed on the first wiring layer of the core member and the active surface of the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; anda passivation layer disposed on the insulating layer and covering ...

THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME

A thin film transistor array panel includes: a gate line including a gate electrode; a first gate insulating layer on the gate line; a semiconductor layer on the first gate insulating layer and overlapping the gate electrode; a second gate insulating layer on the semiconductor layer and the first gate insulating layer, and an opening in the second gate insulating layer and through which the semiconductor layer is exposed; drain and source electrodes on the second gate insulating and semiconductor layers and facing each other; a first field generating electrode; and a second field generating electrode connected to the drain electrode. The semiconductor layer includes an oxide semiconductor layer, and first and second auxiliary layers on the oxide semiconductor layer and separated from each other. An edge of the drain and source electrodes is disposed inside an edge of the first and second auxiliary layers, respectively. 1. A thin film transistor array panel , comprising:an insulating substrate;a gate line on the insulating substrate and comprising a gate electrode;a reference electrode line on the insulating substrate, separated from the gate line and comprising an extension;a first gate insulating layer on the insulating substrate, the gate line and the reference electrode line;a semiconductor layer on the first gate insulating layer and overlapping the gate electrode;a second gate insulating layer on the semiconductor layer and the first gate insulating layer, and a semiconductor opening defined in the second gate insulating layer and through which the semiconductor layer is exposed;a data line comprising a source electrode;a drain electrode on the second gate insulating layer and the semiconductor layer, and facing the source electrode;a first passivation layer on the data line, the drain electrode and the second gate insulating layer;a second passivation layer on the first passivation layer;a first field generating electrode on the second passivation layer;a ...

THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

A thin film transistor substrate includes a gate metal pattern comprising a gate line extending in a first direction and a gate electrode electrically connected to the gate line, an active pattern overlapping the gate electrode, an etch-stop layer disposed on the active pattern and having a first through hole and a second through hole adjacent to the first through hole, a data metal pattern comprising a data line extending in a second direction crossing the first direction, a source electrode electrically connected to the active pattern through the first through hole and a drain electrode electrically connected to the active pattern through the second through hole and a first passivation layer disposed on the data metal pattern. 1. A thin film transistor substrate comprising:a gate metal pattern comprising a gate line extending in a first direction and a gate electrode electrically connected to the gate line;an active pattern overlapping the gate electrode;an etch-stop layer disposed on the active pattern and having a first through hole and a second through hole adjacent to the first through hole;a data metal pattern comprising a data line extending in a second direction crossing the first direction, a source electrode electrically connected to the active pattern through the first through hole and a drain electrode electrically connected to the active pattern through the second through hole; anda first passivation layer disposed on the data metal pattern.2. The thin film transistor substrate of claim 1 , further comprising:a gate pad disposed on the same layer as the gate metal pattern and electrically connected to the gate line; anda signal line disposed on the same layer as the data metal pattern and contacted with the gate pad to apply a gate signal to the gate pad.3. The thin film transistor substrate of claim 2 , further comprising:a gate insulation layer covering the gate line and the gate electrode; andthe etch-stop layer covers the gate insulation layer and ...

METHOD OF PREPARING ELECTRODE ASSEMBLY AND ELECTRODE ASSEMBLY PREPARED USING THE METHOD

Provided are a method of preparing an electrode assembly, in which both sides of a single current collector are coated to form an anode and a cathode, and the current collector is then bent into a vertical sectional zigzag shape and integrated in a state of disposing a separator at interfaces between facing electrode patterns, an electrode assembly prepared by the above method, and a secondary battery comprising the electrode assembly. 1. A method of preparing an electrode assembly , the method comprising:preparing a single current collector;respectively and repeatedly coating both sides of the single current collector with a cathode active material and an anode active material to form one or more anode patterns and cathode patterns and one or more non-coating portions on which the active materials are not coated;bending the one or more non-coating portions, on which the active materials are not coated, into a vertical sectional zigzag shape;disposing a separator at respective interfaces between the cathode patterns and the anode patterns that face each other by the bending, and folding the single current collector; andcutting the bent non-coating portions.2. The method of claim 1 , wherein the electrode assembly is a layered electrode assembly.3. The method of claim 1 , further comprising drying and pressing after the coating of the both sides of the current collector with the cathode active material and the anode active material and before the bending.4. The method of claim 1 , wherein widths of the cathode pattern and the anode pattern are same.5. The method of claim 1 , wherein a width of the non-coating portion is in a range of 5% to 10% based on a total width of the cathode pattern or the anode pattern.6. The method of claim 1 , wherein a marking for facilitating the bending is formed in the non-coating portion.7. The method of claim 1 , wherein the marking comprises one or more holes that are perforated at predetermined spaced intervals along a portion to be ...

Composite film, production thereof, and use thereof in a solid-state electrochemical cell

A composite film ( 1 ) comprising a composition comprising at least one solid electrolyte and at least one binder, wherein the fraction of binder in the composition increases with decreasing distance from the margins ( 30, 31 ) of the composite film ( 1 ). Also a method for producing a composite film ( 1 ) of this kind, to the use thereof, and also a solid-state electrochemical cell comprising a composite film ( 1 ) of this kind.

Thin film transistor substrate and method of manufacturing a thin film transistor substrate

Rather than forming a data line continuously extending in one layer of a thin film transistor substrate, spaced apart segments of a first data connection pattern are formed in a same first layer as that of the gate lines but extending in a crossing direction. Spaced apart parts of a second data connection pattern are formed in a same second layer as that of the source electrodes of the substrate and also extending in the crossing direction. The segments of the first data connection pattern are connected to successive parts of the second data connection pattern to form completed data lines. In one embodiment, the gate lines of the first layer and the spaced apart segments of a first data connection pattern include a low resistivity metal such as copper.

POSITIVE ELECTRODE FOR SECONDARY BATTERY, METHOD OF PREPARING THE SAME, AND LITHIUM SECONDARY BATTERY INCLUDING THE POSITIVE ELECTRODE

The present invention relates to a positive electrode for a secondary battery in which a maximum diameter of internal pores is controlled to be less than 1 μm, a method of preparing the same, and a secondary battery including the positive electrode. 1. A positive electrode for a secondary battery , the positive electrode comprising:a positive electrode collector; anda positive electrode material mixture layer coated on at least one side of the positive electrode collector,wherein the positive electrode material mixture layer comprises a positive electrode active material, a conductive agent, a binder, and bimodal pores composed of first pores and second pores which have different average diameters, and{'sub': '1', 'the conductive agent and the positive electrode active material are included at a volume ratio (K) of 0.08:1 to 0.32:1,'}wherein a volume ratio of the conductive agent to the total pores is in a range of 0.1:1 to 0.33:1,a porosity is in a range of 30 vol % to 45 vol %,maximum diameters of the first pores and the second pores are less than 1 μm, andan average diameter ratio (k) of the first pores to the second pores is in a range of 0.13:1 to 0.27:1.2. The positive electrode for a secondary battery of claim 1 , wherein the positive electrode active material has an average particle diameter (D) of 3 μm to 20 μm.3. The positive electrode for a secondary battery of claim 1 , wherein the positive electrode active material comprises a single material selected from the group consisting of lithium-manganese-based oxide claim 1 , lithium-cobalt-based oxide claim 1 , lithium-nickel-based oxide claim 1 , lithium-nickel-manganese-based oxide claim 1 , lithium-nickel-cobalt-based oxide claim 1 , lithium-manganese-cobalt-based oxide claim 1 , lithium-nickel-manganese-cobalt-based oxide claim 1 , and lithium-nickel-cobalt-transition metal oxide claim 1 , or a mixture of two or more thereof.4. The positive electrode for a secondary battery of claim 1 , wherein the ...

THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME

A thin film transistor array panel is disclosed. The thin film transistor array panel may include a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, a data wiring layer disposed on the substrate and including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode, a polymer layer covering the source electrode and the drain electrode, and a passivation layer disposed on the polymer layer. The data wiring layer may include copper or a copper alloy and the polymer layer may include fluorocarbon. 1. A method for manufacturing a thin film transistor array panel , comprising:forming a gate line comprising a gate electrode on a substrate;forming a gate insulating layer on the gate line;forming a semiconductor layer comprising an oxide semiconductor on the gate insulating layer;forming a data wiring layer comprising a source electrode and a drain electrode on the semiconductor layer;forming a polymer layer by fluorocarbon plasma-processing the surfaces of the source electrode and the drain electrode; andforming a passivation layer on the polymer layer,wherein the data wiring layer is formed from copper or copper alloy.2. The method of claim 1 , wherein the forming of the data wiring layer comprises forming a barrier layer and forming a wiring layer on the barrier layer claim 1 , wherein the main wiring layer is formed from copper or copper alloy claim 1 , and wherein the barrier layer is formed from a metal oxide.3. The method of claim 2 , wherein the forming of the semiconductor layer and the forming of the data wiring layer are simultaneously performed by using a mask.4. The method of claim 3 , wherein in the semiconductor layer claim 3 , an exposed portion not covered by the source electrode and the drain electrode is formed between the source electrode and the drain electrode claim 3 , wherein the ...

THIN-FILM TRANSISTOR SUBSTRATE

A thin-film transistor (TFT) substrate including a first region including a semiconductor layer, a first etch barrier layer covering the semiconductor layer, a first contact hole and a second contact hole, which are formed through the first etch barrier layer, a source electrode, which is disposed on the first etch barrier layer and is electrically connected to the semiconductor layer via the first contact hole, a drain electrode, which is disposed on the first etch barrier layer to be isolated from the source electrode, is electrically connected to the semiconductor layer via the second contact hole and has a transparent conductive oxide layer and a metal layer, and a pixel electrode, which is disposed on the first etch barrier layer and includes the transparent conductive oxide layer. 1. A thin-film transistor (TFT) substrate comprising a first region , the first region comprising:a gate wire;a first gate insulating layer covering the gate wire;a through-hole formed through the first gate insulating layer and positioned over a part of the gate wire;a common electrode disposed on the first gate insulating layer and comprising first and second portions thereof which are isolated from each other, with the through-hole interposed therebetween;a second gate insulating layer covering the common electrode, the first gate insulating layer, and the part of the gate wire over which the through-hole is positioned;a semiconductor layer disposed on the second gate insulating layer;a first etch barrier layer covering the semiconductor layer;a first contact hole and a second contact hole, both of which are formed through the first etch barrier layer;a source electrode disposed on the first etch barrier layer and electrically connected to the semiconductor layer via the first contact hole and comprising a transparent conductive oxide layer and a metal layer;a drain electrode disposed on the first etch barrier layer and isolated from the source electrode, the drain electrode being ...

THREE-DIMENSIONAL IMAGE DISPLAY DEVICE AND DRIVING METHOD THEREOF

A 3D-capable image display device includes: a display panel having a plurality of pixels and a plurality of data lines; a gamma reference voltages generator for generating a plurality of gamma reference voltages including positive gamma reference voltages and negative gamma reference voltages; a data lines driver for converting an image signal into corresponding data line drive voltages based on the plurality of gamma reference voltages; and a signal controller operating according to a mode selection signal including information for selecting one of different 3D driving methods, wherein when a gap between the positive gamma reference voltages and the negative gamma reference voltages is referred to as a black gap, and size of the black gap is variable based on the selected 3D driving method. 1. A 3D-capable image display device comprising:a display panel including a plurality of pixels and a plurality of data lines;a gamma reference voltages generator configured for generating a plurality of gamma reference voltages including a plurality of positive gamma reference voltages and a plurality of negative gamma reference voltages, where polarity is relative to a provided common voltage;a data lines driver configured for converting an image signal into corresponding data line drive voltages using a plurality of gray voltages generated based on the plurality of gamma reference voltages and for applying the data line drive voltages to corresponding ones of the data lines; anda signal controller configured for operating according to a mode selection signal including information indicative of one of a plurality of different 3D driving methods and for controlling the gamma reference voltages generator and the data lines driver,wherein when a gap between the plurality of positive gamma reference voltages and the plurality of negative gamma reference voltages is referred to as a black gap, and the black gap is caused to be a first black gap when the 3D driving method is a first ...

LIQUID CRYSTAL DISPLAY AND METHOD OF FABRICATING THE SAME

A liquid crystal display and a method of fabricating a liquid crystal display (LCD), the LCD including a substrate; gate wiring including a gate pad, a gate electrode, and a gate line, which are formed on the substrate; a gate insulating layer disposed on the gate wiring; an electrode pattern including a connecting electrode, which is disposed on the gate insulating layer and is electrically connected to the gate pad, a source electrode and a drain electrode, which partially overlap the gate electrode; a pixel electrode, which is electrically connected to the drain electrode; a data line, which intersects the gate line; a semiconductor layer disposed on the gate electrode; first auxiliary wiring overlapping the data line and spaced from the semiconductor layer; and second auxiliary wiring overlapping the gate line. 1. A liquid crystal display (LCD) , comprising:a substrate; a gate pad;', 'a gate electrode; and', 'a gate line;, 'gate wiring disposed on the substrate, the gate wiring comprising'}a gate insulating layer disposed on the gate wiring; a connecting electrode electrically connected to the gate pad;', 'a source electrode partially overlapping the gate electrode;', 'a drain electrode partially overlapping the gate electrode;', 'a pixel electrode electrically connected to the drain electrode; and', 'a data line intersecting the gate line;, 'an electrode pattern disposed on the gate insulating layer, the electrode pattern comprisinga semiconductor layer disposed on the gate electrode;first auxiliary wiring overlapping the data line and spaced apart from the semiconductor layer; andsecond auxiliary wiring overlapping the gate line.2. The LCD of claim 1 , wherein the semiconductor layer comprises an indium gallium zinc oxide (IGZO)-based oxide semiconductor.3. The LCD of claim 1 , wherein each of the gate electrode claim 1 , the gate pad claim 1 , and the gate line comprises a layer of titanium (Ti) and a layer of copper (Cu).4. The LCD of claim 1 , wherein the ...

THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

A thin film transistor includes a gate electrode disposed on a substrate, a gate insulating layer disposed on the gate electrode and the substrate, an oxide semiconductor pattern disposed on the gate insulating layer, wherein a part of the oxide semiconductor overlaps the gate electrode, a source electrode disposed on a part of the oxide semiconductor pattern, and a drain electrode disposed on a part of the oxide semiconductor pattern spaced apart from the source electrode, wherein a thickness of the gate insulating layer in a channel region, the channel region overlapping the gate electrode, is thinner than a thickness of the gate insulating layer in a remaining region, the remaining region other than the channel region. 1. A thin film transistor , comprising:a gate electrode disposed on a substrate;a gate insulating layer disposed on the gate electrode and the substrate;an oxide semiconductor pattern disposed on the gate insulating layer, wherein a part of the oxide semiconductor overlaps the gate electrode;a source electrode disposed on a part of the oxide semiconductor pattern; anda drain electrode disposed on a part of the oxide semiconductor pattern spaced apart from the source electrode,wherein a thickness of the gate insulating layer in a channel region, the channel region overlapping the gate electrode, is thinner than a thickness of the gate insulating layer in a remaining region, the remaining region being other than the channel region.2. The thin film transistor of claim 1 , wherein the gate insulating layer is a single layer of silicon oxide.3. The thin film transistor of claim 1 , wherein the gate insulating layer comprises a silicon oxide layer and a silicon nitride layer.4. The thin film transistor of claim 1 , whereinthe gate insulating layer comprises a silicon nitride layer and a silicon oxide layer,and a thickness of the silicon oxide layer in the channel region is thinner than a thickness of the silicon oxide layer in the remaining region.5. The ...

ETCHANT COMPOSITION AND MANUFACTURING METHOD FOR THIN FILM TRANSISTOR USING THE SAME

An etchant composition includes ammonium persulfate (((NH))SO), an azole-based compound, a water-soluble amine compound, a sulfonic acid-containing compound, a nitrate-containing compound, a phosphate-containing compound, a chloride-containing compound, and residual water. 1. An etchant composition comprising: ammonium persulfate (((NH))SO) , an azole-based compound , a water-soluble amine compound , a sulfonic acid-containing compound , a nitrate-containing compound , a phosphate-containing compound , a chloride-containing compound , and residual water.2. The etchant composition of claim 1 , further comprising: an assistance oxidizer.3. The etchant composition of claim 2 , wherein a content of the assistance oxidizer is about 0.1 wt % to about 2 wt %.4. The etchant composition of claim 3 , wherein the assistance oxidizer includes one selected from a group consisting of phosphoric acid (HPO) claim 3 , nitric acid (HNO) claim 3 , acetic acid (CHCOOH) claim 3 , perchloric acid (HClO) claim 3 , and hydrogen peroxide (HO).5. The etchant composition of claim 1 , whereinthe ammonium persulfate content is about 0.1 wt % to about 20 wt %, the azole-based compound content is about 0.01 wt % to about 2 wt %, the water-soluble amine compound content is about 0.1 wt % to about 5 wt %, the sulfonic acid-containing compound content is about 0.1 wt % to about 10 wt %, and the nitrate-containing compound content is about 0.1 wt % to about 10 wt %.6. The etchant composition of claim 5 , wherein the phosphate-containing compound content is about 0.1 wt % to about 5 wt %.7. The etchant composition of claim 6 , wherein the chloride-containing compound content is about 0.001 wt % to about 1 wt %.8. The etchant composition of claim 1 , wherein the azole-based compound includes one selected from the group consisting of benzotriazole claim 1 , aminotetrazole claim 1 , imidazole claim 1 , and pyrazole.9. The etchant composition of claim 1 , wherein the water-soluble amine compound includes ...

LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF

A liquid crystal display and a manufacturing method thereof are disclosed, whereby a common electrode having a planar shape is formed directly on a common voltage line, and a semiconductor layer is formed on the common electrode and a gate line. The common electrode and a pixel electrode are formed on one substrate, with the common electrode being formed directly on the common voltage line. Accordingly, the costs of manufacturing the liquid crystal display may be reduced, and signal delay of a common voltage can be prevented. 1. A liquid crystal display comprising:a substrate;a gate line and a pixel electrode formed on the substrate, the pixel electrode having a single-layered portion including a first layer and a double-layered portion including the first layer and a second layer;a semiconductor layer formed on the gate line; anda data line, a source electrode, and a drain electrode formed on the semiconductor layer,wherein the drain electrode is formed on an upper surface of the double-layered portion of the pixel electrode,wherein the first layer of the pixel electrode is formed of poly indium tungsten oxide (poly-ITO) and the second layer of the pixel electrode is formed of a metal.2. The liquid crystal display of claim 1 , further comprising:a direct connecting part including a gate electrode formed of a same material as the gate line;a gate insulating layer formed on a portion of the gate electrode; anda contact electrode formed on the gate electrode and the gate insulating layer.3. The liquid crystal display of claim 2 , wherein the contact electrode is in contact with the portion of the gate electrode so as to transfer a gate signal from a driving part to the gate electrode.4. The liquid crystal display of claim 2 , wherein each of the gate line and the gate electrode includes a first layer formed of amorphous indium tungsten oxide (a-ITO) and a second layer formed of the metal.5. The liquid crystal display of claim 1 , further comprising:a passivation layer ...

LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF

A liquid crystal display and a manufacturing method thereof include a planar-shaped common electrode disposed directly on a common voltage line, and a semiconductor layer disposed on the common electrode and a gate line, serving as a gate insulating layer. Accordingly, it is possible to prevent signal delay of the common voltage and lower the manufacturing cost by disposing a common electrode and a pixel electrode on one substrate and disposing a common electrode directly on a common voltage line. 1. A liquid crystal display comprising:a substrate;a gate line and a common voltage line disposed on the substrate;a common electrode disposed directly on the common voltage line;a semiconductor layer disposed on the gate line and the common electrode; anda pixel electrode disposed on the semiconductor layer,wherein the common electrode and the pixel electrode are configured to overlap with each other, with the semiconductor layer disposed therebetween.2. The liquid crystal display of claim 1 , wherein the semiconductor layer is disposed on an entire surface of the substrate.3. The liquid crystal display of claim 2 , further comprising:a data line, a source electrode, and a drain electrode disposed on the semiconductor layer; anda passivation layer disposed on the source electrode and the drain electrode.4. The liquid crystal display of claim 3 , wherein the passivation layer comprises a contact hole for partially exposing the drain electrode and a cutout for partially exposing the data line claim 3 , andthe pixel electrode is connected to the drain electrode through the contact hole.5. The liquid crystal display of claim 4 , further comprising a shielding electrode configured to cover top and side surfaces of a part of the data line that is exposed through the cutout.6. A manufacturing method of a liquid crystal display claim 4 , the method comprising:forming a gate line and a common voltage line on a substrate;forming a common electrode directly on the common voltage ...

CANTILEVER SET FOR ATOMIC FORCE MICROSCOPES, SUBSTRATE SURFACE INSPECTION APPARATUS INCLUDING THE SAME, METHOD OF ANALYZING SURFACE OF SEMICONDUCTOR SUBSTRATE BY USING THE SAME, AND METHOD OF FORMING MICROPATTERN BY USING THE SAME

A method of forming a micropattern, a substrate surface inspection apparatus, a cantilever set for an atomic force microscope, and a method of analyzing a surface of a semiconductor substrate, and a probe tip the method including forming pinning patterns on a semiconductor substrate; forming a neutral pattern layer in spaces between the pinning patterns; and inspecting a surface of a guide layer that includes the pinning patterns and the neutral pattern layer by using an atomic force microscope (AFM). 118.-. (canceled)19. A substrate surface inspection apparatus , comprising:a supporter capable of accommodating a substrate;a measurement unit having a cantilever and a probe tip, the probe tip being at an end of the cantilever and being capable of contacting the substrate;a driving unit capable of changing relative positions of the substrate and the probe tip;a light source unit capable of irradiating light onto the cantilever;a sensor capable of obtaining information of a surface of the substrate from light reflected by the cantilever; anda determination unit determining whether the surface of the substrate is normal from the information of the surface of the substrate sensed by sensor,wherein the probe tip includes a probe tip base having a surface modified with a polymer.20. The substrate surface inspection apparatus as claimed in claim 19 , wherein the determination unit is configured to calculate a work of adhesion between the surface of the substrate and the probe tip and to determine whether the surface of the substrate is normal by comparing the obtained work of adhesion with a reference value.21. The substrate surface inspection apparatus as claimed in claim 20 , wherein:the work of adhesion is calculated from a surface energy between the surface of the substrate and the probe tip, andthe surface energy is determined by an interaction between the probe tip and the surface of the substrate.22. The substrate surface inspection apparatus as claimed in claim 21 , ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a support member having first and second surfaces, having a cavity, and including a wiring structure, a semiconductor chip having connection pads, a connection member including a first insulating layer, a first redistribution layer on the first insulating layer, and a plurality of first vias connecting the wiring structure and the connection pads to the first redistribution layer and an encapsulant encapsulating the semiconductor chip, The wiring structure includes wiring patterns disposed on the second surface of the support member, and the first insulating layer includes a first insulating coating covering the wiring patterns and a second insulating coating disposed on the first insulating coating and having a higher level of flatness than that of the first insulating coating. 1. A semiconductor package comprising:a support member having first and second surfaces opposing each other, having a cavity penetrating through the first and second surfaces, and including a wiring structure;a semiconductor chip disposed in the cavity and having an active surface having connection pads disposed thereon;a connection member including a first insulating layer disposed on the second surface of the support member, a first redistribution layer on the first insulating layer, and a plurality of first vias penetrating through the first insulating layer and connecting the wiring structure and the connection pads to the first redistribution layer; andan encapsulant encapsulating the semiconductor chip disposed in the cavity and covering the first surface of the support member,wherein the wiring structure includes wiring patterns disposed on the second surface of the support member, andthe first insulating layer includes a first insulating coating disposed on the second surface of the support member and covering the wiring patterns and a second insulating coating disposed on the first insulating coating and having a higher level of flatness than that of ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a support member having first and second surfaces opposing each other, including a cavity penetrating through the first and second surfaces, and having a primer layer disposed on the first surface; a connection member disposed on the first surface of the support member and having a redistribution layer, the primer layer being disposed between the connection member and the support member; a semiconductor chip having an active surface on which connection pads are disposed and an inactive surface opposing the active surface, the connection pads being electrically connected to the redistribution layer; and an encapsulant covering the second surface of the support member and the inactive surface of the semiconductor chip. 1. A semiconductor package comprising:a support member having first and second surfaces opposing each other, including a cavity penetrating through the first and second surfaces, and having a first primer layer disposed on the first surface;a connection member disposed on the first surface of the support member and having a redistribution layer, the first primer layer being disposed between the connection member and the support member;a semiconductor chip having an active surface on which connection pads are disposed and an inactive surface opposing the active surface, the connection pads being electrically connected to the redistribution layer; andan encapsulant covering the second surface of the support member and the inactive surface of the semiconductor chip.2. The semiconductor package of claim 1 , wherein the first primer layer is not formed on an inner side wall of the cavity.3. The semiconductor package of claim 1 , further comprising a second primer layer disposed on the second surface of the support member.4. The semiconductor package of claim 1 , wherein the support member includes a resin in which a reinforcing material is impregnated.5. The semiconductor package of claim 4 , wherein the reinforcing material ...

Display device

A display device includes: a first substrate including a display area; a thin film transistor positioned on the first substrate; a pixel electrode connected to the thin film transistor; a color filter overlapping the pixel electrode; a second substrate overlapping the first substrate; a liquid crystal layer positioned between the first substrate and the second substrate; and a stain correction layer positioned between the second substrate and the liquid crystal layer and including a semiconductor nanocrystal. The display area includes a first region and a second region excluding the first region. The stain correction layer is positioned in the first region.

SEMICONDUCTOR PACKAGE

A method of manufacturing a semiconductor package is provided and includes forming a protective layer on a passivation layer and a connection pad of a semiconductor chip exposed by a first opening of the passivation layer, forming an insulating layer on the protective layer, forming a via hole penetrating the insulating layer to expose the protective layer, forming a second opening by removing a portion of the protective layer through the via hole, and forming a connection via filling the via hole and the second opening and a redistribution layer on the connection via. The second opening and the via hole are connected to have a stepped portion. The first opening has a width narrower closer to the connection pad, and the second opening has a width wider closer to the connection pad. 1. A method of manufacturing a semiconductor package , the method comprising:forming a protective layer on a passivation layer and a connection pad of a semiconductor chip exposed by a first opening of the passivation layer;forming an insulating layer on the protective layer;forming a via hole penetrating the insulating layer to expose the protective layer;forming a second opening by removing a portion of the protective layer through the via hole; andforming a connection via filling the via hole and the second opening and a redistribution layer on the connection via,wherein the second opening and the via hole are connected to have a stepped portion,wherein the first opening has a width narrower closer to the connection pad, andwherein the second opening has a width wider closer to the connection pad.2. The method of claim 1 , wherein a wall surface of the second opening is recessed toward a wall surface of the first opening to form a recessed region claim 1 ,wherein the recessed region is formed between the insulating layer and the connection pad, andwherein the connection via is formed to fill at least a portion of the recessed region.3. The method of claim 2 , wherein the protective ...

Thin film transistor array panel and method for manufacturing the same

A thin film transistor array panel is disclosed. The thin film transistor array panel may include a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, a data wiring layer disposed on the substrate and including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode, a polymer layer covering the source electrode and the drain electrode, and a passivation layer disposed on the polymer layer. The data wiring layer may include copper or a copper alloy and the polymer layer may include fluorocarbon.

Method of manufacturing color filter substrate and method of manufacturing thin film transistor substrate

A method of manufacturing a color filter substrate includes forming a plurality of trenches having a predetermined depth by etching a surface of a transparent substrate, disposing a color filter material in the plurality of trenches to form a color filter layer, and forming a transparent electrode on the transparent substrate including the color filter layer therein.

ANODE FOR SECONDARY BATTERY COMPRISING ADDITIVE FOR IMPROVING LOW-TEMPERATURE CHARACTERISTICS, AND SECONDARY BATTERY HAVING THE SAME

The present disclosure refers to an anode for a secondary battery that comprises a low-temperature additive, and an electrochemical device using the anode. More specifically, the present disclosure provides a carbon-based anode material comprising a low-temperature additive such as lithium titanium oxide (LTO) to improve low-temperature output characteristics, thereby providing high output at room temperature and even a low temperature, and an electrochemical device using the anode. 1. An anode for a secondary battery , comprising an anode current collector and an anode active material layer formed on at least one surface of the current collector ,{'sup': '+', 'wherein the anode active material layer comprises an anode active material having a reaction potential (vs. Li/Li) of 1V or less, and an additive for improving low-temperature characteristics, the additive comprising titanium oxide, lithium titanium oxide (LTO) or a mixture thereof.'}3. The anode of claim 2 , wherein the lithium titanium oxide is any one selected from the group consisting of LiTiO claim 2 , LiTiO claim 2 , LiTiO claim 2 , LiTiO claim 2 , LiTiO claim 2 , LiTiO claim 2 , LiTiO claim 2 , and a mixture thereof.4. The anode of claim 1 , wherein the additive for improving low-temperature characteristics is present in an amount of 2 to 50 wt % based on 100 wt % of the anode active material layer.5. The anode of claim 1 , wherein the lithium titanium oxide comprises primary particles claim 1 , secondary particles being aggregates of the primary particles claim 1 , or a mixture thereof.6. The anode of claim 5 , wherein the primary particles of the lithium titanium oxide may have a diameter (D) of 0.01 to 2 μm.7. The anode of claim 5 , wherein claim 5 , the primary particles in the lithium titanium oxide are present in an amount of 50 to 100 wt % based on 100 wt % of the lithium titanium oxide.8. The anode of claim 1 , wherein the anode active material comprises at least one of the following a) to c):a ...

THIN FILM TRANSISTOR ARRAY PANEL

A thin film transistor array panel includes: a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, and a data wire layer disposed on the substrate and including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode. In addition, at least one of the data line, the source electrode or the drain electrode of the data wire layer includes a barrier layer and a main wiring layer disposed on the barrier layer. The main wiring layer includes copper or a copper alloy. Also, the barrier layer includes a metal oxide, and the metal oxide includes zinc. 1. A thin film transistor array panel comprising:a gate line disposed on a substrate and including a gate electrode;a gate insulating layer disposed on the gate line;a semiconductor layer including an oxide semiconductor disposed on the gate insulating layer, wherein the semiconductor layer extends in a longitudinal direction and includes a projection which extends toward the gate electrode; anda data line intersecting the gate line;a source electrode connected to the data line;a drain electrode facing the source electrode, anda passivation layer disposed on the data line, the drain electrode and on a portion of the projection of the semiconductor layer disposed between the source electrode and the drain electrode,wherein the data line, the source electrode and the drain electrode each include a barrier layer, a main wiring layer disposed on the barrier layer, and a capping layer disposed on the main wiring layer,wherein the main wiring layer includes a metal or a metal alloy,wherein the barrier layer and the capping layer includes a metal oxide, andwherein the capping layer is in a polycrystalline state.2. The thin film transistor of claim 1 , wherein the barrier layer includes one of indium-zinc oxide (IZO) claim 1 , gallium-zinc oxide (GZO) claim 1 , ...

THIN FILM TRANSISTOR PANEL HAVING AN ETCH STOPPER ON SEMICONDUCTOR

A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper. 1. A method for forming a panel comprising a thin film transistor , the method comprising:forming an oxide semiconductor pattern comprising a channel region;forming an etch stopper at a position corresponding to the channel region; andforming a first electrode and a second electrode spaced apart from the first electrode, the channel region configured to connect the first electrode to the second electrode,wherein the oxide semiconductor pattern, the first electrode, and the second electrode are formed using a first mask.2. The method of claim 1 , further comprising:disposing a first conductive layer on a substrate;disposing a first insulating layer on the first conductive layer;disposing an oxide semiconductor layer on the first insulating layer;disposing a second conductive layer on the etch stopper and the oxide semiconductor layer;wherein the oxide semiconductor layer and the second conductive layer are patterned using the first mask to form the oxide semiconductor pattern, the first electrode, and the second electrode.3. The method of claim 2 , further comprising:forming a second insulating layer on the first electrode and the second electrode;patterning the second insulating layer to form a contact hole exposing the first electrode; andforming a third conductive layer on the second insulating layer;patterning the third conductive layer to form a third electrode,wherein the third electrode is connected to the first electrode via the contact hole.4. The method of claim 3 , wherein the second insulating layer comprises a passivation layer.5. The method of claim 3 , wherein the second insulating layer comprises a color filter.6. The method of ...

Fan-out semiconductor package

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; and an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip. The first interconnection member includes a first insulating layer in contact with the second interconnection member, a first redistribution layer disposed on a surface of the first insulating layer in contact with the second interconnection member and electrically connected to the connection pads, and a blocking layer disposed on the surface of the first insulating layer on which the first redistribution layer is disposed and surrounding the through-hole.

Method for Manufacturing an Electrode Assembly for a Battery Cell and Battery Cell

The invention refers to a method for manufacturing an electrode assembly for a battery cell, whereat segments of a first electrode are placed between a continuous first separator sheet and a continuous second separator sheet; segments of a second electrode are placed on an opposite side of the first separator sheet in respect of the segments of the first electrode and on an opposite side of the second separator sheet in respect of the segments of the first electrode such that a tape element is formed; and the tape element is folded such that the segments of the first electrode and the segments of the second electrode are aligned in a stacking direction. The invention also refers to a battery cell, in particular a lithium ion battery cell, comprising an electrode assembly manufactured using the method according to the invention.

METHOD OF MANUFACTURING A PACKAGE FOR EMBEDDING ONE OR MORE ELECTRONIC COMPONENTS

The present invention relates to the field of integrating electronic systems that operate at mm-wave and THz frequencies. A monolithic multichip package, a carrier structure for such a package as well as manufacturing methods for manufacturing such a package and such a carrier structure are proposed to obtain a package that fully shields different functions of the mm-wave/THz system. The package is poured into place by polymerizing photo sensitive monomers. It gradually grows around and above the MMICs (Monolithically Microwave Integrated Circuit) making connection to the MMICs but recessing the high frequency areas of the chip. The proposed approach leads to functional blocks that are electromagnetically completely shielded. These units can be combined and cascaded according to system needs. 1forming aback-aide metallization layer,forming a polymer profile in layers on top of said backside metallization layer by subsequently forming two or more polymer layers by photo polymerisation, wherein one or more cavities are formed in said polymer profile for placing one or more electronic components therein, said electronic components having a back-side terminal and one or more front-side terminals,forming a front-side metallization layer on top of said polymer profile.. A method of manufacturing a carrier structure of a package for embedding one or more electronic components, in particular microwave integrated circuits and discrete passive components, comprising the steps of: This application is a continuation of U.S. application Ser. No. 13/348,295, filed Jan. 11, 2012, which is based upon and claims the benefit of priority to European patent application 11151208.3 filed on Jan. 18, 2011. The entire contents of the foregoing application is hereby incorporated by reference into the present disclosure.The present invention relates to a method of manufacturing a carrier structure of a package for embedding one or more electronic components, in particular microwave ...

Method of manufacturing a package for embedding one ore more electronic components

The present invention relates to the field of integrating electronic systems that operate at mm-wave and THz frequencies. A monolithic multichip package, a carrier structure for such a package as well as manufacturing methods for manufacturing such a package and such a carrier structure are proposed to obtain a package that fully shields different functions of the mm-wave / THz system. The package is poured into place by polymerizing photo sensitive monomers. It gradually grows around and above the MMICs (Monolithically Microwave Integrated Circuit) making connection to the MMICs but recessing the high frequency areas of the chip. The proposed approach leads to functional blocks that are electromagnetically completely shielded. These units can be combined and cascaded according to system needs.

Positive electrode for secondary battery, method of preparing the same, and lithium secondary battery including the positive electrode

The present invention relates to a positive electrode for a secondary battery in which a maximum diameter of internal pores is controlled to be less than 1 μm, a method of preparing the same, and a secondary battery including the positive electrode.

Composite materials conducting lithium ions and their production and their use in electrochemical cells

Gegenstand der Erfindung ist ein Lithiumionen leitendes Kompositmaterial (3, 4), umfassendmindestens ein partikelförmiges, anorganisches Feststoffelektrolytmaterial (10); undmindestens ein Lithiumionen leitendes, anorganisches Füllmaterial (30);dadurch gekennzeichnet, dassdas Lithiumionen leitende, anorganische Füllmaterial (30) im Wesentlichen sämtliche freien Hohlräume (20), die sich zwischen dem mindestens einen partikelförmigen Feststoffelektrolytmaterial (10) ausbilden, ausfüllt,das Lithiumionen leitende, anorganische Füllmaterial (30) eine Schmelztemperatur von ≤1000°C aufweist, unddas Lithiumionen leitende, anorganische Füllmaterial (30) in einem Temperaturbereich von 0°C bis einschließlich der Schmelztemperatur des Lithiumionen leitenden, anorganischen Füllmaterials (30) mit dem mindestens einen partikelförmigen, anorganisches Feststoffelektrolytmaterial (10) keine chemische Reaktion eingeht.Gegenstand der Erfindung ist auch ein Verfahren zur Herstellung eines solchen Lithiumionen leitenden Kompositmaterials (3, 4), sowie dessen Verwendung als Separator oder Elektrode in einer elektrochemischen Zelle. The invention relates to a composite material (3, 4) which conducts lithium ions and comprises at least one particulate, inorganic solid electrolyte material (10); andat least one lithium ion conductive inorganic filler (30); characterized in that the lithium ion conductive inorganic filler (30) fills substantially all of the free cavities (20) that form between the at least one particulate solid electrolyte material (10), the lithium ion conductive , inorganic filler material (30) has a melting temperature of ≤1000 ° C, and the lithium ion conductive inorganic filler material (30) in a temperature range from 0 ° C up to and including the melting temperature of the lithium ion conductive inorganic filler material (30) with the at least one particulate, inorganic solid electrolyte material (10) does not undergo a chemical reaction. The invention also relates to ...

Solid electrolyte material with improved chemical stability

Gegenstand der Erfindung ist ein Feststoffelektrolytmaterial (1) für eine elektrochemische Zelle (10), insbesondere eine Lithiumionenbatteriezelle, umfassend:mindestens einen Lithiumionen leitenden Feststoffelektrolyt (2) vom Granat-Typ, undmindestens ein Beschichtungsmaterial (3), welches auf mindestens einem Teil der Oberfläche des Lithiumionen leitenden Feststoffelektrolyts (2) vom Granat-Typ aufgebracht ist,wobei das mindestens eine Beschichtungsmaterial (3) mindestens eine Lithiumionen leitende Verbindung umfasst, die chemisch stabil gegenüber Luft und Feuchtigkeit ist.Ein weiterer Gegenstand der Erfindung ist ein Verfahren zur Herstellung des Feststoffelektrolytmaterials (1), dessen Verwendung sowie eine elektrochemische Zelle (10), umfassend das Feststoffelektrolytmaterial (1). The invention relates to a solid electrolyte material (1) for an electrochemical cell (10), in particular a lithium ion battery cell, comprising: at least one lithium ion conductive solid electrolyte (2) of the garnet type, and at least one coating material (3) which is applied to at least part of the surface of the lithium ion conductive solid electrolyte (2) of the garnet type, wherein the at least one coating material (3) comprises at least one lithium ion conductive compound which is chemically stable to air and moisture. Another object of the invention is a method for producing the solid electrolyte material (1), its use and an electrochemical cell (10) comprising the solid electrolyte material (1).

Display substrate and method of manufacturing the same

Cantilever set for atomic force microscopes, substrate surface inspection apparatus including the same, method of analyzing surface of semiconductor substrate by using the same, and method of forming micropattern by using the same

A method of forming a micropattern, a substrate surface inspection apparatus, a cantilever set for an atomic force microscope, and a method of analyzing a surface of a semiconductor substrate, and a probe tip the method including forming pinning patterns on a semiconductor substrate; forming a neutral pattern layer in spaces between the pinning patterns; and inspecting a surface of a guide layer that includes the pinning patterns and the neutral pattern layer by using an atomic force microscope (AFM).

Thin film transistor panel and fabricating method thereof

A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Medium composition for culturing t cells and method for culturing t cells using same

Semiconductor package

A semiconductor package includes a connection member having a first surface and a second surface opposing each other and including a first redistribution layer on the second surface and at least one second redistribution layer on a level different from a level of the first redistribution layer; a semiconductor chip on the first surface of the connection member; a passivation layer on the second surface of the connection member, and including openings; UBM layers connected to the first redistribution layer through the openings; and electrical connection structures on UBM layers. An interface between the passivation layer and the UBM layers has a first unevenness surface, an interface between the passivation layer and the first redistribution layer has a second unevenness surface, connected to the first unevenness surface, and the second unevenness surface has a surface roughness greater than a surface roughness of the second redistribution layer.

Resist topcoat composition, and method of forming patterns using the composition

A resist topcoat composition and a method of forming patterns using the resist topcoat composition are provided. The resist topcoat resist topcoat composition includes an acrylic polymer including a structural unit containing a hydroxy group and a fluorine; at least one acid compound selected from a sulfonic acid compound containing at least one fluorine, a sulfonimide compound containing at least one fluorine, and a carboxylic acid compound containing at least one fluorine; and a solvent.

Discharge prevention cable

A cable prevents discharge caused by capacitive current. The cable includes a conductor, a first insulation layer covering the conductor, a low-dielectric insulation layer covering the first insulation layer, and a second insulation layer covering the low-dielectric insulation layer.

Resist topcoat composition, and method of forming patterns using the composition

A resist topcoat composition includes an acrylic polymer including a structural unit containing a hydroxy group and a fluorine; a mixture including a sulfonic acid compound containing at least one fluorine and a carboxylic acid compound containing at least one fluorine in a weight ratio of about 1:0.1 to about 1:50; and a solvent. A method of forming patterns uses the resist topcoat composition to form a topcoat over a patterned substrate.

Process for the production of electrode materials

Gegenstand der Erfindung ein Verfahren zur Herstellung einer Elektrode umfassend:- herstellen einer ersten Mischung umfassend mindestens ein Lithiumsalz (1), mindestens ein Polymer (2) und mindestens ein Lösungsmittel (3);- herstellen einer zweiten Mischung, umfassend die erste Mischung und mindestens ein leitfähiges Material (4); und- herstellen einer dritten Mischung umfassend die zweite Mischung und mindestens ein Elektrodenaktivmaterial (5).Ferner ist Gegenstand der Erfindung eine Elektrode hergestellt nach einem erfindungsgemäßen Verfahren, sowie eine elektrochemische Zelle umfassend eine Elektrode hergestellt nach einem erfindungsgemäßen Verfahren. The invention relates to a method for producing an electrode comprising: - producing a first mixture comprising at least one lithium salt (1), at least one polymer (2) and at least one solvent (3); - producing a second mixture comprising the first mixture and at least one a conductive material (4); and- producing a third mixture comprising the second mixture and at least one electrode active material (5). The invention furthermore relates to an electrode produced by a method according to the invention and an electrochemical cell comprising an electrode produced by a method according to the invention.

Fusion protein comprising coronavirus-derived receptor-binding domain and nucleocapsid protein, and use thereof

The present invention relates to a fusion protein comprising a SARS-CoV-2-derived receptor-binding domain and a nucleocapsid protein, and the use thereof. The fusion protein comprising a coronavirus-derived receptor-binding domain and a nucleocapsid protein is highly applicable to a multivalent vaccine composition having greatly improved in-vivo half-life and remarkably superior efficacy compared to an immunogenic composition comprising only a receptor-binding domain. In particular, the fusion protein can greatly improve the titer of the coronavirus-specific antibody formation and T-cell immune response, and is thus useful for the prevention and treatment of coronaviruses comprising SARS-CoV-2.

Method for recovering cathode material

The present invention relates to a method for recycling a positive electrode material to an extent close to an original thereof from a positive electrode, and when the present invention is applied, only fluorine components on a surface may be selectively removed without loss of lithium components of the positive electrode material.

Composition for anticancer treatment, comprising nk cells and fusion protein which comprises il-2 protein and cd80 protein

Coronavirus-derived receptor-binding domain variant having reduced ace2-binding affinity and vaccine composition comprising the same

Disclosed are a novel coronavirus-derived receptor-binding domain variant having reduced ACE2-binding affinity, a fusion protein comprising the same, and the use thereof. It is possible to overcome the drawbacks of conventional vaccines using the coronavirus spike protein or receptor-binding domain thereof, wherein the reduced ACE2 expression due to binding to ACE2 and negative feedback may lead to side effects of the lungs or heart, and in particular, may be fatal to patients suffering from underlying diseases of the lungs or heart. In particular, the fusion protein constructed by fusing the coronavirus receptor-binding domain with the Fc domain is imparted with a greatly improved in-vivo half-life, and has superior efficacy by further combining N protein, M protein, ORF protein, or the like of SARS-CoV-2 therewith through additional modification and thus is highly applicable to a multivalent immunogenic composition. Therefore, the coronavirus receptor-binding domain variant is useful for the prevention and treatment of coronavirus infections comprising SARS-CoV-2.

Sposób wytwarzania zespołu elektrod dla ogniwa akumulatorowego oraz ogniwo akumulatorowe

Composicion para el tratamiento anticancerigeno, que comprende celulas nk y proteina de fusion que comprende la proteina il-2 y la proteina cd80.

Se proporciona un agente anticancerígeno que comprende, como ingredientes activos, células NK y una proteína de fusión que comprende una proteína IL-2 y una proteína CD80. En una modalidad específica, una proteína de fusión que comprende un fragmento de CD80, un Fc de inmunoglobulina y una variante de IL-2 puede activar inmunocitos tales como células asesinas naturales. Adicionalmente, dado que el cáncer puede inhibirse efectivamente la composición farmacéutica, cuando se coadministra con células asesinas naturales, aumenta la actividad inmunitaria en el cuerpo de modo que se puede usar efectivamente para el cáncer, de esta manera tiene una alta aplicabilidad industrial.

Medium composition for culturing t cells and method for culturing t cells using same

Composicion de medio para el cultivo de linfocitos t y metodo para el cultivo de linfocitos t mediante el uso de la misma.

La presente invención se refiere a una composición para la proliferación de linfocitos T, que contiene un dímero de proteína de fusión que comprende una proteína IL-2 o una variante de esta y una proteína CD80 o un fragmento de esta, y a un método para cultivar los linfocitos T mediante el uso de la misma. Los linfocitos T cultivados de acuerdo con la presente invención aumentan la proliferación y la actividad de los linfocitos T incluso sin usar perlas magnéticas unidas a anticuerpos contra CD3/CD28, y proliferan los linfocitos T mediante el cultivo de células mononucleares de sangre periférica del propio paciente y no es probable que causen efectos secundarios en el cuerpo humano, y por lo tanto se usará ampliamente como un nuevo agente terapéutico de linfocitos T. Además, en el caso de los linfocitos T CD8+ cultivados como se describió anteriormente, la actividad de estos aumenta y, por tanto, los linfocitos T CD8+ pueden usarse como un agente terapéutico más efectivo.

Composition for anticancer treatment, comprising NK cells and fusion protein which comprises IL-2 protein and CD80 protein

Provided is an anticancer agent, comprising, as active ingredients, NK cells and a fusion protein which comprises an IL-2 protein and a CD80 protein. In one specific embodiment, a fusion protein comprising a CD80 fragment, an immunoglobulin Fc and an IL-2 variant can activate immunocytes such as natural killer cells. In addition, since cancer can be effectively inhibited when co-administering with natural killer cells, the pharmaceutical composition increases the immune activity in the body so as to be effectively usable for cancer, thereby having high industrial applicability.

Method and apparatus for anonymizing personal information

An apparatus for anonymizing personal information according to an embodiment may include an encoder configured to generate an input latent vector by extracting a feature of input data, a generator configured to generate reconstructed data by demodulating a predetermined content vector based on a style vector generated based on the input latent vector, and a discriminator configured to discriminate genuine data and fake data by receiving the reconstructed data and real data.

Photoresist topcoat composition, and method of forming patterns using the composition

Disclosed photoresist topcoat compositions including a polymer including at least one of the first structural units represented by Chemical Formula 1 or Chemical Formula 2, a thermal acid generator (TAG), and a solvent; and a method of forming patterns using the photoresist topcoat composition.

Verfahren zur herstellung einer positiven elektrode für eine batteriezelle

Es wird ein Verfahren (10) zur Herstellung einer positiven Elektrode für eine Batteriezelle beschrieben, mit einem Aktivmaterial und einem Leitadditiv, wobei das Aktivmaterial eine erste Anzahl an insbesondere kugelförmigen Aktivmaterialpartikeln mit einem ersten mittleren Durchmesser aufweist und wobei das Leitadditiv eine zweite Anzahl an insbesondere kugelförmigen Leitadditivpartikeln mit einem zweiten mittleren Durchmesser aufweist, wobei in einem ersten Verfahrensschritt (102) das Aktivmaterial und das Leitadditiv bereitgestellt werden, wobei die Anzahl der Leitadditivpartikel abhängig von einem Verhältnis des zweiten mittleren Durchmessers zu dem ersten mittleren Durchmesser und von der Anzahl der Aktivmaterialpartikel eingestellt wird.

Verfahren zur herstellung einer positiven elektrode für eine batteriezelle

Method for producing a positive electrode for a battery cell

The invention describes a method (10) for producing a positive electrode for a battery cell, comprising an active material and a conductive additive, wherein the active material has a first number of, in particular spherical, active material particles with a first mean diameter, and wherein the conductive additive has a second number of, in particular spherical, conductive additive particles with a second mean diameter, wherein the active material and the conductive additive are provided in a first method step (102), wherein the number of conductive additive particles is adjusted depending on a ratio of the second mean diameter to the first mean diameter and on the number of active material particles.

Method for recovering cathode material

Immunoassay device for diagnosing congestive heart failure

Method for recycling positive electrode material

A method for recycling a positive electrode material. the method includes obtaining positive electrode material particles from a positive electrode. The method further includes mixing the positive electrode material particles with a solution or powder containing sodium ions and heat-treating the mixture including the positive electrode material particles and the solution or power containing sodium ions. The method further includes rinsing the heat-treated positive electrode material particles with water.

Fan-out semiconductor package

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; and an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip. The first interconnection member includes a first insulating layer in contact with the second interconnection member, a first redistribution layer disposed on a surface of the first insulating layer in contact with the second interconnection member and electrically connected to the connection pads, and a blocking layer disposed on the surface of the first insulating layer on which the first redistribution layer is disposed and surrounding the through-hole.

Verfahren zur herstellung einer elektrode einer batteriezelle, batteriezelle und verwendung derselben

Es wird ein Verfahren (10) zur Herstellung einer Elektrode einer Batteriezelle bereitgestellt, wobei in einem ersten Mischschritt (102) ein erster Anteil an Kohlenstoffnanoröhren und ein Elektrodenaktivmaterial in einem Mischgerät mit einer ersten Drehzahl zur Bildung eines ersten Gemisches zusammengemischt werden. Weiter werden in einem zweiten Mischschritt (104) ein zweiter Anteil an Kohlenstoffnanoröhren (206) und das erste Gemisch in dem Mischgerät mit einer zweiten Drehzahl zur Bildung eines zweiten Gemisches zusammengemischt, wobei die erste Drehzahl größer als die zweite Drehzahl ist.

Discharge prevention cable

A cable prevents discharge caused by capacitive current. The cable includes a conductor, a first insulation layer covering the conductor, a low-dielectric insulation layer covering the first insulation layer, and a second insulation layer covering the low-dielectric insulation layer.

Immunoassay device for diagnosing congestive heart failure

Pouch cell, in particular pouch cell for a battery of electric vehicles, and method of manufacturing such a pouch cell

The invention relates to a pouch cell, in particular a pouch cell for a battery of an electric vehicle, with a soft body, the body consisting of a soft and flexible plastic main material, wherein the plastic main material forms a bag (12) for encapsulating at least one battery cell and wherein the bag (12) has at least one sealing area (30) where the bag (12) was sealed after being filled with the at least one battery cell wherein the sealing area (30) comprises a modified sealing material and/or the sealing area (30) comprises an additional sealing material (32) such that the melting temperature of the sealing bag is reduced in the sealing area (30) compared to the melting temperature of the plastic main material.

Medium composition for culturing T cells and method for culturing T cells using same

The present invention relates to a composition for proliferating T cells, containing a fusion protein dimer comprising IL-2 protein or a variant thereof and CD80 protein or a fragment thereof, and to a method for culturing T cells using same. The T cells cultured according to the present invention increase the proliferation and activity of T cells even without using CD3/CD28 antibody-bound magnetic beads and proliferate T cells by culturing a patient's own peripheral blood mononuclear cells and are not likely to cause side effects in the human body, and thus will be widely used as a novel T cell therapeutic agent. Furthermore, in the case of CD8+ T cells cultured as described above, the activity thereof increases, and thus, the CD8+ T cells can be used as a more effective therapeutic agent.

Anode for secondary battery comprising additive for improving low-temperature characteristics, and secondary battery having the same

The present disclosure refers to an anode for a secondary battery that comprises a low-temperature additive, and an electrochemical device using the anode. More specifically, the present disclosure provides a carbon-based anode material comprising a low-temperature additive such as lithium titanium oxide (LTO) to improve low-temperature output characteristics, thereby providing high output at room temperature and even a low temperature, and an electrochemical device using the anode.