Fehlertoleranter Festkörper-Flugdatenschreiber

Technologien zur Durchführung einer Orchestrierung mit Online-Analyse von Telemetriedaten

Technologien zur Durchführung einer Orchestrierung mit Online-Analyse von Telemetriedaten umfassen einen Orchestrator-Server zum Zuweisen von Arbeitslasten an jeden aus einer Gruppe verwalteter Knoten, Empfangen von Telemetriedaten, die eine Ressourcennutzung anzeigen, von den verwalteten Knoten, wenn die Arbeitslasten ausgeführt werden, Erzeugen einer Datenanalyse in Abhängigkeit von den Telemetriedaten, wenn die Arbeitslasten ausgeführt werden, Bestimmen von Anpassungen der Arbeitslastzuweisungen in Abhängigkeit von der Datenanalyse, wenn die Arbeitslasten ausgeführt werden, um die Ressourcennutzung unter den verwalteten Knoten zu erhöhen, und Anwenden der bestimmten Anpassungen auf die verwalteten Knoten, wenn die Arbeitslasten ausgeführt werden. Außerdem werden andere Ausführungsformen beschrieben und beansprucht.

Technologien zum Verwalten der Zuweisung von Beschleunigerressourcen

Technologien zum dynamischen Verwalten der Zuweisung von Beschleunigerressourcen enthalten einen Orchestrator-Server. Der Orchestrator-Server hat die Aufgabe, einem verwalteten Knoten eine Arbeitslast zur Ausführung zuweisen, einen vorhergesagten Bedarf für eine oder mehrere Beschleunigerressourcen zu bestimmen, um die Ausführung eines oder mehrerer Jobs innerhalb der Arbeitslast zu beschleunigen, vor dem vorhergesagten Bedarf eine oder mehrere Beschleunigerressourcen bereitzustellen, um den einen oder die mehreren Jobs zu beschleunigen, und dem verwalteten Knoten die eine oder die mehreren bereitgestellten Beschleunigerressourcen zuzuweisen, um die Ausführung des einen oder der mehreren Jobs zu beschleunigen. Andere Ausführungsformen werden ebenfalls beschrieben und beansprucht.

Boundary Scan-Kette für gestapelten Speicher

Eine Boundary Scan-Kette für gestapelten Speicher. Eine Ausführungsform eines Speichergeräts umfasst ein Systemelement und einen Speicherblock, der eine oder mehrere Speicherchiplagenschichten umfasst, wobei jede Speicherchiplagenschicht Eingabe-Ausgabe-(I/O)-Zellen und eine Boundary Scan-Kette für die I/O-Zellen umfasst. Eine Boundary Scan-Kette einer Speicherchiplagenschicht umfasst einen Scankettenteil für jede der I/O-Zellen, wobei der Scankettenteil für eine I/O-Zelle einen ersten Scanlogik-Multiplexer umfasst, einen Scanlogik-Latch, wobei ein Eingang des Scanlogik-Latches mit einem Ausgang des ersten Scanlogik-Multiplexers gekoppelt ist, und einen Decoder, um Befehlssignale an die Boundary Scan-Kette bereitzustellen.

Speicherbaustein

Speicherbaustein (700), aufweisend: mehrere industriestandardisierte integrierte dynamische Direktzugriffsspeicher(DRAM)-Schaltkreise (720), die in einer vertikalen Richtung gestapelt sind, wobei die mehreren integrierten DRAM-Schaltkreise einen Arbeitspool (885, 886) von integrierten DRAM-Schaltkreisen und einen Ersatzpool (895) von integrierten DRAM-Schaltkreisen aufweisen; und einen integrierten Pufferschaltkreis (710) zum Bilden einer Schnittstelle zwischen den integrierten DRAM-Schaltkreisen und einem Speicherbus (730) durch Puffer von Adress- und/oder Steuer- und/oder Datensignalen, um elektrische Lasten der integrierten DRAM-Schaltkreise von dem Speicherbus elektrisch zu isolieren, wobei der integrierte Pufferschaltkreis konfiguriert ist, um zumindest einen integrierten DRAM-Schaltkreis von dem Arbeitspool von integrierten DRAM-Schaltkreisen durch zumindest einen integrierten DRAM-Schaltkreis von dem Ersatzpool von integrierten DRAM-Schaltkreisen zu ersetzen.

Magnetspeicher

STATISCHE HALBLEITERSPEICHERANLAGE.

HALBLEITERBAUELEMENT UND VERFAHREN ZU SEINER HERSTELLUNG

A rod memory array

... 1,096,840. Magnetic storage apparatus. NATIONAL CASH REGISTER CO. July 8, 1966 [Aug. 6, 1965], No. 30799/66. Heading H3B. In a rod memory array insulated conductive wire is woven perpendicular to the axes of the magnetic rods so that the wire passes by opposite sides of adjacent rods to produce a plurality of half-turn solenoids each coupled to a respective one of the rods. A plate 10, Fig. 1, provided with apertures 10a is first positioned over dummy rods 15a on a support 15 which rods protrude through the apertures 10a to act as mandrels about which the solenoid weaving pattern 18 is formed. After the solenoids have been formed the pins 15a are formed and the magnetic rods 12 comprising an inner conductive substrate on which is deposited a thin bi-stable magnetic film, Fig. 2 (not shown), are inserted in their place. In the weaving pattern of Fig. 1 of a particular row or column a conductive wire starts at a guide pin 19, is woven back and forth between the pins 15a until the end of the ...

Improvements in or relating to methods of manufacturing magnetic matrix arrangements

... 1,146,615. Magnetic storage apparatus. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 16 March, 1966 [19 March, 1965], No. 11525/66. Heading H3B. A magnetic storage matrix is made from a semi-conductor wafer, the peripheral areas of the wafer having transistors and diodes formed on insulated islands and the magnetic storage elements being formed by magnetically coating a network of grooves surrounded by the islands. A silicon wafer has an appropriately doped layer for the initial stages of the manufacture of diodes and transistors grown epitaxially thereon. This layer is then removed as far as the areas to be occupied by the diodes and transistors and coated with a silicon insulating layer, Figs. 1, 2 (not shown). The insulating layer has grown on to it a polycrystalline layer and the opposite side of the block is removed by grinding so that a semi-conductor wafer is obtained which has insulated islands (I) for the formation of the transistors and diodes, the finished wafer being in the ...

Improvements relating to magnetic storage arrangements

... 1,122,385. Circuits employing bi-stable magnetic elements. PLESSEY UK Ltd. 3 Dec., 1965 [7 Dec.. 1964], No. 49628/64. Heading H3B. A magnetic storage element comprises a thin film F of isotropic material having a rectangular hysteresis characteristic, parallel first and second word conductors U, V and an orthogonal digit conductor D being positioned in operative proximity. All three conductors are energized to write a binary " 1." The film may be of nickel-iron alloy which is deposited on to a glass or copper cylindrical former by evaporation, chemical deposition or electroplating, the first and second word conductors being subsequently threaded through the cylindrical former. A matrix store is shown in Fig. 3 in which a binary word may be stored magnetically along any of the cylindrical films F1-F9. To write a word a first and a second word conductor U, V common to a selected cylindrical film are pulsed at the same time as digit conductors D1, D2 are selectively energized. Coincident energization ...

Inkjet printing of cross point passive matrix devices

Methods of manufacturing a cross-point device such as an organic ferroelectric memory array can use inkjet printing from solution in ambient conditions to deposit electrodes 200 and regions of functional material 150 such as ferroelectric material or semiconductor material between top 200 and bottom 100 electrodes at the intersections, thereby reducing the need for lithography and planarising techniques. In some embodiments, two or three sub-arrays of overlapping or interlacing crossed electrodes are formed, with areas of dielectric material (fig 4c; 160b, 160c) printed between sub-arrays of electrodes to electrically insulate the arrays from one another, so that regions of functional material which are part of adjacent cross-point arrays at least partially overlap on the same vertical level. Intersecting electrodes for each array may be at an angle to one another other than 90 degrees (see figs 9). A wetting layer may be deposited on the functional material prior to deposition of the electrodes ...

A method of inserting wires into parallel slots

... 1,031,410. Magnetic storage apparatus. STANDARD TELEPHONES & CABLES Ltd. Nov. 12, 1964, No. 46120/64. Heading H3B. Wires are inserted into parallel slots 28 of a ferrite plate 27 of a waffle-iron memory by winding a continuous piece of wire around two spaced parallel rods 10, 11 so that successive upper 25 and lower 26 lengths of the wire between the rods are spaced from one another along the lengths of the rods by the distance between the slots 28, and inserting the successive lengths of wire into the slots. The rods 10 and 11 are provided with a helical thread having twice the pitch of the slots, and after winding the wire on the jig the latter is lowered so that the lower half 26 of the wire is lowered into alternate slots 28 and followed by the upper half 26. Alternatively, the two halves may be clamped coplanar before insertion. After anchoring the wires they are severed along rod 10 and rod 11 withdrawn. A polished substrate coated with an isotropic magnetic film is placed over the ...

Improvements relating to magnetic data storage matrices

... 1,046,454. Magnetic storage apparatus. ELECTRIC & MUSICAL INDUSTRIES Ltd. Feb. 6, 1963 [Nov. 10, 1961], No. 40262/61. Heading H3B. A magnetic matrix store is constructed by bonding two sheets of copper together by means of an insulating resin, etching the copper sheets so as to form row and column conductors A, B supported by a resin sheet, bonding the assembly into a frame C, dissolving the resin sheet other than that immediately between the row and column conductors, insulating the conductors with a suspension of glass powder in resin followed by a lacquer coating, and finally depositing a film of magnetic alloy over the lacquer coating. The row and column conductors may be arranged either as shown in Fig. 1 or in Fig. 2. Alternatively the conductors may be positioned as shown in Fig. 3. In a modification the manufacturing stage of dissolving the resin sheet is omitted, and both sides of the sheet with the affixed conductors are coated with magnetic alloy with or without the lacquer coating ...

Memory matrices.

... 1,165,513. Magnetic storage apparatus. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 24 May, 1968 [27 May, 1967], No. 24909/68. Heading H3B. A magnetic storage matrix is formed by inserting annular cores 1, into circular recesses 3 in a metal plate 2, each recess containing at least one plate projection 5 which extends through the associated core and above the plate surface, and the plate having grooves 7 of greater depth then the recesses. Subsequently, the recesses, grooves, and the plate are coated with a layer of insulating material e.g. epoxy resin, the extremities of the plate projections being exposed. The plate projections are then interconnected by wiring such as printed conductors, and the bases of the plate projections electrically separated from each other by removing material from the surface of the plate opposite the recesses to an extent such as to expose the grooves. The recesses and grooves may be formed either by etching or a compression and extrusion process, and the ...

EXCHANGEABLE CONNECTING ARRAYS FOR DOUBLE-SIDED DIMM PLACING

SEMICONDUCTOR MEMORY.

SEMICONDUCTOR MEMORY.

A biasing technique for a high density sram

Scalable data processing apparatus

SCALABLE DATA PROCESSING APPARATUS

In a scalable data processing appa-ratus, particularly a data storage appara-tus, one or more thin-film devices which form a substantially planar layer com-prise a plurality of sublayers of thin film. Two or more thin-film devices are pro-vided as an integrated stack of the sub-stantially planar layers which form the thin-film devices, such that the appara-tus thereby forms a stacked configura-tion. Each thin-film device comprises one or more memory areas which form matrix addressable memories and addi-tionally circuit areas which form elec-tronic thin-film circuitry for controlling, driving and addressing memory cells in one or more memories. Each memory device has an interface to every other thin-film device in the apparatus, said in-terfaces being realized with communica-tion and signal lines as well as supporting circuitry for processing extending verti-cally through dedicated interface areas in the thin-film device.

FLEXIBLE FERRITE KEEPERS FOR PLATED WIRE MEMORY ARRAYS

SEMICONDUCTOR MEMORY DEVICE HAVING A THREE-DIMENSIONAL STRUCTURE

A three-dimensional memory device includes a stack of semiconductor layers. Phase change memory (PCM) cell arrays are formed on each layer. Each PCM cell includes a variable resistor as storage element, the resistance of which varies. On one layer, formed is peripheral circuitry which includes row and column decoders, sense amplifiers and global column selectors to control operation of the memory. Local bitlines and worldliness are connected to the memory cells. The global column selectors select global bitlines to be connected to local bit lines. The row decoder selects wordlines. Applied current flows through the memory cell connected to the selected local bitline and wordline. In write operation, set current or reset current is applied and the variable resistor of the selected PCM cell stores "data". In read operation, read current is applied and voltage developed across the variable resistor is compared to a reference voltage to provide as read data.

Procédé de fabrication d'un réseau de mémoire à noyaux magnétiques

Magnetschichtspeicher-Anordnung

Magnetischer Informationsspeicher

Dispositif magnétique de mémoire

Informationsspeicher

Magnetschichtspeicher-Anordnung

Magnetische Speichermatrix

Mémoire matricielle à trois dimensions

Assemblage de mémoire à tiges et procédé de fabrication de cet assemblage

Plan de mémoire magnétique à fils et procédé de fabrication dudit plan de mémoire

3d array storage apparatus and operation method thereof

MASS STORAGE DEVICES PACKAGES AND SOFTWARE-DEFINED ARRAYS OF SUCH PACKAGES

Semiconductor device, storage device and electronic device

Three dimensional structure memory

A Three-Dimensional Structure (3DS) Memory (100) allows for physical separation of the memory circuits (103) and the control logic circuit onto different layers (103) such that each layer may be separately optimized. One control logic (101) circuit suffices for several memory circuits (103), reducing cost. Fabrication of 3DS memory ((100) involves thinning of the memory circuit (103) to less than 50 mum in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density interlayer vertical bus connections are used. The 3DS memory (100) manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

MEMORY CORE SUBMODULE

Magnetic storage

Magnetic matrix for the setting in data memory

Memory with self-resetting

METHOD FOR PRODUCING A MATRIX MEMORY DEVICE OF HIGH BIT DENSITY

Magnetic storage for a digital computer

Stamp block with memory out of ferrite

SEMICONDUCTOR MEMORY DEVICE

RECONFIGURABLE CONNECTIONS FOR STACKED SEMICONDUCTOR DEVICES

... 부분 실시예는 스택에 배열된 반도체 다이스, 다이스 사이에 통신을 제공하도록 구성된 복수의 커넥션, 적어도 하나의 다이스를 통과하는 적어도 하나의 부분과, 커넥션의 결함을 체크하고, 커넥션의 결함을 수리하도록 구성된 모듈을 포함하는 장치, 시스템, 방법을 포함한다.

CARD TYPE RECORDING MEDIUM AND PRODUCTION METHOD THEREFOR

SEMICONDUCTOR MEMORY DEVICE

Multi-Port memory device with stacked banks

MEMORY SYSTEM AND OPERATING METHOD THEREOF

MULTI-CHIP PACKAGE MEMORY STACKED MEMORY CHIPS, METHOD FOR STACKING MEMORY AND METHOD FOR CONTROLLING OPERATION OF MULTI-CHIP PACKAGE MEMORY USING THE THROUGH HOLE VIA

PURPOSE: A multi-chip package memory stacked memory chips, method for stacking memory and method for controlling operation of multi-chip package memory are provided to use the through hole via and control the reading or writing operation. CONSTITUTION: The multi-chip package memory(100) comprises the transmission memory chip, and the four through electrodes(110, 120, 130, 140) of the first and the second memory chip(ME 1, ME 2). The transmission memory chip is laminated on the printed circuit board and delivers the authorization signal to the first and the second memory chip. The transmission memory chip delivers read data from the first memory chip or the second memory chip to the outside of the multi-chip package memory. © KIPO 2009 ...

Semiconductor device

A COMPOSITE MEMORY HAVING A BRIDGING DEVICE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM

Three Dimensional Semiconductor Device

SEMICONDUCTOR DEVICE INCLUDING DIFFERENT KINDS OF MEMORIES

PURPOSE: A semiconductor device is provided to increase read and write speed to that of the SDRAM or SDRAM by duplicating flash data to DRAM. CONSTITUTION: A semiconductor device includes a nonvolatile memory(CHIP1) having first read time, a random access memory having second read time shorter 100 times as much as the firs read time, and a control circuit is combined with the nonvolatile memory and random access memory respectively and control access to the nonvolatile memory and the random access memory. The nonvolatile memory is connected is combined with a plurality of input terminals and the access to the nonvolatile memory is realized through the random access memory. © KIPO 2009 ...

THREE DIMENSIONAL SEMICONDUCTOR DEVICE, AN OPERATING METHOD THEREOF, AND A MANUFACTURING METHOD THEREOF, INCLUDING A SELECTION TRANSISTOR COMPRISED OF AT LEAST ONE DEPLETION TRANSISTOR AND AT LEAST ONE ACTIVE TRANSISTOR

PURPOSE: A semiconductor device, an operating method thereof, and a manufacturing method thereof are provided to select one of cell strings using difference between threshold voltages of the depletion and active transistors. CONSTITUTION: A three dimensional semiconductor device includes a first wiring structure(BLP), a second wiring structure(CSP), and a cell string(STR). The cell strings connect the first and second wiring structures in parallel. The cell strings have memory cell transistors and a plurality of first selection transistors. The memory cell transistors are serially connected. The selection transistors connect the first wiring structure with the adjacent memory cell transistors in series. COPYRIGHT KIPO 2010 ...

MEMORY MODULE DEVICE AND MEMORY SYSTEM HAVING THE SAME, ESPECIALLY FOR REDUCING THE NUMBER OF PINS BY MERGING COMMAND/ADDRESS BUS AND WRITE DATA BUS INTO ONE BUS

PURPOSE: A memory module device and a memory system having the same are provided to obtain desired signal integrity in a memory system having an operation clock frequency over several GHz, by reducing existing capacitive load effect due to command/address signals. CONSTITUTION: A memory module(800a) device comprises First to Nth memory devices(810,820,830). A command/address port is connected to at least one memory device among the memory devices, and transmits write data and a command/address signal. First to Nth data ports are connected to the memory devices respectively, and output read data. A Kth memory device connected to the command/address port re-transmits the write data and the command/address signal to at least another memory device. The Kth memory device includes a repeater re-transmitting the command/address signal to at least another memory device. © KIPO 2007 ...

Memory device power managers and methods

IN-MEMORY LIGHTWEIGHT COHERENCY

Mass data storage system with non-volatile memory modules

A mass data storage system, which comprises: a controller for issuing and receiving signals to carry out memory operations; a motherboard comprising at least one first connector and providing signal pathways for establish a ring from the controller via each of the at least one first connector and back to the controller; and at least one non-volatile memory module comprising a second connector electrically connected to a chain of non-volatile memory devices, wherein mating of the second connector with a given one of the at least one first connector causes the chain of non-volatile memory devices to be inserted into the ring, thereby to allow the controller to carry out the memory operations on the non-volatile memory devices in the chain.

Semiconductor memory

SEMICONDUCTOR DEVICE AND MEMORY MODULE

Semiconductor device

Semiconductor memory device

To provide a semiconductor memory device including a large capacity of non-volatile memory by matching the access time of a large capacity of non-volatile memory with the access time of a random access memory. This semiconductor memory device is constituted of a non-volatile memory FLASH having a first reading time, a random access memory DRAM having a second reading time which is not less than 100 times as short as the first reading time, a circuit connected to the FLASH and the DRAM including a control circuit for controlling access to them, and a plurality of input and output terminals connected to the circuit. Therefore, it is possible to realize the matching of the access time by transferring the data of the FLASH to the DRAM, and performing an access to the DRAM. Also, it is possible to realize the matching and preservation of the data by rewriting the data from the DRAM to the FLASH as necessary.

Non-volatile semiconductor storage device

HIGH DENSITY PLANAR MAGNETIC DOMAIN WALL MEMORY APPARATUS AND METHOD OF FORMING THE SAME

A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.

DATA STORAGE AND STACKABLE CONFIGURATIONS

A first memory device and second memory device have a same input/output layout configuration. To form a stack, the second memory device is secured to the first memory device. To facilitate connectivity, the second memory device is rotationally offset with respect to the first memory device in the stack to align outputs of the first memory device with corresponding inputs of the second memory device. The rotational offset of the second memory device with respect to the first memory device aligns one or more outputs of the first memory device with one or more respective inputs of the second memory device. Based on links between outputs and inputs from one memory device to another in the stack, the stack of memory devices can include paths facilitating one or more series connection configurations through he memory devices.

METHOD AND APPARATUS FOR PRODUCING A METASTABLE FLIP FLOP

The method includes predetermining an output enable time period by measuring the maximum settling time when a signal is read during a transition from 0 to 1 or vice versa, and multiplying the maximum settling time by a safety factor 2.5, to set an output enable time period; reading and latching an input value; and transmitting the latched value onward after the predetermined output enable time period. An embodiment of the apparatus 10 includes two inverters 12, 14 and two pass gates 16, 18 and connected to a line 20 at its input. The pass gates 16, 18 are connected in a multiplexer configuration. A third pass gate 30 for connecting line 32, carrying the (inverted) output B of the metalatch, to further circuit portions, according to a 2-bit output enable signal applied to control lines 34, 36 respectively. In alternate embodiments, other logic circuit portions already provided can perform the function of pass gate 30.

CONFIGURABLE BANDWIDTH MEMORY DEVICES AND METHODS

Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed.

MEMORY DIES, STACKED MEMORIES, MEMORY DEVICES AND METHODS

Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node.

MEMORY DEVICES

A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed.

System and memory for sequential multi-plane page memory operations

A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory operations are sequentially initiated and the memory operation for at least one of the memory planes is initiated during the memory operation for another memory plane. In one embodiment, each of a plurality of programming circuits is associated with a respective memory plane and is operable to program data to the respective memory plane in response to programming signals and when it is enabled. Control logic coupled to the plurality of programming circuits generates programming signals in response to the memory receiving program commands and further generates programming enable signals to individually enable each of the programming circuits to respond to the programming signals and stagger programming of data to each of the memory planes.

Memory device power managers and methods

Memory devices and methods are described that include a stack of memory dies and an attached logic die. Method and devices described provide for power management of portions of a stack of memory dies. Additional devices, systems, and methods are disclosed.

MEMORY CARD AND SD CARD

According to one embodiment, there are provided a memory which is provided on a circuit board, a controller which is provided on the circuit board and controls the memory, and a signal line which is formed on the circuit board and configured to perform data transmission between the controller and the memory, in which a width of the signal line in the place where the signal line is led out from the memory is large compared with a place disposed under the memory.

Three dimensional structure integrated circuit

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 mum in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density interlayer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

High capacity memory module with higher density and improved manufacturability

The present invention provides a double-sided memory module with improved memory device density and improved manufacturability, and with optional bus terminations mounted directly on the memory module for use with high speed, impedance-controlled memory buses. It also allows the same memory devices to be used on both sides of the card, instead of requiring memory devices with mirrored I/O connections on a second side as on prior art double-sided memory cards. The memory module may be formed on a conventional printed circuit card using cost-effective printed circuit board line widths and spaces with unpacked or packed memory chips attached directly to the memory module, while maintaining good signal integrity. Using memory modules with bus terminations mounted directly on the module improves the signal quality and integrity even further and therefore enhances system performance. Such designs may also eliminate the need for bus exit connections, thereby allowing the freed-up connection capacity ...

Stacked semiconductor memory device and semiconductor memory module containing the same

There is a trend to increase that area of a device requiring a memory of large capacity, which is occupied by a semiconductor memory. This trend obstructs reduction of the size of the device. The present invention contemplates to provide a memory which can have a high integration, a high density and a large capacity while minimizing the mounting area. In order to achieve this memory, the TAB (Tape Automated Bonding) of the prior art is mounted on an electrically conductive connector, and a plurality of structures composed of the TAB and the connector are stacked. Moreover, the connector mounting the TAB thereon is constructed such that the independent terminals of the stacked TABs may not be shorted.

Integrated circuit device and electronic equipment

An integrated circuit device includes: a first pad to an ith pad connected to a first memory pad to an ith memory pad of a memory stacked in the integrated circuit device; a jth pad to a kth pad connected to a jth memory pad to a kth (1 Подробнее

Radio frequency identification transponder memory

A radio frequency identification (RFID) transponder includes a vertically configured non-volatile memory array. The RFID transponder additionally includes a logic circuitry connected with the vertically configured non-volatile memory array. The logic circuitry is configured to read data from the vertically configured non-volatile memory array. Additionally included is an antenna, which is connected with the logic circuitry. The antenna is configured to collect power from a radio frequency signal and to transmit the data. The non-volatile memory array may include a plurality of two-terminal memory cells that store data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the terminals of the cell. The logic circuitry can be positioned in a logic plane and at least one non-volatile memory array may be positioned on top of the logic plane and the non-volatile memory arrays may be vertically stacked upon one another.

Systems for reverse bias trim operations in non-volatile memory

A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a second level of resistance. Certain memory cells in a set of cells that was reset may be deeply reset to a level of resistance beyond a target level for the reset state. A second reverse bias is applied to the set of memory cells to move the resistance of each cell that was deeply reset toward the target level of the reset state. A smaller reverse bias than used for the reset operation can shift the resistance of the cells back toward the set level and out of their deeply reset condition. The operation is self-limiting in that cells stop their resistance shifts upon reaching the target level. Cells that were not deeply reset are not affected.

Three dimensional magnetic memory and/or recording device

An electronic memory and/or recording device includes a three dimensional magnetic medium. Three dimensional magnetic medium includes a plurality of magnetic sublayers, each of the magnetic sublayers being separated from one other by non-magnetic interlayers.

SEMICONDUCTOR MEMORY MODULE

A semiconductor device includes a plurality of semiconductor memories, a clock signal synchronization circuit, and a first circuit. The clock signal synchronization circuit is electrically coupled to the plurality of semiconductor memories. The first circuit is electrically coupled to the plurality of semiconductor memories. The first circuit changes a bit width of data. The data is transferred between the first circuit and the plurality of semiconductor memories.

Stacked semiconductor module

The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable to identify the integrated circuit dice that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dice and the programmable memory device. The integrated circuit dice of the plurality of integrated circuit dice that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dice.

MEMORY DEVICE HAVING A DIFFERENT SOURCE LINE COUPLED TO EACH OF A PLURALITY OF LAYERS OF MEMORY CELL ARRAYS

In an embodiment, a memory device may have a plurality of layers of memory cell arrays. Each layer may have a plurality of strings of memory cells and a different source line coupled to each layer of the plurality of layers.

Circuit board having bypass pad

An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided.

READ-OUT CIRCUIT AND READ-OUT METHOD FOR THREE-DIMENSIONAL MEMORY

A read-out circuit and a read-out method for a three-dimensional memory, comprises a read reference circuit and a sensitive amplifier, the read reference circuit produces read reference current capable of quickly distinguishing reading low-resistance state unit current and reading high-resistance state unit current. The read reference circuit comprises a reference unit, a bit line matching module, a word line matching module and a transmission gate parasitic parameter matching module. With respect to the parasitic effect and electric leakage of the three-dimensional memory in the plane and vertical directions, the present invention introduces the matching of bit line parasite parameters, leakage current and transmission gate parasitic parameters into the read reference current, and introduces the matching of parasitic parameters of current mirror into the read current, thereby eliminating the phenomenon of pseudo reading and reducing the read-out time.

MULTI-DIE MEMORY DEVICE

A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

MEMORY DEVICE

A memory device includes a memory element, a first wiring and a second wiring. The memory element includes a memory layer retaining information based on a magnetization state of a magnetic material and a magnetization pinned layer in which a magnetization direction is pinned and which is provided for the memory layer through a non-magnetic layer, in which current flows in a stacking direction to change a magnetization direction of the memory layer. The first wiring supplies current flowing in the stacking direction of the memory element, and the second wiring supplies current to apply a current magnetic field to the memory element. When information is recorded in the memory device, a first pulse current is supplied to the first wiring, a second pulse current is supplied to the second wiring, and the second pulse current falls at least 10 picoseconds after the first pulse current falls.

Third dimensional memory with compress engine

An integrated circuit and method for modifying data by compressing the data in third dimensional memory technology is disclosed. In a specific embodiment, an integrated circuit is configured to perform compression of data disposed in third dimensional memory. For example, the integrated circuit can include a third dimensional memory array configured to store an input independent of storing a compressed copy of the input, a processor configured to compress the input to form the compressed copy of the input, and a controller configured to control access between the processor and the third dimensional memory array. The third dimension memory array can include one or more layers of non-volatile re-writeable two-terminal cross-point memory arrays fabricated back-end-of-the-line (BEOL) over a logic layer fabricated front-end-of-the-line (FEOL). The logic layer includes active circuitry for data operations (e.g., read and write operations) and data compression operations on the third dimension ...

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME

A semiconductor device featuring a substrate having a first surface defined by a first edge and an opposing second edge, electrode pads formed on the first surface, a first semiconductor chip mounted over the first surface between the first edge and the electrode pads and including first pads each electrically connected to a corresponding electrode pad, a second semiconductor chip stacked over the first semiconductor chip and including second pads each electrically connected to a corresponding electrode pad, a third semiconductor chip mounted over the first surface of the substrate between the second edge and the electrode pads and including third pads each electrically connected to a corresponding electrode pad, in which one electrode pad is electrically connected to one first pad, one second pad and one third pad and another electrode pad is electrically connected to a first pad and a second pad corresponding thereto, via separate bonding wires.

Semiconductor memory device including plurality of memory chips

A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips.

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device according to an embodiment includes a memory chip and a circuit chip. The memory chip includes first and second joint metals. The circuit chip includes first and second sense amplifiers, and third and fourth joint metals facing the first and second joint metals, respectively. The first sense amplifier includes first and second active regions. The first active region includes a first transistor coupled between the third joint metal and the second active region. The second amplifier includes third and fourth active region. The third active region includes a second transistor coupled between the fourth joint metal and the fourth active region. The third and fourth joint metals overlap the first and third active regions, respectively.

Semiconductor storage device with two control lines

Provided is a semiconductor storage device with which it is possible to write information to individual memory cells in which a storage node is configured with an oxide semiconductor insulated-gate FET source and a terminal of a capacitor element being connected. A storage node is configured by connecting a source of a first transistor to one terminal of a capacitor element. A drain of the first transistor and a source of a second transistor are connected to each other. A drain of the second transistor is a data input terminal. A first control terminal, which is formed by a gate of the first transistor being connected to another terminal of the capacitor element, is connected to a wordline, which extends in the row direction. A second control terminal, which is formed of a gate of the second transistor terminal, is connected to a write control line, which extends in the column direction. The storage node is connected to a gate of a third transistor, and a current flowing between a drain ...

Multi-chip package

A multi-chip package includes a first semiconductor memory controlled by a clock signal and an inverted clock signal, and a second semiconductor memory controlled by the clock signal. The first semiconductor memory and the second semiconductor memory each include a circuit for guaranteeing that a signal delay is suppressed between a peripheral circuit, and a pad to which the clock signal is input, a pad to which the inverted clock signal is input, a pad for outputting a data enable signal and a pad for outputting a data signal. Thus, it is guaranteed that the signal delay is suppressed, and the reliability of the multi-chip package is improved.

Multi-tier memory architecture

Various implementations described herein are related to a device having voltage regulation architecture with multiple layers arranged in a multi-layer structure. The device may include one or more layers of the multiple layers with voltage regulation circuitry that may be configured to manage at least one of process variation and temperature variation between the multiple layers of the multi-layer structure.

Semiconductor memory apparatus having sense amplifier

Disclosed is a semiconductor memory apparatus comprising an upper mat and a lower mat with a sense amplifier array region in between, where the sense amplifier array region includes a plurality of sense amplifiers. There is also a plurality of bit lines configured to extend toward the sense amplifier array region from the upper mat, and a plurality of complementary bit lines configured to extend toward the sense amplifier array region from the lower mat. Bit lines of the upper mat and complementary bit lines of the lower mat are configured to be alternately disposed at a predetermined interval in the sense amplifier array region, and the sense amplifier is configured to be formed between a bit line and a corresponding complementary bit line.

Semiconductor memory device having stacked structure including resistor-switched based logic circuit and method of manufacturing the same

Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.

Semiconductor device and method of manufacturing the same

According to one embodiment, a semiconductor device includes a stacked chip includes semiconductor chips which are stacked, the semiconductor chips comprises semiconductor substrates and through electrodes formed in the semiconductor substrates, respectively, the through electrodes being electrically connected, and deactivating circuits provided in the semiconductor chips, respectively, and configured to deactivate a failed semiconductor chip.

Semiconductor package

A semiconductor package includes a memory controller chip, a plurality of first memory chips configured to store normal data, a second memory chip configured to store error information for correcting or detecting error of the normal data, and an interface unit configured to interface the memory controller chip, the plurality of first memory chips, and the second memory chip.

Semiconductor device

A semiconductor device includes: an interface chip including a read timing control circuit that outputs, in response to a command signal and a clock signal supplied from the outside, a plurality of read control signals that are each in synchronization with the clock signal and have different timings; and core chips including a plurality of internal circuits that are stacked on the interface chip and each perform an operation indicated by the command signal in synchronization with the read control signals. According to the present invention, it is unnecessary to control latency in the core chips and therefore to supply the clock signal to the core chips.

Memory Modules and Devices Supporting Configurable Core Organizations

Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey width selection information to configurable memory apparatus and support point-to-point data interfaces for multiple width configurations.

Continuous mesh three dimensional non-volatile storage with vertical select devices

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Three dimensional non-volatile storage with multi block row selection

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Dram device with built-in self-test circuitry

A dynamic random access memory (DRAM) device includes a first and second integrated circuit (IC) die. The first integrated circuit die has test circuitry to generate redundancy information. The second integrated circuit die is coupled to the first integrated circuit die in a packaged configuration including primary storage cells and redundant storage cells. The second integrated circuit die further includes redundancy circuitry responsive to the redundancy information to substitute one or more of the primary storage cells with one or more redundant storage cells.

Semiconductor device including plural chips stacked to each other

Such a device is disclosed that includes a first semiconductor chip including a plurality of first terminals, a plurality of second terminals, and a first circuit coupled between the first and second terminals and configured to control combinations of the first terminals to be electrically connected to the second terminals, and a second semiconductor chip including a plurality of third terminals coupled respectively to the second terminals, an internal circuit, and a second circuit coupled between the third terminals and the internal circuit and configured to activate the internal circuit when a combination of signals appearing at the third terminals indicates a chip selection.

Memory System with Multi-Level Status Signaling and Method for Operating the Same

A memory system includes a status circuit having a common status node electrically connected to a respective status pad of each of a plurality of memory chips. The memory system also includes a plurality of resistors disposed within the status circuit to define a voltage divider network for generating different voltage levels at the common status node. Each of the different voltage levels indicates a particular operational state combination of the plurality of memory chips. Also, each of the plurality of memory chips is either in a first operational state or a second operational state. Additionally, the different voltage levels are distributed within a voltage range extending from a power supply voltage level to a reference ground voltage level.

Semiconductor device including plural chips stacked to each other

Such a device is disclosed that includes first and second chips stacked to each other, and a third chip controlling the first and second chips, stacked on the first and second chips, and including first, second and third output circuits. The first output circuit supplies a first command signal to the first chip. The second output circuit supplies the first command signal to the second chip. The third output circuit supplies a second command signal to the first and second chips.

Memory module and video camera

According to the embodiments, there are provided semiconductor memories that are mounted individually on two sides of a mounting board; a controller that is mounted either on an obverse side or a reverse side of the mounting board, and performs read and write control of the semiconductor memories; and a connector that is deviated in a lateral direction from the controller so as not to overlap the controller, is mounted either on the obverse side or the reverse side of the mounting board, and transfers a signal exchanged between the controller and outside.

Flash Memory Device With an Array of Gate Columns Penetrating Through a Cell Stack

A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge.

Magnetic memory device

The present invention provides a magnetic memory device capable of providing high-speed access without increasing an array area. Gate word lines are respectively linearly disposed between source impurity regions and drain impurity regions within a memory cell array area. Gate word line protrusions are respectively provided at boundary regions of memory cell forming regions. Contacts relative to the gate word line protrusions are respectively provided at boundary regions of memory cells at adjacent columns. The drain impurity regions are respectively disposed with being shifted from the centers of the memory cell forming regions in such a manner that spaces between the drain impurity regions become large in the regions in which the protrusions are disposed.

Embedded processor

Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

Three dimensional memory system with intelligent select circuit

A three dimensional monolithic memory array of non-volatile storage elements includes a plurality of word lines and a plurality of bit lines. The plurality of bit lines are grouped into columns. Performing memory operation on the non-volatile storage elements includes selectively connecting bit lines to sense amplifiers using selection circuits that include a storage device, a select circuit connected to the storage device and one or more level shifters providing two or more interfaces to the respective selection circuit.

Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit

A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to perform a power management operation in association with only a portion of the memory circuits.

Sense operation in a stacked memory array device

Methods for sensing and memory devices are disclosed. One such method for sensing includes changing a sense condition of a particular layer responsive to a programming rate of that particular layer (e.g., relative to other layers).

Integrated circuit self aligned 3d memory array and manufacturing method

A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. The 3D memory is made using only two critical masks for multiple layers.

Program cycle skip

A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.

Circuit providing load isolation and noise reduction

Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.

Energy Efficient Power Distribution for 3D INTEGRATED CIRCUIT Stack

Multiple dies can be stacked in what are commonly referred to as three-dimensional modules (or “stacks”) with interconnections between the dies, resulting in an IC module with increased circuit component capacity. Such structures can result in lower parasitics for charge transport to different components throughout the various different layers. In some embodiments, the present invention provides efficient power distribution approaches for supplying power to components in the different layers. For example, voltage levels for global supply rails may be increased to reduce required current densities for a given power objective.

Arrays Of Nonvolatile Memory Cells And Methods Of Forming Arrays Of Nonvolatile Memory Cells

An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first plurality of horizontally oriented first electrode lines and a second plurality of horizontally oriented second electrode lines crossing relative to the first electrode lines. Individual of the memory cells include a crossing one of the first electrode lines and one of the second electrode lines and material there-between. Specifically, programmable material, a select device in series with the programmable material, and current conductive material in series between and with the programmable material and the select device are provided in series with such crossing ones of the first and second electrode lines. The material and devices may be oriented for predominant current flow in defined horizontal and vertical directions. Method and other implementations and aspects are disclosed.

Memory module and layout method therefor

The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.

Integrated circuit memory device

A semiconductor memory device includes a plurality of memory regions formed on one chip, each of the memory regions having a plurality of volatile memory cells that are formed with a density or capacity of 2̂K bits, where K is an integer greater than or equal to 0, and a plurality of input/output (I/O) terminals for inputting and outputting data of the volatile memory cells, and at least one peripheral region that controls a write operation for writing data into the memory regions and a read operation for reading data from the memory regions based on a command and an address input from outside. Thus, a total or entire density of the memory regions corresponds to a non-standard (or ‘interim’) density so that the semiconductor memory device may have an interim density.

Semiconductor memory with sense amplifier

In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row.

Semiconductor memory device

A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

Semiconductor device, adjustment method thereof and data processing system

A method includes preparing a chip-stack structure in which a first memory chip is stacked over a first main surface of a second memory chip, data electrodes of the first and second memory chips being electrically connected and a data signal outputted from the data electrode of the first memory chip being conveyed on a side of the second main surface of the second memory chip, accessing the first memory chip so that the data signal is outputted from the first memory chip and appears on the side of the second main surface of the second memory chip in first access time, accessing the second memory chip so that a data signal is outputted and appears on the side of the second main surface of the second memory chip in second access time, and setting output timing adjustment information into at least one of the first and second memory chips.

Nonvolatile semiconductor memory device and method of manufacturing the same

According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure in which a first insulating layer, a first semiconductor layer, . . . an n-th insulating layer, an n-th semiconductor layer, and an (n+1)-th insulating layer (n is a natural number equal to or more than 2) are stacked in order thereof in a first direction perpendicular to a surface of a semiconductor substrate and which extends in a second direction parallel to the surface of the semiconductor substrate, first to n-th memory strings which use the first to n-th semiconductor layers as channels respectively, a common semiconductor layer which combines the first to n-th semiconductor layers at first ends of the first to n-th memory strings in the second direction.

Apparatuses and methods including memory array and data line architecture

Some embodiments include apparatus and methods having memory cells located in different device levels of a device, at least a portion of a transistor located in a substrate of the device, and a data line coupled to the transistor and the memory cells. The data line can be located between the transistor and the memory cells. Other embodiments including additional apparatus and methods are described.

Semiconductor device and semiconductor chip

The present invention is applicable to a semiconductor device having a plurality of chips being stacked with a TSV structure in which adjacent ones of the chips are connected to each other via a plurality of through electrodes. Each of the chips includes a plurality of TSV array portions provided so as to correspond to a plurality of channels. The TSV array portions include a TSV array portion that contributes to an input and an output depending upon the number of the chips being stacked, and a pass-through TSV array portion that is not connected to an input/output circuit.

Discrete Three-Dimensional Memory

The present invention discloses a discrete three-dimensional memory (3D-M). It is partitioned into at least two discrete dice: a memory-array die and a peripheral-circuit die. The memory-array die comprises at least a 3D-M array, which is built in a 3-D space. The peripheral-circuit die comprises at least a peripheral-circuit component, which is built on a 2-D plane. At least one peripheral-circuit component of the 3D-M is formed in the peripheral-circuit die instead of in the memory-array die. The array efficiency of the memory-array die can be larger than 70%.

Novel semiconductor device and structure

A semiconductor device, including: a first semiconductor layer including first transistors, wherein the first transistors are interconnected by at least one metal layer including aluminum or copper; and a second mono-crystallized semiconductor layer including second transistors and overlaying the at least one metal layer, wherein the at least one metal layer is in-between the first semiconductor layer and the second mono-crystallized semiconductor layer, wherein the second mono-crystallized semiconductor layer is less than 100 nm in thickness, and wherein the second transistors include horizontally oriented transistors.

Die package, method of manufacturing the same, and systems including the same

A die package includes a substrate, a die mounted on the substrate, and a ZQ resistor disposed in the die package and connected to the substrate and the die. The ZQ resistor may be used to calibrate impedance of the die.

Semiconductor device having plural selection lines selected based on address signal

Disclosed herein is a device that includes: a set of address terminals supplied with a set of address signals, each of the address signals being changed in logic level; memory mats to which address ranges are allocated, respectively, the address ranges being different from each other, each of the memory mats including memory cells; and decoder units each provided correspondingly to corresponding memory mat. Each of the decoder units includes a set of first input nodes and a set of second input nodes, the set of first input nodes of each of the decoder units being coupled to the set of address terminals to receive the set of address signals, the set of second input nodes of each of the decoder units being coupled to receive an associated one of sets of control signals, each of the control signals being fixed in logic level.

SEMICONDUCTOR DEVICE

According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate. 1. A semiconductor device comprising:a substrate comprising a multi-layer structure with a wiring pattern, and comprising a substantially rectangular shape in a plan view;a connector to be connectable to a host device;a volatile semiconductor memory element provided on a front surface layer side of the substrate;a first nonvolatile semiconductor memory element provided on the front surface layer side of the substrate;a second nonvolatile semiconductor memory element provided on the front surface layer side of the substrate;a third nonvolatile semiconductor memory element provided on the front surface layer side of the substrate; anda controller provided on the front surface layer side of the substrate to control the volatile semiconductor memory element and the nonvolatile semiconductor memory elements,wherein the wiring pattern includes a signal line formed between the connector and the controller to connect the connector to the controller, andwherein the first nonvolatile semiconductor memory element and the second nonvolatile semiconductor memory element are aligned along the longitudinal direction of the substrate, on the opposite side of the controller to the third nonvolatile semiconductor memory element.2. A semiconductor device comprising:a substrate comprising a multi-layer structure with a wiring pattern, and comprising a substantially rectangular shape in a plan view;a connector provided on a short side of the substrate to be connectable to a ...

SEMICONDUCTOR DEVICE

According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate. 1. A semiconductor system comprising:a host device including a CPU; anda semiconductor device; wherein the semiconductor device comprises:a substrate comprising a multi-layer structure with a wiring pattern, and comprising a substantially rectangular shape in a plan view;a connector to be connectable to the host device;a volatile semiconductor memory element provided on a front surface layer side of the substrate;a first nonvolatile semiconductor memory element provided on the front surface layer side of the substrate;a second nonvolatile semiconductor memory element provided on the front surface layer side of the substrate;a third nonvolatile semiconductor memory element provided on the front surface layer side of the substrate; anda controller provided on the front surface layer side of the substrate to control the volatile semiconductor memory element and the nonvolatile semiconductor memory elements,wherein the wiring pattern includes a signal line formed between the connector and the controller to connect the connector to the controller, andwherein the first nonvolatile semiconductor memory element and the second nonvolatile semiconductor memory element are aligned along the longitudinal direction of the substrate, on the opposite side of the controller to the third nonvolatile semiconductor memory element,wherein the CPU writes information on the first nonvolatile semiconductor memory element and the second nonvolatile semiconductor memory element ...

Method and apparatus for refresh management of memory modules

One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices

Semiconductor storage device

According to one embodiment, a semiconductor storage device includes a stripe, a sense amplifier, a global signal line, and a controller. Blocks are in the stripe. The blocks are formed in a first direction. Each of blocks is made a read unit of data and includes a memory cell capable of holding the data provided along a row and a column. The sense amplifier is provided just under each of the blocks, and reads the data. The global signal line is formed so as to penetrate through the stripe in the first direction, and transfers the data read from the block to the sense amplifier. The controller controls a value of a reference current applied to the sense amplifier according to positional relationship between each area in which the sense amplifier is arranged and the block, which is made a read target of the data, out of the blocks.

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device in accordance with an embodiment includes a plurality of first word lines, a plurality of bit lines, a resistance varying material, a plurality of second word lines and an insulating film. The bit lines intersect the first word lines. The resistance varying material is disposed at respective intersections of the first word lines and the bit lines. The second word lines intersect the bit lines. The insulating film is disposed at respective intersections of the second word lines and the bit lines. One of the first word lines and one of the second word lines are disposed so as to sandwich the bit lines. The second word lines, the bit lines, and the insulating film configure a field-effect transistor at respective intersections of the second word lines and the bit lines. The field-effect transistor and the resistance varying material configure one memory cell. 17-. (canceled)8. A semiconductor memory device , comprising:a semiconductor substrate;a plurality of first word lines extending in a stacking direction perpendicular to the semiconductor substrate, the first word lines being arranged having a certain pitch in a first direction parallel to a surface of the semiconductor substrate and being arranged having a certain pitch in a second direction parallel to the surface of the semiconductor substrate and orthogonal to the first direction;a plurality of bit lines extending in the first direction and arranged having a certain pitch in the second direction and the stacking direction, the bit lines being configured to intersect the first word lines such that a first surface of the bit lines faces the first word lines;a resistance varying material disposed at respective intersections of the first word lines and the bit lines;a plurality of second word lines extending in the stacking direction and arranged having a certain pitch in the first direction and the second direction, the second word lines being configured to intersect the bit lines so ...

SEMICONDUCTOR STORAGE DEVICE

A semiconductor storage device includes: a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a rectifier element and a variable resistance element connected in series; and a control circuit selectively driving the first and second wirings. The plurality of first wirings that are specified and selectively driven at the same time by one of a plurality of address signals are separately arranged with other first wirings interposed therebetween within the memory cell array when a certain potential difference is applied to a selected memory cell positioned at an intersection between the first and second wirings by the control circuit. 1. A semiconductor storage device comprising:a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a variable resistance element; anda control circuit selectively driving the first and second wirings,in applying, by the control circuit, a certain potential difference to a selected memory cell positioned at an intersection between the first and second wirings,the plurality of first wirings specified and selectively driven at the same time by one of a plurality of address signals being separately arranged with other first wirings interposed therebetween within the memory cell array,the first wirings being arranged such that a first set of the plurality of first wirings specified and selectively driven at the same time by a first address signal are positioned apart from a second set of the plurality of first wirings specified and selectively driven at the same time by the first address signal, with other first wirings interposed between the first and second set in the memory cell array, anda plurality of sets of the first wirings being repeatedly arranged in the memory cell array, each of ...

MEMORY DEVICES HAVING BREAK CELLS

A representative memory device includes a cell array, at least one break cell that subdivides the cell array into bit cell arrays, and one or more power switches that are electrically coupled to the bit cell. In one embodiment, the break cell separates a connectivity of a first voltage and a second voltage between at least two bit cell arrays so that the bit cell arrays can be selectively coupled to either the first voltage or the second voltage using the power switches. The power switches control the connection of each separated bit cell array of the cell array to either the first voltage or second voltage. 1. A semiconductor memory , comprising:a first break cell electrically separating a first subset of bit cells from a second subset of bit cells of a cell array; anda first power switch configured to connect the first subset of bit cells to a first voltage during a first operating mode and to a second voltage that is different from the first voltage during a second operating mode.2. The semiconductor memory of claim 1 , wherein the first operational mode is a data retention mode claim 1 , and the second operational mode is a write mode.3. The semiconductor memory of claim 1 , further comprising a section decoder that is coupled to the first power switch claim 1 , wherein the section decoder instructs the first power switch to connect the first subset of bit cells to either the first voltage or to the second voltage.4. The semiconductor memory of claim 1 , further comprising a second power switch configured to connect the second subset of bit cells to the first voltage during the first operating mode and to the second voltage that is different from the second voltage during the second operating mode claim 1 , wherein the second power switch is configured to operate independently of the first power switch.5. The semiconductor memory of claim 4 , further comprising a section decoder that is coupled to the first and second power switches claim 4 , wherein the section ...

Method for implementing spare logic of semiconductor memory apparatus and structure thereof

A method for implementing a spare logic of a semiconductor memory apparatus includes the steps of: forming one or more contact conductive layers, which are independent, in a power line and an active area, respectively; and performing metal programming on the contact conductive layers formed in the power line and the active area to electrically couple the independent contact conductive layers formed in the power line and the active area.

Boundary scan chain for stacked memory

A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.

Layout to minimize fet variation in small dimension photolithography

A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.

STACKED MEMORY WITH REDUNDANCY

A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and stacked with a second integrated circuit memory chip. A redundant memory is shared by the first and second integrated circuit memory chips and has redundant storage locations that selectively replace corresponding storage locations in the first or second integrated circuit memory chips. The stacked memory also includes a pin interface for coupling to an external integrated circuit memory controller and respective first and second signal paths. The first signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface. The second signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface via the first signal path. 1. A stacked memory comprising:a first integrated circuit memory chip having first storage locations;a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip, the second integrated circuit memory chip having second storage locations;a redundant memory shared by the first and second integrated circuit memory chips, the redundant memory having redundant storage locations that selectively replace corresponding storage locations in the first or second integrated circuit memory chips;a pin interface for coupling to an external memory controller;a first signal path formed through the first and second integrated circuit memory chips and coupled to the redundant memory, the first signal path coupled to the pin interface; anda second signal path formed through the first and second integrated circuit memory chips and coupled to the redundant memory, the second signal path coupled to the pin interface via the first signal path.2. The stacked memory according to wherein the redundant memory comprises a redundant integrated ...

Discrete Three-Dimensional Memory Comprising Off-Die Address/Data Translator

The present invention discloses a discrete three-dimensional memory (3D-M). Its 3D-M arrays are located on at least one 3D-array die, while its address-data translator (A/D-translator) is located on a separate peripheral-circuit die. The A/D-translator converts at least an address and/or data between logical space and physical space for the 3D-array die. A single A/D-translator die can support multiple 3D-array dies. 1. A discrete three-dimensional memory (3D-M) , comprising:a first 3D-array die comprising at least a first 3D-M array including a plurality of vertically stacked memory levels;a first peripheral-circuit die comprising an address/data translator for converting at least an address and/or data between logical space and physical space for said first 3D-array die;a second peripheral-circuit die comprising a read/write-voltage generator for providing said first 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply;wherein said first 3D-array die, said first peripheral-circuit die and said second peripheral-circuit die are separate dies.2. The memory according to claim 1 , further comprising a second 3D-array die comprising at least a second 3D-M array including a plurality of vertically stacked memory levels claim 1 , wherein:said address/data translator converts at least an address and/or data between logical space and physical space for said second 3D-array die;said read/write-voltage generator provides said second 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply;said first 3D-array die, said second 3D-array die, said first peripheral-circuit die and said second peripheral-circuit die are separate dies.3. The memory according to claim 1 , wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).4. The memory according to claim 1 , wherein said 3D-M comprises a three-dimensional mask-programmed read- ...

Discrete Three-Dimensional Memory Comprising Off-Die Read/Write-Voltage Generator

The present invention discloses a discrete three-dimensional memory (3D-M). Its 3D-M arrays are located on at least one 3D-array die, while its read/write-voltage generator (V R /V W -generator) is located on a separate peripheral-circuit die. The V R /V W -generator generates at least a read and/or write voltage to the 3D-array die. A single V R /V W -generator die can support multiple 3D-array dies.

High current capable access device for three-dimensional solid-state memory

The present invention generally relates to three-dimensional arrangement of memory cells and methods of addressing those cells. The memory cells can be arranged in a 3D orientation such that macro cells that are in the middle of the 3D arrangement can be addressed without the need for overhead wiring or by utilizing a minimal amount of overhead wiring. An individual macro cell within a memory cell can be addressed by applying three separate currents to the macro cell. A first current is applied to the memory cell directly. A second current is applied to the source electrode of the MESFET, and a third current is applied to the gate electrode of the MESFET to permit the current to travel through the channel of the MESFET to the drain electrode which is coupled to the memory element.

Three-Dimensional Memory Comprising an Integrated Intermediate-Circuit Die

The present invention discloses a discrete three-dimensional memory (3D-M). It comprises at least a 3D-array die and at least an integrated intermediate-circuit die comprising both a read/write-voltage generator (V/V-generator) and an address/data translator (A/D-translator). The intermediate-circuit die performs voltage, address and/or data conversion between the 3D-M core region and the host. Discrete 3D-M support multiple 3D-array dies. 1. A discrete three-dimensional memory (3D-M) , comprising:a 3D-array die comprising at least a 3D-M array including a plurality of vertically stacked memory levels;an intermediate-circuit die comprising a read/write-voltage generator and an address/data translator, wherein said read/write-voltage generator provides said 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply, and said address/data translator converts at least an address and/or data of a host to an address/data of said 3D-array die and vice versa;wherein said 3D-array die and said intermediate-circuit die are separate dies.2. The memory according to claim 1 , further comprising another 3D-array die comprising at least a 3D-M array including a plurality of vertically stacked memory levels claim 1 , wherein:said read/write-voltage generator provides said another 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply;said address/data translator converts at least an address and/or data of a host to an address/data of said second 3D-array die and vice versa;both of said 3D-array dies and said intermediate-circuit die are separate dies.3. The memory according to claim 1 , wherein said read/write-voltage generator comprises a DC-to-DC converter.4. The memory according to claim 1 , wherein said address/data translator is an address translator comprising at least one of an address mapping table claim 1 , a faulty block table and a wear management table.5. The memory according to claim 1 , ...

Integrated circuit

An integrated circuit includes a first chip having a plurality of through-chip vias, and a second chip stacked on the first chip and having a plurality of through-chip vias which are disposed at positions corresponding to the plurality of through-chip vias of the first chip and each of which is connected with at least one through-chip via of the first chip arranged in an oblique direction, which is not on a straight line extending in a chip stacking direction, among the plurality of through-chip vias of the first chip, wherein the first chip inputs/outputs a signal through a through-chip via which is selected by first repair information among the plurality of through-chip vias of the first chip, and the second chip inputs/outputs a signal through a through-chip via which is selected by second repair information among the plurality of through-chip vias of the second chip.

LOAD REDUCED MEMORY MODULE AND MEMORY SYSTEM INCLUDING THE SAME

A device includes a printed circuit board, a clock connector provided on the printed circuit board and configured to be supplied with a first clock signal, a first register buffer provided on the printed circuit board, coupled to the clock connector and, including a first clock generator that produces a second clock signal in response to the first clock signal, a plurality of data connectors, provided on the printed circuit board, a plurality of memory chips each provided on the printed circuit board and including a first data terminal, and a plurality of second register buffers each provided on the printed circuit board independently of the first register buffer. 1. A device comprising:a printed circuit board;a clock connector provided on the printed circuit board and configured to be supplied with a first clock signal;a first register buffer provided on the printed circuit board, coupled to the clock connector and including a first clock generator that produces a second clock signal in response to the first clock signal;a plurality of data connectors provided on the printed circuit board;a plurality of memory chips each provided on the printed circuit board and including a first data terminal; anda plurality of second register buffers each provided on the printed circuit board independently of the first register buffer; a clock terminal configured to receive the second crock signal;', 'a second date terminal coupled to the first data terminal of an associated one of the memory chips;', 'a third data terminal coupled to an associated one of the data connectors;', 'a second clock generator configured to produce a third clock signal in response to the second clock signal; and', 'a data transfer circuit coupled between the second and third data terminals and configured to perform a data transfer therebetween in response to the third clock signal., 'wherein each of the second register buffers comprises2. The device as claimed in claim 1 , wherein the first clock ...

Memories with Cylindrical Read/Write Stacks

A three-dimensional memory is formed as an array of memory elements across multiple layers positioned at different distances above a semiconductor substrate. Cylindrical stacks of memory elements are formed where a cylindrical opening has read/write material deposited along its wall, and a cylindrical vertical bit line formed along its central axis. Memory elements formed on either side of such a cylinder may include sheet electrodes that extend into the read/write material. 1. A three-dimensional array of read/write elements comprising:a plurality of horizontal line stacks, each horizontal line stack comprising a plurality of electrically-conductive horizontal lines that extend in a first direction and are separated from each other by insulating material, individual stacks separated from adjacent stacks in a second direction that is perpendicular to the first direction;a plurality of cylinders of read/write material located between a first horizontal line stack and a second horizontal line stack so that each cylinder of the plurality of cylinders is in electrical contact with horizontal lines of the first and second horizontal line stacks; anda plurality of vertical lines, each vertical line extending through a corresponding cylinder of read/write material to form read/write elements between the vertical line and horizontal lines of the first and second horizontal line stacks.2. The three-dimensional array of wherein the electrically-conductive horizontal lines of the first and second horizontal line stacks include sheet electrodes that extend towards the vertical lines claim 1 , a sheet electrode having a vertical thickness that is less than the total vertical thickness of a horizontal line.3. The three-dimensional array of wherein the sheet electrode extends into a cylinder of read/write material.4. The three-dimensional array of claim three wherein the sheet electrode is formed of Titanium Nitride (TiN).5. The three-dimensional array of wherein the electrically- ...

MEMORY DIES, STACKED MEMORIES, MEMORY DEVICES AND METHODS

Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node. 1. A memory die configured to be arranged in a stack of memory dies , wherein the stack comprises an external select connection node , the memory die comprising:a plurality of detection circuits, each detection circuit being configured to determine if it is coupled to the external select connection node; anda decoder configured to receive detection signals from at least a portion of the plurality of detection circuits and to output an identification of the memory die responsive to which, if any, of the detection circuits is coupled to the external select connection node using the received ones of the detection signals.2. The memory die of claim 1 , further comprising an input buffer configured to receive a signal from the external select connection node.3. The memory die of claim 2 , further comprising a delay circuit claim 2 , wherein the delay circuit is configured to delay a signal received from the external select connection node responsive to the identification.4. The memory die of claim 1 , wherein the memory die is configured to be coupled to another memory die in the stack via four select related connection nodes claim 1 , wherein the plurality of detection circuits comprise at least three detection circuits claim 1 , wherein each of the at least three detection circuits is configured to be coupled to a respective one of the select related connection nodes when the die is arranged in the stack.5. A method comprising:determining an identification ...

Semiconductor integrated circuit

A semiconductor integrated circuit includes a plurality of stacked slices each configured to have a plurality of vias formed therein so that signals are transferred between the slices arranged in a vertical direction, wherein each of the plurality of slices is configured to transfer a pulse signal, generated during a test section, to a lowest slice of the plurality of slices through the vias connected thereto.

MAGNETIC RANDOM ACCESS MEMORY (MRAM)LAYOUT WITH UNIFORM PATTERN

A large scale memory array includes a. uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects. 1. A memory array , comprising:a pattern of adjacent uniformly sized bit cells; andsignal distribution circuitry occupying an area having a size coinciding with an integer multiple of a size of the uniformly sized bit cells.2. The memory array of claim I. in which the adjacent uniformly sized bit cells comprise a plurality of active bit cells outside of a footprint of the signal distribution circuitry area.3. The memory array of claim 2 , comprising:a resistive memory element configured in each of the active bit cells.4. The memory array of claim 2 , comprising:a magnetic tunnel junction configured in each of the active bit cells.5. The memory array of claim 2 , in which the adjacent uniformly sized bit cells comprise a plurality of dummy bit cells within the footprint of the signal distribution circuitry area.6. The memory array of claim 2 , in which the signal distribution circuitry is coupled to the active bit cells.7. The memory array of claim 1 , in which the signal distribution circuitry comprises:word line strapping extending in a first dimension of the pattern.8. The memory array of claim 1 , in which the signal distribution circuitry comprises:at least one substrate tie extending in a second dimension of the pattern.9. The memory array of claim 1 , further comprising a plurality of edge dummy cells extending ...

Small-Grain Three-Dimensional Memory

The present invention discloses a small-grain three-dimensional memory (3D-MSG). Each of its memory cells comprises a thin-film diode with critical dimension no larger than 40 nm. The thin-film diode comprises at least a small-grain material, whose grain size G is substantially smaller than the diode size D. The small-grain material is preferably a nano-crystalline material or an amorphous material. The critical dimension f of the small-grain diode is smaller than the critical dimension F of the single-crystalline transistor.

SEMICONDUCTOR DEVICE HAVING MULTIPORT MEMORY

A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA, WLB, WLB, WLA, WLA. Further, a pitch d between WLA-WLA and between WLB-WLB is made smaller than a pitch d between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d on the other. 1a plurality of word line groups respectively including a first word line for a first port and a second word line for a second port and the first word line and the second word line being disposed in juxtaposition with one another;a plurality of bit line groups respectively extending in a direction orthogonal to an extension direction of the word line groups and including a first bit line for the first port and a second bit line for the second port and the first word line and the second word line being disposed in juxtaposition with one another; anda plurality of memory cells disposed at respective intersections between the word line groups and the bit line groups,wherein the first word line and the second word line included in one of the word line groups are disposed at a first pitch;wherein the first word line included in one of the word line groups is disposed adjacent to the first word line included in a word line group disposed on one neighboring side of the one word line group concerned at a second pitch;wherein the second word line included in one of the word line groups is disposed adjacent to the second word line included in a word line group disposed on the other neighboring side of the one word line group concerned at the second pitch; andwherein a first shield line extending in juxtaposition with the first word line and the ...

SEMICONDUCTOR DEVICE HAVING MEMORY CELL ARRAY DIVIDED INTO PLURAL MEMORY MATS

A semiconductor device includes a plurality of memory mats arranged in an X direction and a mat selecting circuit that activates a part of the memory mats based on a row address and maintains the rest of the memory mats inactivated. The memory mats are divided into a plurality of memory mat groups each including the same number of memory mats arranged in the X direction. The mat selecting circuit activates at least one of the memory mats included in each of the memory mat groups, while maintaining the rest of memory mats inactivated. With this operation, a portion of discontinuity does not occur in the memory mats arranged in the X direction, and thus the necessity of arranging two sub-word driver areas in the portion of discontinuity is eliminated. 1. A semiconductor device comprising:first, second, third, fourth, fifth, sixth, seventh and eighth memory mats that are arranged in line in that order, each of the first to eighth memory mats including a plurality of memory cells; anda selection circuit that is configured to respond to a first bit of a row address including a plurality of bits and to activate the first, second, fifth and sixth memory mats in parallel to one another with deactivating the third, fourth, seventh and eighth memory mats when the first bit of the row address is one of logic-1 and logic-0 and to activate the third, fourth, seventh and eighth memory mats in parallel to one another with deactivating the first, second, fifth and sixth memory mats when the first bit of the row address is the other of logic-1 and logic-0.2. The device as claimed in claim 1 ,wherein each of the first to eighth memory mats further includes a plurality of word lines; andwherein the device further comprises first, second, third and fourth word drivers, the first word driver being between the first and second memory mats to be connected to the word lines of each of the first and second memory mats, the second word driver being between the third and fourth memory mats to ...

Apparatus for High Speed ROM Cells

A ROM cell comprises a first first-level contact formed on a first active region of a transistor of a memory cell, a second first-level contact formed on a second active region of the transistor of the memory cell, wherein the second first-level contact is coupled to a first VSS line and a second VSS line formed in a first interconnect layer, wherein the second VSS line is electrically coupled to the first VSS line, and wherein the second VSS line is of a direction orthogonal to a direction of the first VSS line. The ROM cell further comprises a first bit line formed in the first interconnect layer, wherein the first bit line is formed in parallel with the second VSS line and a second bit line formed in the first interconnect layer, wherein the second bit line is formed in parallel with the second VSS line.

Memory Modules and Devices Supporting Configurable Data Widths

Described are memory apparatus organized in physical banks and including configurable data control circuit to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey configuration value to configurable memory apparatus and support point-to-point data buffers for multiple width configurations. 1. (canceled)2. An integrated-circuit memory device comprising:an input to receive memory-width configuration value;data terminals to exchange data with another device;a plurality of physical banks, each physical bank including columns of memory cells coupled to corresponding sense amplifiers; anda data control circuit coupling the physical banks with the data terminals, the data control circuit supporting first and second width configurations responsive to the configuration value; in the first width configuration, the data control circuit conveys data of a first data width between a first integer number of the physical banks per read operation and the data terminals, and the plurality of physical banks collectively provide a first memory depth, and', 'in the second width configuration, the data control circuit conveys data of a second data width between a second integer number of the physical banks per read operation and the data terminals, the second data width wider than the first data width, the second integer number larger than the first integer number, and the plurality of physical banks collectively provide a second memory depth; and', 'wherein the memory device loads a first page of sense amplifiers in the first number of the physical banks for activate operation in the first width configuration and loads a second page of sense amplifiers in the second number of physical banks for activate operations in the second width configuration, the first page smaller than the second page., 'wherein3 ...

Memory Arrays

Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F 2 .

Multi-chip package and operating method thereof

A multi-chip package includes first and second semiconductor chips each configured to perform first and second operations having different current consumptions. The first and second semiconductor chips perform the first operation in response to an enable control signal transmitted from one of the first and second semiconductor chips to the other and transmitted from the other back to the one.

Semiconductor memory device

A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.

MEMORY HAVING BURIED DIGIT LINES AND METHODS OF MAKING THE SAME

A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4Farchitecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device. 1. A memory cell comprising:a storage device;a vertical access device electrically coupled to the storage device;a word line electrically coupled to the vertical access device; anda buried digit line electrically coupled to the vertical access device and disposed below the storage device, the word line, and the vertical access device.2. The memory cell of claim 1 , wherein the word line and the buried digit line are orthogonal to each other.3. The memory cell of claim 1 , wherein the storage device is disposed above the vertical access device.4. The memory cell of claim 1 , wherein the storage device is disposed above the word line.5. The memory cell of claim 1 , wherein the storage device comprises a capacitor.6. The memory cell of claim 1 , wherein the vertical access device comprises a finFET.7. The memory cell of claim 6 , wherein the finFET comprises a fin claim 6 , and the vertical height of the word line is greater than two times the thickness of the fin.8. The memory cell of claim 1 , wherein the memory cell comprises at least two vertical access devices claim 1 , each of which is disposed above the buried digit line.9. The memory cell of claim 8 , wherein the memory cell comprises at least two word lines electrically coupled to the vertical access devices.10. A memory array comprising:a memory cell having two vertical access devices electrically coupled to and disposed below a storage device;a word line ...

OFFSETTING CLOCK PACKAGE PINS IN A CLAMSHELL TOPOLOGY TO IMPROVE SIGNAL INTEGRITY

The disclosed embodiments relate to the design of a memory system which includes a set of one or more memory modules, wherein each memory module in the set has a clamshell configuration, wherein pairs of opposing memory packages containing memory chips are located on opposite sides of the memory module. The memory system also includes a multi-drop path containing signal lines which pass through the set of memory modules, and are coupled to memory packages in the set of memory modules. For a given signal line in the multi-drop path, a first memory package and a second memory package that comprise a given pair of opposing memory packages are coupled to the given signal line at a first location and a second location, respectively, wherein the first location and the second location are separated from each other by a distance d along the given signal line. 1. A memory system , comprising:a circuit board having one or more pairs of opposing memory chips which are located on opposite sides of the circuit board in a clamshell configuration; anda multi-drop path for at least one signal line coupled to each memory chip;{'sub': '1', 'wherein a first memory chip and a second memory chip are coupled to the at least one signal line at a first location and a second location on the signal line, respectively, wherein the first location and the second location are separated from each other by a distance dalong the signal line.'}2. The memory system of claim 1 , wherein the distance dis substantially half of a spacing dbetween successive pairs of opposing memory chips along the given signal line claim 1 , whereby coupling locations and associated loads for individual memory chips are distributed along the signal line.3. (canceled)4. The memory system of claim 1 ,wherein the first and second memory chips are contained within a first and a second memory package, respectively; andwherein for another signal line in the multi-drop path, the first and second memory chips in each pair of ...

SEMICONDUCTOR DEVICE

According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate. 119-. (canceled)20. A semiconductor device comprising:a substrate portion comprising a first layer portion with a first wiring pattern, a second layer portion with a second wiring pattern, and a third layer portion with a third wiring pattern, and the substrate portion comprising a substantially rectangular shape in a plan view;a connector to be connectable to a host device;a first nonvolatile semiconductor memory element provided on a surface of the first layer portion of the substrate portion;a second nonvolatile semiconductor memory element provided on the surface of the first layer portion of the substrate portion;a third nonvolatile semiconductor memory element provided on the surface of the first layer portion of the substrate portion;a controller provided on the substrate portion and electrically connected to the first nonvolatile semiconductor memory element, the second nonvolatile semiconductor memory element, and the third nonvolatile semiconductor memory element; anda signal line provided on a surface of the second layer portion of the substrate portion and formed between the connector and the controller to electrically connect the connector to the controller,wherein the first nonvolatile semiconductor memory element and the second nonvolatile semiconductor memory element are aligned along the longitudinal direction of the substrate portion.21. The semiconductor device according to claim 20 , further comprising:resistive elements provided on ...

CONFIGURABLE MODULE AND MEMORY SUBSYSTEM

A configurable memory subsystem includes a memory module with a circuit board having a first and a second memory-containing device (MCD) pair mounted thereto. Each MCD pair has a first MCD in communication with a second MCD. Each MCD has an input port, an output port, and a memory each communicating with a bridge. In response to a command, the bridge transfers at least one of a portion of a data packet from the input port to the output port or to the memory, or transfers a portion of a memory packet from the memory to the output port. A loop-back device receives the command and the data packet form the first MCD pair and transmits the command and data packet to the second MCD pair. 1. A memory module comprising:a plurality of devices each including an input port, an output port, a semiconductor chip and a non-volatile memory contained in the semiconductor chip or in a separate memory chip, and the semiconductor chip being configured to receive a command and a data packet on the input port and being further configured to execute, in response to the command: a transfer of a portion of the data packet from the input port to the non-volatile memory; a transfer of a portion of the data packet from the input port to the output port; or a transfer of a portion of a memory packet from the non-volatile memory to the output port; anda circuit board including the plurality of devices mounted thereto and having a plurality of conducting paths for serial communication between a first device of the plurality of devices and a second device of the plurality of devices, the first device being on a first side of the circuit board and the second device being on a second side of the circuit board.2. The memory module of wherein the semiconductor chip is a bridge.3. The memory module of wherein each of the plurality of devices is a stacked multi-chip device with the non-volatile memory contained in the separate memory chip.4. The memory module of wherein each of the plurality of devices ...

Semiconductor Devices Having a Three Dimensional Stacked Structure and Methods of De-Skewing Data Therein

A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard. 1. A semiconductor device comprising:a memory area that includes a plurality of memory areas that are disposed in at least two layers;at least two local wordlines disposed within respective ones of the at least two layers and that is conductively coupled therein;a common wordline that is operable to provide a wordline voltage to the memory area in a layer specific order;a bitline that is configured to output data that is stored in the memory and that is substantially orthogonal to the at least two local wordlines; anda circuit area that is disposed in at least one of the at least two layers and that is operable to generate the wordline voltage and to interface with a device that is external to the semiconductor device.2. The semiconductor device of claim 1 , wherein the layer specific order includes an order from one of the at least two layers that is far from the circuit area relative to another one of the at least two layers that is closer to the circuit area.3. The semiconductor device of ...

Arrays Of Nonvolatile Memory Cells And Methods Of Forming Arrays Of Nonvolatile Memory Cells

An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first plurality of horizontally oriented first electrode lines and a second plurality of horizontally oriented second electrode lines crossing relative to the first electrode lines. Individual of the memory cells include a crossing one of the first electrode lines and one of the second electrode lines and material there-between. Specifically, programmable material, a select device in series with the programmable material, and current conductive material in series between and with the programmable material and the select device are provided in series with such crossing ones of the first and second electrode lines. The material and devices may be oriented for predominant current flow in defined horizontal and vertical directions. Method and other implementations and aspects are disclosed. 122-. (canceled)23. An array of nonvolatile memory cells , comprising: a first plurality of horizontally oriented first electrode lines;', 'a second plurality of horizontally oriented second electrode lines crossing relative to the first electrode lines; and', a crossing one of the first electrode lines and one of the second electrode lines;', 'programmable material, a select device in series with the programmable material, and current conductive material in series between and with the programmable material and the select device; the programmable material and the select device being in series with such crossing ones of the first and second electrode lines; and', 'the programmable material and the select device are oriented for predominant current flow into or out of the crossing one first electrode line out of or into, respectively, one of the programmable material or select device in a first direction, and for predominant current flow into or out of the crossing one second electrode line out of or into, respectively, the other of the ...

NON-VOLATILE MEMORY HAVING 3D ARRAY ARCHITECTURE WITH BIT LINE VOLTAGE CONTROL AND METHODS THEREOF

In a 3D memory with vertical local bit lines, each local bit line is switchably connected to a node on a global bit line having first and second ends, the local bit line voltage is maintained at a predetermined reference level in spite of being driven by a bit line driver from a first end of the global bit line that constitutes variable circuit path length and circuit serial resistance. This is accomplished by a feedback voltage regulator comprising a voltage clamp at the first end of the global bit line controlled by a bit line voltage comparator at the second end of the global bit line. The comparator compares the bit line voltage sensed from the second end with the predetermined reference level and outputs a control voltage to control the voltage clamp In this way the voltage at the local bit line is regulated at the reference voltage. 1. A non-volatile memory , comprising:a local bit line;a global bit line of finite resistance having first and second ends;a switch for switchably connecting said local bit line to a node on said global bit line;a voltage supply for supply a first voltage to the first end of said global bit line; so that a local bit line voltage appears at the node connecting to said local bit line;a bit line voltage control circuit having a voltage clamp and a comparator;the comparator responsive to a comparison between a predetermined reference voltage and a second voltage sensed from the second end to output a control voltage; andthe voltage clamp, responsive to the control voltage, controls the first voltage at the first end such that the local bit line is maintained at the predetermined reference voltage irrespective of the resistance in said global bit line.2. The non-volatile memory as in claim 1 , further comprising:a sense amplifier for providing said voltage supply.3. The non-volatile memory as in claim 1 , wherein:said voltage clamp is a transistor connected in series between said voltage sum ly and the first end; andthe transistor has a ...

NON-VOLATILE MEMORY HAVING 3D ARRAY ARCHITECTURE WITH STAIRCASE WORD LINES AND VERTICAL BIT LINES AND METHODS THEREOF

In a 3D nonvolatile memory with memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes from a bottom plane to a top plane stacked in the z-direction over a semiconductor substrate; a plurality of local bit lines elongated in the z-direction through the plurality of layers and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; the 3D nonvolatile memory further having a plurality of staircase word lines spaced apart in the y-direction and between and separated from the plurality of bit line pillars at a plurality of crossings, individual staircase word lines each having a series of alternating steps and risers elongated respectively in the x-direction and z-direction traversing across the plurality of planes in the z-direction with a segment in each plane. 1. A non-volatile memory , comprising:memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes from a bottom plane to a top plane stacked in the z-direction over a semiconductor substrate;a plurality of local bit lines elongated in the z-direction through the plurality of parallel planes and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction;a plurality of staircase word lines spaced apart in the y-direction and between and separated from the plurality of bit line pillars at a plurality of crossings, individual staircase word lines each having a series of alternating steps and risers elongated respectively in the x-direction and z-direction traversing across the plurality of planes in the z-direction with a segment in each plane; anda plurality of non-volatile re-programmable memory elements individually connected through circuits between the bit line ...

MEMORY BANDWIDTH AGGREGATION USING SIMULTANEOUS ACCESS OF STACKED SEMICONDUCTOR MEMORY DIE

A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin. 1. A packaged semiconductor memory device , comprising:a data pin; a first data interface coupled to the data pin, and', 'a first memory core having a plurality of banks; and, 'a first memory die comprisinga second memory die stacked with the first memory die and comprising a second memory core having a plurality of banks; wherein:a respective bank of the first memory core and a respective bank of the second memory core are to perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal; andthe first data interface is to provide aggregated data from the parallel column access operations to the data pin.2. The packaged semiconductor memory device of claim 1 , wherein:the respective bank of the first memory core and the respective bank of the second memory core are to perform a series of parallel column access operations in response to a series of column access commands; andthe first data interface is to provide aggregated data from the series of parallel column access operations to the data pin.3. The packaged semiconductor memory device of claim 1 , wherein:the first memory die further comprises a first data path, coupled between the first ...

3d memory with vertical bit lines and staircase word lines and vertical switches and methods thereof

A 3D memory with vertical local bit lines global bit lines has an in-line vertical switch in the form of a thin film transistor (TFT) formed as a vertical structure, to switch a local bit line to a global bit line. The TFT is implemented to switch a maximum of current carried by the local bit line by a strongly coupled select gate which must be fitted within the space around the local bit line. Maximum thickness of the select gate is implemented with the select gate exclusively occupying the space along the x-direction from both sides of the local bit line. The switches for odd and even bit lines of the row are staggered and offset in the z-direction so that the select gates of even and odd local bit lines are not coincident along the x-direction. The switching is further enhanced with a wrap-around select gate.

Cross-threaded memory system

In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requestor IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.

Bitline for Memory

Subject matter disclosed herein relates to accessing memory, and more particularly to operation of a partitioned bitline.

Memory system

A memory system includes a processor and a plurality of memories. The processor includes a plurality of ECCs having different error restoration rates with each other, and a plurality of memories is coupled to the plurality of ECCs, respectively, according to distances from the processor.

Dynamic memory performance throttling

Dynamic memory performance throttling. An embodiment of a memory device includes a memory stack including coupled memory elements; the memory elements including multiple ranks, the plurality of ranks including a first rank and a second rank, and a logic device including a memory controller. The memory controller is to determine an amount of misalignment between data signals relating to a read request for the first rank and a read request for the second rank, and, upon determining that misaligment between the first rank and the second rank is greater than a threshold, the memory controller is to insert a time shift between a data signal for the first rank and a data signal for the second rank.

SEMICONDUCTOR DEVICE, ADJUSTMENT METHOD THEREOF AND DATA PROCESSING SYSTEM

A system includes a first device, a second device, and a bus interconnecting the first and second devices to each other, wherein the first device includes a first semiconductor chip that includes a first memory cell array including a plurality of first memory cells, a first control logic circuit accessing the first memory cell array and producing a first data signal in response to data stored in a selected one of the first memory cells, the first control logic circuit being configured to store first timing adjustment information and to produce a first output timing signal that is adjustable in timing of change from an inactive level to an active level by the first timing adjustment information, a first data electrode, and a first data control circuit coupled to the first control logic circuit and the first data electrode. 1. A system comprising:a first device;a second device; anda bus interconnecting the first and second devices to each other; [ a first memory cell array including a plurality of first memory cells,', 'a first control logic circuit accessing the first memory cell array and producing a first data signal in response to data stored in a selected one of the first memory cells, the first control logic circuit being configured to store first timing adjustment information and to produce a first output timing signal that is adjustable in timing of change from an inactive level to an active level by the first timing adjustment information,', 'a first data electrode, and', 'a first data control circuit coupled to the first control logic circuit and the first data electrode, the first data control circuit receiving the first data signal and responding to change from the inactive level to the active level of the first output timing signal to initiate driving the first data electrode to a logic level related to the first data signal;, 'a first semiconductor chip that comprises,'}, a second memory cell array including a plurality of second memory cells,', 'a ...

Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules

A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector.

NON-VOLATILE MEMORY DEVICE WITH CLUSTERED MEMORY CELLS

An embodiment of a non-volatile memory device includes: a memory array, having a plurality of non-volatile logic memory cells arranged in at least one logic row, the logic row including a first row and a second row sharing a common control line; and a plurality of bit lines. Each logic memory cell has a direct memory cell, for storing a logic value, and a complementary memory cell, for storing a second logic value, which is complementary to the first logic value in the corresponding direct memory cell. The direct memory cell and the complementary memory cell of each logic memory cell are coupled to respective separate bit lines and are placed one in the first row and the other in the second row of the respective logic row. 111-. (canceled)12. An integrated circuit , comprising:first and second rows;first and second data lines;a portion of a memory cell disposed in one of the first and second rows and coupled to one of the first and second data lines; anda complementary portion of the memory cell disposed in the other of the first and second rows and coupled to the other of the first and second data lines.13. The integrated circuit of wherein the first and second data lines include first and second bit lines.14. The integrated circuit of wherein the memory cell includes a non-volatile memory cell.15. The integrated circuit of wherein the memory cell includes a differential memory cell.16. The integrated circuit of claim 12 , further comprising a select line coupled to the portion and the complementary portion of the memory cell.17. The integrated circuit of claim 12 , further comprising:a cluster of more than two memory cells each having a respective portion coupled to one of the first and second data lines and having a respective complementary portion coupled to the other of the first and second data lines; andwherein the memory cell is disposed in the cluster.18. The integrated circuit of claim 12 , further comprising:a cluster of more than two memory cells each ...

Memory module with distributed data buffers and method of operation

A memory module is operable to communicate with a memory controller via a data bus and a control/address bus and comprises a module board; a plurality of memory devices mounted on the module board; and multiple sets of data pins along an edge of the module board. Each respective set of the multiple sets of data pins is operatively coupled to a respective set of multiple sets of data lines in the data bus. The memory module further comprises a control circuit configured to receive control/address information from the memory controller via the control/address bus and to produce module control signals. The memory module further comprises a plurality of buffer circuits each being disposed proximate to and electrically coupled to a respective set of the multiple sets of data pins. Each buffer circuit is configured to respond to the module control signals by enabling data communication between the memory controller and at least one first memory device among the plurality of memory devices and by isolating at least one second memory device among the plurality of memory devices from the memory controller.

Three dimensional structure memory

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. 1. A stacked memory integrated circuit comprising:a plurality of circuit layers comprising at least one control circuit layer and at least one memory circuit layer arranged in a stacked relationship;wherein the control and memory circuit layers of the stacked memory integrated circuit are partitioned into a plurality of vertically interconnected circuit blocks and configured for a plurality of said vertically interconnected circuit blocks to independently perform memory operations.2. The stacked memory integrated circuit of claim 1 , wherein each of the plurality of vertically interconnected circuit blocks comprises a memory array and an array of vertical interconnects interconnecting the vertically interconnected circuit block with the at least one control circuit layer.3. The stacked memory integrated circuit of claim 1 , wherein the control circuit layer is configured to perform functional testing of at least part of the stacked memory integrated circuit.4. The stacked memory integrated circuit of claim 1 , wherein the control circuit layer is configured to perform reconfiguration of at least part of the stacked memory integrated circuit.5. A stacked memory integrated circuit comprising:a plurality of circuit layers comprising at least one control circuit layer and at least ...

Nonvolatile semiconductor memory device

This nonvolatile semiconductor memory device comprises a memory cell array configured having a plurality of memory mats arranged therein, each of the memory mats having a memory cell disposed therein at an intersection of a first line and a second line, the memory cell including a first variable resistance element. A third line extends through a plurality of the memory mats. A second variable resistance element is connected between the third line and the second line of each of the plurality of memory mats.

STACKED DRAM DEVICE AND METHOD OF MANUFACTURE

A memory stack includes a number of memory dies including a master die and one or more slave dies. The slave die can be converted to a master die by further processing. The slave die includes a memory core having memory cell arrays. The slave die also includes first and second metal layers that form first and second distribution lines in the memory core, respectively. An interface circuit in the slave die is decoupled from the first and second metal layers. 1. A memory die for use in a memory device comprising:a memory core having memory cell arrays interconnected by first and second distribution lines;a first metal layer including the first distribution linesa second metal layer including the second distribution lines; andan interface circuit that is not coupled to the first or second distribution lines via any conductors on the memory die.2. The memory die according to wherein the memory die comprises a slave memory die configured to communicate with a memory controller via a master memory die claim 1 , and wherein the memory die is incapable of communicating command or data with the memory controller without the master memory die.3. The memory die according to wherein the slave memory die comprises at least one through-silicon-via (TSV) formed to couple the memory core of the slave memory die to an interface circuit of the master memory die.4. (canceled)5. The memory die according to wherein the slave memory die receives power via the at least one TSV.6. (canceled)7. The memory die according to wherein the memory die comprises a slave memory die configured to communicate with a memory controller via a buffer die claim 1 , and wherein the memory die is incapable of communicating command or data with the memory controller without the buffer die.813-. (canceled)14. The memory die according to wherein the memory die is of a predetermined width claim 1 , and is formed with a number of through-silicon-vias claim 1 , wherein the number of through-silicon-vias is based ...

STACKED SEMICONDUCTOR DEVICES INCLUDING A MASTER DEVICE

A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s). 1. (canceled)2. A system , comprising: a first memory chip comprising circuitry for generating one or more of voltage signals and control signals; and', 'a second memory chip lacking circuitry for generating one or more of voltage signals and control signals; and, 'a stack includinga plurality of Through-Silicon Vias extending between the first memory chip and the second memory chip, the Through-Silicon Vias connecting one or more of the voltage signals and the control signals generated by the first memory chip from the first memory chip to the second memory chip.3. The system of claim 1 , wherein the first and second memory chips are non-volatile memory chips.4. The system as claimed in wherein the first memory chip is a master device and the second memory chip is a slave device.5. The system of claim 2 , wherein only the first non-volatile memory chip includes a high voltage generator.6. The system of claim 1 , wherein:the first memory chip comprises circuitry for generating voltage signals; andthe generated voltage signals comprise high voltage signals for program and erase operations.7. The system of claim 1 , further comprising a third memory chip lacking circuitry for generating one or more of voltage signals and control signals claim 1 , wherein one or more of the voltage signals and the control signals generated by the first memory chip are communicated from the first memory chip to the third memory chip.8. The system of claim 1 , further comprising a package printed circuit board claim 1 , the stack connected to the package printed circuit board by flip chip and bumping.9. The system of claim 7 , wherein:the first memory device is larger dimensioned than the second memory device; andthe first memory device is positioned adjacent the package printed circuit ...

Techniques for providing a direct injection semiconductor memory device

Techniques for providing a direct injection semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device including the steps of applying a first non-negative voltage potential to a first region via a bit line and applying a second non-negative voltage potential to a second region via a source line. The method may also include applying a third voltage potential to a word line, wherein the word line may be spaced apart from and capacitively to a body region that may be electrically floating and disposed between the first region and the second region. The method may further include applying a fourth positive voltage potential to a third region via a carrier injection line, wherein the third region may be disposed below at least one of the first region, the body region, and the second region.

Buffer die in stacks of memory dies and methods

Memory devices and methods of making and operating them are shown. Memory devices shown include stacked memory dies with one or more buffer dies included. In one such memory device, a command die communicates with one or more downstream memory dies through the one or more buffer dies. The one or more buffer dies function to repeat signals, and can potentially improve performance for higher numbers of memory dies in the stack.

Apparatuses and methods including memory array and data line architecture

Some embodiments include apparatus and methods having memory cells located in different device levels of a device, at least a portion of a transistor located in a substrate of the device, and a data line coupled to the transistor and the memory cells. The data line can be located between the transistor and the memory cells. Other embodiments including additional apparatus and methods are described.

Continuous mesh three dimensional non-volatile storage with vertical select devices

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Semiconductor integrated circuit and signal transmission method thereof

A semiconductor integrated circuit includes a plurality of semiconductor chips stacked in a multi-layer structure; a correction circuit in each semiconductor chip configured to reflect a delay time corresponding to the position of the chip in the stack into an input signal to output to each semiconductor chip; and a plurality of through-chip vias formed vertically through each of the semiconductor chips and configured to transmit the input signal to the semiconductor chip.

CLOCK ADJUSTING CIRCUIT, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT UNIT

A memory storage device, a memory control circuit unit, and a clock adjusting circuit disposed on a plurality of layers are provided. The clock adjusting circuit includes a detection circuit, a control voltage generating circuit, and a voltage-controlled oscillator (VCO). The detection circuit detects a signal characteristic difference between an input signal and an output signal to generate a first signal. The control voltage generating circuit is coupled to the detection circuit and generates a control voltage according to the first signal. The VCO is coupled to the control voltage generating circuit and includes an inductor and a capacitor. The VCO receives the control voltage and starts oscillating according to an impedance characteristic of the inductor and the capacitor to generate the output signal. The inductor is disposed on a pad layer among the layers. Thereby, the manufacturing cost is reduced. 1. A clock adjusting circuit , disposed on a die , wherein the die has a plurality of layers , the clock adjusting circuit comprising:a detection circuit, configured to detect a signal characteristic difference between an input signal and an output signal to generate a first signal;a control voltage generating circuit, coupled to the detection circuit, and configured to generate a control voltage according to the first signal; anda voltage-controlled oscillator (VCO), coupled to the control voltage generating circuit, and comprising a inductor and a capacitor, wherein the VCO is configured to receive the control voltage and oscillate according to an impedance characteristic of the inductor and the capacitor to generate the output signal,wherein the inductor is disposed on a pad layer among the layers.2. The clock adjusting circuit according to further comprising:a filter, coupled between the control voltage generating circuit and the VCO, wherein the filter comprises a filter capacitor, the filter capacitor is disposed on a first layer among the layers, the first ...

SEMICONDUCTOR DEVICE HAVING MULTIPORT MEMORY

A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA, WLB, WLB, WLA, WLA. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other. 1first and second static memory cells, first, second, third and fourth word lines, and first and second pairs of bit lines,wherein each of the first and second static memory cells includes a latch circuit having a first inverter and a second inverter, a first access transistor and a second access transistor coupled to the first latch circuit, and a third access transistor and a fourth access transistor coupled to the second latch circuit,wherein the first inverter has a first driver transistor and a first load transistor, and the second inverter has a second driver transistor and a second load transistor,wherein the first word line is electrically coupled to the first and third access transistors of the first static memory cell, the second word line is electrically coupled to the second and fourth access transistors of the first static memory cell, the third word line is electrically coupled to the second and fourth access transistors of the second static memory cell, and the fourth word line is electrically coupled to the first and third access transistors of the second static memory cell,wherein one of the first pair of bit lines is electrically coupled to the first access transistor of each of the first and second static memory cells, the other of the first pair of bit lines is electrically coupled to the third access transistor ...

Three-Dimensional Memory Comprising Discrete Read/Write-Voltage Generator Die

The present invention discloses a discrete three-dimensional memory (3D-M). Its 3D-M arrays are located on at least one 3D-array die, while its read/write-voltage generator (V R /V W -generator) is located on a separate peripheral-circuit die. The V R /V W -generator generates at least a read and/or write voltage to the 3D-array die. A single V R /V W -generator die can support multiple 3D-array dies.

BALANCED DIE SET EXECUTION IN A DATA STORAGE SYSTEM

A data storage system can arrange semiconductor memory into a plurality of die sets where performance metrics of execution of a first data access command to a first die set and of a second data access command to a second die set are measured. A proactive strategy is generated to maintain consistent data access command execution performance with a quality of service module based on the measured performance metrics and a third data access command is altered, as directed by the proactive strategy, to prevent a predicted non-uniformity of data access command performance between the first die set and the second die set. 1. A method comprising:measuring performance metrics of execution of a first data access command to a first die set of a semiconductor memory and of a second data access command to a second die set of the semiconductor memory;generating a proactive strategy to maintain consistent data access command execution performance with a quality of service module based on the measured performance metrics; andaltering a third data access command as directed by the proactive strategy to prevent a predicted non-uniformity of data access command performance between the first die set and the second die set.2. The method of claim 1 , wherein the multiple data access commands comprise at least one data read claim 1 , at least one data write claim 1 , and at least one background operation3. The method of claim 1 , wherein the third data access command is altered prior to a predicted event that contributes to the non-uniformity of data access command performance.4. The method of claim 1 , wherein the quality of service module predicts at least one performance bottleneck that contributes to the non-uniformity of data access command performance.5. The method of claim 1 , wherein a prediction circuit of the quality of service module predicts at least one future data access command to the first die set.6. The method of claim 5 , wherein the prediction circuit predicts a data ...

STACKED MEMORY CHIP DEVICE WITH ENHANCED DATA PROTECTION CAPABILITY

A stacked memory chip device is described. The stacked memory chip device includes a plurality of stacked memory chips. The stacked memory chip device includes read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips. The stacked memory chip device includes data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive information of a particular one of the cache lines is not stored in a same memory chip with the respective substantive information. 1. A stacked memory chip device , comprising:a plurality of stacked memory chips;read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips;data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive data of a particular one of the cache lines is not stored in a same memory chip with the respective substantive data, the information to protect the substantive data of the cache lines being one of mirroring information and ECC information.2. The stacked memory chip device of where the information is to be stored at row/column granularity.3. The stacked memory chip device of where the information is to be stored at bank granularity4. The stacked memory chip device of wherein the information is to be stored in a region of the plurality of memory chips that is reserved for storage of respective information to protect respective substantive data of multiple cache lines.5. The stacked memory chip device of wherein the information is ...

METHODS AND APPARATUS FOR MANAGING THERMAL BEHAVIOR IN MULTICHIP PACKAGES

An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors. 1. An integrated circuit , comprising:an interface circuit to communicate with an external die stack having a plurality of vertically stacked dies; andcontrol circuitry to receive one or more parameters of the associated with the external die stack and to distribute accesses among the plurality of vertically stacked dies based at least upon the one or more parameters.2. The integrated circuit of claim 1 , wherein the one or more parameters comprise a memory bandwidth utilization metric.3. The integrated circuit of claim 1 , wherein the one or more parameters comprise a memory bank status claim 1 , a number of commands claim 1 , at least one threshold value claim 1 , a number of page openings and closures claim 1 , or any combination thereof.4. The integrated circuit of claim 1 , wherein the one or more parameters comprise a memory error threshold value.5. The integrated circuit of claim 1 , wherein the one or more parameters comprise a frequently accessed region pattern of a given die in the external die stack.6. The integrated circuit of claim 1 , wherein the one or more parameters comprise temperature data associated with more than one of the vertically stacked dies in the external die stack.7. The integrated circuit of claim 6 , wherein the temperature data includes a first temperature sensor measurement from a topmost die in the ...

CENTRALIZED PLACEMENT OF COMMAND AND ADDRESS IN MEMORY DEVICES

Memory devices, memory systems, and systems, include memory devices with a bonding pad region including two or more bonding pads for operably coupling to external signals and a number of command-and-address (CA) input signals. The memory device also includes centralized CA interface region including two or more CA input circuits operably coupled to the number of input signals. One of the tow or more CA input circuits for each CA input signal may border at least two other CA input circuits coupled to different CA input signals. 1. A device , comprising:a bonding pad region including a number of bonding pads for operably coupling to external signals and a number of command-and-address (CA) input signals; anda centralized CA interface region including two or more CA input circuits operably coupled to the number of CA input signals, wherein one of the two or more CA input circuits for each CA input signal borders at least two other CA input circuits coupled to different CA input signals.2. The device of claim 1 , further comprising a memory cell region claim 1 , wherein the centralized CA interface region is positioned between the bonding pad region and the memory cell region.3. The device of claim 1 , wherein the two or more CA input circuits are arranged with:a first pair of CA input circuits arranged in a first direction; andat least one additional pair of CA input circuits arranged in a second direction relative to the first pair of CA input circuits.4. The device of claim 1 , wherein each of the two or more CA input circuits comprise:a buffer circuit operably coupled to one of the number of CA input signals;a latch circuit for receiving one or more clock signals; anda delay circuit arranged between the buffer circuit and the latch circuit.5. The device of claim 1 , further comprising a clock buffer circuit adjacent to at least one of the two or more CA input circuits and configured to supply one or more clock signals to each of the two or more CA circuits.6. The ...

SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING CHIP SIZE

According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines. 1. (canceled)2. A semiconductor memory device comprising: a first well of a first conductively type being formed in the substrate;', 'a second well of a second conductively type being formed in the first well;, 'a substrate,'}a plurality of bit lines, the plurality of bit lines including a first bit line and a second bit line adjacent to the first bit line;a source line; a first NAND string connected between the first bit line and the source line,', 'a second NAND string connected between the second bit line and the source line', 'a third NAND string connected between the first bit line and the source line, and', 'a fourth NAND string connected between the second bit line and the source line;, 'a plurality of NAND strings, each of the NAND strings including a first select transistor, a second select transistor, and a plurality of memory cells connected in series between the first select transistor and the second select transistor, the plurality of NAND strings includinga first line connected between the source line and a first node;a sense amplifier;a first transistor connected at a first end to the sense amplifier and connected at a second end to a second node; and a first bit line select transistor connected at a first end to the first node and connected at a second end to the first bit line,', 'a second bit line select transistor connected at a first end to the first node and connected ...