Multi-Port memory device with stacked banks
Figure 1 shows a multi-port memory device also of the existing method is that describes a surface. Figure 2 shows a multi-port memory device read path Figure described is surface of Figure 1. Figure 3 shows a multi-port memory device also that describes a path inputs of is surface of Figure 1. A are also Figure 4 shows a multi-port memory according to one embodiment of the invention is surface that describes a device. Figure 5 shows a multi-port memory device read path Figure described is surface of Figure 4. Figure 6 shows a multi-port memory device also that describes a path inputs of is surface of Figure 4. The present invention refers to multi-port memory device relates to, in particular each banks stack multi-port memory that is, before relates to device. Input port and through a redundant output port even pair of data is at the same time, the memory cell array written in memory cell array read out from a general dual port memory device.. Video camera device dual port memory device may be used for Image memory or the like. Dual port memory concurrently accessible together a device which are defined a port since the other, functional, according to the application table control higher Image port number necessary multi-port memory, which is capable of securing required the presence of the device.. Multi-port memory device the internally multi-channel independently banks performs access operation. Independent bank access command independent of reading and writing operation is multi-port memory device of is elements determines the operational speed. A read-independent a plurality of cells, and each multi-port memory device of data within line structure. on the counter directions with each other. Figure 1 shows a multi-port memory of the existing method also to explain an internal structure of device is surface. Refer to surface, multi-port memory device (10) the plurality banks, bank 0 (100), bank 1 (101), bank 2 (102) and bank 3 (103), data line sense amplifier are (IOSA, 110, 112), data line drivers (IO DRV, 120, 122), write buffers (130, 132, 134, 136), read buffers to sense (140, 142, 144, 146), and plurality of ports, port 0 (150), port 1 (152), port 2 (154) and port 3 (156) includes. Bank 0 (100) and bank 1 (101), bank 2 (102) and a bank 3 (103) and configured in a bank structure a stack, ports (150, 152, 154, 156) the MCP through an bit, e.g. 512 is of the I/O bit data. Bank 0 (100) and a bank 1 (101) the number 1 global data lines (GIO <i >, I=0, 1, 2, ..., 511) number 1 through data line sense amplifier (110) or a data line driver number 1 (120) is connected, bank 2 (102) and a bank 3 (103) the number 2 global data lines (GIO <j>, J=0, 1, 2, ..., 511) number 2 through data line sense amplifier (112) or a data line driver number 2 (122) and a are connected. Data line sense amplifier are (110, 120) to be read through the reading data line buffers (RDL) (140, 142, 144, 146) and, read buffers to sense (140, 142, 144, 146) each port (150, 152, 154, 156) and a are connected. Data line drivers (120, 122) through the disk when the disk is rotating (WDL) data line write buffers (130, 132, 134, 136) and, write buffers (140, 142, 144, 146) each port (150, 152, 154, 156) and a are connected. One end of the multibank memory device (10) for reading and write operation is made as follows. Also multibank memory device (10) Figure 2 shows a read data path is the surfaces of the laminated structure in described. Refer to surface, bank 0 (100) and bank 1 (101) F211 number 1 data memory cell 512 global data lines (GIO <0>, GIO <1>, GIO <2>,..., GIO <511>) Number 1 through data line sense amplifier (110) is transferred to a. Bank 2 (102) and a bank 3 (103) F211 number 2 data memory cell 512 global data lines (GIO <0>, GIO <1>, GIO <2>,..., GIO <511>) Number 2 through data line sense amplifier (112) is transferred to a. Number 1 data line sense amplifier (110) and a number 2 data line sense amplifier (112) has a read-data lines (RDL <0>, RDL <1>, RDL <2>,..., RDL <511>) Sharing a. Number 1 and number 2 data line sense amplifier (110, 112) is read data line (RDL) since the sharing, number 1 and number 2 data line sense amplifier (110, 112) only either selectively read buffers to sense (140, 142, 144, 146) are connected and. If number 1 data line sense amplifier (110) is read data lines (RDL <0>, RDL <1>, RDL <2>,..., RDL <511>) And connecting the, bank 0 (100) and a bank 1 (101) selected from number 1 512 memory cell data are data line sense amplifier (110) is amplified sensed by read data lines (RDL <0>, RDL <1>, RDL <2>,..., RDL <511>) To be read through buffers (140, 142, 144, 146) at least one of the, e.g. number 1 read buffers (140) are stored in. Number 1 read buffers (140) stored in the 0 (150) port 512 bit data is output in a manner that continuously arrange files. Here, bank 0 (100) and a bank 1 (101) F211 memory cell data are accessed and read buffers (140) and a port 0 (150) during read-out through the, bank 2 (102) and a bank 3 (103) of memory cell data access of the wafer is not.. Figure 3 shows a multi-port memory device of Figure described the write data path is surface of Figure 1. Refer to surface, of Figure 2 read data path and similarly, e.g. port 0 (150) is in the write data are sequentially write buffers number 1 (130) stored in composed of bits of data 512. Number 1 write data buffer (130) 512 bit data stored in the write data lines (WDL <0>, WDL <1>, WDL <2>,..., WDL <511>) By communicating, a data line driver number 1 (120) is transferred to a. Number 1 a data line driver (120) the of a global input/output line (GIO <0>, GIO <1>, GIO <2>,..., GIO <511>) Through bank 0 (100) or bank 1 (101) is connected to selected banks is activated, e.g. bank 0 (100) of 512 memory cells stores the data write. Even write operation, port 0 (150) and a write buffers (130) a write data input during n periods of a clock are bank 0 (100) or bank 1 (101) stored access to memory cells of a during, bank 2 (102) and a bank 3 (103) .not accessed wrtus of memory cells. Multi-port memory device (10) of the existing method step, the BSD the stacked bank 0 (100) and a bank 1 (101), and bank 2 (102) and a bank 3 (103) returned to the above stage accessed independently of each other data read speed and data writing speed is promoted and the limit. the other. The, stack port independently accessed and independently of reading and writing the position of a multi-port memory device need for is present. The present purpose of the invention a new access, independently one of the other are capable of multi-port memory having a stack bank architecture and a device respectively.. Said end of the, a preferred device multi-port memory of the present invention rest processes plurality of ports; plurality of memory cells are one or more bank 2 are one data line sense amplifier banks share a plurality of stack; each stack banks, is connected between read buffers to sense, in bank stack plurality of memory cells own one selected banks is activated data line sense amplifier are sensing data; each ports and and being linked with each other, data line sense amplifier read from the memory cell of the bank selected in the port and outputs the data signal to the read buffers to sense; and each data line sense amplifier and each read buffers the part interconnects between including read data line. Data line sense amplifier are in bank stack in parallel from memory cells of selected banks is activated and a zero crossing of the line data based on the read data, read buffers to sense the data line sense amplifier read from the memory cell data outputs the in series with ports. Said end of the, a preferred device multi-port memory of the present invention a second example plurality of ports; plurality of memory cells are one or more bank 2 are one data line driver shared a plurality of stack banks; each ports and, is in the write buffers storing write data; each stack banks, is connected between write buffers, within bank stack of selected banks is activated for driving write data memory cells data line drivers; each data line driver and each write buffers the part interconnects between including line write data. Write buffers the port in series via the memory cell data outputted from the then stored in the memory the signals is converted into a parallel, data line drivers stack within bank write data memory cells of selected banks is activated decoder decoding a row address drives in parallel. Said end of the, more device multi-port memory of the present invention a preferred example bi-directional input/output a plurality of ports; plurality of memory cells are one or more bank 2 are one data line sense amplifier and one data line driver shared a plurality of stack banks; stack banks, is connected between read buffers to sense, in bank stack of selected banks is activated in parallel from memory cells read data sensing data line sense amplifier are; each said stack banks, is connected between write buffers, within selected banks is activated bank stack of memory cells write data in parallel that of the display unit driven by a data line drivers; each ports and and being linked with each other, data line sense amplifier read from the parallel memory cell data of the bank selected in the stack in series with the read buffers to sense outputs; each ports and, through data inputted in Serial write data in parallel write buffers a converted to; each data line sense amplifier and each read buffers the part interconnects between read data lines; and each data line driver and each write buffers the part interconnects between including line write data. Therefore, according to multi-port memory device of the present invention, plurality of stack accessed and independently of each other bank independently reading and writing operation in are connected to the switching circuit, a decimator is provided to convert data throughput data read speed and is speed is improved due to the data write. Exit of the present invention or of the present invention embodiment of the present invention and an objective achieved by quite an exemplary embodiment of the present invention in order thereby, the cold air flows accompanying drawing and accompanying drawing describing must reference recorded contents of described.. Hereinafter, based on a text content of the drawing reference to a preferred embodiment of the present invention by describing a thereby, the cold air flows, the described detail the present invention. Each drawing to be presented to the same references exhibits and the same member. For facilitating of the 4 of the present invention in the embodiment are two ports and having bank of the two stacks 2 multi-port memory device is described. Various therefrom number of ports and the stack banks multi-port memory device allowing the expanded application to the decoration plate further comprises an. nontrivial twiddle factors and to one skilled in the art. A are also Figure 4 shows a multi-port memory according to one embodiment of the invention is surface that describes a device. Refer to surface, multi-port memory device (40) the number 1 stack filterbanks bank 0 (400) and a bank 1 (401), a bank stack number 2 bank 2 (402) and a bank 3 (403), data line sense amplifier are (IOSA, 410, 412), data line drivers (IO DRV, 420, 422), write buffers (430, 432, 434, 436), read buffers to sense (440, 442, 444, 446), port 0 (450), port 1 (452), port 2 (454) and port 3 (456) includes. Bank 0 (400) and bank 1 (401) the number 1 global data lines (GIO <i >, I=0-511) number 1 through data line sense amplifier (410) and a number 1 a data line driver (420) and a are connected. Bank 2 (402) and a bank 3 (403) the number 2 global data lines (GIO <j>, J=0-511) number 2 through data line sense amplifier (412) and a number 2 a data line driver (422) and a are connected. Number 1 and number 2 data line sense amplifier are (410, 412) the number 1 read data lines (RDL <i >, I=0-511) and number 2 read data lines (RDL <j>, J=0-511) through to be read buffers (440, 442, 444, 446) and are connected. Number 1 and number 2 a data line driver (420, 422) the number 1 write data lines (WDL <i >, I=0-511) and number 2 write data lines (WDL <j>, J=0-511) write buffers through (430, 432, 434, 436) are connected and. Number 1 write buffers (430) and a number 1 read buffers (440) the port 0 (450) and, write buffers number 2 (432) and a number 2 read buffers (442) the port 1 (452) and, write buffers number 3 (434) and a number 3 read buffers (444) the port 3 (454) and, write buffers number 4 (436) and a number 4 read buffers (446) the port 4 (456) and a are connected. The present embodiment the first deoxygenator multi-port memory device (40) of Figure 1 the multi-port memory device (10) comparison with a, number 1 and number 2 data line sense amplifier are (410, 412) and read buffers to sense (440, 442, 444, 446) coupled between the read data lines number 2 (RDL <j>, J=0-511) further includes a, number 1 and number 2 data line drivers (420, 422) and write buffers (430, 432, 434, 436) coupled between the number 2 write data lines (WDL <j>, J=0-511) further that. which differs in both. In the embodiment the present this serious works data line sense amplifier (410, 412) for 2 one by one, and data line driver (420, 422) including a multi-port memory device 2 one by one in each data line sense amplifier (410, 412) and a data line driver (420, 422) independently to operate the, each data line sense amplifier (410, 412) number 1 and number 2, which are connected with the read data lines (RDL <i >, RDL <j>, I, j=0-511) and each data line driver (420, 422), which are connected with the number 1 and number 2 write data lines (WDL <i >, WDL <j>, I, j=0-511) since having is difference, the laser beam is transmitted through. The present embodiment the first deoxygenator multi-port memory device (450) the read operation of the and write operations also 5 and 6 is described as follows: an reference to. Also multi-port memory device (40) Figure 5 shows a read path is the surfaces of the laminated structure in described. Refer to surface, bank 0 (400) and bank 1 (401) F211 number 1 data memory cell 512 global data lines (GIO <0>, GIO <1>, GIO <2>,..., GIO <511>) Number 1 through data line sense amplifier (410) is transferred to a. Bank 2 (402) and a bank 3 (403) F211 number 2 data memory cell 512 global data lines (GIO <0>, GIO <1>, GIO <2>,..., GIO <511>) Number 2 through data line sense amplifier (412) is transferred to a. Number 1 data line sense amplifier (410) the number 1 read data lines (RDL <0>, RDL <1>, RDL <2>,..., RDL <511>) To be read through buffers (140, 142, 144, 146) and, number 2 data line sense amplifier (412) the number 2 read data lines (RDL <0>, RDL <1>, RDL <2>,..., RDL <511>) To be read through buffers (140, 142, 144, 146) are connected and. Bank 0 (400) and a bank 1 (401) selected from number 1 data memory cell 512 data line sense amplifier (410) is amplified sensed by number 1 read data lines (RDL <0>, RDL <1>, RDL <2>,..., RDL <511>) To be read through buffers (440, 442, 444, 446) at least one of the, e.g. number 1 read buffers (440) are stored in. Bank 2 (402) and a bank 3 (403) selected from number 2 data memory cell 512 data line sense amplifier (412) number 2 is amplified sensed by read data lines (RDL <0>, RDL <1>, RDL <2>,..., RDL <511>) To be read through buffers (440, 442, 444, 446) the other of the one, e.g. number 2 read buffers (442) are stored in. Number 1 read buffers (440) 512 bit data stored in the 0 (550) port number 2 output line and outputs a manner that continuously arrange files of the read buffers (442) 512 bit data stored in the port 1 (552) is output in a manner that continuously arrange files. Here, bank 0 (400) and a bank 1 (401) F211 memory cell data are accessed and read buffers number 1 (440) and a port 0 (450) during read-out through the, bank 2 (402) and a bank 3 (403) F211 memory cell data are accessed and read buffers number 2 (442) and a port 1 (452) being output across the.. This conventional multi-port memory device (10) of Figure 1 in stacked bank 0 (100) and bank 1 (101), and bank 2 (102) and a bank 3 (103) of the wafer is not access independently of each other multiported memory device (10) of operation are set according to the power supply voltage boosting circuit of speed is limited, by using a time hopping code, the present embodiment the first deoxygenator stacked bank 0 (400) and bank 1 (401), and bank 2 (402) and a bank 3 (403) independently of each other since the access multi-port memory device (40) to be aligned is aligned or not speed power supply voltage boosting circuit of. means that the X and Y axis. Also Figure 6 shows a multi-port memory device (40) is surface that describes a path inputs of. Refer to surface, e.g. port 0 (450) the write data without the write buffers sequentially number 1 (430) stored in composed of bits of data 512. Number 1 write data buffer (430) number 1 512 bit data stored in the write data lines (WDL <0>, WDL <1>, WDL <2>,..., WDL <511>) By communicating, a data line driver number 1 (420) is transferred to a. While, e.g. port 1 (452) the write data without the write buffers sequentially number 2 (432) stored in composed of bits of data 512. Number 2 write data buffer (432) number 2 512 bit data stored in the write data lines (WDL <0>, WDL <1>, WDL <2>,..., WDL <511>) By communicating, a data line driver number 2 (420) is transferred to a. Number 1 a data line driver (420) the number 1 of a global input/output line (GIO <0>, GIO <1>, GIO <2>,..., GIO <511>) Through bank 0 (400) or bank 1 (401) is connected to selected banks is activated, e.g. bank 0 (400) of 512 memory cells stores the data write. Number 2 a data line driver (422) the number 2 of a global input/output line (GIO <0>, GIO <1>, GIO <2>,..., GIO <511>) Through bank 2 (402) or bank 3 (403) is connected to selected banks is activated, e.g. bank 2 (402) of 512 memory cells stores the data write Chip selection signal is enabled, 0 (450) port even write operation write buffers number 1 and a (430) a write data input during n periods of a clock are bank 0 (400) or bank 1 (401) stored access to memory cells of a during, port 1 (452) and a write buffers number 2 (432) a write data are input during n periods of a bank are 2 (402) or bank 3 (403) to memory cells of a stored at accessed and, the present embodiment the first deoxygenator stacked bank 0 (400) and bank 1 (401), and bank 2 (402) and a bank 3 (403) independently of each other accessed and multi-port memory device (40) for writing data of. device for warning the overturn of speed. One shown in the present invention refers to drawing in the embodiment described with reference to a an exemplary and a slant which purpose: to avoid a, knowledge usual the art with various modifications therefrom grow for other and equalization embodiment styles are discussed that will understand. The present invention refers to 4 ports and 2 of the two stacks of multi-port memory banks device 2 in the bank of the two stacks data line sense amplifier 2 and a data line driver 2 and 4 respectively connected to sides of the read buffers 4 and 4 between the write buffers, read data line and number 1 and number 2 number 1 and number 2 write data line but described for, e.g., of 4 banks of the two stacks 4 ports and multi-port memory device 4 in the bank of the two stacks data line sense amplifier 4 and a data line driver 4 and 4 respectively connected to sides of the read buffers 4 between the write buffers and 4, number 1 to number 4 read data lines and number 1 to number 4 write data lines is the decoration plate further comprises an. Therefore, the scope of protection of the present invention technical true claimed registration in a manner where the idea range is decided by the will should be. The above-mentioned device according to multi-port memory of the present invention, plurality of stack accessed and independently of each other bank independently reading and writing operation in are connected to the switching circuit, a decimator is provided to convert data throughput data read speed and is speed is improved due to the data write. The device has a set of stacked banks, each bank includes a set of memory cells. Data line sense amplifiers (410, 412) are respectively coupled between the stacked banks and a set of buffers. The amplifiers sense data that is read from memory cells of selected banks. A set of read data lines respectively couple the amplifiers to the buffers. The read data lines simultaneously transmit data from the amplifiers to the buffers. An independent claim is also included for a method of operating stacked banks of multi-port memory device. Plurality of ports; Plurality of memory cells are one or more bank 2 are one data line sense amplifier banks share a plurality of stack; Each said stack banks, read buffers to sense is connected between, said stack bank selected said of said banks in said data memory cells own one data line sense amplifier are said sensing; Each said ports and and being linked with each other, said data line sense amplifier read from the memory cell of the bank selected in the ports, which outputs to the read buffers to sense said; and Each said data line sense amplifier and each said read buffers the part interconnects between read data to composition characterized by multi-port memory device. According to Claim 1, said data line sense amplifier are Said selected said of said banks in bank stack said sensing data read in parallel from memory cells to characterized by multi-port memory device. According to Claim 1, said read buffers to sense the Said data line sense amplifier read from the ports said memory cell data for a power-supply compensation in series with characterized by multi-port memory device. Plurality of ports; Plurality of memory cells are one or more bank 2 are one data line driver shared a plurality of stack banks; Each said ports and, said is in the write buffers storing write data; Said banks, each said stack is connected between write buffers, said stack bank within said memory cells selected said of said banks for driving write data said said data line drivers; A data line driver and each said each said write buffers the part interconnects between write data to composition characterized by multi-port memory device. According to Claim 4, said write buffers Through said data inputted in Serial write data in parallel converted to characterized by a multi-port memory device. According to Claim 4, said data line drivers Said stack bank within said memory cells selected said of said banks said write data in parallel drive a characterized by multi-port memory device. Bi-directional input/output a plurality of ports; Plurality of memory cells are one or more bank 2 are one data line sense amplifier and one data line driver shared a plurality of stack banks; Each said stack banks, read buffers to sense is connected between, said stack bank selected said of said banks in said data memory cells own one data line sense amplifier are said sensing; Each said stack banks and write buffers is connected between, said selected within bank stack said said of said banks for driving write data memory cells said data line drivers; Each said ports and and being linked with each other, said data line sense amplifier read from the memory cell of the bank selected in the ports, which outputs to the read buffers to sense; Each said ports and, said is in the write buffers storing write data; Each said data line sense amplifier and each said read buffers the part interconnects between read data lines; and A data line driver and each said each said write buffers the part interconnects between write data to composition characterized by multi-port memory device. According to Claim 7, said data line sense amplifier are Bank stack said selected said of said banks in said data read in parallel from memory cells sensing characterized by a multi-port memory device. According to Claim 7, said read buffers to sense the Said data line sense amplifier read from the ports said memory cell data for a power-supply compensation in series with characterized by multi-port memory device. According to Claim 7, said write buffers Through said data inputted in Serial write data in parallel converted to characterized by a multi-port memory device. According to Claim 7, said data line drivers Said stack bank within said memory cells selected said of said banks said write data in parallel drive a characterized by multi-port memory device. Bi-directional input/output a plurality of ports; Plurality of memory cells are one or more bank 2 are one data line sense amplifier and one data line driver shared a plurality of stack banks; Each said stack banks, read buffers to sense is connected between, said stack bank selected said of said banks in said data read in parallel from memory cells said data line sense amplifier are sensing; Each said stack banks and write buffers is connected between, said selected said of said banks bank stack within said memory cells write data in parallel that of the display unit driven by said data line drivers; Each said ports and and being linked with each other, said data line sense amplifier read from the parallel memory cell of the bank selected in the a output in series with the ports said read buffers to sense; Each said ports and, through said data inputted in Serial write data in parallel converted to a write buffers; Each said data line sense amplifier and each said read buffers the part interconnects between read data lines; and A data line driver and each said each said write buffers the part interconnects between write data to composition characterized by multi-port memory device.