СПОСОБ ИЗГОТОВЛЕНИЯ НЕСУЩЕГО ЭЛЕМЕНТА ДЛЯ ПОЛУПРОВОДНИКОВЫХ ЧИПОВ

Изобретение относится к области крепления на твердом теле полупроводниковых приборов и может быть использовано для крепления полупроводниковых чипов на несущем элементе. Несущий элемент для полупроводникового чипа (23), в частности, для монтажа в чип-карте содержит подложку (15), несущую чип (23), и пленку (10) жесткости, ламинированную на несущую чип (23) сторону подложки (15), имеющую выемку (14), размещающую чип (23) и его выводы (24), край которой снабжен рамкой (12), выполненной за одно целое с пленкой (10). Техническим результатом изобретения является упрощение способа изготовления несущего элемента для полупроводниковых чипов. 7 з.п. ф-лы, 5 ил.

СПОСОБ ВСТРАИВАНИЯ КОМПОНЕНТА В ОСНОВАНИЕ

Изобретение относится к способу, согласно которому полупроводниковые компоненты, образующие часть электронной схемы, или по меньшей мере некоторые из таких компонентов, встраивают в основание, например, в печатную плату в процессе ее изготовления. Технический результат - создание способа, посредством которого бескорпусные микросхемы могут быть встроены в основание надежным, но экономичным образом. Достигается тем, что в основании выполняют сквозные отверстия для полупроводниковых компонентов, причем отверстия проходят между первой и второй поверхностями основания. После выполнения отверстий на вторую поверхность структуры основания наносят полимерную пленку, причем полимерная пленка закрывает сквозные отверстия для полупроводниковых компонентов со стороны второй поверхности структуры основания. Перед отверждением полимерной пленки или после ее частичного отверждения в отверстия вводят полупроводниковые компоненты со стороны первой поверхности. Полупроводниковые компоненты прижимают к полимерной ...

МНОГОКРИСТАЛЬНЫЙ КОРПУС И СПОСОБ ПРЕДОСТАВЛЕНИЯ В НЕМ ВЗАИМНЫХ СОЕДИНЕНИЙ МЕЖДУ КРИСТАЛЛАМИ

Изобретение относится к микроэлектронике, к структурам взаимного соединения в многокристальных корпусах. Сущность изобретения: многокристальный корпус включает в себя подложку, имеющую первую сторону, противоположную вторую сторону и третью сторону, которая продолжается от первой стороны до второй стороны, первый кристалл, закрепленный на первой стороне подложки, и второй кристалл, также закрепленный на первой стороне подложки, и мост, расположенный рядом с третьей стороной подложки и соединенный с первым кристаллом и со вторым кристаллом. Никакой из участков подложки не находится под мостом. Мост формирует соединение между первым кристаллом и вторым кристаллом. В качестве альтернативы мост может быть расположен в полости на подложке или между подложкой и слоем кристалла. Мост может составлять активный кристалл и может быть закреплен на подложке с использованием проводных соединений. Изобретение позволяет получить структуры взаимных соединений между кристаллами в корпусах с большой плотностью ...

КОНСТРУКТИВНЫЙ ЭЛЕМЕНТ

... 1. Конструктивный элемент, в частности полупроводниковый компонент, содержащий первую микросхему (10), размещенную на второй микросхеме (20), в котором первая и вторая микросхемы (10, 20) имеют соответственно на одной из своих основных поверхностей (13, 23) первую, соответственно, вторую металлизации (12, 22), которые обращены одна к другой, при этом первые участки металлизаций (12, 22) предусмотрены для выполнения электрического соединения между первой и второй микросхемами (10, 20), а вторые участки металлизации (12, 22) предусмотрены как дополнительная электрическая функциональная поверхность вне первой и второй микросхем (10, 20). 2. Конструктивный элемент по п. 1, отличающийся тем, что первая и/или вторая металлизация (12, 22) через контактные элементы (14, 24) соединены с контактными площадками (11, 21), расположенными в верхнем слое металлизации. 3. Конструктивный элемент по п.1 или 2, отличающийся тем, что первая или вторая микросхема (10, 20) в местах, в которых противолежащая ...

СПОСОБ ЗАЩИТЫ ОТ ЭЛЕКТРОСТАТИЧЕСКОГО РАЗРЯДА В УСТРОЙСТВЕ ТРЕХМЕРНОЙ (3-D) МНОГОУРОВНЕВОЙ ИНТЕГРАЛЬНОЙ СХЕМЫ, УСТРОЙСТВО (3-D) МНОГОУРОВНЕВОЙ ИНТЕГРАЛЬНОЙ СХЕМЫ И СПОСОБ ЕГО ИЗГОТОВЛЕНИЯ

Изобретение относится к системам и способам для обеспечения защиты от электростатического разряда в трехмерных многоуровневых интегральных схемах. Сущность изобретения: устройство трехмерной (3-D) многоуровневой интегральной схемы содержит первый и второй полупроводниковые кристаллы, наложенные друг на друга, множество сквозных переходных отверстий, сформированных, чтобы проходить, по существу, между активными слоями первого и второго полупроводниковых кристаллов, и выполненных с возможностью обеспечения связи между первым и вторым полупроводниковыми кристаллами, и активную схему, сформированную, по меньшей мере, частично внутри, по меньшей мере, одного из множества сквозных переходных отверстий, причем первый и второй полупроводниковые кристаллы совместно используют активную схему, по меньшей мере, для защиты от электростатического разряда. Изобретение позволяет осуществить экономию пространства и сократить площадь кристалла, требуемую для схемы ESD-защиты. 3 н. и 8 з.п. ф-лы, 12 ил.

ВЕРТИКАЛЬНЫЕ ЭЛЕКТРИЧЕСКИЕ СОЕДИНЕНИЯ В СТОПЕ СЛОЕВ

... 1. Устройство памяти и/или обработки данных, содержащее, по меньшей мере, два слоя (L), образующие стопу (1), представляющую собой отдельную структуру или расположенную на подложке (2) и содержащую, по меньшей мере, одну структуру, сдвинутую, по меньшей мере, в одном направлении, в результате чего в сдвинутой структуре сформированы ступени, образованные открытыми частями отдельных слоев (L) в стопе (1), причем высота (h) ступени определяется толщиной соответствующего слоя, отличающееся тем, что на каждой ступени сдвинутой структуры образованы одна или более контактных площадок (4), электрически соединенных с контурами памяти и/или обработки данных в соответствующем слое (L); поверх ступени в каждом слое (L) сформированы одно или более краевых соединений (3) в виде электропроводных структур, нанесенных над указанной ступенью и за ее кромкой между ступенями в каждом слое (L) на поверхности этого слоя, причем электрические краевые соединения (3) находятся в контакте с одной или более контактными ...

Hybridisierungsofen für die Verbindung von Bauelementen mittels eines schmelzbares Materials

Halbleiterbauelement

Laterales Leistungs-MOSFET mit einer Metallschicht zur Verminderung des verteilten Widerstandes und Verfahren zur Herstellung

Halbleiteranordnung mit Metallplatte

Einkapselungsverfahren

Verfahren zum Einkapseln eines Halbleiterbauelements, mit den folgenden Schritten: Bereitstellen eines Systemträgers (12), der eine erste Chippadzone und eine zweite Chippadzone aufweist, wobei jede Chippadzone eine erste Seite (60, 62) und eine zweite Seite (70, 72) aufweist, wobei die erste Chippadzone relativ zu der zweiten Chippadzone in der Höhe versetzt ist und wobei die erste Chippadzone und die zweite Chippadzone zusammenhängend sind; Befestigen eines ersten Chips (16) an der ersten Seite (62) der ersten Chippadzone; Befestigen eines zweiten Chips (14) an der ersten Seite (60) der zweiten Chippadzone; Drahtbonden von Drähten an den ersten und zweiten Chip (16, 14); Anordnen eines Gussrahmens gegenüber dem Systemträger (12), um eine Lücke zwischen den zweiten Seiten (72, 70) der ersten und der zweiten Chippadzonen und einer Oberfläche des Gussrahmens zu bilden; und Einkapseln mit einem den ersten Chip (16) und den zweiten Chip (14) überdeckenden Einkapselungsmaterial, das in die ...

Modular aufgebautes Leistungshalbleitermodul

Die Erfindung beschreibt ein modular aufgebautes Leistungshalbleitermodul (1) zur Montage auf einem Kühlkörper. Dieses Modul besteht aus einer Mehrzahl von Teilmodulen (10), welche ihrerseits aus einer Grundplatte (20) sowie einem rahmenartigen Gehäuse (30) und Anschlusselementen (40) für Last- (42) und Hilfsanschlüsse (44) bestehen. Die einzelnen Teilmodule werden mittels eines die Teilmodule gegeneinander fixierenden Deckels (70) und/oder mittels die einzelnen Teilmodule fixierender Verbindungen (34, 36) zu einem gesamten Leistungshalbleitermodul angeordnet.

VERFAHREN ZUR HERSTELLUNG EINER METALLISIERUNG AUF EINEM SUBSTRAT

Gestapelte Mehrchip-Module und Verfahren zur Herstellung

Verbesserte Mehrschichtverpackung

Verpackung für elektronische Komponenten

Halbleiteranordnung mit Versorgungsbusleitungen

Von der Peripherie-unabhängiges präzises Positionsglied für einen Halbleiterchip und Herstellungsverfahren dafür

KLEBSTOFFPASTE WELCHE EIN POLYMERES HARZ ENTHÄLT

VERFAHREN ZUR HERSTELLUNG EINER HALBLEITER-BAUGRUPPE MIT EINEM AUSSENANSCHLUSSTEIL

Verfahren zur Herstellung einer Halbleitervorrichtung mit einem keramischen Substrat und einem integrierten Schaltungskreis

Verfahren zur Herstellung einer elektrischen Verbindung für eine integrierte Schaltung.

Packung für elektronische Schaltung

Mounting for at least one semiconductor component

The invention relates to a low-capacitance mounting, in particular for lossy semiconductor components, for example IMPATT diodes, which can be manufactured inexpensively. This is achieved with the aid of a diamond body (heat sink) having a trench-like recess containing the connected semiconductor component.

Verfahren zum Herstellen einer harzumhüllte Halbleiteranordnung

Leiterplatte für Plastikhalbleitergehäuse

Methode zur Verminderung der gegenseitigen Induktanz zwischen Verbindungsdrähten einer Hochfrequenzverstärkerschaltung

Chip-size package production

Production of a semiconductor chip-size housing (CSP) involves (a) bonding conductive wires (45) onto bond pads on a chip (41); (b) placing the chip in an electrolysis cell (55) such that the wire ends are outside the electrolyte solution (50) of the cell; (c) fitting an electroplating electrode (60) on an inner wall of the cell; (d) placing a conductive plate (65) as common electrode on the exposed wire ends; and (e) connecting the conductive plate (65) and the outer wall of the cell (55) to a current source (70). Preferably, the wires (45) consist of gold, the conductive plate (65) consists of copper and the electroplating electrode (60) consists of nickel or gold.

Bond wire clamping and/or motion unit for semiconductor module

The unit includes a clamp (1) with axially protruding jaws (3) and a hollow base body (2). The unit is fitted to a bonding head of a wire bonding set. The jaws (3) are joined by solid hinges (6). A bonding wire (5) is led through the surrounding clamp. The clamp actuation is carried out by piezoelectric or electromagnetic force transmission in the elastic region. The clamp is movable in the longitudinal direction of the bonding wire.

Verfahren zur Bildung einer Drahtbondelektrode auf einer Dickschichtleiterplatte

Verfahren zum Herstellen einer Drahtbondelektrode auf einer Dickschichtleiterplatte, bei welcher eine Kupfer-Dickschicht (2) als Verdrahtungsschicht auf einem isolierenden Substrat (1) gebildet ist und ein auf dem isolierenden Substrat angebrachtes Teil (7) elektrisch mit der Kupfer-Dickschicht (2) über einen Golddraht (8) verbunden ist, mit: einem Schritt des Druckens der Kupfer-Dickschicht (2) auf das isolierende Substrat und des Sinterns der Kupfer-Dickschicht zur Bildung der Verdrahtungsschicht; und einem Schritt des Druckens einer Gold-Dickschicht, welcher vor dem Drucken Kupfer hinzugefügt worden ist, auf das isolierende Substrat und des Sinterns der Gold-Dickschicht als Drahtbondelektrode, um wenigstens partiell die Kupfer-Dickschicht zu überlappen, welche auf dem isolierenden Substrat gebildet ist.

Herstellungsverfahren von einer Mehrschichtleiterbahn-Struktur über einer Halbleiteranordung

In ein Gehaeuse eingebauter Hochleistungsgleichrichter

Verfahren zum Herstellen eines Kontakts auf einem Halbleiterbauelement

Haft-Klebemittel-Zusammensetzung für Halbleiter.

Chip size semiconductor component

The semiconductor chip (21) carries several beads (22) bonded to the inner ends of the conductive wires (16), in a vertical manner. The entire chip is embedded in synthetic resin (23) such that the outer ends of the conductive wires protrude outwards. Preferably the inner end of the bonded wires, in contact with the chip beads, are shaped as irregular, oval; bonding spheres (25). Typically the outer ends of the protruding conductive vires are bent, directed against the middle of the chip, such as to form L-shaped external conductors.

Contactless chip card manufacturing method

The manufacturing method has a conductive adhesive (9) applied via a dosing device to the surface of an antenna contact surface (20) incorporated in the card body, for securing a chip module contact surface, the height of the applied conductive adhesive measured via an electrode (35) displaced perpendicular to the chip card surface, with a voltage applied across the antenna contact surface and the measuring electrode, for providing a voltage discharge in the gas-filled space between the measuring electrode and the deposited conductive adhesive. An Independent claim for a device for a manufacture of chip cards is also provided.

LOTTRAEGER, VERFAHREN ZU DESSEN HERSTELLUNG UND VERFAHREN ZUR MONTAGE VON HALBLEITERANORDNUNGEN UNTER DESSEN VERWENDUNG

Chip structure for stress-prone chips especially for sensor chips mounted on wiring carrier, provides mechanical or acoustic coupling of chip for bonding process

A chip structure for stress-prone chips has a inter-space between the chip (1) and the connecting carrier (4) at least partly temporarily filled with an adhesive material with reducible adhesion properties or reducible contact surface, so that at least at times a mechanical or acoustic coupling of the chip (1) suitable for a bonding process, is ensured on the wiring carrier (4) and that the chip is fixed over the wiring carrier (4) and is electrically joined to the latter.

Wire bonding method for semiconductor device manufacture

The method involves using a capillary driven by a wire bonding apparatus, the capillary having an opening. A distal end of a bonding wire which enters a bonding circuit through the capillary is ultrasonically bonded. The opening forms a substantial part of a nail head bonding point during nail-head bonding.

VERFAHREN ZUM HERSTELLEN EINES THERMOKOMPRESSIONSKONTAKTES

Verfahren zur Herstellung einer Halbleiter-anordnung

HALBLEITERANORDNUNG UND VERFAHREN ZU IHRER HERSTELLUNG

LEISTUNGSTHYRISTOR AUF EINEM SUBSTRAT

Halbleitervorrichtung, Substrat zum Herstellen einer Halbleitervorrichtung und Verfahren zum Herstellen derselben

Halbleitervorrichtung, umfassend: eine Chipkontaktstelle; ein Halbleiterelement, das auf die Chipkontaktstelle geladen ist, das Elektroden aufweist; eine Mehrzahl von elektrisch leitfähigen bzw. leitenden Abschnitten, die um die Chipkontaktstelle angeordnet sind; Drähte zum Verbinden der Elektroden des Halbleiterelements und der elektrisch leitfähigen Abschnitte; und ein Dichtharz zum Dichten von wenigstens dem Halbleiterelement, den elektrisch leitfähigen Abschnitten und Drähten; wobei jeder der elektrisch leitfähigen Abschnitte eine Metallfolie enthält, wobei den elektrisch leitfähigen Abschnitt plattierende Schichten bzw. Lagen sowohl am oberen als auch unteren Ende der Metallfolie zur Verfügung gestellt sind; wobei die Chipkontaktstelle eine Chipkontaktstellen-Plattierschicht beinhaltet, die in derselben Ebene wie untere, den elektrisch leitfähigen Abschnitt plattierende Schichten der elektrisch leitfähigen Abschnitte vorgesehen ist; und wobei die unteren, den elektrisch leitfähigen ...

IC-Baugruppe und Verfahren zur Herstellung einer IC-Baugruppe

IC-Baugruppe bzw. integrierter Schaltungsbaustein, umfassend: eine integrierte Schaltung mit einer Oberfläche bzw. -fläche, die wenigstens teilweise von einer Metallschicht bedeckt ist; wenigstens einen Verbindungspunkt; wenigstens einen Verbinder, der die integrierte Schaltung mit dem oder jedem Verbindungspunkt elektrisch verbindet; ein Verkapselungsmaterial, das den oder jeden Verbinder, wenigstens einen Teil der integrierten Schaltung und wenigstens einen Teil des oder jedes Verbindungspunktes derart verkapselt, dass eine Kontaktoberfläche bzw. -fläche des oder jedes Verbindungspunktes und die Metallschicht auf der integrierten Schaltung außerhalb des Verkapselungsmaterials freiliegen.

Anschlussrahmen für Harz-Halbleiterverpackungen

Bonddraht für Halbleitervorrichtung

Bonddraht für eine Halbleitervorrichtung, wobei der Bonddraht aufweist:ein Cu-Legierungskernmaterial; undeine auf einer Oberfläche des Cu-Legierungskernmaterials gebildete Pd-Überzugschicht, wobeibei Messung von Kristallorientierungen auf einem Querschnitt des Kernmaterials in senkrechter Richtung zu einer Drahtachse des Bonddrahts eine Kristallorientierung <100> im Winkel von höchstens 15 Grad zu einer Drahtachsenrichtung einen Anteil von mindestens 30 % unter Kristallorientierungen in Drahtachsenrichtung hat,eine mittlere Kristallkorngröße im Querschnitt des Kernmaterials in senkrechter Richtung zur Drahtachse des Bonddrahts 0,9 µm oder mehr und 1,5 µm oder weniger beträgt, undder Bonddraht ein oder mehrere Elemente enthält, die aus Ga und Ge ausgewählt sind, und eine Konzentration der Elemente insgesamt 0,011 bis 1,5 Masse-% relativ zum gesamten Draht beträgt.

ELEKTRONISCHE INTEGRIERTE SCHALTUNG MIT MINDESTENS EINEM ELEKTRONISCHEN BAUELEMENT

Bondhügellose Aufbauschicht- und Laminatkernhybridstrukturen und Verfahren für ihre Montage

Eine Struktur enthält ein Hybridsubstrat zum Stützen eines Halbleiterbauelements, das eine bondhügellose Aufbauschicht, in die das Halbleiterbauelement eingebettet ist, und eine Laminatkernstruktur enthält. Die bondhügellose Aufbauschicht und die Laminatkernstruktur werden durch eine Verstärkungsplattierung, die mit einem plattierten Durchgangsloch in der Laminatkernstruktur und einer anschließenden Bondinsel der bondhügellosen Aufbauschichtstruktur verbunden ist, zu einer integralen Vorrichtung gemacht.

Elektrischer Schaltungsapparat

Compensating circular lamination for power semiconductor modules

Use is made in power semiconductor modules of compensating circular laminations which absorb thermal stresses due to unequal coefficients of expansion of silicon semiconductor chips and metal parts connected thereto, e.g. copper connecting parts or copper/ceramic substrates. The compensating circular laminations are intended, moreover, to exhibit good electrical and thermal conductivity. The object of the invention is to specify a compensating circular lamination which by comparison with known compensating circular laminations leads to a reduction in the thermal stresses occurring during operation. This object is achieved by means of a compensating circular lamination in which a powdery mixture of different materials, e.g. molybdenum and copper, is sintered to produce a moulded part, the concentration of the powder components used varying by location. The circular lamination exhibits a high molybdenum concentration, e.g. on the side facing a silicon chip, and a high copper fraction on the ...

VERFAHREN UND APPARAT ZUM PACKEN INTEGRIERTER SCHALTUNGSCHIPS MIT EINER POLYMERFILM-BEDECKUNGSSCHICHT.

Mehrchip-Halbleitermodul und Herstellungsverfahren dafür

Ein Mehrchip-Halbleitermodul weist auf: ein Chipmontageteil mit einem ersten und zweiten Substrat, wobei das erste Substrat hat: eine entgegengesetzte erste und zweite Oberfläche, mehrere erste leitende Kontaktlöcher, die sich durch die erste und zweite Oberfläche erstrecken, und eine erste Schaltungsanordnung, die auf der zweiten Oberfläche strukturiert und mit den ersten leitenden Kontaktlöchern elektrisch verbunden ist, wobei das zweite Substrat hat: eine entgegengesetzte erste und zweite Oberfläche, mehrere zweite leitende Kontaktlöcher, die sich durch die erste und zweite Oberfläche des zweiten Substrats erstrecken, eine zweite Schaltungsanordnung, die auf der zweiten Oberfläche des zweiten Substrats strukturiert und mit den zweiten leitenden Kontaktlöchern elektrisch verbunden ist, und eine darin ausgebildete erste Chipaufnahmeöffnung, wobei die erste Oberfläche des zweiten Substrats auf der zweiten Oberfläche des ersten Substrats verbunden ist, so daß die zweite Schaltungsanordnung ...

Verpackungsstruktur für elektronische Bauteile und Methode zu deren Herstellung

Verfahren zum Herstellen einer Halbleiteranordnung.

Masterslice-Halbleiteranordnung und Verfahren zu ihrer Herstellung

Druckkontaktanordnung sowie deren Verwendung

Wiring substrate for pressure sensors, acceleration sensors and ultrasonic sensors, comprises electrode cushion pad, which is arranged in opening, formed in protection insulation film

The wiring substrate has a wiring layer (15) formed on the surface of a silicon substrate (11), another wiring layer (16) formed on the surface of the former wiring layer. A protection insulation film (14) is so formed that it covers the latter wiring layer. An opening (14a) is formed in the protection insulation film, and an electrode cushion pad is arranged in the opening. The opening in the protection insulation film and the former wiring layer are formed at such positions that they do not overlap each other toward the card thickness of the substrate.

Vorrichtung und Verfahren zum Verbinden von Komponenten

Vorrichtung zum Verbinden von mindestens zwei Komponenten, wobei die Vorrichtung ein Ober- (96) und ein Unterwerkzeug (95) aufweist, wobei das Unterwerkzeug (95) die mindestens zwei Komponenten (3, 2, 21, 22, 23, 1, 11, 12, 13) umfasst, wobei eine erste Komponente (3) die mindestens eine zweite Komponente (2, 21, 22, 23, 1, 11, 12, 13) mit einem zumindest teilweisen Überlapp relativ zur ersten Komponente (3) trägt; das Unterwerkzeug (95) und das Oberwerkzeug (96) relativ zueinander bewegt werden können; das Oberwerkzeug (96) mindestens zwei heizbare Stempel (7, 8, 15, 16, 71, 72, 81, 82, 83) umfasst, die so verbunden sind, dass sie sich relativ zueinander über ein abgedichtetes Druckkissen (5) bewegen können; wobei die Stempel (7, 8, 15, 16, 71, 72, 81, 82, 83) und das Druckkissen (5) zwischen sich eine erste flexible Schicht (6) aufweisen; dadurch gekennzeichnet, dass zwischen dem Oberwerkzeug (96) und dem Unterwerkzeug...

Electronic component used as a semiconductor wafer comprises a semiconductor chip having contact surfaces of an integrated circuit on its active surface, and a bimetallic strip arranged on the contact surfaces

Electronic component comprises: a semiconductor chip (2) having contact surfaces (4) of an integrated circuit on its active surface (3); and a bimetallic strip (5) arranged on the contact surfaces and having a fixed end (6) connected to the contact surface and a flexible free end (7) protruding from the active surface of the chip. Preferred Features: An angled bimetallic strip is arranged on the contact surfaces. The free end of the bimetallic strip has a coating made from gold or a gold alloy, or silver alloy. The bimetallic strip is made from a copper alloy and an aluminum alloy.

Verdrahtungssubstrat

Ein Verdrahtungssubstrat umfasst ein Substrat mit einem Verdrahtungsmuster und ein linienförmiges Isoliermuster, das auf dem Substrat derart gebildet ist, daß es das Verdrahtungsmuster schneidet und einen Teil des Verdrahtungsmusters für eine Anschlußbereichselektrode definiert. Das Isoliermuster umfasst eine Mehrzahl von linienförmigen Abschnitten, die miteinander verbunden sind, um eine rahmenartige Struktur zu bilden.

Halbleitervorrichtung mit Wärmeabstrahlplatte und Anheftteil

Eine Halbleitervorrichtung mit: einem Wärmeerzeugungselement (10), das durch einen IGBT bereitgestellt wird; einem Anheftteil (50); ersten und zweiten Wärmeabstrahlplatten (20, 30), welche auf ersten und zweiten Seiten (12, 13) des Wärmeerzeugungselementes (10) entsprechend über das Anheftteil (50) angeordnet sind; einem Wärmeabstrahlblock (40), der zwischen der ersten Wärmeabstrahlplatte (30) und dem Wärmeerzeugungselement (10) über das Anheftteil (50) angeordnet ist; und einem Kunstharzverguss (60), der praktisch die gesamte Vorrichtung eingießt, wobei die ersten und zweiten Wärmeabstrahlplatten (20, 30) in der Lage sind, von dem Wärmeerzeugungselement (10) erzeugte Wärme abzustrahlen; das Wärmeerzeugungselement (10) elektrisch und thermisch mit der ersten Wärmeabstrahlplatte (30) über das Anheftteil (50) und den Wärmeabstrahlblock (40) verbunden ist; das Wärmeerzeugungselement (10) elektrisch und thermisch mit der zweiten Wärmeabstrahlplatte (20) über das Anheftteil (50) verbunden ist ...

Semiconductor power module with excess current protection unit has fuse unit surrounded by explosion protection material connected across conductive tracks by narrower leads than power semiconductor

A semiconductor power module (1) with an excess current protection unit comprises a housing with external load connections (42, 44, 46) and a substrate with mutually insulated metallic connection tracks of different polarity, at least one with a semiconductor power element (70, 72) with a connection of given cross-section. A fuse unit comprises a second connection element of smaller lead cross-section between two tracks or a track and a load connection and this unit is encased in a section of explosion-protecting material.

Halbleiterchip, Halbleiterbauteil und Verfahren zu deren Herstellung

Halbleiterchip (1) mit einer haftvermittlungsschichtfreien Dreischichtmetallisierung (2) bestehend aus einer Aluminiumschicht (4), die direkt auf dem Halbleiterchip (1) aufgebracht ist, einer Diffusionssperrschicht (5), die direkt auf der Aluminiumschicht (4) aufgebracht ist, einer Lotschicht (6), die direkt auf die Diffusionssperrschicht (5) aufgebracht ist, wobei, die Diffusionssperrschicht (5) Ti, Ni, Pt oder Cr ist, und die Lotschicht (6) eine Diffusionslotschicht ist, die AuSn, AgSn oder CuSn aufweist, und wobei der Halbleiterchip (1) eine aktive Oberseite (16) und eine passive Rückseite (3) aufweist, und wobei alle drei Schichten in einer Prozessabfolge auf der passiven Rückseite (3) aufgesputtert sind.

Halbleiterbauelement mit Verbindungselementen und Verfahren zur Herstellung desselben

Halbleiterbauelement mit Verbindungselementen (6) zur Herstellung einer Verbindung zwischen einem Halbleiterchip (7) aus einem Halbleiterwafer (8) mit diskreten Halbleiterbauelementen (1 bis 5) und einem übergeordneten Schaltungsträger, wobei das Halbleiterbauelement (1 bis 5) eine koplanare Fläche (9) aus Oberseiten (10) der Verbindungselemente (6) und einer Kunststoffmasse (11) aufweist, und wobei das Verbindungselement (6) eine Mesastruktur (12) oder eine Pilzform (13) für eine Oberflächenmontage aufweist und ein Lotdepot in Form einer strukturierten bleifreien Kontaktbeschichtung (14) umfasst, wobei die Verbindungselemente (6) auf Kontaktflächen (15) der Halbleiterchips (7) angeordnet sind, die flächige Erstreckung der Verbindungselemente (6) den Kontaktflächen (15) des Halbleiterchips (7) entsprechen und alle Verbindungselemente (6) auf einer aktiven Oberseite des Halbleiterchips (7) angeordnet sind.

Parallelchip-Eingebettete gedruckte Schaltungsplatine und Herstellungsverfahren dafür

Eine Parallelchip-eingebettete Schaltungsplatine und ein Herstellungsverfahren dafür sind offenbart. Mit einem Verfahren zum Herstellen einer Parallelchip-eingebetteten, gedruckten Schaltungsplatine, welches umfasst: a) Bilden eines Parallelchips durch ein Verbinden einer Mehrzahl von Einheitschips, die Elektroden oder elektrisch verbundene Elemente aufweisen, die auf den oberen und unteren Flächen davon gebildet sind, parallel unter Verwendung von zumindest einem leitfähigen Element; (b) Verbinden einer Elektrode auf einer Seite des Parallelchips mit einer ersten Platine; und (c) Verbinden einer Elektrode auf der anderen Seite des Parallelchips mit einer zweiten Platine, können Chips in einer Schaltungsplatine zu geringe Kosten eingebettet werden, da eine Mehrzahl von Einheitschips auf einmal eingebettet und ein mechanischer Bohrer oder Fräser anstelle eines Laserbohrers beim Ausstanzen der Kavität oder von Durchlöchern verwendet werden kann.

Verfahren zum Herstellen von Leitungsverbindungen an elektronischen schaltelementen

Electronic power package for e.g. diode, has two non-planar insulating substrates connected in connection regions, so that mechanical separation between substrates is controlled by number, arrangement, design and material of regions

The package (100) has two non-planar insulating substrates (1, 2) with high thermal conductivity. Electronic components e.g. semiconductor power transistor chip (20) and diode chip (30), are attached on each of the substrates. The substrates are connected with each other in connection regions, so that a mechanical separation between the substrates is controlled by the number of connection regions, an arrangement of connection regions, and design and material of the connection regions. The mechanical separation supplies an axially directed net compression force into the electronic components.

Halbleiterbauelement mit einer verstärkten Substruktur einer Kontaktstelle und zugehöriges Herstellungsverfahren

Halbleiterbauelement mit einer verstärkten Substruktur einer Kontaktstelle, mit - einem Halbleitersubstrat (200), - einer auf dem Halbleitersubstrat ausgebildeten Substruktur (205), - einer dielektrischen Zwischenebenenschicht (208) auf der Substruktur, wobei die dielektrische Zwischenebenenschicht eine darin ausgebildete Kontaktöffnung (210) beinhaltet, und - einem Kontaktstift (214), der in der Kontaktöffnung ausgebildet ist, dadurch gekennzeichnet, dass - die Kontaktöffnung (210) aus einer Mehrzahl von separaten Punkten gebildet ist, die miteinander verbunden werden.

Strukturiertes Halbleiterelement zur Reduzierung von Chargingeffekten

Die vorliegende Erfindung bezieht sich auf ein Halbleiterschaltungselement (1) zur Reduzierung von unerwünschten Aufladeeffekten, insbesondere Anschlusselement von Teststrukturen für Halbleiterschaltungen, wobei die Oberfläche (4) des Halbleiterschaltungselements (1) elektrisch von der Rest-Oberfläche (5) des Halbleiterschaltungselements (1) isolierte Leitbahnstrukturen (3) aufweist, und bei dem ausschließlich die Leitbahnstrukturen (3) an nachgeordnete Halbleiterschaltungselemente (8) angeschlossen sind.

Elektronisches Bauelement und Verfahren zur Herstellung eines elektronischen Bauelements

Es handelt sich um ein elektronisches Bauelement (100a, 100b, 200), insbesondere ein optoelektronisches Bauelement. Das elektronische Bauelement weist ein Substrat (124, 224) mit mindestens einer Halbleiterchip-Kontaktschicht (110a, 110b, 210) auf. Auf der Halbleiterchip-Kontaktschicht (110a, 110b, 210) ist ein Halbleiterchip (102, 202) angeordnet. Zwischen der Halbleiterchip-Kontaktschicht (110a, 110b, 210) und einer dem Substrat (124, 224) zugewandten Kontaktfläche (104, 204) des Halbleiterchips (102, 202) ist eine Poren aufweisende Verbindungsschicht (106, 206) angeordnet.

Elektronische Vorrichtung und Verfahren zu deren Fertigung

Eine elektronische Vorrichtung weist ein Leistungselement (30) auf einem ersten Substrat (10) und eine elektronische Komponente (40) auf einem zweiten Substrat (20) auf. Das erste und das zweite Substrat (10, 20) sind derart übereinander angeordnet, dass das Leistungselement (30) und die elektronische Komponente (40) zwischen dem ersten und dem zweiten Substrat (10, 20) angeordnet werden können. Ein erstes Ende eines ersten Drahtes (50) ist mit dem Leistungselement (30) verbunden. Ein zweites Ende des ersten Drahtes (50) ist mit dem ersten Substrat (10) verbunden. Ein mittlerer Abschnitt des ersten Drahtes (50) ragt in Richtung des zweiten Substrats (20). Ein erstes Ende eines zweiten Drahtes (60) ist mit dem Leistungselement (30) verbunden. Ein zweites Ende des Drahtes (60) erstreckt sich über eine Oberseite (51) des mittleren Abschnitts des ersten leitfähigen Elements (50) und ist mit dem zweiten Substrat (20) verbunden.

Druckkontakt-Halbleiterbauelement mit Blindsegment

Jedes der äußersten Segmente (OMSG) und der innersten Segmente (IMSG) wird als Blindsegment verwendet. Eine obere Oberfläche eines vorstehenden Teils (OMPP, IMPP) jedes der äußersten Segmente (OMSG) und der innersten Segmente (IMSG) ist mit einer Isolierschicht (1S + 1P) bedeckt, und zwischen einer oberen Oberfläche der Isolierschicht (1S + 1P) und einer unteren Oberfläche (2BS) einer Katodenentlastungsplatte ist ein Abstand (CL) vorhanden. Alle anderen Segmente (SG), mit Ausnahme der äußersten und der innersten, besitzen einen vorstehenden Teil, auf dem eine Katodenelektrode (1K-AL) ausgebildet ist. Die Dicke (T1) der Katodenelektrode (1K-AL) ist so bemessen, dass eine obere Oberfläche der Katodenelektrode (1K-AL) mit der unteren Oberfläche (2BS) der Katodenentlastungsplatte in Kontakt kommen kann.

Verfahren zum Herstellen von strukturierten Sinterschichten und Halbleiterbauelement mit strukturierter Sinterschicht

Die Erfindung betrifft ein Verfahren zum Herstellestrukturiertes Aufbringens einer Vielzahl von Sinterelementen (22a, 22b, 22c) aus einem die Sinterschicht ausbildenden Ausgangsmaterial auf einer Kontaktfläche (21) einer Hauptoberfläche (11a) eines Substrats (11), des Anordnens eines mit dem Substrat zu verbindenden Chips auf den Sinterelementen (22a, 22b, 22c), und des Erhitzens und Komprimierens der Sinterelemente (22a, 22b, 22c) zum Herstellen einer das Substrat und den Chip verbindenden strukturierten Sinterschicht, welche sich innerhalb der Kontaktfläche (21) erstreckt, wobei die Flächenbelegungsdichte der Sinterelemente (22a, 22b, 22c) auf dem Substrat (11) in einem Mittelbereich (21a) der Kontaktfläche größer ist als die Flächenbelegungsdichte der Sinterelemente in einem Randbereich (21c) der Kontaktfläche, und wobei von jedem der Sinterelemente (22a, 22b, 22c) mindestens ein lateral zur Hauptoberfläche des Substrats verlaufender Durchgangskanal (23) zum Rand der Kontaktfläche (21 ...

Targetted passivation of conductive track intermediate space or track regions on circuit board by applying conductive adhesive in region of tracks formed

The method involves applying a passivation substance (2) to the intermediate spaces between conductive tracks, and then applying a conductive adhesive (3) in the region of the conductive tracks formed. The application of passivation substance involves the application of a passivation mask. An Independent claim is also included for a dispenser device for targetted passivation.

Sinterwerkstoff, Sinterverbindung sowie Verfahren zum Herstellen eines Sinterverbindung

Die Erfindung betrifft einen Sinterwerkstoff mit metallischen, mit einer organischen Beschichtung versehenen Strukturpartikeln. Erfindungsgemäß ist vorgesehen, dass nicht-organisch beschichtete, metallische und/oder keramische, beim Sinterprozess nicht ausgasende Hilfspartikel (7) vorgesehen sind. Ferner betrifft die Erfindung eine Sinterverbindung (1) sowie ein Verfahren zum Herstellen einer Sinterverbindung (1).

Bondkopf für dicken Draht

Ultraschall-Drahtbonder, welcher umfasst: einen Bondkopf (10), welcher so verbunden ist, dass er in der Z-Achse über einem elektrischen oder elektronischen Bauteil, an das ein Draht gebondet werden soll, bewegbar ist; einen Ultraschall-Transducer (72) mit einem mit ihm verbundenen Bondwerkzeug (278) zum Bonden eines Drahtes; und eine flexible Halterung zur Halterung des Bondwerkzeugs (278), welche von mindestens einem bogenförmigen Arm (106, 108, 110, 124, 126, 128) gebildet ist, der mit dem Bondwerkzeug (278) so verbunden ist, dass das Bondwerkzeug (278) in Richtung der Z-Achse flexibel bewegbar ist.

Schichtbauelement-Herstellungsverfahren

Schichtbauelement-Herstellungsverfahren zur Herstellung eines Schichtbauelements unter Verwendung eines verstärkten Wafers (20), bei dem der verstärkte Wafer (20) durch auf einer vorderen Oberfläche (20a) in einem Gittermuster angeordnete Straßen (21) in mehrere Bereiche unterteilt ist und einen mit Bauelementen (22) in den so abgeteilten Bereichen ausgebildeten Bauelementbereich (23) und einen äußeren Umfangsüberschussbereich (24), der den Bauelementbereich (23) umgibt, beinhaltet, ein Bereich einer hinteren Oberfläche (20b), der dem Bauelementbereich (23) entspricht, so geschliffen wird, dass der Bauelementbereich (23) so ausgebildet werden kann, dass er eine vorgegebene Dicke aufweist, und ein Bereich, der dem äußeren Umfangsüberschussbereich (24) entspricht, belassen werden kann, um einen ringförmigen verstärkten Abschnitt (24b) zu bilden, wobei das Verfahren umfasst:einen Waferschichtungsschritt, bei dem ein unten liegender Wafer (200), der einen Durchmesser aufweist, der geringfügig ...

Integrated circuit manufacturing method of chip scale package, involves attaching solder balls in area that is uncovered by resist element, of patterned rewriting element, in patterned form

Integrated circuit (14) is mounted upside down on carrier (10), such that connection element (15) contacts with insulator (17), through the hole of carrier. Patterned rewriting elements (18, 19) attached in insulator, are internally connected by patterned solder resist element (20). Solder balls (22) are attached in area that is uncovered by resist element, of rewriting element, in patterned form. An Independent claim is also included for integrated circuit.

Direkt auf ungehäusten Bauelementen erzeugte freitragende Kontaktierstrukturen

Direkt auf einem ungehäusten Bauelement wird eine freitragende Kontaktierstruktur erzeugt, indem eine Schicht aus isolierendem Material und eine Schicht aus elektrisch leitendem Material auf das Bauelement sowie einen Träger aufgebracht und vom Träger wieder abgelöst werden.

Elektronisches Bauteil mit Halbleiterchip und Halbleiterwafer mit Kontaktflecken, sowie Verfahren zur Herstellung derselben

Die Erfindung betrifft ein elektronisches Bauteil mit Halbleiterchips (1) und einen Halbleiterwafer mit Kontaktflecken (2) sowie Verfahren zur Herstellung derselben. Dazu weisen die Kontaktflecken (2) auf dem Halbleiterchip (1) Mesastrukturen (6) auf, die derart dimensioniert sind, dass sie an die Größen von Kompressionsköpfen (7) von Bondverbindungen (4) angepasst sind und eine druckverteilende Wirkung auf die Oberseite (10) der Kontaktflecken (2) ausüben.

Halbleiterpackung und -modul, Herstellungsverfahren und elektronisches Bauelement

Die Erfindung bezieht sich auf eine Halbleiterpackung mit gestapelten Halbleiterchips, auf ein Halbleitermodul mit einer derartigen Packung, auf ein Verfahren zur Herstellung der Halbleiterpackung sowie auf ein elektronisches Bauelement, das ein derartiges Modul beinhaltet. Eine Halbleiterpackung gemäß der Erfindung beinhaltet ein Packungssubstrat (200) mit einem Durchkontakt (220s), wenigstens einen Halbleiterchip (100, 120), der auf dem Packungssubstrat gestapelt ist, einen thermischen Grenzflächenfilm (132), der auf dem Halbleiterchip gestapelt ist, eine Packungsabdeckung (300), die in Kontakt mit dem thermischen Grenzflächenfilm und über dem Halbleiterchip positioniert ist, und eine Packungshaftstruktur (310) zwischen dem Durchkontakt und einem Teil der Packungsabdeckung. Verwendung in der Halbleiterbauelementtechnologie.

Verfahren zum elektrischen Verbinden eines Kontaktfeldes eines Halbleiterchips mit zumindest einer Kontaktfläche sowie danach hergestellte Chipkarte

Vorrichtung zum Anschweissen von duennen Draehten an Halbleiterbauteile mit Hilfe der Pressschweissung (Kalt- und Warmschweissung), mit einer Zufuhr fuer den Draht an einem den Pressdruck auf den Draht uebertragenden Schweisskopf

VERFAHREN ZUR HERSTELLUNG UND ZUM TRANSFERIEREN METALLISCHER TROPFEN

Leiterplatte mit primären und sekundären Durchgangslöchern

Leiterplatte mit primären und sekundären Durchgangslöchern

VERFAHREN ZUR HERSTELLUNG EINER HALBLEITERVORRICHTUNG

Packung für Mikrowellenschaltung

Elektrode zum anodischen Bonden

Verfahren und Vorrichtung zur "Flip-Chip" Montage eines elektronischen Bauteils

Halbleiterschaltung

Verfahren zur Kontaktierung und Verbindung von Halbleiterelementen

Anordnung einer Mehrzahl von Schaltungsmodulen

Zur zuverlässigen und gleichwohl einfachen Verschaltung übereinander angeordneter Schaltungsmodule (2) wird bei einer entsprechenden Anordnung (1) vorgeschlagen, eine elektrische Verbindung verschiedener Verbindungseinrichtungen (5) der übereinander angeordneten Schaltungsmodule (2) jeweils durch direkten mechanischen und elektrischen Kontakt zwischen Verbindungselementen (6) verschiedener Verbindungseinrichtungen (5) auszubilden.

Active energy ray-curable pressure-sensitive adhesive for re-release and dicing die-bonding film

Provided is an active energy ray-curable pressure-sensitive adhesive for re-release, which has a small influence on an environment or a human body, can be easily handled, can largely change its pressure-sensitive adhesiveness before and after irradiation with an active energy ray, and can express high pressure-sensitive adhesiveness before the irradiation with the active energy ray and express high releasability after the irradiation with the active energy ray. The active energy ray-curable pressure-sensitive adhesive for re-release includes an active energy ray-curable polymer (P), in which the polymer (P) includes one of a polymer obtained by causing a carboxyl group-containing polymer (P3) and an oxazoline group-containing monomer (m3) to react with each other, and a polymer obtained by causing an oxazoline group-containing polymer (P4) and a carboxyl group-containing monomer (m2) to react with each other.

Wiring board and method for manufacturing the same

A wiring board including a first insulation layer, a conductive pattern formed on the first insulation layer, a second insulation layer formed on the conductive pattern and the first insulation layer and having an opening portion exposing at least a portion of the conductive pattern, and a connection conductor formed in the opening portion of the second insulation layer such that the connection conductor is positioned on the portion of the conductive pattern. The connection conductor has a tip portion which protrudes from a surface of the second insulation layer and which has a tapered side surface tapering toward an end of the tip portion.

Semiconductor device

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Microelectronic packages with dual or multiple-etched flip-chip connectors

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Semiconductor device and package

A semiconductor device includes a semiconductor substrate having an upper surface, a lower surface, a first side and a second side, wherein the lower surface has a slope so that the first side is thicker than the second side, and a circuit pattern including a bonding pad on the upper surface of the semiconductor substrate.

Power semiconductor module and fabrication method

A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.

Interconnections for flip-chip using lead-free solders and having reaction barrier layers

An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components. With a two-layer ball-limiting composition comprising an adhesion/reaction barrier layer, wherein the adhesion/reaction barrier layer serves both as an adhesion layer and a reaction barrier layer, the adhesion/reaction barrier layer can be comprised of a material selected from the group consisting of Zr and ZrN

Semiconductor-encapsulating adhesive, semiconductor-encapsulating film-form adhesive, method for producing semiconductor device, and semiconductor device

The present invention relates to a semiconductor-encapsulating adhesive, a semiconductor-encapsulating film-form adhesive, a method for producing a semiconductor device, and a semiconductor device. The present invention provides a semiconductor-encapsulating adhesive comprising (a) an epoxy resin, and (b) a compound formed of an organic acid reactive with an epoxy resin and a curing accelerator.

Stacked microelectronic packages having at least two stacked microelectronic elements adjacent one another

A microelectronic assembly includes first and second microelectronic elements. Each of the microelectronic elements has oppositely-facing first and second surfaces and edges bounding the surfaces. The first microelectronic element is disposed on the second microelectronic element with the second surface of the first microelectronic element facing toward the first surface of the second microelectronic element. The first microelectronic element preferably extends beyond at least one edge of the second microelectronic element and the second microelectronic element preferably extends beyond at least one edge of the first microelectronic element. A first edge of the first microelectronic element has a length that is smaller than a first edge of the second microelectronic element. A second edge of the first microelectronic element has a length that is greater than the second edge of the second microelectronic element.

Methods of forming semiconductor elements using micro-abrasive particle stream

A method of fabricating a microelectronic unit includes providing a semiconductor element having a front surface and a rear surface remote from the front surface, forming at least one first opening extending from the rear surface partially through the semiconductor element towards the front surface by directing a jet of fine abrasive particles towards the semiconductor element, and forming at least one conductive contact and at least one conductive interconnect coupled thereto. The semiconductor element can include a plurality of active semiconductor devices therein. The semiconductor element can include a plurality of conductive pads exposed at the front surface. Each conductive interconnect can extend within one or more of the first openings and can be coupled directly or indirectly to at least one of the conductive pads. Each of the conductive contacts can be exposed at the rear surface of the semiconductor element for electrical connection to an external device.

Film for flip chip type semiconductor back surface, dicing tape-integrated film for semiconductor back surface, process for producing semiconductor device, and flip chip type semiconductor device

The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, in which the film for flip chip type semiconductor back surface before thermal curing has, at the thermal curing thereof, a volume contraction ratio within a range of 23° C. to 165° C. of 100 ppm/° C. to 400 ppm/° C.

Semiconductor device and method for producing such a device

A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.

Semiconductor device and method of manufacturing the same

A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL 1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1 S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL 2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL 2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

Semiconductor device

There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.

Capillary and ultrasonic transducer for ultrasonic bonding

A capillary is attached to an ultrasonic transducer of a wire-bonding apparatus. The capillary includes a first part configured to be attached to the ultrasonic transducer, and a second part other than the first part and extending from the first part. The first part has a shape different from a shape of the second part so that the first part has a flexure rigidity larger than the second part.

Packaging Integrated Circuits

An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.

Mechanisms for forming copper pillar bumps using patterned anodes

The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.

Process for assembling two parts of a circuit

A three-dimensional integrated structure is fabricated by assembling at least two parts together, wherein each part contains at least one metallic line covered with a covering region and having a free side. A cavity is formed in the covering region of each part, that cavity opening onto the metallic line. The two parts are joined together with the free sides facing each other and the cavities in each covering region aligned with each other. The metallic lines are then electrically joined to each other through an electromigration of the metal within at least one of the metallic lines, the electromigrated material filling the aligned cavities.

Multi-chip package with offset die stacking

A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed.

Power Semiconductor Chip Package

A device includes a vertical power semiconductor chip having an epitaxial layer and a bulk semiconductor layer. A first contact pad is arranged on a first main face of the power semiconductor chip and a second contact pad is arranged on a second main face of the power semiconductor chip opposite to the first main face. The device further comprises an electrically conducting carrier attached to the second contact pad.

Semiconductor device and manufacturing method of the same

A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.

Semiconductor chip device with polymeric filler trench

A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package

A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate.

Method of manufacture of integrated circuit packaging system with stacked integrated circuit

A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.

Anti-tamper microchip package based on thermal nanofluids or fluids

A tamper-resistant microchip package contains fluid- or nanofluid-filled capsules, channels, or reservoirs, wherein the fluids, either alone or in combination, can destroy circuitry by etching, sintering, or thermally destructing when reverse engineering of the device is attempted. The fluids are released when the fluid-filled cavities are cut away for detailed inspection of the microchip. Nanofluids may be used for the sintering process, and also to increase the thermal conductivity of the fluid for die thermal management. Through-vias and micro vias may be incorporated into the design to increase circuitry destruction efficacy by improving fluid/chip contact. Thermal interface materials may also be utilized to facilitate chip cooling.

Multi-function and shielded 3d interconnects

A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element.

Semiconductor device and manufacturing method thereof

Semiconductor devices of embodiments include a plurality of solder bumps electrically connected on a plurality of electrode pads disposed on a semiconductor substrate in parallel at a pitch of 40 μm or less via under bump metals. The ratio of the diameter (the top diameter) of the portion of each solder bump most away from the semiconductor substrate and the diameter (the bottom diameter) of the bottom side of each solder bump is 1:1 to 1:4.

Method of making a light emitting device having a molded encapsulant

Disclosed herein is a method of making a light emitting device having an LED die and a molded encapsulant made by polymerizing at least two polymerizable compositions. The method includes: (a) providing an LED package having an LED die disposed in a reflecting cup, the reflecting cup filled with a first polymerizable composition such that the LED die is encapsulated; (b) providing a mold having a cavity filled with a second polymerizable composition; (c) contacting the first and second polymerizable compositions; (d) polymerizing the first and second polymerizable compositions to form first and second polymerized compositions, respectively, wherein the first and second polymerized compositions are bonded together; and (e) optionally separating the mold from the second polymerized composition. Light emitting devices prepared according to the method are also described.

Semiconductor module including a switch and non-central diode

A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.

Semiconductor structure and method for making same

One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.

Off-chip vias in stacked chips

A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.

Semiconductor die package including low stress configuration

A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.

Wiring board and method for manufacturing the same

A wiring board including a core substrate having an accommodation portion, an electronic component in the accommodation portion having a substrate, a resin layer on a surface of the substrate and an electrode on the resin layer, a first interlayer resin insulation layer on a surface of the core substrate and a surface of the substrate of the component, and a second interlayer resin insulation layer on the opposite surface of the core substrate and a surface of the substrate having the resin layer and electrode. The first insulation layer has resin in the amount greater than the amount of resin in the second insulation layer such that the total amount of resin component including the resin in the first insulation layer is adjusted to be substantially the same as the total amount of resin component including the resin in the second insulation layer and resin in the resin layer.

Electrode connection method, electrode connection structure, conductive adhesive used therefor, and electronic device

By connecting together connecting electrodes having an organic film serving as an oxidation-preventing film using a conductive adhesive, the manufacturing process can be simplified, and a highly reliable connection structure can be constructed at low cost. An electrode connection method, in which a first connecting electrode 2 and a second connecting electrode 10 are connected together through a conductive adhesive 9 that is interposed between the electrodes, includes an organic film formation step in which an organic film 6 is formed on at least a surface of the first connecting electrode, and an electrode connection step in which the first connecting electrode and the second connecting electrode are connected together through the conductive adhesive. In the electrode connection step, by allowing an organic film decomposing component mixed in the conductive adhesive to act on the organic film, the organic film is decomposed, and thus connection between the connecting electrodes is performed.

Composite alloy bonding wire and manufacturing method thereof

A manufacturing method for a composite alloy bonding wire and products thereof. A primary material of Ag is melted in a vacuum melting furnace, and then a secondary metal material of Pd is added into the vacuum melting furnace and is co-melted with the primary material to obtain an Ag—Pd alloy solution. The obtained Ag—Pd alloy solution is drawn to obtain an Ag—Pd alloy wire. The Ag—Pd alloy wire is then drawn to obtain an Ag—Pd alloy bonding wire with a predetermined diameter.

Power/ground layout for chips

Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

Semiconductor package and manufacturing method thereof

There are provided a semiconductor package including an electromagnetic shielding structure having excellent electromagnetic interference (EMI) and electromagnetic susceptibility (EMS) characteristics, while protecting individual elements in an inner portion thereof from impacts, and a manufacturing method thereof. The semiconductor package includes: a substrate having ground electrodes formed on an upper surface thereof; at least one electronic component mounted on the upper surface of the substrate; an insulating molding part including an internal space in which the electronic component is accommodated, and fixed to the substrate such that at least a portion of the ground electrode is externally exposed; and a conductive shield part closely adhered to the molding part to cover an outer surface of the molding part and electrically connected to the externally exposed ground electrodes.

Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product

A leadframe package includes a die pad with four unitary, outwardly extending slender bars; a plurality of leads arranged along periphery of the die pad; a separate pad segment separated from the die pad and isolated from the plurality of leads; a semiconductor die mounted on an upper side of the die pad, wherein the semiconductor die contains first bond pads wire-bonded to respective the plurality of leads and a second bond pad wire-bonded to the separate pad segment; and a molding compound encapsulating the semiconductor die, the upper side of the die pad, the first suspended pad segment and inner portions of the plurality of leads.

Chip-on-chip structure and manufacturing method therof

According to an embodiment, a chip-on-chip structure includes a first chip, a second chip, the first chip and the second chip being opposite to each other, a first electrode terminal, a second electrode terminal, a bump and a protecting material. The first electrode terminal is provided on the surface of the first chip at the side of the second chip. The second electrode terminal is provided on the surface of the second chip at the side of the first chip. The bump electrically connects the first electrode terminal and the second electrode terminal. The protecting material is formed around the bump between the first chip and the second chip. The protecting material includes a layer made of a material having heat-sensitive adhesive property.

Semiconductor module

A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.

Electronic element unit and reinforcing adhesive agent

It is an object of the present invention to provide an electronic element unit and a reinforcing adhesive agent in which a bonding strength can be improved between an electronic element and a circuit board and a repairing work can be carried out without giving a thermal damage to the electronic element or the circuit board. In an electronic element unit ( 1 ) including an electronic element ( 2 ) having a plurality of connecting terminals ( 12 ) on a lower surface thereof, a circuit board ( 3 ) having a plurality of electrodes ( 22 ) corresponding to the connecting terminals ( 12 ) on an upper surface thereof. The connecting terminals ( 12 ) and the electrodes ( 22 ) are connected by solder bumps ( 23 ), and the electronic element ( 2 ) and the circuit board ( 3 ) are partly bond by a resin bond part ( 24 ) made of a thermosetting material of a thermosetting resin, and a metal powder ( 25 ) is included in the resin bond parts ( 24 ) in a dispersed state. The metal powder ( 25 ) has a melting point lower than a temperature at which the resin bond parts ( 24 ) are heated when a work (a repairing work) is carried out for removing the electronic element ( 2 ) from the circuit board ( 3 ).

Semiconductor Device and Method of Forming Prefabricated EMI Shielding Frame with Cavities Containing Penetrable Material Over Semiconductor Die

A semiconductor device has a plurality of semiconductor die mounted to a temporary carrier. A prefabricated shielding frame has a plate and integrated bodies extending from the plate. The bodies define a plurality of cavities in the shielding frame. A penetrable material is deposited in the cavities of the shielding frame. The shielding frame is mounted over the semiconductor die such that the penetrable material encapsulates the die. The carrier is removed. An interconnect structure is formed over the die, shielding frame, and penetrable material. The bodies of the shielding frame are electrically connected through the interconnect structure to a ground point. The shielding frame is singulated through the bodies or through the plate and penetrable material to separate the die. TIM is formed over the die adjacent to the plate of the shielding frame. A heat sink is mounted over the plate of the shielding frame.

Method for manufacturing a semiconductor device having a refractory metal containing film

A semiconductor device and a method for manufacturing the same of the present invention in which the semiconductor device is provided with a fuse structure or an electrode pad structure, suppress the copper blowing-out from a copper containing metal film. The semiconductor device comprises a silicon substrate, SiO 2 film provided on the silicon substrate, copper films embedded in the SiO 2 film, TiN films covering an upper face of a boundary region between an upper face of copper films and the copper films, and the SiO 2 film, and SiON films covering an upper face of the TiN films.

Semiconductor Device And Method Of Manufacturing Semiconductor Device

A semiconductor chip includes a magnetic storage device and includes an electrode pad on a first face. The semiconductor chip is coated with a magnetic shield layer in a state in which at least the electrode pad is exposed. The semiconductor chip is mounted on an interconnect substrate through a bump. At least one of the semiconductor chip and the interconnect substrate includes a convex portion, and the bump is disposed over the convex portion.

Electric part package and manufacturing method thereof

A disclosed electric part package includes a supporting member that includes a first area in which an electric part is arranged, and a second area in which a first opening is positioned, the second area being isolated from the first area; a resin part provided on the supporting member thereby to cover the electric part arranged in the first area, the resin part including an electric terminal exposed in the first opening of the supporting member; and a wiring structure provided on the resin part, the wiring structure being electrically connected to the electric part and the electric terminal of the resin part.

Connecting and Bonding Adjacent Layers with Nanostructures

An apparatus, comprising two conductive surfaces or layers and a nanostructure assembly bonded to the two conductive surfaces or layers to create electrical or thermal connections between the two conductive surfaces or layers, and a method of making same.

Copper conductor film and manufacturing method thereof, conductive substrate and manufacturing method thereof, copper conductor wiring and manufacturing method thereof, and treatment solution

Provided are a copper conductor film and manufacturing method thereof, and patterned copper conductor wiring, which have superior conductivity and wiring pattern formation, and with which there is no decrease in insulation between circuits, even at narrow wiring widths and narrow inter-wiring spacing. Disclosed are a copper conductor film and manufacturing method thereof in which a copper-based particle-containing layer, which contains both a metal having catalytic activity toward a reducing agent and copper oxide, is treated using a treatment solution that contains a reagent that ionizes or complexes copper oxide and a reducing agent that reduces copper ions or copper complex to form metallic copper in a single solution, and patterned copper conductor wiring that is obtained by patterning a copper-based particle-containing layer using printing and by said patterned particle-containing layer being treated by a treatment method using a solution that contains both a reagent that ionizes or complexes copper oxide and a reducing agent that reduces copper ions or copper complexes to form metallic copper in a single solution.

Structures and methods for improving solder bump connections in semiconductor devices

Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.

Semiconductor device

The semiconductor device has the CSP structure, and includes: a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps are arranged in two rows along the periphery of the semiconductor device. The electrode pads are arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring is extended from an electrode pad, and is connected to any one of the outermost solder bumps or any one of the inner solder bumps.

Semiconductor Device

The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

Semiconductor component, semiconductor wafer component, manufacturing method of semiconductor component, and manufacturing method of joining structure

A semiconductor component of the present invention includes a semiconductor element and a joining layer formed on one surface of the semiconductor element and consisting of a joining material containing Bi as an essential ingredient, and projecting sections are formed on a surface of the joining layer on a side opposite to a surface in contact with the semiconductor element. By joining the semiconductor component to an electrode arranged so as to face the joining layer, the generation of a void can be suppressed.

Semiconductor package and manufacturing method therefor

According to one embodiment, there is provided a semiconductor package including: a semiconductor chip; a resin portion formed to cover the semiconductor chip; a wiring structure formed on the resin portion and electrically connected to the semiconductor chip; and a warpage preventing member provided above the resin portion to have a thermal expansion coefficient closer to that of the semiconductor chip than to that of the wiring structure.

Chip Pad Resistant to Antenna Effect and Method

A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in forming the chip pad structure, electrical connections from the gate electrodes of MOS transistors in the IC substrate generally are made only to the ring pad portion that has an antenna-to-gate area ratio substantially below a predetermined antenna design rule ratio, and thus is resistant or immune to antenna effect. The main pad portion and the ring pad portion are coupled together through metal bridges formed in an upper interconnect metal layer or in the top conductive pad layer. The chip pad may be used as probe pads on a parametric testline or bonding pads on an IC.

Method of manufacturing semiconductor device including plural semiconductor chips stacked together

Such a method is disclosed that includes preparing first and second semiconductor chips, the first semiconductor chip including a first electrode formed on one surface thereof and a second electrode formed on the other surface thereof so as to overlap the first electrode as viewed from a stacking direction, and the second semiconductor chip including a third electrode formed on one surface thereof and a fourth electrode formed on the other surface thereof so as not to overlap the third electrode as viewed from the stacking direction, and stacking the first and second semiconductor chips in the stacking direction so that the second electrode is connected to the third electrode by using a bonding tool including a concave at a position corresponding to the fourth electrode.

Semiconductor device

A semiconductor device is configured that two or more semiconductor elements are stacked and mount on a lead frame, the aforementioned lead frame is electrically joined to the semiconductor element with a wire, and the semiconductor element, the wire and an electric junction are encapsulated with a cured product of an epoxy resin composition for encapsulating semiconductor device, and that the epoxy resin composition for encapsulating semiconductor device contains (A) an epoxy resin; (B) a curing agent; and (C) an inorganic filler, and that the (C) inorganic filler contains particles having particle diameter of equal to or smaller than two-thirds of a thinnest filled thickness at a rate of equal to or higher than 99.9% by mass.

Substrate bonding method and semiconductor device

A first Sn absorption layer is formed on a principal surface of a first substrate, the first Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A second Sn absorption layer is formed on a principal surface of a second substrate, the second Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A solder layer made of AuSn alloy is formed at least on one Sn absorption layer of the first and second Sn absorption layers. The first and second substrates are bonded together by melting the solder layer in a state that the first and second substrates are in contact with each other, with the principal surfaces of the first and second substrates facing each other.

Increasing Dielectric Strength by Optimizing Dummy Metal Distribution

A method includes providing a wafer representation including a metal layer and a plurality of bump pads over the metal layer, wherein the metal layer includes directly-under-bump-pad regions. A solid metal pattern is inserted into the metal layer, wherein the solid metal pattern includes first parts in the directly-under-bump-pad regions and second parts outside the directly-under-bump-pad regions. Portions of the second parts of the solid metal pattern are removed, wherein substantially no portions of the first parts of the solid metal pattern are removed. The remaining portions of the solid metal pattern not removed during the step of removing form dummy metal patterns. The dummy metal patterns and the plurality of bump pads are implemented in a semiconductor wafer.

Direct Edge Connection for Multi-Chip Integrated Circuits

The present invention allows for direct chip-to-chip connections using the shortest possible signal path.

Semiconductor Package with Embedded Die

A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.

Device mounting board and method of manufacturing the same, semiconductor module, and mobile device

A device mounting board includes: an insulating resin layer; a wiring layer formed on one of the principal surfaces of the insulating resin layer; a protection layer covering the insulating resin layer and the wiring layer; a protruding electrode electrically connected to the wiring layer, the protruding electrode protruding from the wiring layer toward the insulating resin layer and penetrating through the insulating resin layer; a wiring-layer-side convex portion protruding from the wiring layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer; and a resin-layer-side convex portion protruding from the protection layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer.

Chip package with plank stack of semiconductor dies

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier

A semiconductor device includes a first semiconductor die or component having a plurality of bumps, and a plurality of first and second contact pads. In one embodiment, the first and second contact pads include wettable contact pads. The bumps are mounted directly to a first surface of the first contact pads to align the first semiconductor die or component. An encapsulant is deposited over the first semiconductor die or component. An interconnect structure is formed over the encapsulant and is connected to a second surface of the first and second contact pads opposite the first surface of the first contact pads. A plurality of vias is formed through the encapsulant and extends to a first surface of the second contact pads. A conductive material is deposited in the vias to form a plurality of conductive vias that are aligned by the second contact pads to reduce interconnect pitch.

Semiconductor devices and methods of manufacturing semiconductor devices

Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed.

Heat radiation material, electronic device and method of manufacturing electronic device

The electronic device includes a heat generator 54, a heat radiator 58, and a heat radiation material 56 disposed between the heat generator 54 and the heat radiator 58 and including a plurality of linear structures 12 of carbon atoms and a filling layer 14 formed of a thermoplastic resin and disposed between the plurality of linear structures 12.

Electronic device and method for producing a device

An electronic device or devices and method for producing a device is disclosed. One embodiment provides an integrated component, a first package body and a contact device. The contact device penetrates the package body.

Manufacturing method of semiconductor device, and semiconductor device

To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, and a heat conductive member composed of a solder material. The heat conductive member covers the semiconductor element, and is connected to a connection pad formed on the substrate. A heat radiator is disposed on the heat conductive member. The heat conductive member thermally connecting the semiconductor element to the heat radiator reduces the risk that electromagnetic noise may be emitted from or may be incident on the semiconductor element.

Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereof

A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the first die through a die interconnect positioned between the first die and the second die; connecting a first lead adjacent the first die pad to the first die; connecting a second lead to the second die, the second lead opposing the first lead and adjacent the second die; and providing a molding material around the first die, the second die, the die interconnect, the first lead and the second lead, with a portion of the first lead exposed.

Optical Printed Circuit Board and Method of Fabricating the Same

Provided are a photovoltaic apparatus and a manufacturing method thereof. The photovoltaic apparatus includes: substrate; a back electrode layer disposed on the substrate; a plurality of first intermediate layers disposed on the back electrode layer; a plurality of second intermediate layers disposed on the back electrode layer and each disposed between the first intermediate layers; light absorbing layers disposed on the first intermediate layers and the second intermediate layers; and a front electrode layer disposed on the light absorbing layer.

Semiconductor device

A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.

Die attach film

Provided are a die attach film, a semiconductor wafer, and a semiconductor packaging method. The die attach film can prevent generation of burrs or scattering of chips in a dicing process, and exhibits excellent expandability and pick-up characteristics in a die pressure-sensitive adhesive process. Further, the die attach film can prevent release, shifting, or deflection of a chip in a wire pressure-sensitive adhesive or molding process. Thus, it is possible to improve embeddability, inhibit warpage of a wafer or wiring substrate, and enhance productivity in a semiconductor packaging process.

Three-dimensional system-in-a-package

A microelectronic assembly can include first, second and third stacked substantially planar elements, e.g., of dielectric or semiconductor material, and which may have a CTE of less than 10 ppm/° C. The assembly may be a microelectronic package and may incorporate active semiconductor devices in one, two or more of the first, second or third elements to function cooperatively as a system-in-a-package. In one example, an electrically conductive element having a minimum thickness less than 10 microns, may be formed by plating, and may electrically connect two or more of the first, second or third elements. The conductive element may entirely underlie a surface of another one of the substantially planar elements.

Circuit module and manufacturing method for the same

A circuit module and a manufacturing method for the same, reduce a possibility that a defect area where an electrically conductive resin is not coated may occur in a shield layer. A mother board is prepared. A plurality of electronic components are mounted on a principal surface of the mother board. An insulator layer is arranged so as to cover the principal surface of the mother board and the electronic components. The insulator layer is cut such that grooves and projections are formed in and on the principal surface of the insulator layer and the insulator layer has a predetermined thickness H. An electrically conductive resin is coated on the principal surface of the insulator layer to form a shield layer. The mother board including the insulator layer and the shield layer both formed thereon is divided to obtain a plurality of circuit modules.

Manufacturing method of semiconductor device

Performing electrolysis plating to a wiring is made possible, aiming at the increasing of pin count of a semiconductor device. Package substrate 3 by which ring shape common wiring 3 p for electric supply was formed in the inner area of bonding lead 3 j in device region 3 v of main surface 3 a is used. Since a plurality of first plating lines 3 r and fourth plating lines 3 u for electric supply connected to common wiring 3 p can be arranged by this, the feeder for electrolysis plating can be arranged to all the land parts on the back. Hereby, it becomes possible to perform electrolysis plating to the wiring of main surface 3 a of package substrate 3 , and the back surface.

Electronic device and manufacturing thereof

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Method for Making Solder-top Enhanced Semiconductor Device of Low Parasitic Packaging Impedance

A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

Methods and structures for forming integrated semiconductor structures

The invention provides methods and structures for fabricating a semiconductor structure and particularly for forming a semiconductor structure with improved planarity for achieving a bonded semiconductor structure comprising a processed semiconductor structure and a number of bonded semiconductor layers. Methods for forming semiconductor structures include forming a dielectric layer over a non-planar surface of a processed semiconductor structure, planarizing a surface of the dielectric layer on a side thereof opposite the processed semiconductor structure, and attaching a semiconductor structure to the planarized surface of the dielectric layer. Semiconductor structures include a dielectric layer overlaying a non-planar surface of a processed semiconductor structure, and a masking layer overlaying the dielectric layer on a side thereof opposite the processed semiconductor structure. The masking layer includes a plurality of mask openings over conductive regions of the non-planar surface of the processed semiconductor structure.

Distributed semiconductor device methods, apparatus, and systems

Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.

Semiconductor device and method of manufacturing the same

A method of manufacturing a semiconductor device, includes temporarily fixing a semiconductor chip to a supporting member to direct a connection electrode toward the supporting member side, forming an insulating layer for preventing resin-permeation covering the semiconductor chip, on the supporting member and the semiconductor chip, forming a resin substrate sealing a periphery and a back surface side of the semiconductor chip, on the insulating layer, and removing the supporting member to expose the connection electrode of the semiconductor chip. A build-up wiring is connected directly to the connection electrode of the semiconductor chip.

Impedence controlled packages with metal sheet or 2-layer rdl

A microelectronic assembly includes an interconnection element, a conductive plane, a microelectronic device, a plurality of traces, and first and second bond elements. The interconnection element includes a dielectric element, a plurality of element contacts, and at least one reference contact thereon. The microelectronic device includes a front surface with device contacts exposed thereat. The conductive plane overlies a portion of the front surface of the microelectronic device. Traces overlying a surface of the conductive plane are insulated therefrom and electrically connected with the element contacts. The traces also have substantial portions spaced a first height above and extending at least generally parallel to the conductive plane, such that a desired impedance is achieved for the traces. First bond element electrically connects the at least one conductive plane with the at least one reference contact. Second bond elements electrically connect device contacts with the traces.

Semiconductor package, electrical and electronic apparatus including the semiconductor package, and method of manufacturing the semiconductor package

In one embodiment, a semiconductor package may include a semiconductor chip having a chip pad formed on a first surface thereof, a sealing member for sealing the semiconductor chip and exposing the first surface of the semiconductor chip, a conductive wiring overlying a part of the first surface of the semiconductor chip and directly contacting a part of an upper surface of the sealing member. The conductive wiring further contacts the pad. The semiconductor package may also include an encapsulant covering the conductive wiring and having openings for exposing parts of the conductive wiring.

Method for producing reconstituted wafers and method for producing semiconductor devices

In order to provide a method for producing semiconductor devices that can use the highly productive W to W method, and achieve a high yield, a method for producing semiconductor devices comprises a step (S 401 ) in which a reconstituted wafer is prepared by replacing defective chips with non-defective chips, a step (S 403 ) in which the reconstituted wafer and the base wafer are connected to one another by laminating, a step (S 406 ) in which through-electrodes are formed in the reconstituted wafer, and a step (S 409 ) in which a separate reconstituted wafer is laminated onto and connected to the reconstituted wafer having through-electrodes.

Semiconductor module manufacturing method, semiconductor module, and manufacturing device

In the disclosed method for manufacturing a semiconductor module, a metal layer and a cooler, which have different coefficients of thermal expansion from each other, are joined into a single unit via an insulating resin sheet. A work, comprising a semiconductor element placed on the metal layer with solder interposed therebetween, is fed into a reflow furnace. The work, in that state, is heated in the reflow furnace, thereby mounting the semiconductor element to the metal layer. The heating is carried out such that the temperature of the cooler and the temperature of the metal layer differ by an amount that make the cooler and the metal layer undergo the same amount of thermal expansion as each other.

Module substrate, module-substrate manufacturing method, and terminal connection substrate

In a module substrate, a plurality of terminal connection substrates each including an insulator and a plurality of columnar terminal electrodes arranged on a single lateral surface or both lateral surfaces of the insulator is mounted on a single side of a composite substrate such that at least one of the terminal connection substrates extends over a border between a plurality of neighboring module substrates. The composite substrate, in which the plurality of terminal connection substrates is mounted on the single side and a plurality of electronic components is mounted on at least the single side, is divided at a location where the module substrates are to be cut from the composite substrate.

Semiconductor device package and method of manufacturing thereof

A semiconductor device package includes a semiconductor device having connection pads formed thereon, with the connection pads being formed on first and second surfaces of the semiconductor device with edges of the semiconductor device extending therebetween. A first passivation layer is applied on the semiconductor device and a base dielectric laminate is affixed to the first surface of the semiconductor device that has a thickness greater than that of the first passivation layer. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface and the edges of the semiconductor device, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads.

Fabrication method of semiconductor integrated circuit device

Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage.

Through wafer vias and method of making same

A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.

Semiconductor device and method for manufacturing same

A semiconductor device includes an interlayer insulating film, a wiring formed on the interlayer insulating film so as to protrude therefrom and made of a material having copper as a main component, and a passivation film formed so as to cover the wiring. The passivation film is made of a laminated film in which a first nitride film, an intermediate film, and a second nitride film are laminated in that order from the wiring side. The intermediate film is made of an insulating material (for example, an oxide) differing from those of the first and second nitride films.

Method for manufacturing a semiconductor device having a heat spreader

A semiconductor device manufacturing method includes cutting a resin sealing body into a plurality of pieces, the resin sealing body including a plurality of semiconductor chips mounted on a wiring board, a heat spreader disposed above the plurality of the semiconductor chips, and a sealing resin filled between the wiring board and the heat spreader, wherein the cutting the resin sealing body includes shaving the resin sealing body from a side of the heat spreader, and shaving the resin sealing body from a side of the wiring board, wherein the shaving the resin sealing body from the side of the wiring board is carried out after the shaving from the side of the heat spreader, and wherein the resin sealing body is completely cut off by the shaving from the side of the wiring board, and mounting a group of ball-like electrodes at a back side of the wiring board.

Semiconductor element-embedded substrate, and method of manufacturing the substrate

A semiconductor element-embedded substrate includes a semiconductor element; a chip component; a peripheral insulating layer covering at least the outer circumferential side surfaces thereof; an upper surface-side wiring line provided on the upper surface side of the substrate; and a lower surface-side wiring line provided on the lower surface side of the substrate. The built-in semiconductor element includes a terminal on the upper surface side thereof, and this terminal is electrically connected to the upper surface-side wiring line. The built-in chip component includes an upper surface-side terminal electrically connected to the upper surface-side wiring line; a lower surface-side terminal electrically connected to the lower surface-side wiring line; and a through-chip via penetrating through the chip component to connect the upper surface-side terminal and the lower surface-side terminal.

Semiconductor device

A semiconductor device which has a plurality of semiconductor chips stacked on a substrate. The semiconductor device includes semiconductor chip 2 , semiconductor chip 3 a stacked on substrate 4 together with semiconductor chip 2 , and having a foot print larger than semiconductor chip 2 , through electrode 22 extending through semiconductor chip 2 only in a central portion of semiconductor chip 2 , through electrode 32 extending through semiconductor chip 3 a at a position facing to through electrode 22 , and conduction bump 7 b arranged between through electrode 22 and through electrode 32 , and conductively connecting through electrode 22 with through electrode 32.

Three dimensional semiconductor assembly board with bump/flange supporting board, coreless build-up circuitry and built-in electronic device

A semiconductor assembly board includes a supporting board, a coreless build-up circuitry and a built-in electronic device. The supporting board includes a bump, a flange and a via hole in the bump. The built-in electronic device extends into the via hole and is electrically connected to the build-up circuitry. The build-up circuitry extends from the flange and the built-in electronic device and provides signal routing for the built-in electronic device. The supporting board provides mechanical support, ground/power plane and heat sink for the coreless build-up circuitry.

Semiconductor device and communication method

A semiconductor device, includes a substrate with a first surface, a semiconductor chip disposed over the first surface of the substrate, the semiconductor chip including a first region and a second region, and an encapsulant resin formed over the first surface of the substrate and encapsulating the semiconductor chip. The encapsulant resin has a thickness that is less at the first region of the semiconductor chip than that at the second region.

Method for manufacturing a circuit device

A semiconductor substrate and a copper sheet stacked with an insulating resin layer are bonded together at a temperature of 130° C. or below (first temperature) so that an element electrode provided on the semiconductor substrate connects to the copper sheet before a thinning process. Then the semiconductor substrate and the copper sheet, on which the insulating resin layer has been stacked, are press-bonded at a high temperature of 170° C. or above (second temperature) with the copper sheet thinned to thickness of a wiring layer. Then the wiring layer (rewiring) is formed by patterning the thinned copper sheet.

Die package including encapsulated die and method of manufacturing the same

Disclosed herein is a die package including an encapsulated die, including: a die including pads on one side thereof; an encapsulation layer covering lateral sides of the die; a support layer covering the encapsulation layer and one side of the die; a passivation layer formed on the other side of the die such that the pads are exposed therethrough; and a redistribution layer formed on the passivation layer such that one part thereof is connected with the pad. Here, since one side of the die is supported by the support layer and the encapsulation layer is formed on only the lateral side of the die, the warpage of the die package due to the difference in thermal expansion coefficient can be minimized

Electronic component and method for producing same

This electronic component is provided with an inorganic substrate, a conductor film formed on a surface of the substrate, and bonding wires bonded to a part of said conductor film, and wire bonding sections are formed on at least a part of the electronic component. The part of the conductor film at least forming the aforementioned wire bonding sections contains an Ag-based metal formed of Ag or an alloy having Ag as the main constituent and a metal oxide which coats said Ag-based metal and which has, as a constituent element, any of the elements selected from the group consisting of Al, Zr, Ti, Y, Ca, Mg, and Zn. The coating quantity of the metal oxide is a quantity corresponding to 0.02 to 0.1 parts by mass relative to 100 parts by mass of the aforementioned Ag-based metal.

Semiconductor device including cladded base plate

A semiconductor device includes a semiconductor chip coupled to a substrate and a base plate coupled to the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure.

Method for manufacturing semiconductor apparatus

A method for manufacturing a semiconductor apparatus includes: forming a protrusion made of a conductor on each of the electrodes provided on a semiconductor wafer top face side of a plurality of semiconductor devices formed in a semiconductor wafer; making a trench in the top face between the plurality of semiconductor devices; filling an insulator into a gap between the protrusions and into the trench to form a sealing member; grinding a bottom face of the semiconductor wafer opposing the top face until the sealing member being exposed to divide the semiconductor wafer into each of the semiconductor devices; forming a first lead made of a conductor on each of the protrusions, the first lead forming a portion of a first external electrode; and forming a conductive material layer directly to form a second lead on the bottom face of the plurality of semiconductor devices.

Multilayer adhesive sheet and method for manufacturing electronic component

Provided is a multilayer adhesive sheet which enables easy separation between an adhesive layer and a die attach film during the pick-up even in cases where an acrylate ester copolymer is used in the die attach film, thereby making the pick-up work of semiconductor chips after the dicing easy. The multilayer adhesive sheet comprises a base film, an adhesive layer that is disposed on one surface of the base film, and a die attach film that is disposed on an exposed surface of the adhesive layer. The adhesive that constitutes the adhesive layer contains: (A) a (meth)acrylate ester copolymer; (B) an ultraviolet polymerizable compound; (C) a multifunctional isocyanate curing agent; (D) a photopolymerization initiator; and (E) a silicone polymer.

Top-side Cooled Semiconductor Package with Stacked Interconnection Plates and Method

A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate. The stacked interconnection plate can be partially etched or three dimensionally formed to create the peripheral overhang.