material de interface térmica, e componente eletrônico

Metal-semiconductor contact structure with doped interlayer

Disclosed herein is a method of forming a metal-to-semiconductor contact with a doped metal oxide interlayer. An insulating layer is formed on a top surface of a semiconductor substrate with target region at the top surface of the semiconductor substrate. An opening is etched through the insulating layer with the opening exposing a top surface of a portion of the target region. A doped metal oxide interlayer is formed in the opening and contacts the top surface of the target region. The remainder of the opening is filled with a metal plug, the doped metal oxide interlayer disposed between the metal plug and the substrate. The doped metal oxide interlayer is formed from one of tin oxide, titanium oxide or zinc oxide and is doped with fluorine.

Multiple-chip package with multiple thermal interface materials

A multiple chip package is described with multiple thermal interface materials. In one example, a package has a substrate, a first semiconductor die coupled to the substrate, a second semiconductor die coupled to the substrate, a heat spreader coupled to the die, wherein the first die has a first distance to the heat spreader and the second die has a second distance to the heat spreader, a first filled thermal interface material (TIM) between the first die and the heat spreader to mechanically and thermally couple the heat spreader to the die, and a second filled TIM between the second die and the heat spreader to mechanically and thermally couple the heat spreader to the second die.

THIN FILM TRANSISTOR AND METHOD FOR MAKING THE SAME

The disclosure relates to a thin film transistor and a method for making the same. The thin film transistor includes a substrate; a gate located on the substrate; a dielectric layer located on the gate; a semiconductor layer located on the dielectric layer and including nano-scaled semiconductor materials; and a drain and a source spaced apart from each other and electrically connected to the semiconductor layer. The dielectric layer is an oxide layer formed by magnetron sputtering and in direct contact with the gate. The thin film transistor has inverse current hysteresis.

이방 도전성 필름용 조성물, 이방 도전성 필름 및 이를 이용한 접속 구조체

이방 도전성 필름용 조성물, 이방 도전성 필름 및 그것을 사용한 접속 구조체가 제공된다. 일 예에서, 이방 도전성 필름은, 바인더 수지, 지환족 에폭시 화합물 및 옥세탄 화합물을 포함하는 경화성 화합물, 4급 암모늄 화합물 촉매 및 도전 입자를 포함하고, 하기 식 1의 열시차주사열량계(DSC) 상 발열량 변화율이 15% 이하이다. [식 1] 발열량 변화율(%) = [(H 0 -H 1 )/H 0 ]×100 상기 식 1에서, H 0 는 이방 도전성 필름에 대해 40℃에서 24시간 보관하기 전에 25℃에서 측정한 열시차주사열량계(DSC) 상 발열량을 나타내고, H 1 은 상기 이방 도전성 필름을 40℃에서 24시간 보관 후 측정한 열시차주사열량계 상 발열량을 나타낸다. 지환족 에폭시 화합물 및 옥세탄 화합물을 경화성 화합물로 함께 사용하고, 나아가, 4급 암모늄 화합물 촉매를 사용하고 발열량 변화율을 위 범위 내로 함으로써 저온 속경화가 가능하며 보관 안정성 및 신뢰성이 우수한 이방 도전성 필름이 제공된다. A composition for anisotropic conductive film, an anisotropic conductive film and a connection structure using the same. In one example, the anisotropic conductive film comprises a curable compound containing a binder resin, an alicyclic epoxy compound, and an oxetane compound, a quaternary ammonium compound catalyst, and conductive particles, and has a thermal differential scanning calorimeter (DSC) The rate of change in calorific value is 15% or less. [Formula 1] Heating rate change rate (%) = [(H 0 -H 1 ) / H 0 ] × 100 In the above formula (1), H 0 represents the calorific value on the DSC of the anisotropic conductive film measured at 25 ° C before being stored at 40 ° C for 24 hours, H 1 represents the caloric value of the anisotropic conductive film at 24 ° C It shows the calorific value on the thermal differential scanning calorimetry measured after storage. An anisotropic conductive film excellent in storage stability and reliability can be obtained by using a cycloaliphatic epoxy compound and an oxetane compound together as a curing compound and further using a quaternary ammonium compound catalyst and setting a rate of change in calorific value within the upper range, do.

ENGINEERED POLYMER-BASED ELECTRONIC MATERIALS

HEAT INSULATING INTERCONNECT FEATURES IN A COMPONENT OF A COMPOSITE IC DEVICE STRUCTURE

A composite integrated circuit (IC) structure includes at least a first IC die in a stack with a second IC die. Each die has a device layer and metallization layers interconnected to transistors of the device layer and terminating at features. First features of the first IC die are primarily of a first composition with a first microstructure. Second features of the second IC die are primarily of a second composition or a second microstructure. A first one of the second features is in direct contact with one of the first features. The second composition has a thermal conductivity at least an order of magnitude lower than that of the first composition and first microstructure. The first composition may have a thermal conductivity at least 40 times that of the second composition or second microstructure.

THERMAL INTERFACE MATERIAL WITH ION SCAVENGER

A thermal interface material includes at least one polymer,at least one thermally conductive filler; and at least one ion scavenger. In some embodiments, the ion scavenger is a complexing agent selected from the group consisting of : nitrogen containing complexing agents,phosphorus containing complexing agents, and hydroxyl carboxylic acid based complexing agents.

이온 스캐빈저를 갖는 열 계면 재료

... 열 계면 재료는 적어도 1종의 폴리머, 적어도 1종의 열전도성 충전제; 및 적어도 1종의 이온 스캐빈저를 포함한다. 일부 실시양태들에서, 이온 스캐빈저는 질소 함유 착화제, 인 함유 착화제, 및 히드록실 카르복실산계 착화제로 이루어진 군에서 선택되는 착화제이다.

Metal-semiconductor contact structure with doped interlayer

Disclosed herein is a method of forming a metal-to-semiconductor contact with a doped metal oxide interlayer. An insulating layer is formed on a top surface of a semiconductor substrate with target region at the top surface of the semiconductor substrate. An opening is etched through the insulating layer with the opening exposing a top surface of a portion of the target region. A doped metal oxide interlayer is formed in the opening and contacts the top surface of the target region. The remainder of the opening is filled with a metal plug, the doped metal oxide interlayer disposed between the metal plug and the substrate. The doped metal oxide interlayer is formed from one of tin oxide, titanium oxide or zinc oxide and is doped with fluorine.

Semiconductor power module using discrete semiconductor components

本公开涉及使用分立半导体部件的半导体功率模块，并且公开了一种电子功率模块。该模块包括基板；和安装在该基板上的多个内部绝缘的分立电子器件，使得他们的电导线定位为远离该基板。该电导线耦合至印刷电路板(PCB)。公开的其他特征包括热界面材料和专用热沉。该组件通过注射模制进行二次模制或采用封装体进行灌封。示例的电子器件包括晶闸管、二极管或晶体管。

Semiconductor packaging structure and process

A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.

Metall-Halbleiter-Kontaktstruktur mit dotierter Zwischenschicht

Es ist ein Verfahren offenbart zum Ausbilden eines Metall-Halbleiter-Kontakts mit einer dotierten Metalloxid-Zwischenschicht. Eine Isolierschicht wird auf einer oberen Fläche eines Halbleitersubstrats ausgebildet, wobei ein Zielbereich an der oberen Fläche des Halbleitersubstrats liegt. Eine Öffnung wird durch die Isolierschicht geätzt, wobei die Öffnung eine obere Fläche eines Teils des Zielbereichs freilegt. Eine dotierte Metalloxid-Zwischenschicht wird in der Öffnung ausgebildet und kontaktiert die obere Fläche des Zielbereichs. Der Rest der Öffnung wird mit einem Metallzapfen gefüllt, wobei die dotierte Metalloxid-Zwischenschicht zwischen dem Metallzapfen und dem Substrat angeordnet ist. Die dotierte Metalloxid-Zwischenschicht wird aus entweder Zinnoxid, Titanoxid oder Zinkoxid ausgebildet und ist mit Fluor dotiert.

Semiconductor Packaging Structure and Process

A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow. 1. A semiconductor device comprising:a first substrate with a first surface;a second substrate bonded to the first surface;a first thermal interface material located on the first surface laterally separated from the second substrate; andan underfill material located between the first substrate and the second substrate, the underfill material extending in a first direction from a first point to physically contact the first thermal interface material, the first point being between the first substrate and the second substrate, and the underfill material extending in a second direction from the first point only partially towards the first thermal interface material.2. The semiconductor device of claim 1 , further comprising a third substrate bonded to the first substrate.3. The semiconductor device of claim 2 , wherein the third substrate is a printed circuit board.4. The semiconductor device of claim 1 , wherein the first substrate is a logic die.5. The semiconductor device of claim 4 , wherein the first substrate further comprises through substrate vias.6. The semiconductor device of claim 4 , wherein the second substrate is a memory die.7. The semiconductor device of claim 4 , further comprising a third ...

Engineered polymer-based electronic materials

一種用於電子組裝製程的組成，組成包含分散於有機介質的填料，其中：有機介質包含聚合物；填料包含一或更多的石墨烯、官能化石墨烯、氧化石墨烯、多面體寡聚半矽氧烷、石墨、二維材料、氧化鋁、氧化鋅、氮化鋁、氮化硼、銀、奈米纖維、碳纖維、鑽石、奈米碳管、二氧化矽和金屬塗覆粒子，及組成按組成總重量計包含0.001-40重量%的填料。

SEPARATE HALBLEITERKOMPONENTEN VERWENDENDES HALBLEITERLEISTUNGSMODUL

Es wird ein elektronisches Leistungsmodul offenbart. Das Modul umfasst eine Grundplatte und eine Vielzahl von intern isolierten, separaten, auf der Grundplatte montierten elektronischen Geräten, so dass ihre elektrischen Leitungen von der Grundplatte weg ausgerichtet sind. Die elektrischen Leitungen können mit einer Leiterplatte (LP) gekoppelt sein. Weitere offenbarte Merkmale umfassen ein thermisches Schnittstellenmaterial und einen anwendungsspezifischen Kühlkörper. Die Baugruppe kann mittels Spritzguss unter Verwendung eines Einkapselungsmittels eingekapselt werden. Beispielhafte elektronische Geräte umfassen Thyristoren, Dioden und Transistoren.

LIGHT EMITTING DIODE DISPLAY DEVICE

The present disclosure relates to an LED display device, and more particularly, to an LED display device including a repair structure for a deteriorated pixel. In the present disclosure, a sub LED electrically coupled to first and second connecting electrodes for applying a voltage to a LED is disposed on a deteriorated LED. Thus, deterioration of a display quality due to a deteriorated pixel is prevented. Since it is not required to remove a deteriorated LED, a fabrication cost is reduced and a process efficiency is improved.

METAL-OXIDE CONTACT STRUCTURE HAVING DOPED INTERLAYER

A method for forming metal-semiconductor contact having a doped metal oxide interlayer is disclosed. An insulation layer is formed on the upper surface of a semiconductor substrate having a target area on the upper surface of the semiconductor substrate. An opening is etched through the insulation layer, and the opening exposes the upper surface of a portion of the target area. The doped metal oxide interlayer is formed inside the opening and comes in contact with the upper surface of the target area. The remaining portion of the opening is filled with a metal plug, and the doped metal oxide interlayer is disposed between the metal plug and the substrate. The doped metal oxide interlayer is formed from one material among a tin oxide or a titanium oxide or a zinc oxide and doped with fluorine. COPYRIGHT KIPO 2016 (1202) Forming an insulation layer (1204) Masking and etching the insulation layer (1206) Annealing/removing etching residue (1208) Forming an inter-layer (1210) Doping the inter-layer ...

도핑된 중간층을 갖는 금속-산화물 컨택 구조물

... 도핑된 금속 산화물 중간층을 갖는 금속-반도체 컨택을 형성하는 방법이 개시된다. 반도체 기판의 상부 표면에 타겟 영역을 갖는 반도체 기판의 상부 표면 상에 절연 층이 형성된다. 절연 층을 통해 개구가 에칭되며, 개구는 타겟 영역의 일부의 상부 표면을 노출시킨다. 개구 내에 도핑된 금속 산화물 중간층이 형성되고 타겟 영역의 상부 표면에 접촉한다. 개구의 나머지는 금속 플러그로 채워지며, 도핑된 금속 산화물 중간층이 금속 플러그와 기판 사이에 배치된다. 도핑된 금속 산화물 중간층은 주석 산화물, 티타늄 산화물 또는 아연 산화물 중의 하나로부터 형성되고, 불소로 도핑된다.

Film transistor and preparation method thereof

Metall-Halbleiter-Kontaktstruktur mit dotierter Zwischenschicht und Herstellungsverfahren dafür

Verfahren zum Ausbilden einer Vorrichtung, das Folgendes umfasst: Ausbilden einer Isolierschicht (106) auf einer oberen Fläche eines Halbleitersubstrats (104), das mindestens eine aktive Vorrichtung aufweist, die darin ausgebildet ist, wobei ein Zielbereich (102) der mindestens einen aktiven Vorrichtung an der oberen Fläche des Halbleitersubstrats angeordnet ist; Ätzen einer Öffnung (202) durch die Isolierschicht, wobei die Öffnung den Zielbereich freilegt; Ausbilden einer Metalloxid-Zwischenschicht (402) in der Öffnung und in Kontakt mit dem Zielbereich; Dotieren der Metalloxid-Zwischenschicht mit einem ersten Dotiermittel (502); Ausbilden einer Haftschicht (602) in der Öffnung, die über der dotierten Metalloxid-Zwischenschicht angeordnet ist; Ausbilden eines Metallzapfens (702) in der Öffnung und über der Haftschicht, wobei die dotierte Metalloxid-Zwischenschicht zwischen dem Metallzapfen und dem Halbleitersubstrat angeordnet ist; und Ausbilden einer Redistribution-Layer (RDL) (1002) ...

Phase change material

A thermal interface material includes, in one exemplary embodiment, at least one polymer, at least one phase change material, at least one crosslinker, and at least one thermally conductive filler. The at least one thermally conductive filler includes a first plurality of particles having a particle diameter of about 1 micron or less. The at least one thermally conductive filler comprises at least 80 wt.% of the total weight of the thermal interface material. A formulation for forming a thermal interface material and an electronic component including a thermal interface material are also provided.

DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME

A display device may include a conductive pattern disposed on a substrate. A passivation layer may be disposed on the conductive pattern. A first shielding electrode and a second shielding electrode that may be disposed on the passivation layer may be spaced apart from each other. A first electrode may be disposed on the first shielding electrode. A second electrode may be disposed on the second shielding electrode. A light emitting element may be electrically connected between the first electrode and the second electrode. A first distance between the first shielding electrode and the second shielding electrode may be less than a second distance between the first electrode and the second electrode.

METAL-SEMICONDUCTOR CONTACT STRUCTURE WITH DOPED INTERLAYER

Phase change material

在一個例示性實施例中，一種熱界面材料包括至少一種聚合物、至少一種相變化材料、至少一種交聯劑及至少一種導熱填料。該至少一種導熱填料包括第一複數個粒子直徑係約1微米或更小的粒子。該至少一種導熱填料佔該熱界面材料總重量的至少80重量%。亦提供用於形成熱界面材料之調配物及包括熱界面材料之電子組件。

Thin film transistor and method for making the sam

A thin film transistor is related. The thin film transistor includes a substrate, a gate electrode located on the substrate, a dielectric layer located on the substrate and covering the gate electrode, a semiconductor layer located on the dielectric layer and comprising a plurality of nano-scaled semiconductor materials, and a drain electrode and a source electrode spaced from each other and electrically connected to the semiconductor layer. The dielectric layer is an oxide layer formed by sputtering and in direct contact with the gate electrode. The thin film transistor has inverse hysteresis. A method for making the thin film transistor is also related.

전자 재료용 에폭시 수지 조성물, 그의 경화물 및 전자 부재

... 트리글리시딜옥시비페닐 또는 테트라글리시딜옥시비페닐인 다관능 비페닐형 에폭시 수지와, 경화제 또는 경화 촉진제 중 적어도 1종을 함유하는, 전자 재료용 에폭시 수지 조성물을 제공한다. 또한, 필러, 특히 열전도성 필러를 더 함유하는 전자 재료용 에폭시 수지 조성물을 제공한다. 또한, 당해 전자 재료용 에폭시 수지 조성물을 경화시켜 이루어지는 경화물, 및 당해 경화물을 함유하는 전자 부재를 제공한다.

COMPOSITION FOR ANISOTROPIC CONDUCTIVE FILM, ANISOTROPIC CONDUCTIVE FILM, AND CONNECTION STRUCTURE USING THE SAME

An anisotropic conductive film composition, an anisotropic conductive film prepared using the same, and a connection structure using the same, the anisotropic conductive film including a binder resin; a curable alicyclic epoxy compound; a curable oxetane compound; a quaternary ammonium catalyst; and conductive particles, wherein the anisotropic conductive film has a heat quantity variation rate of about 15% or less, as measured by differential scanning calorimetry (DSC) and calculated by Equation 1: 1. An anisotropic conductive film , comprising:a binder resin;a curable alicyclic epoxy compound;a curable oxetane compound;a quaternary ammonium catalyst; andconductive particles, {'br': None, 'i': H', '−H', 'H, 'sub': 0', '1', '0, 'Heat quantity variation rate (%)=[()/]×100\u2003\u2003Equation 1'}, 'wherein the anisotropic conductive film has a heat quantity variation rate of about 15% or less, as measured by differential scanning calorimetry (DSC) and calculated by Equation 1{'sub': 0', '1, 'wherein His a DSC heat quantity of the anisotropic conductive film, as measured at 25° C. and a time point of 0 hr, and His a DSC heat quantity of the anisotropic conductive film, as measured after being left at 40° C. for 24 hours.'}3. The anisotropic conductive film as claimed in claim 1 , wherein the oxetane compound is a carbon polymer compound containing 1 to 4 oxetane rings per molecule.5. The anisotropic conductive film as claimed in claim 4 , wherein M is SbF or B(CF).6. The anisotropic conductive film as claimed in claim 1 , wherein the binder resin includes a polyimide resin claim 1 , a polyamide resin claim 1 , a phenoxy resin claim 1 , a polymethacrylate resin claim 1 , a polyacrylate resin claim 1 , a polyurethane resin claim 1 , a polyester resin claim 1 , a polyester urethane resin claim 1 , a polyvinyl butyral resin claim 1 , a styrene-butadiene-styrene (SBS) resin or an epoxylated compound thereof claim 1 , a styrene-ethylene/butylene-styrene (SEBS) resin or a ...

Semiconductor package structure and process

METAL-SEMICONDUCTOR CONTACT STRUCTURE WITH DOPED INTERLAYER

Disclosed herein is a method of forming a metal-to-semiconductor contact with a doped metal oxide interlayer. An insulating layer is formed on a top surface of a semiconductor substrate with target region at the top surface of the semiconductor substrate. An opening is etched through the insulating layer with the opening exposing a top surface of a portion of the target region. A doped metal oxide interlayer is formed in the opening and contacts the top surface of the target region. The remainder of the opening is filled with a metal plug, the doped metal oxide interlayer disposed between the metal plug and the substrate. The doped metal oxide interlayer is formed from one of tin oxide, titanium oxide or zinc oxide and is doped with fluorine. 1. A method of forming a device , comprising:forming an insulating layer on a top surface of a semiconductor substrate, a target region disposed at the top surface of the semiconductor substrate;etching an opening through the insulating layer, the opening exposing a top surface of a portion of the target region;forming a doped metal oxide interlayer in the opening and contacting the top surface of the target region; andfilling a remainder of the opening with a metal plug, the doped metal oxide interlayer disposed between the metal plug and the substrate.2. The method of claim 1 , wherein the etching the opening comprises generating an etching byproduct disposed on surfaces of the opening and comprising a first dopant claim 1 , and wherein the forming the doped metal oxide interlayer comprises forming a metal oxide interlayer over the etching byproduct claim 1 , and wherein the first dopant from the etching byproduct at least partially dopes the metal oxide interlayer.3. The method of claim 1 , wherein the forming the doped metal oxide interlayer comprises implanting a first dopant into a metal oxide interlayer.4. The method of claim 3 , wherein the forming the doped metal oxide interlayer comprises forming the metal oxide ...

Metal-Semiconductor Contact Structure with Doped Interlayer

Disclosed herein is a method of forming a metal-to-semiconductor contact with a doped metal oxide interlayer. An insulating layer is formed on a top surface of a semiconductor substrate with target region at the top surface of the semiconductor substrate. An opening is etched through the insulating layer with the opening exposing a top surface of a portion of the target region. A doped metal oxide interlayer is formed in the opening and contacts the top surface of the target region. The remainder of the opening is filled with a metal plug, the doped metal oxide interlayer disposed between the metal plug and the substrate. The doped metal oxide interlayer is formed from one of tin oxide, titanium oxide or zinc oxide and is doped with fluorine.

Composition for anisotropic conductive film, anisotropic conductive film, and connection structure using the same

An anisotropic conductive film composition, an anisotropic conductive film prepared using the same, and a connection structure using the same. The anisotropic conductive film includes: a binder resin; curable compounds comprising an alicyclic epoxy compound and an oxetane compound; a quaternary ammonium catalyst; and conductive particles, the anisotropic conductive film having a heat quantity variation rate of 15% or less, as measured by differential scanning calorimetry (DSC) and calculated by Equation 1: Heat quantity variation rate (%) = [(H0-H1)/H0]*100 --- (1), wherein H0 is DSC heat quantity of the anisotropic conductive film, as measured at 25 DEG C and a time point of 0 hr, and H1 is DSC heat quantity of the anisotropic conductive film, as measured after being left at 40 DEG C for 24 hours. The anisotropic conductive film uses the alicyclic epoxy compound and the oxetane compound as achieves rapid curing at low temperature while exhibiting excellent storage stability and reliability ...

Thermal interface material with ion scavenger

Composition for anisotropic conductive film, anisotropic conductive film, and connection structure using the same

LIQUID ALLOY THERMAL PASTE AND FABRICATION METHOD THEREOF

A liquid alloy thermal paste comprises: a liquid alloy and a trace element, the liquid alloy and the trace element are stirred and reformed to a paste-like liquid alloy mixture that is viscous and does not flow easily, and the liquid alloy mixture is used as the liquid alloy thermal paste.

Thin film transistor and method for making the same

A thin film transistor and a method for making the same are related. The thin film transistor includes a substrate; a semiconductor layer located on the substrate and comprising a plurality of nano-scaled semiconductor materials; a drain electrode and a source electrode spaced from each other and electrically connected to the semiconductor layer; a dielectric layer located on the substrate and covering the semiconductor layer, the drain electrode and the source electrode; and a gate electrode located on the dielectric layer. The dielectric layer is an oxide layer formed by sputtering and in direct contact with the gate electrode. The thin film transistor has inverse hysteresis.

THIN FILM TRANSISTOR AND METHOD FOR MAKING THE SAME

The disclosure relates to a thin film transistor and a method for making the same. The thin film transistor includes a substrate; a semiconductor layer on the substrate, wherein the semiconductor layer includes nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are on the substrate, spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer on the semiconductor layer, wherein the dielectric layer is an oxide dielectric layer formed by magnetron sputtering; and a gate in direct contact with the dielectric layer. The thin film transistor has inverse current hysteresis. 1. A thin film transistor , comprising:a substrate;a semiconductor layer on the substrate, wherein the semiconductor layer comprises a plurality of nano-scaled semiconductor materials;a source and a drain, wherein the source and the drain are on the substrate, spaced apart from each other, and electrically connected to the semiconductor layer;a dielectric layer on the semiconductor layer, wherein the dielectric layer is an oxide dielectric layer formed by magnetron sputtering; anda gate in direct contact with the dielectric layer.2. The thin film transistor of claim 1 , wherein the oxide dielectric layer is a metal oxide dielectric layer.3. The thin film transistor of claim 2 , wherein the metal oxide dielectric layer is an aluminum oxide (AlO) layer.4. The thin film transistor of claim 1 , wherein the oxide dielectric layer is a silicon dioxide (SiO) layer.5. The thin film transistor of claim 1 , wherein a thickness of the dielectric layer is in a range of about 10 nanometers to about 1000 nanometers.6. The thin film transistor of claim 1 , wherein the plurality of nano-scaled semiconductor materials are materials selected from the group consisting of graphene claim 1 , carbon nanotubes claim 1 , molybdenum disulfide (MoS) claim 1 , tungsten disulfide (WS) claim 1 , manganese oxide (MnO) claim 1 , zinc oxide (ZnO) ...

THERMAL INTERFACE MATERIAL WITH ION SCAVENGER

A thermal interface material includes at least one polymer, at least one thermally conductive filler; and at least one ion scavenger. In some embodiments, the ion scavenger is a complexing agent selected from the group consisting of: nitrogen containing complexing agents, phosphorus containing complexing agents, and hydroxyl carboxylic acid based complexing agents.

Composition for anisotropic conductive film, anisotropic conductive film, and connection structure using the same

Multiple-chip package with multiple thermal interface materials

A multiple chip package is described with multiple thermal interface materials. In one example, a package has a substrate, a first semiconductor die coupled to the substrate, a second semiconductor die coupled to the substrate, a heat spreader coupled to the die, wherein the first die has a first distance to the heat spreader and the second die has a second distance to the heat spreader, a first filled thermal interface material (TIM) between the first die and the heat spreader to mechanically and thermally couple the heat spreader to the die, and a second filled TIM between the second die and the heat spreader to mechanically and thermally couple the heat spreader to the second die.

Engineered polymer-based electronic materials

Electronic power module and method of making the same

本發明揭露一種電子電力模組。所述模組包含底座以及安裝至所述底座的多個在內部經隔離的分離電子器件，以使得將多個在內部經隔離的分離電子器件的電導線定向遠離所述底座。可將電導線耦接至印刷電路板。所揭露的其他特徵包含熱介面材料及特殊應用散熱體。組合件可經由射出模製而被包覆模製，或使用封裝劑而被罐封。實例電子器件包含閘流體、二極體以及電晶體。

Thermal interface material with ion scavenger

A thermal interface material includes at least one polymer, at least one thermally conductive filler; and at least one ion scavenger. In some embodiments, the ion scavenger is a complexing agent selected from the group consisting of: nitrogen containing complexing agents, phosphorus containing complexing agents, and hydroxyl carboxylic acid based complexing agents.

With doping in the middle layer of the metal - semiconductor contact structure

SEMICONDUCTOR POWER MODULE USING DISCRETE SEMICONDUCTOR COMPONENTS

An electronic power module is disclosed. The module includes a baseplate and a plurality of internally isolated discrete electronic devices mounted to the baseplate such that their electrical leads are oriented away from the baseplate. Electrical leads may be coupled to a printed circuit board (PCB). Other features disclosed include a thermal interface material and an application-specific heat sink. The assembly may be overmolded via injection molding or potted using an encapsulant. Example electronic devices include thyristors, diodes, and transistors. 1. An electronic power module comprising:a baseplate; anda plurality of internally isolated discrete electronic devices mounted to the baseplate;wherein each of the plurality of internally isolated discrete electronic devices includes electrical leads oriented away from the baseplate.2. The electronic power module of further comprising:a thermal interface material disposed between the plurality of internally isolated discrete electronic devices and the baseplate.3. The electronic power module of wherein:the thermal interface material comprises beryllium oxide, aluminum nitride, zinc oxide, or silicon dioxide.4. The electronic power module of wherein:the baseplate comprises copper.5. The electronic power module of wherein:the electrical leads are coupled to a printed circuit board (PCB).6. The electronic power module of wherein:the electrical leads are coupled to the PCB by soldering.7. The electronic power module of wherein:the baseplate is coupled to at least one heat sink.8. The electronic power module of wherein:the plurality of internally isolated discrete electronic devices and the baseplate are overmolded via injection molding.9. The electronic power module of wherein:the plurality of internally isolated discrete electronic devices and the baseplate are potted using an encapsulant.10. The electronic power module of wherein:each discrete electronic device is either a thyristor, a diode, or a transistor.11. A ...

Film transistor and preparation method thereof

THIN FILM TRANSISTOR AND METHOD FOR MAKING THE SAME

一種薄膜電晶體及其製備方法。該薄膜電晶體包括；一基底；一半導體層，所述半導體層設置於所述基底的一表面，且所述半導體層包括複數個奈米半導體材料；一源極和一漏極，所述源極和漏極間隔設置於所述基底上，且分別與所述半導體層電連接；一電介質層，所述電介質層設置於所述半導體層遠離所述基底的表面，且將所述半導體層、源極和漏極覆蓋；一柵極，所述柵極設置於所述電介質層遠離所述基底的表面；其中，所述電介質層為採用磁控濺射法製備的氧化物層，且與所述柵極直接接觸。本發明的薄膜電晶體具有反常遲滯曲線。

Composition for anisotropic conductive film, anisotropic conductive film, and connection structure using the same

METAL-SEMICONDUCTOR CONTACT STRUCTURE WITH DOPED INTERLAYER

Engineered polymer-based electronic materials

A composition for use in an electronic assembly process, the composition comprising a filler dispersed in an organic medium, wherein: the organic medium comprises a polymer; the filler comprises one or more of graphene, functionalized graphene, graphene oxide, a polyhedral oligomeric silsesquioxane, graphite, a 2D material, aluminum oxide, zinc oxide, aluminum nitride, boron nitride, silver, nano fibers, carbon fibers, diamond, carbon nanotubes, silicon dioxide and metal-coated particles, and the composition comprises from 0.001 to 40 wt. % of the filler based on the total weight of the composition.

For electronic material epoxy resin composition, cured product thereof and the electronic component

本发明提供一种电子材料用环氧树脂组合物，其含有为三缩水甘油基氧基联苯或四缩水甘油基氧基联苯的多官能联苯型环氧树脂和固化剂或固化促进剂中的至少一种。另外，本发明提供电子材料用环氧树脂组合物，其进一步含有填料特别是导热性填料。另外，本发明提供其使该电子材料用环氧树脂组合物固化而得到的固化物及含有该固化物的电子构件。

Semiconductor Packaging Structure and Process

A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.

PHASE CHANGE MATERIAL

A thermal interface material includes, in one exemplary embodiment, at least one polymer, at least one phase change material, at least one crosslinker, and at least one thermally conductive filler. The at least one thermally conductive includes a first plurality of particles having a particle diameter of about 1 micron or less. The at least one thermally conductive filler comprises at least 80 wt. % of the total weight of the thermal interface material. A formulation for forming a thermal interface material and an electronic component including a thermal interface material are also provided.

Light emitting diode display device

The present disclosure relates to an LED display device, and more particularly, to an LED display device including a repair structure for a deteriorated pixel. In the present disclosure, a sub LED electrically coupled to first and second connecting electrodes for applying a voltage to a LED is disposed on a deteriorated LED. Thus, deterioration of a display quality due to a deteriorated pixel is prevented. Since it is not required to remove a deteriorated LED, a fabrication cost is reduced and a process efficiency is improved.

THERMALLY CONDUCTIVE SHEET, METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR MOUNTING THERMALLY CONDUCTIVE SHEET

A thermally conductive sheet excellent in adhesiveness to an electronic component, handleability and reworkability, a method for manufacturing the same, and a method for mounting a thermally conductive sheet, the sheet includes: a sheet body formed by curing a thermally conductive resin composition containing at least a polymer matrix component and a thermally conductive filler, wherein the volume ratio of the thermally conductive filler to the polymer matrix component is 1.00 to 1.70, the thermally conductive filler contains a fibrous thermally conductive filler, and the fibrous thermally conductive filler projects from the surface of the sheet body and is coated with an uncured component of the polymer matrix component.

PHASE CHANGE MATERIAL

在一个示例性实施方案中，热界面材料包含至少一种聚合物、至少一种相变材料、至少一种交联剂和至少一种导热填料。所述至少一种导热填料包含颗粒直径为约1微米或更小的多个第一颗粒。所述至少一种导热填料占热界面材料总重量的至少80重量％。还提供了用于形成热界面材料的配制物和包含热界面材料的电子部件。

Semiconductor packaging structure and process

A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.

Epoxy resin composition for electronic material, cured product thereof and electronic member

An epoxy resin composition for an electronic material is provided which contains: a multifunctional biphenyl-type epoxy resin which is a triglycidyloxybiphenyl or a tetraglycidyloxybiphenyl; and a curing agent and/or a curing promoting agent. Further, an epoxy resin composition for an electronic material is provided which also contains a filler, specifically a thermally conductive filler. Further, a cured product formed by curing said epoxy resin composition, and an electronic member containing said cured product are provided.

THERMAL INTERFACE MATERIAL WITH ION SCAVENGER

A thermal interface material includes at least one polymer, at least one thermally conductive filler; and at least one ion scavenger. In some embodiments, the ion scavenger is a complexing agent selected from the group consisting of: nitrogen containing complexing agents, phosphorus containing complexing agents, and hydroxyl carboxylic acid based complexing agents.

Thermal interface material including crosslinker and multiple fillers

A thermal interface material includes, in one exemplary embodiment, at least one polymer, at least one phase change material, at least one crosslinker, and at least one thermally conductive filler. The at least one thermally conductive includes a first plurality of particles having a particle diameter of about 1 micron or less. The at least one thermally conductive filler comprises at least 80 wt. % of the total weight of the thermal interface material. A formulation for forming a thermal interface material and an electronic component including a thermal interface material are also provided.

Engineered Polymer-Based Electronic Materials

A composition for use in an electronic assembly process, the composition comprising a filler dispersed in an organic medium, wherein: the organic medium comprises a polymer; the filler comprises one or more of graphene, functionalized graphene, graphene oxide, a polyhedral oligomeric silsesquioxane, graphite, a 2D material, aluminum oxide, zinc oxide, aluminum nitride, boron nitride, silver, nano fibers, carbon fibers, diamond, carbon nanotubes, silicon dioxide and metal-coated particles, and the composition comprises from 0.001 to 40 wt. % of the filler based on the total weight of the composition.

material de interface térmica, e componente eletrônico

THIN FILM TRANSISTOR AND METHOD FOR MAKING THE SAM

Thermal interface material with ion scavenger

A thermal interface material includes at least one polymer, at least one thermally conductive filler; and at least one ion scavenger. In some embodiments, the ion scavenger is a complexing agent selected from the group consisting of: nitrogen containing complexing agents, phosphorus containing complexing agents, and hydroxyl carboxylic acid based complexing agents.

ANISOTROPIC CONDUCTIVE FILM INCLUDING A REFLECTIVE LAYER

An anisotropic conductive film (ACF) is disclosed. In one approach, the ACF includes a non-reflective adhesive layer including a top surface, a plurality of conductive particles included with the non-reflective adhesive layer, and a reflective adhesive layer disposed along the top surface of the non-reflective adhesive layer.

EPOXY RESIN COMPOSITION FOR ELECTRONIC MATERIAL, CURED PRODUCT THEREOF AND ELECTRONIC MEMBER

An epoxy resin composition for electronic material, containing a polyfunctional biphenyl type epoxy resin that is a triglycidyloxybiphenyl or a tetraglycidyloxybiphenyl and at least one of a curing agent and a curing accelerator is provided. Furthermore, the epoxy resin composition for electronic material, further containing a filler, in particular, a thermal conductive filler, is provided. Furthermore, a cured product obtained by curing the epoxy resin composition for electronic material, and an electronic component containing the cured product are provided.

Anisotropic conductive film including a reflective layer

An anisotropic conductive film (ACF) is disclosed. In one approach, the ACF includes a non-reflective adhesive layer including a top surface, a plurality of conductive particles included with the non-reflective adhesive layer, and a reflective adhesive layer disposed along the top surface of the non-reflective adhesive layer.

Metal-semiconductor contact structure with doped interlayer

Disclosed herein is a method of forming a metal-to-semiconductor contact with a doped metal oxide interlayer. An insulating layer is formed on a top surface of a semiconductor substrate with target region at the top surface of the semiconductor substrate. An opening is etched through the insulating layer with the opening exposing a top surface of a portion of the target region. A doped metal oxide interlayer is formed in the opening and contacts the top surface of the target region. The remainder of the opening is filled with a metal plug, the doped metal oxide interlayer disposed between the metal plug and the substrate. The doped metal oxide interlayer is formed from one of tin oxide, titanium oxide or zinc oxide and is doped with fluorine.

MULTIPLE-CHIP PACKAGE WITH MULTIPLE THERMAL INTERFACE MATERIALS

A multiple chip package is described with multiple thermal interface materials. In one example, a package has a substrate, a first semiconductor die coupled to the substrate, a second semiconductor die coupled to the substrate, a heat spreader coupled to the die, wherein the first die has a first distance to the heat spreader and the second die has a second distance to the heat spreader, a first filled thermal interface material (TIM) between the first die and the heat spreader to mechanically and thermally couple the heat spreader to the die, and a second filled TIM between the second die and the heat spreader to mechanically and thermally couple the heat spreader to the second die. 1. A semiconductor package comprising:a substrate;a first semiconductor die coupled to the substrate;a second semiconductor die coupled to the substrate;a heat spreader coupled to the die, wherein the first die has a first distance to the heat spreader and the second die has a second distance to the heat spreader;a first thermal interface material (TIM) between the first die and the heat spreader to mechanically and thermally couple the heat spreader to the die; anda second TIM between the second die and the heat spreader to mechanically and thermally couple the heat spreader to the second die.2. The semiconductor package of claim 1 , wherein the first and the second TIMs comprise:thermally conductive particles; anda polymer matrix.3. The semiconductor package of claim 2 , wherein the second distance is greater than the first distance and the particles of the second TIM are larger than the particles of the first TIM.4. The semiconductor package of claim 3 , wherein the particles of the first TIM have a mean size of about 10 μm and the particles of the second TIM have a mean size of about 40 μm.5. The semiconductor package of claim 2 , wherein the particles of the second TIM have a mean size greater than the first distance.6. The semiconductor package of claim 2 , wherein the particles ...

Semiconductor packaging structure and process

A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.

Epoxy resin composition for electronic material, cured product thereof and electronic member

Phase change material

具有离子清除剂的热界面材料

热界面材料包含至少一种聚合物、至少一种导热填料、和至少一种离子清除剂。在一些实施方案中，所述离子清除剂为络合剂，其选自含氮络合剂、含磷络合剂、和基于羟基羧酸的络合剂。

Thermal interface material with ion scavenger

열 계면 재료는 적어도 1종의 폴리머, 적어도 1종의 열전도성 충전제; 및 적어도 1종의 이온 스캐빈저를 포함한다. 일부 실시양태들에서, 이온 스캐빈저는 질소 함유 착화제, 인 함유 착화제, 및 히드록실 카르복실산계 착화제로 이루어진 군에서 선택되는 착화제이다. The thermal interface material may include at least one polymer, at least one thermally conductive filler; and at least one ion scavenger. In some embodiments, the ion scavenger is a complexing agent selected from the group consisting of nitrogen-containing complexing agents, phosphorus-containing complexing agents, and hydroxyl carboxylic acid-based complexing agents.

Thermally conductive sheet, method for manufacturing same, and method for mounting thermally conductive sheet

本发明提供与电子部件的密合性、操作性和再加工性优异的导热性片及其制造方法、导热性片的安装方法。具有至少包含高分子基质成分和导热性填充剂的导热性树脂组合物固化而成的片主体(2)，导热性填充剂相对于高分子基质成分的体积比例为1.00～1.70，导热性填充剂包含纤维状导热性填充剂(10)，纤维状导热性填充剂(10)从片主体(2)的表面突出，并且被高分子基质成分的未固化成分被覆。

Display device

표시 장치가 제공된다. 표시 장치는 서로 이격된 제1 전극 및 제2 전극, 상기 제1 전극과 상기 제2 전극 사이에 배치된 발광 소자들, 상기 제1 전극 및 상기 발광 소자들의 제1 단부와 접하는 제1 연결 전극, 상기 제2 전극 및 상기 발광 소자들의 제2 단부와 접하는 제2 연결 전극, 및 상기 제1 연결 전극과 상기 제2 연결 전극 사이에 배치된 도전 패턴을 포함하며, 상기 도전 패턴의 제1 단부는 상기 제1 연결 전극과 접하고, 상기 도전 패턴의 제2 단부는 상기 제2 연결 전극과 접한다.

Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate

A semiconductor device includes a wafer level substrate having a plurality of first conductive vias formed through the wafer level substrate. A first semiconductor die is mounted to the wafer level substrate. A first surface of the first semiconductor die includes contact pads oriented toward a first surface of the wafer level substrate. A first encapsulant is deposited over the first semiconductor die. A second semiconductor die is mounted to the wafer level substrate. A first surface of the second semiconductor die includes contact pads oriented toward a second surface of the wafer level substrate opposite the first surface of the wafer level substrate. A second encapsulant is deposited over the second semiconductor die. A plurality of bumps is formed over the plurality of first conductive vias. A second conductive via can be formed through the first encapsulant and connected to the first conductive via. The semiconductor packages are stackable.

Micro-led element mounted substrate, and display device using same

A micro-light-emitting diode (LED) mounting board includes a substrate (1) having a mount surface (1a) receiving multiple micro-LEDs, and at least one pixel unit (15) located on the mount surface (1a) and including the multiple micro-LEDs (74R, 74G, 74B) having different emission colors to operate as a basic element of display. The multiple micro-LEDs (74R, 74G, 74B) include vertical stacks of multiple first electrodes (61R, 61G, 61B), multiple emissive layers (74RL, 74GL, 74BL), and multiple second electrodes (62R, 62G, 62B). The at least one pixel unit (15) includes a power electrode pad (60S) connected to each of the multiple second electrodes (62R, 62G, 62B). The power electrode pad (60S) is spaced from each of the multiple first electrodes (61R, 61G, 61B) by a distance (L1, L2, L3) greater than an interelectrode distance (L4, L5) between adjacent first electrodes of the multiple first electrodes (61R, 61G, 61B).

Chip module and method for forming the same

A chip module is provided. The chip module includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a signal pad region adjacent to the upper surface. A recess extends from the upper surface toward the lower surface along the sidewall of the chip. A redistribution layer is electrically connected to the signal pad region and extends into the recess. A circuit board is located between the upper surface and the lower surface and extends into the recess. A conducting structure is located in the recess and electrically connects the circuit board to the redistribution layer. A method for forming the chip module is also provided.

Phase change material

A thermal interface material includes, in one exemplary embodiment, at least one polymer, at least one phase change material, at least one crosslinker, and at least one thermally conductive filler. The at least one thermally conductive includes a first plurality of particles having a particle diameter of about 1 micron or less. The at least one thermally conductive filler comprises at least 80wt.％ of the total weight of the thermal interface material. A formulation for forming a thermal interface material and an electronic component including a thermal interface material are also provided.

Thermal interface material with ion scavenger

A thermal interface material includes at least one polymer,at least one thermally conductive filler; and at least one ion scavenger. In some embodiments, the ion scavenger is a complexing agent selected from the group consisting of : nitrogen containing complexing agents,phosphorus containing complexing agents, and hydroxyl carboxylic acid based complexing agents.

Semiconductor device and method of forming conductive posts and heat sink over semiconductor die using leadframe

A semiconductor device has a prefabricated multi-die leadframe with a base and integrated raised die paddle and a plurality of bodies extending from the base. A thermal interface layer is formed over a back surface of a semiconductor die or top surface of the raised die paddle. The semiconductor die is mounted over the raised die paddle between the bodies of the leadframe with the TIM disposed between the die and raised die paddle. An encapsulant is deposited over the leadframe and semiconductor die. Vias can be formed in the encapsulant. An interconnect structure is formed over the leadframe, semiconductor die, and encapsulant, including into the vias. The base is removed to separate the bodies from the raised die paddle. The raised die paddle provides heat dissipation for the semiconductor die. The bodies are electrically connected to the interconnect structure. The bodies operate as conductive posts for electrical interconnect.

Semiconductor Packaging Structure and Process

本发明提供了一种用于封装半导体器件的方法和结构。在实施例中，将第一衬底接合至第二衬底，将第二衬底接合至第三衬底。在应用底部填充材料之前将热界面材料放置在第二衬底上。可以将环形件放置在热界面材料上，以及在第二衬底和第三衬底之间分配底部填充材料。通过在放置底部填充材料之前放置热界面材料和环形件，使得底部填充材料不能干扰热界面材料和第二衬底之间的界面，并且热界面材料和环形件可以用作底部填充材料的物理屏障，从而防止溢流。本发明还包括半导体封装结构和工艺。

Display device and method of manufacturing the same

公开了一种显示装置以及制造该显示装置的方法。显示装置包括基板、显示元件、晶体管和焊盘。基板包括显示区和外围区。显示元件被设置在显示区上。晶体管电连接到显示元件。焊盘被设置在外围区上，并且具有多层结构。焊盘包括焊盘金属层、设置在焊盘金属层上的第一焊盘保护层以及介于焊盘金属层与第一焊盘保护层之间的第二焊盘保护层。第二焊盘保护层与第一焊盘保护层包括不同的材料。晶体管包括设置在基板上的半导体层、设置在覆盖半导体层的栅绝缘层上的栅电极以及布置在覆盖栅电极的层间绝缘层上的连接电极。连接电极具有与焊盘的多层结构相同的多层结构，并且连接电极连接到半导体层。

Epoxy resin composition for electronic material, cured product thereof and electronic member

An epoxy resin composition for electronic material, containing a polyfunctional biphenyl type epoxy resin that is a triglycidyloxybiphenyl or a tetraglycidyloxybiphenyl and at least one of a curing agent and a curing accelerator is provided. Furthermore, the epoxy resin composition for electronic material, further containing a filler, in particular, a thermal conductive filler, is provided. Furthermore, a cured product obtained by curing the epoxy resin composition for electronic material, and an electronic component containing the cured product are provided.

Thermally conductive sheet, method for manufacturing same, and method for mounting thermally conductive sheet

전자 부품과의 밀착성, 핸들링성 및 리워크성이 우수한 열전도성 시트, 및 그의 제조 방법, 열전도성 시트의 실장 방법을 제공한다. 적어도 고분자 매트릭스 성분과 열전도성 충전제를 포함하는 열전도성 수지 조성물이 경화되어 이루어지는 시트 본체(2)를 갖고, 고분자 매트릭스 성분에 대한 열전도성 충전제의 체적 비율이, 1.00 내지 1.70이고, 열전도성 충전제가, 섬유상 열전도성 충전제(10)를 포함하고, 섬유상 열전도성 충전제(10)는, 시트 본체(2)의 표면으로부터 돌출됨과 함께, 고분자 매트릭스 성분의 미경화 성분으로 피복되어 있다.

phase change material

열 계면 물질은, 일 예시적인 구현으로, 적어도 하나의 폴리머, 적어도 하나의 상 변화 물질, 적어도 하나의 가교제 및 적어도 하나의 열 전도성 충전제를 포함한다. 적어도 하나의 열 전도성은 약 1미크론 이하의 입자 직경을 갖는 제1 복수의 입자를 포함한다. 적어도 하나의 열 전도성 충전제는 열 계면 물질의 총 중량의 적어도 80중량%로 포함된다. 열 계면 물질을 형성하기 위한 제형 및 열 계면 물질을 포함하는 전자 부품이 또한 제공된다. The thermal interface material, in one exemplary implementation, includes at least one polymer, at least one phase change material, at least one crosslinker, and at least one thermally conductive filler. The at least one thermal conductivity comprises a first plurality of particles having a particle diameter of about 1 micron or less. The at least one thermally conductive filler comprises at least 80% by weight of the total weight of the thermal interface material. An electronic component comprising the thermal interface material and a formulation for forming the thermal interface material is also provided.

Micro-led element mounted substrate, and display device using same

Phase change material

Pixel and display device including the same

본 발명의 일 실시예에 의한 화소는, 제1 방향을 따라 서로 이격된 제1 전극 및 제2 전극; 상기 제1 전극과 상기 제2 전극 사이의 제1 영역에서 제2 방향을 따라 배열되며, 각각이 상기 제1 전극에 인접한 제1 단부 및 상기 제2 전극에 인접한 제2 단부를 포함한 제1 발광 소자들; 상기 제1 발광 소자들의 제1 단부들 상에 배치되며, 투명 전극층을 포함한 제1 컨택 전극; 상기 제1 발광 소자들의 제2 단부들 상에 배치되며, 반사 전극층을 포함한 제2 컨택 전극; 상기 제1 전극의 일 부분과 중첩되며, 상기 제1 전극의 하부에 배치된 제1 뱅크 패턴; 및 상기 제2 전극의 일 부분과 중첩되며, 상기 제2 전극의 하부에 배치된 제2 뱅크 패턴을 포함할 수 있다. 상기 제1 뱅크 패턴과 상기 제2 뱅크 패턴은 상기 제1 영역으로부터 서로 다른 거리만큼 이격될 수 있다.

像素和具有该像素的显示装置

该像素包括：第一电极和第二电极，在第一方向上彼此间隔开；第一发光元件，沿着第二方向布置在第一电极与第二电极之间的第一区域中，并且包括第一端部和第二端部；第一接触电极，定位在第一发光元件的第一端部上，并且包括透明电极层；第二接触电极，定位在第一发光元件的第二端部上，并且包括反射电极层；第一堤图案，与第一电极的一部分叠置，并且定位在第一电极下方；以及第二堤图案，与第二电极的一部分叠置，并且定位在第二电极下方。第一堤图案和第二堤图案可以与第一区域间隔开不同的距离。

Engineered polymer-based electronic materials

相变材料

在一个示例性实施方案中，热界面材料包含至少一种聚合物、至少一种相变材料、至少一种交联剂和至少一种导热填料。所述至少一种导热填料包含颗粒直径为约1微米或更小的多个第一颗粒。所述至少一种导热填料占热界面材料总重量的至少80重量％。还提供了用于形成热界面材料的配制物和包含热界面材料的电子部件。

微型led元件搭载基板以及使用其的显示装置

微型LED元件搭载基板具备：基板(1)，具有微型LED元件的搭载面(1a)；和作为显示单位的像素部(15)，被配置于搭载面(1a)侧，包含发光颜色不同的多个微型LED元件(74R、74G、74B)，微型LED元件(74R、74G、74B)是将第1电极(61R、61G、61B)、发光层(74RL、74GL、74BL)、第2电极(62R、62G、62B)层叠而成的纵型LED元件，在像素部(15)之中配置有与多个第2电极(62R、62G、62B)分别连接的电源电极焊盘(60S)，电源电极焊盘(60S)与多个第1电极(61R、61G、61B)的各距离(L1、L2、L3)比多个第1电极(61R、61G、61B)的相邻间距离(L4、L5)长。

Engineered Polymer-Based Electronic Materials

A composition for use in an electronic assembly process, the composition comprising a filler dispersed in an organic medium, wherein: the organic medium comprises a polymer; the filler comprises one or more of graphene, functionalized graphene, graphene oxide, a polyhedral oligomeric silsesquioxane, graphite, a 2D material, aluminum oxide, zinc oxide, aluminum nitride, boron nitride, silver, nano fibers, carbon fibers, diamond, carbon nanotubes, silicon dioxide and metal-coated particles, and the composition comprises from 0.001 to 40 wt. % of the filler based on the total weight of the composition.

薄膜トランジスタ及びその製造方法

【課題】本発明は、薄膜トランジスタ及びその製造方法に関する。【解決手段】本発明の薄膜トランジスタは、基板、ゲート電極、誘電層、半導体層、ソース電極及びドレイン電極を含む。前記ゲート電極が前記基板の表面に設置される。前記誘電層が前記基板に設置され、前記ゲート電極を被覆する。前記半導体層が前記誘電層の前記基板から離れる表面に設置され、複数のナノ半導体材料を含む。前記ソース電極及び前記ドレイン電極が前記誘電層の前記基板を離れる表面に間隔をあけて設置され、それぞれ前記半導体層と電気的に接続される。前記誘電層がマグネトロンスパッタリング法によって製造された酸化物層であり、前記ゲート電極と直接に接触される。また、本発明は、薄膜トランジスタの製造方法を提供する。【選択図】図１

显示装置

显示装置可以包括：板；多个像素列，设置在板上，并且具有多个像素组，该多个像素组各自包括在第一方向上布置的第一像素和第二像素；以及堤部，围绕多个像素组中的每个的周边，并且包括第一开口和第二开口，第一开口分别对应于多个像素组，第二开口位于多个像素组中的在第一方向上彼此相邻的两个像素组之间。

Led显示装置

本申请涉及一种LED显示装置，更具体地，涉及一种包括用于劣化像素的修复结构的LED显示装置。本发明旨在将子微型LED堆叠并设置在已发生劣化的微型LED上，其中，子微型LED电联接至向微型LED施加电压的第一和第二连接电极。因此，可以防止由于劣化的像素而导致的显示质量的劣化，并且由于不需要另外去除已发生劣化的微型LED，因此可以降低工艺成本并提高工艺效率。

Led display device

薄膜トランジスタ及びその製造方法

표시 장치

표시 장치는 표시 영역 및 표시 영역을 둘러싸는 주변 영역을 포함하는 기판, 기판의 주변 영역의 제1 방향에 배치되고, 제1 방향에 수직한 제2 방향으로 배열되는 복수의 패드들 및 패드들 상에 배치되는 회로 필름을 포함한다. 패드들 각각은 기판 상에 배치되는 신호 배선, 기판 상에서 신호 배선과 제1 방향으로 이격되어 배치되는 제1 더미 패턴 및 기판 상에서 신호 배선과 제1 더미 패턴 사이에 배치되는 제1 절연 패턴을 포함한다.

复合ic装置结构的部件中的绝热互连特征

一种复合集成电路(IC)结构至少包括与第二IC管芯堆叠的第一IC管芯。每一管芯具有装置层以及互连至所述装置层的晶体管并且终止于特征处的金属化层。第一IC管芯的第一特征主要具有第一成分，所述第一成分具有第一微结构。第二IC管芯的第二特征主要具有第二成分或者第二微结构。第二特征中的第一个与第一特征中的一个直接接触。第二成分具有的热导率比第一成分和第一微结构的热导率低至少一个数量级。第一成分具有的热导率可以是第二成分或第二微结构的热导率的至少40倍。

薄膜トランジスタ及びその製造方法

薄膜トランジスタ及びその製造方法

【課題】本発明は、薄膜トランジスタ及びその製造方法に関する。 【解決手段】本発明の薄膜トランジスタは、基板、ゲート電極、誘電層、半導体層、ソース電極及びドレイン電極を含む。前記半導体層が前記基板の表面に設置され、複数のナノ半導体材料を含み、前記ソース電極及び前記ドレイン電極が前記基板に間隔をあけて設置され、それぞれ前記半導体層と電気的に接続される。前記誘電層が前記半導体層の前記基板から離れる表面に設置され、前記半導体層、前記ソース電極及び前記ドレイン電極を被覆する。前記ゲート電極が前記誘電層の前記基板から離れる表面に設置される。前記誘電層がマグネトロンスパッタリング法によって製造された酸化物層であり、前記ゲート電極と直接に接触される。また、本発明は、薄膜トランジスタの製造方法を提供する。 【選択図】図７

Heatsink pedestals for thermal interface material fill

Mounting a heat sink to an electrical component by applying a thermal interface material on at least one of a surface of one of the electrical component and the heat sink, wherein the heat sink includes a heat pedestal including an interface surface with an apex having at least one curvature extending therethrough. The heat sink contacts the electrical component through the thermal interface material. The apex of the interface surface is an element of the heat sink closest to the electrical component. The interface surface that includes the apex and the at least one curvature cause the thermal interface material to flow during the contacting so that any space between the heat sink and the electrical component is filled with thermal interface material and is substantially free of voids.

Display device

A display device includes a substrate including a display area and a peripheral area surrounding the display area, a plurality of pads in a first direction of the peripheral area of the substrate and in a second direction perpendicular to the first direction, and a circuit film on the pads. Each of the pads includes a signal line on the substrate, a first dummy pattern on the substrate and spaced apart from the signal line in the first direction, and a first insulating pattern between the signal line and the first dummy pattern on the substrate.

显示装置

显示装置包括：基板，包括显示区域以及包围显示区域的周边区域；多个焊盘，配置在基板的周边区域的第一方向上，并且在与第一方向垂直的第二方向上排列多个焊盘；以及电路膜，配置在焊盘上。各个焊盘包括：信号布线，配置在基板上；第一虚设图案，在基板上，在第一方向上与信号布线间隔开来配置第一虚设图案；以及第一绝缘图案，在基板上配置在信号布线与第一虚设图案之间。

Wärmeisolierende interconnect-merkmale in einer komponente einer verbundic-vorrichtungsstruktur

Eine Verbund-Integrierte-Schaltung(IC)-Struktur beinhaltet mindestens einen ersten IC-Die in einem Stapel mit einem zweiten IC-Die. Jeder Die weist eine Vorrichtungsschicht und Metallisierungsschichten auf, die mit Transistoren der Vorrichtungsschicht verbunden sind und bei Merkmalen enden. Erste Merkmale des ersten IC-Die weisen hauptsächlich eine erste Zusammensetzung mit einer ersten Mikrostruktur auf. Zweite Merkmale des zweiten IC-Die weisen hauptsächlich eine zweite Zusammensetzung oder eine zweite Mikrostruktur auf. Ein erstes der zweiten Merkmale befindet sich in direktem Kontakt mit einem der ersten Merkmale. Die zweite Zusammensetzung weist eine Wärmeleitfähigkeit auf, die mindestens eine Größenordnung niedriger als die der ersten Zusammensetzung und der ersten Mikrostruktur ist. Die erste Zusammensetzung kann eine Wärmeleitfähigkeit aufweisen, die mindestens das 40-Fache der der zweiten Zusammensetzung oder zweiten Mikrostruktur beträgt.

显示装置

显示装置包括：电源线；栅极线，分别在平面图上沿第一方向延伸且沿第二方向排列；像素，连接于电源线及栅极线；以及垂直线，分别在平面图上沿第二方向延伸且沿第一方向排列。其中，垂直线包括栅极连接线以及布置于栅极连接线之间的虚设线。栅极连接线将栅极线连接于栅极驱动部。虚设线连接于电源线。将栅极连接线中的至少一条置于其之间而隔开的虚设线之间的间距整体恒定。

Led display device

The present disclosure relates to an LED display device, and more particularly, to an LED display device including a repair structure for a deteriorated pixel.In the present disclosure, a sub LED electrically connected to first and second connecting electrodes for applying a voltage to a LED is disposed on a deteriorated LED.Thus, deterioration of a display quality due to a deteriorated pixel is prevented. Since it is not required to remove a deteriorated LED, a fabrication cost is reduced and a process efficiency is improved.

화소 및 이를 구비한 표시 장치

화소는 제1 방향을 따라 이격된 제1 전극 및 제2 전극; 제1 전극과 제2 전극 사이의 제1 영역에서 제2 방향을 따라 배열되며, 제1 단부 및 제2 단부를 포함한 제1 발광 소자들; 제1 발광 소자들의 제1 단부들 상에 위치하며 투명 전극층을 포함한 제1 컨택 전극; 제1 발광 소자들의 제2 단부들 상에 위치하며 반사 전극층을 포함한 제2 컨택 전극; 제1 전극의 일 부분과 중첩되며, 제1 전극의 하부에 위치하는 제1 뱅크 패턴; 및 제2 전극의 일 부분과 중첩되며, 제2 전극의 하부에 위치하는 제2 뱅크 패턴을 포함하고, 제1 뱅크 패턴과 제2 뱅크 패턴은 제1 영역으로부터 서로 다른 거리만큼 이격될 수 있다.

Pixel and display device including the same

A pixel may include first and second electrodes spaced apart from each other along a first direction, first light emitting elements arranged along a second direction in a first area between the first electrode and the second electrode, and including a first end portion adjacent to the first electrode and a second end portion adjacent to the second electrode, a first contact electrode on the first end portions of the first light emitting elements, and including a transparent electrode layer, a second contact electrode on the second end portions of the first light emitting elements, and including a reflective electrode layer, a first bank pattern overlapping a portion of the first electrode beneath the first electrode, and a second bank pattern overlapping a portion of the second electrode beneath the second electrode, wherein the first and second bank patterns are spaced apart from the first area by different distances.

표시 장치

표시 장치는, 전원 라인; 각각이 평면도 상에서 제1 방향으로 연장하고 제2 방향을 따라 배열되는 게이트 라인들; 전원 라인 및 게이트 라인들에 연결된 화소들; 및 각각이 평면도 상에서 제2 방향으로 연장하며 제1 방향을 따라 배열되는 수직 라인들을 포함한다. 수직 라인들은 게이트 연결 라인들 및 게이트 연결 라인들 사이에 배치되는 더미 라인들을 포함한다. 게이트 연결 라인들은 게이트 라인들을 게이트 구동부에 연결한다. 더미 라인들은 전원 라인에 연결된다. 게이트 연결 라인들 중 적어도 하나를 사이에 두고 이격된 더미 라인들 간의 간격은 전체적으로 일정하다.

Method of interconnecting semiconductor devices and assembly of interconnected semiconductor devices

The present disclosure relates to a method of interconnecting semiconductor devices and an assembly of interconnected semiconductor devices. The method comprises forming a metal layer on a first connection surface of the first semiconductor device, and forming an oxidant layer on a second connection surface of the second semiconductor device, the first connection surface including first coupling pads, the second connection surface including the second coupling pads. The method further comprises aligning the first connecting pads and respective ones of the second connecting pads to each other, pressing together the metal layer and the oxidant layer, and reacting the metal layer with the oxidant layer under target condition to form a bonding layer. The bonding layer first regions, second regions, and third regions that are conductive regions, and a fourth region that is a nonconductive adhesive region. The method of interconnecting semiconductor devices allows alignment errors, improves yield, and reduces cost.

Multiple composition thermal interface materials for multi-die packages

A die package comprises a substrate comprising a first face and an opposing second face, a first semiconductor die coupled to the first face of the substrate, a second semiconductor die coupled to the first face of the substrate; and a heat spreader, wherein the first semiconductor die is thermally connected to the heat spreader by a first thermal interface material and the second semiconductor die is thermally connected to the heat spreader by a second thermal interface material, wherein the first thermal interface material comprises a first composition and the second thermal interface material comprises a second composition, wherein the first composition has a lower elastic modulus than the second composition under a first specified condition or conditions.

显示装置

显示装置可以包括：板；多个像素列，设置在板上，并且具有多个像素组，该多个像素组各自包括在第一方向上布置的第一像素和第二像素；以及堤部，围绕多个像素组中的每个的周边，并且包括第一开口和第二开口，第一开口分别对应于多个像素组，第二开口位于多个像素组中的在第一方向上彼此相邻的两个像素组之间。

像素和具有该像素的显示装置

该像素包括：第一电极和第二电极，在第一方向上彼此间隔开；第一发光元件，沿着第二方向布置在第一电极与第二电极之间的第一区域中，并且包括第一端部和第二端部；第一接触电极，定位在第一发光元件的第一端部上，并且包括透明电极层；第二接触电极，定位在第一发光元件的第二端部上，并且包括反射电极层；第一堤图案，与第一电极的一部分叠置，并且定位在第一电极下方；以及第二堤图案，与第二电极的一部分叠置，并且定位在第二电极下方。第一堤图案和第二堤图案可以与第一区域间隔开不同的距离。

显示装置以及制造该显示装置的方法

公开了一种显示装置以及制造该显示装置的方法。显示装置包括基板、显示元件、晶体管和焊盘。基板包括显示区和外围区。显示元件被设置在显示区上。晶体管电连接到显示元件。焊盘被设置在外围区上，并且具有多层结构。焊盘包括焊盘金属层、设置在焊盘金属层上的第一焊盘保护层以及介于焊盘金属层与第一焊盘保护层之间的第二焊盘保护层。第二焊盘保护层与第一焊盘保护层包括不同的材料。晶体管包括设置在基板上的半导体层、设置在覆盖半导体层的栅绝缘层上的栅电极以及布置在覆盖栅电极的层间绝缘层上的连接电极。连接电极具有与焊盘的多层结构相同的多层结构，并且连接电极连接到半导体层。

반도체 장치의 상호연결 방법 및 상호연결 반도체 장치

본 발명은 반도체 장치의 상호연결 방법 및 상호연결 반도체 장치와 관련이 있으며, 상기 상호연결 방법은 다음을 포함한다: 제1 반도체 장치의 제1 결합 표면에 금속층을 형성하고, 제2 반도체 장치의 제2 결합 표면에 산화층을 형성하는 단계, 상기 제1 결합 표면은 제1 결합 패드를 포함하며, 상기 제2 결합 표면은 제2 결합 패드를 포함하며; 상기 제1 결합 패드와 상기 제2 결합 패드를 서로 정렬하고 서로 일대일 대응시키고, 상기 금속층과 상기 산화층을 적층하는 단계; 타겟 조건 하에서 상기 금속층과 상기 산화층을 반응시켜 결합층을 형성하는 단계, 상기 결합층 내의 제1 영역, 제2 영역, 및 제3 영역이 도전성 영역이며, 제4 영역이 비도전성 결합 영역이다. 따라서, 제 1 결합 패드와 제 2 결합 패드가 정렬 전위(dislocation) 상태인 경우, 제 2 영역과 제 3 영역을 사용하여 두 결합 패드 간의 유효한 도전성 영역이 증가하며, 제 4 영역을 사용하여 결합 효과가 향상되어 상호연결 신뢰성이 향상된다. 이 상호연결 방법은 정렬 오류를 허용하며 생산 수율을 향상시키고 비용을 절감한다.

半导体器件的互联方法及互联半导体器件

本公开涉及半导体器件的互联方法及互联半导体器件，该互联方法包括：在第一半导体器件的第一联接面形成金属层，在第二半导体器件的第二联接面形成氧化层，第一联接面包括第一联接点，第二联接面包括第二联接点；将第一联接点和第二联接点相互对准且一一对应，将金属层和氧化层压合；在目标条件下金属层和氧化层发生反应形成粘结层；在粘结层中，第一区域、第二区域和第三区域为导电区域，第四区域为不导电粘合区域。由此，在第一联接点和第二联接点存在对准错位的情况下，利用第二区域和第三区域增加了两个联接点之间的有效导电面积，利用第四区域增强了粘合效果，从而提高了互联可靠性；该互联方法允许存在对准误差，提升了良率和降低了成本。

半导体器件的互联方法及互联半导体器件

本公开涉及半导体器件的互联方法及互联半导体器件，该互联方法包括：在第一半导体器件的第一联接面形成金属层，在第二半导体器件的第二联接面形成氧化层，第一联接面包括第一联接点，第二联接面包括第二联接点；将第一联接点和第二联接点相互对准且一一对应，将金属层和氧化层压合；在目标条件下金属层和氧化层发生反应形成粘结层；在粘结层中，第一区域、第二区域和第三区域为导电区域，第四区域为不导电粘合区域。由此，在第一联接点和第二联接点存在对准错位的情况下，利用第二区域和第三区域增加了两个联接点之间的有效导电面积，利用第四区域增强了粘合效果，从而提高了互联可靠性；该互联方法允许存在对准误差，提升了良率和降低了成本。

显示装置及其制造方法

提供了一种显示装置及其制造方法，所述显示装置可以包括设置在基底上的导电图案。钝化层可以设置在导电图案上。可以设置在钝化层上的第一屏蔽电极和第二屏蔽电极可以彼此间隔开。第一电极可以设置在第一屏蔽电极上。第二电极可以设置在第二屏蔽电极上。发光元件可以电连接在第一电极与第二电极之间。第一屏蔽电极与第二屏蔽电极之间的第一距离可以小于第一电极与第二电极之间的第二距离。

显示装置

提供了一种显示装置，所述显示装置包括：第一电极和第二电极，彼此间隔开；发光元件，设置在第一电极与第二电极之间；第一连接电极，电接触第一电极和发光元件的第一端部；第二连接电极，电接触第二电极和发光元件的第二端部；以及导电图案，设置在第一连接电极与第二连接电极之间。导电图案的第一端部电接触第一连接电极，导电图案的第二端部电接触第二连接电极。

显示装置

显示装置包括：电源线；栅极线，分别在平面图上沿第一方向延伸且沿第二方向排列；像素，连接于电源线及栅极线；以及垂直线，分别在平面图上沿第二方向延伸且沿第一方向排列。其中，垂直线包括栅极连接线以及布置于栅极连接线之间的虚设线。栅极连接线将栅极线连接于栅极驱动部。虚设线连接于电源线。将栅极连接线中的至少一条置于其之间而隔开的虚设线之间的间距整体恒定。

复合ic装置结构的部件中的绝热互连特征

一种复合集成电路(IC)结构至少包括与第二IC管芯堆叠的第一IC管芯。每一管芯具有装置层以及互连至所述装置层的晶体管并且终止于特征处的金属化层。第一IC管芯的第一特征主要具有第一成分，所述第一成分具有第一微结构。第二IC管芯的第二特征主要具有第二成分或者第二微结构。第二特征中的第一个与第一特征中的一个直接接触。第二成分具有的热导率比第一成分和第一微结构的热导率低至少一个数量级。第一成分具有的热导率可以是第二成分或第二微结构的热导率的至少40倍。

Led显示装置

本申请涉及一种LED显示装置，更具体地，涉及一种包括用于劣化像素的修复结构的LED显示装置。本发明旨在将子微型LED堆叠并设置在已发生劣化的微型LED上，其中，子微型LED电联接至向微型LED施加电压的第一和第二连接电极。因此，可以防止由于劣化的像素而导致的显示质量的劣化，并且由于不需要另外去除已发生劣化的微型LED，因此可以降低工艺成本并提高工艺效率。

显示装置

显示装置包括：基板，包括显示区域以及包围显示区域的周边区域；多个焊盘，配置在基板的周边区域的第一方向上，并且在与第一方向垂直的第二方向上排列多个焊盘；以及电路膜，配置在焊盘上。各个焊盘包括：信号布线，配置在基板上；第一虚设图案，在基板上，在第一方向上与信号布线间隔开来配置第一虚设图案；以及第一绝缘图案，在基板上配置在信号布线与第一虚设图案之间。

微型led元件搭载基板以及使用其的显示装置

微型LED元件搭载基板具备：基板(1)，具有微型LED元件的搭载面(1a)；和作为显示单位的像素部(15)，被配置于搭载面(1a)侧，包含发光颜色不同的多个微型LED元件(74R、74G、74B)，微型LED元件(74R、74G、74B)是将第1电极(61R、61G、61B)、发光层(74RL、74GL、74BL)、第2电极(62R、62G、62B)层叠而成的纵型LED元件，在像素部(15)之中配置有与多个第2电极(62R、62G、62B)分别连接的电源电极焊盘(60S)，电源电极焊盘(60S)与多个第1电极(61R、61G、61B)的各距离(L1、L2、L3)比多个第1电极(61R、61G、61B)的相邻间距离(L4、L5)长。

导热性片及其制造方法、导热性片的安装方法

本发明提供与电子部件的密合性、操作性和再加工性优异的导热性片及其制造方法、导热性片的安装方法。具有至少包含高分子基质成分和导热性填充剂的导热性树脂组合物固化而成的片主体(2)，导热性填充剂相对于高分子基质成分的体积比例为1.00～1.70，导热性填充剂包含纤维状导热性填充剂(10)，纤维状导热性填充剂(10)从片主体(2)的表面突出，并且被高分子基质成分的未固化成分被覆。

Display device

A display device includes a substrate including a display area and a peripheral area surrounding the display area, a plurality of pads in a first direction of the peripheral area of the substrate and in a second direction perpendicular to the first direction, and a circuit film on the pads. Each of the pads includes a signal line on the substrate, a first dummy pattern on the substrate and spaced apart from the signal line in the first direction, and a first insulating pattern between the signal line and the first dummy pattern on the substrate.

Display device

A display device includes a substrate including a display area and a peripheral area surrounding the display area, a plurality of pads in a first direction of the peripheral area of the substrate and in a second direction perpendicular to the first direction, and a circuit film on the pads. Each of the pads includes a signal line on the substrate, a first dummy pattern on the substrate and spaced apart from the signal line in the first direction, and a first insulating pattern between the signal line and the first dummy pattern on the substrate.

Underfill composition for encapsulating a bond line

An underfill composition for encapsulating a bond line and a method of using the underfill composition are described. Advantageously, the disclosed underfill composition in an uncured state has a fluidity value of less than about ten minutes over about a two centimeter distance at a temperature of about 90 degrees C. and at a bond line thickness of about 50 microns or less and still have a bulk thermal conductivity that is greater than about 0.8 W/mK in the cured state.

Chip package and method for forming the same

A chip package is provided. The chip package includes a substrate having a first surface and a second surface opposite thereto. A dielectric layer is disposed on the first surface of the substrate and includes a conducting pad structure. A first opening penetrates the substrate and exposes a surface of the conducting pad structure. A second opening is communication with the first opening and penetrates the conducting pad structure. A redistribution layer is conformally disposed on a sidewall of the first opening and the surface of the conducting pad structure and is filled into the second opening. A method for forming the chip package is also provided.

相变材料

在一个示例性实施方案中，热界面材料包含至少一种聚合物、至少一种相变材料、至少一种交联剂和至少一种导热填料。所述至少一种导热填料包含颗粒直径为约1微米或更小的多个第一颗粒。所述至少一种导热填料占热界面材料总重量的至少80重量％。还提供了用于形成热界面材料的配制物和包含热界面材料的电子部件。