Finnendiodenstruktur und deren Verfahren

Verfahren und Struktur zum Ausbilden einer Finnenbodendiode schließt die Bereitstellung eines Substrats ein, aus dem sich mehrere Finnen erstrecken. Jede der mehreren Finnen enthält einen Substratanteil und einen Epitaxialschichtanteil über dem Substratanteil. Eine erste Dotiersubstanzschicht wird auf Seitenwänden eines ersten Bereichs des Substratanteils von jeder der mehreren Finnen ausgebildet. Nach Ausbilden der ersten Dotiersubstanzschicht wird ein erster Temperprozess ausgeführt, um einen ersten Diodenbereich innerhalb des ersten Bereichs des Substratanteils zu bilden. Eine zweite Dotiersubstanzschicht wird auf Seitenwänden eines zweiten Bereichs des Substratanteils von jeder der mehreren Finnen ausgebildet. Nach Ausbilden der zweiten Dotiersubstanzschicht wird ein zweiter Temperprozess ausgeführt, um einen zweiten Diodenbereich innerhalb des zweiten Bereichs des Substratanteils von jeder der mehreren Finnen auszubilden.

PHOTOMASK AND METHOD OF FORMING THE SAME

A method for forming a photomask includes the following steps. A substrate is provided, which has a pattern region and a peripheral region surrounding the pattern region. A first etching operation is performed on a first surface of the substrate to remove first portions of the substrate in the pattern region, so as to form recesses in the pattern region of the substrate. A blasting operation is performed on the first surface of the substrate. A BARC layer is formed filling the recesses and over the first surface of the substrate. A second etching operation is performed on a second surface of the substrate opposite to the first surface until portions of the BARC layer in the recesses are exposed. The BARC layer is removed after the second etching operation, so as to form openings in the substrate in the pattern region. 1. A method of forming a photomask , the method comprising:providing a substrate having a pattern region and a peripheral region surrounding the pattern region;performing a first etching operation on a first surface of the substrate to remove first portions of the substrate in the pattern region, thereby forming a plurality of recesses in the pattern region of the substrate;performing a blasting operation on the first surface of the substrate;forming a bottom anti-reflective coating (BARC) layer filling the recesses and over the first surface of the substrate;performing a second etching operation on a second surface of the substrate opposite to the first surface until portions of the BARC layer in the recesses are exposed; andremoving the BARC layer, thereby forming openings in the substrate in the pattern region.2. The method of claim 1 , wherein the substrate is formed from quartz.3. The method of claim 1 , wherein performing the second etching operation comprises:forming a patterned photoresist on the second surface of the substrate in the peripheral region;removing a second portion of the substrate in the pattern region and the portions of the BARC ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a semiconductor substrate, a capacitor, and an interconnection layer. The capacitor is over the semiconductor substrate and includes a bottom electrode, a top electrode, and an insulator layer. The top electrode has a top surface and a bottom surface rougher than the top surface of the top electrode. The insulator layer is between the bottom electrode and the top electrode. The interconnection layer is over the semiconductor substrate and is electrically connected to the capacitor.

Barrier structure for copper interconnect

A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming an opening in the dielectric layer, forming a metal-containing layer overlying the opening in the dielectric layer, forming a conformal protective layer overlying the metal-containing layer, filling a conductive layer in the opening, and performing a thermal process to form a metal oxide layer barrier layer underlying the metal-containing layer.

Verfahren zum Beurteilen von Eigenschaften einer ionenimplantierten Probe

Ein Verfahren zum Beurteilen von Eigenschaften eines Werkstücks enthält ein Bilden einer lichtempfindlichen Schicht auf dem Werkstück. Dann wird eine Ionenimplantation an dem Werkstück durchgeführt. Das Werkstück wird bestrahlt und eine optische Intensität des lichtempfindlichen Materials auf dem Werkstück wird berechnet. Das Ionenimplantationsmuster wird anhand der optischen Intensität beurteilt. Eine chemische Struktur des lichtempfindlichen Materials ändert sich bei Ionenimplantation. Das Werkstück wird durch Umkehr der chemischen Struktur des lichtempfindlichen Materials oder Entfernen des ionenunterbrochenen lichtempfindlichen Materials durch Chemikalien wiederhergestellt.

Reverse-tone mask method for post-cmp elimination of copper overburden humps

A novel reverse-tone mask method which is capable of eliminating metal overburden humps in a metal layer electroplated onto a substrate, is disclosed. Typically, the method includes providing a masking layer on a metal layer such as copper previously electroplated onto a substrate; depositing a photoresist layer on the masking layer; patterning the photoresist layer according to the size and location of the largest metal overburden humps in the metal layer; exposing the overburden humps by etching the masking layer according to the patterned photoresist layer; stripping the photoresist layer from the masking layer; subjecting the metal overburden humps to a first CMP or reverse electroplating process; removing the masking layer from the metal layer; and subjecting the metal layer to a second CMP or reverse electroplating process.

Kontaktstrukturen und Verfahren ihrer Ausbildung

Ausführungsformen der vorliegenden Offenbarung umfassen Kontaktstrukturen und Verfahren zum Ausbilden derselben. Eine Ausführungsform besteht aus einem Verfahren zum Ausbilden einer Halbleitervorrichtung, wobei das Verfahren das Ausbilden eines Kontaktbereichs über einem Substrat, das Ausbilden einer dielektrischen Schicht über dem Kontaktbereich und dem Substrat und das Ausbilden einer Öffnung durch die dielektrische Schicht umfasst, um Abschnitte des Kontaktbereichs freizulegen. Das Verfahren umfasst weiter das Ausbilden einer Metall-Silizid-Schicht auf den freigelegten Abschnitten des Kontaktbereichs und entlang Seitenwänden der Öffnung; und Füllen der Öffnung mit einem leitenden Material, um einen leitenden Stöpsel in der dielektrischen Schicht auszubilden, wobei der leitenden Stöpsel mit dem Kontaktbereich elektrisch verbunden ist.

Metal-semiconductor contact structure with doped interlayer

Disclosed herein is a method of forming a metal-to-semiconductor contact with a doped metal oxide interlayer. An insulating layer is formed on a top surface of a semiconductor substrate with target region at the top surface of the semiconductor substrate. An opening is etched through the insulating layer with the opening exposing a top surface of a portion of the target region. A doped metal oxide interlayer is formed in the opening and contacts the top surface of the target region. The remainder of the opening is filled with a metal plug, the doped metal oxide interlayer disposed between the metal plug and the substrate. The doped metal oxide interlayer is formed from one of tin oxide, titanium oxide or zinc oxide and is doped with fluorine.

Gamma ray generator

One of gamma ray lithography systems includes a gamma ray generator and a wafer stage. The gamma ray generator is configured to generate a substantially uniform gamma ray. The gamma ray generator includes a plurality of gamma ray sources and a rotational carrier. The rotational carrier is configured to hold the gamma ray sources and rotate along a rotational axis. The wafer stage is disposed below the gamma ray generator and configured to secure a wafer.

Probe Card for Simultaneously Testing Multiple Dies

In accordance with an embodiment, a probe card comprises a contact pad interface comprising front side contacts and back side contacts electrically coupled together. The front side contacts are arranged to simultaneously electrically couple respective bumps of a plurality of dies on a wafer, and the back side contacts are arranged to electrically couple respective contacts of a testing structure.

CONDUCTIVE POWDER FORMATION METHOD, DEVICE FOR FORMING CONDUCTIVE POWDER, AND METHOD OF FORMING SEMICONDUCTOR DEVICE

A method of forming a conductive powder includes reducing, by a reduction reaction, a conductive powder precursor gas using a plasma. Reducing the conductive powder precursor gas forms the conductive powder. The method further includes filtering the conductive powder based on particle size. The method further includes dispersing a portion of the conductive powder having a particle size below a threshold value in a fluid. 1. A method of forming a conductive powder , the method comprising:reducing, by a reduction reaction, a conductive powder precursor gas using a plasma to form the conductive powder;filtering the conductive powder based on particle size; anddispersing a portion of the conductive powder having a particle size below a threshold value in a fluid.2. The method of claim 1 , further comprising preheating the conductive powder precursor gas prior to the reducing of the conductive powder precursor gas.3. The method of claim 1 , further comprising performing an ultrasonic vibration on a reaction chamber simultaneously with the reducing of the conductive powder precursor gas in the reaction chamber.4. The method of claim 1 , wherein the filtering of the conductive powder comprises performing at least one of an electro-static collector (ESC) process or a centrifugal process.5. The method of claim 1 , wherein the dispersing of the conductive powder in the fluid comprises dispersing the conductive powder in a fluid free of oxygen.6. The method of claim 1 , wherein the dispersing of the conductive powder in the fluid comprises dispersing the conductive powder in a solvent including methane claim 1 , acetone or isopropyl alcohol.7. The method of claim 1 , wherein the reducing of the conductive powder precursor gas comprises reducing the conductive powder precursor gas comprising a conductive-material organic compound.8. The method of claim 1 , wherein the reducing of the conductive powder precursor gas comprises reducing the conductive powder precursor gas ...

Method for forming a high density dielectric film by chemical vapor deposition

A method for forming a high density dielectric film by chemical vapor deposition. The method comprises: (a) a substrate is provided in a processing chamber; (b) a first gas is introduced into the processing chamber with a first pressure and adsorbed on the substrate, wherein the first gas comprises silicon-containing or carbon-containing gas; (c) the first gas is stopped, and the first pressure is lowered to a second pressure; (d) a second gas is introduced into the processing chamber with a third pressure, and forced to react with the first gas absorbed on the substrate and remained in the processing chamber, wherein the second gas comprises oxidizer or reduction agent; (e) the steps (b)~(d) are repeated until a high density dielectric film is formed on the substrate.

Two-step shallow trench isolation (STI) process

Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel.

Metal-semiconductor contact structure with doped interlayer

Disclosed herein is a method of forming a metal-to-semiconductor contact with a doped metal oxide interlayer. An insulating layer is formed on a top surface of a semiconductor substrate with target region at the top surface of the semiconductor substrate. An opening is etched through the insulating layer with the opening exposing a top surface of a portion of the target region. A doped metal oxide interlayer is formed in the opening and contacts the top surface of the target region. The remainder of the opening is filled with a metal plug, the doped metal oxide interlayer disposed between the metal plug and the substrate. The doped metal oxide interlayer is formed from one of tin oxide, titanium oxide or zinc oxide and is doped with fluorine.

Method of evaluating characteristics of ion implanted sample

A method of evaluating characteristics of a work piece includes forming a photosensitive layer on the work piece. Then an ion implantation is performed on the work piece. The work piece is radiated, and an optical intensity of the photosensitive material on the work piece is calculated. The ion implantation pattern is evaluated according to the optical intensity. A chemical structure of the photosensitive material is changed upon the ion implantation. The work piece is recovered by reversing the chemical structure of the photosensitive material or removing the ion interrupted photosensitive material by chemicals.

Dielectric layer, interconnection structure using the same, and manufacturing method thereof

A method for manufacturing a dielectric layer includes forming a first dielectric film over a substrate. A first porogen is deposited over the first dielectric film. A second dielectric film is formed on and in contact with the first dielectric film and the first porogen. The first porogen is removed.

Method of forming semiconductor device

A method of forming a semiconductor device is disclosed herein. The method includes: forming at least one opening in a dielectric material; depositing a graphene layer in the at least one opening; filling the at least one opening with a conductive powder dispersed in a fluid, wherein the fluid comprises at least one of methane, isopropyl alcohol, acetone, or ethyl acetate; melting the conductive powder.

Two-step shallow trench isolation (STI) process

An integrated circuit device and a process for making the integrated circuit device. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel.

APPARATUS AND METHOD FOR PROCESSING WAFER

An apparatus for processing a wafer includes a process chamber, a wafer support, a heat source, and a movable device. The wafer support is in the process chamber. The heat source is in the process chamber. The movable device contacts the heat source, in which the movable device is movable with respect to the wafer support. 1. An apparatus for processing a wafer , comprising:a process chamber;a wafer support in the process chamber;a heat source in the process chamber and comprising a lamp socket configured to be coupled to a lamp; and a stator that is stationary with respect to the wafer support; and', 'a lift pin that is movable with respect to the stator and that abuts the lamp socket., 'a movable device comprising25-. (canceled)6. The apparatus of claim 1 , wherein the lamp socket has opposite first and second end surfaces that are arranged along a first direction claim 1 , the second end surface of the lamp socket is configured to be coupled to the lamp claim 1 , and the lift pin is movable along a second direction perpendicular to the first direction.7. The apparatus of claim 6 , wherein the lift pin abuts a side surface of the lamp socket between the first and second end surfaces of the lamp socket.8. The apparatus of claim 7 , further comprising a pivot connected to the first end surface of the lamp socket and the process chamber so as to permit movement of the lamp socket along a curved line with respect to the process chamber.9. The apparatus of claim 1 , further comprising: a base supporting the movable device and coupled pivotally to the lamp socket of the heat source; and', 'a lifting device abutting the base and configured to move the base with respect to the wafer support., 'a level-adjusting device comprising10. An apparatus for processing a wafer claim 1 , comprising:a process chamber;a wafer support in the process chamber;a heat source in the process chamber; anda movable device comprising a step motor having an output rod, wherein the heat source is ...

Metall-Halbleiter-Kontaktstruktur mit dotierter Zwischenschicht

Es ist ein Verfahren offenbart zum Ausbilden eines Metall-Halbleiter-Kontakts mit einer dotierten Metalloxid-Zwischenschicht. Eine Isolierschicht wird auf einer oberen Fläche eines Halbleitersubstrats ausgebildet, wobei ein Zielbereich an der oberen Fläche des Halbleitersubstrats liegt. Eine Öffnung wird durch die Isolierschicht geätzt, wobei die Öffnung eine obere Fläche eines Teils des Zielbereichs freilegt. Eine dotierte Metalloxid-Zwischenschicht wird in der Öffnung ausgebildet und kontaktiert die obere Fläche des Zielbereichs. Der Rest der Öffnung wird mit einem Metallzapfen gefüllt, wobei die dotierte Metalloxid-Zwischenschicht zwischen dem Metallzapfen und dem Substrat angeordnet ist. Die dotierte Metalloxid-Zwischenschicht wird aus entweder Zinnoxid, Titanoxid oder Zinkoxid ausgebildet und ist mit Fluor dotiert.

Electrostatic chuck with multi-zone control

An electrostatic chuck for clamping a warped workpiece has a clamping surface comprising a dielectric layer. The dielectric layer has a field and one or more zones formed of differing dielectric materials. One or more electrodes are coupled to a power supply, and a controller controls a clamping voltage supplied to the one or more electrodes via the power supply. An electrostatic attraction force associated with each of the field and one or more zones of the dielectric layer of the electrostatic chuck is induced, wherein the electrostatic attraction force varies based on the dielectric material of each of the field and one or more zones. The electrostatic attraction force is greater in the one or more zones than in the field, therein attracting warped regions of the workpiece to the clamping surface and clamping the warped workpiece to the clamping surface across a surface of the warped workpiece.

Contact structures and methods of forming the same

Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.

Method for detecting alignment mark shielding

A method of testing a test wafer includes shielding test centers on a test wafer using shielding tabs during the deposition of a layer. The test wafer has the same size and shape of product wafers. The shielding tabs are then removed from the test wafer. A plurality of predetermined points which are separated from each test center by a critical interval are checked, and whether each point is covered by the layer is determined through an interferometer or a microprobe. The test wafer is processed after adjustments to or maintenance on equipment, or after a fixed number of product wafers have been processed.

POLISHING SYSTEM AND POLISHING METHOD

A polishing system for polishing a semiconductor wafer includes a wafer support for holding the semiconductor wafer, and a first polishing pad for polishing a region of the semiconductor wafer. The semiconductor wafer has a first diameter, and the first polishing pad has a second diameter shorter than the first diameter. 1. A polishing system for polishing a semiconductor wafer comprising:a wafer support for holding the semiconductor wafer, the semiconductor wafer having a first diameter; anda first polishing pad for polishing a region of the semiconductor wafer, the first polishing pad having a second diameter shorter than the first diameter.2. The polishing system of claim 1 , wherein the wafer support is a wafer table.3. The polishing system of claim 1 , wherein the wafer support is a polishing head.4. The polishing system of claim 1 , further comprising:a pad positioning mechanism for moving the first polishing pad in three dimensions relative to a surface of the semiconductor wafer.5. The polishing system of claim 1 , further comprising:a slurry supply system for introducing slurry to the region of the semiconductor wafer.6. The polishing system of claim 1 , wherein the first polishing pad is a bevel polishing pad claim 1 , and the region is a bezel of the semiconductor wafer.7. The polishing system of claim 1 , wherein the region is a ring region approximately concentric to the semiconductor wafer and having an outer radius shorter than an outer radius of the semiconductor wafer.8. The polishing system of claim 1 , further comprising:a second polishing pad for polishing a second region of the semiconductor wafer, the second polishing pad having a third diameter shorter than or equal to about one quarter the first diameter;wherein the second diameter of the first polishing pad is shorter than or equal to about one quarter the first diameter.9. The polishing system of claim 8 , wherein:the region is a first ring region approximately concentric to the ...

Die Edge Contacts for Semiconductor Devices

A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like. 1. A semiconductor structure comprising:an integrated circuit substrate having a contact pad formed thereon;a passivation layer formed over the substrate, the passivation layer exposing at least a portion of the contact pad and having a trench from the contact pad to an edge of the substrate; anda conductive material filling the trench of the passivation layer to form a die-edge contact.2. The semiconductor structure of claim 1 , further comprising a through-substrate via on the edge of the substrate such that the die-edge contact comprises the through-substrate via.3. The semiconductor structure of claim 1 , further comprising an inner connection structure claim 1 , the inner connection structure having a plurality of inner connection substrates perpendicular to the integrated circuit substrate claim 1 , at least one of the inner connection substrates having a contact pads electrically coupled to the die-edge contact.4. The semiconductor structure of claim 3 , wherein the inner connection structure comprises die supports.5. The semiconductor ...

Integrated circuit device and method for fabricating the same

An integrated circuit device and a method for fabricating the same are provided. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel.

PVD apparatus and method with deposition chamber having multiple targets and magnets

A thin film deposition system and method provide for multiple target assemblies that may be separately powered. Each target assembly includes a target and associated magnet or set of magnets. The disclosure provides a tunable film profile produced by multiple power sources that separately power the target arrangements. The relative amounts of power supplied to the target arrangements may be customized to provide a desired film and may be varied in time to produce a film with varied characteristics.

GAMMA RAY GENERATOR, GAMMA RAY LITHOGRAPHY SYSTEM AND METHOD OF PERFORMING GAMMA RAY LITHOGRAPHY

One of gamma ray lithography systems includes a gamma ray generator and a wafer stage. The gamma ray generator is configured to generate a substantially uniform gamma ray. The gamma ray generator includes a plurality of gamma ray sources and a rotational carrier. The rotational carrier is configured to hold the gamma ray sources and rotate along a rotational axis. The wafer stage is disposed below the gamma ray generator and configured to secure a wafer. 1. A gamma ray generator , comprising: a main body; and', 'a plurality of holes in the main body; and, 'a rotational carrier, configured to rotate along a rotational axis, comprisinga plurality of gamma ray sources, respectively placed in the holes and radiating gamma rays through bottom openings of the holes.2. The gamma ray generator of claim 1 , wherein a diameter of a top opening opposite to the bottom opening of the hole is not less than a diameter of the gamma ray source claim 1 , and a diameter of the bottom opening is less than a diameter of the gamma ray source.3. The gamma ray generator of claim 1 , wherein the main body is a circular plate claim 1 , and the holes are arranged in a matrix.4. The gamma ray generator of claim 1 , wherein the main body includes a shaft and a plurality of holders connecting to the shaft claim 1 , and the holders have the holes respectively.5. The gamma ray generator of claim 1 , wherein a diameter of the bottom opening of the hole decreases as the hole becomes closer to the rotational axis.6. The gamma ray generator of claim 1 , wherein a separation between the holes increases as the holes becomes closer to the rotational axis.7. The gamma ray generator of claim 1 , wherein the bottom openings of the holes have substantially the same diameter.8. The gamma ray generator of claim 1 , wherein the gamma ray sources are metal radiative ingots claim 1 , metal radiative pills or metal radiative blocks.9. A gamma ray lithography system claim 1 , comprising: a plurality of gamma ray ...

ZUSAMMENGESETZTE KONTAKTSTÖPSEL-STRUKTUR UND VERFAHREN ZUR HERSTELLUNG

Ein Kontaktstöpsel einer Ausführungsform umfasst eine Zwei-Schichten-Struktur und eine Diffusionsbarriere-Schicht und eine Bodenfläche der Zwei-Schichten-Struktur. Die Zwei-Schichten-Struktur umfasst einen leitenden Kern und eine leitende Auskleideschicht auf einer Seitenwand und einer Bodenfläche des leitenden Kerns. Bei dem Kontaktstöpsel der Ausführungsform umfasst die leitende Auskleideschicht Kobalt oder Ruthenium.

SHIELDING DESIGN FOR METAL GAP FILL

The present disclosure is directed to a physical vapor deposition system configured to heat a semiconductor substrate or wafer. In some embodiments the disclosed physical vapor deposition system comprises at least one heat source having one or more lamp modules for heating of the substrate. The lamp modules may be separated from the substrate by a shielding device. In some embodiments, the shielding device comprises a one-piece device or a two piece device. The disclosed physical vapor deposition system can heat the semiconductor substrate, reflowing a metal film deposited thereon without the necessity for separate chambers, thereby decreasing process time, requiring less thermal budget, and decreasing substrate damage. 1. A method for heating a substrate in a physical vapor deposition process chamber , comprising:supporting a substrate on a pedestal housed within a process chamber;forming target atoms on a surface of the substrate; andheating the surface of the substrate using a radiant heat source during or after forming the target atoms on the surface.2. The method of claim 1 , further comprising:providing a shielding device at a first position that blocks energy from the radiant heat source from reaching the surface of the substrate during forming the target atoms on the surface; andmoving the shielding device to a second position that enables energy from the radiant heat source to reach the surface of the substrate after depositing the target atoms onto the surface.3. The method of claim 2 ,wherein the shielding device comprises an upper portion and a lower portion; andwherein a separation between the upper portion and the lower portion is different in the first position than in the second position.4. The method of claim 2 , further comprising:returning the shielding device from the second position back to the first position; andcooling the substrate by reducing a temperature of the pedestal after the shielding device has been returned to the first position.5. ...

Semiconductor film formation apparatus and process

An apparatus and method are disclosed for forming thin films on a semiconductor substrate. The apparatus in one embodiment includes a process chamber configured for supporting the substrate, a gas excitation power source, and first and second gas distribution showerheads fluidly coupled to a reactive process gas supply containing film precursors. The showerheads dispense the gas into two different zones above the substrate, which is excited to generate an inner plasma field and an outer plasma field over the wafer. The apparatus deposits a material on the substrate in a manner that promotes the formation of a film having a substantially uniform thickness across the substrate. In one embodiment, the substrate is a wafer. Various embodiments include first and second independently controllable power sources connected to the first and second showerheads to vary the power level and plasma intensity in each zone.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes a non-insulator structure, at least one carbon nano-tube (CNT), a dielectric layer, and a graphene-based conductive layer. The CNT is over the non-insulator structure. The dielectric layer surrounds the CNT. The graphene-based conductive layer is over the at least one CNT. The CNTs and the graphene-based conductive layer have low resistance. 1. A semiconductor device , comprising:a non-insulator structure formed in one of a source/drain region and a gate structure;at least one carbon nano-tube (CNT) over the non-insulator structure;a dielectric layer surrounding the CNT; anda graphene-based conductive layer over the at least one CNT.2. The semiconductor device of claim 1 , further comprising:a conductive material filling interspaces between a plurality of the at least one CNTs.3. The semiconductor device of claim 2 , wherein the non-insulator structure comprises a metal silicide claim 2 , and the metal silicide and the conductive material comprise the same metal.4. The semiconductor device of claim 1 , further comprising:a catalyst layer between the at least one CNT and the non-insulator structure.5. The semiconductor device of claim 4 , wherein the catalyst layer and the non-insulator structure comprise the same metal.6. The semiconductor device of claim 1 , further comprising:a catalyst layer between the graphene-based conductive layer and the at least one CNT.7. The semiconductor device of claim 6 , wherein the catalyst layer wraps around the graphene-based conductive layer.8. The semiconductor device of claim 1 , further comprising:a conductor, wherein the graphene-based conductive layer wraps around the conductor.9. The semiconductor device of claim 8 , wherein a top surface of the conductor is substantially level with an end surface of the graphene-based conductive layer.10. A semiconductor device claim 8 , comprising:a non-insulator structure;a carbon nano-tube (CNT) electrically connected to the non-insulator structure;a first ...

Fin diode structure and methods thereof

A method and structure for forming a fin bottom diode includes providing a substrate having a plurality of fins extending therefrom. Each of the plurality of fins includes a substrate portion and an epitaxial layer portion over the substrate portion. A first dopant layer is formed on sidewalls of a first region of the substrate portion of each of the plurality of fins. After forming the first dopant layer, a first annealing process is performed to form a first diode region within the first region of the substrate portion. A second dopant layer is formed on sidewalls of a second region of the substrate portion of each of the plurality of fins. After forming the second dopant layer, a second annealing process is performed to form a second diode region within the second region of the substrate portion of each of the plurality of fins.

Semiconductor device including shallow trench isolator and method of forming same

A semiconductor device and method of manufacturing include an STI trench having a low-k dielectric material as a liner oxide layer and a bulk oxide trench fill layer.

Reverse damascene process

The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure.

Method for silicide formation

Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.

Ultra-low oxygen and humility loadport and stocker system

One or more pods for adjusting at least one of an oxygen content or a water content therein and methods of their use are provided, where one or more semiconductor wafer are selectively stored within a storage chamber of the pod. The pod comprises a storage chamber having a side wall surface defining an opening at one side thereof and a pod door fitted to the storage chamber at the opening so as to provide ingress and egress to the storage chamber. The pod door comprises a door body, a first door locking mechanism on the door body and a seal band configured to engage the sidewall surface. The first door locking mechanism comprises a first pressure applicator, a first key assembly and a first connector-rod.

Die edge contacts for semiconductor devices

A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like.

Verfahren zum Ausbilden einer Halbleitervorrichtung und Verfahren zum Ausbilden einer Kontaktstruktur

Verfahren zum Ausbilden einer Halbleitervorrichtung, wobei das Verfahren Folgendes umfasst: Ausbilden eines Kontaktbereichs über einem Substrat; Ausbilden einer dielektrischen Schicht über dem Kontaktbereich und dem Substrat; Ausbilden einer Öffnung durch die dielektrische Schicht, um Abschnitte des Kontaktbereichs freizulegen; Ausbilden einer Metall-Silizid-Schicht auf den freigelegten Abschnitten des Kontaktbereichs und entlang Seitenwänden der Öffnung; wobei die Metall-Silizid-Schicht eine erste Dicke entlang des Kontaktbereichs und eine zweite Dicke entlang der Seitenwände der Öffnung aufweist, wobei die erste Dicke von etwa 3 Nanometer (nm) bis etwa 30 nm und die zweite Dicke von etwa 0,3 nm bis etwa 3 nm reicht, und Füllen der Öffnung mit einem leitenden Material, um einen leitenden Stöpsel in der dielektrischen Schicht auszubilden, wobei der leitende Stöpsel mit dem Kontaktbereich elektrisch verbunden ist.

METHOD OF EVALUATING CHARACTERISTICS OF ION IMPLANTED SAMPLE

A method of evaluating characteristics of a work piece includes forming a photosensitive layer on the work piece. Then an ion implantation is performed on the work piece. The work piece is radiated, and an optical intensity of the photosensitive material on the work piece is calculated. The ion implantation pattern is evaluated according to the optical intensity. A chemical structure of the photosensitive material is changed upon the ion implantation. The work piece is recovered by reversing the chemical structure of the photosensitive material or removing the ion interrupted photosensitive material by chemicals. 1. A method of evaluating characteristics of a work piece , comprising:forming a photosensitive layer on a substrate to form the work piece;performing ion implantation on the work piece;radiating the work piece after performing the ion implantation; and 'measuring a refractive index difference of the photosensitive layer.', 'calculating an optical intensity of the work piece due to radiating the workpiece, wherein calculating the optical intensity of the work piece comprises2. The method of evaluating characteristics of a work piece according to claim 1 , wherein performing ion implantation on the work piece comprises:changing a chemical structure of the photosensitive layer.3. The method of evaluating characteristics of a work piece according to claim 1 , wherein:performing ion implantation on the work piece comprises changing a chemical structure of the photosensitive layer from a first state to a second state, andthe method comprises recovering the chemical structure of the photosensitive layer from the second state to the first state after calculating the optical intensity of the work piece.4. The method of evaluating characteristics of a work piece according to claim 3 , wherein recovering the chemical structure of the photosensitive layer comprises heating the work piece.5. The method of evaluating characteristics of a work piece according to claim 1 ...

Manufacturing method of semiconductor device

Wafer pod handling method

A method for wafer pod handling includes at least the following steps. A wafer pod is moved into a load chamber by conveying the wafer pod to the load chamber via one side of a track and removing a cover of the load chamber via an opposing side of the track. The wafer pod that is inside the load chamber is coupled to a port of a platform that is linked to the load chamber. A wafer to be processed is moved from the wafer pod and out of the load chamber to the platform for performing a semiconductor process. Other methods for wafer pod handling are also provided.

Method for forming semiconductor structure

A method for forming a semiconductor structure is provided. The method includes depositing a hard mask layer over a substrate. The method further includes depositing a silver precursor layer over the hard mask layer. The method further includes exposing portions of the silver precursor layer to a radiation, the radiation causing a reduction of silver ions in the irradiated portions of the silver precursor layer. The method further includes removing non-irradiated portions of the silver precursor layer, resulting in a plurality of silver seed structures.

Metal contact structure and method of forming the same in a semiconductor device

A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.

TWO-STEP SHALLOW TRENCH ISOLATION (STI) PROCESS

An integrated circuit device and a process for making the integrated circuit device. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel.

Apparatus and method for processing wafer

A method includes delivering a wafer into a process chamber, applying a thermal energy to the wafer by a heat source, and moving the heat source substantially along a longitudinal direction of the heat source with respect to the wafer. An apparatus that performs the method is also disclosed.

SEMICONDUCTOR DEVICE HAVING INTERFACIAL LAYER AND HIGH K DIELECTRIC LAYER

A transistor includes a channel region, a gate stack, and source and drain structures. The channel region comprises silicon germanium and has a first silicon-to-germanium ratio. The gate stack is over the channel region and comprises a silicon germanium oxide layer over the channel region, a high-κ dielectric layer over the silicon germanium oxide layer, and a gate electrode over the high-κ dielectric layer. The silicon germanium oxide layer has a second silicon-to-germanium ratio. The second silicon-to-germanium ratio is substantially the same as the first silicon-to-germanium ratio. The channel region is between the source and drain structures. 1. A transistor comprising:a channel region comprising silicon germanium, wherein the channel region has a first silicon-to-germanium ratio; a silicon germanium oxide layer over the channel region, wherein the silicon germanium oxide layer has a second silicon-to-germanium ratio, and the second silicon-to-germanium ratio is substantially the same as the first silicon-to-germanium ratio;', 'a high-κ dielectric layer over the silicon germanium oxide layer; and', 'a gate electrode over the high-κ dielectric layer; and, 'a gate stack over the channel region, wherein the gate stack comprisessource and drain structures, wherein the channel region is between the source and drain structures.2. The transistor of claim 1 , wherein the silicon germanium oxide layer includes a portion soluble in water.3. The transistor of claim 2 , wherein said portion of the silicon germanium oxide layer soluble in the water comprises germanium.4. The transistor of claim 1 , further comprising:a pair of gate spacers respectively on opposite sidewalls of the silicon germanium oxide layer.5. A device comprising: a channel region;', a silicon germanium oxide layer over the channel region, wherein the silicon germanium oxide layer has a first silicon-to-germanium ratio;', 'a high-κ dielectric layer over the silicon germanium oxide layer; and', 'a gate ...

ZUSAMMENGESETZTE KONTAKTSTÖPSEL-STRUKTUR UND VERFAHREN ZUR HERSTELLUNG

Kontaktstöpsel (120), der Folgendes umfasst:eine Zwei-Schichten-Struktur (110), die Folgendes umfasst:einen leitenden Kern (110a); undeine leitende Auskleideschicht (110b) auf einer Seitenwand und einer Bodenfläche des leitenden Kerns (110a), wobei die leitende Auskleideschicht (110b) Kobalt oder Ruthenium umfasst;eine Diffusionsbarriere-Schicht (108) auf einer Seitenwand und einer Bodenfläche der Zwei-Schichten-Struktur (110); und einen leitenden Film (106) auf einer Seitenwand der Diffusionsbarriere-Schicht (108) umfasst, wobei die Diffusionsbarriere-Schicht (108) zwischen dem leitenden Film (106) und der Zwei-Schichten-Struktur (110) angeordnet ist und wobei gegenüberliegende Seitenwände der Zweischichten-Struktur (110) und der Diffusionsbarrieren-Schicht (108) nicht parallel sind.

Methods for detecting alignment mark shielding

A method of testing a test wafer includes shielding test centers on a test wafer using shielding tabs during the deposition of a layer. The test wafer has the same size and shape of product wafers. The shielding tabs are then removed from the test wafer. A plurality of predetermined points which are separated from each test center by a critical interval are checked, and whether each point is covered by the layer is determined through an interferometer or a microprobe. The test wafer is processed after adjustments to or maintenance on equipment, or after a fixed number of product wafers have been processed.

Semiconductor device, electrical device, fuel cell and the method of fabricating thereof

A structure having a cavity or enclosed space is fabricated by forming a recessed region in a surface of a substrate, and providing a first layer adjacent the recessed region. A liquid mixture including first and second components is supplied to the recessed region. The first component has a higher chemical affinity to the first layer than the second component such that the first component separates from the second component and adheres to an edge portion of the first layer. The substrate may then be heated to remove the second component from the recessed region through evaporation. As a result, the first component remains as a second layer adhering to the edge portion of the first layer and covering the recessed region, thereby defining a cavity or enclosed space with the recessed region. Unique structures including such cavities may be employed to realize a capacitor having a fluid, as opposed to solid, dielectric material, in order to increase the capacitance of the capacitor. Alternatively ...

ULTRA-LOW OXYGEN AND HUMILITY LOADPORT AND STOCKER SYSTEM

One or more pods for adjusting at least one of an oxygen content or a water content therein and methods of their use are provided, where one or more semiconductor wafer are selectively stored within a storage chamber of the pod. The pod comprises a storage chamber having a side wall surface defining an opening at one side thereof and a pod door fitted to the storage chamber at the opening so as to provide ingress and egress to the storage chamber. The pod door comprises a door body, a first door locking mechanism on the door body and a seal band configured to engage the sidewall surface. The first door locking mechanism comprises a first pressure applicator, a first key assembly and a first connector-rod. 1. A pod comprising:a storage chamber having a side wall surface defining an opening at one side thereof; and a door body;', a first pressure applicator;', 'a first key assembly; and', 'a first connector-rod; and, 'a first door locking mechanism on the door body, the first door locking mechanism comprising, 'a seal band configured to engage the sidewall surface., 'a pod door fitted to the storage chamber at the opening so as to provide ingress and egress to the storage chamber, the pod door comprising2. The pod of claim 1 , wherein the first key assembly is operatively connected to the first pressure applicator by the first connector-rod and actuatable to cause the first pressure applicator to engage the seal band to seal and unseal the pod door to and from a sidewall surface defining the opening in the storage chamber.3. The pod of claim 1 , comprising a second door locking mechanism comprising:a second pressure applicator;a second key assembly; anda second connector-rod;4. The pod of claim 1 , wherein the first pressure applicator comprises at least one of a pressure applicator rod or a pressure applicator ball.5. The pod of claim 4 , wherein at least one of the pressure applicator rod or the pressure applicator ball comprises a metal core coated with silicone.6. ...

Metall-Halbleiter-Kontaktstruktur mit dotierter Zwischenschicht und Herstellungsverfahren dafür

Verfahren zum Ausbilden einer Vorrichtung, das Folgendes umfasst: Ausbilden einer Isolierschicht (106) auf einer oberen Fläche eines Halbleitersubstrats (104), das mindestens eine aktive Vorrichtung aufweist, die darin ausgebildet ist, wobei ein Zielbereich (102) der mindestens einen aktiven Vorrichtung an der oberen Fläche des Halbleitersubstrats angeordnet ist; Ätzen einer Öffnung (202) durch die Isolierschicht, wobei die Öffnung den Zielbereich freilegt; Ausbilden einer Metalloxid-Zwischenschicht (402) in der Öffnung und in Kontakt mit dem Zielbereich; Dotieren der Metalloxid-Zwischenschicht mit einem ersten Dotiermittel (502); Ausbilden einer Haftschicht (602) in der Öffnung, die über der dotierten Metalloxid-Zwischenschicht angeordnet ist; Ausbilden eines Metallzapfens (702) in der Öffnung und über der Haftschicht, wobei die dotierte Metalloxid-Zwischenschicht zwischen dem Metallzapfen und dem Halbleitersubstrat angeordnet ist; und Ausbilden einer Redistribution-Layer (RDL) (1002) ...

Method of trimming fin structure

A method of trimming a fin structure includes the following operations: (i) forming a fin structure on a substrate; (ii) epitaxially growing an epitaxy structure cladding the fin structure, in which the epitaxy structure has a first lattice plane with Miller index (111), a second lattice plane with Miller index (100) and a third lattice plane with Miller index (110); and (iii) removing the epitaxy structure and a portion of the fin structure to obtain a trimmed fin structure.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a semiconductor substrate, a capacitor, and an interconnection layer. The capacitor is over the semiconductor substrate and includes a bottom electrode, a top electrode, and an insulator layer. The top electrode has a top surface and a bottom surface rougher than the top surface of the top electrode. The insulator layer is between the bottom electrode and the top electrode. The interconnection layer is over the semiconductor substrate and is electrically connected to the capacitor.

FIN DIODE STRUCTURE AND METHODS THEREOF

A method and structure for forming a fin bottom diode includes providing a substrate having a plurality of fins extending therefrom. Each of the plurality of fins includes a substrate portion and an epitaxial layer portion over the substrate portion. A first dopant layer is formed on sidewalls of a first region of the substrate portion of each of the plurality of fins. After forming the first dopant layer, a first annealing process is performed to form a first diode region within the first region of the substrate portion. A second dopant layer is formed on sidewalls of a second region of the substrate portion of each of the plurality of fins. After forming the second dopant layer, a second annealing process is performed to form a second diode region within the second region of the substrate portion of each of the plurality of fins.

Reverse tone mask method for post-CMP elimination of copper overburden

A novel reverse-tone mask method which is capable of eliminating metal overburden humps in a metal layer electroplated onto a substrate, is disclosed. Typically, the method includes providing a masking layer on a metal layer such as copper previously electroplated onto a substrate; depositing a photoresist layer on the masking layer; patterning the photoresist layer according to the size and location of the largest metal overburden humps in the metal layer; exposing the overburden humps by etching the masking layer according to the patterned photoresist layer; stripping the photoresist layer from the masking layer; subjecting the metal overburden humps to a first CMP or reverse electroplating process; removing the masking layer from the metal layer; and subjecting the metal layer to a second CMP or reverse electroplating process.

Damascene MIM capacitor structure with self-aligned oxidation fabrication process

A self aligned MIM capacitor structure and method for forming the same, the method including forming a metal filled damascene having an exposed surface in a dielectric insulating layer; forming a metal precursor layer on the exposed surface; carrying out a process on the metal precursor layer selected from the group consisting of oxidation and nitridation to form a capacitor dielectric portion; and, forming a conductive electrode on the capacitor dielectric portion.

Shielding design for metal gap fill

The present disclosure is directed to a physical vapor deposition system configured to heat a semiconductor substrate or wafer. In some embodiments the disclosed physical vapor deposition system comprises at least one heat source having one or more lamp modules for heating of the substrate. The lamp modules may be separated from the substrate by a shielding device. In some embodiments, the shielding device comprises a one-piece device or a two piece device. The disclosed physical vapor deposition system can heat the semiconductor substrate, reflowing a metal film deposited thereon without the necessity for separate chambers, thereby decreasing process time, requiring less thermal budget, and decreasing substrate damage.

Semiconductor processing station, semiconductor process and method of operating semiconductor processing station

A semiconductor processing station comprises a platform and a load port, wherein the platform includes an intake/outtake port and a plurality of processing modules. The load port includes a load chamber, a movable cover and a carrier transfer module. The load chamber communicates with the intake/outtake port and has a load opening at its top end for receiving a transport carrier within the load chamber. The movable cover is disposed at the load opening and is configured to seal the load opening. The carrier transfer module is configured to transfer the transport carrier to the intake/outtake port. A semiconductor process and a method of operating a semiconductor processing station are also provided.

Method for silicide formation

Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.

Method of fabricating photomask

A method of manufacturing a photomask includes depositing a first absorbing layer over a substrate, patterning the first absorbing layer using a photoresist, and depositing a conformal second absorbing layer along surfaces of the first absorbing layer.

Processing system and processing method

A processing system includes a machine, a storage device, a first database and a processor. The machine is configured to perform a semiconductor process on a first wafer. The storage device is configured to store computer program codes. The first database is configured to collect a process data from the machine. The processor is configured to execute the computer program codes in the storage device for steps as follows. The process data are calibrated to generate a calibrated process data. The calibrated process data are filtered to generate a filtered process data. A prediction data is generated according to the filtered process data for a recipe management system to adjust at least one recipe parameter of the semiconductor process of the machine to a second wafer.

Atomic layer deposition apparatus and semiconductor process

An atomic layer deposition apparatus comprises a processing chamber, at least one partition and an injector. The at least one partition is disposed in the processing chamber for dividing the processing chamber into a plurality of sections. The injector includes a plurality of nozzles disposed in the processing chamber and configured to respectively provide a reacting gaseous flow to each of the plurality of sections. A semiconductor process is also provided.

Photomask and fabrication method therefor

A method of manufacturing a photomask includes depositing a first absorbing layer over a substrate, patterning the first absorbing layer using a photoresist, and depositing a conformal second absorbing layer along surfaces of the first absorbing layer.

Probe card for simultaneously testing multiple dies

In accordance with an embodiment, a probe card comprises a contact pad interface comprising front side contacts and back side contacts electrically coupled together. The front side contacts are arranged to simultaneously electrically couple respective bumps of a plurality of dies on a wafer, and the back side contacts are arranged to electrically couple respective contacts of a testing structure.

SEMICONDUCTOR DEVICE AND FORMATION THEREOF

A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate. The metal plug has a contact bottom surface that is substantially convex. The substantially convex contact bottom surface has an increased contact area as compared to a contact bottom surface of a metal plug that is not substantially convex. The increased contact area decreases a resistance of the metal plug. The increased contact area requires a smaller deposition amount to form a metal plug seed layer of the metal plug than a semiconductor device with a smaller contact area. A smaller deposition amount reduces an overhang of the deposited metal plug seed layer material. A reduced overhang of the deposited metal plug seed layer material reduces pitting in a metal plug formed from the deposited metal plug seed layer material.

Conductive powder formation method

A method of forming a conductive powder includes reducing, by a reduction reaction, a conductive powder precursor gas using a plasma. Reducing the conductive powder precursor gas forms the conductive powder. The method further includes filtering the conductive powder based on particle size. The method further includes dispersing a portion of the conductive powder having a particle size below a threshold value in a fluid.

Devices having a cavity structure and related methods

A method of making a device. The method comprises providing a first layer including a first material on a surface of a substrate, removing a portion of the first layer and a corresponding portion of the substrate to form an opening in the first layer and a recessed portion in the surface of the substrate, and supplying a liquid mixture to the opening and the recessed portion. The liquid mixture includes a first component having a first chemical affinity to the first material and a second component having a second chemical affinity to the first material, which is smaller than the first chemical affinity. The method also includes removing the second component and forming a second layer including the first component. The second layer covers the recessed portion and adheres to an edge portion of the first layer, such that the second layer and the recessed portion define a cavity.

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Methods for manufacturing semiconductor devices are disclosed. A photoresist layer is formed over a substrate. A cryogenic process is performed on the photoresist layer. After the cryogenic process, a cleaning process is performed on the photoresist layer to remove the photoresist layer.

Metal bumps for cooling device connection

The mechanisms for forming metal bumps to connect to a cooling device (or a heat sink) described herein enable substrates with devices to dissipate heat generated more efficiently. In addition, the metal bumps allow customization of bump designs to meet the needs of different chips. Further, the usage of metal bumps between the semiconductor chip and cooling device enables advanced cooling by passing a cooling fluid between the bumps.

Semiconductor structures and methods of forming the same

A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like.

Atomic layer deposition for filling a gap between devices

A method is provided for filling a trench or gap between a pair of semiconductor devices formed above a substrate. A liner is applied in a trench or gap between a pair of devices by atomic layer deposition to partially fill the trench or gap. The trench or gap is filled by a bulk fill process.

Shielding design for metal gap fill

The present disclosure is directed to a physical vapor deposition system configured to heat a semiconductor substrate or wafer. In some embodiments the disclosed physical vapor deposition system comprises at least one heat source having one or more lamp modules for heating of the substrate. The lamp modules may be separated from the substrate by a shielding device. In some embodiments, the shielding device comprises a one-piece device or a two piece device. The disclosed physical vapor deposition system can heat the semiconductor substrate, reflowing a metal film deposited thereon without the necessity for separate chambers, thereby decreasing process time, requiring less thermal budget, and decreasing substrate damage.

Metal-Semiconductor Contact Structure with Doped Interlayer

Disclosed herein is a method of forming a metal-to-semiconductor contact with a doped metal oxide interlayer. An insulating layer is formed on a top surface of a semiconductor substrate with target region at the top surface of the semiconductor substrate. An opening is etched through the insulating layer with the opening exposing a top surface of a portion of the target region. A doped metal oxide interlayer is formed in the opening and contacts the top surface of the target region. The remainder of the opening is filled with a metal plug, the doped metal oxide interlayer disposed between the metal plug and the substrate. The doped metal oxide interlayer is formed from one of tin oxide, titanium oxide or zinc oxide and is doped with fluorine. 1. A structure comprising:an insulating layer disposed over a semiconductor substrate and having an opening extending therethrough, a first surface of the substrate disposed at a bottom of the opening;an interlayer of a contact disposed in the opening and having a first portion contacting the first surface of the substrate; anda metal plug of the contact disposed in the opening, the interlayer separating the metal plug from the first surface of the substrate,wherein the interlayer comprises a doped oxide.2. The structure of claim 1 , wherein the interlayer comprises a doped metal oxide.3. The structure of claim 2 , wherein the metal oxide of the doped metal oxide is one of tin oxide claim 2 , titanium oxide or zinc oxide.4. The structure of claim 2 , wherein the doped metal oxide is doped with fluorine.5. The structure of claim 4 , wherein the doped metal oxide is doped to a concentration between about 0.1% and about 15%.6. The structure of claim 2 , further comprising an adhesion layer disposed between the interlayer and the metal plug.7. The structure of claim 6 , wherein the adhesion layer comprises titanium nitride and the metal plug comprises tungsten.8. The structure of claim 6 , wherein a topmost surface of the metal ...

Semiconductor device having interfacial layer and high κ dielectric layer

A semiconductor device has a semiconductor substrate. A silicon germanium layer is disposed on the semiconductor substrate. The silicon germanium layer has a first silicon-to-germanium ratio. A first gate structure is disposed on the silicon germanium layer, and the first gate structure includes an interfacial layer on the silicon germanium layer. The interface layer has a second silicon-to-germanium ratio substantially the same as the first silicon-to-germanium ratio of the silicon germanium layer. The first gate structure also includes a high-dielectric layer on the interfacial layer and a first gate electrode on the high-κ dielectric layer.

Semiconductor device and fabrication method therefor

A method of manufacturing a semiconductor device includes forming a first insulating film over a first fin structure and a second insulating film over a second fin structure, coating a protective layer over the second insulating film, removing the first insulating film to expose a portion of the first fin structure, and forming a first oxide film over the exposed portion of the first fin structure using a non-aqueous solvent-based chemical.

Two-step shallow trench isolation (STI) process

An integrated circuit device and a process for making the integrated circuit device. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel. The invention also discloses a two-step shallow trench isolation (STI) process.

Semiconductor device

A semiconductor device includes a non-insulator structure, at least one carbon nano-tube (CNT), a dielectric layer, and a graphene-based conductive layer. The CNT is over the non-insulator structure. The dielectric layer surrounds the CNT. The graphene-based conductive layer is over the at least one CNT.

METHOD OF TRIMMING FIN STRUCTURE

A method of trimming a fin structure includes the following operations: (i) forming a fin structure on a substrate; (ii) epitaxially growing an epitaxy structure cladding the fin structure, in which the epitaxy structure has a first lattice plane with Miller index (111), a second lattice plane with Miller index (100) and a third lattice plane with Miller index (110); and (iii) removing the epitaxy structure and a portion of the fin structure to obtain a trimmed fin structure.

Semiconductor device comprising metal plug having substantially convex bottom surface

A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate. The metal plug has a contact bottom surface that is substantially convex. The substantially convex contact bottom surface has an increased contact area as compared to a contact bottom surface of a metal plug that is not substantially convex. The increased contact area decreases a resistance of the metal plug. The increased contact area requires a smaller deposition amount to form a metal plug seed layer of the metal plug than a semiconductor device with a smaller contact area. A smaller deposition amount reduces an overhang of the deposited metal plug seed layer material. A reduced overhang of the deposited metal plug seed layer material reduces pitting in a metal plug formed from the deposited metal plug seed layer material.

SEMICONDUCTOR DEVICE HAVING INTERFACIAL LAYER AND HIGH K DIELECTRIC LAYER

A semiconductor device has a semiconductor substrate. A silicon germanium layer is disposed on the semiconductor substrate. The silicon germanium layer has a first silicon-to-germanium ratio. A first gate structure is disposed on the silicon germanium layer, and the first gate structure includes an interfacial layer on the silicon germanium layer. The interface layer has a second silicon-to-germanium ratio substantially the same as the first silicon-to-germanium ratio of the silicon germanium layer. The first gate structure also includes a high-dielectric layer on the interfacial layer and a first gate electrode on the high-κ dielectric layer. 16-. (canceled)7. A method of fabricating a semiconductor device , the method comprising:forming a first dummy gate structure and a second dummy gate structure on a semiconductor substrate;forming an interlayer dielectric layer on the first dummy gate structure, the second dummy gate structure, and the semiconductor substrate;removing the first dummy gate structure and the second dummy gate structure to expose a first portion and a second portion of the semiconductor substrate;forming a first dielectric layer and a second dielectric layer respectively on the first portion and the second portion of the semiconductor substrate;forming a mask layer on the second dielectric layer;removing the first dielectric layer to expose the first portion of the semiconductor substrate; andperforming a first surface oxidation with an oxidizing gas to form an interfacial layer on the first portion of the semiconductor substrate and to remove the mask layer from the second dielectric layer.8. The method of claim 7 , wherein the oxidizing gas comprises ozone claim 7 , oxygen claim 7 , hydrogen dioxide claim 7 , nitrogen dioxide claim 7 , sulfur dioxide claim 7 , or combinations thereof.9. The method of claim 7 , wherein the performing the first surface oxidation comprising:heating the semiconductor substrate.10. The method of claim 7 , further ...

METHOD OF FORMING CONDUCTIVE BUMPS FOR COOLING DEVICE CONNECTION AND SEMICONDUCTOR DEVICE

A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate. The method includes depositing a first-side UBM layer on a first surface of the semiconductor substrate. The method includes forming a plurality of first-side metal bumps on the first surface of the semiconductor substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the semiconductor substrate. The method includes forming a plurality of second-side metal bumps on the second surface of the semiconductor substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps. 1. A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate , comprising:depositing a first-side UBM layer on a first surface of the semiconductor substrate;forming a plurality of first-side metal bumps on the first surface of the semiconductor substrate after the first-side UBM layer is deposited;forming a second-side UBM layer on a second side of the semiconductor substrate, wherein the first surface and the second surface are opposite of each other;forming a plurality of second-side metal bumps on the second surface of the semiconductor substrate after the second-side UBM layer is deposited;removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed; andreflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.2. The method of claim 1 , wherein the plurality of first-side metal bumps and the plurality of second-side metal bumps are solder bumps or ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A device includes a non-insulator structure, a first dielectric layer, and a first conductive feature. The first dielectric layer is over the non-insulator structure. The first conductive feature is in the first dielectric layer and includes carbon nano-tubes. The first catalyst layer is between the first conductive feature and the non-insulator structure. A top of the first catalyst layer is lower than a top of the first conductive feature. 1. A device , comprising:a non-insulator structure;a first dielectric layer over the non-insulator structure;a first conductive feature in the first dielectric layer and comprising carbon nano-tubes; anda first catalyst layer between the first conductive feature and the non-insulator structure, wherein a top of the first catalyst layer is lower than a top of the first conductive feature.2. The device of claim 1 , wherein the first catalyst layer has a first portion between the first conductive feature and the non-insulator structure and a second portion extending along sidewalls of the first conductive feature towards the top of the first conductive feature without extending to the top of the first conductive feature.3. The device of claim 1 , wherein the first conductive feature comprises metal.4. The device of claim 1 , further comprising:a second dielectric layer over the first dielectric layer; anda graphene-based conductive layer in the second dielectric layer and electrically connected to the first conductive feature.5. The device of claim 4 , further comprising:a second catalyst layer between the graphene-based conductive layer and the first conductive feature.6. The device of claim 5 , wherein a bottom of the second catalyst layer is above the top of the first conductive feature.7. The device of claim 5 , wherein the second catalyst layer is spaced from the first catalyst layer.8. The device of claim 4 , further comprising:a second conductive feature in the second dielectric layer, wherein the graphene-based conductive ...

Integrated technology for partial air gap low K deposition

A semiconductor device includes a semiconductor body and a low K dielectric layer overlying the semiconductor body. A first portion of the low K dielectric layer comprises a dielectric material, and a second portion of the low K dielectric layer comprise an air gap, wherein the first portion and the second portion are laterally disposed with respect to one another. A method for forming a low K dielectric layer is also disclosed and includes forming a dielectric layer over a semiconductor body, forming a plurality of air gaps laterally disposed from one another in the dielectric layer, and forming a capping layer over the dielectric layer and air gaps.

SEMICONDUCTOR DEVICE HAVING INTERFACIAL LAYER AND HIGH K DIELECTRIC LAYER

A transistor includes a silicon germanium layer, a gate stack, and source and drain features. The silicon germanium layer has a channel region. The silicon germanium layer has a first silicon-to-germanium ratio. The gate stack is disposed over the channel region of the silicon germanium layer and includes a silicon germanium oxide layer over and in contact with the channel region of the silicon germanium layer, a high-κ dielectric layer over the silicon germanium oxide layer, and a gate electrode over the high-κ dielectric layer. The silicon germanium oxide layer has a second silicon-to-germanium ratio, and the second silicon-to-germanium ratio is substantially the same as the first silicon-to-germanium ratio. 1. A transistor comprising:a silicon germanium layer having a channel region, wherein the silicon germanium layer has a first silicon-to-germanium ratio; a silicon germanium oxide layer over and in contact with the channel region of the silicon germanium layer, wherein the silicon germanium oxide layer has a second silicon-to-germanium ratio, and the second silicon-to-germanium ratio is substantially the same as the first silicon-to-germanium ratio;', 'a high-κ dielectric layer over the silicon germanium oxide layer; and', 'a gate electrode over the high-κ dielectric layer; and, 'a gate stack over the channel region of the silicon germanium layer, wherein the gate stack comprisessource and drain features in the silicon germanium layer, wherein the channel region of the silicon germanium layer is between the source and drain structures.2. The transistor of claim 1 , further comprising:a gate spacer surrounding and in contact with the silicon germanium oxide layer.3. The transistor of claim 1 , wherein a bottom of the source feature is lower than a bottom of the silicon germanium layer.4. The transistor of claim 1 , wherein a topmost portion of the silicon germanium oxide layer is lower than a bottommost portion of the high-κ dielectric layer.5. A device ...

Interconnect structure and method of forming the same

An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a contact layer over a substrate; a dielectric layer over the contact layer, wherein the dielectric layer has an opening, the opening exposing a portion of the contact layer; a silicide layer over the exposed portion of the contact layer; a barrier layer along sidewalls of the opening; an alloy layer over the barrier layer; a glue layer over the alloy layer; and a conductive plug over the glue layer.

METHOD OF EVALUATING CHARACTERISTICS OF ION IMPLANTED SAMPLE

A method of evaluating characteristics of a work piece includes forming a photosensitive layer on the work piece. Then an ion implantation is performed on the work piece. The work piece is radiated, and an optical intensity of the photosensitive material on the work piece is calculated. The ion implantation pattern is evaluated according to the optical intensity. A chemical structure of the photosensitive material is changed upon the ion implantation. The work piece is recovered by reversing the chemical structure of the photosensitive material or removing the ion interrupted photosensitive material by chemicals.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes forming a first insulating film over a first fin structure and a second insulating film over a second fin structure, coating a protective layer over the second insulating film, removing the first insulating film to expose a portion of the first fin structure, and forming a first oxide film over the exposed portion of the first fin structure using a non-aqueous solvent-based chemical.

Method for enhancing FSG film stability

A method for enhancing stability of a fluorinated silicon glass layer is disclosed. A fluorinated silicon glass layer provided on a substrate is subjected to a phosphorous-containing and hydrogen-containing gas such as phosphine (PH₃), for example. The gas forms reactive hydrogen species which removes fluorine radicals and reactive phosphorous species which forms a moisture-gettering and ion-gettering phosphorious oxide film the layer.

PHOTOMASK AND FABRICATION METHOD THEREFOR

A method of manufacturing a photomask includes depositing a first absorbing layer over a substrate, patterning the first absorbing layer using a photoresist, and depositing a conformal second absorbing layer along surfaces of the first absorbing layer. 1. A method of manufacturing a photomask , the method comprising:depositing a first absorbing layer over a substrate;patterning the first absorbing layer using a photoresist; anddepositing a conformal second absorbing layer along surfaces of the first absorbing layer.2. The method of claim 1 , wherein the depositing of the first absorbing layer comprises:depositing the first absorbing layer using electroless plating or atomic layer deposition (ALD).3. The method of claim 1 , wherein the depositing of the conformal second absorbing layer comprises:depositing the conformal second absorbing layer using electroless plating or ALD.4. The method of claim 1 , wherein the depositing of the conformal second absorbing layer comprises:depositing the conformal second absorbing layer using a same process as that for depositing the first absorbing layer.5. The method of claim 1 , wherein the depositing of the conformal second absorbing layer comprises:depositing the conformal second absorbing layer using a different process from that for depositing the first absorbing layer.6. The method of claim 1 , wherein the depositing of the conformal second absorbing layer comprises:depositing the conformal second absorbing layer to have a thickness about two times to about ten times greater than a thickness of the first absorbing layer.7. The method of claim 1 , wherein the patterning of the first absorbing layer comprises:coating a photoresist over the first absorbing layer;exposing and developing the photoresist to define a pattern set; andremoving an exposed portion of the first absorbing layer to form a pattern set.8. The method of claim 1 , further comprising:removing a portion of the substrate to form a phase shifting region.9. The ...

Semiconductor device having interfacial layer and high K dielectric layer

A transistor includes a channel region, a gate stack, and source and drain structures. The channel region comprises silicon germanium and has a first silicon-to-germanium ratio. The gate stack is over the channel region and comprises a silicon germanium oxide layer over the channel region, a high-κ dielectric layer over the silicon germanium oxide layer, and a gate electrode over the high-κ dielectric layer. The silicon germanium oxide layer has a second silicon-to-germanium ratio. The second silicon-to-germanium ratio is substantially the same as the first silicon-to-germanium ratio. The channel region is between the source and drain structures.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a non-insulator structure, at least one carbon nano-tube (CNT), a dielectric layer, and a graphene-based conductive layer. The CNT is over the non-insulator structure. The dielectric layer surrounds the CNT. The graphene-based conductive layer is over the at least one CNT. The CNTs and the graphene-based conductive layer have low resistance.

Semiconductor processing station

A semiconductor processing station including a platform, a load port, and a carrier transport track is provided. The platform includes an intake/outtake port and a plurality of processing modules. The load port includes a load chamber, a movable cover, and a carrier transfer module. The load chamber communicates with the intake/outtake port and has a load opening at its top end for receiving a transport carrier within the load chamber. The movable cover is disposed at the load opening and configured to seal the load opening. The carrier transfer module is configured to transfer the transport carrier to the intake/outtake port. The carrier transport track has a bottom side configured to open the load chamber.

Composite contact plug structure and method of making same

An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.

METHOD OF USING A POLISHING SYSTEM

A method of using a polishing system includes securing a wafer to a support, wherein the wafer has a first diameter. The method further includes polishing the wafer using a first polishing pad rotating about a first axis, wherein the first polishing pad has a second diameter greater than the first diameter. The method further includes rotating the support about a second axis perpendicular to the first axis after polishing the wafer using the first polishing pad. The method further includes polishing the wafer using a second polishing pad after rotating the support, wherein the second polishing pad has a third diameter less than the first diameter. The method further includes releasing the wafer from the support following polishing the wafer using the second polishing pad.

Shower head apparatus and method for controlling plasma or gas distribution

An apparatus comprises: a shower head having a supply plenum for supplying the gas to the chamber and a vacuum manifold fluidly coupled to the supply plenum; and at least one vacuum system fluidly coupled to the vacuum manifold of the shower head.

Gamma ray generator, gamma ray lithography system and method of performing gamma ray lithography

One of gamma ray lithography systems includes a gamma ray generator and a wafer stage. The gamma ray generator is configured to generate a substantially uniform gamma ray. The gamma ray generator includes a plurality of gamma ray sources and a rotational carrier. The rotational carrier is configured to hold the gamma ray sources and rotate along a rotational axis. The wafer stage is disposed below the gamma ray generator and configured to secure a wafer.

CVD conformal vacuum/pumping guiding design

The present disclosure relates to a guiding element for guiding gas flow within a chamber. The guiding element includes a structure, one or more inlets, an outlet, and a transportation region. The one or more inlets are formed on a first side of the structure. The inlets have inlet sizes selected according to a removal rate and to mitigate gas flow variations within the chamber. The outlet is on a second side of the structure, opposite the first side of the structure. The outlet has an outlet size selected according to the removal rate. The transportation region is within the structure and couples or connects the inlets to the outlet.

Rotation plus vibration magnet for magnetron sputtering apparatus

In some embodiments, the present disclosure relates to a plasma processing system having a magnetron that provides a symmetric magnetic track through a combination of vibrational and rotational motion. The disclosed magnetron has a magnetic element that generates a magnetic field. The magnetic element is attached to an elastic element connected between the magnetic element and a rotational shaft that rotates the magnetic element about a center of the sputtering target. The elastic element may vary its length during rotation of the magnetic element to change the radial distance between the rotational shaft and the magnetic element. The resulting magnetic track enables concurrent motion of the magnetic element in both an angular direction and a radial direction. Such motion enables a symmetric magnetic track that provides good wafer uniformity and a short deposition time.

Barrier structure for copper interconnect

A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming an opening in the dielectric layer, forming a metal-containing layer overlying the opening in the dielectric layer, forming a conformal protective layer overlying the metal-containing layer, filling a conductive layer in the opening, and performing a thermal process to form a metal oxide layer barrier layer underlying the metal-containing layer.

Mechanisms for resistivity measurement of bump structures

The embodiments described above provide mechanisms for bump resistivity measurement. By using designated bumps on one or more corners of dies, the resistivity of bumps may be measured without damaging devices and without a customized probing card. In addition, bump resistivity may be collected across the entire wafer. The collected resistivity data may be used to monitor the stability and/or health of processes used to form bumps and their underlying layers.

Reverse Damascene Process

The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure. 1. A method for forming integrated chip back-end-of-the-line metallization layers , comprising:forming a plurality of first metal layer structures of a first single metal layer positioned on a first copper barrier film that is disposed on a semiconductor substrate;depositing a diffusion barrier layer onto the semiconductor substrate that conforms to top and side surfaces of the first metal layer structures;depositing an inter-level dielectric material onto the surface of the semiconductor substrate in areas between the first metal layer structures;planarizing the semiconductor substrate to expose the top of the first metal layer structures; andforming a plurality of second metal layer structures of a second single metal layer positioned on a second copper barrier film disposed onto the plurality of first metal layer structures, so that the plurality of first metal layer structures are separated from the plurality of second metal layer structures by the second copper barrier film.2. The method of claim 1 , wherein forming the plurality of first metal layer structures claim 1 , comprises:depositing an under metal metallurgy (UMM) layer on the surface of the semiconductor substrate;forming a patterned photoresist layer having ...

Electrostatic Chuck Robotic System

A workpiece transfer system has a plurality of joints having a bearing and a primary and secondary transformer coil, wherein power provided to the primary transformer coil and secondary transformer coil of each joint produces mutual inductance between the primary and secondary transformer coil of the respective joint. A first pair of arms are rotatably coupled to a blade by a first pair of the joints, wherein the primary transformer coil of each of the first pair of joints is operably coupled to the first pair of arms, and the secondary transformer coil of each of the first pair of joints is operably coupled to the blade and an electrode beneath a dielectric workpiece retaining surface of the blade. The electrode is contactlessly energized through the transformer coils of the joint and the blade can chuck and de-chuck a workpiece by reversing current directions and by voltage adjustment. 1. A workpiece transfer system , comprising:a blade, wherein the blade comprises one or more electrodes associated with a dielectric workpiece retaining surface;a plurality of joints, each of the plurality of joints comprising a bearing, a primary transformer coil, and a secondary transformer coil, wherein the bearing of each joint rotatably couples the primary transformer coil to the secondary transformer coil of the respective joint, and wherein power provided to one of the primary transformer coil and secondary transformer coil of each joint produces mutual inductance between the primary transformer coil and secondary transformer coil of the respective joint, therein providing contactless power across each joint; anda first pair of arms respectively rotatably coupled to the blade via a first pair of the plurality of joints, wherein the primary transformer coil of each of the first pair of the plurality of joints is operably coupled to the respective first pair of arms, and wherein the secondary transformer coil of each of the first pair of the plurality of joints is operably ...

APPARATUS AND METHOD WITH DEPOSITION CHAMBER HAVING MULTIPLE TARGETS AND MAGNETS

A thin film deposition system and method provide for multiple target assemblies that may be separately powered. Each target assembly includes a target and associated magnet or set of magnets. The disclosure provides a tunable film profile produced by multiple power sources that separately power the target arrangements. The relative amounts of power supplied to the target arrangements may be customized to provide a desired film and may be varied in time to produce a film with varied characteristics. 1. A film deposition system comprising:a deposition chamber with a target arrangement including a plurality of target assemblies therein, each said target assembly including a target member and dedicated magnet or plurality of dedicated magnets, each said target assembly having a separately controllable power source; anda stage for receiving a workpiece thereon.2. The film deposition system as in claim 1 , wherein said plurality of target assemblies includes a central target member and an annular target member surrounding said central target member.3. The film deposition system as in claim 1 , wherein said plurality of target assemblies comprises said target members being concentrically arranged.4. The film deposition system as in claim 1 , wherein each said target member is formed of a different material.5. The film deposition system as in claim 1 , wherein each said dedicated magnet or plurality of dedicated magnets is rotatable with respect to said associated target member of said associated target assembly.6. The film deposition system as in claim 1 , wherein said plurality of target assemblies includes a centrally disposed first target assembly claim 1 , an annular second target assembly surrounding said first target assembly and an annular third target assembly surrounding said second target assembly and wherein each of said plurality of target assemblies is adapted to deposit associated target material on a workpiece disposed on said stage.7. The film deposition ...

Integrated Technology for Partial Air Gap Low K Deposition

A semiconductor device includes a semiconductor body and a low K dielectric layer overlying the semiconductor body. A first portion of the low K dielectric layer comprises a dielectric material, and a second portion of the low K dielectric layer comprise an air gap, wherein the first portion and the second portion are laterally disposed with respect to one another. A method for forming a low K dielectric layer is also disclosed and includes forming a dielectric layer over a semiconductor body, forming a plurality of air gaps laterally disposed from one another in the dielectric layer, and forming a capping layer over the dielectric layer and air gaps.

CHEMICAL VAPOR DEPOSITION FILM PROFILE UNIFORMITY CONTROL

The present disclosure provides for methods and systems for controlling profile uniformity of a chemical vapor deposition (CVD) film. A method includes depositing a first layer on a substrate by CVD with a first shower head, the first layer having a first profile, and depositing a second layer over the first layer by CVD with a second shower head, the second layer having a second profile. The combined first layer and second layer have a third profile, and the first profile, the second profile, and the third profile are different from one another. 1. A method of controlling chemical vapor deposition (CVD) film profile uniformity , the method comprising:depositing a first layer on a substrate by CVD with a first shower head, the first layer having a first profile; anddepositing a second layer over the first layer by CVD with a second shower head, the second layer having a second profile,wherein the combined first layer and second layer have a third profile, andwherein the first profile, the second profile, and the third profile are different from one another.2. The method of claim 1 , wherein the first layer is deposited in a first reaction chamber and the second layer is deposited in a second reaction chamber.3. The method of claim 1 , wherein the first profile of the first layer includes a protrusion sloping upward claim 1 , the second profile of the second layer includes a depression sloping downward claim 1 , and the third profile of the combined first layer and second layer is more planar than the first profile and/or the second profile.4. The method of claim 1 , wherein the second shower head has a second shower head aperture design including apertures in concentric circles claim 1 , and the first shower head has a first shower head aperture design including apertures in concentric circles at different locations than the second shower head aperture design.5. The method of claim 1 , further comprising selecting the second shower head to compensate the first ...

WAFER PROCESSING METHOD AND SYSTEM USING MULTI-ZONE CHUCK

In a wafer processing method and a wafer processing system, a first property on a back side of a wafer is measured. The back side of the wafer is supported on a multi-zone chuck having a plurality of zones with controllable clamping forces. The wafer is secured to the multi-zone chuck by controlling the clamping forces in the corresponding zones in accordance with measured values of the first property in the zones. 1. A wafer processing method , comprising:measuring a first property on a back side of a wafer,supporting the back side of the wafer on a multi-zone chuck having a plurality of zones with controllable clamping forces,securing the wafer to the multi-zone chuck by controlling the clamping forces in the corresponding zones in accordance with measured values of the first property in said zones.2. The wafer processing method of claim 1 , further comprisingheating the wafer secured on the multi-zone chuck by at least one heater included in the multi-zone chuck;whereinthe clamping forces in the corresponding zones of the multi-zone chuck are controlled to compensate for different measured values of the first property in different zones to achieve a uniform heat transfer from the multi-zone chuck to the wafer.3. The wafer processing method of claim 1 , whereinthe first property comprises a thickness of a first layer on the back side of the wafer, andthe clamping forces are controlled to compensate for a non-uniformity in the thickness of said first layer.4. The wafer processing method of claim 1 , further comprisingperforming a treatment on the wafer,measuring a second property of the wafer after said treatment, said second property different from the first property, andadjusting the clamping forces in one or more zones of the multi-zone chuck in accordance with measured values of the second property in said zones.5. The wafer processing method of claim 4 , further comprisingusing the adjusted clamping forces to secure a subsequent wafer on the multi-zone chuck ...

Shielding Design for Metal Gap Fill

The present disclosure is directed to a physical vapor deposition system configured to heat a semiconductor substrate or wafer. In some embodiments the disclosed physical vapor deposition system comprises at least one heat source having one or more lamp modules for heating of the substrate. The lamp modules may be separated from the substrate by a shielding device. In some embodiments, the shielding device comprises a one-piece device or a two piece device. The disclosed physical vapor deposition system can heat the semiconductor substrate, reflowing a metal film deposited thereon without the necessity for separate chambers, thereby decreasing process time, requiring less thermal budget, and decreasing substrate damage. 1. A physical vapor deposition system , comprising:a processing chamber configured to house a substrate;a target configured to provide target atoms to the processing chamber; andat least one heat source comprising one or more lamp modules configured to heat a surface of the substrate.2. The physical vapor deposition system of claim 1 , further comprising a shielding device.3. The physical vapor deposition system of claim 2 , wherein the shielding device comprises a one-piece device or a two-piece device.4. The physical vapor deposition system of claim 3 , wherein the two-piece device comprises an upper portion and a lower portion.5. The physical vapor deposition system of claim 4 , wherein the one or more lamp modules are positioned within the processing chamber:a) between the lower shielding and a chamber wall in a chamber containing a two-piece shielding device;b) between the upper and the lower shielding in a chamber containing a two-piece shielding device;c) below the chamber shielding device in a chamber containing a one-piece shielding device; ord) on a rotatably moveable transfer arm in a chamber containing a two-piece shielding device.6. The physical vapor deposition system of claim 1 , wherein the lamp modules comprise a plurality of ...

CVD Conformal Vacuum/Pumping Guiding Design

The present disclosure relates to a guiding element for guiding gas flow within a chamber. The guiding element includes a structure, one or more inlets, an outlet, and a transportation region. The one or more inlets are formed on a first side of the structure. The inlets have inlet sizes selected according to a removal rate and to mitigate gas flow variations within the chamber. The outlet is on a second side of the structure, opposite the first side of the structure. The outlet has an outlet size selected according to the removal rate. The transportation region is within the structure and couples or connects the inlets to the outlet. 1. A guiding element for guiding gas flow within a chamber , the element comprising:a structure;one or more inlets formed on a first side of the structure, the inlets having inlet sizes selected according to a removal rate and to mitigate gas flow variations;an outlet formed on a second side of the structure and having an outlet size selected according to the removal rate; anda transportation region within the structure and coupled to the inlets and the outlet.2. The guiding element of claim 1 , wherein the structure is in the shape of a circle.3. The guiding element of claim 1 , wherein the inlet sizes are additionally selected according to a position relative to a chamber exit port.4. The guiding element of claim 1 , wherein the outlet size is about equal to a chamber exit port size.5. The guiding element of claim 1 , further comprising a seal surrounding the outlet.6. The guiding element of claim 1 , wherein the removal rate is selected according to a deposition rate.7. The guiding element of claim 1 , wherein the structure is in the shape of a disc.8. A semiconductor process system comprising:a chamber having an exit port;a showerhead located at a top portion of the chamber, the showerhead configured to distribute a process gas;a heater located below the showerhead within the chamber, the heater configured to yield a selected ...

Electrostatic Chuck with Multi-Zone Control

An electrostatic chuck for clamping a warped workpiece has a clamping surface comprising a dielectric layer. The dielectric layer has a field and one or more zones formed of differing dielectric materials. One or more electrodes are coupled to a power supply, and a controller controls a clamping voltage supplied to the one or more electrodes via the power supply. An electrostatic attraction force associated with each of the field and one or more zones of the dielectric layer of the electrostatic chuck is induced, wherein the electrostatic attraction force varies based on the dielectric material of each of the field and one or more zones. The electrostatic attraction force is greater in the one or more zones than in the field, therein attracting warped regions of the workpiece to the clamping surface and clamping the warped workpiece to the clamping surface across a surface of the warped workpiece. 1. An electrostatic chuck , comprising:a clamping surface comprising a dielectric layer, wherein the dielectric layer comprises a field and one or more zones defined therein, wherein the field is comprised of a first dielectric material, and wherein the one or more zones are comprised of a second dielectric material, wherein each of the first dielectric material and second dielectric material have different dielectric constants associated therewith; andone or more electrodes associated with the dielectric layer, wherein a voltage supplied to the one or more electrodes is configured to induce an electrostatic attraction force associated with each of the field and one or more zones, and wherein the electrostatic attraction force varies based on the dielectric material of each of the field and one or more zones.2. The electrostatic chuck of claim 1 , wherein the electrostatic attraction force is greater in the one or more zones than in the field.3. The electrostatic chuck of claim 1 , wherein the one or more zones comprise a central zone associated with a center of the ...

Rotation Plus Vibration Magnet for Magnetron Sputtering Apparatus

In some embodiments, the present disclosure relates to a plasma processing system comprising a magnetron configured to provide a symmetric magnetic track through a combination of vibrational and rotational motion. The disclosed magnetron comprises a magnetic element configured to generate a magnetic field. The magnetic element is attached to an elastic element connected between the magnetic element and a rotational shaft configured to rotate magnetic element about a center of the sputtering target. The elastic element is configured to vary its length during rotation of the magnetic element to change the radial distance between the rotational shaft and the magnetic element. The resulting magnetic track enables concurrent motion of the magnetic element in both an angular direction and a radial direction. Such motion enables a symmetric magnetic track that provides good wafer uniformity and a short deposition time. 1. A physical vapor deposition system , comprising:a processing chamber configured to house a workpiece;a sputtering target located within the processing chamber; a magnetic element positioned on a backside of the sputtering target and configured to generate a magnetic field that operates upon ions within the processing chamber;', 'a first ambulatory element configured to move the magnetic element in an angular direction; and', 'a second ambulatory element configured to linearly move the magnetic element in a radial direction concurrent to movement in the angular direction;, 'a magnetron comprisingwherein the concurrent angular and radial motion move the magnetic element along a symmetric magnetic track.2. The physical vapor deposition system of claim 1 , wherein the first ambulatory element comprises a rotational shaft configured to rotate the magnetic element about a center of the sputtering target.3. The physical vapor deposition system of claim 2 , wherein the second ambulatory element comprises an elastic element claim 2 , having a variable length claim ...

NOVEL CLOSED LOOP CONTROL FOR RELIABILITY

The present disclosure relates to semiconductor tool monitoring system having multiple sensors configured to concurrently and independently monitor processing conditions of a semiconductor manufacturing tool. In some embodiments, the disclosed tool monitoring system comprises a first sensor system configured to monitor one or more processing conditions of a semiconductor manufacturing tool and to generate a first monitoring response based thereupon. A redundant, second sensor system is configured to concurrently monitor the one or more processing conditions of the manufacturing tool and to generate a second monitoring response based thereupon. A comparison element is configured to compare the first and second monitoring responses, and if the responses deviate from one another (e.g., have a deviation greater than a threshold value) to generate a warning signal. By comparing the first and second monitoring responses, errors in the sensor systems can be detected in real time, thereby preventing yield loss. 1. A semiconductor manufacturing tool monitoring system , comprising:a first sensor system configured to measure one or more processing conditions of a semiconductor manufacturing tool and to generate a first monitoring response based thereupon;a second sensor system configured to measure the one or more processing conditions of the semiconductor manufacturing tool and to generate a second monitoring response based thereupon; anda comparison element configured to compare the first monitoring response to the second monitoring response, wherein a deviation between the first and second monitoring responses is indicative of an error in the first or second sensor systems.2. The monitoring system of claim 1 , wherein the first sensor system comprises:a first sensor configured to measure the one or more processing conditions of the semiconductor manufacturing tool;a first amplifier configured to receive and amplify an output of the first sensor to generate the first ...

Valve purge assembly for semiconductor manufacturing tools

A semiconductor manufacturing tool and method for operating the tool are provided. The semiconductor manufacturing tool includes a process chamber in which plasma operations or ion etching operations are carried out and a valve assembly for opening and closing a valve that provides for loading and unloading substrates into and out of, the semiconductor manufacturing tool. While a processing operation is being carried out in the chamber, a valve assembly purge operation also takes place. The valve assembly purge operation involves inert gases being directed to the valve assembly area to prevent the buildup of particles and contaminating films in the valve assembly. Because the valve assembly is maintained in a clean condition, particle contamination is reduced or eliminated.

Reverse Damascene Process

The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure. 1. A method for forming a metallization layer , comprising:depositing an under metal metallurgy (UMM) layer over a surface of a semiconductor substrate;forming a patterned photoresist layer above the UMM layer having one or more cavities extending from a top to a bottom of the patterned photoresist layer;growing a single metal layer from the UMM layer, wherein the single metal layer is grown from the UMM layer in a single processing step, which is uninterrupted by other processing steps, to form metal layer structures shaped by the one or more cavities in the patterned photoresist layer;removing the patterned photoresist layer from the semiconductor substrate to leave the metal layer structures over the surface of the semiconductor substrate;forming a diffusion barrier layer that conforms to top and side surfaces of the metal layer structures; andforming an inter-level dielectric material onto the surface of the semiconductor substrate to fill areas between the metal layer structures.2. The method of claim 1 , wherein depositing the inter-level dielectric material on the surface of the semiconductor substrate comprises spin coating the inter-level dielectric material on the surface of the semiconductor substrate.3. The ...

SHOWER HEAD APPARATUS AND METHOD FOR CONTROLLIGN PLASMA OR GAS DISTRIBUTION

An apparatus comprises: a shower head having a supply plenum for supplying the gas to the chamber and a vacuum manifold fluidly coupled to the supply plenum; and at least one vacuum system fluidly coupled to the vacuum manifold of the shower head. 1. An apparatus , comprising:a shower head configured to be mounted inside a chamber and provide a processing gas onto a semiconductor wafer inside the chamber, the shower head having a supply plenum for supplying the gas to the chamber and a vacuum manifold fluidly coupled to the supply plenum; andat least one vacuum system fluidly coupled to the vacuum manifold of the shower head.2. The apparatus of claim 1 , wherein the shower head comprises:a first plate defining a first side of the supply plenum, the first plate having a plurality of openings adapted for providing the processing gas flowing from the shower head to the semiconductor wafer inside the chamber;an inlet connected with the supply plenum and adapted to supply at least one chemical in a gas state from outside the chamber; anda second plate defining a second side of the supply plenum.3. The apparatus of claim 2 , wherein the first plate and the second plate are configured so that a space exists between the first and the second plates for the at least one chemical in the gas state to flow from the inlet to the plurality of openings on the first plate.4. The apparatus of claim 3 , wherein each of the at least one vacuum system comprises a conduit for vacuum claim 3 , and the conduit for vacuum is connected to at least one opening in the second plate and is configured to provide vacuum in a respective area in the space between the first and second plates.5. The apparatus of claim 3 , wherein each of the at least one vacuum system further comprises a respective vacuum pump.6. The apparatus of claim 4 , wherein the conduit for vacuum is a vacuum line or a tunnel inside the second plate and is connected to the space between the first and second plate through the ...

SEMICONDUCTOR FILM FORMATION APPARATUS AND PROCESS

An apparatus and method are disclosed for forming thin films on a semiconductor substrate. The apparatus in one embodiment includes a process chamber configured for supporting the substrate, a gas excitation power source, and first and second gas distribution showerheads fluidly coupled to a reactive process gas supply containing film precursors. The showerheads dispense the gas into two different zones above the substrate, which is excited to generate an inner plasma field and an outer plasma field over the wafer. The apparatus deposits a material on the substrate in a manner that promotes the formation of a film having a substantially uniform thickness across the substrate. In one embodiment, the substrate is a wafer. Various embodiments include first and second independently controllable power sources connected to the first and second showerheads to vary the power level and plasma intensity in each zone. 1. An apparatus for forming thin films on a semiconductor substrate comprising:a process chamber configured for supporting the substrate;a first gas distribution showerhead disposed in the chamber, the first showerhead being fluidly coupled to a process gas supply system and operable to dispense the process gas into the chamber in a first zone above the substrate;a second gas distribution showerhead disposed in the chamber, the second showerhead being fluidly coupled to the process gas supply system and operable to dispense the process gas into the chamber in a second zone above the substrate, the second zone being different than the first zone; anda gas excitation power system conductively coupled to the process chamber, the power system being operable to excite the process gas and generate a gas plasma inside the process chamber for forming a material film on the substrate.2. The apparatus of claim 1 , wherein the second showerhead is annular-shaped and the first showerhead is disposed inside the second showerhead.3. The apparatus of claim 2 , wherein the first ...

UV CURING SYSTEM FOR SEMICONDUCTORS

Embodiments of an ultraviolet (UV) curing system for treating a semiconductor substrate such as a wafer are disclosed. The curing system generally includes a processing chamber, a wafer support for holding a wafer in the chamber, a UV radiation source disposed above the chamber, and a UV transparent window interspersed between the radiation source and wafer support. In one embodiment, the wafer support is provided by a belt conveyor operable to transport wafers through the chamber during UV curing. In another embodiment, the UV radiation source is a movable lamp unit that travels across the top of the chamber for irradiating the wafer. In another embodiment, the UV transparent window includes a UV radiation modifier that reduces the intensity of UV radiation on portions of the wafer positioned below the modifier. Various embodiments enhance wafer curing uniformity by normalizing UV intensity levels on the wafer. 1. A semiconductor wafer curing system comprising:a processing chamber;a belt conveyor disposed in the processing chamber, the belt conveyor being configured for holding a wafer and operable to transport the wafer through the processing chamber;an ultraviolet (UV) radiation source disposed above the processing chamber, the UV radiation source being operable to irradiate a wafer disposed on the belt conveyor for UV curing; andthe processing chamber provided with a UV transparent window that is positioned between the belt conveyor and the UV radiation source, wherein the UV transparent window includes a UV radiation modifying section, having a surface area less than a total surface area of the UV transparent window and localized to a high intensity region of the UV transparent window, that reduces the intensity of the UV radiation passing through the radiation modifying section to the wafer on the belt conveyor.2. (canceled)3. The wafer curing system of claim 1 , wherein the processing chamber is elongated and rectilinear in configuration.4. The wafer curing ...

REVERSE DAMASCENE PROCESS

The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure. 1. A metallization layer , comprising:a metal layer structure disposed over a semiconductor substrate;a nitride free under metal metallurgy (UMM) metal seed layer extending along a bottom surface the metal layer structure, wherein sidewalls of UMM metal seed layer are aligned with sidewalls of the metal layer structure along a straight line;a nitride based diffusion barrier layer which conforms to the sidewalls of the metal layer structure; andan inter-level dielectric material located between metal layer structures.2. The metallization layer of claim 1 , further comprising a nitride free dielectric film disposed below the UMM layer.3. The metallization layer of claim 2 , wherein the nitride free dielectric film comprises Trimethoxysilane-based silicon dioxide.4. The metallization layer of claim 1 , wherein the nitride based diffusion barrier layer comprises titanium nitride (TiN) claim 1 , tantalum silicon nitride (TaSiN) claim 1 , titanium silicon nitride (TiSiN) claim 1 , tantalum aluminum nitride (TaAIN) claim 1 , tantalum nitride (TaN) claim 1 , or hafnium nitride (HfN).5. The metallization layer of claim 1 , wherein the metal layer structure has linear sidewalls claim 1 , which extend along a straight line.6. The ...

Die Edge Contacts for Semiconductor Devices

A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like. 1. A semiconductor structure comprising:an integrated circuit substrate having a contact pad formed thereon;a passivation layer formed over the integrated circuit substrate, the passivation layer exposing at least a portion of the contact pad and having a trench from the contact pad to an edge of the integrated circuit substrate; anda conductive material filling the trench of the passivation layer to form a die-edge contact.2. The semiconductor structure of claim 1 , further comprising a through-substrate via on the edge of the substrate such that the die-edge contact comprises the through-substrate via.3. The semiconductor structure of claim 1 , further comprising an inner connection structure claim 1 , the inner connection structure having a plurality of inner connection substrates perpendicular to the integrated circuit substrate claim 1 , at least one of the inner connection substrates having a contact pad electrically coupled to the die-edge contact.4. The semiconductor structure of claim 3 , wherein the inner connection structure comprises ...

Probe Card for Simultaneously Testing Multiple Dies

In accordance with an embodiment, a probe card comprises a contact pad interface comprising front side contacts and back side contacts electrically coupled together. The front side contacts are arranged to simultaneously electrically couple respective bumps of a plurality of dies on a wafer, and the back side contacts are arranged to electrically couple respective contacts of a testing structure. 1. A probe card comprising:a contact pad interface comprising front side contacts and back side contacts electrically coupled together, the front side contacts being arranged to simultaneously electrically couple respective bumps of a plurality of dies on a wafer, and the back side contacts being arranged to electrically couple respective contacts of a testing structure.2. The probe card of claim 1 , wherein the front side contacts are arranged to simultaneously electrically couple the respective bumps of all of the dies on the wafer.3. The probe card of claim 1 , wherein the testing structure comprises a docking board secured to the contact pad interface claim 1 , the docking board comprising a contact pad claim 1 , the contact pad comprising board contacts claim 1 , the board contacts being the contacts of the testing structure.4. The probe card of claim 3 , wherein the contact pad interface is secured to the docking board by a clamp.5. The probe card of claim 3 , wherein the contact pad interface is secured to the docking board by a vacuum system.6. The probe card of claim 1 , wherein the contact pad interface comprises:a substrate with a front side and a back side, the back side being opposite from the front, wherein the front side contacts are on the front side, and the back side contacts are on the back side;through substrate vias (TSVs) penetrating through the substrate and electrically coupling the front side contacts to respective back side contacts; andinterconnect structures on at least one of the front side and the back side electrically disposed between the ...

METHOD AND APPARATUS FOR PREPARING POLYSILAZANE ON A SEMICONDUCTOR WAFER

A method for depositing a polysilazane on a semiconductor wafer is provided. The method includes steps of disposing a silazane onto the semiconductor wafer, and heating the silazane to form the polysilazane on the semiconductor wafer. An apparatus for preparing a polysilazane on a semiconductor wafer is also provided. 1. A method for depositing polysilazane on a semiconductor wafer , comprising steps of:disposing silazane onto the semiconductor wafer, wherein the semiconductor wafer includes a trench structure, and the disposing step comprises a substep of fully filling the trench structure with the silazane for forming a shallow trench isolation structure and wherein the silazane is in a silazane solution with a solvent prior to and at least partially during being disposed onto the semiconductor wafer; andheating the silazane to form the polysilazane on the semiconductor wafer.2. (canceled)3. The method of claim 1 , whereinthe disposing step is performed at a cooling temperature in a range of about −30 to 10° C., and includes a sub-step of using a shower head having plural injecting holes to inject therethrough the silazane solution onto the semiconductor wafer.4. The method of claim 3 , wherein the solvent includes NH claim 3 , and the cooling temperature is in a range of about −10 to 0° C.5. The method of claim 3 , wherein the heating step includes sub-steps of:heating the silazane solution at a drive-out temperature in a range of about 30 to 100° C. to drive out the solvent;venting the driven-out solvent; andannealing the silazane at an annealing temperature in a range of about 200 to 400° C. for an annealing time in a range of about 10 seconds to 1 hour.6. The method of claim 5 , wherein:the drive-out temperature is in a range of about 40 to 60° C.;the annealing temperature is in a range of about 250 to 300° C.; andthe annealing time is in a range of about 30 seconds to 10 minutes.7. The method of claim 1 , further comprising a step of introducing an oxygen and ...

Contact structures and methods of forming the same

Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.

Semiconductor integrated circuit

A method including forming a first insulating film over a first fin structure. The method further includes removing the first insulating film to expose a portion of the first fin structure. The method further includes forming a first oxide film over the exposed portion of the first fin structure using a non-aqueous solvent-based chemical.

Electrostatic Check with Multi-Zone Control

An electrostatic chuck for clamping a warped workpiece has a clamping surface comprising a dielectric layer. The dielectric layer has a field and one or more zones formed of differing dielectric materials. One or more electrodes are coupled to a power supply, and a controller controls a clamping voltage supplied to the one or more electrodes via the power supply. An electrostatic attraction force associated with each of the field and one or more zones of the dielectric layer of the electrostatic chuck is induced, wherein the electrostatic attraction force varies based on the dielectric material of each of the field and one or more zones. The electrostatic attraction force is greater in the one or more zones than in the field, therein attracting warped regions of the workpiece to the clamping surface and clamping the warped workpiece to the clamping surface across a surface of the warped workpiece. 1. An electrostatic chuck , comprising:a clamping surface comprising a dielectric layer, wherein the dielectric layer comprises a field and one or more zones defined therein, wherein the field is comprised of a first dielectric material, and wherein the one or more zones are comprised of a second dielectric material, wherein each of the first dielectric material and second dielectric material have different dielectric constants associated therewith; andone or more electrodes associated with the dielectric layer, wherein a voltage supplied to the one or more electrodes is configured to induce an electrostatic attraction force associated with each of the field and one or more zones, and wherein the electrostatic attraction force varies based on the dielectric material of each of the field and one or more zones.2. The electrostatic chuck of claim 1 , wherein the electrostatic attraction force is greater in the one or more zones than in the field.3. The electrostatic chuck of claim 1 , wherein the one or more zones comprise a central zone associated with a center of the ...

METHOD OF PATTERNING MATERIAL LAYER

A method of patterning a material layer includes the following steps. A first material layer is formed over a substrate, and the first material layer includes a first metal compound. Through a first photomask, portions of the first material layer is exposed with a gamma ray, wherein a first metal ion of the first metal compound in the portions of the first material layer is chemically reduced to a first metal grain. Other portions of the first material layer are removed to form a plurality of first hard mask patterns including the first metal grain. 1. A method of patterning a material layer , comprising:forming a first material layer over a substrate, the first material layer comprising a first metal compound;through a first photomask, exposing portions of the first material layer with a gamma ray, wherein a first metal ion of the first metal compound in the portions of the first material layer is chemically reduced to a first metal grain; andremoving other portions of the first material layer, to form a plurality of first hard mask patterns comprising the first metal grain.2. The method of claim 1 , wherein the first metal compound comprises silver salt claim 1 , and the first hard mask patterns comprise silver patterns.3. The method of claim 1 , further comprising forming a first dielectric layer to fill gaps between the first hard mask patterns.4. The method of claim 3 , wherein forming the first dielectric layer comprises:forming a dielectric material layer over the first hard mask patterns; andperforming a planarization process on the dielectric material layer, wherein a top surface of the first dielectric layer is substantially coplanar with top surfaces of the first hard mask patterns after the planarization process.5. The method of claim 1 , further comprising forming a plurality of second hard mask patterns between and over the first hard mask patterns.6. The method of claim 1 , further comprising:forming a second material layer over the plurality of first ...

Metal Contact Structure and Method of Forming the Same in a Semiconductor Device

A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer. 1. A method of forming a semiconductor device , comprising:forming a first metal layer in an opening defined in a dielectric layer over a substrate;forming a second metal layer in the opening over the first metal layer;forming a third metal layer in the opening over the second metal layer;forming a metal plug in the opening over the third metal layer; andannealing the semiconductor device to react the first metal layer with the second metal layer to form an amorphous layer there-between and to form a silicide layer between the first metal layer and the substrate, the amorphous layer comprising Ni—Ta.2. The method of claim 1 , wherein forming the first metal layer comprises depositing at least one of cobalt (Co) or nickel (Ni) by physical vapor deposition (PVD).3. The method of claim 1 , wherein forming the second metal layer comprises depositing at least one of tantalum (Ta) or titanium (Ti) by physical vapor deposition (PVD).4. The method of claim 1 , wherein forming the third metal layer comprises depositing at least one of cobalt (Co) or ruthenium (Ru) by at least one of atomic layer deposition (ALD) or chemical vapor deposition (CVD).5. The method of claim 1 , wherein the annealing comprises exposing the semiconductor device to a temperature from 200 degrees Celsius to 800 degrees Celsius for a duration from 20 seconds to 1 claim 1 ,000 seconds.6. The method of claim 1 , further comprising planarizing the first metal layer claim 1 , the second metal layer claim 1 , the third metal layer claim 1 , and the metal ...

Interconnect Structure and Method of Forming the Same

An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a contact layer over a substrate; a dielectric layer over the contact layer, wherein the dielectric layer has an opening, the opening exposing a portion of the contact layer; a silicide layer over the exposed portion of the contact layer; a barrier layer along sidewalls of the opening; an alloy layer over the barrier layer; a glue layer over the alloy layer; and a conductive plug over the glue layer. 1. An interconnect structure , comprising:a contact layer over a substrate;a dielectric layer over the contact layer, wherein the dielectric layer has an opening, the opening comprising an exposed portion of the contact layer;a silicide layer over the exposed portion of the contact layer;a barrier layer along sidewalls of the opening;an alloy layer over the barrier layer, the barrier layer interposed between the alloy layer and the dielectric layer;a glue layer over the alloy layer; anda conductive plug over the glue layer.2. The interconnect structure of claim 1 , wherein the contact layer comprises silicon claim 1 , silicon germanium claim 1 , silicon phosphide claim 1 , silicon carbide claim 1 , or a combination thereof.3. The interconnect structure of claim 1 , wherein the silicide layer comprises nickel silicide claim 1 , cobalt silicide claim 1 , titanium silicide claim 1 , tungsten silicide claim 1 , or a combination thereof.4. The interconnect structure of claim 1 , wherein the silicide layer has a thickness in a range from about 30 angstroms (Å) to about 300 angstroms (Å).5. The interconnect structure of claim 1 , wherein the barrier layer is a metal oxide layer.6. The interconnect structure of claim 5 , wherein the metal oxide layer comprises manganese oxide (MnOx) or manganese silicon oxide (MnSiyOz).7. The interconnect structure of claim 1 , wherein the barrier layer has a thickness in a range from about 3 angstroms (Å) to about 30 ...

DIELECTRIC LAYER, INTERCONNECTION STRUCTURE USING THE SAME, AND MANUFACTURING METHOD THEREOF

A method for manufacturing a dielectric layer includes forming a first dielectric film over a substrate. A first porogen is deposited over the first dielectric film. A second dielectric film is formed on and in contact with the first dielectric film and the first porogen. The first porogen is removed. 1. A method for manufacturing a dielectric layer , the method comprising:forming a first dielectric film over a substrate;depositing a first porogen over the first dielectric film;forming a second dielectric film on and in contact with the first dielectric film and the first porogen; andremoving the first porogen.2. The method of claim 1 , further comprising performing a thermal treatment on the first porogen before forming the second dielectric film.3. The method of claim 1 , further comprising performing a surface treatment on a surface of the substrate to form a terminating species on the surface of the substrate before forming the first dielectric film.4. The method of claim 1 , wherein the first and the second dielectric films have the same material.5. The method of claim 1 , wherein the first and the second dielectric films have different materials.6. The method of claim 1 , further comprising:depositing a second porogen over the second dielectric film after removing the first porogen;forming a third dielectric film on the second dielectric film and the second porogen; andremoving the second porogen.7. A method for manufacturing an interconnection structure claim 1 , the method comprising:depositing a first dielectric film over a substrate by a first atomic layer deposition process using first precursors;depositing a porogen over the first dielectric film;depositing a second dielectric film over the porogen and the first dielectric film by a second atomic layer deposition process using second precursors;removing the porogen to form a dielectric layer comprising the first and second dielectric films;forming an opening in the dielectric layer; andforming a ...

PHOTOMASK

A photomask includes a patterned photomask plate and a supporting member. The patterned photomask plate has a pattern region and a peripheral region surrounding the pattern region. The patterned photomask plate includes a plurality of openings in the pattern region. The supporting member directly abuts the patterned photomask plate and is in a peripheral region of the patterned photomask plate. The supporting member is formed from a different material than the patterned photomask plate. 1. A photomask , comprising:a patterned photomask plate having a pattern region and a peripheral region surrounding the pattern region, wherein the patterned photomask plate comprises a plurality of openings in the pattern region; anda supporting member directly abutting the patterned photomask plate and in a peripheral region of the patterned photomask plate, wherein the supporting member is formed from a different material than the patterned photomask plate.2. The photomask of claim 1 , wherein the patterned photomask and the supporting member have a substantially U-shaped cross-section.3. The photomask of claim 1 , wherein the patterned photomask plate has a melting point higher than about 1100° C.4. The photomask of claim 1 , wherein the patterned photomask plate has a thermal expansion coefficient less than about 9×10K.5. The photomask of claim 1 , wherein the patterned photomask plate includes a plurality of light absorber layers.6. The photomask of claim 5 , wherein the light absorber layers are formed from different materials.7. The photomask of claim 1 , wherein the patterned photomask plate is formed from quartz.8. A photomask claim 1 , comprising:a patterned photomask plate having a pattern region formed with a plurality of openings and a peripheral region surrounding the pattern region; anda supporting member in a peripheral region, wherein the patterned photomask plate and the supporting member are an integrally formed structure.9. The photomask of claim 8 , further ...

MECHANISMS FOR CONTROLLING GAS FLOW IN ENCLOSURE

Embodiments of mechanisms for controlling a gas flow in an interface module are provided. A method for controlling a gas flow in an enclosure includes providing the enclosure which is capable of containing a substrate. The method also includes providing a gas into the enclosure. The method further includes cleaning the gas. In addition, the method includes actuating the gas to generate the gas flow, and the gas flow passes through the substrate when the substrate is located in the enclosure. 1. An interface module for transferring at least one substrate , comprising:a housing comprising a plurality of walls, and an enclosure is defined by the walls, wherein the enclosure is capable of containing the substrate;a gas inlet positioned on one of the walls of the housing; anda gas outlet positioned on one of the walls of the housing, wherein when the substrate is located in the enclosure, a gas flow between the gas inlet and the gas outlet passes through the substrate.2. The interface module as claimed in claim 1 , further comprising a circulation assembly claim 1 , wherein the circulation assembly comprises a conduit connected to the gas inlet and the gas outlet claim 1 , and a driving unit configured for driving the gas flow passing through the conduit.3. The interface module as claimed in claim 2 , further comprising a filter unit arranged downstream of the circulation assembly.4. The interface module as claimed in claim 3 , wherein the filter unit comprises a chemical filter and a high-efficiency particulate air filter.5. The interface module as claimed in claim 2 , wherein the circulation assembly further comprises a pressure sensor positioned in the conduit.6. The interface module as claimed in claim 1 , wherein the walls includes an upper wall claim 1 , a lower wall opposite to the upper wall claim 1 , and a side wall connected between the upper wall and the lower wall claim 1 , wherein the gas inlet is positioned on the upper wall claim 1 , and the gas outlet is ...

Ultra-low oxygen and humility loadport and stocker system

One or more apparatuses for adjusting at least one of an oxygen content or a water content in a pod and methods of their use are provided, where one or more semiconductor wafer are selectively stored within a storage chamber of the pod. The apparatus comprises the pod and a pipeline. The pod comprises the storage chamber and a port. The port comprises a receptacle having a first opening and a constraining ring proximate the first opening. The pipeline comprises a pipe, a diffuser attached to a first end of the pipe and a controller attached to a second end of the pipe.

TWO-STEP SHALLOW TRENCH ISOLATION (STI) PROCESS

Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel. 1. A method of forming an integrated circuit device , comprising:etching a trench in a silicon substrate;depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate;capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material;epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material; andforming a gate structure on the silicon layer, the gate structure defining a channel.2. The method of claim 1 , further comprising depositing the first layer of isolation material using a high density oxide deposition process.3. The method of claim 1 , further comprising depositing the second layer of isolation material using a high density oxide deposition process.4. The method of claim 1 , further comprising depositing the second layer of isolation material such that a portion thereof abuts the substrate.5. The method of claim 1 , further comprising depositing the first layer of isolation material such that a portion ...

SEMICONDUCTOR DEVICE AND FORMATION THEREOF

A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer. 1. A method of forming a semiconductor structure comprising:forming a first metal layer in an opening defined by a dielectric layer over a substrate;forming a second metal layer in the opening over the first metal layer;forming a third metal layer in the opening over the second metal layer;annealing the semiconductor structure to form a metal oxide layer from the first metal layer and to form a silicide layer over the metal oxide layer from the second metal layer; andforming a metal plug in the opening over the third metal layer.2. The method of claim 1 , wherein forming the first metal layer comprises:depositing at least one of zinc, oxide, or titanium by at least one of atomic layer deposition or physical vapor deposition.3. The method of claim 1 , wherein forming the second metal layer comprises:depositing at least one of titanium, nickel, tungsten, or cobalt by atomic layer deposition.4. The method of claim 1 , wherein forming the third metal layer comprises:depositing at least one of titanium or nitrogen over the second metal layer.5. The method of claim 1 , wherein annealing the semiconductor structure comprises:exposing the semiconductor ...

WAFER POD HANDLING METHOD

A method for wafer pod handling includes at least the following steps. A wafer pod is moved into a load chamber by conveying the wafer pod to the load chamber via one side of a track and removing a cover of the load chamber via an opposing side of the track. The wafer pod that is inside the load chamber is coupled to a port of a platform that is linked to the load chamber. A wafer to be processed is moved from the wafer pod and out of the load chamber to the platform for performing a semiconductor process. Other methods for wafer pod handling are also provided. 1. A method for wafer pod handling , comprising:moving a wafer pod into a load chamber by conveying the wafer pod to the load chamber via one side of a track and removing a cover of the load chamber via an opposing side of the track;coupling the wafer pod that is inside the load chamber to a port of a platform that is linked to the load chamber; andmoving a wafer to be processed from the wafer pod and out of the load chamber to the platform for performing a semiconductor process.2. The method for wafer pod handling of claim 1 , further comprising:moving the wafer to be processed from the platform to a processing module to perform the semiconductor process via a transfer mechanism.3. The method for wafer pod handling of claim 1 , further comprising:sealing the load chamber by moving the cover of the load chamber back in place, after loading the wafer pod into the load chamber.4. The method for wafer pod handling of claim 1 , further comprising:forming a vacuum environment in the load chamber before moving out the wafer to be processed.5. The method for wafer pod handling of claim 1 , wherein removing the cover of the load chamber via the opposing side of the track comprises:applying a force via the opposing side of the track to remove the cover of the load chamber.6. The method for wafer pod handling of claim 1 , further comprising:moving the wafer pod from the load chamber to a buffer port that is disposed ...

Composite Contact Plug Structure and Method of Making Same

An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium. 1. A device comprising:a semiconductor substrate;a silicide region in the semiconductor substrate;a dielectric layer over the semiconductor substrate;a conductive film extending through the dielectric layer; and a diffusion barrier layer contacting and having a different material composition than the conductive film, the conductive film is disposed between the diffusion barrier layer and the dielectric layer, the diffusion barrier layer further contacting the silicide region;', 'a conductive liner contacting a sidewall and a top surface of the diffusion barrier layer, the conductive liner comprises cobalt or ruthenium, and the conductive liner has a different material composition than the diffusion barrier layer; and', 'a conductive core contacting a sidewall and a top surface of the conductive liner, the conductive core has a different material composition than the conductive liner., 'a contact plug extending through the dielectric layer to the silicide region, wherein the contact plug comprises2. The device of claim 1 , wherein the conductive film does not extend below the diffusion barrier layer.3. The device of claim 1 , wherein the conductive liner extends a first distance from a bottom surface of the conductive core to the top surface of the diffusion barrier layer claim 1 , the conductive liner extends a second distance from the sidewall of the diffusion barrier layer to a sidewall of the conductive core claim 1 , and wherein the second distance is less than the first distance.4. The device of claim 3 , wherein the diffusion barrier layer extends a third distance from a bottom surface of the conductive ...

METAL BUMPS FOR COOLING DEVICE CONNECTION

A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate includes depositing a first-side UBM layer on a first surface of the substrate, and forming a plurality of first-side metal bumps on the first surface of the substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the substrate, and the first surface and the second surface are opposite of each other. The method includes forming a plurality of second-side metal bumps on the second surface of the substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps. 1. A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate , comprising:depositing a first-side UBM layer on a first surface of the semiconductor substrate;forming a plurality of first-side metal bumps on the first surface of the semiconductor substrate after the first-side UBM layer is deposited;forming a second-side UBM layer on a second side of the semiconductor substrate, wherein the first surface and the second surface are opposite of each other;forming a plurality of second-side metal bumps on the second surface of the semiconductor substrate after the second-side UBM layer is deposited;removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed; andreflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.2. The method of claim 1 , wherein the plurality of first-side metal bumps and the plurality of second-side metal bumps are solder bumps or copper posts.3. ...

Wafer processing system using multi-zone chuck

A wafer processing system includes at least one metrology chamber, a process chamber, and a controller. The at least one metrology chamber is configured to measure a thickness of a first layer on a back side of a wafer. The process chamber is configured to perform a treatment on a front side of the wafer. The front side is opposite the back side. The process chamber includes therein a multi-zone chuck. The multi-zone chuck is configured to support the back side of the wafer. The multi-zone chuck has a plurality of zones with controllable clamping forces for securing the wafer to the multi-zone chuck. The controller is coupled to the metrology chamber and the multi-zone chuck. The controller is configured to control the clamping forces in the corresponding zones in accordance with measured values of the thickness of the first layer in the corresponding zones.

Mechanisms for processing wafer

Embodiments of mechanisms for processing a wafer are provided. A method for processing a wafer includes creating an exhaust flow in a fluid conduit assembly that is connected to a process module used for processing the wafer. The method also includes detecting the exhaust pressure in the fluid conduit assembly. The method further includes determining whether the exhaust pressure meets a set point. In addition, the method includes regulating the exhaust flow if the exhaust pressure fails to meet the set point.

COMPOSITE CONTACT PLUG STRUCTURE AND METHOD OF MAKING SAME

An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium. 1. A conductive structure comprising:a conductive core disposed in a dielectric layer of an integrated circuit chip;a conductive liner in direct contact with and comprising a different material than the conductive core, wherein the conductive liner has a substantially constant thickness along an entirety of a sidewall of the conductive core, and wherein the conductive liner is thinner along the sidewall of the conductive core than along a bottom surface of the conductive core; anda diffusion barrier layer on a sidewall and a bottom surface of the conductive liner.2. The conductive structure of claim 1 , wherein the conductive liner comprises cobalt or ruthenium.3. The conductive structure of claim 1 , further comprising a conductive film on a sidewall of the diffusion barrier layer claim 1 , wherein the diffusion barrier layer is disposed between the conductive film and the conductive liner.4. The conductive structure of claim 3 , wherein the conductive film comprises titanium claim 3 , cobalt claim 3 , nickel claim 3 , or tungsten.5. The conductive structure of claim 3 , wherein the conductive film is not disposed along at least a portion of a bottom surface of the diffusion barrier layer.6. The conductive structure of claim 1 , wherein the conductive core comprises tungsten claim 1 , cobalt claim 1 , or ruthenium.7. The conductive structure of claim 1 , wherein a thickness of the conductive liner along the sidewall of the conductive core is greater than a thickness of the diffusion barrier layer.8. The conductive structure of claim 1 , wherein the conductive liner is at least ten times thinner along the ...

Method for Silicide Formation

Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region. 1. A method comprising:forming an opening in a dielectric layer to expose a first portion of a surface of a substrate;depositing a silicon-containing capping layer along the exposed first portion of the surface of the substrate and sidewalls of the opening;depositing a metal layer over the silicon-containing capping layer in the opening, the metal layer comprising cobalt, nickel, tungsten, or a combination thereof;annealing the silicon-containing capping layer and the metal layer to form a metal-silicide layer in the opening along the first portion of the surface of the substrate and the sidewalls of the dielectric layer; andfilling a conductive material in the opening over the metal-silicide layer and over the dielectric layer.2. The method of further comprising:depositing a glue layer over the metal layer in the opening, the conductive material being over the glue layer.3. The method of claim 2 , wherein annealing the silicon-containing capping layer and the metal layer to form a metal-silicide layer is after depositing the glue layer.4. The method of claim 2 , wherein after the annealing the silicon-containing capping layer and the metal layer to form the metal-silicide layer claim 2 , a portion of the metal layer remains unreacted and is interposed between the metal-silicide ...

METHOD OF FORMING CONDUCTIVE BUMPS FOR COOLING DEVICE CONNECTION

A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate includes depositing a first-side UBM layer on a first surface of the substrate, and forming a plurality of first-side metal bumps on the first surface of the substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the substrate, and the first surface and the second surface are opposite of each other. The method includes forming a plurality of second-side metal bumps on the second surface of the substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps. 1. A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate , comprising:depositing a first-side UBM layer on a first surface of the semiconductor substrate;forming a plurality of first-side metal bumps on the first surface of the semiconductor substrate after the first-side UBM layer is deposited;forming a second-side UBM layer on a second side of the semiconductor substrate, wherein the first surface and the second surface are opposite of each other;forming a plurality of second-side metal bumps on the second surface of the semiconductor substrate after the second-side UBM layer is deposited;removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed; andreflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.2. The method of claim 1 , wherein the plurality of first-side metal bumps and the plurality of second-side metal bumps are solder bumps or copper posts.3. ...

Two-Step Shallow Trench Isolation (STI) Process

Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel.

DIELECTRIC LAYER, INTERCONNECTION STRUCTURE USING THE SAME, AND MANUFACTURING METHOD THEREOF

A structure includes a first dielectric film and a second dielectric film. The second dielectric film is formed on and in contact with the first dielectric film, in which a first pore is formed between the first dielectric film and the second dielectric film, and a thickness of the first dielectric film is smaller than a diameter of the first pore. 1. A structure , comprising:a first dielectric film; anda second dielectric film on and in contact with the first dielectric film, wherein a first pore is formed between the first dielectric film and the second dielectric film, and a thickness of the first dielectric film is smaller than a diameter of the first pore.2. The structure of claim 1 , wherein a thickness of the second dielectric film is smaller than a diameter of the first pore.3. The structure of claim 1 , wherein the first pore has a diameter in a range from about 3 nm to about 10 nm.4. The structure of claim 1 , wherein the first dielectric film is a monolayer.5. The structure of claim 1 , wherein the second dielectric film is a monolayer.6. The structure of claim 1 , further comprising a third dielectric film on and in contact with the second dielectric film claim 1 , wherein a second pore is formed between the second dielectric film and the third dielectric film.7. The structure of claim 6 , wherein the third dielectric film is a monolayer.8. The structure of claim 1 , wherein the first and the second dielectric films have the same material.9. The structure of claim 1 , wherein the first and the second dielectric films have different materials.10. The structure of claim 1 , wherein the first and the second dielectric films comprise carbon.11. A structure claim 1 , comprising:a filling material;a dielectric layer laterally surrounding the filling material;an etch stop layer over the dielectric layer and the filling material;a first dielectric monolayer extending along a top surface of the etch stop layer;a second dielectric monolayer over the first ...

APPARATUS AND METHOD FOR PROCESSING WAFER

A method includes delivering a wafer into a process chamber, applying a thermal energy to the wafer by a heat source, and moving the heat source substantially along a longitudinal direction of the heat source with respect to the wafer. An apparatus that performs the method is also disclosed. 1. A method , comprising:delivering a wafer into a process chamber;applying a thermal energy to the wafer by a heat source; andmoving the heat source substantially along a longitudinal direction of the heat source with respect to the wafer.2. The method of claim 1 , wherein applying the thermal energy to the wafer comprises enabling the heat source to emit radiation upward.3. The method of claim 1 , wherein applying the thermal energy to the wafer comprises enabling the heat source to emit radiation downward.4. The method of claim 1 , wherein moving the heat source comprises moving the heat source upward to increase a temperature of the wafer.5. The method of claim 1 , wherein moving the heat source comprises moving the heat source downward to increase a temperature of the wafer.6. The method of claim 1 , wherein moving the heat source comprises moving a movable portion that is coupled to the heat source and that is telescopically and movably received in a stationary portion.7. A method claim 1 , comprising:delivering a wafer into a process chamber;applying thermal energy to the wafer by a heat source; androtating the heat source using a spherical joint.8. The method of claim 7 , wherein rotating the heat source is such that the heat source is slanted from a vertical direction.9. The method of claim 7 , wherein rotating the heat source comprises a ball-shaped end in a ball socket.10. The method of claim 7 , wherein rotating the heat source comprises swinging a movable device coupled to the heat source.11. The method of claim 7 , further comprising moving the heat source substantially along a longitudinal direction of the heat source.12. The method of claim 11 , wherein moving ...

OVERHEAD CRANE

One or more overhead cranes are provided. The overhead cranes include a first horizontal rail having a first end and a second end, a second horizontal rail having a third end and a fourth end, a first post connected to the first end of the first horizontal rail, a second post connected to the second end of the first horizontal rail, a third post connected to the third end of the second horizontal rail, a fourth post connected to the fourth end of the second horizontal rail and a cross member extending from the first horizontal rail to the second horizontal rail. The cross member includes a center span section, a first side arm and a second side arm. In some embodiments, the center span section is trapezoidialy shaped. In some embodiments, the overhead crane includes a vacuum system. 1. An overhead crane comprising:a first horizontal rail having a first end and a second end;a second horizontal rail having a third end and a fourth end, the second horizontal rail positioned parallel to and spaced apart from the first horizontal rail;a first post connected to the first end of the first horizontal rail;a second post connected to the second end of the first horizontal rail;a third post connected to the third end of the second horizontal rail;a fourth post connected to the fourth end of the second horizontal rail; and a center span section having a first side and a second side;', 'a first side arm connecting the first horizontal rail to the first side of the center span section; and', 'a second side arm connecting the second horizontal rail to the second side of the center span section., 'a cross member extending from the first horizontal rail to the second horizontal rail comprising2. The overhead crane of claim 1 , comprising:a dust collector;a dust sensor; anda vacuum pipeline.3. The overhead crane of claim 2 , wherein the vacuum pipeline is contained within at least one of the first post claim 2 , the second post claim 2 , the third post or the fourth post.4. The ...

ATOMIC LAYER DEPOSITION APPARATUS AND SEMICONDUCTOR PROCESS

An atomic layer deposition apparatus comprises a processing chamber, at least one partition and an injector. The at least one partition is disposed in the processing chamber for dividing the processing chamber into a plurality of sections. The injector includes a plurality of nozzles disposed in the processing chamber and configured to respectively provide a reacting gaseous flow to each of the plurality of sections. A semiconductor process is also provided. 1. An atomic layer deposition apparatus , comprising:a processing chamber;at least one partition disposed in the processing chamber for dividing the processing chamber into a plurality of sections; andan injector comprising a plurality of nozzles disposed in the processing chamber and configured to respectively provide a reacting gaseous flow to each of the plurality of sections.2. The atomic layer deposition apparatus according to claim 1 , wherein the plurality of nozzles comprises:a first nozzle having a first geometric parameter and configured to provide a first reacting gaseous flow to a first section of the processing chamber; anda second nozzle having a second geometric parameter different from the first geometric parameter and configured to provide a second reacting gaseous flow to a second section of the processing chamber.3. The atomic layer deposition apparatus according to claim 2 , wherein the first geometric parameter comprises an opening size of the first nozzle claim 2 , and the second geometric parameter comprises an opening size of the second nozzle.4. The atomic layer deposition apparatus according to claim 1 , wherein the processing chamber comprises a plurality of pumping ports configured to evacuate the reacting gaseous flows from the processing chamber.5. The atomic layer deposition apparatus according to claim 4 , wherein the plurality of pumping ports comprises:a first pumping port having a third geometric parameter and configured to evacuate a first reacting gaseous flows from a first ...

SEMICONDUCTOR PROCESSING STATION, SEMICONDUCTOR PROCESS AND METHOD OF OPERATING SEMICONDUCTOR PROCESSING STATION

A semiconductor processing station comprises a platform and a load port, wherein the platform includes an intake/outtake port and a plurality of processing modules. The load port includes a load chamber, a movable cover and a carrier transfer module. The load chamber communicates with the intake/outtake port and has a load opening at its top end for receiving a transport carrier within the load chamber. The movable cover is disposed at the load opening and is configured to seal the load opening. The carrier transfer module is configured to transfer the transport carrier to the intake/outtake port. A semiconductor process and a method of operating a semiconductor processing station are also provided. 1. A semiconductor processing station , comprising:a platform comprising an intake/outtake port and a plurality of processing modules; and a load chamber communicating with the intake/outtake port and having a load opening at its top end for receiving a transport carrier within the load chamber;', 'a movable cover disposed at the load opening and configured to seal the load opening; and', 'a carrier transfer module configured to transfer the transport carrier to the intake/outtake port., 'a load port comprising2. The semiconductor processing station of claim 1 , wherein the load opening is sealed by the movable cover to form a vacuum environment containing the transport carrier.3. The semiconductor processing station of claim 1 , wherein the platform further comprises:a central transfer module communicating with the intake/outtake port and the plurality of processing modules; anda substrate transfer mechanism configured in the central transfer module to pick up and traversely transfer a plurality of substrates from the transport carrier to the plurality of processing modules in sequence.4. The semiconductor processing station of claim 3 , wherein the carrier transfer module comprises a carrier lift mechanism configured to move the transport carrier upward and downward in ...

SEMICONDUCTOR DEVICE AND FORMATION THEREOF

A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer. 1. A semiconductor device comprising:a metal plug in a first opening defined by a dielectric layer over a substrate, the metal plug over a metal oxide layer; anda silicide layer between the metal oxide layer and the metal plug.2. The semiconductor device of claim 1 , the metal plug comprising tungsten.3. The semiconductor device of claim 1 , the metal oxide layer comprising at least one of titanium or zinc.4. The semiconductor device of claim 1 , the metal oxide layer comprising an oxygen gradient claim 1 , such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer.5. The semiconductor device of claim 1 , comprising a first metal layer on a sidewall of the first opening defined by the dielectric layer claim 1 , the first metal layer comprising at least one of zinc claim 1 , oxide claim 1 , or titanium.6. The semiconductor device of claim 5 , comprising a second metal layer on the first metal layer claim 5 , the second metal layer comprising at least one of titanium claim 5 , nickel claim 5 , tungsten claim 5 , or cobalt.7. The semiconductor device of claim 6 , comprising a ...

SEMICONDUCTOR DEVICE AND FORMATION THEREOF

A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate. The metal plug has a contact bottom surface that is substantially convex. The substantially convex contact bottom surface has an increased contact area as compared to a contact bottom surface of a metal plug that is not substantially convex. The increased contact area decreases a resistance of the metal plug. The increased contact area requires a smaller deposition amount to form a metal plug seed layer of the metal plug than a semiconductor device with a smaller contact area. A smaller deposition amount reduces an overhang of the deposited metal plug seed layer material. A reduced overhang of the deposited metal plug seed layer material reduces pitting in a metal plug formed from the deposited metal plug seed layer material. 1. A semiconductor device comprising:a metal plug in a first opening defined by a dielectric layer over a substrate, the metal plug having a contact bottom surface that is substantially convex; anda silicide layer between the substrate and the metal plug, the silicide layer having a silicide layer top surface that is substantially concave to interface with the substantially convex contact bottom surface of the metal plug.2. The semiconductor device of claim 1 , the contact bottom surface having a first distal location claim 1 , a second distal location and an apex claim 1 , the first distal location and the second distal location lying within a plane and separated a distal distance from one another claim 1 , the apex separated an apex distance from the plane claim 1 , the apex distance about 0.2 to about 2.5 times the distal distance.3. The semiconductor device of claim 1 , the apex substantially equidistant from the first distal location and the second distal location such that a first distance between the first distal location and the apex is substantially equal to a second distance between the ...

Barrier Structure for Copper Interconnect

A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming an opening in the dielectric layer, forming a metal-containing layer overlying the opening in the dielectric layer, forming a conformal protective layer overlying the metal-containing layer, filling a conductive layer in the opening, and performing a thermal process to form a metal oxide layer barrier layer underlying the metal-containing layer. 1. A semiconductor device comprising:a dielectric layer overlying a substrate, the dielectric layer having a recess;a first barrier layer along a sidewall of the recess;a second barrier layer over the first barrier layer; anda conductive material over the second barrier layer, wherein the conductive material and the first barrier layer have a same chemical element.2. The semiconductor device of claim 1 , wherein the conductive material comprises a seed layer and a conductive fill material claim 1 , the seed layer being a different material than the conductive fill material.3. The semiconductor device of claim 1 , wherein the conductive material is a copper-manganese (CuMn) layer.4. The semiconductor device of claim 3 , wherein a ratio of manganese (Mn) to copper (Cu) in the CuMn layer ranges from about 0.02% to about 5%.5. The semiconductor device of claim 1 , wherein the second barrier layer comprises cobalt (Co).6. The semiconductor device of claim 1 , further comprising a silicide layer interposed between the second barrier layer and the substrate.7. The semiconductor device of claim 6 , wherein the silicide layer is a cobalt silicide (CoSi) layer.8. The semiconductor device of claim 1 , wherein the first barrier layer comprises MnOand/or MnSiO.9. A semiconductor device comprising:a dielectric layer overlying a substrate;an interconnect in the dielectric layer;a cobalt (Co) layer interposed between the interconnect and the dielectric layer;{'sub': 'x', 'a manganese oxide (MnO) layer interposed between the Co ...

Barrier Structure for Copper Interconnect

A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming an opening in the dielectric layer, forming a metal-containing layer overlying the opening in the dielectric layer, forming a conformal protective layer overlying the metal-containing layer, filling a conductive layer in the opening, and performing a thermal process to form a metal oxide layer barrier layer underlying the metal-containing layer. 1. A method , comprising:forming a dielectric layer overlying a substrate;forming an opening in the dielectric layer;forming a metal-containing layer overlying the opening in the dielectric layer;forming a conformal protective layer overlying the metal-containing layer;filling a conductive layer in the opening; andperforming a thermal process to form a metal oxide barrier layer underlying the metal-containing layer.2. The method of claim 1 , wherein the metal-containing layer is a copper-containing layer.3. The method of claim 2 , wherein the copper-containing layer comprises an additive metal element including manganese (Mn) claim 2 , aluminum (Al) claim 2 , titanium (Ti) claim 2 , niobium (Nb) claim 2 , chromium (Cr) claim 2 , vanadium (V) claim 2 , yttrium (Y) claim 2 , technetium (Tc) claim 2 , rhenium (Re) claim 2 , cobalt (Co) claim 2 , or combinations thereof.4. The method of claim 1 , wherein the metal-containing layer is a CuMn layer claim 1 , a CuTi layer claim 1 , a CuNb layer claim 1 , a CuAl layer claim 1 , a CuCo layer claim 1 , a CuV layer claim 1 , a CuY layer claim 1 , a CuTc layer claim 1 , a CuRe layer claim 1 , or combinations thereof.5. The method of claim 4 , wherein a ratio of manganese (Mn) to copper in the CuMn layer ranges from about 0.02% to about 5%.6. The method of claim 1 , wherein the metal-containing layer has a thickness ranging from about 20 Angstroms to about 200 Angstroms.7. The method of claim 1 , wherein the conformal protective layer is a cobalt (Co) layer claim 1 , a ...

Composite Contact Plug Structure and Method of Making Same

An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium. 1. A method for forming a contact plug , the method comprising:forming a dielectric layer over a substrate;patterning an opening in the dielectric layer, the opening exposing the substrate;depositing a diffusion barrier layer in the opening;depositing a conductive liner comprising cobalt or ruthenium over the diffusion barrier layer, wherein the conductive liner is thicker on a bottom surface of the opening than on sidewalls of the opening; andfilling remaining portions of the opening with a conductive core, wherein the conductive core and the conductive liner comprise different conductive materials, and wherein the conductive liner is disposed between the conductive core and the diffusion barrier layer.2. The method of claim 1 , wherein depositing the diffusion barrier layer comprises depositing tantalum or tantalum nitride.3. The method of further comprising claim 1 , before depositing the diffusion barrier layer claim 1 , depositing a conductive film on the bottom surface of the opening claim 1 , wherein the conductive film contacts the substrate.4. The method of further comprising claim 3 , after filling the remaining portions of the opening with the conductive core claim 3 , forming a silicide region in an upper portion of the substrate.5. The method of claim 4 , wherein forming the silicide region comprises an annealing process claim 4 , and wherein the annealing process diffuses at least a portion of the conductive film into the upper portion of the substrate.6. The method of claim 4 , wherein filling the remaining portions of the opening with the conductive core comprises filling the remaining portions ...

Interconnect Structure and Method of Forming the Same

An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a contact layer over a substrate, a dielectric layer over the contact layer, a silicide layer over the exposed portion of the contact layer, a barrier layer along sidewalls of the opening, an alloy layer over the barrier layer, a glue layer over the alloy layer, and a conductive plug over the glue layer, wherein the dielectric layer has an opening, and the opening exposes a portion of the contact layer. 1. A method of forming an interconnect structure , the method comprising:forming a contact layer over a substrate;forming a dielectric layer over the contact layer;forming an opening through the dielectric layer to an exposed portion of the contact layer;forming an alloy layer along sidewalls of the opening and the exposed portion of the contact layer;forming a glue layer over the alloy layer;performing a thermal treatment to form a silicide layer, the alloy layer over and in contact with the silicide layer, the silicide layer adjacent the exposed portion of the contact layer, wherein the thermal treatment further forms a barrier layer interposed between the dielectric layer and the alloy layer; andforming a conductive plug over the glue layer in the opening.2. The method of claim 1 , wherein:{'sub': x', 'y', 'z, 'the barrier layer comprises manganese oxide (MnO)or manganese silicon oxide (MnSiO);'}the alloy layer comprises a main metal and an additive metal; anda ratio of the additive metal to the main metal is from about 0.01 atomic percent to about 25 atomic percent.3. The method of claim 2 , wherein the main metal comprises nickel claim 2 , cobalt claim 2 , titanium claim 2 , tungsten claim 2 , or a combination thereof.4. The method of claim 2 , wherein the additive metal comprises manganese.5. The method of claim 1 , wherein the contact layer comprises silicon claim 1 , silicon germanium claim 1 , silicon phosphide claim 1 , silicon ...

SEMICONDUCTOR DEVICE AND FORMATION THEREOF

A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer. 1. A method of forming a semiconductor structure comprising:forming a first metal layer in an opening defined by a dielectric layer;forming a second metal layer over the first metal layer;annealing the semiconductor structure to form a metal oxide layer from the first metal layer after forming the second metal layer; andforming a metal plug in the opening over the metal oxide layer.2. The method of claim 1 , wherein annealing the semiconductor structure comprises forming a silicide layer from the second metal layer.3. The method of claim 1 , wherein a portion of the second metal layer overlies the metal oxide layer after annealing the semiconductor structure.4. The method of claim 1 , comprising:forming a third metal layer over the second metal layer prior to annealing the semiconductor structure.5. The method of claim 1 , wherein annealing the semiconductor structure to form a metal oxide layer comprises forming the metal oxide layer such that a first portion of the metal oxide layer has a first oxygen concentration and a second portion of the metal oxide layer has a second oxygen concentration different than the first oxygen concentration.6. The ...

GAMMA RAY GENERATOR? GAMMA RAY LITHOGRAPHY SYSTEM AND METHOD OF PERFORMING GAMMA RAY LITHOGRAPHY

A gamma ray generator includes a plate, a plurality of holes and a plurality of gamma ray sources. The plate is configured to rotate along a rotational axis. The holes are disposed in the plate, and the holes are arranged in a matrix. The gamma ray sources are respectively placed in the holes. 1. A gamma ray generator , comprising:a plate, configured to rotate along a rotational axis;a plurality of holes in the plate, wherein the holes are arranged in a matrix; anda plurality of gamma ray sources, respectively placed in the holes.2. The gamma ray generator of claim 1 , wherein the gamma ray sources radiate gamma rays through bottom openings of the holes claim 1 , respectively.3. The gamma ray generator of claim 1 , wherein the hole has a top opening and a bottom opening opposite to the top opening claim 1 , a diameter of the top opening is not less than a diameter of the gamma ray source claim 1 , and a diameter of the bottom opening is less than the diameter of the gamma ray source.4. The gamma ray generator of claim 1 , wherein the hole has an upper portion and a lower portion connecting to the upper portion claim 1 , and the gamma ray source is placed at an interface between the upper portion and the upper portion.5. The gamma ray generator of claim 1 , wherein a diameter of a bottom opening of the hole decreases as the hole becomes closer to the rotational axis.6. The gamma ray generator of claim 1 , wherein a separation between the holes increases as the holes become closer to the rotational axis.7. The gamma ray generator of claim 1 , wherein the holes are arranged along a plurality of concentric circular paths.8. A gamma ray generator claim 1 , comprising:a shaft, configured to rotate along a rotational axis;a plurality of holders surrounding and connecting to the shaft; anda plurality of gamma ray sources, respectively placed in the holders.9. The gamma ray generator of claim 8 , wherein the gamma ray sources radiate gamma rays through bottom openings of the ...

Semiconductor device and formation thereof

A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer.

LITHOGRAPHY DEVICE AND APPARATUS AND METHOD FOR LITHOGRAPHY DEVICE

An apparatus for a lithography device is provided, which includes a laser-based particle eliminating component and a particle collector. The laser-based particle eliminating component includes a laser emitter and a laser absorbing member. The laser emitter is configured to emit laser beams for irradiating particles in a space near a photomask of the lithography device. The laser absorbing member is disposed opposite to the laser emitter for absorbing the laser beams. The particle collector is configured for collecting the irradiated particles. 1. An apparatus for a lithography device , the apparatus comprising: a laser emitter configured to emit laser beams for irradiating particles in a space near a photomask of the lithography device; and', 'a laser absorbing member disposed opposite to the laser emitter for absorbing the laser beams;, 'a laser-based particle eliminating component, comprisinga particle collector for collecting the irradiated particles; anda laser source configured to generate light, wherein a first portion of the light is transmitted to the laser emitter for emitting the laser beams, and a second portion of the light is used for generating extreme ultraviolet (eUV) light for a process of the lithography device.2. The apparatus of claim 1 , wherein a power of the laser beams emitted by the laser emitter is substantially greater than 10 Watts (W).3. The apparatus of claim 1 , further comprising:a cooler disposed against the laser absorbing member for cooling the laser absorbing member.4. The apparatus of claim 1 , further comprising:a force field generator disposed between the particle collector and the laser-based particle eliminating component for attracting the irradiated particles.5. The apparatus of claim 4 , wherein a magnitude of an electric field generated by the force field generator is substantially from 10Volts per meter (V/m) to 10V/m.6. The apparatus of claim 1 , wherein the particle collector comprises a static charge particle ...

Rotation plus vibration magnet for magnetron sputtering apparatus

In some embodiments, the present disclosure relates to a plasma processing system having a magnetron that provides a symmetric magnetic track through a combination of vibrational and rotational motion. The disclosed magnetron has a magnetic element that generates a magnetic field. The magnetic element is attached to an elastic element connected between the magnetic element and a rotational shaft that rotates the magnetic element about a center of the sputtering target. The elastic element may vary its length during rotation of the magnetic element to change the radial distance between the rotational shaft and the magnetic element. The resulting magnetic track enables concurrent motion of the magnetic element in both an angular direction and a radial direction. Such motion enables a symmetric magnetic track that provides good wafer uniformity and a short deposition time.

Metal Contact Structure and Method of Forming the Same

A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer. 1. A semiconductor device comprising:a silicide layer over a substrate;a metal plug in an opening defined by a dielectric layer over the substrate;a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer;a second metal layer over the first metal layer; andan amorphous layer between the first metal layer and the second metal layer.2. The semiconductor device of claim 1 , wherein the first metal layer comprises at least one of cobalt (Co) or nickel (Ni).3. The semiconductor device of claim 1 , wherein the first metal layer has a thickness ranging from about 30 angstroms to about 250 angstroms.4. The semiconductor device of claim 1 , wherein the silicide layer comprises cobalt silicide (CoSi) claim 1 , nickel silicide (NiSi) claim 1 , or combinations thereof and has a thickness ranging from about 30 angstroms to about 200 angstroms.5. The semiconductor device of claim 1 , wherein the second metal layer is a metal diffusion barrier layer.6. The semiconductor device of claim 5 , wherein the metal diffusion barrier layer comprises tantalum (Ta) claim 5 , titanium (Ti) claim 5 , or combinations thereof.7. The semiconductor device of claim 1 , wherein the second metal layer has a thickness ranging from about 20 angstroms to about 200 angstroms.8. The semiconductor device of claim 1 , wherein the amorphous layer comprises Co—Ta claim 1 , Co—Ti claim 1 , Ni—Ta claim 1 , Ni—Ti claim 1 , or combinations thereof.9. The semiconductor device of claim 1 , wherein the metal ...

Composite Contact Plug Structure and Method of Making Same

An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium. 1. A contact plug comprising: a conductive core; and', 'a conductive liner on a sidewall and a bottom surface of the conductive core, wherein the conductive liner comprises cobalt or ruthenium; and, 'a bilayer structure comprisinga diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure.2. The contact plug of claim 1 , further comprising a conductive film on a sidewall of the diffusion barrier layer claim 1 , wherein the diffusion barrier layer is disposed between the conductive film and the bilayer structure.3. The contact plug of claim 2 , wherein the conductive film comprises titanium claim 2 , cobalt claim 2 , nickel claim 2 , or tungsten.4. The contact plug of claim 1 , wherein the diffusion barrier layer comprises tantalum or tantalum nitride.5. The contact plug of claim 1 , wherein the conductive core comprises tungsten.6. The contact plug of claim 1 , wherein the conductive liner comprises ruthenium and the conductive core comprises cobalt.7. The contact plug of wherein the conductive liner comprises cobalt and the conductive core comprises ruthenium.8. A semiconductor device comprising:a dielectric layer; a conductive core;', 'a conductive liner on sidewalls and a bottom surface of the conductive core, wherein the conductive liner comprises cobalt or ruthenium; and', 'a diffusion barrier layer on sidewalls and a bottom surface of the conductive liner, wherein the conductive liner is disposed between the diffusion barrier layer and the conductive core; and, 'a contact plug extending through the dielectric layer, wherein the contact plug comprisesa silicide region under the ...

POLISHING SYSTEM

A polishing system includes a wafer support that holds a wafer, the wafer having a first diameter. The polishing system further includes a first polishing pad that polishes a first region of the wafer, the first polishing pad having a second diameter greater than the first diameter. The polishing system further includes an auxiliary polishing system comprising at least one second polishing pad that polishes a second region of the wafer, wherein the second polishing pad has a third diameter less than the first diameter, and the wafer support is configured to support the wafer during use of the first polishing pad and the auxiliary polishing system. 1. A polishing system comprising:a wafer support that holds a wafer, the wafer having a first diameter;a first polishing pad that polishes a first region of the wafer, the first polishing pad having a second diameter greater than the first diameter; andan auxiliary polishing system comprising at least one second polishing pad that polishes a second region of the wafer, wherein the second polishing pad has a third diameter less than the first diameter, and the wafer support is configured to support the wafer during use of the first polishing pad and the auxiliary polishing system.2. The polishing system of claim 1 , wherein the wafer support is a wafer table.3. The polishing system of claim 1 , wherein the wafer support is a polishing head.4. The polishing system of claim 1 , further comprising:a pad positioning mechanism that moves the first polishing pad in three dimensions relative to a surface of the semiconductor wafer.5. The polishing system of claim 1 , further comprising:a slurry supply system that introduces slurry to the first polishing pad.6. The polishing system of claim 1 , wherein the first polishing pad is a bevel polishing pad claim 1 , and the region is a bevel of the wafer.7. The polishing system of claim 1 , wherein the second region is a ring region approximately concentric to the semiconductor wafer and ...

Pvd apparatus and method with deposition chamber having multiple targets and magnets

A thin film deposition system and method provide for multiple target assemblies that may be separately powered. Each target assembly includes a target and associated magnet or set of magnets. The disclosure provides a tunable film profile produced by multiple power sources that separately power the target arrangements. The relative amounts of power supplied to the target arrangements may be customized to provide a desired film and may be varied in time to produce a film with varied characteristics.

METAL-SEMICONDUCTOR CONTACT STRUCTURE WITH DOPED INTERLAYER

Disclosed herein is a method of forming a metal-to-semiconductor contact with a doped metal oxide interlayer. An insulating layer is formed on a top surface of a semiconductor substrate with target region at the top surface of the semiconductor substrate. An opening is etched through the insulating layer with the opening exposing a top surface of a portion of the target region. A doped metal oxide interlayer is formed in the opening and contacts the top surface of the target region. The remainder of the opening is filled with a metal plug, the doped metal oxide interlayer disposed between the metal plug and the substrate. The doped metal oxide interlayer is formed from one of tin oxide, titanium oxide or zinc oxide and is doped with fluorine. 1. A method of forming a device , comprising:forming an insulating layer on a top surface of a semiconductor substrate, a target region disposed at the top surface of the semiconductor substrate;etching an opening through the insulating layer, the opening exposing a top surface of a portion of the target region;forming a doped metal oxide interlayer in the opening and contacting the top surface of the target region; andfilling a remainder of the opening with a metal plug, the doped metal oxide interlayer disposed between the metal plug and the substrate.2. The method of claim 1 , wherein the etching the opening comprises generating an etching byproduct disposed on surfaces of the opening and comprising a first dopant claim 1 , and wherein the forming the doped metal oxide interlayer comprises forming a metal oxide interlayer over the etching byproduct claim 1 , and wherein the first dopant from the etching byproduct at least partially dopes the metal oxide interlayer.3. The method of claim 1 , wherein the forming the doped metal oxide interlayer comprises implanting a first dopant into a metal oxide interlayer.4. The method of claim 3 , wherein the forming the doped metal oxide interlayer comprises forming the metal oxide ...

Semiconductor device and fabrication method therefor

A method of manufacturing a semiconductor device includes forming a first insulating film over a first fin structure and a second insulating film over a second fin structure, coating a protective layer over the second insulating film, removing the first insulating film to expose a portion of the first fin structure, and forming a first oxide film over the exposed portion of the first fin structure using a non-aqueous solvent-based chemical.

SEMICONDUCTOR PROCESSING STATION

A semiconductor processing station including a platform, a load port, and a carrier transport track is provided. The platform includes an intake/outtake port and a plurality of processing modules. The load port includes a load chamber, a movable cover, and a carrier transfer module. The load chamber communicates with the intake/outtake port and has a load opening at its top end for receiving a transport carrier within the load chamber. The movable cover is disposed at the load opening and configured to seal the load opening. The carrier transfer module is configured to transfer the transport carrier to the intake/outtake port. The carrier transport track has a bottom side configured to open the load chamber. 1. A semiconductor processing station , comprising:a platform comprising an intake/outtake port and a plurality of processing modules; a load chamber communicating with the intake/outtake port and having a load opening at its top end for receiving a transport carrier within the load chamber;', 'a movable cover disposed at the load opening and configured to seal the load opening; and', 'a carrier transfer module configured to transfer the transport carrier to the intake/outtake port; and, 'a load port comprisinga carrier transport track having a bottom side configured to open the load chamber.2. The semiconductor processing station of claim 1 , wherein the load opening is sealed by the movable cover to form a vacuum environment containing the transport carrier.3. The semiconductor processing station of claim 1 , wherein the platform further comprises:a central transfer module communicating with the intake/outtake port and the plurality of processing modules; anda substrate transfer mechanism configured in the central transfer module to pick up and traversely transfer a plurality of substrates from the transport carrier to the plurality of processing modules in sequence.4. The semiconductor processing station of claim 3 , wherein the carrier transfer module ...

Method for Silicide Formation

Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region. 1. A method comprising:forming a contact region on a substrate;forming a dielectric layer over the contact region and the substrate;forming an opening through the dielectric layer to expose a portion of the contact region;forming a silicon-containing capping layer along the exposed portion of the contact region, sidewalls of the opening, and over the dielectric layer;forming a metal layer over the silicon-containing capping layer in the opening and over the dielectric layer;performing a silicidation process to react at least portions of the silicon-containing capping layer and the metal layer to form a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening, the silicidation process consuming at least a portion of the contact region; andfilling the opening over the metal-silicide layer with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.2. The method of further comprising:planarizing the conductive material to form the conductive plug, wherein after the planarizing step a top surface of the conductive plug is coplanar with a top surface of the dielectric layer.3. The method of claim 1 , where the substrate is a semiconductor fin for a fin ...

SUBSTRATE HANDLING CONTACTS AND METHODS

A substrate handling device includes a substrate reception area defined by an edge. The substrate reception area includes a planar surface and a plurality of contact structures. At least one contact structure of the plurality of contact structures is located at the edge and at least one contact structure of the plurality of contact structures is located on the planar surface. The substrate reception area and planar surface are made of a first material. Each contact structure of the plurality of contact structures includes a second material different from the first material, the second material having a hardness aligned to a hardness of a substrate material. 1. A substrate handling device comprising: a planar surface; and', 'a plurality of contact structures, at least one contact structure of the plurality of contact structures being located at the edge and at least one contact structure of the plurality of contact structures being located on the planar surface, wherein the at least one contact structure of the plurality of contact structures located at the edge extends from a sidewall of the edge,, 'a substrate reception area defined by an edge, the substrate reception area comprisingwhereinthe substrate reception area and the planar surface are made of a first material, andeach contact structure of the plurality of contact structures comprises a second material different from the first material, the second material having a hardness aligned to a hardness of a substrate material.2. The substrate handling device of claim 1 , wherein at least one contact structure of the plurality of contact structures comprises one or more of a ridge pattern claim 1 , a groove pattern claim 1 , or a pyramid pattern at a surface thereof.3. The substrate handling device of claim 1 , wherein the at least one contact structure of the plurality of contact structures located on the planar surface comprises a first contact structure near the edge and a second contact structure distal to the ...

METHOD OF USING A POLISHING SYSTEM

A method of using a polishing system includes securing a wafer to a support, wherein the wafer has a first diameter. The method further includes polishing the wafer using a first polishing pad rotating about a first axis, wherein the first polishing pad has a second diameter greater than the first diameter. The method further includes rotating the support about a second axis perpendicular to the first axis after polishing the wafer using the first polishing pad. The method further includes polishing the wafer using a second polishing pad after rotating the support, wherein the second polishing pad has a third diameter less than the first diameter. The method further includes releasing the wafer from the support following polishing the wafer using the second polishing pad. 1. A method of using a polishing system , the method comprising:securing a wafer to a support, wherein the wafer has a first diameter;polishing the wafer using a first polishing pad rotating about a first axis, wherein the first polishing pad has a second diameter greater than the first diameter;rotating the support about a second axis perpendicular to the first axis after polishing the wafer using the first polishing pad;polishing the wafer using a second polishing pad after rotating the support, wherein the second polishing pad has a third diameter less than the first diameter; andreleasing the wafer from the support following polishing the wafer using the second polishing pad.2. The method of claim 1 , wherein polishing the wafer using the second polishing pad comprises polishing the wafer using the second polishing pad having the third diameter shorter than or equal to about one quarter the second diameter.3. The method of claim 1 , wherein polishing the wafer using the second polishing pad comprises polishing the wafer using a plurality of second polishing pads.4. The method of claim 1 , wherein polishing the wafer using the first polishing pad comprises moving the first polishing pad in three ...

CONDUCTIVE POWDER FORMATION METHOD AND DEVICE FOR FORMING CONDUCTIVE POWDER

A method of forming a conductive powder includes reducing, by a reduction reaction, a conductive powder precursor gas using a plasma to form the conductive powder. The method further includes filtering the conductive powder based on particle size. The method further includes dispersing a portion of the conductive powder having a particle size below a threshold value in a fluid. 1. A method of forming a conductive powder , the method comprising:reducing, by a reduction reaction, a conductive powder precursor gas using a plasma to form the conductive powder;filtering the conductive powder based on particle size; anddispersing a portion of the conductive powder having a particle size below a threshold value in a fluid.2. The method of claim 1 , further comprising preheating the conductive powder precursor gas prior to the reducing of the conductive powder precursor gas.3. The method of claim 1 , further comprising performing an ultrasonic vibration on a reaction chamber simultaneously with the reducing of the conductive powder precursor gas in the reaction chamber.4. The method of claim 1 , wherein the filtering of the conductive powder comprises performing at least one of an electro-static collector (ESC) process or a centrifugal process.5. The method of claim 1 , wherein the dispersing of the conductive powder in the fluid comprises dispersing the conductive powder in a fluid free of oxygen.6. The method of claim 1 , wherein the dispersing of the conductive powder in the fluid comprises dispersing the conductive powder in a solvent including methane claim 1 , acetone or isopropyl alcohol.7. The method of claim 1 , wherein the reducing of the conductive powder precursor gas comprises reducing the conductive powder precursor gas comprising a conductive-material organic compound.8. The method of claim 1 , wherein the reducing of the conductive powder precursor gas comprises reducing the conductive powder precursor gas comprising a conductive-material halide compound.9. ...

Method of handling a substrate

A method of aligning a substrate contact material to a substrate material includes determining a hardness of a substrate material. The method further includes matching a hardness of a substrate contact material to the hardness of the substrate material. The method further includes adding the substrate contact material to a plurality of contact structures of a substrate handling device, wherein the substrate handling device comprises an edge and a planar surface, a first contact structure of the plurality of contact structures extends from the edge, and a second contact structure of the plurality of contact structures extends from the planar surface.

GAMMA RAY GENERATOR AND METHOD OF GENERATING GAMMA RAY

A gamma ray generator includes a rotational shaft, a plurality of holders and a plurality of gamma ray sources. The holders are connected to the rotational shaft. The gamma ray sources are disposed in the holders respectively, wherein the holders respectively have an upper portion and a lower portion connecting to the upper portion, and the gamma ray source is placed at an interface between the upper portion and the lower portion. 1. A gamma ray generator , comprising:a plurality of gamma ray sources, wherein the gamma ray sources are arranged to surround a rotational axis.2. The gamma ray generator of claim 1 , further comprising a main body comprising a plurality of holes claim 1 , wherein the gamma ray sources are respectively disposed in the holes.3. The gamma ray generator of claim 2 , wherein the holes are arranged in a matrix.4. The gamma ray generator of claim 2 , wherein a separation between the holes increases as the holes becomes closer to the rotational axis.5. The gamma ray generator of claim 2 , wherein the main body is a circular plate.6. The gamma ray generator of claim 1 , further comprising a plurality of holders claim 1 , wherein the gamma ray sources are respectively disposed in the holders.7. A gamma ray generator claim 1 , comprising:a rotational shaft;a plurality of holders connecting to the rotational shaft; anda plurality of gamma ray sources in the holders respectively, wherein the holders respectively have an upper portion and a lower portion connecting to the upper portion, and the gamma ray source is placed at an interface between the upper portion and the lower portion.8. The gamma ray generator of claim 7 , wherein the gamma ray source radiates a gamma ray through a bottom opening of the lower portion.9. The gamma ray generator of claim 7 , wherein a diameter of the lower portion decrease as the lower portion becomes away from the upper portion.10. The gamma ray generator of claim 7 , wherein a diameter of the upper portion is ...

Composite contact plug structure and method of making same

An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.

Method of handling a substrate

A method of aligning a substrate contact material to a substrate material includes determining a hardness of a substrate material. The method further includes matching a hardness of a substrate contact material to the hardness of the substrate material. The method further includes adding the substrate contact material to a plurality of contact structures of a substrate handling device, wherein the substrate handling device comprises an edge and a planar surface, a first contact structure of the plurality of contact structures extends from the edge, and a second contact structure of the plurality of contact structures extends from the planar surface.

Interconnect structure and method of forming the same

An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a contact layer over a substrate, a dielectric layer over the contact layer, a silicide layer over the exposed portion of the contact layer, a barrier layer along sidewalls of the opening, an alloy layer over the barrier layer, a glue layer over the alloy layer, and a conductive plug over the glue layer, wherein the dielectric layer has an opening, and the opening exposes a portion of the contact layer.

Semiconductor structures and methods of forming the same