CONDUCTIVE COMPOSITION AND ELECTRONIC PARTS USING THE SAME

A conductive composition, which can form bonded portions and is capable of maintaining a thickness of the bonded portions and bonding strength, and which includes: (A) silver fine particles having a number average particle diameter of primary particles of 40 nm to 400 nm, (B) a solvent, and (C) thermoplastic resin particles having a maximal value of an endothermic peak in a DSC chart, determined by a measurement using a differential scanning calorimeter, within a range of 80° C. to 170° C. 1. A conductive composition which comprises (A) silver fine particles having a number average particle diameter of primary particles of 40 nm to 400 nm , (B) a solvent and (C) thermoplastic resin particles having a maximal value of an endothermic peak in a DSC chart , obtained by a measurement using a differential scanning calorimeter , within a range of 80° C. to 170° C.2. The conductive composition according to claim 1 , wherein the silver fine particles (A) have (a) a number average particle diameter of primary particles of 40 nm to 350 nm claim 1 , (b) a crystallite diameter of 20 nm to 70 nm and (c) a ratio of a number average particle diameter of primary particles based on a crystallite diameter of 1.5 to 5.3. The conductive composition according to claim 1 , wherein the silver fine particles (A) are contained in a paste containing 40% to 95% by mass of the silver fine particles based on 100% by mass of the paste and a solvent claim 1 , and the silver fine particles (A) in the paste are sintered when the paste is maintained at a temperature of 180° C. to 250° C. for 20 minutes to 2 hours.4. The conductive composition according to claim 1 , wherein the composition further comprises (D) metal particles having a number average particle diameter of primary particles of 0.5 μm to 20 μm.5. The conductive composition according to claim 1 , wherein the maximal value of the endothermic peak of the thermoplastic resin particles (C) in a DSC chart claim 1 , obtained by a measurement ...

WAFER PROCESSING METHOD

A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of blowing air to each device chip through the polyolefin sheet to push up each device chip, thereby picking up each device chip from the polyolefin sheet after performing the dividing step.

For the adhesive film for semiconductor device

ENGINEERED POLYMER-BASED ELECTRONIC MATERIALS

WAFERBEARBEITUNGSVERFAHREN

Ein Waferbearbeitungsverfahren beinhaltet einen Polyolefinfolienbereitstellungsschritt des Positionierens eines Wafers in einer inneren Öffnung eines Ringrahmens und des Vorsehens einer Polyolefinfolie an einer Rückseite des Wafers und an einer Rückseite des Ringrahmens, einen Verbindungsschritt des Erwärmens der Polyolefinfolie während eines Aufbringens eines Drucks auf die Polyolefinfolie, um dadurch den Wafer und den Ringrahmen über die Polyolefinfolie durch ein Thermokompressionsverbinden zu verbinden, einen Teilungsschritt des Aufbringens eines Laserstrahls auf den Wafer, um Teilungsnuten im Wafer auszubilden, wodurch der Wafer in einzelne Bauelementchips geteilt wird, und einen Aufnahmeschritt des Erwärmens der Polyolefinfolie in jedem Bereich der Polyolefinfolie, der einem jeweiligen Bauelementchip entspricht, und des Hochdrückens jedes Bauelementchips von der Seite der Polyolefinfolie, um jeden Bauelementchip von der Polyolefinfolie aufzunehmen.

Conductive composition and electronic component using the same

WAFERBEARBEITUNGSVERFAHREN

Ein Waferbearbeitungsverfahren beinhaltet einen Polyolefinfolienbereitstellungsschritt des Positionierens eines Wafers in einer inneren Öffnung eines Ringrahmens und des Vorsehens einer Polyolefinfolie an einer Rückseite des Wafers und an einer Rückseite des Ringrahmens, einen Verbindungsschritt des Erwärmens der Polyolefinfolie während eines Aufbringens eines Drucks auf die Polyolefinfolie, um dadurch den Wafer und den Ringrahmen über die Polyolefinfolie durch ein Thermokompressionsverbinden zu verbinden, einen Teilungsschritt des Aufbringens eines Laserstrahls auf den Wafer, um Teilungsnuten im Wafer auszubilden, wodurch der Wafer in einzelne Bauelementchips geteilt wird, und einen Aufnahmeschritt des Aufnehmens jedes Bauelementchips von der Polyolefinfolie.

Engineered polymer-based electronic materials

一種用於電子組裝製程的組成，組成包含分散於有機介質的填料，其中：有機介質包含聚合物；填料包含一或更多的石墨烯、官能化石墨烯、氧化石墨烯、多面體寡聚半矽氧烷、石墨、二維材料、氧化鋁、氧化鋅、氮化鋁、氮化硼、銀、奈米纖維、碳纖維、鑽石、奈米碳管、二氧化矽和金屬塗覆粒子，及組成按組成總重量計包含0.001-40重量%的填料。

Base film and adhesive film for semiconductor devices using the same

본 발명은 0℃ ~ 5℃에서의 선팽창계수가 50 내지 150㎛/m·℃인 것을 특징으로 하는 기재필름 및 이를 포함하는 반도체용 접착필름에 관한 것으로 저온에서 장기간 경과시 와인딩 형태의 안정성이 우수하여 쏠림 현상이 발생하지 않으며, 후속 반도체 패키징 공정 등에 불량을 유발하지 않는 장점이 있다. The present invention relates to a substrate film and a semiconductor adhesive film comprising the same, wherein the coefficient of linear expansion at 0 ° C to 5 ° C is 50 to 150 μm / m ° C. And there is an advantage that no defects are caused in the subsequent semiconductor packaging process and the like.

Conductive composition and electronic component using same

WAFER PROCESSING METHOD

WAFERBEARBEITUNGSVERFAHREN

Ein Waferbearbeitungsverfahren beinhaltet einen Polyesterfolienbereitstellungsschritt des Positionierens eines Wafers in einer inneren Öffnung eines Ringrahmens und des Vorsehens einer Polyesterfolie an einer Rückseite des Wafers und an einer Rückseite des Ringrahmens, einen Verbindungsschritt des Erwärmens der Polyesterfolie während eines Aufbringens eines Drucks auf die Polyesterfolie, um dadurch den Wafer und den Ringrahmen über die Polyesterfolie durch ein Thermokompressionsverbinden zu verbinden, einen Teilungsschritt des Aufbringens eines Laserstrahls auf den Wafer, um Teilungsnuten im Wafer auszubilden, wodurch der Wafer in einzelne Bauelementchips geteilt wird, und einen Aufnahmeschritt des Blasens von Luft zu jedem Bauelementchip via die Polyesterfolie nach einem Durchführen des Teilungsschritts, um jeden Bauelementchip hochzudrücken, wodurch jeder Bauelementchip von der Polyesterfolie aufgenommen wird.

Conductive composition and electronic component using the same

本發明係提供可形成維持接合部的厚度、可維持接合強度的接合部之導電性組成物及使用該導電性組成物的電子組件。 本發明之導電性組成物係包含(A)一次粒子的個數平均粒徑為40nm~400nm的銀微粒子、(B)溶劑及(C)使用示差掃描熱量計所測定之DSC圖的吸熱峰的極大值在80℃~170℃的範圍之熱塑性樹脂粒子。(C)熱塑性樹脂粒子使用示差掃描熱量計所測定之DSC圖的吸熱峰的極大值在110℃~140℃的範圍較佳。

WAFERBEARBEITUNGSVERFAHREN

Ein Waferbearbeitungsverfahren beinhaltet einen Polyolefinfolienbereitstellungsschritt des Positionierens eines Wafers in einer inneren Öffnung eines Ringrahmens und des Vorsehens einer Polyolefinfolie an einer Rückseite des Wafers und an einer Rückseite des Ringrahmens, einen Verbindungsschritt des Erwärmens der Polyolefinfolie während eines Aufbringens eines Drucks auf die Polyolefinfolie, um dadurch den Wafer und den Ringrahmen über die Polyolefinfolie durch ein Thermokompressionsverbinden zu verbinden, einen Teilungsschritt des Aufbringens eines Laserstrahls auf den Wafer, um Teilungsnuten im Wafer auszubilden, wodurch der Wafer in einzelne Bauelementchips geteilt wird, und einen Aufnahmeschritt des Blasens von Luft zu jedem Bauelementchip durch die Polyolefinfolie nach einem Durchführen des Teilungsschritts, um jeden Bauelementchip hochzudrücken, wodurch jeder Bauelementchip von der Polyolefinfolie aufgenommen wird.

TERMINAL AND CONNECTION METHOD

An object of the present technology is to prevent damage in a bonded portion between a semiconductor chip and a substrate in a semiconductor device in which the semiconductor chip is mounted on the substrate. A terminal is disposed between an electrode of an element and an electrode of a substrate on which the element is mounted, and electrically connects the electrode of the element and the electrode of the substrate. The terminal includes a plurality of unit lattices and a coupling portion. The unit lattices included in the terminal are formed by bonding a plurality of beams in a cube shape. The coupling portion included in the terminal couples adjacent unit lattices among the plurality of unit lattices.

Wafer processing method

A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of blowing air to each device chip through the polyolefin sheet to push up each device chip, thereby picking up each device chip from the polyolefin sheet after performing the dividing step.

Underfill material including block copolymer to tune coefficient of thermal expansion and tensile modulus

Embodiments of the present disclosure are directed toward underfill material including block copolymer. In one embodiment, an underfill material includes epoxy material and a copolymer including an epoxy-philic block and an epoxy-phobic block, wherein the epoxy-philic block is miscible in the epoxy material, the epoxy-phobic block is covalently bonded with the epoxy-philic block, the epoxy-phobic block is separated in a microphase domain within the epoxy material and the epoxy-philic block is configured to restrict thermal expansion or contraction of the epoxy material.

CONDUCTIVE SOLUTION COMPOSITION AND CONDUCTIVE STRUCTURE USING SAME

Disclosed are a conductive solution composition having excellent adhesion to a crystalline polymer substrate and excellent surface hardness at the time of coating, and a conductive structure using the same. The conductive solution composition comprises: a first binder comprising a first polyolefin resin comprising maleic anhydride; a second binder comprising a second polyolefin resin having the glass transition temperature of 20°C or lower; a conductive filler; and a dispersion medium. COPYRIGHT KIPO 2018 ...

WAFERBEARBEITUNGSVERFAHREN

Ein Waferbearbeitungsverfahren beinhaltet einen Polyesterfolienbereitstellungsschritt des Positionierens eines Wafers in einer inneren Öffnung eines Ringrahmens und des Vorsehens einer Polyesterfolie an einer Rückseite des Wafers und an einer Rückseite des Ringrahmens, einen Verbindungsschritt des Erwärmens der Polyesterfolie während eines Aufbringens eines Drucks auf die Polyesterfolie, um dadurch den Wafer und den Ringrahmen über die Polyesterfolie durch ein Thermokompressionsverbinden zu verbinden, einen Teilungsschritt des Aufbringens eines Laserstrahls auf den Wafer, um Teilungsnuten im Wafer auszubilden, wodurch der Wafer in einzelne Bauelementchips geteilt wird, und einen Aufnahmeschritt des Erwärmens der Polyesterfolie in jedem Bereich der Polyesterfolie, der einem jeweiligen Bauelementchip entspricht, und des Hochdrückens jedes Bauelementchips von der Seite der Polyesterfolie, um jeden Bauelementchip von der Polyesterfolie aufzunehmen.

Adhesive film for semiconductor device

Wafer processing method using a ring frame and a polyester sheet

A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of blowing air to each device chip through the polyester sheet to push up each device chip, thereby picking up each device chip from the polyester sheet after performing the dividing step.

MODULE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC DEVICE

A module, comprising an electronic component having a first electrode, a mounting board having a second electrode, a solder-bump configured to connect the first electrode and the second electrode, and a thermoplastic resin member configured to contact both the first electrode and the second electrode and cover the solder-bump, so as to form a space between the electronic component and the mounting board.

도전성 조성물 및 그것을 사용한 전자 부품

... 본 발명은 접합부의 두께를 유지하며 접합 강도를 유지할 수 있는 접합부를 형성할 수 있는 도전성 조성물, 및 그것을 사용한 전자 부품을 제공한다. 본 발명은, (A) 1차 입자의 개수 평균 입자 직경이 40㎚ 내지 400㎚인 은 미립자와, (B) 용제와, (C) 시차 주사 열량계를 사용한 측정으로 얻어지는 DSC 차트에 있어서의 흡열 피크의 극댓값이 80℃ 내지 170℃의 범위에 있는 열가소성 수지 입자를 포함하는, 도전성 조성물이다. (C) 열가소성 수지 입자의 시차 주사 열량계를 사용한 측정으로 얻어지는 DSC 차트에 있어서의 흡열 피크의 극댓값이 110℃ 내지 140℃의 범위인 것이 바람직하다.

WAFER PROCESSING METHOD

A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of heating the polyester sheet in each region of the polyester sheet corresponding to each device chip, pushing up each device chip from the polyester sheet side to pick up each device chip from the polyester sheet.

Wafer processing method

A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of picking up each device chip from the polyolefin sheet.

PROCESSING METHOD FOR WAFER

A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of heating the polyolefin sheet in each region of the polyolefin sheet corresponding to each device chip, pushing up each device chip from the polyolefin sheet side to pick up each device chip from the polyolefin sheet.

UNDERFILL MATERIAL INCLUDING BLOCK COPOLYMER TO TUNE COEFFICIENT OF THERMAL EXPANSION AND TENSILE MODULUS

Embodiments of the present disclosure are directed toward underfill material including block copolymer. In one embodiment, an underfill material includes epoxy material and a copolymer including an epoxy-philic block and an epoxy-phobic block, wherein the epoxy-philic block is miscible in the epoxy material, the epoxy-phobic block is covalently bonded with the epoxy-philic block, the epoxy-phobic block is separated in a microphase domain within the epoxy material and the epoxy-philic block is configured to restrict thermal expansion or contraction of the epoxy material. 17-. (canceled)8. An integrated circuit (IC) assembly comprising:a package substrate;a die coupled with the package substrate; and epoxy material, and', 'a copolymer including an epoxy-philic block and an epoxy-phobic block, wherein the epoxy-philic block is miscible in the epoxy material, the epoxy-phobic block is covalently bonded with the epoxy-philic block, the epoxy-phobic block is separated in a microphase domain within the epoxy material and the epoxy-philic block is configured to restrict thermal expansion or contraction of the epoxy material., 'an underfill material disposed between the die and the package substrate, the underfill material including9. The IC assembly of claim 8 , wherein the package substrate is an epoxy-based laminate package substrate.10. The IC assembly of claim 8 , wherein:the die is coupled with the substrate using one or more die-level interconnect structures; andthe underfill material is in direct contact with the one or more die-level interconnect structures.11. The IC assembly of claim 8 , wherein the underfill material encapsulates the die.12. The IC assembly of claim 8 , wherein the epoxy-phobic block includes a material selected from the group consisting of poly(ethylene-alt-propylene) (PEP) claim 8 , poly(nbutyl-acrylate) (PnBA) claim 8 , poly(styrene) (PS) claim 8 , polybutadiene (PBD) claim 8 , polypropylene oxide (PPO) claim 8 , polyethylene (PE) claim 8 , ...

Engineered polymer-based electronic materials

Wafer processing method

The present invention is to form a device chip without deteriorating the quality. According to the present invention, a wafer processing method for allowing a plurality of devices to divide a wafer formed on each region of a surface divided by a division-scheduled line into individual device chips, comprises: a polyolefin-based sheet arrangement process of placing a wafer in an opening of a frame having the opening for accommodating the wafer, and arranging a polyolefin-based sheet on a back surface of the wafer and the outer periphery of the frame; an integration process of heating the polyolefin-based sheet and integrating the wafer and the frame through the polyolefin-based sheet by thermal compression; a dividing process of irradiating a laser beam of a wavelength having the absorbency with respect to the wafer along the division-scheduled line, and forming a division groove to divide the wafer into individual device chips; and a pickup process of heating the polyolefin-based sheet ...

ADHESIVE FILM FOR SEMICONDUCTOR DEVICE

An adhesive film for semiconductor devices, the adhesive film including a base film having a coefficient of linear expansion of about 50 to about 150 μm/m•° C. at 0 to 5° C. 1. An adhesive film for semiconductor devices , the adhesive film comprising a base film having a coefficient of linear expansion of about 50 to about 150 μm/m•° C. at 0 to 5° C. ,further comprising a pressure sensitive adhesive layer on one side of the base film,further comprising a bonding layer and a protective film sequentially stacked on one side of the pressure sensitive adhesive layer,wherein the base film has a thermal contraction ratio of greater than 0 to about 0.1% after 120 hours at 5° C.2. The adhesive film as claimed in claim 1 , wherein the base film includes at least one of a polyolefin claim 1 , polyvinyl chloride claim 1 , polyethylene terephthalate claim 1 , polycarbonate claim 1 , poly(methyl methacrylate) claim 1 , polyimide claim 1 , polyethylene naphthalate claim 1 , polyester sulfone claim 1 , polystyrene claim 1 , polyacrylate claim 1 , and a thermoplastic elastomer.3. The adhesive film as claimed in claim 1 , wherein the pressure sensitive adhesive layer includes:a pressure sensitive adhesive binder,a heat curing agent, anda photoinitiator.4. The adhesive film as claimed in claim 3 , wherein the pressure sensitive adhesive binder has a weight average molecular weight of about 100 claim 3 ,000 to about 1 claim 3 ,000 claim 3 ,000.5. The adhesive film as claimed in claim 1 , wherein the adhesive film having a four-layer structure of a base film claim 1 , a pressure sensitive adhesive layer claim 1 , a bonding layer claim 1 , and a protective film claim 1 , the adhesive films has a thermal contraction ratio of greater than 0 to about 0.2% after 120 hours at 5° C.6. The adhesive film as claimed in claim 1 , wherein the bonding layer includes an acrylic resin and an epoxy resin.7. The adhesive film as claimed in claim 6 , wherein:the acrylic resin has a glass transition ...

WAFER PROCESSING METHOD

WAFER PROCESSING METHOD

SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES AND METHODS OF MANUFACTURING THE SAME

Semiconductor devices are provided. The semiconductor device includes a semiconductor layer having a first surface and a second surface that are opposite each other, a through electrode penetrating the semiconductor layer and having a protrusion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed over the first surface of the semiconductor layer and electrically coupled to the through electrode, a polymer pattern disposed over the second surface of the semiconductor layer to enclose a part of the protrusion of the through electrode, and a back-side bump covering an upper surface and a sidewall of a remaining part of the protrusion of the through electrode and extending over a portion of the polymer pattern. 1. A semiconductor device comprising:a semiconductor layer having a first surface and a second surface that are opposite to each other;a through electrode penetrating the semiconductor layer and having a protrusion that protrudes over the second surface of the semiconductor layer;a front-side bump disposed over the first surface of the semiconductor layer and electrically coupled to the through electrode;a polymer pattern disposed over the second surface of the semiconductor layer to enclose a part of the protrusion of the through electrode; anda back-side bump covering an upper surface and a sidewall of a remaining part of the protrusion of the through electrode and extending over a portion of the polymer pattern.2. The semiconductor device of claim 1 ,wherein the first surface of the semiconductor layer corresponds to a front-side surface adjacent to an active region disposed in the semiconductor layer; andwherein the second surface of the semiconductor layer corresponds to a back-side surface that is opposite to the front-side surface.3. The semiconductor device of claim 1 , wherein the through electrode includes a first end surface disposed at the same side of the semiconductor layer as the first surface of the ...

Wafer processing method

The purpose of the present invention is to form a device chip without a deterioration in quality. A wafer treatment method, wherein a plurality of devices divide a wafer formed in each area of a surface by divided by a division-expected line into individual device chips, includes: a polyolefin-based sheet placement process of locating a wafer in an opening of a frame having the opening to store the wafer, and placing a polyolefin-based sheet on the outer circumference of the frame and the rear side of the wafer; an integration process of integrating the frame and the wafer through the polyolefin-based sheet with thermal compression by heating the polyolefin-based sheet; a division process of radiating a laser beam of a wavelength having absorbability for the wafer along the division-expected line, and forming a division groove to divide the wafer into individual device chips; and a pickup process of picking up the individual device chips from the polyolefin-based sheet.

Engineered polymer-based electronic materials

A composition for use in an electronic assembly process, the composition comprising a filler dispersed in an organic medium, wherein: the organic medium comprises a polymer; the filler comprises one or more of graphene, functionalized graphene, graphene oxide, a polyhedral oligomeric silsesquioxane, graphite, a 2D material, aluminum oxide, zinc oxide, aluminum nitride, boron nitride, silver, nano fibers, carbon fibers, diamond, carbon nanotubes, silicon dioxide and metal-coated particles, and the composition comprises from 0.001 to 40 wt. % of the filler based on the total weight of the composition.

WAFER PROCESSING METHOD

Wafer processing method

A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of heating the polyester sheet in each region of the polyester sheet corresponding to each device chip, pushing up each device chip from the polyester sheet side to pick up each device chip from the polyester sheet.

Adhesive film for semiconductor device

The present disclosure provides an adhesive film for semiconductor devices, which includes a base film having a coefficient of linear expansion of 50 to 150 m/m. DEG C at 0 to 5 DEG C. The adhesive film has excellent winding shape stability after storage at low temperature for long time, thereby not causing a tilting phenomenon and reducing defects in a following semiconductor packaging process.

For the adhesive film for semiconductor device

Wafer processing method using a ring frame and a polyolefin sheet

A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of heating the polyolefin sheet in each region of the polyolefin sheet corresponding to each device chip, pushing up each device chip from the polyolefin sheet side to pick up each device chip from the polyolefin sheet.

WAFER PROCESSING METHOD

Wafer processing method including applying a polyolefin sheet to a wafer

A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of blowing air to each device chip through the polyolefin sheet to push up each device chip, thereby picking up each device chip from the polyolefin sheet after performing the dividing step.

Engineered Polymer-Based Electronic Materials

A composition for use in an electronic assembly process, the composition comprising a filler dispersed in an organic medium, wherein: the organic medium comprises a polymer; the filler comprises one or more of graphene, functionalized graphene, graphene oxide, a polyhedral oligomeric silsesquioxane, graphite, a 2D material, aluminum oxide, zinc oxide, aluminum nitride, boron nitride, silver, nano fibers, carbon fibers, diamond, carbon nanotubes, silicon dioxide and metal-coated particles, and the composition comprises from 0.001 to 40 wt. % of the filler based on the total weight of the composition.

Wafer processing method

The purpose of the present invention is to form a device chip without causing a degradation in quality. Disclosed is a wafer processing method for allowing a plurality of devices to divide, into individual device chips, a wafer formed in each of separate regions of a surface partitioned by division-expected lines. The wafer processing method comprises: a polyester-based sheet arrangement step of placing a wafer in an opening of a frame having the opening for receiving the wafer, and arranging a polyester-based sheet on a back surface of the wafer and an outer periphery of the frame; an integration step of heating the polyester-based sheet to integrate the wafer and the frame through the polyester-based sheet by thermocompression bonding; a dividing step of applying a laser beam of wavelengths with absorbency to the wafer along the division-expected lines, and forming dividing grooves to divide the wafer into individual device chips; and a pickup step of spraying air to push up the device ...

Conductive composition and electronic parts using the same

A conductive composition, which can form bonded portions and is capable of maintaining a thickness of the bonded portions and bonding strength, and which includes: (A) silver fine particles having a number average particle diameter of primary particles of 40 nm to 400 nm, (B) a solvent, and (C) thermoplastic resin particles having a maximal value of an endothermic peak in a DSC chart, determined by a measurement using a differential scanning calorimeter, within a range of 80° C. to 170° C.

WAFER PROCESSING METHOD

A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of blowing air to each device chip through the polyester sheet to push up each device chip, thereby picking up each device chip from the polyester sheet after performing the dividing step.

Module, method for manufacturing the same, and electronic device

A module, comprising an electronic component having a first electrode, a mounting board having a second electrode, a solder-bump configured to connect the first electrode and the second electrode, and a thermoplastic resin member configured to contact both the first electrode and the second electrode and cover the solder-bump, so as to form a space between the electronic component and the mounting board.

Wafer processing method using a ring frame with a polyester sheet with no adhesive layer

A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of heating the polyester sheet in each region of the polyester sheet corresponding to each device chip, pushing up each device chip from the polyester sheet side to pick up each device chip from the polyester sheet.

WAFER PROCESSING METHOD

A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of picking up each device chip from the polyolefin sheet.

ADHESIVE FILM FOR SEMICONDUCTOR DEVICE

An adhesive film for semiconductor devices, the adhesive film including a base film having a coefficient of linear expansion of about 50 to about 150 m/m·° C. at 0 to 5° C.

COMPOSITION FOR ANISOTROPIC CONDUCTIVE FILM, ANISOTROPIC CONDUCTIVE FILM, AND CONNECTION STRUCTURE USING THE SAME

An anisotropic conductive film composition, an anisotropic conductive film prepared using the same, and a connection structure using the same, the anisotropic conductive film including a binder resin; a curable alicyclic epoxy compound; a curable oxetane compound; a quaternary ammonium catalyst; and conductive particles, wherein the anisotropic conductive film has a heat quantity variation rate of about 15% or less, as measured by differential scanning calorimetry (DSC) and calculated by Equation 1: 1. An anisotropic conductive film , comprising:a binder resin;a curable alicyclic epoxy compound;a curable oxetane compound;a quaternary ammonium catalyst; andconductive particles, {'br': None, 'i': H', '−H', 'H, 'sub': 0', '1', '0, 'Heat quantity variation rate (%)=[()/]×100\u2003\u2003Equation 1'}, 'wherein the anisotropic conductive film has a heat quantity variation rate of about 15% or less, as measured by differential scanning calorimetry (DSC) and calculated by Equation 1{'sub': 0', '1, 'wherein His a DSC heat quantity of the anisotropic conductive film, as measured at 25° C. and a time point of 0 hr, and His a DSC heat quantity of the anisotropic conductive film, as measured after being left at 40° C. for 24 hours.'}3. The anisotropic conductive film as claimed in claim 1 , wherein the oxetane compound is a carbon polymer compound containing 1 to 4 oxetane rings per molecule.5. The anisotropic conductive film as claimed in claim 4 , wherein M is SbF or B(CF).6. The anisotropic conductive film as claimed in claim 1 , wherein the binder resin includes a polyimide resin claim 1 , a polyamide resin claim 1 , a phenoxy resin claim 1 , a polymethacrylate resin claim 1 , a polyacrylate resin claim 1 , a polyurethane resin claim 1 , a polyester resin claim 1 , a polyester urethane resin claim 1 , a polyvinyl butyral resin claim 1 , a styrene-butadiene-styrene (SBS) resin or an epoxylated compound thereof claim 1 , a styrene-ethylene/butylene-styrene (SEBS) resin or a ...

Molded composite enclosure for integrated circuit assembly

Embodiments of the present disclosure are directed toward a molded composite enclosure for an integrated circuit (IC) assembly. In one embodiment, an enclosure for an integrated circuit (IC) assembly may include a molded lid structure having a body portion, and a side portion that extends from the body portion and forms a cavity configured to house the IC assembly, wherein the body portion and the side portion share a contiguous interior material comprising a polymer and share a contiguous exterior material comprising a metal, the contiguous interior material having an opening formed in the body portion such that the IC assembly can be thermally coupled with the contiguous exterior material through the opening. Other embodiments may be described and/or claimed.

NANOSCALE INTERCONNECT ARRAY FOR STACKED DIES

A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together. 1. A method of fabricating a microelectronic assembly , comprising:forming an insulating layer comprising a diblock copolymer on a substrate, the insulating layer including a self-assembled nanoscale matrix array of a first polymer and a second polymer;removing the second polymer from the nanoscale matrix array to reveal a plurality of nanoscale holes in the nanoscale matrix array;filling the plurality of nanoscale holes with one or more conductive materials to form a plurality of nanoscale conductors within the insulating layer, the nanoscale conductors extending from a first surface of the insulating layer to a second surface of the insulating layer opposite the first surface;joining the array of nanoscale conductors within the insulating layer to a plurality of first element contacts at a first face of a first microelectronic element, the plurality of first element contacts facing the first surface of the insulating layer;removing the substrate from the second surface of the insulating layer;joining the array of nanoscale conductors within the insulating layer to a plurality of second element contacts at a second face of a second microelectronic element, the plurality of second element contacts facing the second surface of the insulating layer;forming electrical interconnections between the first element contacts of the first microelectronic element and the second element contacts of the second microelectronic element with the plurality of nanoscale conductors.2. The method of claim 1 , further comprising exposing the diblock copolymer to ultra-violet radiation claim 1 , ...

MOLDED COMPOSITE ENCLOSURE FOR INTEGRATED CIRCUIT ASSEMBLY

Embodiments of the present disclosure are directed toward a molded composite enclosure for an integrated circuit (IC) assembly. In one embodiment, an enclosure for an integrated circuit (IC) assembly may include a molded lid structure having a body portion, and a side portion that extends from the body portion and forms a cavity configured to house the IC assembly, wherein the body portion and the side portion share a contiguous interior material comprising a polymer and share a contiguous exterior material comprising a metal, the contiguous interior material having an opening formed in the body portion such that the IC assembly can be thermally coupled with the contiguous exterior material through the opening. Other embodiments may be described and/or claimed. 1. An enclosure for an integrated circuit (IC) assembly , the enclosure comprising: a body portion, and', 'a side portion that extends from the body portion and forms a cavity configured to house the IC assembly, wherein the body portion and the side portion share a contiguous interior material comprising a polymer and share a contiguous exterior material comprising a metal, the contiguous interior material having an opening formed in the body portion such that the IC assembly can be thermally coupled with the contiguous exterior material through the opening., 'a molded lid structure having'}2. The enclosure of claim 1 , wherein the IC assembly includes heat-generating elements of a solid-state drive (SSD).3. The enclosure of claim 1 , wherein the opening is one of multiple openings formed in the body portion such that the IC assembly can be thermally coupled with the contiguous exterior material through the multiple openings.4. The enclosure of claim 1 , wherein the polymer is selected from a group consisting of ABS (Acrylonitrile Butadiene Styrene) claim 1 , ABS+PC (ABS+Polycarbonate) claim 1 , Acetal (POM) claim 1 , Acrylic (PMMA) claim 1 , LCP (Liquid Crystal Polymer) claim 1 , PA-Nylon 6 (Polyamide) ...

Nanoscale Interconnect Array for Stacked Dies

A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together. 1. A microelectronic assembly , comprising:an insulating layer having a first surface and a second surface opposite the first surface;a plurality of nanoscale conductors disposed in an array within the insulating layer, the plurality of nanoscale conductors extending from the first surface to the second surface of the insulating layer, the array having a nanoscale pitch;a first microelectronic element having a first face and a plurality of first element contacts at the first face, the first element contacts facing and joined to the plurality of nanoscale conductors at the first surface of the insulating layer; anda second microelectronic element having a second face and a plurality of second element contacts at the second face, the second element contacts facing and joined to the plurality of nanoscale conductors at the second surface of the insulating layer, the plurality of nanoscale conductors forming electrical interconnections between first element contacts of the first microelectronic element and second element contacts of the second microelectronic element.2. The microelectronic assembly of claim 1 , wherein the insulating layer comprises an adhesive mechanically coupling the first microelectronic element to the second microelectronic element while the plurality of nanoscale conductors electrically couples element contacts of the first microelectronic element to element contacts of the second microelectronic element.3. The microelectronic assembly of claim 1 , wherein the insulating layer is a first insulating layer claim 1 , the microelectronic assembly further ...

Composition for use of anisotropic conductive film, anisotropic conductive film, and connection structure using the same

이방 도전성 필름용 조성물, 이방 도전성 필름 및 그것을 사용한 접속 구조체가 제공된다. 일 예에서, 이방 도전성 필름은, 바인더 수지, 지환족 에폭시 화합물 및 옥세탄 화합물을 포함하는 경화성 화합물, 4급 암모늄 화합물 촉매 및 도전 입자를 포함하고, 하기 식 1의 열시차주사열량계(DSC) 상 발열량 변화율이 15% 이하이다. [식 1] 발열량 변화율(%) = [(H 0 -H 1 )/H 0 ]×100 상기 식 1에서, H 0 는 이방 도전성 필름에 대해 40℃에서 24시간 보관하기 전에 25℃에서 측정한 열시차주사열량계(DSC) 상 발열량을 나타내고, H 1 은 상기 이방 도전성 필름을 40℃에서 24시간 보관 후 측정한 열시차주사열량계 상 발열량을 나타낸다. 지환족 에폭시 화합물 및 옥세탄 화합물을 경화성 화합물로 함께 사용하고, 나아가, 4급 암모늄 화합물 촉매를 사용하고 발열량 변화율을 위 범위 내로 함으로써 저온 속경화가 가능하며 보관 안정성 및 신뢰성이 우수한 이방 도전성 필름이 제공된다. A composition for anisotropic conductive film, an anisotropic conductive film and a connection structure using the same. In one example, the anisotropic conductive film comprises a curable compound containing a binder resin, an alicyclic epoxy compound, and an oxetane compound, a quaternary ammonium compound catalyst, and conductive particles, and has a thermal differential scanning calorimeter (DSC) The rate of change in calorific value is 15% or less. [Formula 1] Heating rate change rate (%) = [(H 0 -H 1 ) / H 0 ] × 100 In the above formula (1), H 0 represents the calorific value on the DSC of the anisotropic conductive film measured at 25 ° C before being stored at 40 ° C for 24 hours, H 1 represents the caloric value of the anisotropic conductive film at 24 ° C It shows the calorific value on the thermal differential scanning calorimetry measured after storage. An anisotropic conductive film excellent in storage stability and reliability can be obtained by using a cycloaliphatic epoxy compound and an oxetane compound together as a curing compound and further using a quaternary ammonium compound catalyst and setting a rate of change in calorific value within the upper range, do.

Wafer processing method

Dicing die bonding film having excellent burr property and reliability and semiconductor device using the same

本发明涉及一种用于半导体封装工艺的切割模片粘合膜和应用该切割模片粘合膜的半导体器件。设置该切割模片粘合膜，从而使晶片和模片粘合部分的粘合层之间的粘合力X与模片粘合部分和切割部分的粘性层之间的粘性力Y的比值X/Y为0.15-1，并且模片粘合部分的粘合层在常温下的储能模量为100-1000MPa。根据本发明的切割模片粘合膜在切割工艺中能减少毛刺的产生，由此制备的半导体器件具有优异的可靠性并且没有由于覆盖结合区的毛刺而因差的连接可靠性所导致的劣化。

Nanoscale interconnect array for stacked dies

A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together.

Nanoscale interconnect array for stacked dies

A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together.

Adhesive Film For Semiconductor Device

本发明提供了一种用于半导体装置的粘合剂膜，所述粘合剂膜包括在0℃至5℃下具有50μm/m·℃至150μm/m·℃的线性膨胀系数的基膜。所述粘合剂膜在低温储存较长时间后具有优异的卷绕形状稳定性，从而在以后的半导体封装工艺中不会导致倾斜现象并降低缺陷。

Conductive composition and electronic component using the same

Nanoscale interconnect array for stacked dies

A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together.

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전도성 용액 조성물 및 이를 이용한 전도성 구조체

결정성 폴리머 기판과의 접착성 및 코팅시 표면의 경도가 우수한 전도성 용액 조성물 및 이를 이용한 전도성 구조체가 개시된다. 상기 전도성 용액 조성물은 무수말레인산을 포함하는 제1 폴리올레핀 수지를 포함하는 제1 바인더; 유리전이온도가 20 ℃ 이하인 제2 폴리올레핀 수지를 포함하는 제2 바인더; 전도성 필러; 및 분산매;를 포함한다.

含有填料之膜

本發明之各向異性導電膜等含有填料之膜10A具備樹脂層2及填料分散層3，上述填料分散層3具有：第1填料層，其由以單層分散於樹脂層2之填料1A所構成；及第2填料層，其由在與第1填料層不同之深度以單層分散於樹脂層2之填料1B所構成。第1填料層之填料1A自樹脂層2之一表面2a露出、或接近於該表面2a，第2填料層之填料1B自樹脂層2之另一表面2b露出、或接近於該表面2b。

Engineered polymer-based electronic materials

自致密纳米银浆及制备用于高功率电子器件的互连层的方法

在选自GaN或SiC体系的高温半导体装置与基板之间形成自致密互连层。互连层包括具有微米级银颗粒的基质，其含量约为10至60重量百分比，且该微米级银颗粒具有约0.1至15微米的粒径；键合颗粒以化学键合的方式连接基质中的微米银颗粒，且该键合颗粒包括核心银纳米颗粒，以及以原位形成并且以化学结合的方式结合到核心银纳米颗粒的表面银纳米颗粒，同时该表面银纳米颗粒也以化学结合的方式与具有微米级银颗粒的基质结合。该键合颗粒具有约10至100纳米的核心粒径，而原位形成的表面银纳米颗粒具有约3至9纳米的粒径。

Method of joining microelectronic elements of a microelectronic assembly using nanoscale conductors fabricated in an insulating nanoscale matrix obtained from a diblock copolymer

晶片的加工方法

提供晶片的加工方法，不降低品质而形成器件芯片。该晶片的加工方法将在由分割预定线划分的正面的各区域内形成有多个器件的晶片分割成各个器件芯片，其中，该晶片的加工方法具有如下的工序：聚烯烃系片配设工序，将晶片定位于具有对晶片进行收纳的开口的框架的该开口内，将聚烯烃系片配设在晶片的背面和框架的外周上；一体化工序，对该聚烯烃系片进行加热，通过热压接使晶片与该框架借助该聚烯烃系片而一体化；分割工序，沿着该分割预定线照射对于该晶片具有吸收性的波长的激光束，形成分割槽而将该晶片分割成各个器件芯片；以及拾取工序，对该聚烯烃系片进行加热，将器件芯片顶起，拾取该器件芯片。

晶片的加工方法

提供晶片的加工方法，不降低品质而形成器件芯片。该晶片的加工方法将在由分割预定线划分的正面的各区域内形成有多个器件的晶片分割成各个器件芯片，其中，该晶片的加工方法具有如下的工序：聚酯系片配设工序，将晶片定位于具有对晶片进行收纳的开口的框架的该开口内，将聚酯系片配设在晶片的背面和框架的外周上；一体化工序，对该聚酯系片进行加热，通过热压接使晶片与该框架借助该聚酯系片而一体化；分割工序，沿着该分割预定线照射对于该晶片具有吸收性的波长的激光束，形成分割槽而将该晶片分割成各个器件芯片；以及拾取工序，对该聚酯系片进行加热，并将器件芯片顶起，从该聚酯系片拾取该器件芯片。

晶圓的加工方法

[課題]在不使品質降低的情形下形成元件晶片。 [解決手段]一種晶圓的加工方法，讓已將複數個元件形成在藉由分割預定線所區劃出的正面的各區域中之晶圓分割成一個個的元件晶片，前述晶圓的加工方法具備以下步驟：聚酯系片材配設步驟，將晶圓定位在具有容置晶圓之開口的框架的該開口內，並將聚酯系片材配設在晶圓的背面與框架的外周；一體化步驟，將該聚酯系片材加熱並藉由熱壓接來將晶圓及該框架透過該聚酯系片材一體化；分割步驟，沿著該分割預定線照射對該晶圓具有吸收性之波長的雷射光束，而形成分割溝來將該晶圓分割成一個個的元件晶片；及拾取步驟，藉由噴附空氣來將元件晶片頂推，並從該聚酯系片材拾取一個個的該元件晶片。

이방성 도전 필름 및 이를 포함하는 표시 장치

이방성 도전 필름 및 이를 포함하는 표시 장치에 제공된다. 표시 장치는 제1 패드 전극 및 제2 패드 전극을 포함하는 표시 패널, 제1 패드 전극과 제2 패드 전극 각각에 대향하는 제1 리드 전극 및 제2 리드 전극을 포함하는 인쇄 회로 기판, 표시 패널과 인쇄 회로 기판 사이에 배치되며, 베이스 수지, 폴리머 물질로 이루어진 코어와 코어를 둘러싸는 적어도 하나의 금속층을 포함하고, 상기 베이스 수지 내에 분산되어 배치된 제1 도전볼 및 용융 가능한 물질로 이루어지고, 상기 베이스 수지 내에 분산되어 배치된 제2 도전볼을 포함하는 이방성 도전 필름, 이방성 도전 필름이 제1 패드 전극 및 제1 리드 전극과 두께 방향에서 중첩하는 제1 영역 및 제1 리드 전극과 제2 리드 전극의 사이 영역인 제2 영역을 포함하며, 제1 도전볼의 금속층 및 제2 도전볼의 표면은 제1 패드 전극 및 제1 리드 전극과 접촉한다.

Resin particles, electrically conductive particles, electrically conductive material, and connection structure

Method of joining microelectronic elements of a microelectronic assembly using nanoscale conductors fabricated in an insulating nanoscale matrix obtained from a diblock copolymer

A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together.

집적 회로 조립체용 성형 복합 인클로저

본 발명의 실시예는 집적 회로(IC) 조립체용 성형 복합 인클로저에 관한 것이다. 일 실시예에서, 집적 회로(IC) 조립체용 인클로저는 보디 부분, 및 상기 보디 부분으로부터 연장되고 IC 조립체를 수용하도록 구성된 공동을 형성하는 사이드 부분을 갖는 성형 덮개 구조물을 구비할 수 있으며, 상기 보디 부분과 사이드 부분은 폴리머를 포함하는 인접 내측 재료를 공유하고 금속을 포함하는 인접 외측 재료를 공유하며, 인접 내측 재료는 IC 조립체가 개구를 통해서 인접 외측 재료와 열적으로 결합될 수 있도록 보디 부분에 형성되는 개구를 갖는다. 다른 실시예가 기재 및/또는 청구될 수 있다.

Anisotropic conductive film and display device including same

The disclosure relates to a display device and an anisotropic conductive film. An anisotropic conductive film disposed between a display panel and a printed circuit board, the anisotropic conductive film including a base resin, a plurality of first conductive balls dispersed in the base resin, each of the plurality of first conductive balls including a core made of a polymer material and at least one metal layer surrounding the core, and a plurality of second conductive balls dispersed in the base resin, each of the plurality of second conductive balls being made of a meltable material, and the anisotropic conductive film having a first area in which the anisotropic conductive film overlaps the first pad electrode and the first lead electrode in a thickness direction of the display device, and a second area as an area disposed between the first lead electrode and the second lead electrode. Each of the metal layer of the first conductive ball and a surface of the second conductive ball are in contact with both the first pad electrode and the first lead electrode.

Method of joining microelectronic elements of a microelectronic assembly using nanoscale conductors fabricated in an insulating nanoscale matrix obtained from a diblock copolymer

A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together.

樹脂粒子、導電性粒子、導電材料、及連接結構體

本發明之目的在於提供一種樹脂粒子，其耐熱性優異，且於用作導電性粒子之基材粒子之情形時，能夠應對較低壓力下之熱壓接安裝而獲得連接可靠性優異之連接結構體。又，本發明之目的在於提高一種使用該樹脂粒子而成之導電性粒子、導電材料、及連接結構體。 本發明之樹脂粒子之5%失重溫度為350℃以上，於25℃之10%K值為100 N/mm 2 以上且2500 N/mm 2 以下，且於25℃之30%K值為100 N/mm 2 以上且1500 N/mm 2 以下。

晶圓的加工方法

[課題]在不使品質降低的情形下形成器件晶片。 [解決手段]一種晶圓的加工方法，讓已將複數個器件形成在藉由分割預定線所區劃出的正面的各區域中之晶圓分割成一個個的器件晶片，前述晶圓的加工方法具備以下步驟：聚烯烴系片材配設步驟，將晶圓定位在具有容置晶圓之開口的框架的該開口內，並將聚烯烴系片材配設在晶圓的背面與框架的外周；一體化步驟，將該聚烯烴系片材加熱並藉由熱壓接來將晶圓及該框架透過該聚烯烴系片材一體化；分割步驟，沿著該分割預定線照射對該晶圓具有吸收性之波長的雷射光束，而形成分割溝來將該晶圓分割成一個個的器件晶片；及拾取步驟，將該聚烯烴系片材加熱並將器件晶片頂推而拾取該器件晶片。

晶圓的加工方法

[課題]在不使品質降低的情形下形成元件晶片。 [解決手段]一種晶圓的加工方法，讓已將複數個元件形成在藉由分割預定線所區劃出的正面的各區域中之晶圓分割成一個個的元件晶片，前述晶圓的加工方法具備以下步驟：聚烯烴系片材配設步驟，將晶圓定位在具有容置晶圓之開口的框架的該開口內，並將聚烯烴系片材配設在晶圓的背面與框架的外周；一體化步驟，將該聚烯烴系片材加熱並藉由熱壓接來將晶圓及該框架透過該聚烯烴系片材而一體化；分割步驟，沿著該分割預定線照射對該晶圓具有吸收性之波長的雷射光束，而形成分割溝以將該晶圓分割成一個個的元件晶片；及拾取步驟，從該聚烯烴系片材拾取一個個的該元件晶片。

Thermal conduction sheet holder and method of manufacturing heat dissipating device

A thermal conduction sheet holder include, in the following order, an elongated carrier film, a plurality of thermal conduction sheets, and an elongated cover film covering the plurality of thermal conduction sheets, the shortest distance between adjacent thermal conduction sheets is 2 mm or more, the plurality of thermal conduction sheets are disposed at intervals in a longitudinal direction of the carrier film and the cover film, and the plurality of thermal conduction sheets are peelable from the cover film and the carrier film.

用于被堆叠的晶粒的纳米级互连阵列

本发明提供一种微电子组件，其包括：一绝缘层，其具有成一纳米级间距阵列安置于其中的多个纳米级导体；及一对微电子元件。所述纳米级导体可形成所述微电子元件的接点之间的电气互连，而所述绝缘层可以机械方式将所述微电子元件耦接在一起。

晶圓的加工方法

[課題]在不使品質降低的情形下形成元件晶片。 [解決手段]一種晶圓的加工方法，讓已將複數個元件形成在藉由分割預定線所區劃出的正面的各區域中之晶圓分割成一個個的元件晶片，前述晶圓的加工方法具備以下步驟：聚烯烴系片材配設步驟，將晶圓定位在具有容置晶圓之開口的框架的該開口內，並將聚烯烴系片材配設在晶圓的背面與框架的外周；一體化步驟，將該聚烯烴系片材加熱並藉由熱壓接來將晶圓及該框架透過該聚烯烴系片材一體化；分割步驟，沿著該分割預定線照射對該晶圓具有吸收性之波長的雷射光束，而形成分割溝來將該晶圓分割成一個個的元件晶片；及拾取步驟，藉由噴附空氣來將元件晶片頂推，並從該聚烯烴系片材拾取一個個的該元件晶片。

Engineered Polymer-Based Electronic Materials

A composition for use in an electronic assembly process, the composition comprising a filler dispersed in an organic medium, wherein: the organic medium comprises a polymer; the filler comprises one or more of graphene, functionalized graphene, graphene oxide, a polyhedral oligomeric silsesquioxane, graphite, a 2D material, aluminum oxide, zinc oxide, aluminum nitride, boron nitride, silver, nano fibers, carbon fibers, diamond, carbon nanotubes, silicon dioxide and metal-coated particles, and the composition comprises from 0.001 to 40 wt. % of the filler based on the total weight of the composition.

晶片的加工方法

提供晶片的加工方法，不降低品质而形成器件芯片。该晶片的加工方法将在由分割预定线划分的正面的各区域内形成有多个器件的晶片分割成各个器件芯片，其中，该晶片的加工方法具有如下的工序：聚烯烃系片配设工序，将晶片定位于具有对晶片进行收纳的开口的框架的该开口内，将聚烯烃系片配设在晶片的背面和框架的外周上；一体化工序，对该聚烯烃系片进行加热，通过热压接使晶片与该框架借助该聚烯烃系片而一体化；分割工序，沿着该分割预定线照射对于该晶片具有吸收性的波长的激光束，形成分割槽而将该晶片分割成各个器件芯片；以及拾取工序，对该聚烯烃系片进行加热，将器件芯片顶起，拾取该器件芯片。

Wafer processing method including applying a polyolefin sheet to a wafer

A wafer processing method includes a polyolefin sheet providing step of positioning a wafer (1) in an inside opening (7a) of a ring frame (7) and providing a polyolefin sheet (9) on a back side (1b) of the wafer (1) and on a back side (7c) of the ring frame (7), a uniting step of heating the polyolefin sheet (9) as applying a pressure to the polyolefin sheet (9) to thereby unite the wafer (1) and the ring frame (7) through the polyolefin sheet (9) by thermocompression bonding, a dividing step of applying a laser beam (16) to the wafer (1) to form division grooves (3a) in the wafer (1), thereby dividing the wafer (1) into individual device chips, and a pickup step of blowing air (34a) to each device chip through the polyolefin sheet (9) to push up each device chip, thereby picking up each device chip from the polyolefin sheet (9) after performing the dividing step. (FIG.6)

用於積體電路總成之模製合成外殼

含填料膜

各向异性导电膜等的含填料膜10A具备填料分散层3，所述填料分散层3具有：树脂层2、在树脂层2中以单层分散的由填料1A构成的第一填料层、和在与第一填料层不同的深度在树脂层2中以单层分散的由填料1B构成的第二填料层。第一填料层的填料1A从树脂层2的一侧表面2a露出、或接近于该表面2a，第二填料层的填料1B从树脂层2的另一侧表面2b露出、或接近于该表面2b。

晶片的加工方法

提供晶片的加工方法，不降低品质而形成器件芯片。该晶片的加工方法将在由分割预定线划分的正面的各区域内形成有多个器件的晶片分割成各个器件芯片，其中，该晶片的加工方法具有如下的工序：聚烯烃系片配设工序，将晶片定位于具有对晶片进行收纳的开口的框架的该开口内，将聚烯烃系片配设在晶片的背面和框架的外周上；一体化工序，对该聚烯烃系片进行加热，通过热压接使晶片与该框架借助该聚烯烃系片而一体化；分割工序，沿着该分割预定线照射对于该晶片具有吸收性的波长的激光束，形成分割槽而将该晶片分割成各个器件芯片；以及拾取工序，吹送空气而将器件芯片顶起，从该聚烯烃系片拾取各个该器件芯片。

晶片的加工方法

提供晶片的加工方法，不降低品质而形成器件芯片。该晶片的加工方法将在由分割预定线划分的正面的各区域内形成有多个器件的晶片分割成各个器件芯片，其中，该晶片的加工方法具有如下的工序：聚烯烃系片配设工序，将晶片定位于具有对晶片进行收纳的开口的框架的该开口内，将聚烯烃系片配设在晶片的背面和框架的外周上；一体化工序，对该聚烯烃系片进行加热，通过热压接使晶片与该框架借助该聚烯烃系片而一体化；分割工序，沿着该分割预定线照射对于该晶片具有吸收性的波长的激光束，形成分割槽而将该晶片分割成各个器件芯片；以及拾取工序，从该聚烯烃系片拾取各个该器件芯片。

웨이퍼의 가공 방법

본 발명은, 품질을 저하시키지 않고 디바이스 칩을 형성하는 것을 목적으로 한다. 복수의 디바이스가, 분할 예정 라인에 의해 구획된 표면의 각 영역에 형성된 웨이퍼를 개개의 디바이스 칩으로 분할하는 웨이퍼의 가공 방법으로서, 웨이퍼를 수용하는 개구를 갖는 프레임의 상기 개구 내에 웨이퍼를 위치시키고, 웨이퍼의 이면과 프레임의 외주에 폴리올레핀계 시트를 배치하는 폴리올레핀계 시트 배치 공정과, 상기 폴리올레핀계 시트를 가열하여 열 압착에 의해 웨이퍼와 상기 프레임을 상기 폴리올레핀계 시트를 통해 일체화하는 일체화 공정과, 상기 웨이퍼에 대하여 흡수성을 갖는 파장의 레이저빔을 상기 분할 예정 라인을 따라 조사하고, 분할홈을 형성하여 상기 웨이퍼를 개개의 디바이스 칩으로 분할하는 분할 공정과, 에어를 분사하여 디바이스 칩을 밀어올려, 상기 폴리올레핀계 시트로부터 개개의 상기 디바이스 칩을 픽업하는 픽업 공정을 포함한다.

ウェーハの加工方法

【課題】品質を低下させることなくデバイスチップを形成する。【解決手段】複数のデバイスが、分割予定ラインによって区画された表面の各領域に形成されたウェーハを個々のデバイスチップに分割するウェーハの加工方法であって、ウェーハを収容する開口を有するフレームの該開口内にウェーハを位置付け、ウェーハの裏面とフレームの外周とにポリオレフィン系シートを配設するポリオレフィン系シート配設工程と、該ポリオレフィン系シートを加熱し熱圧着によりウェーハと該フレームとを該ポリオレフィン系シートを介して一体化する一体化工程と、該ウェーハに対して吸収性を有する波長のレーザービームを該分割予定ラインに沿って照射し、分割溝を形成して該ウェーハを個々のデバイスチップに分割する分割工程と、該ポリオレフィン系シートを加熱し、デバイスチップを突き上げ、該デバイスチップをピックアップするピックアップ工程と、を備える。【選択図】図４

웨이퍼의 가공 방법

본 발명은, 품질을 저하시키지 않고 디바이스 칩을 형성하는 것을 목적으로 한다. 복수의 디바이스가, 분할 예정 라인에 의해 구획된 표면의 각 영역에 형성된 웨이퍼를 개개의 디바이스 칩으로 분할하는 웨이퍼의 가공 방법으로서, 웨이퍼를 수용하는 개구를 갖는 프레임의 상기 개구 내에 웨이퍼를 위치시키고, 웨이퍼의 이면과 프레임의 외주에 폴리올레핀계 시트를 배치하는 폴리올레핀계 시트 배치 공정과, 상기 폴리올레핀계 시트를 가열하여 열 압착에 의해 웨이퍼와 상기 프레임을 상기 폴리올레핀계 시트를 통해 일체화하는 일체화 공정과, 상기 웨이퍼에 대하여 흡수성을 갖는 파장의 레이저빔을 상기 분할 예정 라인을 따라 조사하고, 분할홈을 형성하여 상기 웨이퍼를 개개의 디바이스 칩으로 분할하는 분할 공정과, 상기 폴리올레핀계 시트를 가열하고, 디바이스 칩을 밀어올려, 상기 디바이스 칩을 픽업하는 픽업 공정을 포함한다.

显示装置和各向异性导电膜

本公开涉及一种显示装置和一种各向异性导电膜。各向异性导电膜设置在显示面板与印刷电路板之间，各向异性导电膜包括：基体树脂；多个第一导电球，分散在基体树脂中，多个第一导电球中的每一个第一导电球包括由聚合物材料制成的核和围绕核的至少一个金属层；和多个第二导电球，分散在基体树脂中，多个第二导电球中的每一个第二导电球由可熔材料制成，并且各向异性导电膜具有：第一区域，在第一区域中，各向异性导电膜在显示装置的厚度方向上与第一焊盘电极和第一引线电极重叠；和第二区域，作为设置在第一引线电极与第二引线电极之间的区域。第一导电球的金属层和第二导电球的表面中的每一者与第一焊盘电极和第一引线电极两者接触。

用於積體電路總成之模製合成外殼

本揭示案之實施例係針對用於積體電路(IC)總成之模製合成外殼。在一實施例中，用於積體電路(IC)總成之外殼可包括模製上蓋結構，該模製上蓋結構具有主體部分及側面部分，該側面部分自該主體部分延伸且形成空腔，該空腔經組配以容納該IC總成，其中該主體部分及該側面部分共用包含聚合物的相連內部材料且共用包含金屬的相連外部材料，該相連內部材料具有形成於該主體部分中的開口，使得該IC總成可經由該開口與該相連外部材料熱耦接。可描述且/或請求其他實施例。

Molded composite enclosure for integrated circuit assembly

集積回路アセンブリ用の成形コンポジットエンクロージャ

本開示の実施形態は、集積回路（ＩＣ）アセンブリ用の成形された複合筐体（成形コンポジットエンクロージャ）に向けられる。一実施形態において、集積回路（ＩＣ）アセンブリ用の筐体は、本体部分と、該本体部分から延在し、ＩＣアセンブリを収容するように構成されたキャビティを形成する側面部分と、を有する成形蓋構造を含むことができ、上記本体部分及び上記側面部分は、ポリマーを有する連続した内側材料を共有し、且つ金属を有する連続した外側材料を共有し、上記連続した内側材料は、ＩＣアセンブリが開口を通して上記連続した外側材料と熱的に結合され得るように上記本体部分に形成された開口を有する。他の実施形態も記載され及び／又は特許請求され得る。

집적 회로 조립체용 성형 복합 인클로저

본 발명의 실시예는 집적 회로(IC) 조립체용 성형 복합 인클로저에 관한 것이다. 일 실시예에서, 집적 회로(IC) 조립체용 인클로저는 보디 부분, 및 상기 보디 부분으로부터 연장되고 IC 조립체를 수용하도록 구성된 공동을 형성하는 사이드 부분을 갖는 성형 덮개 구조물을 구비할 수 있으며, 상기 보디 부분과 사이드 부분은 폴리머를 포함하는 인접 내측 재료를 공유하고 금속을 포함하는 인접 외측 재료를 공유하며, 인접 내측 재료는 IC 조립체가 개구를 통해서 인접 외측 재료와 열적으로 결합될 수 있도록 보디 부분에 형성되는 개구를 갖는다. 다른 실시예가 기재 및/또는 청구될 수 있다.

Molded composite enclosure for integrated circuit assembly

Embodiments of the present disclosure are directed toward a molded composite enclosure for an integrated circuit (IC) assembly. In one embodiment, an enclosure for an integrated circuit (IC) assembly may include a molded lid structure having a body portion, and a side portion that extends from the body portion and forms a cavity configured to house the IC assembly, wherein the body portion and the side portion share a contiguous interior material comprising a polymer and share a contiguous exterior material comprising a metal, the contiguous interior material having an opening formed in the body portion such that the IC assembly can be thermally coupled with the contiguous exterior material through the opening. Other embodiments may be described and/or claimed.

ウェーハの加工方法

Thermally conductive sheet holder and method for manufacturing heat dissipation device

Method of deposition of a thermal interface material onto a circuit assembly and an integrated circuit formed therefrom

A method of deposition of a thermal interface material onto a circuit assembly and an integrated circuit formed therefrom is provided. The method includes depositing a thermal interface material at a first layer thickness between a first layer of a circuit assembly and a second layer of the circuit assembly. The thermal interface material includes an emulsion of liquid metal droplets and polymer. The first layer thickness is at least 1.1 times a D90 of the liquid metal droplets prior to compressing the circuit assembly. The method includes compressing the circuit assembly to decrease the first layer thickness to a second layer thickness, thereby deforming the liquid metal droplets. The second layer thickness is no greater than a D90 of the liquid metal droplets in thermal interface material prior to compressing the circuit assembly.

Thermal interface material, an integrated circuit formed therewith, and a method of application thereof

A thermal interface material, an integrated circuit formed therewith, and a method of application thereof are provided. The thermal interface material includes 5% to 30% by volume of a polymer component and at least 70% by volume of liquid metal droplets, all based on total volume of the thermal interface material. The polymer component has a first polymer having a molecular weight in a range of 400 g/mol to 400,000 g/mol. The liquid metal droplets are dispersed throughout the polymer component.

Anisotropic conductive film and production method of the same

An anisotropic conductive film contains conductive particles and spacers. The spacers are arranged at a central part of the film in a width direction. The central part of the film in the width direction represents 20 to 80% of the overall width of the film. The height of the spacers in the thickness direction of the anisotropic conductive film is larger than 5 μm and less than 75 μm. Such an anisotropic conductive film has a layered structure having a first insulating adhesion layer and a second insulating adhesion layer, wherein the conductive particles are dispersed in the first insulating adhesion layer, and the spacers are regularly arranged on a surface of the first insulating adhesion layer on a side of the second insulating adhesion layer.

블록공중합체 마이셀을 이용한 형광체층 형성 방법

블록공중합체 마이셀을 이용한 형광체층 형성 방법이 개시된다.　 본 발명에 따른 형광체층 형성 방법은, 기판을 준비하는 단계; 블록공중합체 마이셀 용액을 제조하는 단계; 상기 블록공중합체 마이셀의 코어에 제1 형광체 및 제2 형광체를 도입하여 제1 마이셀 용액을 제조하는 단계; 상기 블록공중합체 마이셀의 코어에 상기 제1 형광체 및 제3 형광체를 도입하여 제2 마이셀 용액을 제조하는 단계; 상기 제1 마이셀 용액과 상기 제2 마이셀 용액을 혼합하는 단계; 및 상기 기판 상에 상기 제1 마이셀 용액과 상기 제2 마이셀 용액이 혼합된 용액을 도포하는 단계를 포함한다.　 본 발명에 따르면 이종의 형광체를 마이셀에 도입하는 방법을 적절히 제어하여 형광체의 발광 세기를 증폭시킬 수 있고, 발광 세기가 증폭된 형광체를 서로 다른 마이셀 코어 속에 도입하여 이를 혼합함으로써 증폭된 개별 발광색을 하나의 발광층 내에서 얻을 수도 있다. 블록공중합체, 마이셀, 형광체, FRET

晶片的加工方法

提供晶片的加工方法，不降低品质而形成器件芯片。该晶片的加工方法将在由分割预定线划分的正面的各区域内形成有多个器件的晶片分割成各个器件芯片，其中，该晶片的加工方法具有如下的工序：聚酯系片配设工序，将晶片定位于具有对晶片进行收纳的开口的框架的该开口内，将聚酯系片配设在晶片的背面和框架的外周上；一体化工序，对该聚酯系片进行加热，通过热压接使晶片与该框架借助该聚酯系片而一体化；分割工序，沿着该分割预定线照射对于该晶片具有吸收性的波长的激光束，形成分割槽而将该晶片分割成各个器件芯片；以及拾取工序，对该聚酯系片进行加热，并将器件芯片顶起，从该聚酯系片拾取该器件芯片。

端子及连接方法

本发明防止在基板上安装有半导体芯片的半导体装置中所述半导体芯片和所述基板的连接部的损坏。该端子设置在元件的电极和安装有所述元件的基板的电极之间，并且电连接所述元件的所述电极和所述基板的所述电极。所述端子设置有多个单元网格和连接部。设置在所述端子中的所述单元网格通过将多个梁连接成立方体形状而形成。设置在所述端子中的所述连接部连接所述多个单元网格中的相邻单元网格。

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用于集成电路组件的模塑复合壳体

本公开内容的实施例针对用于集成电路(IC)组件的模塑复合壳体。在一个实施例中，用于集成电路(IC)组件的壳体可以包括具有本体部分和侧部部分的模塑盖结构，该侧部部分从本体部分延伸并且形成被配置为容纳IC组件的腔，其中，本体部分和侧部部分共享包括聚合物的连续内部材料并且共享包括金属的连续外部材料，连续内部材料具有形成在本体部分中的开口，以使得IC组件能够通过开口与连续外部材料热耦合。可以描述和/或请求保护其它实施例。

晶圓的加工方法

[課題]在不使品質降低的情形下形成器件晶片。 [解決手段]一種晶圓的加工方法，讓已將複數個器件形成在藉由分割預定線所區劃出的正面的各區域中之晶圓分割成一個個的器件晶片，前述晶圓的加工方法具備以下步驟：聚酯系片材配設步驟，將晶圓定位在具有容置晶圓之開口的框架的該開口內，並將聚酯系片材配設在晶圓的背面與框架的外周；一體化步驟，將該聚酯系片材加熱並藉由熱壓接來將晶圓及該框架透過該聚酯系片材一體化；分割步驟，沿著該分割預定線照射對該晶圓具有吸收性之波長的雷射光束，而形成分割溝來將該晶圓分割成一個個的器件晶片；及拾取步驟，將該聚酯系片材加熱，並將器件晶片頂堆，而從該聚酯系片材拾取該器件晶片。

블록공중합체 마이셀을 이용한 형광체층 형성 방법

블록공중합체 마이셀을 이용한 형광체층 형성 방법이 개시된다.　 본 발명에 따른 형광체층 형성 방법은, 기판을 준비하는 단계; 블록공중합체 마이셀 용액을 제조하는 단계; 상기 블록공중합체 마이셀의 코어에 제1 형광체 및 제2 형광체를 도입하여 제1 마이셀 용액을 제조하는 단계; 상기 블록공중합체 마이셀의 코어에 상기 제1 형광체 및 제3 형광체를 도입하여 제2 마이셀 용액을 제조하는 단계; 상기 제1 마이셀 용액과 상기 제2 마이셀 용액을 혼합하는 단계; 및 상기 기판 상에 상기 제1 마이셀 용액과 상기 제2 마이셀 용액이 혼합된 용액을 도포하는 단계를 포함한다.　 본 발명에 따르면 이종의 형광체를 마이셀에 도입하는 방법을 적절히 제어하여 형광체의 발광 세기를 증폭시킬 수 있고, 발광 세기가 증폭된 형광체를 서로 다른 마이셀 코어 속에 도입하여 이를 혼합함으로써 증폭된 개별 발광색을 하나의 발광층 내에서 얻을 수도 있다. 블록공중합체, 마이셀, 형광체, FRET

晶片的加工方法

提供晶片的加工方法，不降低品质而形成器件芯片。该晶片的加工方法将在由分割预定线划分的正面的各区域内形成有多个器件的晶片分割成各个器件芯片，其中，该晶片的加工方法具有如下的工序：聚烯烃系片配设工序，将晶片定位于具有对晶片进行收纳的开口的框架的该开口内，将聚烯烃系片配设在晶片的背面和框架的外周上；一体化工序，对该聚烯烃系片进行加热，通过热压接使晶片与该框架借助该聚烯烃系片而一体化；分割工序，沿着该分割预定线照射对于该晶片具有吸收性的波长的激光束，形成分割槽而将该晶片分割成各个器件芯片；以及拾取工序，从该聚烯烃系片拾取各个该器件芯片。

晶片的加工方法

提供晶片的加工方法，不降低品质而形成器件芯片。该晶片的加工方法将在由分割预定线划分的正面的各区域内形成有多个器件的晶片分割成各个器件芯片，其中，该晶片的加工方法具有如下的工序：聚酯系片配设工序，将晶片定位于具有对晶片进行收纳的开口的框架的该开口内，将聚酯系片配设在晶片的背面和框架的外周上；一体化工序，对该聚酯系片进行加热，通过热压接使晶片与该框架借助该聚酯系片而一体化；分割工序，沿着该分割预定线照射对于该晶片具有吸收性的波长的激光束，形成分割槽而将该晶片分割成各个器件芯片；以及拾取工序，吹送空气而将器件芯片顶起，从该聚酯系片拾取各个该器件芯片。

含有填料之膜

本發明之各向異性導電膜等含有填料之膜10A具備樹脂層2及填料分散層3，上述填料分散層3具有：第1填料層，其由以單層分散於樹脂層2之填料1A所構成；及第2填料層，其由在與第1填料層不同之深度以單層分散於樹脂層2之填料1B所構成。第1填料層之填料1A自樹脂層2之一表面2a露出、或接近於該表面2a，第2填料層之填料1B自樹脂層2之另一表面2b露出、或接近於該表面2b。

Molded composite enclosure for integrated circuit assembly

Resin particles, electrically conductive particles, electrically conductive material, and connection structure

The present invention aims to provide resin particles that have excellent heat resistance and that, when used as base particles of conductive particles, are applicable to mounting by thermocompression bonding at low pressure to produce a connection structure having excellent connection reliability. The present invention also aims to provide conductive particles, a conductive material, and a connection structure each including the resin particles. Provided are resin particles having a 5% weight loss temperature of 350°C or higher, a 10% K value at 25°C of 100 N/mm² or more and 2,500 N/mm² or less, and a 30% K value at 25°C of 100 N/mm² or more and 1,500 N/mm² or less.

用于被堆叠的晶粒的纳米级互连阵列

本发明提供一种微电子组件，其包括：一绝缘层，其具有成一纳米级间距阵列安置于其中的多个纳米级导体；及一对微电子元件。所述纳米级导体可形成所述微电子元件的接点之间的电气互连，而所述绝缘层可以机械方式将所述微电子元件耦接在一起。

显示装置和各向异性导电膜

本公开涉及一种显示装置和一种各向异性导电膜。各向异性导电膜设置在显示面板与印刷电路板之间，各向异性导电膜包括：基体树脂；多个第一导电球，分散在基体树脂中，多个第一导电球中的每一个第一导电球包括由聚合物材料制成的核和围绕核的至少一个金属层；和多个第二导电球，分散在基体树脂中，多个第二导电球中的每一个第二导电球由可熔材料制成，并且各向异性导电膜具有：第一区域，在第一区域中，各向异性导电膜在显示装置的厚度方向上与第一焊盘电极和第一引线电极重叠；和第二区域，作为设置在第一引线电极与第二引线电极之间的区域。第一导电球的金属层和第二导电球的表面中的每一者与第一焊盘电极和第一引线电极两者接触。

自致密纳米银浆及制备用于高功率电子器件的互连层的方法

在选自GaN或SiC体系的高温半导体装置与基板之间形成自致密互连层。互连层包括具有微米级银颗粒的基质，其含量约为10至60重量百分比，且该微米级银颗粒具有约0.1至15微米的粒径；键合颗粒以化学键合的方式连接基质中的微米银颗粒，且该键合颗粒包括核心银纳米颗粒，以及以原位形成并且以化学结合的方式结合到核心银纳米颗粒的表面银纳米颗粒，同时该表面银纳米颗粒也以化学结合的方式与具有微米级银颗粒的基质结合。该键合颗粒具有约10至100纳米的核心粒径，而原位形成的表面银纳米颗粒具有约3至9纳米的粒径。

热传导片材保持体以及放热装置的制造方法

本发明的热传导片材保持体依次具备长条状的承载膜；多个热传导片材；以及覆盖上述多个热传导片材的长条状的覆盖膜，相邻的上述热传导片材的最短距离为2mm以上，上述多个热传导片材在上述承载膜以及上述覆盖膜的长度方向上空有间隔地进行配置，上述多个热传导片材可以从上述覆盖膜以及上述承载膜上剥离。

树脂粒子、导电性粒子、导电材料和连接结构体

本发明的目的在于提供一种树脂粒子，其耐热性优异，并且在用于导电性粒子的基材粒子的情况下能够得到应对低压力下的热压接安装、连接可靠性优异的连接结构体。另外，本发明的目的在于提供使用该树脂粒子而成的导电性粒子、导电材料和连接结构体。本发明为一种树脂粒子，其5％重量减少温度为350℃以上，25℃时的10％K值为100N/mm 2 以上且2500N/mm 2 以下，且25℃时的30％K值为100N/mm 2 以上且1500N/mm 2 以下。

端子及连接方法

本发明防止在基板上安装有半导体芯片的半导体装置中所述半导体芯片和所述基板的连接部的损坏。该端子设置在元件的电极和安装有所述元件的基板的电极之间，并且电连接所述元件的所述电极和所述基板的所述电极。所述端子设置有多个单元网格和连接部。设置在所述端子中的所述单元网格通过将多个梁连接成立方体形状而形成。设置在所述端子中的所述连接部连接所述多个单元网格中的相邻单元网格。

含填料膜

各向异性导电膜等的含填料膜10A具备填料分散层3，所述填料分散层3具有：树脂层2、在树脂层2中以单层分散的由填料1A构成的第一填料层、和在与第一填料层不同的深度在树脂层2中以单层分散的由填料1B构成的第二填料层。第一填料层的填料1A从树脂层2的一侧表面2a露出、或接近于该表面2a，第二填料层的填料1B从树脂层2的另一侧表面2b露出、或接近于该表面2b。

Resin particles, electrically conductive particles, electrically conductive material, and connection structure

The present invention aims to provide resin particles that have excellent heat resistance and that, when used as base particles of conductive particles, are applicable to mounting by thermocompression bonding at low pressure to produce a connection structure having excellent connection reliability. The present invention also aims to provide conductive particles, a conductive material, and a connection structure each including the resin particles. Provided are resin particles having a 5% weight loss temperature of 350° C. or higher, a 10% K value at 25° C. of 100 N/mm2 or more and 2,500 N/mm2 or less, and a 30% K value at 25° C. of 100 N/mm2 or more and 1,500 N/mm2 or less.

熱伝導シート保持体及び放熱装置の製造方法

【課題】効率的に放熱装置を製造することが可能な熱伝導シート保持体を提供する。【解決手段】長尺状のキャリアフィルムと、複数の熱伝導シートと、前記複数の熱伝導シートを覆う長尺状のカバーフィルムと、をこの順で備え、隣接する前記熱伝導シートの最短距離は２ｍｍ以上であり、前記複数の熱伝導シートは、前記キャリアフィルム及び前記カバーフィルムの長手方向に間隔を空けて配置され、前記複数の熱伝導シートは、前記カバーフィルム及び前記キャリアフィルムから剥離可能である熱伝導シート保持体。【選択図】なし

晶片的加工方法

提供晶片的加工方法，不降低品质而形成器件芯片。该晶片的加工方法将在由分割预定线划分的正面的各区域内形成有多个器件的晶片分割成各个器件芯片，其中，该晶片的加工方法具有如下的工序：聚烯烃系片配设工序，将晶片定位于具有对晶片进行收纳的开口的框架的该开口内，将聚烯烃系片配设在晶片的背面和框架的外周上；一体化工序，对该聚烯烃系片进行加热，通过热压接使晶片与该框架借助该聚烯烃系片而一体化；分割工序，沿着该分割预定线照射对于该晶片具有吸收性的波长的激光束，形成分割槽而将该晶片分割成各个器件芯片；以及拾取工序，对该聚烯烃系片进行加热，将器件芯片顶起，拾取该器件芯片。

晶片的加工方法

提供晶片的加工方法，不降低品质而形成器件芯片。该晶片的加工方法将在由分割预定线划分的正面的各区域内形成有多个器件的晶片分割成各个器件芯片，其中，该晶片的加工方法具有如下的工序：聚酯系片配设工序，将晶片定位于具有对晶片进行收纳的开口的框架的该开口内，将聚酯系片配设在晶片的背面和框架的外周上；一体化工序，对该聚酯系片进行加热，通过热压接使晶片与该框架借助该聚酯系片而一体化；分割工序，沿着该分割预定线照射对于该晶片具有吸收性的波长的激光束，形成分割槽而将该晶片分割成各个器件芯片；以及拾取工序，对该聚酯系片进行加热，并将器件芯片顶起，从该聚酯系片拾取该器件芯片。

晶片的加工方法

提供晶片的加工方法，不降低品质而形成器件芯片。该晶片的加工方法将在由分割预定线划分的正面的各区域内形成有多个器件的晶片分割成各个器件芯片，其中，该晶片的加工方法具有如下的工序：聚烯烃系片配设工序，将晶片定位于具有对晶片进行收纳的开口的框架的该开口内，将聚烯烃系片配设在晶片的背面和框架的外周上；一体化工序，对该聚烯烃系片进行加热，通过热压接使晶片与该框架借助该聚烯烃系片而一体化；分割工序，沿着该分割预定线照射对于该晶片具有吸收性的波长的激光束，形成分割槽而将该晶片分割成各个器件芯片；以及拾取工序，吹送空气而将器件芯片顶起，从该聚烯烃系片拾取各个该器件芯片。

晶片的加工方法

提供晶片的加工方法，不降低品质而形成器件芯片。该晶片的加工方法将在由分割预定线划分的正面的各区域内形成有多个器件的晶片分割成各个器件芯片，其中，该晶片的加工方法具有如下的工序：聚酯系片配设工序，将晶片定位于具有对晶片进行收纳的开口的框架的该开口内，将聚酯系片配设在晶片的背面和框架的外周上；一体化工序，对该聚酯系片进行加热，通过热压接使晶片与该框架借助该聚酯系片而一体化；分割工序，沿着该分割预定线照射对于该晶片具有吸收性的波长的激光束，形成分割槽而将该晶片分割成各个器件芯片；以及拾取工序，吹送空气而将器件芯片顶起，从该聚酯系片拾取各个该器件芯片。

晶片的加工方法

提供晶片的加工方法，不降低品质而形成器件芯片。该晶片的加工方法将在由分割预定线划分的正面的各区域内形成有多个器件的晶片分割成各个器件芯片，其中，该晶片的加工方法具有如下的工序：聚烯烃系片配设工序，将晶片定位于具有对晶片进行收纳的开口的框架的该开口内，将聚烯烃系片配设在晶片的背面和框架的外周上；一体化工序，对该聚烯烃系片进行加热，通过热压接使晶片与该框架借助该聚烯烃系片而一体化；分割工序，沿着该分割预定线照射对于该晶片具有吸收性的波长的激光束，形成分割槽而将该晶片分割成各个器件芯片；以及拾取工序，从该聚烯烃系片拾取各个该器件芯片。

含填料膜

各向异性导电膜等的含填料膜10A具备填料分散层3，所述填料分散层3具有：树脂层2、在树脂层2中以单层分散的由填料1A构成的第一填料层、和在与第一填料层不同的深度在树脂层2中以单层分散的由填料1B构成的第二填料层。第一填料层的填料1A从树脂层2的一侧表面2a露出、或接近于该表面2a，第二填料层的填料1B从树脂层2的另一侧表面2b露出、或接近于该表面2b。

Anisotropic conductive film including oblique region having lower curing ratio

An anisotropic conductive film has a first connection layer and a second connection layer formed on surface of the first connection layer. The first connection layer is a photopolymerized resin layer, and the second connection layer is a thermo- or photo-cationically, anionically, or radically polymerizable resin layer. On the surface of first connection layer on the side of second connection layer, conductive particles for anisotropic conductive connection are arranged in a single layer. A region in which the curing ratio is lower than that of the surface of the first connection layer exists in a direction oblique to the thickness direction of the first connection layer. Alternatively, the curing ratio of a region relatively near another surface of the first connection layer among regions of the first connection layer in the vicinity of the conductive particles is lower than that of the surface of the first connection layer.

Anisotropic conductive film, method for producing anisotropic conductive film, method for producing connection body, and connection method

To reduce substrate warp occurring after connection an anisotropic conductive film is used. An anisotropic conductive film has: a first insulating adhesive layer; a second insulating adhesive layer; and a conductive particle-containing layer sandwiched by the first insulating adhesive layer and the second insulating adhesive layer and having conductive particles contained in an insulating adhesive, wherein air bubbles are contained between the conductive particle-containing layer and the first insulating adhesive layer, and, the conductive particle-containing layer, a portion thereof below the conductive particles and in contact with the second insulating adhesive layer has a lower degree of cure than other portions thereof.