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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 3549. Отображено 100.

12-01-2012 дата публикации

Power semiconductor module and fabrication method

Номер: US20120009733A1

Автор: Eladio Clemente Delgado, Ernest Wayne Balch, Kevin Matthew Durocher, Paul Alan McConnelee, Raymond Albert Fillion, Richard Alfred Beaupre, Stephen Daley Arthur

Принадлежит: General Electric Co

A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.

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Номер записи: 1

15-03-2012 дата публикации

Thermal interface material application for integrated circuit cooling

Номер: US20120063094A1

Автор: Dong G. Kam, Duixian Liu, Michael A. Gaynes, Scott K. Reynolds

Принадлежит: International Business Machines Corp

Techniques provide improved thermal interface material application in an assembly associated with an integrated circuit package. For example, an apparatus comprises an integrated circuit module, a printed circuit board, and a heat transfer device. The integrated circuit module is mounted on a first surface of the printed circuit board. The printed circuit board has at least one thermal interface material application via formed therein in alignment with the integrated circuit module. The heat transfer device is mounted on a second surface of the printed circuit board and is thermally coupled to the integrated circuit module. The second surface of the printed circuit board is opposite to the first surface of the printed circuit board.

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Номер записи: 2

15-03-2012 дата публикации

Method of manufacture of integrated circuit packaging system with stacked integrated circuit

Номер: US20120064668A1

Автор: Henry Descalzo Bathan, Jairus Legaspi Pisigan, Zigmund Ramirez Camacho

Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.

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Номер записи: 3

05-07-2012 дата публикации

Low cost thermally enhanced hybrid bga and method of manufacturing the same

Номер: US20120168929A1

Автор: Kim-yong Goh

Принадлежит: STMICROELECTRONICS PTE LTD

A semiconductor package is formed having a substrate juxtaposed on at least two sides of a semiconductor die. Both the substrate and the semiconductor die are affixed to a conductive layer that draws heat generated during use of the semiconductor package away from the semiconductor die and the substrate. There are also electrical contacts affixed to the substrate and the semiconductor die. The electrical contacts facilitate electrical connection between the semiconductor die, the substrate, and any external devices or components making use of the semiconductor die. The substrate, semiconductor die, and at least a portion of some of the electrical contacts are enclosed by an encapsulating layer insulating the components. Portions of the electrical contacts not enclosed by the encapsulating layer are affixed to an outside device, such as a printed circuit board.

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Номер записи: 4

19-07-2012 дата публикации

Dram device with built-in self-test circuitry

Номер: US20120182776A1

Автор: Ming Li, Scott C. Best

Принадлежит: RAMBUS INC

A dynamic random access memory (DRAM) device includes a first and second integrated circuit (IC) die. The first integrated circuit die has test circuitry to generate redundancy information. The second integrated circuit die is coupled to the first integrated circuit die in a packaged configuration including primary storage cells and redundant storage cells. The second integrated circuit die further includes redundancy circuitry responsive to the redundancy information to substitute one or more of the primary storage cells with one or more redundant storage cells.

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Номер записи: 5

26-07-2012 дата публикации

Direct Edge Connection for Multi-Chip Integrated Circuits

Номер: US20120187577A1

Автор: James L. Speidell, John U. Knickerbocker, Matthew J. Farinelli, Peter A. Gruber, Sherif A. Goma, Steven A. Cordes

Принадлежит: International Business Machines Corp

The present invention allows for direct chip-to-chip connections using the shortest possible signal path.

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Номер записи: 6

26-07-2012 дата публикации

Packaged semiconductor device for high performance memory and logic

Номер: US20120187578A1

Автор: Ming Li

Принадлежит: Individual

A packaged semiconductor device is disclosed. The device comprises a substrate having multiple layers between first and second oppositely disposed faces, and a cavity with an opening at the first face to nest at least one integrated circuit memory device. Logic circuitry is disposed on the second face and includes contacts for electrically coupling to the stacked integrated circuit memory devices. The logic circuitry is coupled to electrical contacts formed on the first face through first electrical paths formed in the multiple layers of the substrate, the first electrical paths including conductive traces and vias.

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Номер записи: 7

30-08-2012 дата публикации

Semiconductor device and noise suppressing method

Номер: US20120217653A1

Автор: Hisashi Ishida, Koichi Takemura

Принадлежит: NEC Corp

A first semiconductor chip ( 200 ) is mounted on a second semiconductor chip ( 100 ). The first semiconductor chip ( 200 ) has a first conductor pattern ( 222 ). The second semiconductor chip ( 100 ) has a second conductor pattern ( 122 ). The second conductor pattern ( 122 ) is formed at a region overlapping the first conductor pattern ( 222 ) in a plan view. At least one element selected from a group consisting of the first conductor pattern ( 222 ) and the second conductor pattern ( 122 ) has a repetitive structure.

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Номер записи: 8

13-09-2012 дата публикации

Chip-last embedded interconnect structures and methods of making the same

Номер: US20120228754A1

Автор: Fuhan Liu, Nitesh Kumbhat, Rao Tummala, Venkatesh Sundaram

Принадлежит: Georgia Tech Research Corp

The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.

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Номер записи: 9

20-09-2012 дата публикации

Electronic device and method for producing a device

Номер: US20120235298A1

Автор: Harry Hedler, Markus Brunnbauer, Thorsten Meyer

Принадлежит: INFINEON TECHNOLOGIES AG

An electronic device or devices and method for producing a device is disclosed. One embodiment provides an integrated component, a first package body and a contact device. The contact device penetrates the package body.

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Номер записи: 10

08-11-2012 дата публикации

Processing Signals by Couplers Embedded in an Integrated Circuit Package

Номер: US20120280763A1

Автор: Ahmadreza Rofougaran

Принадлежит: Broadcom Corp

Methods and systems for processing signals via directional couplers embedded in a package are disclosed and may include generating via a directional coupler, one or more output RF signals that may be proportional to a received RF signal. The directional coupler may be integrated in a multi-layer package. The generated RE signal may be processed by an integrated circuit electrically coupled to the multi-layer package. The directional coupler may include quarter wavelength transmission lines, which may include microstrip or coplanar structures. The directional coupler may be electrically coupled to one or more variable capacitances in the integrated circuit. The variable capacitance may include CMOS devices in the integrated circuit. The directional coupler may include discrete devices, which may be surface mount devices coupled to the multi-layer package or may be devices integrated in the integrated circuit. The integrated circuit may be flip-chip bonded to the multi-layer package.

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Номер записи: 11

31-01-2013 дата публикации

Semiconductor device, semiconductor module structure configured by vertically stacking semiconductor devices, and manufacturing method thereof

Номер: US20130026650A1

Автор: Akio Katsumata, Hiroshi Inoue, Osamu Yamagata, Satoru Itakura, Shigenori Sawachi, Yasuhiro Yamaji

Принадлежит: Individual

A semiconductor device is made up of an organic substrate; through vias which penetrate the organic substrate in its thickness direction; external electrodes and internal electrodes provided to the front and back faces of the organic substrate and electrically connected to the through vias; a semiconductor element mounted on one main surface of the organic substrate via a bonding layer, with an element circuit surface thereof facing upward; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part of this metal thin film wiring layer being exposed on an external surface; metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer; and external electrodes formed on the metal thin film wiring layer.

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Номер записи: 12

21-02-2013 дата публикации

Package-on-package structures

Номер: US20130043587A1

Автор: Huahung Kao, Shiann-Ming Liou

Принадлежит: MARVELL WORLD TRADE LTD

Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls.

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Номер записи: 13

07-03-2013 дата публикации

Thermally Enhanced Structure for Multi-Chip Device

Номер: US20130056871A1

Автор: Chen-Hua Yu, Chih-Hang Tung, Tung-Liang Shao

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved.

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Номер записи: 14

28-03-2013 дата публикации

Integrated circuit packaging system with encapsulation and method of manufacture thereof

Номер: US20130075923A1

Автор: HeeJo Chi, Hyungmin Lee, YeongIm Park

Принадлежит: Stats Chippac Pte Ltd

A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a substrate first side and a substrate second side opposite the substrate first side; attaching a base integrated circuit to the substrate first side; attaching a mountable integrated circuit to the substrate second side; attaching a via base to the substrate second side adjacent the mountable integrated circuit; forming a device encapsulation surrounding the via base and the mountable integrated circuit; and forming a via extension through the device encapsulation and attached to the via base, the via extension exposed from the device encapsulation.

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Номер записи: 15

04-07-2013 дата публикации

Semiconductor Package with a Bridge Interposer

Номер: US20130168854A1

Автор: Kevin Kunzhong Hu, Pieter Vorenkamp, Rezaur Rahman Khan, Sam Ziqun Zhao, Sampath K.V. Karikalan, Xiangdong Chen

Принадлежит: Broadcom Corp

There are disclosed herein various implementations of semiconductor packages including a bridge interposer. One exemplary implementation includes a first active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The semiconductor package also includes a second active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The second portion of the first active die and the second portion of the second active die include solder balls mounted on a package substrate, and are configured to communicate electrical signals to the package substrate utilizing the solder balls and without utilizing through-semiconductor vias (TSVs).

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Номер записи: 16

04-07-2013 дата публикации

Molded interposer package and method for fabricating the same

Номер: US20130168857A1

Автор: Andrew C. Chang, Thomas Matthew Gregorich, Tzu-Hung Lin

Принадлежит: MediaTek Inc

The invention provides a molded interposer package and a method for fabricating the same. The molded interposer package includes a plurality of metal studs. A molding material encapsulates the metal studs leaving the bottom surfaces of the metal studs exposed. A first chip is disposed on the molding material, connecting to the top surfaces of the metal studs. A plurality of solder balls connects and contacts to the bottom surfaces of the metal studs.

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Номер записи: 17

18-07-2013 дата публикации

Methods and Apparatus for Thinner Package on Package Structures

Номер: US20130181359A1

Автор: Jiun Yi Wu

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Methods and apparatus for thinner package on package (“PoP”) structures. A structure includes a first integrated circuit package including at least one integrated circuit device mounted on a first substrate and a plurality of package on package connectors extending from a bottom surface; and a second integrated circuit package including at least another integrated circuit device mounted on a second substrate and a plurality of lands on an upper surface coupled to the plurality of package on package connectors, and a plurality of external connectors extending from a bottom surface; wherein at least the second substrate is formed of a plurality of layers of laminated dielectric and conductors. In another embodiment a cavity is formed on the bottom surface of the first substrate and a portion of the another integrated circuit extends partially into the cavity. Methods for making the PoP structures are disclosed.

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Номер записи: 18

25-07-2013 дата публикации

Integrated circuit package assembly and method of forming the same

Номер: US20130187266A1

Автор: Hsien-Wei Chen

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An integrated circuit package assembly includes a first integrated circuit package and a second integrated circuit package disposed under the first integrated circuit package. Solder bumps are disposed between the first integrated circuit package and the second integrated circuit package providing electrical signal connections between the first integrated circuit package and the second integrated circuit package. At least one support structure is disposed between the first integrated circuit package and the second integrated circuit package to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package without providing electrical signal connections.

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Номер записи: 19

25-07-2013 дата публикации

Semiconductor Packaging Structure and Method

Номер: US20130187268A1

Автор: Cheng-Ting Chen, Chun-Cheng Lin, Chung-Shi Liu, Kuei-Wei Huang, Ming-Da Cheng, Wei-Hung Lin

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

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Номер записи: 20

01-08-2013 дата публикации

Transmission line transition having vertical structure and single chip package using land grip array coupling

Номер: US20130194754A1

Автор: Dong-Hyun Lee, Dong-Yun Jung, Jei-Young Lee, Ji-Hoon Kim, Jung-han Choi, Sung-Tae Choi, Young-Hwan Kim

Принадлежит: SAMSUNG ELECTRONICS CO LTD

An apparatus for a single chip package using Land Grid Array (LGA) coupling is provided. The apparatus includes a multi-layer substrate, at least one integrated circuit chip, and a Printed Circuit Board (PCB). The a multi-layer substrate has at least one substrate layer, has at least one first chip region and at least one second chip region in a lowermost substrate layer, configures a transmission line transition of a vertical structure for transmitting a signal from at least one integrated circuit chip coupled in the first chip region in a coaxial shape or in a form of a Co-Planar Waveguide guide (CPW), and has an LGP coupling pad for connecting with a Printed Circuit Board (PCB) in the lowermost layer. The at least one integrated circuit chip is coupled in the first chip region and the second chip region. The PCB is connected with the multi-layer substrate using the LGA coupling via the LGA coupling pad.

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Номер записи: 21

29-08-2013 дата публикации

Semiconductor Package with Integrated Electromagnetic Shielding

Номер: US20130221499A1

Автор: Kevin Kunzhong Hu, Pieter Vorenkamp, Rezaur Rahman Khan, Sam Ziqun Zhao, Sampath K.V. Karikalan, Xiangdong Chen

Принадлежит: Broadcom Corp

There are disclosed herein various implementations of a shield interposer situated between a top active die and a bottom active die for shielding the active dies from electromagnetic noise. One implementation includes an interposer dielectric layer, a through-silicon via (TSV) within the interposer dielectric layer, and an electromagnetic shield. The TSV connects the electromagnetic shield to a first fixed potential. The electromagnetic shield may include a grid of conductive layers laterally extending across the shield interposer. The shield interposer may also include another electromagnetic shield connected to another fixed potential.

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Номер записи: 22

31-10-2013 дата публикации

Semiconductor package module

Номер: US20130285232A1

Автор: Job Ha

Принадлежит: Samsung Electro Mechanics Co Ltd

Disclosed herein is a semiconductor package module, including: a circuit board having connection pads formed on one surface thereof; a semiconductor package including lead terminals protruded out of a housing; and an interposer positioned between the circuit board and the semiconductor package, the interposer including a body allowing the circuit board and the semiconductor package to be spaced apart from each other and elastic members contacted with the connection pads and the lead terminals.

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Номер записи: 23

19-12-2013 дата публикации

Contact and Method of Formation

Номер: US20130334710A1

Автор: Chih Chun Chiu, Chih-Wei Lin, Chung-Shi Liu, Kuei-Wei Huang, Meng-Tse Chen, Ming-Da Cheng, Wei-Hung Lin

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A system and method for forming contacts is provided. An embodiment comprises forming the contacts on a substrate and then coining the contacts by physically shaping them using, e.g., a molding chamber. The physical shaping of the contacts may be performed using a patterned portion of the molding chamber or else by placing a patterned stencil around the contacts prior before a force is applied to physically reshape the contacts. The contacts may be reshaped into a cylindrical, oval, cuboid, or rectangular shape, for example.

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Номер записи: 24

06-02-2014 дата публикации

Interface Substrate with Interposer

Номер: US20140035162A1

Автор: Rezaur Rahman Khan, Sam Ziqun Zhao

Принадлежит: Broadcom Corp

An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided.

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Номер записи: 25

27-03-2014 дата публикации

Method for producing multi-layer substrate and multi-layer substrate

Номер: US20140085843A1

Автор: Yoshihito OTSUBO

Принадлежит: Murata Manufacturing Co Ltd

A mounting-completed core parent substrate in which surface mount devices are mounted on both principal surfaces of the core parent substrate including a plurality of the core individual substrates and having a through hole formed in each core individual substrate so as to extend therethrough is formed. Then, resin layers in a partially cured state are formed on both the principal surfaces of the core parent substrate and the resin layers on both the principal surfaces are joined through the through holes so that the resin layers on both principal surfaces of each core individual substrate are joined and integrated to each other at a predetermined region, each core individual substrate being obtained by dividing the core parent substrate. After that, the resin layers are subjected to main curing. Thereafter, the core parent substrate is divided at a predetermined position and separated into the core individual substrates.

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Номер записи: 26

10-04-2014 дата публикации

TWO-SIDED-ACCESS EXTENDED WAFER-LEVEL BALL GRID ARRAY (eWLB) PACKAGE, ASSEMBLY AND METHOD

Номер: US20140097536A1

Автор: Nikolaus W. Schunk

Принадлежит: Avago Technologies General IP Singapore Pte Ltd

A two-sided-access (TSA) eWLB is provided that makes it possible to easily access electrical contact pads disposed on both the front and rear faces of the die(s) of the eWLB package. When fabricating the IC die wafer, metal stamps are formed in the IC die wafer in contact with the rear faces of the IC dies. When the IC dies are subsequently reconstituted in an artificial wafer, portions of the metal stamps are exposed through the mold of the artificial wafer. When the artificial wafer is sawed to singulate the TSA eWLB packages and the packages are mounted on PCBs, any electrical contact pad that is disposed on the rear face of the IC die can be accessed via the respective metal stamp of the IC die.

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Номер записи: 27

01-01-2015 дата публикации

DE-POP ON-DEVICE DECOUPLING FOR BGA

Номер: US20150001716A1

Автор: BROWN Paul James, Chan Alex

Принадлежит:

Embodiments of the invention place surface-mount devices such as decoupling capacitors, resistors or other devices directly on the underside of a ball grid array (BGA) electronic integrated circuit (EIC) package, in place of de-populated BGA pads. 1. An electronic integrated circuit (EIC) package comprising:an EIC substrate;an array of ball grid array (BGA) pads on a first side of said EIC substrate, arranged in a grid pattern of rows and columns; andcontact pads on said first side of said EIC substrate to accommodate electrical connection of a surface-mount device, wherein said surface-mount device occupies a grid location of said grid pattern in place of one or more BGA pads.2. The EIC package of claim 1 , wherein said contact pads comprise at least two adjacent contact pads.3. The EIC package of claim 2 , wherein each of the contact pads is connected to an adjacent BGA pad by a conductor on said first side of said EIC substrate.4. The EIC package of claim 1 , wherein said surface-mount device comprises a two-port device.5. The EIC package of claim 4 , wherein said surface-mount device comprises a decoupling capacitor.6. The EIC package of claim 1 , wherein said surface-mount device is selected from a set of a capacitor claim 1 , a resistor claim 1 , an inductor claim 1 , a diode claim 1 , a transistor claim 1 , a capacitor array claim 1 , and a resistor-capacitor circuit.7. The EIC package of claim 1 , wherein said BGA grid comprises a pitch of between about 0.4 mm×0.4 mm and about 1.27 mm×1.27 mm.8. The EIC package of claim 7 , wherein said BGA grid comprises an irregular pitch.9. A computer-aided design tool for accommodating a surface-mount device on a first surface of a ball grid array (BGA) electronic integrated circuit (EIC) package claim 7 , said tool comprising:a design tool configured to identify, in an EIC configuration of BGA pads in a grid pattern on said first side of said EIC package, at least two contact pads for forming directly on said first ...

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Номер записи: 28

04-01-2018 дата публикации

Planar integrated circuit package interconnects

Номер: US20180005928A1

Автор: Robert L. Sankman, Sanka Ganesan

Принадлежит: Intel Corp

Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.

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Номер записи: 29

04-01-2018 дата публикации

Lead-Free Solder Ball

Номер: US20180005970A1

Автор: Hikaru Nomura, Ken Tachibana, Shunsaku Yoshikawa, Yoshie Yamanaka

Принадлежит: Senju Metal Industry Co Ltd

A lead-free solder ball is provided which suppresses interfacial peeling in a bonding interface of a solder ball, fusion defects which develop between the solder ball and solder paste, and which can be used both with Ni electrodes plated with Au or the like and Cu electrodes having a water-soluble preflux applied atop Cu. The lead-free solder ball for electrodes of BGAs or CSPs consists of 1.6-2.9 mass % of Ag, 0.7-0.8 mass % of Cu, 0.05-0.08 mass % of Ni, and a remainder of Sn. It has excellent resistance to thermal fatigue and to drop impacts regardless of the type of electrodes of a printed circuit board to which it is bonded, which are Cu electrodes or Ni electrodes having Au plating or Au/Pd plating as surface treatment.

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Номер записи: 30

04-01-2018 дата публикации

Bumped land grid array

Номер: US20180005971A1

Автор: Ah Ron Lee, Deog Soon Choi, Hyon Mo Ku

Принадлежит: Avago Technologies General IP Singapore Pte Ltd

A semiconductor package and methods for producing the same are described. One example of the semiconductor package is described to include a substrate having a first face and an opposing second face. The package is further described to include a plurality of solderable surfaces formed on the first face of the substrate, a first solderable surface in the plurality of solderable surfaces having a pattern plating structure on an outward facing surface of the first solderable surface. There may also be an amount of solder bonded to the outward facing surface of the first solderable surface, where the pattern plating structure on the outward facing surface of the first solderable surface causes the amount of solder to have a first thickness at its ends, a second thickness at its center, and a discrete transition between the first thickness and the second thickness.

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Номер записи: 31

04-01-2018 дата публикации

Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over a Temporary Substrate

Номер: US20180006008A1

Автор: Chen Kang, Lin Yaojian

Принадлежит: STATS ChipPAC Pte. Ltd.

A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a first interconnect structure over the substrate;disposing a first semiconductor die over the first interconnect structure;disposing the substrate over a carrier with the first semiconductor die oriented away from the carrier;depositing an encapsulant over the carrier, substrate, and first semiconductor die;forming a second interconnect structure over the encapsulant and semiconductor die; andremoving the substrate to expose the first interconnect structure after forming the second interconnect structure.2. The method of claim 1 , further including forming a conductive column over the first interconnect structure.3. The method of claim 2 , wherein the conductive column extends from the first interconnect structure to the second interconnect structure ...

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Номер записи: 32

03-01-2019 дата публикации

Platform with thermally stable wireless interconnects

Номер: US20190006298A1

Автор: Adel A. Elsherbini, Brandon M. Rawlings, Feras Eid, Georgios C. Dogiamis, Sasha N. OSTER, Telesphor Kamgaing

Принадлежит: Intel Corp

Embodiments of the invention may include a packaged device that includes thermally stable radio frequency integrated circuits (RFICs). In one embodiment the packaged device may include an integrated circuit chip mounted to a package substrate. According to an embodiment, the package substrate may have conductive lines that communicatively couple the integrated circuit chip to one or more external components. One of the external components may be an RFIC module. The RFIC module may comprise an RFIC and an antenna. Additional embodiments may also include a packaged device that includes a plurality of cooling spots formed into the package substrate. In an embodiment the cooling spots may be formed proximate to interconnect lines the communicatively couple the integrated circuit chip to the RFIC.

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Номер записи: 33

08-01-2015 дата публикации

DEVICE PACKAGING WITH SUBSTRATES HAVING EMBEDDED LINES AND METAL DEFINED PADS

Номер: US20150008578A1

Автор: Hlad Mark S., Lee Kyu Oh, Liu Yueli, Roy Mihir K., Salama Islam A., Wu Tao

Принадлежит:

Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing. 1. A method of forming an integrated circuit (IC) package substrate , the method comprising:laminating a first dielectric layer over a first metal feature;laser drilling a via in the dielectric layer to expose the first metal feature;laminating a permanent photodefinable layer over the first dielectric layer;patterning a pad into the permanent photodefinable layer, the pad disposed over the via;electrolytically plating a fill metal into the via and the pad;planarizing the fill metal to a top surface of the permanent photodefinable layer; andperforming a self-aligned plating of a surface finish metal over a top surface of the fill metal.2. The method of claim 1 , wherein filling the pad and via further comprises:depositing a catalyst on the permanent photodefinable layer;electrolessly plating a seed layer on the catalyst; andwherein the method further comprises removing the catalyst, with a wet chemical treatment, from the permanent photodefinable layer that is exposed when the fill metal is planarized.3. The method of claim 2 , wherein plating a surface finish metal over the fill metal further comprises: forming a catalyst on an exposed surface of the fill metal and plating one or more metal layers.4. A method of forming an integrated circuit (IC) package substrate claim 2 , the method comprising:laminating a first dielectric layer over a first metal feature;laser drilling a via in the dielectric layer to expose the first metal feature;laser patterning a trace in the dielectric laterally ...

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Номер записи: 34

08-01-2015 дата публикации

Package-on-Package Process for Applying Molding Compound

Номер: US20150008581A1

Автор: Bor-Ping Jang, Chih-Wei Lin, Chun-Cheng Lin, Chung-Shi Liu, Hsiu-Jen Lin, Kuei-Wei Huang, Meng-Tse Chen, Ming-Da Cheng, Sheng-Yu Wu, Wei-Hung Lin, Wen-Hsiung LU, Yu-Peng Tsai

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method of packaging includes placing a package component over a release film, wherein solder regions on a surface of the package component are in physical contact with the release film. Next, A molding compound filled between the release film and the package component is cured, wherein during the step of curing, the solder regions remain in physical contact with the release film.

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Номер записи: 35

09-01-2020 дата публикации

Substrate design for semiconductor packages and method of forming same

Номер: US20200013635A1

Автор: Chen-Hua Yu, Chien-Hsiun Lee, Jung Wei Cheng, Mirng-Ji Lii, Tsung-Ding Wang

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of connectors on a surface of the one or more RDLs and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate comprises a cavity, and the second die is at least partially disposed in the cavity.

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Номер записи: 36

21-01-2016 дата публикации

Multi-layer package with integrated antenna

Номер: US20160020165A1

Автор: Adel A. Elsherbini, Telesphor Kamgaing, Torrey W. Frank

Принадлежит: Intel Corp

Embodiments of the present disclosure describe a multi-layer package with antenna and associated techniques and configurations. In one embodiment, an integrated circuit (IC) package assembly includes a first layer having a first side and a second side disposed opposite to the first side a second layer coupled with the first side of the first layer, one or more antenna elements coupled with the second layer and a third layer coupled with the second side of the first layer, wherein the first layer is a reinforcement layer having a tensile modulus that is greater than a tensile modulus of the second layer and the third layer. Other embodiments may be described and/or claimed.

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Номер записи: 37

03-02-2022 дата публикации

Semiconductor device package and method of manufacturing the same

Номер: US20220037244A1

Автор: Li-Hua TAI, Wen-Pin Huang

Принадлежит: Advanced Semiconductor Engineering Inc

The present disclosure provides a semiconductor device package. The semiconductor device package includes a first substrate and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface of the first substrate. The second substrate has a first surface facing the first substrate and a second surface opposite to the first surface of the second substrate. The semiconductor device package also includes a first electronic component disposed on the first surface of the second substrate and electrically connected to the first surface of the second substrate. The semiconductor device package also includes a first encapsulant and a second encapsulant between the first substrate and the second substrate. The first encapsulant is different from the second encapsulant. A method of manufacturing a semiconductor device package is also disclosed.

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Номер записи: 38

18-01-2018 дата публикации

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

Номер: US20180019191A1

Автор: Katkar Rajesh, Uzoh Cyprian Emeka

Принадлежит: INVENSAS CORPORATION

A solder connection may be surrounded by a solder locking layer () and may be recessed in a hole () in that layer. The recess may be obtained by evaporating a vaporizable portion () of the solder connection. Other features are also provided. 1. A manufacturing method comprising: one or more first components each of which comprises solder and a material sublimatable or vaporizable when the solder is melted; and', 'a first layer comprising a top surface and one or more holes in the top surface, each hole containing at least a segment of a corresponding first component;, 'obtaining a first structure comprisingheating each first component to sublimate or vaporize at least part of each sublimatable or vaporizable material and provide an electrically conductive connection at a location of each first component;wherein in the heating operation at least part of each first component recedes down from the top surface to provide or increase a recess in each hole at the top surface.2. The method of wherein each hole is a through-hole.3. The method of wherein each hole's sidewall is a dielectric sidewall.4. The method of wherein the first layer is dielectric.5. The method of wherein the first layer is formed by molding.6. The method of further comprising:obtaining a second structure with one or more protruding conductive posts; andinserting each conductive post into a corresponding recess provided or increased in the heating operation, and forming a solder bond in each recess between the corresponding conductive post and the corresponding electrically conductive connection.7. The method of wherein before the heating operation claim 1 , at least a segment of each first component either:comprises of a solder core coated with the sublimatable or vaporizable material; orconsists of the sublimatable or vaporizable material.8. The method of wherein in obtaining the first structure claim 7 , the one or more first components are formed before the first layer.9. The method of wherein in ...

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Номер записи: 39

18-01-2018 дата публикации

INTEGRATED CIRCUIT PACKAGE ASSEMBLY

Номер: US20180019229A1

Автор: Chen Hsien-Wei

Принадлежит:

An integrated circuit package assembly includes a first integrated circuit package and a second integrated circuit package. The first integrated circuit package includes a first integrated circuit die mounted on a first substrate. The second integrated circuit package includes a second integrated circuit die mounted on a second substrate. The second integrated circuit package is disposed under the first integrated circuit package. Solder bumps are disposed between the first integrated circuit package and the second integrated circuit package and provide electrical signal connections between the first integrated circuit die and the second integrated circuit die. A buffer layer is disposed between the first substrate and the second integrated circuit die to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package. 1. An integrated circuit package assembly , comprising:a first integrated circuit package including a first integrated circuit die mounted on a first substrate;a second integrated circuit package including a second integrated circuit die mounted on a second substrate, the second integrated circuit package being disposed under the first integrated circuit package;solder bumps disposed between the first integrated circuit package and the second integrated circuit package providing electrical signal connections between the first integrated circuit die and the second integrated circuit die; anda buffer layer disposed between the first substrate and the second integrated circuit die to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package.2. The integrated circuit package assembly of claim 1 , wherein the buffer layer is configured to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package without providing electrical connections.3. The integrated circuit package assembly of claim 2 ...

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Номер записи: 40

16-01-2020 дата публикации

INTERPOSER FRAME AND METHOD OF MANUFACTURING THE SAME

Номер: US20200020674A1

Автор: WU Jiun Yi

Принадлежит:

Some embodiments relate to a package. The package includes a first substrate, a second substrate, and an interposer frame between the first and second substrates. The first substrate has a first connection pad disposed on a first face thereof, and the second substrate has a second connection pad disposed on a second face thereof. The interposer frame is arranged between the first and second faces and generally separates the first substrate from the second substrate. The interposer frame includes a plurality of through substrate holes (TSHs) which pass entirely through the interposer frame. A TSH is aligned with the first and second connection pads, and solder extends through the TSH to electrically connect the first connection pad to the second connection pad. 1. A package comprising:a first substrate comprising a first plurality of connectors; an interposer substrate having a plurality of through substrate holes (TSHs) which are aligned with the first plurality of connectors, respectively, and having an opening whose width is greater than a width of each TSH of the plurality of TSHs, wherein the interposer substrate is made of a base material and at least one additive and the at least one additive adjusts a strength and a coefficient of thermal expansion of the interposer substrate; and', 'a conductive layer lining sidewalls of each TSH of the plurality of TSHs, the conductive layer filling less than an entirety of each TSH;, 'an interposer frame arranged over the first substrate, the interposer frame comprisinga semiconductor die arranged in the opening in the interposer substrate; anda second substrate arranged over the interposer frame and electrically connected to the first plurality of connectors, wherein a conductive structure extends through at least one TSH of the plurality of TSHs to electrically connect the second substrate to a connector of the first plurality of connectors.2. The package of claim 1 , wherein the conductive structure includes solder to ...

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Номер записи: 41

28-01-2016 дата публикации

Semiconductor device having single layer substrate and method

Номер: US20160027753A1

Автор: Byong Jin Kim, Gi Jeong Kim, Hyung Il Jeon, Jae Min Bae, Tae Ki Kim

Принадлежит: Amkor Technology Inc

In one embodiment, a semiconductor device includes a single layer substrate having an insulation layer and conductive patterns on a first surface of the insulation layer. A semiconductor die is attached on a first surface of the single layer substrate and electrically connected to the conductive patterns. Conductive bumps are also on the first surface of the single layer substrate and electrically connected to the semiconductor die through the conductive patterns. An encapsulant overlaps at least portions of the first surface of the single layer substrate. The conductive bumps are at least partially exposed in the encapsulant.

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Номер записи: 42

25-01-2018 дата публикации

3D Semiconductor Package Interposer with Die Cavity

Номер: US20180026008A1

Автор: Chen Kim Hong, Hou Shang-Yun, Huang Szu-Po, Hung Wensen, Jeng Shin-Puu

Принадлежит:

Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects. 1. A device , comprising:a substrate having a top surface;an interposer over the top surface of the substrate, the interposer being connected to the substrate by first interconnects;a first integrated circuit die connected to a first side of the interposer by first connectors;a second integrated circuit die connected to a second side of the interposer opposite the first side by second connectors, the second integrated circuit die having a smaller footprint than the interposer; anda fan-out structure disposed over a top surface of the interposer and extending beyond outermost edges of the interposer, wherein the fan-out structure is electrically connected to second interconnects, the second interconnects in contact with the top surface of the substrate.2. The device of claim 1 , further comprising third connectors connecting the fan-out structure to the second integrated circuit die.3. The device of claim 1 , further comprising a cavity in the top surface of the substrate claim 1 , wherein the first integrated circuit die extends into the cavity.4. The device of claim 1 , further comprising:a first molding compound on sidewalls of the interposer, the first interconnects, and the second interconnects; anda second molding compound on the first molding compound, the fan-out structure, and the second integrated circuit die.5. The device of claim 1 , ...

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Номер записи: 43

25-01-2018 дата публикации

Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP

Номер: US20180026023A1

Автор: KANG Chen, Seung Wook Yoon, Yaojian Lin

Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.

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Номер записи: 44

10-02-2022 дата публикации

Semiconductor device with sealed semiconductor chip

Номер: US20220044987A9

Автор: Isao Ozawa

Принадлежит: Toshiba Memory Corp

A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.

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Номер записи: 45

10-02-2022 дата публикации

Pre-Plating of Solder Layer on Solderable Elements for Diffusion Soldering

Номер: US20220046792A1

Автор: Alexander Heinrich, Alexander Roth

Принадлежит: INFINEON TECHNOLOGIES AG

A pre-soldered circuit carrier includes a carrier having a metal die attach surface, a plated solder region on the metal die attach surface, wherein a maximum thickness of the plated solder region is at most 50 μm, the plated solder region has a lower melting point than the first bond pad, and the plated solder region forms one or more intermetallic phases with the die attach surface at a soldering temperature that is above the melting point of the plated solder region.

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Номер записи: 46

05-02-2015 дата публикации

MILLIMETER WAVE WAFER LEVEL CHIP SCALE PACKAGING (WLCSP) DEVICE

Номер: US20150035145A1

Автор: DING Hanyi, Graf Richard S., Hill Gary R., JR. Wayne H., Woods

Принадлежит:

Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad. 1. A wafer level chip scale package (WLCSP) structure comprising:a printed circuit board (PCB) trace connection including at least one ground connection connected with a PCB ground plane;a set of ground pillars each contacting the printed circuit board trace connection;a set of chip pads contacting each of the ground pillars in the set of ground pillars;a chip ground plane connecting the set of chip pads; and a signal trace connection electrically isolated from the PCB ground plane;', 'a signal pillar contacting the signal trace connection;', 'a chip pad contacting the signal pillar; and', 'a signal trace connection on a chip contacting the chip pad., 'a signal interconnect interposed between two of the set of ground pillars, the signal interconnect including2. The WLCSP structure of claim 1 , wherein each of the ground pillars includes:a pillar section contacting a corresponding chip pad in the set of chip pads; anda solder joint contacting the pillar section and the printed circuit board trace connection.3. The WLCSP structure of claim 1 , wherein the signal trace connection electrically ...

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Номер записи: 47

02-02-2017 дата публикации

Semiconductor package and method of manufacturing the same

Номер: US20170033039A1

Автор: Eung Suek Lee, Jae Hyun Lim, Jin Su Kim, Jun Woo MYUNG, Ki Ju Lee, No Il PARK

Принадлежит: Samsung Electro Mechanics Co Ltd

A semiconductor package includes a first substrate, a pattern layer disposed on the first substrate, a first chip member disposed on a surface of the first substrate, lead frames mounted on the first substrate surrounding the first chip member, and a first encapsulation layer disposed on the first substrate, encapsulating the first chip member and the lead frame, wherein upper end portions of the lead frame and the first encapsulation layer are removed, and lead frame columns are exposed through the first encapsulation layer.

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Номер записи: 48

04-02-2016 дата публикации

SEMICONDUCTOR TSV DEVICE PACKAGE FOR CIRCUIT BOARD CONNECTION

Номер: US20160035693A1

Автор: Graf Richard S., West David J.

Принадлежит:

An electronic device includes a circuit board and a semiconductor device package. The semiconductor device package includes a laminate layer. The semiconductor device package includes a semiconductor die having an active side, an inactive side opposite the active side, and through-silicon vias (TSVs) conductively connecting the active side to the inactive side and conductively connecting the semiconductor die to one of the laminate layer and the circuit board. The semiconductor device package includes a laminate layer having a side attached to the active side or the inactive side semiconductor die. The semiconductor device package includes solder balls at the side of the laminate layer attached to the semiconductor die, around the semiconductor die, and attached to the circuit board. 1. A method comprising:preparing a semiconductor die having an active side, an inactive side opposite the active side, and a plurality of through-silicon vias (TSVs) conductively connecting the active side to the inactive side;attaching a laminate layer to the semiconductor die; andattaching a circuit board to the semiconductor die.2. The method of claim 1 , wherein the laminate layer is attached to the semiconductor die before the circuit board is attached to the semiconductor die claim 1 ,wherein attaching the laminate layer to the semiconductor die comprises employing a plurality of solder bumps to attach a side of the laminate layer to the active side of the semiconductor die, employing a plurality of solder balls at the side of the laminate layer attached to the semiconductor die, around the semiconductor die, to attach laminate layer to the circuit board; and', 'employing solder paste to attach the circuit board to the inactive side of the semiconductor at which the TSVs are exposed., 'and wherein attaching the circuit board to the semiconductor die includes attaching the circuit board to the laminate layer and comprises3. The method of claim 1 , wherein the laminate layer is ...

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Номер записи: 49

04-02-2021 дата публикации

Semiconductor device package and method for manufacturing the same

Номер: US20210035899A1

Автор: Hsin Hsiang WANG, Hung-Jung Tu, Min Lung Huang

Принадлежит: Advanced Semiconductor Engineering Inc

A semiconductor device package includes a conductive layer, a first conductive pillar, a circuit layer and a second conductive pillar. The conductive layer has a first surface. The first conductive pillar is disposed on the first surface of the conductive layer. The circuit layer is disposed over the conductive layer. The circuit layer has a first surface facing the conductive layer. The second conductive pillar is disposed on the first surface of the circuit layer. The first conductive pillar is physically spaced apart from the second conductive pillar and electrically connected to the second conductive pillar.

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Номер записи: 50

04-02-2021 дата публикации

Semiconductor package having discrete antenna device

Номер: US20210036405A1

Автор: Che-Hung KUO, Che-Ya Chou, Fu-Yi Han, Hsing-Chih Liu, Min-Chen Lin, Nan-Cheng Chen, Wen-Chou Wu

Принадлежит: MediaTek Inc

One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.

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Номер записи: 51

12-02-2015 дата публикации

METHOD FOR FABRICATING MULTI-CHIP STACK STRUCTURE

Номер: US20150044821A1

Автор: Chang Chin-Huang, Chang Yi-Feng, Huang Jung-Pin, Liu Chung-Lun

Принадлежит:

A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficultly. 1. A method for fabricating a multi-chip stack structure , comprising:disposing a first chip group comprising a plurality of first chips on a chip carrier in a step-like manner, disposing a second chip on the first chip on top of the first chip group, wherein the first and second chips are electrically connected to the chip carrier through bonding wires;stacking a third chip on the first chip group and the second chip with an insulative film provided therebetween, the insulative film covering part of the ends of the bonding wire of the first chip on the top of the first chip group and at least part of the second chip; andelectrically connecting the third chip with the chip carrier through bonding wires.2. The method of claim 1 , wherein planar size of the second chip is smaller than that of the first chip.3. The method of claim 1 , wherein the first and third chips are memory chips claim 1 , and the second chip is a controller ...

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Номер записи: 52

19-02-2015 дата публикации

Integrated circuit package having surface-mount blocking elements

Номер: US20150050777A1

Автор: Chua Ching Chua Edgardo L., Zeta Ruben C.

Принадлежит: MAXIM INTEGRATED PRODUCTS, INC.

A first cavity-down ball grid array (BGA) package includes a substrate member and an array of bond balls. The array of bond balls includes a pair of parallel extending rows of outer mesh bond balls and a row of inner signal bond balls that is parallel to the pair of rows of outer mesh bond balls. A surface-mount blocking element is disposed between the row of inner signal bond balls and the pair of rows of outer mesh bond balls. The surface-mount blocking element is either a passive or an active component of the BGA package. In one example, the first cavity-down BGA package is surface-mounted to a second cavity-down BGA package to form a package-on-package (POP) security module. The surface-mount blocking element provides additional physical barrier against the probing of the inner signal bond balls. Sensitive data is therefore protected from unauthorized access. 1. A method comprising:(a) providing a first cavity-down Ball Grid Array (BGA) package having a substrate member and an array of bond balls, wherein the array of bond balls includes a pair of parallel extending rows of outer mesh bond balls and a row of inner signal bond balls that is parallel to the pair of rows of outer mesh bond balls, wherein each of the bond balls has a diameter, and wherein the distance between the row of inner signal bond balls and the pair of rows of outer mesh bond balls is less than five times the diameter of the bond balls;(b) providing a second cavity-down BGA package having a substrate member and a surface-mount blocking element; and(c) surface-mounting the first BGA package to the substrate member of the second BGA package such that the surface-mount blocking element is disposed between the pair of rows of outer mesh bond balls and the row of inner signal bond balls.2. The method of claim 1 , wherein step (b) involves attaching the surface-mount blocking element to the substrate member of the second BGA package.3. The method of claim 1 , wherein the substrate member of the ...

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Номер записи: 53

16-02-2017 дата публикации

Package structure and the method to fabricate thereof

Номер: US20170047273A1

Автор: Bau-Ru Lu, Jeng-Jen Li, KAIPENG CHIANG, Kun-Hong SHIH

Принадлежит: Cyntec Co Ltd

The invention discloses a package structure made of the combination of a device carrier and a modifiable substrate. In one embodiment, a recess is formed in the device carrier and a conductive element is disposed on the substrate, wherein the substrate is disposed on the device carrier and the conductive element is located in the recess of the device carrier. The conductive pattern in the substrate is electrically connected to the device carrier and I/O terminals of the first conductive element. The invention also discloses a method for manufacturing a package structure made of the combination of a device carrier and a modifiable substrate. In one embodiment, a portion of the conductive pattern in the substrate can be modified.

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Номер записи: 54

15-02-2018 дата публикации

MULTI-CHIP PACKAGE WITH INTERCONNECTS EXTENDING THROUGH LOGIC CHIP

Номер: US20180047704A1

Автор: Haba Belgacem

Принадлежит:

A microelectronic package includes a first microelectronic element comprising logic circuitry which is flip-chip mounted to a substrate, the substrate having terminals for connection with a circuit panel or other external component. A second microelectronic element overlies a rear surface of the first microelectronic element and has contacts electrically coupled with the substrate through electrically conductive interconnects extending through a region of the first microelectronic element. A heat spreader is thermally coupled with the rear surface of the substrate, either directly or through an additional element overlying the rear surface. Additional contacts of the second microelectronic element may be coupled with contacts of the substrate through electrically conductive structure disposed beyond an edge surface of the first microelectronic element. 1. A microelectronic package , comprising:a substrate having first and second oppositely-facing surfaces, a plurality of substrate contacts at the first surface and a plurality of terminals at the second surface;a first microelectronic element having a front surface and first contacts at its front surface, a rear surface opposite the front surface, a semiconductor region between the front and rear surfaces, and electrically conductive interconnects extending through the semiconductor region in a direction from the rear surface to the front surface, the first contacts facing and joined with the substrate contacts;a second microelectronic element having a front surface and second contacts at its front surface, the front surface and the second contacts of the second microelectronic element partially overlying the rear surface of the first microelectronic element,wherein the second contacts are electrically coupled with the substrate contacts through the interconnects, andat least a portion of the rear surface of the first microelectronic element is uncovered by the second microelectronic element.2. The microelectronic ...

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Номер записи: 55

15-02-2018 дата публикации

Semiconductor Packaging Structure and Method

Номер: US20180047708A1

Автор: Chen Cheng-Ting, Cheng Ming-Da, Huang Kuei-Wei, Lin Chun-Cheng, Lin Wei-Hung, Liu Chung-Shi

Принадлежит:

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections. 1. A semiconductor device comprising:a first external conductive connector in physical contact with a first post-contact material over a first underbump metallization over a first contact of a first package; anda second package over the first package, wherein the first external conductive connector extends away from the first package a first distance, the second package extends away from the first package a second distance, the second distance being parallel to and less than the first distance, and wherein the second package comprises a second conductive connector in physical contact with a second underbump metallization.2. The semiconductor device of claim 1 , wherein the first external conductive connector comprises a solder material.3. The semiconductor device of claim 1 , wherein the first post-contact material has a thickness of between about 10 μm and about 200 μm.4. The semiconductor device of claim 1 , wherein the second package comprises a semiconductor die.5. The semiconductor device of claim 1 , wherein the second conductive connector comprises solder.6. The semiconductor device of claim 5 , wherein the second package comprises a copper pillar is physical contact with the second conductive connector.7. A semiconductor device comprising:a post contact material located on a first set of a first plurality of package contacts on a first side of a first package;a second package with external connections bonded directly to a second set of the first plurality of package contacts, the second package comprising a first surface facing away from ...

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Номер записи: 56

15-02-2018 дата публикации

Package-On-Package (PoP) Structure Including Stud Bulbs

Номер: US20180047709A1

Автор: Cheng Ming-Da, Lii Mirng-Ji, Liu Chung-Shi, Yu Chen-Hua

Принадлежит:

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. 1. A device comprising:a first pad on a first surface of a first substrate;a second pad on a second surface of a second substrate;a metallic element interposed between the first pad and the second pad, the metallic element electrically coupled to the first pad, the metallic element comprising a base portion and an elongated portion extending from the base portion toward the second pad;a solder connector in contact with the elongated portion and electrically coupled to the second pad; andan inter-metallic compound (IMC) between the elongated portion and the solder connector.2. The device of claim 1 , further comprising a protection layer extending over the base portion and the elongated portion.3. The device of claim 1 , further comprising a die attached to the first substrate adjacent the metallic element.4. The device of claim 3 , wherein a height of the metallic element from the first substrate is greater than a height of the die from the first substrate.5. The device of claim 1 , wherein the metallic element comprises a copper wire.6. The device of claim 1 , wherein the base portion and the elongated portion comprises a single continuous element.7. A device comprising:a first substrate having a first pad;a second substrate having a second pad;a first connector interposed between the first pad and the second pad, the first connector having a first wide portion and a second elongated portion, the first wide portion being ...

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Номер записи: 57

06-02-2020 дата публикации

BLADE COMPUTING SYSTEM WITH WIRELESS COMMUNICATION BETWEEN BLADES WITHIN A BLADE ENCLOSURE

Номер: US20200045754A1

Автор: Kamgaing Telesphor, Khanna Rahul

Принадлежит:

A blade computing system is described with a wireless communication between blades. In one embodiment, the system includes a first blade in the enclosure having a radio transceiver to communicate with a radio transceiver of a second blade in the enclosure. The second blade has a radio transceiver to communicate with the radio transceiver of the first blade. A switch in the enclosure communicates with the first blade and the second blade and establishes a connection through the respective radio transceivers between the first blade and the second blade. 1. (canceled)2. An apparatus comprising:a blade enclosure;a first blade and a second blade in the enclosure, the first blade having a radio transceiver to communicate with a radio transceiver of the second blade, and the second blade having a radio transceiver to communicate with the radio transceiver of the first blade; anda third blade in the enclosure, the third blade comprising a switch to communicate with the first blade and the second blade and to establish a direct connection through the respective radio transceivers between the first blade and the second blade, wherein the switch establishes the direct connection by assigning a direct radio path between the first blade and the second blade.3. The apparatus of claim 2 , wherein the switch establishes the connection by activating the respective radio transceivers.4. The apparatus of claim 2 , wherein the first blade comprises a processor package including a processor and the radio transceiver.5. The apparatus of claim 2 , wherein the first blade comprises a motherboard having a front side and a back side and a processor claim 2 , wherein the radio transceiver and the processor are attached to the front side claim 2 , the first blade further comprising a second radio transceiver attached to the back side of the motherboard to communicate with another blade without communicating with the switch.6. The apparatus of claim 5 , wherein the second blade comprises a ...

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Номер записи: 58

26-02-2015 дата публикации

RIGID WAVE PATTERN DESIGN ON CHIP CARRIER SUBSTRATE AND PRINTED CIRCUIT BOARD FOR SEMICONDUCTOR AND ELECTRONIC SUB-SYSTEM PACKAGING

Номер: US20150054177A1

Автор: Chen Han-Shiao, Chiu Chin-Tien, Liao Chih-Chin, Takiar Hem, Wang Ken Jian Ming, Yu Cheeman

Принадлежит: SANDISK TECHNOLOGIES INC.

A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking. 1. A substrate for supporting and electrically connecting to a semiconductor dice , the substrate including a first surface supporting the semiconductor die and a second surface opposite the first surface , the second surface including portions defining a planar surface and a patterned area recessed within the planar surface , the substrate comprising:a first pattern on the first surface of the substrate, the first pattern aligning with the patterned area, the first pattern comprising:an etched portion within a footprint of the aligned patterned area; andan unetched portion surrounding the etched portion, the first pattern reducing a mechanical stress generated by the patterned area on the semiconductor dice during a molding process.2. A substrate as recited in claim 1 , wherein the patterned area includes a contact finger for forming an external electrical connection.3. A substrate as recited in claim 2 , wherein the etched portion of the first pattern includes a pair of straight edges claim 2 , a distance between the straight edges being approximately equal to a width of the contact finger claim 2 , and a length of the straight edges being approximately equal to a length of the contact finger.4. A substrate as recited in claim 2 , wherein the etched portion of the first pattern includes two pair of etched sections claim 2 , each pair of etched sections including straight sections inclined toward each other from a middle of the etched portion to ...

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Номер записи: 59

03-03-2022 дата публикации

Semiconductor package including a redistribution structure

Номер: US20220068896A1

Автор: Yonghwan Kwon

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor package includes: a first wiring pattern; a dielectric layer that covers the first wiring pattern; a second wiring pattern on the dielectric layer, wherein the second wiring pattern includes a line part that extends in a first direction and a via part that connects the line part to the first wiring pattern; a pad pattern electrically connected to the second wiring pattern, wherein the pad pattern includes a connection part and an extension part, wherein the connection part covers a first surface of the line part of the second wiring pattern, and the extension part has a top surface at a level lower than a level of the top surface of the line part of the second wiring pattern; and a seed pattern between the extension part and the dielectric layer.

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Номер записи: 60

25-02-2016 дата публикации

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE THEREOF

Номер: US20160056055A1

Автор: Kim Do Hyung, Kim Dong Jin, Kim Jin Han, Ko Yeong Beom, Rinne Glenn

Принадлежит:

A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method for manufacturing a semiconductor device that comprises ordering and performing processing steps in a manner that prevents warpage deformation from occurring to a wafer and/or die due to mismatching thermal coefficients. 1. A method of manufacturing a semiconductor device , the method comprising:forming contact structures on a first surface of an interposer, where the interposer is on a surface of a substrate;coupling a wafer support system (WSS) on the first surface of the interposer and the contact structures;removing the substrate;coupling a semiconductor die to a second surface of the interposer opposite to the first surface of the interposer;encapsulating the second surface of the interposer and the semiconductor die with an encapsulant; andremoving the WSS.2. The method of claim 1 , comprising prior to said removing the WSS claim 1 , thinning the encapsulant to expose the semiconductor die.3. The method of claim 1 , comprising after said encapsulating claim 1 , forming a stiffener on at least the encapsulant.4. The method of claim 3 , wherein said forming a stiffener comprises forming the stiffener directly on at least the encapsulant without an intervening adhesive layer.5. The method of claim 3 , wherein said forming a stiffener comprises forming a multi-layer multi-material stiffener structure directly on at least the encapsulant.6. The method of claim 1 , comprising forming the interposer by claim 1 , at least in part:forming a dielectric layer comprising openings to the substrate; andforming a conductive layer in the openings to the substrate.7. The method of claim 1 , wherein the substrate comprises silicon and/or glass.8. The method of claim 1 , comprising:prior to said encapsulating and prior to said coupling a WSS, first encapsulating the first surface of the interposer and the contact ...

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Номер записи: 61

14-02-2019 дата публикации

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20190051590A1

Автор: FANG Jen-Kuang, Lu Wen-Long

Принадлежит: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

A semiconductor package device includes a circuit layer having a top surface, a first electronic component disposed on the top surface of the circuit layer, and a first conductive element disposed on the top surface of the circuit layer, the first conductive element having a top surface. The first electronic component has an active surface and a back surface facing the top surface of the circuit layer. A distance between the active surface of the first electronic component and the top surface of the circuit layer is greater than a distance between the top surface of the first conductive element and the top surface of the circuit layer. 1. A semiconductor package device , comprising:a circuit layer having a top surface;a first electronic component disposed on the top surface of the circuit layer, the first electronic component having an active surface and a back surface facing the top surface of the circuit layer;a first conductive element disposed on the top surface of the circuit layer, the first conductive element having a top surface; anda second electronic component disposed between the first electronic component and the circuit layer,wherein the second electronic component has an active surface facing the top surface of the circuit layer and a back surface facing the back surface of the first electronic component, andwherein a distance between the active surface of the first electronic component and the top surface of the circuit layer is greater than a distance between the top surface of the first conductive element and the top surface of the circuit layer.2. (canceled)3. The semiconductor package device of claim 1 , wherein a distance from the second electronic component to the first conductive element is in a range from 1.89 micrometer (μm) to 1432.2 μm.4. The semiconductor package device of claim 1 , further comprising a package body encapsulating the first electronic component and the first conductive element claim 1 , wherein the package body defines a ...

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Номер записи: 62

23-02-2017 дата публикации

SEMICONDUCTOR PACKAGE WITH PILLAR-TOP-INTERCONNECTION (PTI) CONFIGURATION AND ITS MIS FABRICATING METHOD

Номер: US20170053898A1

Автор: HSU Hung-Hsin, YEH YUN-HSIN

Принадлежит:

Disclosed is a semiconductor package with Pillar-Top-Interconnection (PTI) configuration, comprising a redistribution layer (RDL) formed on a carrier plane, a plurality of metal pillars disposed on the RDL, a chip bonded onto the RDL, and a molding core. The molding core is formed on the carrier plane and has a bottom surface defined by the carrier plane so that the RDL is embedded inside the molding core. The package thickness of the molding core is greater than the chip-bonding height of the chip so that the chip is completely embedded inside the molding core. The metal pillars are encapsulated at the peripheries of the molding core with a plurality of pillar top portions exposed from the molding core. The exposed pillar top portions are reentrant from a top surface of the molding core and uneven. Accordingly, it realizes the effects of ultra-thin and smaller footprint POP stacked assembly with fine pitch vertically electrical connections in POP structure. Also, it is possible to achieve zero spacing between POP stacked assembly. 1. A semiconductor package comprising:a first redistribution layer, the first redistribution layer including a plurality of first fan-in pads and a plurality of first fan-out pads;a plurality of first metal pillars disposed on the first fan-out pads;a first chip bonded onto the first redistribution layer and electrically connected to the first fan-in pads;a first molding core formed to encapsulate the first redistribution layer, the first metal pillars, and the first chip, the first molding core having a first bottom surface coplanar to a surface of the first redistribution layer and a first top surface, wherein the first top surface is a planar surface having first dimple holes, each of the first dimple holes configured to expose a first pillar top portion of one of the first metal pillars;a second redistribution layer disposed on the first top surface of the first molding core, the second redistribution layer including a plurality of ...

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Номер записи: 63

05-03-2015 дата публикации

Ball arrangement for integrated circuit package devices

Номер: US20150061128A1

Автор: Arun Ramakrishnan, Hongyu Li

Принадлежит: Broadcom Corp

An integrated circuit package includes a ball arrangement that includes transmitter contact pairs arranged in a first portion of a ball grid array disposed in the integrated circuit package. Each of the transmitter contact pairs include transmitter differential signal contacts. Pairs of the transmitter contact pairs located adjacent to one another are in a staggered arrangement. The ball arrangement also includes receiver contact pairs arranged in a second portion of the ball grid array. Each of the receiver contact pairs include receiver differential signal contacts. Pairs of the receiver contact pairs located adjacent to one another are in a staggered arrangement. The ball arrangement also includes voltage supply contacts arranged at least between every two pairs of the transmitter contact pairs and the receiver contact pairs.

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Номер записи: 64

05-03-2015 дата публикации

Chip arrangement and a method for manufacturing a chip arrangement

Номер: US20150061130A1

Автор: Thorsten Meyer

Принадлежит: Intel Mobile Communications GmbH

A chip arrangement may include: a first semiconductor chip having a first side and a second side opposite the first side; a second semiconductor chip having a first side and a second side opposite the first side, the second semiconductor chip disposed at the first side of the first semiconductor chip and electrically coupled to the first semiconductor chip, the first side of the second semiconductor chip facing the first side of the first semiconductor chip; an encapsulation layer at least partially encapsulating the first semiconductor chip and the second semiconductor chip, the encapsulation layer having a first side and a second side opposite the first side, the second side facing in a same direction as the second side of the second semiconductor chip; an interconnect structure disposed at least partially within the encapsulation layer and electrically coupled to at least one of the first and second semiconductor chips, wherein the interconnect structure may extend to the second side of the encapsulation layer; and a third semiconductor chip disposed at at least one of the second side of the second semiconductor chip and the second side of the encapsulation layer, the third semiconductor chip having a first side and a second side opposite the first side, the second side of the third semiconductor chip facing in the same direction as the second side of the second semiconductor chip and the second side of the encapsulation layer.

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Номер записи: 65

15-05-2014 дата публикации

Manufacturing methods of semiconductor substrate, package and device

Номер: US20140134806A1

Автор: Kian-Hock Lim, Shoa-Siong Lim

Принадлежит: ADVANPACK SOLUTIONS PTE LTD

A manufacturing method of semiconductor substrate includes following steps: providing a base layer; forming a plurality of traces on the base layer; forming a plurality of studs correspondingly on the traces; forming a molding material layer on the base layer to encapsulate the traces and studs; forming a concave portion on the molding material layer; and, removing the base layer.

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Номер записи: 66

05-03-2015 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

Номер: US20150061160A1

Автор: Asamura Norihiro, Ishino Takahiro

Принадлежит:

Disclosed is a semiconductor device in which, when two adjacent semiconductor chips are coupled with bonding wires, a short circuit between the adjacent bonding wires can be suppressed. A first bonding wire, a second bonding wire, a third bonding wire, and a fourth bonding wire are lined up in this order along a first side. When viewed from a direction perpendicular to a chip mounting part, a maximum of the space between the first bonding wire and the second bonding wire is larger than that of the space between the second bonding wire and the third bonding wire. Further, a maximum of the space between the second bonding wire and the third bonding wire is larger than that of the space between the third bonding wire and the fourth bonding wire. 1. A semiconductor device comprising:a first semiconductor chip that is a rectangle having a first side, a second side facing the first side, a third side, and a fourth side;a second semiconductor chip that is a rectangle having a fifth side, a sixth side facing the fifth side, a seventh side, and an eighth side;a chip mounting part, over the same surface of which the first semiconductor chip and the second semiconductor chip are mounted; anda plurality of bonding wires that couple the first semiconductor chip to the second semiconductor chip,wherein the first side of the first semiconductor chip faces the fifth side of the second semiconductor chip,wherein the first semiconductor chip has a plurality of first electrode pads arranged along the first side,wherein the second semiconductor chip has a plurality of second electrode pads arranged along the fifth side,wherein, of the bonding wires, a first bonding wire, a second bonding wire, a third bonding wire, and a fourth bonding wire are lined up in this order along the first side,wherein, when viewed from a direction perpendicular to the chip mounting part, a maximum of a space between the first bonding wire and the second bonding wire is larger than that of a space between the ...

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Номер записи: 67

21-02-2019 дата публикации

Semiconductor package and electronic device having the same

Номер: US20190057924A1

Автор: Eun Kyoung Kim, Jung Hyun Lim, Se Min JIN, Seung Goo JANG, Tae Hyun Kim

Принадлежит: Samsung Electro Mechanics Co Ltd

A semiconductor package includes a substrate including an antenna; a heating element disposed on a first surface of the substrate and connected to the antenna; a heat radiating part coupled to the heating element; and a signal transfer part disposed on the first surface of the substrate and configured to electrically connect the substrate to a main substrate. The heat radiating part may include a heat transfer part connected to the heating element and heat radiating terminals connecting the heat transfer part and the main substrate to each other.

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Номер записи: 68

20-02-2020 дата публикации

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20200058607A1

Автор: Chang Shou-Zen, CHUANG NAN-CHIN, Shih Chao-Wen, Wan Albert

Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A package structure include a ground plate, a semiconductor die, a molding compound, and an antenna element. The semiconductor die is located over the ground plate. The molding compound is located over the semiconductor die. The antenna element is located in the molding compound and overlaps with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound. The antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element. 1. A package structure , comprising:a ground plate;a semiconductor die, located over the ground plate;a molding compound, located over the semiconductor die; andan antenna element, located in the molding compound and overlapping with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound, wherein the antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element.2. The package structure of claim 1 , wherein the antenna element has a second side opposing the first side along the stacking direction and a third side connecting the first side and the second side claim 1 , and a portion of the second side and a portion of the third side overlapped with the ground plate are covered by the molding compound.3. The package structure of claim 2 , further comprising:a redistribution circuit structure, located on a second surface of the molding compound and electrically connected to the semiconductor die, the second surface being opposite to the first surface along the stacking direction, wherein the ground plate is a part of redistribution circuit structure, and the redistribution circuit structure is located between the semiconductor die and the molding compound.4. The package structure of claim 3 , further comprising:at least one ...

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Номер записи: 69

02-03-2017 дата публикации

UNIVERSAL BGA SUBSTRATE

Номер: US20170062320A1

Автор: Foong Chee Seng, Khoo Ly Hoon, Koh Wen Shi, Lo Wai Yew, Poh Zi Song, Yow Kai Yun

Принадлежит:

A universal substrate for assembling ball grid array (BGA) type integrated circuit packages has a non-conducting matrix, an array of conducting vias extending between top and bottom surfaces of the matrix, and one or more instances of each of two or more different types of fiducial pairs on the top surface of the matrix. Each instance of each different fiducial pair indicates a location of a different via sub-array of the substrate for a different BGA package of a particular package size. The same substrate can be used to assemble BGA packages of different size, thereby avoiding having to design a different substrate for each different BGA package size. 1. A substrate for ball grid array (BGA) packages , the substrate comprising:a non-conducting matrix having a top surface and a bottom surface;an array of conducting vias extending between the top and bottom surfaces of the matrix;one or more instances of a first fiducial pair on the top surface of the matrix, wherein each instance of the first fiducial pair indicates a location of a different via sub-array for a different BGA package of a first package size; andone or more instances of a second fiducial pair, different from the first fiducial pair, on the top surface of the matrix, wherein each instance of the second fiducial pair indicates a location of a different via sub-array for a different BGA package of a second package size different from the first package size.2. The substrate of claim 1 , wherein the via sub-array for at least one instance of the first fiducial pair overlaps the via sub-array for at least one instance of the second fiducial pair.3. The substrate of claim 1 , wherein the one or more instances of the first fiducial pair have a uniquely different design from the design of the one or more instances of the second fiducial pair.4. The substrate of claim 1 , wherein the matrix comprises multiple instances of the first fiducial pair that all have the same design.5. The substrate of claim 1 , ...

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Номер записи: 70

09-03-2017 дата публикации

BALL GRID ARRAY (BGA) APPARATUS AND METHODS

Номер: US20170066088A1

Автор: LIU Boxi, Mirpuri Kabir J., SOOD Mohit, Tan Wei, XU Huili

Принадлежит:

Embodiments herein may relate to an apparatus with a ball grid array (BGA) package that includes a plurality of solder balls of an off-eutectic material. In embodiments, the respective solder balls of the plurality of solder balls may form solder joints between a substrate of the BGA and a second substrate. In some embodiments the joints may be less than approximately micrometers from one another. Other embodiments may be described and/or claimed. 1. An apparatus comprising:a first substrate; anda ball grid array (BGA) package that includes a second substrate soldered to the first substrate via a plurality of solder balls comprising an off-eutectic material such that respective solder balls of the plurality of solder balls form respective joints between the first substrate and the second substrate, wherein a first joint of the respective joints is less than 0.6 micrometers from a second joint of the respective joints.2. The apparatus of claim 1 , wherein the off-eutectic material includes tin (Sn) and bismuth (Bi).3. The apparatus of claim 1 , wherein the first joint is an interior joint and a third joint of the respective joints is an edge joint claim 1 , and the first joint and third joint have an approximately equal height as measured from the first substrate to the second substrate.4. The apparatus of claim 3 , wherein the height of the first joint is greater than or equal to a height of one of the plurality of solder balls prior to a soldering process.5. The apparatus of claim 1 , wherein the off-eutectic material has a solidus temperature and a liquidus temperature that is higher than the solidus temperature.6. The apparatus of claim 5 , wherein the solidus temperature is a temperature at which the off-eutectic material transitions from a liquid to a solid while cooling.7. The apparatus of claim 6 , wherein the solidus temperature is between approximately 135 degrees Celsius and approximately 145 degrees Celsius.8. The apparatus of claim 5 , wherein the ...

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Номер записи: 71

17-03-2022 дата публикации

METHOD FOR CONVEYING HIGH FREQUENCY MODULE AND A HIGH-FREQUENCY MODULE

Номер: US20220084964A1

Автор: Koren Guy, Rubovitch Ben

Принадлежит:

A method and a high-frequency module that includes a high frequency die that may include multiple die pads; a substrate that may include a first buildup layer, a second buildup layer and a core that is positioned between the first buildup layer and a second buildup layer; a line card that may include multiple line card pads; and multiple conductors that pass through the substrate without reaching a majority of a depth of the core, and couple the multiple die pads to the multiple line card pads. 1. A method for conveying high-frequency signals between a line card and a high frequency die of a high frequency module , the method comprises:outputting a first high frequency signal from a first die pad of the high frequency die; andconveying the first high frequency signal through a first conductive path to a first line card pad of the line card; wherein the first conductive path passes through a substrate without reaching a majority of a depth of a core of the substrate.2. The method according to comprising: outputting a second high frequency signal from a second line card pad of the line card; and conveying the second high frequency signal through a second conductive path to a second die pad of the high frequency die; wherein the second conductive path passes through the substrate without reaching the majority of the depth of the core of the substrate.3. The method according to wherein the high frequency die comprises multiple die pads claim 1 , the line card comprises multiple line card pads claim 1 , and the high frequency module comprises multiple conductors that couple the multiple die pads to the multiple line card pads; wherein the multiple conductors pass through the substrate without reaching the majority of the depth of the core; wherein the multiple line card pads comprise the first line card pad; wherein the multiple die pads comprises the first die pad; and wherein the first conductive path comprises a first conductor that belongs to the multiple conductors. ...

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Номер записи: 72

08-03-2018 дата публикации

Electronic package and method for fabricating the same

Номер: US20180068870A1

Автор: Hsin-Long Chen, Jau-En Liang, Kuo-Ching Tsai

Принадлежит: Siliconware Precision Industries Co Ltd

The present disclosure provides an electronic package and a method for fabricating the same. The method including: connecting a first carrier structure with an electronic component via a bonding layer formed thereon; stacking the first carrier structure on a second carrier structure via a plurality of conductive elements; and electrically connecting the electronic component to the second carrier structure to thereby maintain and secure the distance between the first and second carrier structures.

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Номер записи: 73

11-03-2021 дата публикации

Chip package structure having warpage control and method of forming the same

Номер: US20210074602A1

Автор: Feng-Cheng Hsu, Shin-puu Jeng, Shuo-Mao Chen

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A package structure and a method of forming the same are provided. The package structure includes a package substrate, an interposer substrate, a first semiconductor device, a second semiconductor device, and a protective layer. The interposer substrate is disposed over the package substrate. The first semiconductor device and the second semiconductor device are disposed over the interposer substrate, wherein the first semiconductor device and the second semiconductor device are different types of electronic devices. The protective layer is formed over the interposer substrate to surround the first semiconductor device and the second semiconductor device. The second semiconductor device is exposed from the protective layer and the first semiconductor device is not exposed from the protective layer.

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Номер записи: 74

11-03-2021 дата публикации

SEMICONDUCTOR DEVICE WITH SEALED SEMICONDUCTOR CHIP

Номер: US20210074609A1

Автор: Ozawa Isao

Принадлежит: Toshiba Memory Corporation

A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires. 1. (canceled)2: A semiconductor device comprising:a resin;a first terminal group, which is located outside the resin and is provided on a first side; wherein a terminal at one end of the first terminal group is a first terminal, a terminal at another end is a second terminal, and a distance between the first terminal and the second terminal is a first distance,', 'a terminal at one end of the second terminal group and closer to the first terminal than the second terminal is a third terminal, a terminal at another end is a fourth terminal, and a distance between the third terminal and the fourth terminal is a second distance,', 'a distance between the first terminal and the third terminal is a third distance, the third distance being larger than the first distance and the second distance,', 'a distance between the second terminal and the fourth terminal is the fourth distance, the fourth distance being larger than the first distance and the second distance,', 'a fifth terminal, which is one terminal in the first terminal group, and a sixth terminal, which is one terminal in the second terminal group, are physically connected inside the resin via a center wiring; and, 'a second terminal ...

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Номер записи: 75

11-03-2021 дата публикации

INTERPOSER FRAME AND METHOD OF MANUFACTURING THE SAME

Номер: US20210074692A1

Автор: WU Jiun Yi

Принадлежит:

Some embodiments relate to a package. The package includes a first substrate, a second substrate, and an interposer frame between the first and second substrates. The first substrate has a first connection pad disposed on a first face thereof, and the second substrate has a second connection pad disposed on a second face thereof. The interposer frame is arranged between the first and second faces and generally separates the first substrate from the second substrate. The interposer frame includes a plurality of through substrate holes (TSHs) which pass entirely through the interposer frame. A TSH is aligned with the first and second connection pads, and solder extends through the TSH to electrically connect the first connection pad to the second connection pad. 1. A package comprising:a first substrate comprising a first plurality of connectors; an interposer substrate having a plurality of through substrate holes (TSHs) which are aligned with the first plurality of connectors, respectively, and having an opening whose width is greater than a width of each TSH of the plurality of TSHs, wherein the interposer substrate is made of a base material and at least one additive and the at least one additive adjusts a strength and a coefficient of thermal expansion of the interposer substrate; and', 'a conductive layer lining sidewalls of each TSH of the plurality of TSHs, the conductive layer filling less than an entirety of each TSH., 'an interposer frame arranged over the first substrate, the interposer frame comprising2. The package of claim 1 , wherein a pitch at which the plurality of TSHs are spaced is in a range from about 75 μm to about 500 μm; and wherein each TSH of the plurality of TSHs has a width in a range from about 50 μm to about 200 μm.3. The package of claim 1 , wherein the plurality of TSHs each pass entirely through a periphery region of the interposer substrate and collectively surround a central region of the interposer substrate in which the opening is ...

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Номер записи: 76

05-06-2014 дата публикации

Wireless module

Номер: US20140151860A1

Автор: Hirokazu Kitamura, Jun'ichi KIMURA, Maki Nakamura, Ryosuke Shiozaki, Suguru Fujita, Toshiaki Nakamura

Принадлежит: Panasonic Corp

A wireless module includes a first board which has a first component mounted thereon, a second board which faces the first board and has a second component mounted thereon, a connecting member which is provided between the first board and the second board and transmits a signal between the first board and the second board, and a filling material with which a space between the first board and the second board including the connecting member is sealed. A conductive member for connecting a ground between the first board and the second board is arranged in a periphery of the connecting member.

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Номер записи: 77

19-03-2015 дата публикации

Millimeter band transmitting/receiving system

Номер: US20150079912A1

Автор: Alexandre Siligaris, Cedric Dehos, Laurent Dussopt, PIERRE Vincent

Принадлежит: Commissariat a lEnergie Atomique et aux Energies Alternatives CEA

In the field of millimeter band transmitting/receiving systems for a high-speed contactless transmission, an architecture is provided with a common processing circuit supplying modulation signals and a plurality of transmitting/receiving integrated circuits, all identical to one another, receiving these signals, and also a common clock. The transmitting/receiving integrated circuits each comprise: an oscillator locked with the clock signal to produce a carrier frequency, a transmit channel comprising a first controllable phase shift circuit, a frequency transposition to the carrier frequency, and a power amplifier, a receive channel comprising a low noise amplifier, a frequency transposition from the carrier frequency, and a second controllable phase shift circuit. An antenna is associated with each transmitting/receiving circuit.

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Номер записи: 78

15-03-2018 дата публикации

Tin-zinc microbump structures and method of making same

Номер: US20180076119A1

Автор: Amanda E. Schuckman, Kyu Oh Lee, Sri Chaitra J. Chavali

Принадлежит: Intel Corp

Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes a combination of tin and zinc that mitigates precipitation of residual copper by promoting the formation of miconstituents in the microbump. In another embodiment, the microbump has a mass fraction of zinc, or a mass fraction of tin, that is different in various regions along a height of the microbump.

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Номер записи: 79

05-03-2020 дата публикации

FAN-OUT ANTENNA PACKAGING STRUCTURE AND PREPARATION THEREOF

Номер: US20200075515A1

Автор: Chen Yenheng, Lin Chengchung, LIN Jangshen, Wu Chengtar

Принадлежит:

A method for preparing fan-out antenna packaging structure, includes: providing a carrier and a release layer structure; forming a single-layer antenna structure and a redistribution layer on an upper surface of the release layer; disposing a semiconductor chip electrically connected with the redistribution layer; forming a leading-out conducting wire on the redistribution layer at least on one side of the semiconductor chip; forming a plastic packaging layer wrapping the chip and the leading-out conducting wire; removing part of the plastic packaging layer to expose the chip and the leading-out conducting wire; forming an under-bump metal layer and a solder ball bump on an upper surface of the plastic packaging layer; removing the carrier and the release layer to expose the single-layer antenna structure; soldering a substrate on the solder ball bump; and forming a layer of cooling fins on a second surface of the semiconductor chip. 1. A fan-out antenna packaging structure , comprising:a single-layer antenna structure;a redistribution layer formed on a bottom surface of the single-layer antenna structure;one semiconductor chip formed on a bottom surface of the redistribution layer, wherein the semiconductor chip comprises a first surface and a second surface opposite to the first surface, wherein the first surface of the semiconductor chip sits on and is electrically connected with the redistribution layer;a leading-out conducting wire formed on and electrically connected to the bottom surface of the redistribution layer at least on one side of the semiconductor chip;a plastic packaging layer formed on the bottom surface of the redistribution layer and wrapping around the semiconductor chip and the leading-out conducting wire;an under-bump metal layer formed on a bottom surface of the plastic packaging layer and electrically connected with the leading-out conducting wire;a solder ball bump formed on a bottom surface of the under-bump metal layer;a substrate formed ...

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Номер записи: 80

22-03-2018 дата публикации

Circuit pin positioning structure, fabrication method of soldered circuit elements, and method of forming circuit pins of a stacked package

Номер: US20180082974A1

Автор: Mu-Jung Huang, Tsung-Chi Chen

Принадлежит: Tarng Yu Enterpries Co Ltd

The invention provides a circuit pin positioning structure, a fabrication method of soldered circuit elements and a method of forming circuit pins of a stacked package, applicable to a semiconductor package structure. A positioning rack and a plurality of conductor elements are used. A plurality of positioning holes are provided on a bottom surface of the positioning rack to form a conductor positioning area, and an operational portion is formed on an opposing surface away from the conductor positioning area, for being mounted with pick and place equipment. The conductor elements are positioned in the positioning holes. When the pick and place equipment loads and moves the positioning rack to preformed circuit contacts of the stacked package, the conductor elements are soldered to the preformed circuit contacts and then the positioning rack is removed.

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Номер записи: 81

21-03-2019 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20190088569A1

Автор: SAWANAKA Kenichi

Принадлежит: Toshiba Memory Corporation

A semiconductor memory device includes a housing having a wall, a circuit board located in the housing and spaced from the wall and extending along the surface of the wall, a memory located on the circuit board, a heat conduction member interposed, and compressed, between the wall and the memory. The wall includes an uneven region comprising contact portions contacting the heat conduction member and recess portions located between the contact portions. The recess portions are recessed inwardly of the wall from the ends of the contact portions in a direction away from the location of the memory. 1. A semiconductor memory device comprising:a housing having a wall;a circuit board located in the housing and spaced from the wall, and extending along the surface of the wall;a memory located above the circuit board; anda heat conduction member interposed, and compressed, between the wall and the memory, whereinthe wall includes an uneven region comprising contact portions that contact the heat conduction member and recess portions located between the contact portions, the recess portions recessed inwardly of the wall from the ends of the contact portions in a direction away from a location of the memory.2. The semiconductor memory device according to claim 1 , wherein portions of the heat conduction member extend inwardly of the recess portions.3. The semiconductor memory device of claim 1 , wherein portions of the contact portions surround at least one of the recess portions.4. The semiconductor memory device according to claim 1 , whereinthe uneven region includes a region in which at least two of the contact portions and at least two of the recess portions are dispersedly arranged with respect to each other.5. The semiconductor memory device according to claim 1 , whereinthe uneven region includes a region in which at least one portion of the contact portions and at least one portion of the recess portions are provided in a mesh shaped pattern.6. The semiconductor ...

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Номер записи: 82

21-03-2019 дата публикации

"Lead-Free Solder Ball"

Номер: US20190088611A1

Автор: NOMURA Hikaru, Tachibana Ken, Yamanaka Yoshie, Yoshikawa Shunsaku

Принадлежит:

A lead-free solder ball is provided which suppresses interfacial peeling in a bonding interface of a solder ball, fusion defects which develop between the solder ball and solder paste, and which can be used both with Ni electrodes plated with Au or the like and Cu electrodes having a water-soluble preflux applied atop Cu. The lead-free solder ball for electrodes of BGAs or CSPs consists of 1.6-2.9 mass % of Ag, 0.7-0.8 mass % of Cu, 0.05-0.08 mass % of Ni, and a remainder of Sn. It has excellent resistance to thermal fatigue and to drop impacts regardless of the type of electrodes of a printed circuit board to which it is bonded, which are Cu electrodes or Ni electrodes having Au plating or Au/Pd plating as surface treatment. 1. A lead-free solder ball which is installed for use as an electrode on a rear surface of a module substrate for a BGA or a CSP and which is fused with a solder paste , the solder ball having a solder composition consisting of:1.6-2.9 mass % of Ag;0.7-0.8 mass % of Cu;0.05-0.08 mass % of Ni; at least one of Fe and Co in a total amount of 0.003-0.1 mass %; and', 'Ge in a total amount of 0.003-0.1 mass %; and, 'at least one ofa remainder of Sn.2. The lead-free solder ball as set forth in claim 1 , wherein the solder composition consists of:1.6-2.9 mass % of Ag;0.7-0.8 mass % of Cu;0.05-0.08 mass % of Ni;at least one of Fe and Co in a total amount of 0.003-0.1 mass %; anda remainder of Sn.3. The lead-free solder ball as set forth in claim 1 , wherein the solder composition consists of:1.6-2.9 mass % of Ag;0.7-0.8 mass % of Cu;0.05-0.08 mass % of Ni;Ge in a total amount of 0.003-0.1 mass %; anda remainder of Sn.4. The lead-free solder ball as set forth in claim 1 , wherein the solder composition consists of:1.6-2.9 mass % of Ag;0.7-0.8 mass % of Cu;0.05-0.08 mass % of Ni;at least one of Fe and Co in a total amount of 0.003-0.1 mass %;Ge in a total amount of 0.003-0.1 mass %; anda remainder of Sn.5. The lead-free solder ball as set forth in claim 1 ...

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Номер записи: 83

21-03-2019 дата публикации

MICRO-TRANSFER PRINTABLE ELECTRONIC COMPONENT

Номер: US20190088630A1

Автор: Bower Christopher, Cok Ronald S., JR. Carl, MEITL Matthew, Prevatte

Принадлежит:

A micro-transfer printable electronic component includes one or more electronic components, such as integrated circuits or LEDs. Each electronic component has device electrical contacts for providing electrical power to the electronic component and a post side. A plurality of electrical conductors includes at least one electrical conductor electrically connected to each of the device electrical contacts. One or more electrically conductive connection posts protrude beyond the post side. Each connection post is electrically connected to at least one of the electrical conductors. Additional connection posts can form electrical jumpers that electrically connect electrical conductors on a destination substrate to which the printable electronic component is micro-transfer printed. The printable electronic component can be a full-color pixel in a display. 1. A micro-transfer printable electronic component , comprising:a dielectric layer;a plurality of electronic devices disposed in contact with the dielectric layer, each electronic device having an individual substrate and device electrical contacts for providing electrical power to the electronic device, the electronic device having a post side and an opposing stamp side;a plurality of electrical conductors, at least one electrical conductor electrically connected to each of the device electrical contacts; andone or more electrically conductive connection posts that protrude from the dielectric layer in a direction opposite to the stamp side, each connection post electrically connected to at least one of the electrical conductors.2. The micro-transfer printable electronic component of claim 1 , wherein the dielectric layer is on or adjacent to the post side claim 1 , wherein the dielectric layer is on or adjacent to the stamp side claim 1 , or comprising one or more dielectric layers that are on both the stamp side and the post side.3. The micro-transfer printable electronic component of claim 2 , wherein the dielectric ...

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Номер записи: 84

05-05-2022 дата публикации

MULTI-DIE MEMORY DEVICE

Номер: US20220139446A1

Автор: Best Scott C., Li Ming

Принадлежит:

A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

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Номер записи: 85

09-04-2015 дата публикации

60 ghz integrated circuit to printed circuit board transitions

Номер: US20150097633A1

Автор: Christopher Andrew Devries, Houssam Kanj, Huanhuan Gu, Morris Repeta

Принадлежит: BlackBerry Ltd

Embodiments are directed to a transition structure for interfacing an integrated circuit chip and a substrate, comprising: a co-planar waveguide (CPW) structure formed based on ground-signal-ground (GSG) pads on the integrated circuit chip, a grounded co-planar waveguide (CPWG) structure coupled to the GSG pads, and a microstrip coupled to the CPWG structure.

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Номер записи: 86

30-03-2017 дата публикации

PACKAGE TOPSIDE BALL GRID ARRAY FOR ULTRA LOW Z-HEIGHT

Номер: US20170092618A1

Автор: Huitink David

Принадлежит:

Embodiments of the present disclosure describe integrated circuit (IC) package assemblies having top-side connection pads, computing devices incorporating the IC package assemblies, methods for formation of the IC package assemblies, and associated configurations. An IC package assembly may include a substrate having a first side and a second side opposite the first side, an IC die coupled with the first side of the substrate, a plurality of connection pads coupled with the first side of the substrate, and a plurality of interconnect structures coupled with the plurality of connection pads. Other embodiments may be described and/or claimed. 1. A computing device comprising:a printed circuit board (PCB) having a die cavity formed therein;a substrate having a first side with a plurality of connection pads electrically coupled with the PCB, and a second side opposite the first side; anda first integrated circuit (IC) die coupled with the first side of the substrate, wherein the first IC die is positioned such that it is within a boundary of the die cavity in a first direction parallel with the first side of the substrate and a second direction parallel with the first side of the substrate and perpendicular to the first direction, and the first IC die is electrically coupled with one or more of the plurality of connection pads; anda second IC die coupled with the second side of the substrate, wherein the second IC die is a radio frequency (RF) communication die electrically coupled with one or more of the plurality of connection pads.2. The computing device of claim 1 , further comprising a plurality of interconnect structures coupled with the plurality of connection pads and the PCB.3. The computing device of claim 2 , wherein the plurality of interconnect structures are solder balls.4. The computing device of claim 1 , further comprising a heat sink coupled with the first IC die.5. The computing device of claim 4 , wherein the first IC die includes one or more thermal ...

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Номер записи: 87

05-04-2018 дата публикации

Circuits and methods related to radio-frequency devices with overmold structure

Номер: US20180096951A1

Автор: Hoang Mong Nguyen, Howard E. CHEN, Robert Francis Darveaux

Принадлежит: Skyworks Solutions Inc

A method for manufacturing packaged radio-frequency devices is disclosed, including providing a packaging substrate configured to receive a plurality of components, the packaging substrate including a first side and a second side. The method further includes forming a shielded package on the first side of the packaging substrate, the shielded package including a first circuit and a first overmold structure, the shielded package configured to provide radio-frequency shielding for at least a portion of the first circuit. The method includes mounting a component on the second side of the packaging substrate, forming a second overmold structure over the component and forming a set of cavities in the second overmold structure, the set of cavities positioned relative to the component. The method includes forming a set of through-mold connections in the set of cavities in the second overmold structure.

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Номер записи: 88

06-04-2017 дата публикации

Semiconductor device

Номер: US20170098625A1

Автор: Hirofumi Takeda, Yoshihisa Takada

Принадлежит: ROHM CO LTD

A semiconductor device is provided. The semiconductor device can be manufactured with a reduced cost. The semiconductor device ( 1 D) includes, a substrate ( 100 D), which includes a main surface ( 101 D) and a recess ( 108 D) depressed from the main surface ( 101 D), and includes a semiconductor material; a wiring layer ( 200 D) in which at least a portion thereof is formed on the substrate ( 100 D); one or more first elements ( 370 D) accommodated in the recess ( 108 D); a sealing resin ( 400 D) covering at least a portion of the one or more first elements ( 370 D) and filled in the recess ( 108 D); and a plurality of columnar conductive portions ( 230 D) penetrating through the sealing resin ( 400 D) in the depth direction of the recess ( 108 D), and respectively connected with the portion of the wiring layer ( 200 D) that is formed at the recess ( 108 D).

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Номер записи: 89

28-03-2019 дата публикации

Very Thin Embedded Trace Substrate-System in Package (SIP)

Номер: US20190096815A1

Автор: Ernesto Gutierrez, III, Ian Kent, Jesus Mennen Belonio, JR., Melvin Martin, Rajesh Subraya Aiyandra, Shou Cheng Eric Hu

Принадлежит: Dialog Semiconductor UK Ltd

A system in package is provided comprising an embedded trace substrate having redistribution layers therein, at least one passive component mounted on one side of the embedded trace substrate and embedded in a first molding compound, at least one silicon die mounted on an opposite side of the embedded trace substrate and embedded in a second molding compound wherein electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers, and solder balls mounted through openings in the second molding layer to the redistribution layers wherein the solder balls provide package output.

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Номер записи: 90

12-04-2018 дата публикации

Manufacturing method of semiconductor device and semiconductor device thereof

Номер: US20180102342A1

Автор: Do Hyung Kim, Dong Jin Kim, Glenn Rinne, Jin Han Kim, Yeong Beom Ko

Принадлежит: Amkor Technology Inc

A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method for manufacturing a semiconductor device that comprises ordering and performing processing steps in a manner that prevents warpage deformation from occurring to a wafer and/or die due to mismatching thermal coefficients.

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Номер записи: 91

13-04-2017 дата публикации

Molding compound wrapped package substrate

Номер: US20170103943A1

Автор: Dyi-chung Hu

Принадлежит: Individual

A package substrate for chip/chips package wrapped by a molding compound is disclosed. The molding compound functions as a stiffener for the thin film package substrate. One embodiment discloses at least one redistribution layer (RDL) is prepared and the RDL is wrapped by a molding compound. The molding compound wraps four lateral sides and bottom side of the RDL. A top side of the RDL is made for a chip to mount and a bottom side of the RDL is planted a plurality of solder balls so that the bottom side of the chip package is adaptive to mount onto a system board in a later process.

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Номер записи: 92

04-04-2019 дата публикации

INTEGRATED EMBEDDED SUBSTRATE AND SOCKET

Номер: US20190103349A1

Автор: Nekkanty Srikant, VISWANATH Ram

Принадлежит: Intel Corporation

An apparatus is provided which comprises: a substrate material comprising one or more embedded copper planes, one or more plated through holes through the substrate material, one or more metal contacts, the metal contacts comprising a substantially straight section coupled with adhesive within the one or more plated through holes, and a cantilever spring section extending beyond a first surface of the substrate material, and one or more conductive contacts on a second surface of the substrate material, opposite the first surface, the conductive contacts coupled with the metal contacts. Other embodiments are also disclosed and claimed. 1. An apparatus comprising:a substrate material comprising one or more embedded copper planes;one or more plated through holes through the substrate material;one or more metal contacts, the metal contacts comprising a substantially straight section coupled with adhesive within the one or more plated through holes, and a cantilever spring section extending beyond a first surface of the substrate material; andone or more conductive contacts on a second surface of the substrate material, opposite the first surface, the conductive contacts coupled with the metal contacts.2. The apparatus of claim 1 , further comprising separate power and ground planes embedded in the substrate material.3. The apparatus of claim 2 , wherein one or more plated through holes are coupled with a ground plane.4. The apparatus of claim 3 , wherein at least one of the one or more metal contacts is conductively coupled with a surrounding plated through hole.5. The apparatus of claim 3 , wherein the one or more conductive contacts comprise a pitch spacing coarser than a metal contact pitch spacing.6. The apparatus of claim 3 , wherein at least one of the one or more plated through holes is conductively coupled with at least one of the one or more conductive contacts at least in part to spread heat.7. The apparatus of claim 3 , wherein the substrate material ...

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Номер записи: 93

30-04-2015 дата публикации

SEMICONDUCTOR PACKAGE AND WIRING BOARD HAVING THE SEMICONDUCTOR PACKAGE THEREON

Номер: US20150115430A1

Автор: Yamamoto Toshihisa

Принадлежит:

A semiconductor package includes a chip, a sealing body covering the chip, and a plurality of external connection terminals connected to the chip. The external connection terminals expose from a surface of the sealing body and are arranged in a grid on the surface of the sealing body. In the grid on the surface of the sealing body, each external connection terminal is adjacent to an area vacant of an other external connection terminal in at least one direction of eight directions from each external connection terminal, the eight directions including first linear directions along a row of the grid, second linear directions along a row of the grid perpendicular to the first linear directions, and four diagonal directions defined between the first linear directions and the second linear directions. 1. A semiconductor package comprising:a chip;a sealing body covering the chip; anda plurality of external connection terminals being connected to the chip and exposing from a surface of the sealing body, the plurality of external connection terminals being arranged in a grid on the surface of the sealing body, wherein, in the grid, each external connection terminal is adjacent to an area vacant of an other external connection terminal in at least one direction of eight directions from each external connection terminal, the eight directions including first linear directions along a row of the grid, second linear directions along a row of the grid perpendicular to the first linear directions, and four diagonal directions defined between the first linear directions and the second linear directions.2. A wiring board for receiving a semiconductor package thereon , the semiconductor package having a plurality of external connection terminals arranged in a grid , the wiring board comprising:a substrate having a first surface for receiving the semiconductor package thereon;a plurality of pads being disposed on the first surface of the substrate to correspond to the external ...

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Номер записи: 94

29-04-2021 дата публикации

IC CHIP PACKAGE WITH DUMMY SOLDER STRUCTURE UNDER CORNER, AND RELATED METHOD

Номер: US20210125952A1

Автор: Graf Richard S., Habib Nazmul, NAYINI Manish, Patel Janak G.

Принадлежит:

An IC chip package includes a substrate having a plurality of interconnect metal pads, and a chip having a plurality of interconnect metal pads arranged thereon. An interconnect solder structure electrically connects each of the plurality of interconnect metal pads. The chip is devoid of the interconnect solder structures and interconnect metal pads at one or more corners of the chip. Rather, a dummy solder structure connects the IC chip to the substrate at each of the one or more corners of the IC chip, and the dummy solder structure is directly under at least one side of the IC chip at the one or more corners of the IC chip. The dummy solder structure has a larger volume than a volume of each of the plurality of interconnect solder structures. The dummy solder structure eliminates a chip-underfill interface at corner(s) of the chip where delamination would occur. 1. An integrated circuit (IC) chip package , comprising:a substrate having a first plurality of interconnect metal pads thereon;an integrated circuit (IC) chip having a second plurality of interconnect metal pads arranged thereon;an interconnect solder structure electrically connecting each of the first and second plurality of interconnect metal pads, the IC chip being devoid of the interconnect solder structures at one or more corners of the IC chip; anda dummy solder structure connecting the IC chip to the substrate at each of the one or more corners of the IC chip, andwherein the dummy solder structure is directly under at least one side of the IC chip at the one or more corners of the IC chip, andwherein the dummy solder structure has a larger volume than a volume of each of the interconnect solder structures.2. The IC chip package of claim 1 , wherein at least one dummy solder structure extends laterally outward beyond the at least one side of the IC chip.3. The IC chip package of claim 1 , wherein the dummy solder structure includes a first solder material that is softer than a different claim 1 , ...

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Номер записи: 95

29-04-2021 дата публикации

Semiconductor device package and method of manufacturing the same

Номер: US20210125965A1

Автор: Wen-Long Lu

Принадлежит: Advanced Semiconductor Engineering Inc

A semiconductor device package includes a dielectric layer and a patterned conductive layer disposed in the dielectric layer. The dielectric layer has a first surface, a second surface opposite the first surface, and a third surface extended from the first surface to the second surface. The semiconductor device package also includes a first electronic component in direct contact with the first surface of the dielectric layer and a first connection structure disposed between the first electronic component and the patterned conductive layer. A method of manufacturing a semiconductor device package is also disclosed.

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Номер записи: 96

02-04-2020 дата публикации

Manufacturing method of semiconductor package

Номер: US20200105715A1

Автор: Byeongdeck Jang, Youngsuk Kim

Принадлежит: Disco Corp

A manufacturing method of a semiconductor package includes a groove forming step of cutting a semiconductor package substrate from an upper surface side along division lines in a cut-in-depth range of at least such a depth as to cause a ground line included in a wiring substrate to be exposed in a processing groove to such a depth that the semiconductor package substrate is not fully cut with a first cutting blade, thereby forming the processing groove having a first width at least on an upper surface of a sealing material, a shielding layer forming step of forming a shielding layer on a side surface of the processing groove, a bottom surface of the processing groove, and the upper surface of the sealing material with a conductive material from an upper side of the sealing material, and a dividing step of, cutting the semiconductor package substrate into individual semiconductor packages.

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Номер записи: 97

18-04-2019 дата публикации

ROOM TEMPERATURE METAL DIRECT BONDING

Номер: US20190115247A1

Автор: ENQUIST Paul M., Rose Anthony Scot, TONG Qin-Yi

Принадлежит:

A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed. 1. A bonded structure comprising:a first plurality of metallic pads disposed on a first substrate;a first non-metallic region located on a first surface of said first substrate proximate to the first plurality of metallic pads;a second plurality of metallic pads disposed on a second substrate; anda second non-metallic region located on a second surface of the second substrate proximate to the second plurality of metallic pads,wherein a portion of each metallic pad of the first plurality of metallic pads directly contacts a corresponding metallic pad of the second plurality of metallic pads to form a metallic contact, andwherein the first non-metallic region contacts and is directly bonded to the second non-metallic region along an interface, the interface between the first non-metallic region and the second non-metallic region extending substantially to the metallic contact.2. The bonded structure of claim 1 , wherein each metallic pad comprises a reflowable material.3. The bonded structure of claim 1 , wherein the first non-metallic region comprises silicon oxide. This application is a continuation of application Ser. No. 14/959,204 filed Dec. 4, 2015, which is a continuation of application Ser. No. 14/474,476 ...

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Номер записи: 98

09-04-2020 дата публикации

ANTENNA MODULE AND DUAL-BAND ANTENNA APPARATUS

Номер: US20200112100A1

Автор: JANG Seung Goo, KIM Hong In, KIM Nam Ki, Kim Sang Hyun, KIM Thomas A., RYOO Jeong Ki

Принадлежит: SAMSUNG ELECTRO-MECHANICS CO., LTD.

An antenna module includes a connection member including at least one wiring layer and at least one insulating layer; an IC disposed on a first surface of the connection member and electrically connected to at least one wiring layer of the connection member; and an antenna package disposed on a second surface of the connection member and including first antenna members and feed vias, wherein the connection member includes a feed line having a first end electrically connected to a corresponding wire of at least one wiring layer of the connection member; a second antenna member electrically connected to a second end of the feed line and configured to transmit or receive a radio frequency (RF) signal; and a ground member spaced apart from the feed line in a direction toward the first surface or the second surface of the connection member. 1. An antenna module , comprising:patch antennas;feed vias coupled to the patch antennas;an integrated circuit (IC) electrically connected to the feed vias;a connection member disposed between the IC and the patch antennas, comprising a ground layer, and wiring members electrically connected to the IC and surrounded by the ground layer;feed lines electrically connected to the wiring members;dipole antennas electrically connected to the feed lines, and disposed on a first level between the patch antennas and the IC; andfirst arm members disposed on a second level between the dipole antennas and the IC, and separated from the dipole antennas and the ground layer,wherein at least portions of the first arm members overlap with the dipole antennas in a vertical direction.2. The antenna module of claim 1 , wherein sizes of the first arm members are larger than sizes of the dipole antennas.3. The antenna module of claim 1 , further comprising second arm members disposed on a third level between the dipole antennas and the patch antennas and overlapping with at least portions of the dipole antennas in the vertical direction.4. The antenna ...

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Номер записи: 99

05-05-2016 дата публикации

HIGH DENSITY FAN OUT PACKAGE STRUCTURE

Номер: US20160126173A1

Автор: Gu Shiqun, KIM Dong Wook, LEE Jae Sik, WE Hong Bok

Принадлежит:

A high density fan out package structure may include a contact layer. The contact layer includes a conductive interconnect layer having a first surface facing an active die and a second surface facing a redistribution layer. The high density fan out package structure has a barrier layer on the first surface of the conductive interconnect layer. The high density fan out package structure may also include the redistribution layer, which has conductive routing layers. The conductive routing layers may be configured to couple a first conductive interconnect to the conductive interconnect layer. The high density fan out package structure may further include a first via coupled to the barrier liner and configured to couple with a second conductive interconnect to the active die. 1. A high density fan out package structure , comprising:a contact layer including a conductive interconnect layer having a first surface facing an active die and a second surface facing a redistribution layer;a barrier liner on the first surface of the conductive interconnect layer;the redistribution layer comprising a plurality of conductive routing layers configured to couple a first conductive interconnect to the conductive interconnect layer; anda first via coupled to the barrier liner and configured to couple with a second conductive interconnect to the active die.2. The high density fan out package structure of claim 1 , in which the first conductive interconnect is a ball grid array (BGA).3. The high density fan out package structure of claim 1 , in which the barrier liner comprises tantalum.4. The high density fan out package structure of claim 1 , in which the first via comprises an under bump conductive layer on the barrier liner and a conductive material on the under bump conductive layer and coupled to the second conductive interconnect.51. The high density fan out package structure of claim 1 , in which the conductive interconnect layer comprises a first back-end-of-line (BEOL) ...

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Номер записи: 100