Drucksensorgehäuse und Verfahren zu seiner Herstellung

Ein Drucksensorgehäuse (1) der vorliegenden Erfindung umfasst einen vertieft geformten Gehäusehauptkörper (20), in dessen Inneres ein Drucksensor (10) montiert ist, und einen Deckel (30) aus einem lichtabschirmenden Element, der den Gehäusehauptkörper (20) in einem Zustand abdeckt, in dem über der Membran (11) des Drucksensors (10) ein Innenraum (21) sichergestellt wird. Der Gehäusehauptkörper (20) und der Deckel (30) sind an mehreren Stellen abschnittsweise verklebt. In den anderen Bereichen zwischen dem Gehäusehauptkörper (20) und dem Deckel (30) außer den abschnittsweisen Verklebungen sind Zwischenräume (34) gebildet, die die Außenseite und den Innenraum (21) des Gehäusehauptkörpers (20) verbinden.

Component mounting method

Semiconductor device

A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, a heat radiating plate disposed on the substrate and covering the semiconductor element, and a connection member connecting an upper surface of the semiconductor element and a lower surface of the heat radiating plate, wherein the connection member includes a first member being in contact with the upper surface of the semiconductor element and having a first melting point, a second member being in contact with the first member, having a larger area than the first member, and having a second melting point higher than the first melting point, and a third member interposed between the second member and the heat radiating plate, having an area smaller than the second member, and having a third melting point lower than the second melting point.

SHIELDED PACKAGE ASSEMBLIES WITH INTEGRATED CAPACITOR

Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

LEAD FRAMELESS HERMETIC CIRCUIT PACKAGE

MOLDED HIGH DENSITY ELECTRONIC PACKAGING STRUCTURE FOR HIGH PERFORMANCE APPLICATIONS

The invention discloses a thermally enhanced ball grid array package (200) including a base layer element (202) and a flip chip die (203) mounted on the base layer element (202). The die (203) has a first surface (203a) electrically coupled to the base layer element (202), a second surface (203b) opposite to the first surface (203a), and lateral sides (203c). A molding compound (205) encapsulates the base layer element (202) and the lateral sides (203c) of the die (203). A surface (220) is formed of the second surface (203b) of the die (203) and an upper surface of the molding compound. A material (207) is disposed on the surface (220), and a heat spreader (206) is mounted on the material.

Stacked semiconductor die assemblies with partitioned logic and associated systems and methods

Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies.

Method for manufacturing a semiconductor device having multiple heat sinks

A method for manufacturing a semiconductor device is provided, the method including: mounting a first element on a wiring substrate, placing a first heat sink on the first element with a metal material interposed between the first heat sink and the first element, attaching the first heat sink to the first element via the metal material by heating and melting the metal material, and mounting a second element on the wiring substrate after the steps of attaching the first heat sink to the first element.

Stacked semiconductor die assemblies with partitioned logic and associated systems and methods

Semiconductor package and manufacturing method thereof

A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.

DIE SEALANT FOR CHIP PACKAGING AND PACKAGING STRUCTURE

The present application discloses a die sealant for chip packaging and a packaging structure, wherein epoxy resin adopted in the die sealant has flexible units such as polyether. In combination with the compounding of components such as a curing agent and a diluent, good flexibility and strength are achieved, and warpage is effectively reduced, wherein the warpage can be reduced to 0 mm, the modulus can reach up to 8 GPa or above, good silicon adhesion is achieved, and a silicon wafer can be effectively protected from bending cracks caused by warpage. Moreover, by adding a p-tert-butylphenol epoxy resin diluent, impacts of a monofunctional aliphatic diluent on a curing system can be further reduced effectively, and the flexibility and modulus of the die sealant can be further improved.

STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH PARTITIONED LOGIC AND ASSOCIATED SYSTEMS AND METHODS

OF THE DISCLOSURE STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH PARTITIONED LOGIC AND ASSOCIATED SYSTEMS AND METHODS Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies. Fig. 1 ...

Thermal interface material on package

A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly.

Thermal interface material on package

A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly.

MOLDED HIGH DENSITY ELECTRONIC PACKAGING STRUCTURE FOR HIGH PERFORMANCE APPLICATIONS

A thermally enhanced ball grid array package is disclosed. The package includes a base layer element and a flip chip die mounted on the base layer element. The die has a first surface electrically coupled to the base layer element, a second surface opposite to the first surface, and lateral sides. A molding compound encapsulates the base layer element and the lateral sides of the die. A surface is formed of the second surface of the die and an upper surface of the molding compound. A material is disposed on the surface, and a heat spreader is mounted on the material.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, a heat radiating plate disposed on the substrate and covering the semiconductor element, and a connection member connecting an upper surface of the semiconductor element and a lower surface of the heat radiating plate, wherein the connection member includes a first member being in contact with the upper surface of the semiconductor element and having a first melting point, a second member being in contact with the first member, having a larger area than the first member, and having a second melting point higher than the first melting point, and a third member interposed between the second member and the heat radiating plate, having an area smaller than the second member, and having a third melting point lower than the second melting point.

RADIO FREQUENCY MODULE

A packaged radio frequency (RF) module is disclosed. The module can include a package substrate, a first die electrically and mechanically attached to the substrate, the first die comprising an RF switch, wherein the first die is flip-chip attached to the package substrate by way of a plurality of interconnects between the first die and the package substrate, a second die electrically and mechanically attached to the substrate, an encapsulating material protecting electrical connections between the first die and the package substrate, and a lid attached to the package substrate such that the package substrate and the lid at least partially define an air cavity within which the first and the second die are mounted, an active surface of the second die being exposed to the air cavity.

Semiconductor device and manufacturing method of semiconductor device

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

PRESSURE-SENSOR PACKAGE AND METHOD FOR PRODUCING SAME

This pressure-sensor package (1) is provided with a concave package body (20) having a pressure sensor (10) mounted in the interior thereof, and a lid (30) comprising a light-blocking member for covering the package body (20) in a state ensuring the presence of an interior space (21) above a diaphragm (11) of the pressure sensor (10). The package body (20) and the lid (30) are each sectionally adhered to one another in a plurality of locations. The sections between the package body (20) and the lid (30) other than the sectionally adhered areas have gaps (34) formed therein for connecting the exterior of the package body (20) to the interior space (21).

ELECTRICAL PACKAGE INCLUDING BIMETAL LID

Electrical package including bimetal lid. The electrical package includes: an organic substrate; a semiconductor chip electrically connected to electrical pads on a surface of the organic substrate via a plurality of solder balls; and a lid for encapsulating the semiconductor chip on the organic substrate, wherein (i) an inner surface of a central part of the lid is connected to a surface of the semiconductor chip via a first TIM, (ii) an inner surface of an outer part of the lid is hermetically connected to the surface of the organic substrate, and (iii) the lid has a bimetal structure including at least two different metals. A circuit module is also provided.

Electronic device and its manufacturing method

The thinned integrated circuit device and its production process

ELECTRONIC ASSEMBLY WITH A COMPONENT ARRANGED BETWEEN TWO CIRCUIT CARRIERS, AND METHOD FOR JOINING SUCH AN ASSEMBLY

Lead frameless hermetic circuit package

A open cavity semiconductor chip package that is leadless and does not have a metal lead frame as in conventional packages. The absence of a lead frame minimizes leakage paths and allows the novel package to be more readily fabricated as a hermetic package. A dual sided insulative or dielectric film is employed as the base interconnect between a semiconductor chip and outside contacts. Electrical connection from the top side of the film to the bottom side of the film is made through conductive micro-vias. The semiconductor chip is mounted on a paddle in a central opening in the film and wire bonded to pads on the film. After mounting of the chip, a cover or lid is attached to the film to encapsulate the assembly and maintain hermeticity of the package.

Semiconductor package structure

Various embodiments relating to semiconductor package structures having reduced thickness while maintaining rigidity are provided. In one embodiment, a semiconductor package structure includes a substrate including a surface, a semiconductor die including a first interface surface connected to the surface of the substrate and a second interface surface opposing the first interface surface, a mold compound applied to the substrate surrounding the semiconductor die. The second interface surface of the semiconductor die is exposed from the mold compound. The semiconductor package structure includes a heat dissipation cover attached to the second interface surface of the semiconductor die and the mold compound.

RADIO FREQUENCY COMMUNICATION SYSTEMS

A packaged radio frequency (RF) module is disclosed. The module can include a substrate, a first die electrically and mechanically attached to the substrate, a second die electrically and mechanically attached to the substrate, an encapsulating material, and a lid attached to the substrate. The first die comprises a silicon-based die, such as an RF switch die, and the second die comprises a compound semiconductor die, such as an RF amplifier. The encapsulating material can protect electrical connections between the first die and the substrate. The substrate and the lid at least partially define an air cavity within which the first and the second die are mounted. An active surface of the second die is exposed to the air cavity.

SEMICONDUCTOR DEVICE AND MICROPHONE

... [Solution] A bump bonding pad (61) is disposed at an upper surface of a substrate (45), and a bump (70) of a circuit element (43) is connected to the bump bonding pad (61). The bump bonding pad (61) is connected to a substrate side junction (69) disposed at a surface facing a cover (44) by a pattern wiring (64). A microphone tip (42) is mounted on a lower surface of the cover (44). A first connection pad (a bonding pad (48), and a cover side junction (49)) is disposed at a surface of the cover (44) facing the substrate (45), and the microphone tip (42) is connected to the first connection pad by a bonding wire (50). The first connection pad of the cover (44) and the substrate side junction (69) of the substrate (45) are connected by an electrically conducting material (65), and therefore the microphone tip (42) and the circuit element (43) are connected electrically.

Thermal interface material on package

A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly.

LEAD FRAMELESS HERMETIC CIRCUIT PACKAGE

A open cavity semiconductor chip package that is leadless and does not have a metal lead frame as in conventional packages. The absence of a lead frame minimizes leakage paths and allows the novel package to be more readily fabricated as a hermetic package. A dual sided insulative or dielectric film is employed as the base interconnect between a semiconductor chip and outside contacts. Electrical connection from the top side of the film to the bottom side of the film is made through conductive micro-vias. The semiconductor chip is mounted on a paddle in a central opening in the film and wire bonded to pads on the film. After mounting of the chip, a cover or lid is attached to the film to encapsulate the assembly and maintain hermeticity of the package.

THERMAL INTERFACE MATERIAL ON PACKAGE

A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly. 1. A method , comprising:dispensing a thermal interface material (TIM) on an electronic assembly;pressing a lid onto the electronic assembly to perform a packaged assembly;performing a sonoscan of the packaged assembly for determining a presence of voiding in the TIM.2. The method of claim 1 , further comprising removing volatile species of the TIM prior to pressing the lid.3. The method of claim 2 , wherein the volatile species comprises cyclic siloxanes and decyl trimethoxysilane.4. The method of claim 2 , wherein the removal of the volatile species comprises maintaining the TIM at room temperature for a predetermined time period prior to pressing the lid.5. The method of claim 4 , wherein the predetermined time period is about 60 minutes.6. The method of claim 2 , wherein the removal of the volatile species comprises subjecting the TIM to a predetermined temperature claim 2 , in an oven claim 2 , for a predetermined time period.7. The method of claim 6 , wherein the predetermined temperature is about 45° C. to 55° C. and the predetermined time period is about 15-30 minutes.8. The method of claim 6 , wherein the predetermined temperature is about 50° C. and the predetermined time period is about 20 minutes.9. The method of claim 6 , wherein the predetermined temperature is about 50° C. and the predetermined time period is about 15 minutes.10. The method of claim 2 , wherein the removal of the volatile species comprises subjecting the TIM to a vacuum outgassing process. ...

LIMITING ELECTRONIC PACKAGE WARPAGE

An electronic package includes a carrier, semiconductor chip, a lid, and a lid-ring. The carrier includes a top surface and a bottom surface configured to be electrically connected to a system board. The semiconductor chip is electrically connected to the top surface. The lid is attached to the top surface enclosing semiconductor chip and includes a perimeter recess. The lid-ring is juxtaposed within the perimeter recess. The lid-ring exerts a reverse bending moment upon the lid to limit warpage of the electronic package.

Printed circuit board

A printed circuit board includes: a printed wiring board including an insulating layer wherein a recessed part is provided on a top surface of the insulating layer, and a printed conductor provided inside the recessed part; a bare chip part mounted in the recessed part and electrically connected to the printed conductor; an electronic part mounted on the top surface of the printed wiring board other than the recessed part; and a cap fixed to the top surface of the printed wiring board and hollow-sealing the bare chip part mounted in the recessed part, wherein using a height of the top surface of the printed wiring board as a reference, a height of a top surface of the cap is equal to or below a maximum height of a top surface of the electronic part.

Semiconductor device

A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, a heat radiating plate disposed on the substrate and covering the semiconductor element, and a connection member connecting an upper surface of the semiconductor element and a lower surface of the heat radiating plate, wherein the connection member includes a first member being in contact with the upper surface of the semiconductor element and having a first melting point, a second member being in contact with the first member, having a larger area than the first member, and having a second melting point higher than the first melting point, and a third member interposed between the second member and the heat radiating plate, having an area smaller than the second member, and having a third melting point lower than the second melting point.

High reliability wafer level semiconductor packaging

Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, a redistribution layer coupled to a second side of the semiconductor die, and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer coupled to the semiconductor die. The adhesive may be located in a trench around a perimeter of the semiconductor die and located in a corresponding trench around a perimeter of the glass lid.

STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH PARTITIONED LOGIC AND ASSOCIATED SYSTEMS AND METHODS

Shielded package assemblies with integrated capacitor

Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

Sandwich structure with double-sided cooling and EMI shielding

A sandwich structure and method thereof is disclosed for double-sided cooling, EMI noise shielding and current carrying in mini-modules. The proposed structure comprises a top structure and a bottom structure to achieve double-sided cooling. Meanwhile, the top structure is configured to shield EMI noises as well. The proposed structure further comprises a first set of connecting structures for connecting devices of the mini-modules with the top structure and a second set of connecting structure for connecting the top structure with the bottom structure. The connecting structures are capable of carrying current.

Semiconductor device

A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, a heat radiating plate disposed on the substrate and covering the semiconductor element, and a connection member connecting an upper surface of the semiconductor element and a lower surface of the heat radiating plate, wherein the connection member includes a first member being in contact with the upper surface of the semiconductor element and having a first melting point, a second member being in contact with the first member, having a larger area than the first member, and having a second melting point higher than the first melting point, and a third member interposed between the second member and the heat radiating plate, having an area smaller than the second member, and having a third melting point lower than the second melting point.

Packaging for high speed chip to chip communication

Disclosed are chip packaging structures for high speed chip to chip and chip to carrier communications and methods of making such structures. The chip packaging structures do not require an interposer containing through silicon vias and/or provide structures having reduced warping.

Thermal interface material on package

A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly.

HIGH RELIABILITY WAFER LEVEL SEMICONDUCTOR PACKAGING

Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, a redistribution layer coupled to a second side of the semiconductor die, and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer coupled to the semiconductor die. The adhesive may be located in a trench around a perimeter of the semiconductor die and located in a corresponding trench around a perimeter of the glass lid. 1. A semiconductor package comprising:a semiconductor die comprising a first side and a second side;a first trench comprised in the first side of the semiconductor die, the trench positioned outside an active area of the die;a glass lid comprising a second trench, the glass lid fixedly coupled to a first side of the semiconductor die by an adhesive;wherein the adhesive is comprised in the first trench in the first side of the semiconductor die and comprised in the second trench positioned around a perimeter of the glass lid.2. The semiconductor package of claim 1 , wherein the adhesive is selected from the group consisting of thermal curable resin claim 1 , epoxy claim 1 , ultraviolet light curable resin and any combination thereof.3. The semiconductor package of claim 2 , wherein the adhesive is cured.4. The semiconductor package of claim 1 , wherein the adhesive is evenly distributed within the first trench and the second trench.5. The semiconductor package of claim 1 , wherein the adhesive extends out from the first trench and the second trench to further bond the glass lid and the semiconductor die.6. The semiconductor package of claim 1 , further comprising a redistribution layer coupled to the second side of the semiconductor die.7. The semiconductor package of claim 5 , further comprising a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer opposing the side of the redistribution layer ...

BALL ARRANGEMENT FOR INTEGRATED CIRCUIT PACKAGE DEVICES

An integrated circuit package includes a ball arrangement that includes transmitter contact pairs arranged in a first portion of a ball grid array disposed in the integrated circuit package. Each of the transmitter contact pairs include transmitter differential signal contacts. Pairs of the transmitter contact pairs located adjacent to one another are in a staggered arrangement. The ball arrangement also includes receiver contact pairs arranged in a second portion of the ball grid array. Each of the receiver contact pairs include receiver differential signal contacts. Pairs of the receiver contact pairs located adjacent to one another are in a staggered arrangement. The ball arrangement also includes voltage supply contacts arranged at least between every two pairs of the transmitter contact pairs and the receiver contact pairs.

SEMICONDUCTOR DEVICE AND MICROPHONE

A bump-joining pad (61) is provided to the upper surface of a substrate (45), and a bump (70) of a circuit element (43) is connected to the bump-joining pad. The bump-joining pad (61) is connected to a substrate-side joining section (69) provided to a surface facing a cover by a pattern wiring (64). A microphone chip (42) is mounted on the lower surface of the cover (44). A first joining pad (a bonding pad (48), a cover-side joining section (49)) is provided to a surface of the cover (44) facing the substrate (45), and the microphone chip (42) is connected to the first joining pad by a bonding wire (50). The first joining pad of the cover (44) and the substrate-side joining section (69) of the substrate (45) are joined by a conductive material (65), and as a result, the microphone chip (42) and the circuit element (43) are electrically connected.

SEMICONDUCTOR DEVICE

A semiconductor device which can prevent an external connecting terminal and a heat dissipating member from being damaged even when an external force is applied. The semiconductor device is provided with a semiconductor element, a substrate for mounting the semiconductor element, the heat dissipating member thermally connected with the semiconductor element and fixed to the substrate, and a plurality of external connecting terminals arranged on an opposite plane to a substrate plane whereupon the heat dissipating member is arranged. A position for fixing the heat dissipating member on the substrate is substantially arranged on a circle, which has a center position of the substrate at the center and is inscribed in the substrate.

Limiting electronic package warpage with semiconductor chip lid and lid-ring

An electronic package includes a carrier, semiconductor chip, a lid, and a lid-ring. The carrier includes a top surface and a bottom surface configured to be electrically connected to a system board. The semiconductor chip is electrically connected to the top surface. The lid is attached to the top surface enclosing semiconductor chip and includes a perimeter recess. The lid-ring is juxtaposed within the perimeter recess. The lid-ring exerts a reverse bending moment upon the lid to limit warpage of the electronic package.

Semiconductor Device And Method For Manufacturing The Semiconductor Device

The invention provides a semiconductor device and a method for manufacturing the semiconductor device. The method includes the steps of: mounting a first element on a wiring substrate, placing a first heat sink on the first element with a metal material interposed between the first heat sink and the first element, attaching the first heat sink to the first element via the metal material by heating and melting the metal material, and mounting a second element on the wiring substrate after the steps of attaching the first heat sink to the first element. Through the invention, even elements in different types are mounted on a same substrate, reliability reduction of the semiconductor device can be prevented.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH PARTITIONED LOGIC AND ASSOCIATED SYSTEMS AND METHODS

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, a heat radiating plate disposed on the substrate and covering the semiconductor element, and a connection member connecting an upper surface of the semiconductor element and a lower surface of the heat radiating plate, wherein the connection member includes a first member being in contact with the upper surface of the semiconductor element and having a first melting point, a second member being in contact with the first member, having a larger area than the first member, and having a second melting point higher than the first melting point, and a third member interposed between the second member and the heat radiating plate, having an area smaller than the second member, and having a third melting point lower than the second melting point.

밀봉 부재, 이 밀봉 부재로 밀봉된 밀봉 기판 및 그의 제조 방법

... 본 발명은 필름상 또는 트레이상의 형태를 갖고, 또한 적어도 주연부(13)가 열 가소성 수지(공중합 폴리아미드계 수지 등)를 포함하는 밀봉 부재(11)로 디바이스(1)의 피밀봉 영역을 덮고, 피밀봉 영역의 내측에서 밀봉 부재(11)가 디바이스(1)의 실장 부품(3a 내지 3c)과 유리된 형태로 밀봉 부재(11)의 주연부(13)를 디바이스(1)의 기판(2)과 열 접착시켜, 밀봉 부재(11)로 디바이스(1)의 피밀봉 영역이 커버된 밀봉 디바이스를 제조한다. 본 발명에서는 공중합 폴리아미드계 수지는 C8-16알킬렌기를 갖는 장쇄 성분(C9-17락탐 및 아미노C9-17알칸카르복실산 등)에서 유래되는 단위를 포함하고 있을 수도 있다. 이 밀봉 부재는 디바이스의 소정부를 선택적으로 또한 유효하게 밀봉하여 보호할 수 있다.

STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH PARTITIONED LOGIC AND ASSOCIATED SYSTEMS AND METHODS

Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies.

Electrical package including bimetal lid

Electrical package including bimetal lid. The electrical package includes: an organic substrate; a semiconductor chip electrically connected to electrical pads on a surface of the organic substrate via a plurality of solder balls; and a lid for encapsulating the semiconductor chip on the organic substrate, wherein (i) an inner surface of a central part of the lid is connected to a surface of the semiconductor chip via a first TIM, (ii) an inner surface of an outer part of the lid is hermetically connected to the surface of the organic substrate, and (iii) the lid has a bimetal structure including at least two different metals. A circuit module is also provided.

Thermal interfaces for integrated circuit packages

A thermal interface may include a wired network made of a first TIM, and a second TIM surrounding the wired network. A heat spreader lid may include a wired network attached to an inner surface of the heat spreader lid. An IC package may include a heat spreader lid placed over a first electronic component and a second electronic component. A first thermal interface may be formed between the first electronic component and the inner surface of the heat spreader lid, and a second thermal interface may be formed between the second electronic component and the inner surface of the heat spreader lid. The first thermal interface may include a wired network of a first TIM surrounded by a second TIM, while the second thermal interface may include the second TIM, without a wired network of the first TIM. Other embodiments may be described and/or claimed.

Thermal interface material on package

A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly.

ELECTRONIC APPARATUS AND METHOD FOR FABRICATING THE SAME

STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH PARTITIONED LOGIC AND ASSOCIATED SYSTEMS AND METHODS

SEMICONDUCTOR DEVICE AND MICROPHONE

A bump-joining pad (61) is provided to the upper surface of a substrate (45), and a bump (70) of a circuit element (43) is connected to the bump-joining pad. The bump-joining pad (61) is connected to a substrate-side joining section (69) provided to a surface facing a cover by a pattern wiring (64). A microphone chip (42) is mounted on the lower surface of the cover (44). A first joining pad (a bonding pad (48), a cover-side joining section (49)) is provided to a surface of the cover (44) facing the substrate (45), and the microphone chip (42) is connected to the first joining pad by a bonding wire (50). The first joining pad of the cover (44) and the substrate-side joining section (69) of the substrate (45) are joined by a conductive material (65), and as a result, the microphone chip (42) and the circuit element (43) are electrically connected.

Power distribution for 3D semiconductor package

A method including a printed circuit board electrically coupled to a bottom of a laminate substrate, the laminate substrate having an opening extending through the entire thickness of the laminate substrate, a main die electrically coupled to a top of the laminate substrate, a die stack electrically coupled to a bottom of the main die, the die stack including one or more chips stacked vertically and electrically coupled to one another, the die stack extending into the opening of the laminate substrate, and an interposer positioned between and electrically coupled to a topmost chip and the printed circuit board, the interposer providing an electrical path from the printed circuit board to the topmost chip of the die stack.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, a heat radiating plate disposed on the substrate and covering the semiconductor element, and a connection member connecting an upper surface of the semiconductor element and a lower surface of the heat radiating plate, wherein the connection member includes a first member being in contact with the upper surface of the semiconductor element and having a first melting point, a second member being in contact with the first member, having a larger area than the first member, and having a second melting point higher than the first melting point, and a third member interposed between the second member and the heat radiating plate, having an area smaller than the second member, and having a third melting point lower than the second melting point.

Integrated circuit package and apparatus and method of producing an integrated circuit package

An integrated circuit package is disclosed. The integrated circuit package comprises an integrated circuit die having a plurality of solder bumps; and a substrate comprising a first plurality of contact pads on a first surface and a second plurality of contact pads on a second surface. The plurality of solder bumps on the integrated circuit die is coupled to the first plurality of contact pads on the first surface of the substrate, wherein at least one edge of the substrate is formed after the integrated circuit die is attached to the substrate. According to one embodiment of the invention, the at least one edge of the substrate is formed after excess substrate material is detached at designated areas. According to another aspect of the invention, an assembly fixture is disclosed. An apparatus and method for assembling an integrated circuit package are also disclosed.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

A method for manufacturing a semiconductor device is provided, the method including: mounting a first element on a wiring substrate, placing a first heat sink on the first element with a metal material interposed between the first heat sink and the first element, attaching the first heat sink to the first element via the metal material by heating and melting the metal material, and mounting a second element on the wiring substrate after the steps of attaching the first heat sink to the first element.

Apparatuses and methods for heat transfer from packaged semiconductor die

Apparatuses and methods for heat transfer from packaged semiconductor die are described. For example, an apparatus may include a plurality of die in a stack, and a barrier in close proximity to at least an edge of each of the plurality of die. The apparatus may further include fill material in spaces between adjacent die of the plurality of die and in between the plurality of die and the barrier.

SEMICONDUCTOR PACKAGE STRUCTURE

Various embodiments relating to semiconductor package structures having reduced thickness while maintaining rigidity are provided. In one embodiment, a semiconductor package structure includes a substrate including a surface, a semiconductor die including a first interface surface connected to the surface of the substrate and a second interface surface opposing the first interface surface, a mold compound applied to the substrate surrounding the semiconductor die. The second interface surface of the semiconductor die is exposed from the mold compound. The semiconductor package structure includes a heat dissipation cover attached to the second interface surface of the semiconductor die and the mold compound.

Wafer-level process for fabricating photoelectric modules

A wafer-level process for fabricating a plurality of photoelectric modules is provided. The wafer-level process includes at least following procedures. Firstly, a wafer including a plurality of chips arranged in an array is provided. Next, a plurality of photoelectric devices are mounted on the chips. Next, a cover plate including a plurality of covering units arranged in an array is provided. Next, a plurality of light guiding mediums are formed over the cover plate. Next, the cover plate is bonded with the wafer by an adhesive, wherein each of the covering units covers and bonds with one of the chips, and the light guiding mediums are sandwiched between the cover plate and the wafer. Then, the wafer and the cover plate are diced to obtain the plurality of photoelectric modules.

Hermetisches Schaltungsgehäuse ohne Leitungsrahmen

Ein Halbleiterchipgehäuse mit offenem Hohlraum, das anschlussleitungsfrei ist und keinen Leitungsrahmen aus Metall wie konventionelle Gehäuse hat. Das Fehlen eines Leitungsrahmens minimiert Leckpfade und erlaubt es dem neuen Gehäuse, einfacher als ein hermetisches Gehäuse hergestellt zu werden. Ein beidseitig isolierender oder dielektrischer Film wird als die Basisverbindung zwischen einem Halbleiterchip und Außenkontakten eingesetzt. Elektrische Verbindung von der Oberseite des Films zu der Unterseite des Films wird durch leitende Mikrobohrungen hergestellt. Der Halbleiterchip wird auf einer Auflage in einer zentralen Öffnung in dem Film angebracht und an Kontaktstellen auf dem Film drahtgebondet. Nach dem Anbringen auf dem Chip wird eine Abdeckung oder ein Deckel an dem Film befestigt, um die Anordnung einzuschließen und Hermetizität des Gehäuses zu erhalten.

Heat spreading structures for integrated circuits

A heat spreader structure includes a planar portion and a slanted portion. The slanted portion extends at an angle from an edge of the planar portion. The first slanted portion includes a first slot. A second heat spreader structure includes a planar member, a first edge member and a second edge member. The first edge member extends only perpendicularly from a first edge of the planar member whereas the second edge member extends from the second edge of the planar member and has a slanted surface with respect to that of the planar member. In addition to that, the first and second heat spreader structure may be formed using different manufacturing methods.

파티션화된 로직을 가진 적층 반도체 다이 조립체 및 관련 시스템 및 방법

... 파티션화된 로직 다이들 사이에 적층되는 메모리 다이들을 가진 적층 반도체 다이 조립체들과, 관련 시스템 및 방법이 여기서 개시된다. 일 실시예에서, 반도체 다이 조립체는 제 1 로직 다이와, 제 2 로직 다이와, 인클로저를 형성하는 열전도성 케이싱을 포함할 수 있다. 메모리 다이들의 스택은 인클로저 내에, 그리고, 상기 제 1 로직 다이와 제 2 로직 다이 사이에 배치될 수 있다.

LEAD FRAMELESS HERMETIC CIRCUIT PACKAGE

A open cavity semiconductor chip package that is leadless and does not have a metal lead frame as in conventional packages. The absence of a lead frame minimizes leakage paths and allows the novel package to be more readily fabricated as a hermetic package. A dual sided insulative or dielectric film is employed as the base interconnect between a semiconductor chip and outside contacts. Electrical connection from the top side of the film to the bottom side of the film is made through conductive micro-vias. The semiconductor chip is mounted on a paddle in a central opening in the film and wire bonded to pads on the film. After mounting of the chip, a cover or lid is attached to the film to encapsulate the assembly and maintain hermeticity of the package.

Electronic apparatus and method for fabricating the same

An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.

PACKAGING FOR HIGH SPEED CHIP TO CHIP COMMUNICATION

Disclosed are chip packaging structures for high speed chip to chip and chip to carrier communications and methods of making such structures. The chip packaging structures do not require an interposer containing through silicon vias and/or provide structures having reduced warping.

CERAMIC ELECTRONIC COMPONENT AND ITS MANUFACTURING METHOD

PROBLEM TO BE SOLVED: To provide a ceramic electronic component which comprises a cover for covering a surface mounting component and further comprises an external electrode at a position protruded from a mounting surface of a ceramic substrate to a mother board, so that the substrate can be mounted while securing a gap between the mounting surface and the mother board, and to provide its manufacturing method. SOLUTION: On a first principal surface F1 of the ceramic substrate 1, a first surface mounting component 14 (14a, 14b) is mounted, and further a case 18 for covering the first surface mounting component 14 (14a, 14b) is provided. On a second principal surface F2, the external electrode 5 is provided in the ceramic electronic component A. In this ceramic electronic component A, a step 30 for fixing the case 18 is provided to the first principal surface F1, a protrusion 40 is provided to the second principal surface F2, and further the external electrode 5 is provided on the protrusion ...

Molded high density electronic packaging structure for high performance applications

A thermally enhanced ball grid array package is disclosed. The package includes a base layer element and a flip chip die mounted on the base layer element. The die has a first surface electrically coupled to the base layer element, a second surface opposite to the first surface, and lateral sides. A molding compound encapsulates the base layer element and the lateral sides of the die. A surface is formed of the second surface of the die and an upper surface of the molding compound. A material is disposed on the surface, and a heat spreader is mounted on the material.

파티션화된 로직을 가진 적층 반도체 다이 조립체 및 관련 시스템 및 방법

파티션화된 로직 다이들 사이에 적층되는 메모리 다이들을 가진 적층 반도체 다이 조립체들과, 관련 시스템 및 방법이 여기서 개시된다. 일 실시예에서, 반도체 다이 조립체는 제 1 로직 다이와, 제 2 로직 다이와, 인클로저를 형성하는 열전도성 케이싱을 포함할 수 있다. 메모리 다이들의 스택은 인클로저 내에, 그리고, 상기 제 1 로직 다이와 제 2 로직 다이 사이에 배치될 수 있다.

Thermal interface material on package

A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly.

Ball arrangement for integrated circuit package devices

An integrated circuit package includes a ball arrangement that includes transmitter contact pairs arranged in a first portion of a ball grid array disposed in the integrated circuit package. Each of the transmitter contact pairs include transmitter differential signal contacts. Pairs of the transmitter contact pairs located adjacent to one another are in a staggered arrangement. The ball arrangement also includes receiver contact pairs arranged in a second portion of the ball grid array. Each of the receiver contact pairs include receiver differential signal contacts. Pairs of the receiver contact pairs located adjacent to one another are in a staggered arrangement. The ball arrangement also includes voltage supply contacts arranged at least between every two pairs of the transmitter contact pairs and the receiver contact pairs.

PACKAGE SUBSTRATE CAPABLE OF IMPROVING COMBINING FORCE OF A METAL CAP AND A PRINTED CIRCUIT BOARD

PURPOSE: A package substrate is provided to secure reliability from external impact by combining a metal cap on the upper end of a wall printed circuit board which is combined with a printed circuit board. CONSTITUTION: A part is mounted on a connection terminal. A wire(230) is combined with the part. A wall printed circuit board(240) is combined with a conductive adhesive layer. The wall printed circuit board covers the part. A metal cap(250) is combined with the upper part of the wall printed circuit board in order to cover the part. COPYRIGHT KIPO 2012 ...

Semiconductor device and manufacturing method thereof

Provided are a semiconductor device and a method of manufacturing the same. A carrier is removed after a first semiconductor die and a second semiconductor die are stacked on each other, and then a first encapsulant is formed, so that the carrier may be easily removed when compared to approaches in which a carrier is removed from a wafer having a thin thickness.

SEMICONDUCTOR PACKAGE STRUCTURES AND METHODS OF FORMING THE SAME

A ring structure on a package substrate is divided into at least four different components, including a plurality of first pieces and a plurality of second pieces. By dividing the ring structure into at least four different components, the ring structure reduces flexibility of the package substrate, which thus reduces stress on a molding compound (e.g., in a range from approximately 1% to approximately 10%). As a result, molding cracking is reduced, which reduces defect rates and increases yield. Accordingly, raw materials, power, and processing resources are conserved that would otherwise be consumed with manufacturing additional packages when defect rates are higher.

Printed circuit board

A printed circuit board includes: a printed wiring board including an insulating layer wherein a recessed part is provided on a top surface of the insulating layer, and a printed conductor provided inside the recessed part; a bare chip part mounted in the recessed part and electrically connected to the printed conductor; an electronic part mounted on the top surface of the printed wiring board other than the recessed part; and a cap fixed to the top surface of the printed wiring board and hollow-sealing the bare chip part mounted in the recessed part, wherein using a height of the top surface of the printed wiring board as a reference, a height of a top surface of the cap is equal to or below a maximum height of a top surface of the electronic part.

Packaging for high speed chip to chip communication

Disclosed are chip packaging structures for high speed chip to chip and chip to carrier communications and methods of making such structures. The chip packaging structures do not require an interposer containing through silicon vias and/or provide structures having reduced warping.

Semiconductor device package and a method of manufacturing the same

A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.

Semiconductor package

Disclosed is a semiconductor package comprising a substrate, a semiconductor chip on the substrate, a molding layer on the substrate covering the semiconductor chip, and a shield layer on the molding layer. The shield layer includes a polymer in which a plurality of conductive structures and a plurality of nano-structures are distributed wherein at least some of the conductive structures are connected to one another.

Semiconductor device and manufacturing method thereof

Provided are a semiconductor device and a method of manufacturing the same. A carrier is removed after a first semiconductor die and a second semiconductor die are stacked on each other, and then a first encapsulant is formed, so that the carrier may be easily removed when compared to approaches in which a carrier is removed from a wafer having a thin thickness.

APPARATUSES AND METHODS FOR HEAT TRANSFER FROM PACKAGED SEMICONDUCTOR DIE

Apparatuses and methods for heat transfer from packaged semiconductor die are described. For example, an apparatus may include a plurality of die in a stack, and a barrier in close proximity to at least an edge of each of the plurality of die. The apparatus may further include fill material in spaces between adjacent die of the plurality of die and in between the plurality of die and the barrier.

Shielded package assemblies with integrated capacitor

Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

High reliability wafer level semiconductor packaging

Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, a redistribution layer coupled to a second side of the semiconductor die, and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer coupled to the semiconductor die. The adhesive may be located in a trench around a perimeter of the semiconductor die and located in a corresponding trench around a perimeter of the glass lid.

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor element; a board where the semiconductor element is mounted; a heat radiation member thermally connected to the semiconductor element and fixed to the board; and a plurality of outside connection terminals provided on a surface opposite to a surface where the heat radiation member is provided of the board; wherein a fixing position where the heat radiation member is fixed to the board is substantially positioned on an inscribing circle; and the center of the inscribing circle is a center position of the board and the inscribing circle inscribes the heat radiation member.

Semiconductor device having multiple bonded heat sinks

A method for manufacturing a semiconductor device is provided, the method including: mounting a first element on a wiring substrate, placing a first heat sink on the first element with a metal material interposed between the first heat sink and the first element, attaching the first heat sink to the first element via the metal material by heating and melting the metal material, and mounting a second element on the wiring substrate after the steps of attaching the first heat sink to the first element.

Semi-hermetic semiconductor package

A method of assembling a semi-hermetic semiconductor package includes bonding a semiconductor die having bond pads to a top side of a base region of a package substrate having vertical side walls that are hollow which define an inner open volume (gap) having an adhesive or thermoplastic material therein. There are a plurality of metal terminals providing top terminal contacts on the top side of the base region and bottom terminal contacts on a bottom side or below the base region. The bond pads are coupled to the top terminal contacts. A lid is placed which provides a top for the semiconductor package, where the lid extends to vertically oriented end protrusions so that the protrusions are positioned within the adhesive or thermoplastic material to secure the protrusions within the adhesive or thermoplastic material to provide a seal for the semiconductor package.

INTEGRATED CIRCUIT PACKAGE INCLUDING WIRE BOND AND ELECTRICALLY CONDUCTIVE ADHESIVE ELECTRICAL CONNECTIONS

A system may include a package defining a cavity and an integrated circuit (IC) disposed within the cavity. The package may include a first electrically conductive package contact and a second electrically conductive package contact. The IC may include a first electrically conductive IC contact and a second electrically conductive IC contact. The system also may include a wire bond extending between and electrically connecting the first electrically conductive package contact and the first electrically conductive IC contact. The system further may include an electrically conductive adhesive extending between and electrically connecting the second electrically conductive package contact and the second electrically conductive IC contact. Use of wire bonds and electrically conductive adhesive may increase an interconnect density between the IC and the package, while not requiring an increase in size of the IC or a decrease in pitch between wire bonds.

Thermal interface material on package

A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly.

Semiconductor device and manufacturing method thereof

Provided are a semiconductor device and a method of manufacturing the same. A carrier is removed after a first semiconductor die and a second semiconductor die are stacked on each other, and then a first encapsulant is formed, so that the carrier may be easily removed when compared to approaches in which a carrier is removed from a wafer having a thin thickness.

Semiconductor package and manufacturing method thereof

A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.

Printed circuit board

POWER DISTRIBUTION FOR 3D SEMICONDUCTOR PACKAGE

A method including a printed circuit board electrically coupled to a bottom of a laminate substrate, the laminate substrate having an opening extending through the entire thickness of the laminate substrate, a main die electrically coupled to a top of the laminate substrate, a die stack electrically coupled to a bottom of the main die, the die stack including one or more chips stacked vertically and electrically coupled to one another, the die stack extending into the opening of the laminate substrate, and an interposer positioned between and electrically coupled to a topmost chip and the printed circuit board, the interposer providing an electrical path from the printed circuit board to the topmost chip of the die stack.

Wafer-level process for fabricating photoelectric modules

A wafer-level process for fabricating a plurality of photoelectric modules is provided. The wafer-level process includes at least following procedures. Firstly, a wafer including a plurality of chips arranged in an array is provided. Next, a plurality of photoelectric devices are mounted on the chips. Next, a cover plate including a plurality of covering units arranged in an array is provided. Next, a plurality of light guiding mediums are formed over the cover plate. Next, the cover plate is bonded with the wafer by an adhesive, wherein each of the covering units covers and bonds with one of the chips, and the light guiding mediums are sandwiched between the cover plate and the wafer. Then, the wafer and the cover plate are diced to obtain the plurality of photoelectric modules.

Electronic apparatus and method for fabricating the same

An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.

Radio frequency shielding cavity package

A radio-frequency shielding cavity package is set forth along with a method of manufacturing thereof. According to one embodiment, the radio-frequency shielding cavity package comprises a metallic leadframe and plastic molded body. The leadframe has a plurality of contact pads extending from top to bottom surfaces thereof, at least one contact pad on the top surface being surrounded by metal for shielding the contact pad from external electric fields. A plated inner ring surrounds a die attach pad on the leadframe. The die attach pad receives a semiconductor die adapted to be wire bonded to the inner ring and plurality of contact pads. A plated outer ring defines a ground plane circumscribing the perimeter of the leadframe. A cap is connected to the ground plane for enclosing and protecting the wire bonded semiconductor device die and providing electrical grounding thereof.

THERMAL INTERFACE MATERIAL ON PACKAGE

A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly. 1. A method , comprising:dispensing a thermal interface material (TIM) on an electronic assembly;placing a lid on the TIM, over the electronic assembly;pressing the lid onto the electronic assembly to perform a packaged assembly;curing the packaged assembly; andperforming a sonoscan of the packaged assembly to determine a presence of voiding in the TIM.2. The method of claim 1 , further comprising removing volatile species of the TIM prior to lid placement.3. The method of claim 2 , wherein the volatile species comprises cyclic siloxanes and decyl trimethoxysilane.4. The method of claim 2 , wherein the removal of the volatile species comprises maintaining the TIM at room temperature for a predetermined time period prior to the lid placement.5. The method of claim 4 , wherein the predetermined time period is about 60 minutes.6. The method of claim 2 , wherein the removal of the volatile species comprises subjecting the TIM to a predetermined temperature claim 2 , in an oven claim 2 , for a predetermined time period.7. The method of claim 6 , wherein the predetermined temperature is about 45° C. to 55° C. and the predetermined time period is about 15-30 minutes.8. The method of claim 6 , wherein the predetermined temperature is about 50° C. and the predetermined time period is about 20 minutes.9. The method of claim 6 , wherein the predetermined temperature is about 50° C. and the predetermined time period is about 15 minutes.10. The method of claim 2 , wherein the removal ...

Thinned integrated circuit device and manufacturing process for the same

A thinned integrated circuit device and manufacturing process for the same are disclosed. The manufacturing process includes forming a through-silicon via (TSV) on a substrate, a first terminal of the TSV is exposed on a first surface of the substrate, disposing a bump on the first surface of the substrate to make the bump electrically connected with the TSV, disposing an integrated circuit chip (IC) on the bump so that a first side of the IC is connected to the bump, disposing a thermal interface material (TIM) layer on a second side of the IC opposite to the first side of the IC, attaching a heat-spreader cap on the IC by the TIM layer, and backgrinding a second surface of the substrate to expose the TSV to the second surface of the substrate while carrying the heat-spreader cap.

SHIELDED PACKAGE ASSEMBLIES WITH INTEGRATED CAPACITOR

Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor. 1. A method for electrostatically storing energy in a package assembly including a chip stack and a lid , the method comprising:storing a first charge on a first plate of a capacitor provided by a flange of the lid that is coupled with the chip stack; andstoring a second charge on a second plate of the capacitor provided by a section of a conductive layer located along a sidewall of a first substrate of the package assembly that supports and laterally surrounds the chip stack, wherein the flange of the first plate and the second plate are laterally separated by a gap composed of dielectric material having a permittivity, and the first substrate is a laminated substrate containing a through-hole in which at least a portion of the chip stack and the lid and flange are located.2. The method of claim 1 , wherein the conductive layer is ring-shaped.3. The method of claim 1 , further comprising a solder ball on the conductive layer of the first substrate.4. The method of claim 1 , wherein the lid is cup shaped.5. The method of claim 1 , wherein the dielectric material that provides the gap is air.6. The method of claim 1 , wherein the ...

Method and apparatus for high temperature semiconductor device packages and structures using a low temperature process

A semiconductor device package that incorporates a combination of ceramic, organic, and metallic materials that are coupled using silver is provided. The silver is applied in the form of fine particles under pressure and a low temperature. After application, the silver forms a solid that has a typical melting point of silver, and therefore the finished package can withstand temperatures significantly higher than the manufacturing temperature. Further, since the silver is an interfacial material between the various combined materials, the effect of differing material properties between ceramic, organic, and metallic components, such as coefficient of thermal expansion, is reduced due to low temperature of bonding and the ductility of the silver.

Cavity package with pre-molded cavity leadframe

A cavity package is disclosed comprising a metal leadframe, a metal ring connected to the metal leadframe, a plastic body molded to the metal leadframe forming a substrate cavity including an exposed die attach pad of the leadframe for affixing a semiconductor device, exposed lead fingers of the leadframe for wire bonding to the semiconductor device and an external circuit, and an exposed top surface of the metal ring, and a metal cap for closing and encapsulating the substrate cavity. The metal ring is integrated into the pre-molded cavity leadframe for providing an electrical ground path from the metal cap to the die attach pad and permitting attachment of the metal cap to the pre-molded leadframe using solder reflow.

STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH PARTITIONED LOGIC AND ASSOCIATED SYSTEMS AND METHODS

Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies. 1. A semiconductor die assembly , comprising:a first die including a controller; a central portion beneath a footprint of the first die;', 'a peripheral portion extending beyond the footprint of the first die;', 'a circuit component disposed in the central portion; and', 'a communication component disposed in the peripheral portion and configured to deserialize serial input data into a plurality of input data streams;, 'a second die including—'}a stack of third dies positioned on the second die, wherein the first die is positioned on the stack of third dies;a plurality of first through-stack interconnects extending through the entire stack of third dies to couple the controller to the communication component, wherein the first through-stack interconnects are configured to transmit (a) the plurality of input data streams from the communication component to the controller and (b) a plurality of output data streams from the controller to the communication component;a plurality of second through-stack interconnects extending through the entire stack of third dies to couple the first die to the circuit component; and{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'a casing attached to the peripheral portion of the second die and configured to dissipate heat from the communication component during operation. The semiconductor die assembly of wherein the casing defines a cavity, and wherein the first die and the third dies are positioned in the cavity.'}3. The semiconductor die assembly of wherein the first die includes a bulk portion of a semiconductor substrate ...

METHOD FOR MOUNTING COMPONENT

A method includes attaching a discrete component on a circuit board with a first glue, attaching an integrated circuit to the circuit board using a third glue, and attaching a cap to the circuit board using a second glue. The first glue has a composition such that it does not interact electrically with the second glue and does not interact electrically with the third glue. 1. A method comprising:attaching a discrete component on a circuit board with a first glue;attaching an integrated circuit to the circuit board using a third glue; andattaching a cap to the circuit board using a second glue, wherein the first glue has a composition such that it does not interact electrically with the second glue and does not interact electrically with the third glue.2. The method according to claim 1 , wherein the first glue is an electrically insulating glue.3. The method according to claim 2 , wherein the first glue is identical to the second glue.4. The method according to claim 1 , wherein the second glue is an electrically insulating glue.5. The method according to claim 1 , wherein the third glue is an electrically insulating glue.6. The method according to claim 5 , wherein the first glue is identical to the third glue.7. The method according to claim 1 , wherein the discrete component is a passive component.8. The method according to claim 1 , wherein the discrete component is a component comprising a plurality of contacts accessible from an upper face that faces away from the circuit board.9. The method according to claim 1 , wherein the second glue is an epoxy-type polyepoxide-based glue.10. The method according to claim 1 , wherein the third glue is an epoxy-type polyepoxide-based glue.11. The method according to claim 1 , wherein the discrete component is a surface-mount component.12. A method comprising:attaching a discrete component to a circuit board with a first glue, the discrete component having first and second electrical contacts that extend from a bottom ...

High reliability wafer level semiconductor packaging

Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, a redistribution layer coupled to a second side of the semiconductor die, and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer coupled to the semiconductor die. The adhesive may be located in a trench around a perimeter of the semiconductor die and located in a corresponding trench around a perimeter of the glass lid.

HIGH RELIABILITY WAFER LEVEL SEMICONDUCTOR PACKAGING

Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, a redistribution layer coupled to a second side of the semiconductor die, and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer coupled to the semiconductor die. The adhesive may be located in a trench around a perimeter of the semiconductor die and located in a corresponding trench around a perimeter of the glass lid. 1. A semiconductor package comprising:a semiconductor die comprising a first side and a second side;a first trench comprised in the first side of the semiconductor die, the trench positioned outside an active area of the die;a lid comprising a second trench, the lid fixedly coupled to a first side of the semiconductor die by an adhesive;wherein the adhesive is comprised in the first trench in the first side of the semiconductor die and simultaneously comprised in the second trench positioned around a perimeter of the glass lid.2. The semiconductor package of claim 1 , wherein the adhesive is selected from the group consisting of thermal curable resin claim 1 , epoxy claim 1 , ultraviolet light curable resin and any combination thereof.3. The semiconductor package of claim 2 , wherein the adhesive is cured.4. The semiconductor package of claim 1 , wherein the adhesive is evenly distributed within the first trench and the second trench.5. The semiconductor package of claim 1 , wherein the adhesive extends out from the first trench and the second trench to further bond the lid and the semiconductor die.6. The semiconductor package of claim 1 , further comprising a redistribution layer coupled to the second side of the semiconductor die.7. The semiconductor package of claim 5 , further comprising a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer opposing the side of the redistribution layer ...

SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME

A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel. 1. A semiconductor device package , comprising:a supporting element;a plate disposed on the supporting element;a semiconductor device disposed under the plate; andwherein the supporting element and the plate define an opening exposed to outside of the semiconductor device package.2. The semiconductor device package of claim 1 , wherein the plate is a transparent plate.3. The semiconductor device package of claim 1 , further comprising an adhesive disposed between the supporting element and the plate and surrounding the semiconductor device claim 1 , wherein the adhesive has a gap.4. The semiconductor device package of claim 3 , wherein the supporting element has a first upper surface and the first portion has a second upper surface claim 3 , wherein the second upper surface of the first portion is lower than the first upper surface of the supporting element.5. The semiconductor device package of claim 1 , further comprising a lid disposed on the supporting element and surrounding the plate.6. The semiconductor device package of claim 5 , wherein the lid comprises a first portion covering a periphery of the plate.7. The semiconductor device package of claim 1 , wherein an opaque film is disposed on a surface of the plate.8. The semiconductor device package of claim 5 , wherein the supporting element claim 5 , the plate claim 5 , and the lid define the opening.9. The semiconductor device package of claim 1 , wherein the supporting element comprises a through via.10. The semiconductor device package of claim 1 , wherein the supporting element partially overlaps with the plate in a cross sectional perspective.11. A semiconductor device package claim 1 , comprising:a supporting element ...

Methods for forming semiconductor device packages

A semiconductor device package that incorporates a combination of ceramic, organic, and metallic materials that are coupled using silver is provided. The silver is applied in the form of fine particles under pressure and a low temperature. After application, the silver forms a solid that has a typical melting point of silver, and therefore the finished package can withstand temperatures significantly higher than the manufacturing temperature. Further, since the silver is an interfacial material between the various combined materials, the effect of differing material properties between ceramic, organic, and metallic components, such as coefficient of thermal expansion, is reduced due to low temperature of bonding and the ductility of the silver.

Shielded package assemblies with integrated capacitor

Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

Radio frequency communication systems

A packaged radio frequency (RF) module is disclosed. The module can include a substrate, a first die electrically and mechanically attached to the substrate, a second die electrically and mechanically attached to the substrate, an encapsulating material, and a lid attached to the substrate. The first die comprises a silicon-based die, such as an RF switch die, and the second die comprises a compound semiconductor die, such as an RF amplifier. The encapsulating material can protect electrical connections between the first die and the substrate. The substrate and the lid at least partially define an air cavity within which the first and the second die are mounted. An active surface of the second die is exposed to the air cavity.

Semiconductor device and microphone

在基板45的上表面设置凸点接合焊盘61，将电路元件43的凸点70连接在凸点接合焊盘61上。凸点接合焊盘61通过图案布线64与基板侧接合部69连接，并且该基板侧接合部69设置在与罩体44相对置的相对置面。在罩体44的下表面安装有麦克风芯片42。在罩体44的与基板45相对置的面设置第一接合用焊盘（焊接用焊盘48、罩体侧接合部49），麦克风芯片42通过焊线50与第一接合用焊盘连接。罩体44的第一接合用焊盘和基板45的基板侧接合部69通过导电性材料65接合，结果使麦克风芯片42和电路元件43电连接。

Heat spreader having thermal interface material retainment

In embodiments described herein, an integrated circuit (IC) package is provided. The IC package may include a substrate, an IC die, and a heat spreader. The IC die may have opposing first and second surfaces, where the first surface of the IC die is coupled to a surface of the substrate. The heat spreader may have a surface coupled to the second surface of the IC die by a thermal interface (TI) material. The surface of the heat spreader may have a micro-recess which may include a micro-channel or a micro-dent to direct a flow of TI material towards or away from a predetermined area of the second surface of the IC die based on temperatures of the substrate, the IC die, and/or the heat spreader.

Semiconductor packages

本实用新型涉及半导体封装。所述半导体封装包括：半导体管芯；和通过粘合剂固定地耦接到所述半导体管芯第一侧的玻璃盖；其中所述粘合剂包含在位于所述半导体管芯周边处的所述半导体管芯的沟槽中，并且包含在位于所述玻璃盖周边处的围绕所述玻璃盖的相应沟槽中。本实用新型解决的一个技术问题是增加半导体装置之间接合的强度。本实用新型实现的一个技术效果是提供改进的半导体封装。

Hermetic-sealing package member, production method therefor, and hermetically-sealed package production method using this hermetic-sealing package member

본 발명은 기판과, 기판 상에 형성된 밀봉 영역을 획정하는 적어도 1개의 프레임 형상의 밀봉재로 이루어지는 기밀 밀봉 패키지 부재에 있어서, 밀봉재는, 순도가 99.9중량％ 이상이며, 평균 입경이 0.005㎛∼1.0㎛인 금, 은, 팔라듐, 백금으로부터 선택되는 1종 이상의 금속 분말이 소결하여 이루어지는 소결체로 형성된 것이며, 또한, 밀봉 영역으로부터 영역 외를 향한 임의 단면에 대하여, 밀봉재의 상단부 길이가 하단부 길이보다도 짧게 되어 있는 기밀 밀봉 패키지 부재이다. 밀봉재의 단면 형상으로서는, 일정 높이를 갖는 기초부와, 기초부로부터 돌출되는 적어도 1개의 산부를 포함하는 것이나, 밀봉재의 하단부 길이를 저변으로 하는 대략 삼각 형상의 산부로 되는 것 등을 들 수 있다. 본 발명은 금속 분말 소결체를 밀봉재로서 이용한 기밀 밀봉 패키지 부재이며, 기밀 밀봉 시의 하중을 저감하면서도 충분한 밀봉 효과를 발휘할 수 있는 것이다. The present invention provides a hermetic seal package member comprising a substrate and at least one frame-shaped seal member defining a seal region formed on the substrate, wherein the seal member has a purity of 99.9 wt% or more, an average particle diameter of 0.005 mu m to 1.0 mu m And the length of the upper end portion of the sealing material is shorter than the length of the lower end portion of the sintered body formed by sintering at least one metal powder selected from gold, silver, palladium, and platinum. Tight sealed package member. Examples of the cross-sectional shape of the sealing material include a base portion having a predetermined height and at least one protruding portion protruding from the base portion, and an approximately triangular protruding portion having a bottom end length of the sealing material. The present invention is a hermetically sealed package member using a metal powder sintered body as a sealing material, and it is possible to exhibit a sufficient sealing effect while reducing the load during hermetic sealing.

Manufacturing method of ceramic electronic component

Mold sealing glue for chip packaging and packaging structure

本申请公开了一种芯片封装用模封胶及封装结构，其中模封胶采用的环氧树脂中具有聚醚等柔性单元，结合固化剂和稀释剂等成分的复配，实现了良好的柔韧性和强度，且有效降低了翘曲，其中翘曲可降低至0mm，模量可达8GPa以上，具有良好的硅接着力，可有效保护硅片不因翘曲而弯曲裂纹。并且，通过加入对叔丁基苯酚型环氧树脂稀释剂，可进一步有效降低单官能脂肪族稀释剂对固化体系的影响，能进一步改善模封胶的柔韧性和模量。

Manufacturing method of pressure sensor package

Electronic equipment and its manufacture method

本发明公开了一种电子设备及其制造方法。该电子设备包括：具有第一端子的第一电子部件，具有与第一端子相对的第二端子的第二电子部件，以及将第一端子与第二端子接合的接合部。接合部包含极状化合物，该极状化合物在第一端子与第二端子彼此相对的方向上延伸。接合部包含极状化合物，使得接合部的强度提高。当第一端子与第二端子接合时，使第一电子部件和第二电子部件中的一个电子部件的温度高于另一个电子部件的温度。在这种状态中冷却并且固化接合材料。通过这样做，形成极状化合物。

Airtight-sealing package member, production method therefor, and airtight-sealed package production method using this airtight-sealing package member

本发明提供一种气密性密封封装体构件，是包含基板和形成于基板上的划定密封区域的至少1个框状的密封材料的气密性密封封装体构件，密封材料由将纯度为99.9重量％以上、平均粒径为0.005μm～1.0μm的选自金、银、钯、铂中的一种以上的金属粉末烧结而成的烧结体形成，此外，对于从密封区域朝向区域外的任意截面，密封材料的上端长度比下端长度短。作为密封材料的截面形状，可以举出包含具有一定高度的基部和从基部突出的至少一个山部的形状、或以密封材料的下端长度作为底边的近似三角形的山部的形状等。本发明是利用金属粉末烧结体作为密封材料的气密性密封封装体构件，可以在降低气密性密封时的载荷的同时也获得充分的密封效果。

Semiconductor package

반도체 패키지가 제공된다. 반도체 패키지는 제1 기판, 제1 기판 상에 배치되는 제1 반도체 칩, 제1 반도체 칩 상에 배치되는 인터포저, 제1 기판과 인터포저 사이에서 제1 반도체 칩과 제1 수평 방향으로 이격되고, 제1 기판과 인터포저를 직접 전기적으로 연결하는 연결부, 연결부와 제1 반도체 칩 사이에 배치되는 커패시터, 및 제1 부분 및 제1 부분과 제1 수평 방향으로 이격된 제2 부분을 포함하고, 제1 부분은 연결부와 커패시터 사이에 배치되고, 제2 부분은 커패시터와 제1 반도체 칩 사이에 배치되고, 제1 부분과 제2 부분 사이에 커패시터의 적어도 일부가 삽입되는 가이드 패턴을 포함한다.

Lead frameless hermetic circuit package

Semiconductor packages

本实用新型涉及半导体封装。所述半导体封装包括：半导体管芯；和通过粘合剂固定地耦接到所述半导体管芯第一侧的玻璃盖；其中所述粘合剂包含在位于所述半导体管芯周边处的所述半导体管芯的沟槽中，并且包含在位于所述玻璃盖周边处的围绕所述玻璃盖的相应沟槽中。本实用新型解决的一个技术问题是增加半导体装置之间接合的强度。本实用新型实现的一个技术效果是提供改进的半导体封装。

半导体器件

本公开的各实施例涉及半导体器件。根据一个实施例的一种半导体器件包括：具有芯绝缘层的布线衬底；安装在布线衬底的上表面上的半导体芯片；形成在布线衬底的下表面上的多个焊球；以及散热器，该散热器具有经由第一粘合层固定到半导体芯片的后表面的第一部分和位于第一部分周围并且经由第二粘合层固定到布线衬底的第二部分。这里，多个焊球的一部分布置在与散热器的第二部分和第二粘合层中的每一者交叠的位置处。此外，第二粘合层的第二厚度大于第一粘合层的第一厚度的两倍。

半導体装置

【課題】半導体装置の性能を向上させる。【解決手段】一実施の形態に係る半導体装置ＰＫＧ１は、コア絶縁層を有する配線基板ＳＵＢ１と、配線基板ＳＵＢ１の上面２ｔに搭載された半導体チップＣＨＰ１と、配線基板ＳＵＢ１の下面に形成された複数の半田ボールと、接着層ＢＮＤ１を介して半導体チップＣＨＰ１の裏面３ｂに固定された部分ＬＩＤｐ１、および部分ＬＩＤｐ１の周囲に位置し、且つ、接着層ＢＮＤ２を介して配線基板ＳＵＢ１に固定された部分ＬＩＤｐ２を有する放熱板ＬＩＤと、を含でいる。複数の半田ボールのうちの一部は、部分ＬＩＤｐ２および接着層ＢＮＤ２と重畳する位置に配置されている。接着層ＢＮＤ２の厚さＴ２は、接着層ＢＮＤ１の厚さＴ１の２倍よりも大きい。【選択図】図５

반도체 장치

반도체 장치의 성능을 향상시킨다. 일 실시 형태에 관한 반도체 장치 PKG1은, 코어 절연층을 갖는 배선 기판 SUB1과, 배선 기판 SUB1의 상면(2t)에 탑재된 반도체 칩 CHP1과, 배선 기판 SUB1의 하면에 형성된 복수의 땜납 볼과, 접착층 BND1을 통해 반도체 칩 CHP1의 이면(3b)에 고정된 부분 LIDp1, 및 부분 LIDp1의 주위에 위치하고, 또한, 접착층 BND2를 통해 배선 기판 SUB1에 고정된 부분 LIDp2를 갖는 방열판 LID를 포함하고 있다. 복수의 땜납 볼 중 일부는, 부분 LIDp2 및 접착층 BND2와 중첩되는 위치에 배치되어 있다. 접착층 BND2의 두께 T2는, 접착층 BND1의 두께 T1의 2배보다도 크다.

Semiconductor Device and Method Forming Same

Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes a package component with one or more integrated circuits adhered to a package substrate, a hybrid thermal interface material utilizing a combination of polymer based material with high elongation values and metal based material with high thermal conductivity values. The polymer based thermal interface material placed on the edge of the package component contains the metal based thermal interface material in liquid form.

Radio frequency module

Shielded package assemblies with integrated capacitor

Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

電子封裝件及其製法

一種電子封裝件，係於一承載結構上設置一封裝模組及一屏蔽件，以令該屏蔽件遮蓋該封裝模組之上方與側面，以止擋該封裝模組向外之輻射，避免該承載結構上之其它電子組件遭受該封裝模組之電磁干擾而無法正常傳輸之問題。

電子封裝件及其製法

一種電子封裝件，係於一承載結構上設置一封裝模組及一屏蔽件，以令該屏蔽件遮蓋該封裝模組之上方與側面，以止擋該封裝模組向外之輻射，避免該承載結構上之其它電子組件遭受該封裝模組之電磁干擾而無法正常傳輸之問題。

Electronic package and manufacturing method thereof

An electronic package is provided, in which a package module and a shielding member are disposed on a carrier structure, such that the shielding member covers a top surface and side surfaces of the package module to block the radiation outward from the package module and prevent problem that other electronic components on the carrier structure cannot be transmitted signals normally due to the electromagnetic interference of the package module.

Electronic devices and methods of manufacturing electronic devices

In one example, an electronic device includes a substrate having a substrate top side, a substrate bottom side opposite to the substrate top side. A first electronic component is connected to the substrate top side and having a first electronic component top side distal to the substrate top side. A second electronic is connected to the substrate top side, laterally spaced apart from the first electronic component, and having a second electronic component top side distal to the substrate top side. A lid is connected to the substrate top side, covering the first electronic component and the second electronic component. The lid includes a lid ceiling; and a lid wall extending from the lid ceiling and defining a lid periphery. A dam structure is connected to the first electronic device top side and the lid ceiling within the lid periphery and having a vent. A first interface material is over the first electronic component top side and contained within the dam structure. A second interface material is over the second electronic component top side and connected to the lid ceiling, where the dam structure separates the first interface material from the second interface material. The first interface material has a higher thermal conductivity than the second interface material. Other examples and related methods are also disclosed herein.

半导体封装及其制造方法

一种半导体封装及其制造方法。作为一非限制性的例子，此揭露内容的各种特点是提供一种半导体封装以及一种制造其之方法，其包括一第一半导体晶粒、在所述第一半导体晶粒上的复数个和彼此间隔开的黏着剂区域、以及一黏着至所述复数个黏着剂区域的第二半导体晶粒。

Semiconductor device package and a method of manufacturing the same

A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.

Electrical package including bimetal lid

Electrical package including bimetal lid. The electrical package includes: an organic substrate; a semiconductor chip electrically connected to electrical pads on a surface of the organic substrate via a plurality of solder balls; and a lid for encapsulating the semiconductor chip on the organic substrate, wherein (i) an inner surface of a central part of the lid is connected to a surface of the semiconductor chip via a first TIM, (ii) an inner surface of an outer part of the lid is hermetically connected to the surface of the organic substrate, and (iii) the lid has a bimetal structure including at least two different metals. A circuit module is also provided.

Cavity package with pre-molded cavity leadframe

A cavity package is disclosed comprising a metal leadframe, a metal ring connected to the metal leadframe, a plastic body molded to the metal leadframe forming a substrate cavity including an exposed die attach pad of the leadframe for affixing a semiconductor device, exposed lead fingers of the leadframe for wire bonding to the semiconductor device and an external circuit, and an exposed top surface of the metal ring, and a metal cap for closing and encapsulating the substrate cavity. The metal ring is integrated into the pre-molded cavity leadframe for providing an electrical ground path from the metal cap to the die attach pad and permitting attachment of the metal cap to the pre-molded leadframe using solder reflow.

파티션화된 로직을 가진 적층 반도체 다이 조립체 및 관련 시스템 및 방법

파티션화된 로직 다이들 사이에 적층되는 메모리 다이들을 가진 적층 반도체 다이 조립체들과, 관련 시스템 및 방법이 여기서 개시된다. 일 실시예에서, 반도체 다이 조립체는 제 1 로직 다이와, 제 2 로직 다이와, 인클로저를 형성하는 열전도성 케이싱을 포함할 수 있다. 메모리 다이들의 스택은 인클로저 내에, 그리고, 상기 제 1 로직 다이와 제 2 로직 다이 사이에 배치될 수 있다.

半导体装置

在具备在背面设置有接地电极并包含多个树脂层(11)的基板(6)、和安装于该基板(6)的表面的半导体芯片(1)的半导体装置中，具备：芯(9)，以一个表面暴露在上述基板(6)的表面侧的方式埋入于上述基板(6)的内部；填充通孔(12)，设置为贯通上述树脂层(11)中的配置于上述芯(9)与上述接地电极之间的树脂层(11)，将上述芯(9)的背面与上述接地电极电连接；表面暴露的高热传导率的盖(4)，以覆盖上述半导体芯片的方式设置于上述基板(6)的表面；包含烧结银(3)的接合材料，将上述盖(4)的背面与上述芯(9)的表面接合；以及模制树脂(7)，在上述基板(6)的整个表面被传递成型，以包围上述盖(4)的周围的方式设置。

Semiconductor device package and a method of manufacturing the same

A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.

Method for manufacturing a semiconductor device having multiple heat sinks

A method for manufacturing a semiconductor device is provided, the method including: mounting a first element on a wiring substrate, placing a first heat sink on the first element with a metal material interposed between the first heat sink and the first element, attaching the first heat sink to the first element via the metal material by heating and melting the metal material, and mounting a second element on the wiring substrate after the steps of attaching the first heat sink to the first element.

封止部材、この封止部材で封止された封止基板及びその製造方法

フィルム状又はトレイ状の形態を有し、かつ少なくとも周縁部１３が熱可塑性樹脂（共重合ポリアミド系樹脂など）を含む封止部材１１で、デバイス１の被封止域を覆い、被封止域の内側で封止部材１１がデバイス１の実装部品３ａ〜３ｃと遊離した形態で、封止部材１１の周縁部１３をデバイス１の基板２と熱接着させ、封止部材１１でデバイス１の被封止域がカバーされた封止デバイスを製造する。共重合ポリアミド系樹脂は、Ｃ８−１６アルキレン基を有する長鎖成分（Ｃ９−１７ラクタム及びアミノＣ９−１７アルカンカルボン酸など）に由来する単位を含んでいてもよい。この封止部材は、デバイスの所定部を選択的かつ有効に封止して保護できる。

Semiconductor device

A semiconductor device includes a package substrate, a package component and at least one adhesive pattern. The package component has a thermal interface material (TIM) layer thereon. The adhesive pattern has a first surface facing the package substrate and a second surface opposite to the first surface, and the second surface of the at least one adhesive pattern is substantially coplanar with a surface of the TIM layer.

区分された論理素子を有する積層半導体ダイアセンブリおよび関連システムと方法

HERMETIC-SEALING PACKAGE MEMBER, PRODUCTION METHOD THEREFOR, AND 
HERMETICALLY-SEALED PACKAGE PRODUCTION METHOD USING THIS HERMETIC-SEALING 
PACKAGE MEMBER

밀봉 부재, 이 밀봉 부재로 밀봉된 밀봉 기판 및 그의 제조 방법

본 발명은 필름상 또는 트레이상의 형태를 갖고, 또한 적어도 주연부(13)가 열 가소성 수지(공중합 폴리아미드계 수지 등)를 포함하는 밀봉 부재(11)로 디바이스(1)의 피밀봉 영역을 덮고, 피밀봉 영역의 내측에서 밀봉 부재(11)가 디바이스(1)의 실장 부품(3a 내지 3c)과 유리된 형태로 밀봉 부재(11)의 주연부(13)를 디바이스(1)의 기판(2)과 열 접착시켜, 밀봉 부재(11)로 디바이스(1)의 피밀봉 영역이 커버된 밀봉 디바이스를 제조한다. 본 발명에서는 공중합 폴리아미드계 수지는 C 8-16 알킬렌기를 갖는 장쇄 성분(C 9- 17 락탐 및 아미노C 9 - 17 알칸카르복실산 등)에서 유래되는 단위를 포함하고 있을 수도 있다. 이 밀봉 부재는 디바이스의 소정부를 선택적으로 또한 유효하게 밀봉하여 보호할 수 있다.

固体金属泡沫热界面材料

本文描述了固体金属泡沫热界面材料及其在电子组件中的应用。在一个实施中，方法包括：在第一装置和第二装置之间施加热界面材料(TIM)，以形成组件，该组件具有与第一装置的表面接触的TIM的第一表面，以及与第二装置的表面接触的与第一表面相对的TIM的第二表面，TIM包括固体金属泡沫和第一液态金属；并且压缩所述组件以由TIM形成将第一装置与第二装置结合的合金。

電子裝置及製造電子裝置的方法

一種電子裝置包含基板和連接到所述基板的第一電子組件，所述第一電子組件包含第一電子組件頂側。第二電子連接到所述基板，與所述第一電子組件橫向間隔開，且包含第二電子組件頂側。蓋連接到所述基板，且包含蓋頂板以及從所述蓋頂板延伸且界定蓋周邊的蓋壁。壩連接到第一電子裝置頂側和所述蓋周邊內的所述蓋頂板。第一界面材料在所述第一電子組件上方且包含於所述壩內。第二界面材料在所述第二電子組件上方且連接到所述蓋頂板。所述壩使所述第一界面材料與所述第二界面材料分離。所述第一界面材料具有比所述第二界面材料高的熱導率。

Halbleitervorrichtung

Eine Halbleitervorrichtung gemäß einer Ausführungsform enthält Folgendes: ein Verdrahtungssubstrat, das eine Kernisolierschicht aufweist; einen Halbleiterchip, der auf einer oberen Fläche des Verdrahtungssubstrats angebracht ist; mehrere Lötmittelkugeln, die auf einer unteren Fläche des Verdrahtungssubstrats gebildet sind; und eine Wärmesenke, die einen ersten Abschnitt, der über eine erste Haftschicht an einer Rückfläche des Halbleiterchips befestigt ist, und einen zweiten Abschnitt, der um den ersten Abschnitt angeordnet ist und über eine zweite Haftschicht am Verdrahtungssubstrat befestigt ist, aufweist. Hier ist ein Anteil der mehreren Lötmittelkugeln an einer Position angeordnet, die jeweils mit dem zweiten Abschnitt der Wärmesenke und der zweiten Haftschicht überlappt. Außerdem ist eine zweite Dicke der zweiten Haftschicht größer als das Zweifache einer ersten Dicke der ersten Haftschicht.

Semiconductor device

A semiconductor device according to one embodiment, includes: a wiring substrate having a core insulating layer; a semiconductor chip mounted on an upper surface of the wiring substrate; a plurality of solder balls formed on a lower surface of the wiring substrate; and a heat sink having a first portion fixed to a back surface of the semiconductor chip via a first adhesive layer, and a second portion located around the first portion and fixed to the wiring substrate via a second adhesive layer. Here, a portion of the plurality of solder balls is arranged at a position overlapping with each of the second portion of the heat sink and the second adhesive layer. Also, a second thickness of the second adhesive layer is greater than two times a first thickness of the first adhesive layer.

半導體裝置及其製造方法

提供封裝結構及封裝結構的形成方法。根據一些實施例，封裝結構包括封裝組件及混合熱界面材料。封裝組件具有黏著到封裝基板的一個或多個積體電路。混合熱界面材料使用以聚合物為主的材料及以金屬為主的材料的組合。以聚合物為主的材料具有高伸長率值，以金屬為主的材料具有高導熱率值。放置在封裝組件的邊緣上的以聚合物為主的熱界面材料含有液態形式的以金屬為主的熱界面材料。

半导体装置

一种半导体装置，封装结构包括封装组件及混合热界面材料。封装组件具有黏着到封装基板的一个或多个集成电路。混合热界面材料使用以聚合物为主的材料及以金属为主的材料的组合。以聚合物为主的材料具有高伸长率值，以金属为主的材料具有高导热率值。放置在封装组件的边缘上的以聚合物为主的热界面材料含有液态形式的以金属为主的热界面材料。

半導體裝置

本發明實施例的一種半導體裝置包括封裝基底、封裝組件及至少一個黏合圖案。封裝組件上具有熱介面材料（TIM）層。黏合圖案具有面對封裝基底的第一表面及與第一表面相對的第二表面，且所述至少一個黏合圖案的第二表面與熱介面材料層的表面實質上共面。

电子组件和用于接合该电子组件的方法

本发明涉及一种电子组件，其具有构造空穴(15)的第一电路载体(11)和第二电路载体(13)。在空穴(15)中布置构件(16)，其中，为构件在第一电路载体(11)中设置接触区域(21)。该接触区域根据本发明可挠曲地、尤其弹性地构造，由此通过接触区域(21)的变形能够吸收公差。由此即使存在接合配合件的多重公差的情况下也能有利地实现组件的可靠的接合。

电子封装件及其制法

一种电子封装件及其制法，包括于一承载结构上设置一封装模块及一屏蔽件，以令该屏蔽件遮盖该封装模块的上方与侧面，以止挡该封装模块向外的辐射，避免该承载结构上的其它电子组件遭受该封装模块的电磁干扰而无法正常传输的问题。

电子装置和制造电子装置的方法

电子装置和制造电子装置的方法。一种电子装置包含衬底和连接到所述衬底的第一电子组件，所述第一电子组件包含第一电子组件顶侧。第二电子组件连接到所述衬底，与所述第一电子组件横向间隔开，且包含第二电子组件顶侧。盖连接到所述衬底，且包含盖顶板以及从所述盖顶板延伸且界定盖周边的盖壁。坝连接到第一电子装置顶侧和所述盖周边内的所述盖顶板。第一界面材料在所述第一电子组件上方且包含于所述坝内。第二界面材料在所述第二电子组件上方且连接到所述盖顶板。所述坝使所述第一界面材料与所述第二界面材料分离。所述第一界面材料具有比所述第二界面材料高的热导率。

Semiconductor package and manufacturing method thereof

A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.

半導體封裝及其製造方法

一種半導體封裝以及一種製造一半導體封裝之方法。作為一非限制性的例子，此揭露內容的各種特點是提供一種半導體封裝以及一種製造其之方法，其包括一第一半導體晶粒、在所述第一半導體晶粒上的複數個和彼此間隔開的黏著劑區域、以及一黏著至所述複數個黏著劑區域的第二半導體晶粒。

Semiconductor package and manufacturing method thereof

A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.

반도체 패키지 및 그 제조 방법

반도체 패키지 및 반도체 패키지를 제조하는 방법이 개시된다. 비-한정적인 예로서, 본 발명의 다양한 양태들은 제1반도체 다이, 제1반도체 다이 위에서 상호간 이격된 다수의 접착 영역들, 및 다수의 접착 영역들에 부착된 제2반도체 다이를 포함하는 반도체 패키지, 및 이의 제조 방법을 제공한다.

半导体封装及其制造方法

一种半导体封装及其制造方法。作为一非限制性的例子，此揭露内容的各种特点是提供一种半导体封装以及一种制造其之方法，其包括一第一半导体晶粒、在所述第一半导体晶粒上的复数个和彼此间隔开的黏着剂区域、以及一黏着至所述复数个黏着剂区域的第二半导体晶粒。

半导体封装及其制造方法

一种半导体封装及其制造方法。作为一非限制性的例子，此揭露内容的各种特点是提供一种半导体封装以及一种制造其之方法，其包括一第一半导体晶粒、在所述第一半导体晶粒上的复数个和彼此间隔开的黏着剂区域、以及一黏着至所述复数个黏着剂区域的第二半导体晶粒。

半導體裝置封裝及其製造方法

一種半導體裝置封裝，其包括一支撐元件、安置於該支撐元件上之一透明板、安置於該透明板下方之一半導體裝置，及圍繞該透明板之一蓋。該支撐元件及該透明板界定一通道。

固体金属発泡体熱界面材料

電子装置組立体における固体金属発泡体熱界面材料およびそれらの使用について説明する。一実装形態では、方法は、第１の装置と第２の装置との間に熱界面材料（ＴＩＭ）を適用する工程であって、第１の装置の表面と接触関係にあるＴＩＭの第１の表面と、第１の表面とは反対側の、第２の装置の表面と接触関係にあるＴＩＭの第２の表面とを有する組立体を形成し、ＴＩＭが固体金属発泡体および第１の液体金属を含む、適用する工程と、第１の装置を第２の装置に接合する合金をＴＩＭから形成するように組立体を圧縮する工程と、を含む。【選択図】図２

반도체 패키지

본 발명의 실시예들에 따르면, 반도체 패키지는 기판; 상기 기판 상의 반도체칩; 상기 기판 상에서 상기 반도체칩을 덮는 몰딩막; 및 상기 몰딩막 상에 제공된 차폐층을 포함할 수 있다. 상기 차폐층은: 서로 연결된 도전 구조체들; 상기 도전 구조체들을 둘러싸고, 상기 도전 구조체들과 상기 몰딩막 사이의 갭들에 제공된 폴리머; 및 상기 폴리머 내에 분산된 나노 구조체들을 포함할 수 있다.

Packages for three-dimensional die stacks

Packages for a three-dimensional die stack, methods for fabricating a package for a three-dimensional die stack, and methods for distributing power in a package for a three-dimensional die stack. The package may include a first lid, a second lid, a die stack located between the first lid and the second lid, a first thermal interface material layer between the first lid and a first die of the die stack, and a second thermal interface material layer between the second lid and the second die of the die stack. The second thermal interface material layer is comprised of a thermal interface material having a high electrical conductivity and a high thermal conductivity.

Packaging for high speed chip to chip communication

Disclosed are chip packaging structures for high speed chip to chip and chip to carrier communications and methods of making such structures. The chip packaging structures do not require an interposer containing through silicon vias and/or provide structures having reduced warping.

Electronic Assembly With A Component Arranged Between Two Circuit Carriers, and Method For Joining Such An Assembly

Various embodiments may include an electronic assembly comprising: a first circuit carrier having a first mounting face for electronic components; a second circuit carrier having a second mounting face for electronic components; wherein the second mounting face faces the first mounting face and is connected thereto; and an electronic component connected both to the first mounting face and the second mounting face; wherein the first mounting face includes a contact region between the first circuit carrier and the component; and the contact region is flexible in a direction perpendicular to the first mounting face in comparison to an adjacent region of the first circuit carrier surrounding the contact region and in comparison to the second circuit carrier.

具有劃分邏輯的堆疊式半導體晶粒總成以及相關的系統及方法

本文中揭示具有堆疊於劃分邏輯晶粒之間的記憶體晶粒之堆疊式半導體晶粒總成以及相關的系統及方法。在一項實施例中，一半導體晶粒總成可包含一第一邏輯晶粒、一第二邏輯晶粒及界定一外殼之一導熱殼體。該記憶體晶粒堆疊可安置於該外殼內且在該第一邏輯晶粒與該第二邏輯晶粒之間。

Stacked semiconductor die assemblies with partitioned logic and associated systems and methods

Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies.