Flip-chip package assembly

In a described example, a method includes: forming cavities in a die mount surface of a package substrate, the cavities extending into the die mount surface of the package substrate at locations corresponding to post connects on a semiconductor die to be flip-chip mounted to the package substrate; placing flux in the cavities; placing solder balls on the flux; and performing a thermal reflow process and melting the solder balls to form solder pads in the cavities on the package substrate.

Semiconductor device

Chip package and a wafer level package

Various embodiments provide for a chip package consisting of a layer over a carrier, further carrier material over the layer, wherein one or more portions of the further carrier material is removed, and a chip with one or more contact pads, where the chip is adhered to the carrier via the layer. A wafer level package consisting of a plurality of chips adhered to the carrier via a plurality of portions of the layer released from the further carrier material is also provided for.

For lead-free solder-connected lead frame structure

Shaped lead terminals for packaging a semiconductor device for electric power

Herein provided are: a ceramic board; a semiconductor element for electric power, on one surface of which an electrode is formed, and the other surface of which is bonded to the ceramic board; a lead terminal, one end side of which is bonded to the electrode, and the other end side of which is to be electrically connected to an outside thereof; and a sealing member by which the semiconductor element for electric power is sealed together with a part, in the lead terminal, bonded to the electrode; wherein, near an end in said one end side of the lead terminal, an inclined surface is formed which becomes farther from the circuit board as it becomes closer to the end.

Klammerbasiertes Halbleitergehäuse zum Ausweiten freiliegender Anschlussleitungen

Semiconductor package and method for manufacturing the same

A semiconductor package includes a lower package including a lower substrate, a lower semiconductor chip, and a lower molding layer exposing an upper surface of the lower semiconductor chip, bumps on the lower substrate, the bumps being spaced apart from the lower semiconductor chip, a lead frame on the lower semiconductor chip and on the bumps, the lead frame being electrically connected to the bumps and having a thermal conductivity of about 100 W/mk to about 10,000 W/mk, and an upper package on the lead frame and electrically connected to the lead frame.

Metal base substrate, power module, and method for manufacturing metal base substrate

A metal base substrate of the present invention includes a copper plate made of copper, a metal layer that is formed on the copper plate and is made of a metal different from the copper, an insulating resin sheet that is formed by bonding a sheet made of an insulating resin onto the metal layer, and a circuit pattern formed on the insulating resin sheet.

Semiconductor device

A semiconductor device has a semiconductor element provided with a functional surface on which a functional circuit is formed and with a back surface facing in the opposite direction to the functional surface, while also having a lead supporting the semiconductor element and electrically connected to the semiconductor element, and a resin package covering at least a portion of the semiconductor element and the lead. The semiconductor element has a functional surface side electrode formed on the functional surface and equipped with a functional surface side raised part that projects in the direction in which the functional surface faces. The functional surface side raised part of the functional surface side electrode is joined to the lead by solid state bonding.

IC-GEHÄUSE MIT INTEGRIERTER INDUKTIVITÄT

Bei einer Implementierung weist ein Halbleitergehäuse einen integrierten Schaltkreis (IC) auf, der an einem Chipkontaktierungssegment eines ersten strukturierten leitfähigen Trägers befestigt ist und mit einem Schaltknotensegment des ersten strukturierten leitfähigen Trägers durch einen elektrischen Verbinder gekoppelt ist. Zusätzlich weist das Halbleitergehäuse einen zweiten strukturierten leitfähigen Träger, der über dem IC angeordnet ist, ein magnetisches Material, das über dem zweiten strukturierten leitfähigen Träger angeordnet ist, und einen dritten strukturierten leitfähigen Träger, der über dem magnetischen Material angeordnet ist, auf. Der zweite strukturierte leitfähige Träger und der dritte strukturierte leitfähige Träger sind elektrisch gekoppelt, um in dem Halbleitergehäuse Wicklungen einer integrierten Induktivität zu bilden. In one implementation, a semiconductor package includes an integrated circuit (IC) attached to a chip contacting segment of a first structured conductive carrier and coupled to a switching node segment of the first structured conductive carrier through an electrical connector. In addition, the semiconductor package includes a second patterned conductive substrate disposed over the IC, a magnetic material disposed over the second patterned conductive substrate, and a third patterned conductive substrate disposed over the magnetic material. The second structured conductive support and the third structured conductive support are electrically coupled to form integrated inductance windings in the semiconductor package.

Elektrisch isolierende thermische Schnittstellenstruktur auf Diskontinuität einer Verkapselungsstruktur

Verfahren zum Herstellen eines elektronischen Halbleitergehäuses (400), wobei bei dem Verfahren ein elektronischer Chip (100) mit einem Träger (102) gekoppelt wird, der elektronische Chip (100) mittels einer Verkapselungsstruktur (200), die eine Diskontinuität (300) hat, zumindest teilweise verkapselt und der Träger (102) teilweise verkapselt wird, und zumindest ein Teil der Diskontinuität (300) und ein daran angeschlossenes Volumen, das an einen freiliegenden Oberflächenabschnitt des Trägers (102) angrenzt, mit einer elektrisch isolierenden thermischen Schnittstellenstruktur (402) bedeckt wird, die zumindest einen Teil des Trägers (102) gegenüber einer Umgebung elektrisch entkoppelt.

Assembly comprising a vertical power component mounted on a metal connection plate

Assemblage comportant un composant vertical de puissance monté sur une plaque métallique de connexion La présente description concerne un assemblage comportant : - un composant vertical de puissance (100) comportant un substrat semiconducteur (101), une première électrode (A2) en contact avec une face inférieure du substrat (101), et une deuxième électrode (A1) en contact avec une face supérieure du substrat (101) ; - une plaque métallique de connexion (150) disposée du côté de la face inférieure du substrat (101) ; et - une entretoise métallique (140) comportant une face inférieure soudée à la plaque métallique de connexion (150) et une face supérieure soudée à la première électrode (A2) du composant vertical de puissance, l'entretoise métallique (140) étant en le même métal que la plaque métallique de connexion (150). Figure pour l'abrégé : Fig. 1 Assembly comprising a vertical power component mounted on a metal connection plate The present description relates to an assembly comprising: - a vertical power component (100) comprising a semiconductor substrate (101), a first electrode (A2) in contact with a face bottom of the substrate (101), and a second electrode (A1) in contact with an upper face of the substrate (101); - a metal connection plate (150) disposed on the side of the lower face of the substrate (101); and - a metal spacer (140) comprising a lower face welded to the metal connection plate (150) and an upper face welded to the first electrode (A2) of the vertical power component, the metal spacer (140) being in the same metal as the metal connection plate (150). Figure for the abstract: Fig. 1

Method of making a wire support leadframe for a semiconductor device

A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of dies electrically connected by at least one wire. A support bracket extends between the die pads and includes a surface for maintaining the at least one wire at a predetermined distance from the die pads during overmolding of the leadframe.

Elektronisches Bauelement und ein Verfahren zur Herstellung eines elektronischen Bauelements

Das elektronische Bauelement enthält einen Träger, ein an dem Träger angebrachtes Halbleiter-Substrat und ein zwischen dem Halbleiter-Substrat und dem Träger angeordnetes Schichtsystem. Das Schichtsystem enthält eine auf dem Halbleiter-Substrat angeordnete elektrische Kontaktschicht. Eine Funktionsschicht ist auf der elektrischen Kontaktschicht angeordnet. Eine Klebeschicht ist auf der Funktionsschicht angeordnet. Eine Lötschicht ist zwischen der Klebeschicht und dem Träger angeordnet.

SEMICONDUCTOR DEⅥCE

Bottom package exposed die MEMS pressure sensor integrated circuit package design

A MEMS pressure sensor packaged with a molding compound. The MEMS pressure sensor features a lead frame, a MEMS semiconductor die, a second semiconductor die, multiple pluralities of bonding wires, and a molding compound. The MEMS semiconductor die has an internal chamber, a sensing component, and apertures. The MEMS semiconductor die and the apertures are exposed to an ambient atmosphere. A method is desired to form a MEMS pressure sensor package that reduces defects caused by mold flashing and die cracking. Fabrication of the MEMS pressure sensor package comprises placing a lead frame on a lead frame tape; placing a MEMS semiconductor die adjacent to the lead frame and on the lead frame tape with the apertures facing the tape and being sealed thereby; attaching a second semiconductor die to the MEMS semiconductor die; attaching pluralities of bonding wires to form electrical connections between the MEMS semiconductor die, the second semiconductor die, and the lead frame; and forming a ...

Electronic device

STRIP-SHAPED SUBSTRATE FOR PRODUCING CHIP CARRIERS, ELECTRONIC MODULE WITH A CHIP CARRIER OF THIS TYPE, ELECTRONIC DEVICE WITH A MODULE OF THIS TYPE, AND METHOD FOR PRODUCING A SUBSTRATE

A strip-shaped substrate made from a film includes a plurality of units for producing chip carriers. Each unit has a chip island for fixing a semiconductor chip, electrodes for electrical connection of the semiconductor chip, and through-openings for structuring the unit. At least one through-opening forms an anchoring edge for a casting compound for encapsulating the semiconductor chip. A surface section of the film abutting the through-opening is chamfered to form the anchoring edge. The anchoring edge protrudes past the side of the film on which the chip island is arranged. 1. A strip-shaped substrate , the substrate comprising:a film; a chip island for fixing a semiconductor chip,', 'a plurality of electrodes for electrically connecting the semiconductor chip, and', 'a plurality of through-openings for structuring the respective unit, at least one through-opening forming an anchoring edge for a casting compound, the casting compound encapsulating the semiconductor chip; and, 'a plurality of units disposed on the film, the plurality of units for producing chip carriers, each unit comprising'}a surface section abutting the at least one through-opening of the film is chamfered for forming the anchoring edge:wherein the anchoring edge protrudes beyond a side of the film on which the respective chip island is arranged.2. The substrate according to claim 1 , wherein a thickness of the film is between 15 μm and 35 μm.3. The substrate according to . wherein the film is formed from a steel claim 1 , austenitic stainless steel claim 1 , copper claim 1 , or a copper alloy.4. The substrate according to claim 1 , wherein a chamfer angle between the surface section and a second surface of the film is between 30° and 60° or between 40° and 50°.5. The substrate according to claim 1 , wherein the surface section is straight.6. The substrate according to claim 1 , wherein the surface section comprises a comb-like profile for reducing a mechanical stress or the surface section ...

Power module of square flat pin-free packaging structure

A power module of a square flat pin-free packaging structure for suppressing the power module from being excessively high in local temperature. The power module includes an insulating resin, a driving chip, a plurality of power chips, and a plurality of metal electrode contacts. The driving chip, the power chips, and the metal electrode contacts are electrically connected through a metal lead according to a predetermined circuit. A plurality of metal heat dissipating disks used for heat dissipation of the power chips and a driving chip lead frame are disposed at the bottom of the insulating resin. A plurality of metal power chip lead frames are disposed on the metal heat dissipating disks, the power chips are disposed on the power chip lead frames, and the drain electrodes of the power chips are electrically connected to the metal heat dissipating disks.

Wire support for a leadframe

A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of dies electrically connected by at least one wire. A support bracket extends between the die pads and includes a surface for maintaining the at least one wire at a predetermined distance from the die pads during overmolding of the leadframe.

SEMICONDUCTOR DEVICE PACKAGE

A semiconductor device package includes a copper lead frame, a copper oxide compound layer and an encapsulant. The copper oxide compound layer is in contact with a surface of the copper lead frame. The copper oxide compound layer includes a copper(II) oxide, and a thickness of the copper oxide compound layer is in a range from about 50 nanometers to about 100 nanometers. The encapsulant is in contact with a surface of the copper oxide compound layer.

Bandförmiges Substrat zur Herstellung von Chipträgern, elektronisches Modul mit einem solchen Chipträger, elektronische Einrichtung mit einem solchen Modul und Verfahren zur Herstellung eines Substrates

Bandförmiges Substrat aus einer Folie (1) mit mehreren Einheiten (2) zur Herstellung von Chipträgern, wobei jeweils eine Einheit eine Chipinsel (3) zur Befestigung eines Halbleiterchips, Elektroden (4) zur elektrischen Verbindung des Halbleiterchips und Durchbrüche (7, 8, 9, 10) zur Strukturierung der Einheit (2) aufweist, wobei wenigstens ein Durchbruch (7, 8, 9, 10) eine Verankerungskante (11) für eine Vergussmasse zur Einkapselung des Halbleiterchips bildet, wobei ein an den Durchbruch (7, 8, 9, 10) angrenzender Flächenabschnitt (12) der Folie (1) zur Bildung der Verankerungskante (11) abgekantet ist, wobei die Verankerungskante (11) über die Seite der Folie (1) vorsteht, auf der die Chipinsel (3) angeordnet ist, dadurch gekennzeichnet, dass die Dicke der Folie (1) von 15 µm bis 35 µm beträgt und die Folie (1) aus einem austenitischen Edelstahl gebildet ist.

Waterproof electronic device and manufacturing method thereof

SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SAME

The present invention relates to a semiconductor package, and a method for manufacturing the same. According to the present invention, the semiconductor package comprises: a lower package including a lower substrate, a lower semiconductor chip, and a lower molding layer for exposing an upper surface of the lower semiconductor chip; bumps separated from the lower semiconductor chip on the lower substrate; a lead frame arranged on the lower semiconductor chip and the bumps, and electrically connected to the bumps; and an upper package arranged on the lead frame, and electrically connected to the lead frame. COPYRIGHT KIPO 2016 ...

The molded flip-chip semiconductor package

Semiconductor device

Matrix lid heatspreader for flip chip package

A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array (310) designed for direct attachment to an array of integrated circuit die (306) by including a thermal interface adhesion layer (308) to each die (306) and encapsulating the attached heat spreader lid array (310) and array of integrated circuit die (306) with mold compound (321) except for planar upper lid surfaces of the heat spreader lids (312).

PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF

A package structure includes a first carrier plate, a second carrier plate, a pin group and an encapsulant member. A power component is disposed on a first top surface of the first carrier plate. The second carrier plate is disposed on the first top surface of the first carrier plate. A driving circuit is disposed on a second top surface of the second carrier plate for driving the power component. An opening runs through the second carrier plate, and the power component is accommodated within the opening. The pin group is assembled on the first carrier plate and/or the second carrier plate. The encapsulant member encapsulates the first carrier plate, the second carrier plate, a part of the first pin group and a part of the second pin group, so that the first pin group and the second pin group are partially exposed outside the encapsulant member. 1. A package structure , comprising:a first carrier plate, wherein at least a power component is disposed on a first top surface of the first carrier plate;a second carrier plate disposed on the first top surface of the first carrier plate, wherein a driving circuit is disposed on a second top surface of the second carrier plate for driving the power component, wherein at least an opening runs through the second carrier plate and corresponds to the power component, and the power component is accommodated within the opening when the second carrier plate is disposed on the first top surface of the first carrier plate;a pin group assembled on the first carrier plate and/or the second carrier plate, wherein the pin group comprises a first pin group and a second pin group; andan encapsulant member encapsulating the first carrier plate, the second carrier plate, a part of the first pin group and a part of the second pin group, so that the first pin group and the second pin group are partially exposed outside the encapsulant member.2. The package structure according to claim 1 , wherein the current-flowing capability and the heat- ...

무연 솔더 접속을 위한 리드 프레임 구조체

... 본 개시내용은 전자 패키징 장치, 전자 패키징 장치에 이용되는 리드 프레임 구조체, 및 전자 패키징 장치를 제조하는 방법을 제공한다. 구리로 이루어지는 리드 프레임은 예컨대 니켈로 된 금속성 배리어층을, 예컨대 리드 프레임의 금속의 산화를 방지하기 위해 포함한다. 예컨대 구리로 된 비교적 얇은 젖음성 촉진층이, 칩이 리드 프레임에 접속되는 다이 접속 공정 중에 리드 프레임에 대해, 무연의 아연계 솔더 등의 솔더의 균일한 젖음성을 촉진시키기 위해 금속성 배리어층 상에 제공된다. 구리/아연 금속간층이 솔더의 플로잉 및 고화(solidification) 시에 형성된다. 구리층에 있는 실질적으로 구리 전체가 구리/아연 금속간층의 형성 중에 소비되고, 금속간층은 전자 패키징 장치의 제조 및 후속 이용 시에 내부 균열 결함에 저항하기에 충분히 얇다.

METAL BASE SUBSTRATE, POWER MODULE, AND METHOD FOR MANUFACTURING METAL BASE SUBSTRATE

A metal base substrate of the present invention includes a copper plate made of copper, a metal layer that is formed on the copper plate and is made of a metal different from the copper, an insulating resin sheet that is formed by bonding a sheet made of an insulating resin onto the metal layer, and a circuit pattern formed on the insulating resin sheet.

SEMICONDUCTOR DEVICE

A semiconductor device has a semiconductor element provided with a functional surface on which a functional circuit is formed and with a back surface facing in the opposite direction to the functional surface, while also having a lead supporting the semiconductor element and electrically connected to the semiconductor element, and a resin package covering at least a portion of the semiconductor element and the lead. The semiconductor element has a functional surface side electrode formed on the functional surface and equipped with a functional surface side raised part that projects in the direction in which the functional surface faces. The functional surface side raised part of the functional surface side electrode is joined to the lead by solid state bonding. 1. A semiconductor device comprising:a semiconductor element having a functional surface on which a functional circuit is formed and a back surface facing in an opposite direction to the functional surface;a conduction supporting member supporting the semiconductor element and electrically connected to the semiconductor element; anda resin package at least partially covering the semiconductor element and the conduction supporting member,wherein the semiconductor element includes a functional surface side electrode that is formed on the functional surface and equipped with a functional surface side raised part projecting in a direction in which the functional surface faces, andthe functional surface side raised part of the functional surface side electrode is joined to the conduction supporting member by solid state bonding.2. The semiconductor device according to claim 1 , wherein the functional surface side electrode has abase layer that contacts the functional surface.3. The semiconductor device according to claim 2 , wherein the base layer is made of Al.4. The semiconductor device according to claim 2 , wherein the functional surface side raised part and the base layer do not overlap with each other in ...

Halbleitervorrichtung für elektrische Energie

Vorgesehen sind: eine keramische Platte (2), ein Halbleiterelement für elektrische Energie (3), auf dessen einer Oberfläche eine Elektrode (z.B. 3a, 3e) ausgebildet ist und dessen andere Oberfläche an die keramische Platte 2 gebondet ist; ein Leitungsanschluss (62), dessen eine Endseite an die Elektrode gebondet ist, und dessen andere Endseite mit einer Außenseite hiervon elektrisch verbunden werden kann; und ein Abdichtungselement (7), mit welchem das Halbleiterelement für elektrische Energie (3) abdichtend mit einem Abschnitt im Leitungsanschluss (62) verbunden ist, welcher an die Elektrode gebondet ist; wobei in der Nähe eines Endes (62e) der einen Endseite des Leitungsanschlusses (62) eine geneigte Oberfläche (62t) ausgebildet ist, wobei sich der Abstand der geneigten Oberfläche (62t) zur Leiterplatte (2) in Richtung des Endes (62e) erhöht.

Semiconductor device, method of manufacturing a semiconductor device, and positioning jig

A semiconductor device has a plurality of small-sized semiconductor chips disposed between an insulated circuit board having a conductive pattern and a terminal. The semiconductor device exhibits a high accuracy in positioning the semiconductor chips. The semiconductor device includes an insulated circuit board having a conductive pattern, a first semiconductor chip with a rectangular shape connected to the conductive pattern through a first joining material, a second semiconductor chip with a rectangular shape, disposed on the conductive pattern separated from the first semiconductor chip and connected to the conductive pattern through a second joining material, and a terminal disposed above the first semiconductor chip and the second semiconductor chip, connected to the first semiconductor chip through a third joining material, and connected to the second semiconductor chip through a fourth joining material. The terminal has a through-hole above a place between the first semiconductor ...

Method Of Making A Wire Support Leadframe For A Semiconductor Device

A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of dies electrically connected by at least one wire. A support bracket extends between the die pads and includes a surface for maintaining the at least one wire at a predetermined distance from the die pads during overmolding of the leadframe. 1. A method of forming a circuit comprising:providing a leadframe having a plurality of interconnected support members, a pair of die pads connected to the support members, and a support bracket extending between the die pads, the support bracket having a an upper surface;applying an insulating layer to the upper surface of the support bracket;securing a pair of dies to the respective die pads, each die having an upper surface;electrically connecting the dies with at least one wire such that the at least one wire extends over the upper surface of the support bracket; andovermolding the leadframe with an electrically insulating material, the upper surface of the support bracket spacing a portion of the at least one wire above the upper surfaces of the dies during overmolding.2. The method recited in claim 1 , wherein the support bracket spaces a middle portion of the at least one wire above the upper surface of each die.3. The method recited in claim 1 , wherein the insulating layer comprises a polymer.4. The method recited in claim 1 , wherein the insulating layer comprises a solder resistant layer.5. The method recited in claim 1 , wherein the at least one wire contacts the insulating layer.6. A method claim 1 , comprising:providing a leadframe having a plurality of interconnected support members and a plurality of die pads connected to the support members, each die pad arranged to receive a respective die; andforming a support bracket having an upper surface and extending between the die pads, wherein the upper surface is formed above an upper surface of each die.7. The ...

Waterproof electronic device and manufacturing method thereof

A waterproof electronic device includes: an electronic component module having an electronic component including a semiconductor element, a heat dissipating member provided on the electronic component in a thermally conductive manner, and an insulating material that surrounds the electronic component in such a manner that one surface of the heat dissipating member is exposed; and a waterproof film that is formed at least on whole surfaces in regions of the electronic component module that are to be immersed in a coolant.

Package for a surface-mount semiconductor device and manufacturing method thereof

A method for manufacturing a surface-mount electronic device includes making a first partial cut from a bottom of an assembly that includes a first semiconductor body that is disposed on a first die pad, a second semiconductor body that is disposed on a second die pad, and a plurality of terminal regions that is disposed between the first and second die pads. The first partial cut forms a recess by removing a portion of each of the terminal regions. The recess is defined by a transverse wall, a first sidewall, and a second sidewall. The first and second sidewalls and the transverse wall are coated with an anti-oxidation layer. A second partial cut is made from the top, where the second partial cut removes the transverse wall, separates the first and second semiconductor bodies, and has a width that is greater than a width of the first partial cut.

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, AND POSITIONING JIG

A semiconductor device has a plurality of small-sized semiconductor chips disposed between an insulated circuit board having a conductive pattern and a terminal. The semiconductor device exhibits a high accuracy in positioning the semiconductor chips. The semiconductor device includes an insulated circuit board having a conductive pattern, a first semiconductor chip with a rectangular shape connected to the conductive pattern through a first joining material, a second semiconductor chip with a rectangular shape, disposed on the conductive pattern separated from the first semiconductor chip and connected to the conductive pattern through a second joining material, and a terminal disposed above the first semiconductor chip and the second semiconductor chip, connected to the first semiconductor chip through a third joining material, and connected to the second semiconductor chip through a fourth joining material. The terminal has a through-hole above a place between the first semiconductor chip and the second semiconductor chip. 1. A semiconductor device comprising:an insulated circuit board having a conductive pattern;a first semiconductor chip with a rectangular shape connected through a first joining material to the conductive pattern;a second semiconductor chip with a rectangular shape disposed on the conductive pattern separated from the first semiconductor chip and connected through a second joining material to the conductive pattern;a terminal disposed above the first semiconductor chip and the second semiconductor chip, connected to the first semiconductor chip through a third joining material, and connected to the second semiconductor chip through a fourth joining material, the terminal having a through-hole above a place between the first semiconductor chip and the second semiconductor chip.2. The semiconductor device according to claim 1 , wherein a gap between a side of the first semiconductor chip and a side of the second semiconductor chip claim 1 , the ...

Die attachment for packaged semiconductor device

A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects.

Wire Support for a Leadframe

A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of dies electrically connected by at least one wire. A support bracket extends between the die pads and includes a surface for maintaining the at least one wire at a predetermined distance from the die pads during overmolding of the leadframe. 1. A leadframe comprising:a plurality of interconnected support members;a pair of die pads connected to the support members and configured to receive a pair of dies electrically connected by at least one wire; anda support bracket extending between the die pads and having a surface for maintaining the at least one wire at a predetermined distance from the die pads during overmolding of the leadframe.2. The leadframe recited in claim 1 , wherein the support bracket includes a middle portion including the surface and spaced equidistant from the die pads.3. The leadframe recited in claim 1 , wherein the surface of the support bracket is planar.4. The leadframe recited in claim 1 , wherein the surface of the support bracket extends parallel to the die pads.5. The leadframe recited in claim 1 , wherein the support bracket extends from a first end to a second end claim 1 , each first and second end having a triangular shape.6. The leadframe recited in claim 1 , wherein the support bracket is coated with a solder resistant layer.7. The leadframe recited in claim 1 , wherein the support bracket includes a plurality of spaced apart middle portions that each includes a surface for supporting the at least one wire.8. The leadframe recited in claim 1 , wherein the surface of the support bracket has a width of about 4 mm.9. A circuit board comprising: a plurality of interconnected support members;', 'a pair of die pads connected to the support members; and', 'a support bracket extending between the die pads and having a surface;, 'leadframe comprisinga pair of dies secured to the die ...

ELECTRONIC DEVICE

An electronic device includes: a heating element; an insulation metal component; and a sealing component. The insulation metal component includes a first metal part to which the heating element is mounted, a second metal part having a portion exposed from the sealing component, and an insulation part interposed between the first metal part and the second metal part. The second metal part has a central part and a peripheral part having a thickness thinner than that of the central part. The second metal part has one surface opposing and in tight contact with the insulation part, and an exposed surface opposite from the sealing component within an area corresponding to the central part. The second metal part has a recess recessed from a virtual straight line that connects an end of the one surface to an end of the exposed surface at a shortest distance around the central part. 1. An electronic device comprising:a heating element that emits heat by operating;an insulation metal component to which the heating element is mounted, the insulation metal component radiating heat of the heating element; anda sealing component that seals the heating element and the insulation metal component, wherein a first metal part to which the heating element is mounted,', 'a second metal part having a portion exposed from the sealing component, and', 'an insulation part interposed between the first metal part and the second metal part to be insulated from each other in a stacked manner,, 'the insulation metal component includes'}the second metal part has a central part and a peripheral part surrounding the central part, the peripheral part having a thickness thinner than that of the central part, the sealing component sealing the peripheral part,the second metal part has one surface opposing and in tight contact with the insulation part, and an exposed surface opposite from the one surface, the exposed surface being exposed from the sealing component within an area corresponding to the ...

Substrate, electronic module and apparatus relating to a chip carrier and method of manufacturing a substrate

SINGULATION METHOD FOR SEMICONDUCTOR PACKAGE WITH PLATING ON SIDE OF CONNECTORS

A method of singulating semiconductor packages, the method comprising: providing a plurality of semiconductor dies coupled to a single common leadframe, wherein a molding compound at least partially encases the semiconductor dies and the leadframe; singulating the plurality of semiconductor dies, wherein the leadframe is at least partially cut between adjacent semiconductor dies, thereby forming exposed side surfaces on leads of the leadframe; and plating the exposed side surfaces of the leads with a plating material, wherein the plating material is a different material than the leads. In some embodiments, singulating the plurality of semiconductor dies comprises performing a full cut of the leadframe. In some embodiments, singulating the plurality of semiconductor dies comprises performing separate partial cuts of the leadframe.

SINGULATION METHOD FOR SEMICONDUCTOR PACKAGE WITH PLATING ON SIDE OF CONNECTORS

A method of singulating semiconductor packages, the method comprising: providing a plurality of semiconductor dies coupled to a single common leadframe, wherein a molding compound at least partially encases the semiconductor dies and the leadframe; singulating the plurality of semiconductor dies, wherein the leadframe is at least partially cut between adjacent semiconductor dies, thereby forming exposed side surfaces on leads of the leadframe; and plating the exposed side surfaces of the leads with a plating material, wherein the plating material is a different material than the leads. In some embodiments, singulating the plurality of semiconductor dies comprises performing a full cut of the leadframe. In some embodiments, singulating the plurality of semiconductor dies comprises performing separate partial cuts of the leadframe. 1. A method of singulating semiconductor packages , the method comprising:providing a plurality of semiconductor dies coupled to a single common leadframe, wherein a molding compound at least partially encases the semiconductor dies and the leadframe;singulating the plurality of semiconductor dies, wherein the leadframe is at least partially cut between adjacent semiconductor dies, thereby forming exposed side surfaces on leads of the leadframe; andplating the exposed side surfaces of the leadsplating material is a different material than the leads.2. The method of claim 1 , wherein the leads are copper.3. The method of claim 1 , wherein the plating material is a metallic material.4. The method of claim 3 , wherein the plating material is tin claim 3 , silver claim 3 , gold claim 3 , nickel-gold claim 3 , nickel-palladium claim 3 , or nickel-palladium-gold.5. The method of claim 1 , wherein the leadframe has a top surface and a bottom surface opposite the top surface claim 1 , and the step of singulating the plurality of semiconductor dies comprises performing a full cut of the leadframe in a single cutting operation before the step of ...

Wasserdichte elektronische Vorrichtung und Verfahren zu ihrer Herstellung

Eine wasserdichte elektronische Vorrichtung umfasst: ein Modul elektronischer Komponenten, das eine elektronische Komponente, die ein Halbleiterelement umfasst, ein Wärmeabführungselement, das auf der elektronischen Komponente in einer thermisch leitenden Weise bereitgestellt ist, und ein Isolationsmaterial, das die elektronische Komponente so umgibt, dass eine Oberfläche des Wärmeabführungselements freigelegt ist, aufweist; und einen wasserdichten Film, der mindestens in Bereichen des Moduls elektronischer Komponenten, die in ein Kühlmittel eingetaucht werden sollen, auf gesamten Oberflächen ausgebildet ist.

Method for packaging circuit element module and product thereof

A method for packaging circuit element module and its product are provided. The method for packaging the circuit element module comprises the following steps: removing a part of a metal plate on a first plate surface of the metal plate by using etching technique in order to form multiple pairs of adjacent terminals; disposing a chip on each pair of terminals and electrically connecting each pair of terminals with the correspondingly chip; forming an insulating layer covering and sealing each pair of terminals and the chips on the first plate surface of the metal plate; and removing a part of the metal plate on a second plate surface of the metal plate opposite to the first plate surface by using the etching technique in order to form a circuit structure connected to the terminals. A circuit unit electrically connected to the chips is co-formed by the terminals and the circuit structure.

WAFER-LEVEL CHIP-SCALE PACKAGE INCLUDING POWER SEMICONDUCTOR AND MANUFACTURING METHOD THEREOF

A wafer-level chip-scale package includes: a power semiconductor comprising a first semiconductor device formed on a semiconductor substrate, and a second semiconductor device formed on the semiconductor substrate; a common drain electrode connected to the first semiconductor device and the second semiconductor device; a first source metal bump formed on a surface of the first semiconductor device; and a second source metal bump formed on the surface of the second semiconductor device; wherein the first source metal bump, the common drain electrode, and the second source metal bump form a current path in an order of the first source metal bump, the common drain electrode, and the second source metal bump. 1. A method of manufacturing a wafer-level chip-scale package , the method comprising:preparing a power semiconductor comprising a first semiconductor device disposed on a semiconductor substrate and a second semiconductor device disposed on a semiconductor substrate;forming a first source metal bump and a second source metal bump on the power semiconductor;forming a recessed area and a rim disposed around the recessed area by polishing a bottom of the semiconductor substrate;forming a common drain electrode, connected to the first semiconductor device and the second semiconductor device, by depositing a first metal layer on the recessed area; andflattening the bottom of the semiconductor substrate by trimming the rim.2. The method of claim 1 , further comprising testing the power semiconductor before the trimming of the rim.3. The method of claim 1 , further comprising forming a second metal layer on the first metal layer claim 1 , wherein the first metal layer comprises copper and the second metal layer comprises nickel.4. A method of manufacturing a wafer-level chip-scale package claim 1 , the method comprising:preparing a power semiconductor by disposing a first semiconductor device and a second semiconductor device on a substrate;forming a recessed area on a ...

Method of making a wire support leadframe for a semiconductor device

A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of dies electrically connected by at least one wire. A support bracket extends between the die pads and includes a surface for maintaining the at least one wire at a predetermined distance from the die pads during overmolding of the leadframe.

Bandförmiges Substrat zur Herstellung von Chipträgern, elektronisches Modul mit einem solchen Chipträger, elektronische Einrichtung mit einem solchen Modul und Verfahren zur Herstellung eines Substrates

Die Erfindung betrifft ein bandförmiges Substrat aus einer Folie (1) mit mehreren Einheiten (2) zur Herstellung von Chipträgern, wobei jeweils eine Einheit eine Chipinsel (3) zur Befestigung eines Halbleiterchips, Elektroden (4) zur elektrischen Verbindung des Halbleiterchips und Durchbrüche (7, 8, 9, 10) zur Strukturierung der Einheit (2) aufweist, wobei wenigstens ein Durchbruch (7, 8, 9, 10) eine Verankerungskante (11) für eine Vergussmasse zur Einkapselung des Halbleiterchips bildet, wobei ein an den Durchbruch (7, 8, 9, 10) angrenzender Flächenabschnitt (12) der Folie (1) zur Bildung der Verankerungskante (11) abgekantet ist, wobei die Verankerungskante (11) über die Seite der Folie (1) vorsteht, auf der die Chipinsel (3) angeordnet ist.

Semiconductor device

SEMICONDUCTOR DEVICE

A semiconductor device that includes a first die pad, an adhesive, and a second die pad fixed to the top surface of the first die pad via the adhesive. The second die pad includes a body portion and a protrusion portion provided on a side surface of the body portion. A semiconductor chip is fixed to a top surface of the second die pad, and a lead is electrically connected to the semiconductor chip. The semiconductor device further includes a package material that covers the first die pad, the second die pad, the semiconductor chip, and the lead. The first die pad is substantially as thick as the lead. 2. The semiconductor device of claim 1 , wherein at least a portion of the lead is disposed above the first die pad.3. The semiconductor device of claim 1 , wherein the second die pad comprises a plurality of protrusion portions claim 1 , including the protrusion portion claim 1 , provided on the side surface of the body portion.4. The semiconductor device of claim 3 , wherein the plurality of protrusion portions are integrally formed with the body portion.5. The semiconductor device of claim 1 , wherein the body portion has a plurality of side surfaces claim 1 , including the side surface claim 1 , and each of the plurality of side surfaces includes at least one protrusion portion.6. The semiconductor device of claim 5 , wherein each of the plurality of side surfaces includes a respective plurality of protrusion portions.7. The semiconductor device of claim 1 , wherein the body portion has a rectangular top surface.8. The semiconductor device of claim 1 , wherein the metal is copper.9. The semiconductor device of claim 1 , wherein the first die pad comprises the metal.10. A method of manufacturing a semiconductor device claim 1 , the method comprising:providing a first die pad;disposing a second die pad comprising a metal on a top surface of the first die pad, the second die pad comprising a body portion and a protrusion portion provided on a side surface of the body ...

Package for a surface-mount semiconductor device and manufacturing method thereof

BOTTOM PACKAGE EXPOSED DIE MEMS PRESSURE SENSOR INTEGRATED CIRCUIT PACKAGE DESIGN

A MEMS pressure sensor packaged with a molding compound. The MEMS pressure sensor features a lead frame, a MEMS semiconductor die, a second semiconductor die, multiple pluralities of bonding wires, and a molding compound. The MEMS semiconductor die has an internal chamber, a sensing component, and apertures. The MEMS semiconductor die and the apertures are exposed to an ambient atmosphere. A method is desired to form a MEMS pressure sensor package that reduces defects caused by mold flashing and die cracking. Fabrication of the MEMS pressure sensor package comprises placing a lead frame on a lead frame tape; placing a MEMS semiconductor die adjacent to the lead frame and on the lead frame tape with the apertures facing the tape and being sealed thereby; attaching a second semiconductor die to the MEMS semiconductor die; attaching pluralities of bonding wires to form electrical connections between the MEMS semiconductor die, the second semiconductor die, and the lead frame; and forming a molding compound. 1. A method comprising:placing a lead frame on a first side of a lead frame tape;placing a MEMS semiconductor die on the first side of the lead frame tape, adjacent to the lead frame, the MEMS semiconductor die having an internal chamber, apertures, and a sensing component inside the internal chamber, the apertures facing the lead frame tape;attaching a second semiconductor die to the MEMS semiconductor die;attaching a first plurality of bonding wires having a first end connected to the MEMS semiconductor die and a second end connected to the second semiconductor die;attaching a second plurality of bonding wires having a first end connected to the lead frame and a second end connected to at least one of the second semiconductor die or the MEMS semiconductor die;forming a molding compound that partially covers the MEMS semiconductor die and the lead frame and fully encapsulates the second semiconductor die and the first and second pluralities of bonding wires; ...

Lead frame construct for lead-free solder connections

An electronics packaging arrangement, a lead frame construct for use in an electronics packaging arrangement, and a method for manufacturing an electronics packaging arrangement. A lead frame made of copper, for example, includes a metallic barrier layer of nickel, for example, to prevent oxidation of the metal of the lead frame. A relatively thin wetting promoting layer of copper, for example, is provided on the metallic barrier layer to promote uniform wetting of a solder, such as a lead-free, zinc-based solder, onto the lead frame during a die connect process by which a chip is connected to the lead frame. A copper/zinc intermetallic layer is formed during the flow and solidification of the solder. Substantially all of the copper in the copper layer is consumed during formation of the copper/zinc intermetallic layer, and the intermetallic layer is sufficiently thin to resist internal cracking failure during manufacture and subsequent use of the electronics packaging arrangement.

Packaging solutions for devices and systems comprising lateral GaN power transistors

Packaging solutions for large area, GaN die comprising one or more lateral GaN power transistor devices and systems are disclosed. Packaging assemblies comprise an interposer sub-assembly comprising the lateral GaN die and a leadframe. The GaN die is electrically connected to the leadframe using bump or post interconnections, silver sintering, or other low inductance interconnections. Then, attachment of the GaN die to the substrate and the electrical connections of the leadframe to contacts on the substrate are made in a single process step. The sub-assembly may be mounted in a standard power module, or alternatively on a substrate, such as a printed circuit board. For high current applications, the sub-assembly also comprises a ceramic substrate for heat dissipation. This packaging scheme provides interconnections with lower inductance and higher current capacity, simplifies fabrication, and enables improved thermal matching of components, compared with conventional wirebonded power modules ...

For surface mount semiconductor device improved packaging and manufacturing method thereof

Chip package and a wafer level package

Various embodiments provide for a chip package including a carrier; a layer over the carrier; a further carrier material over the layer, the further carrier material comprising a foil; one or more openings in the further carrier material, wherein the one or more openings expose at least one or more portions of the layer from the further carrier material; and a chip comprising one or more contact pads, wherein the chip is adhered to the carrier via the one or more exposed portions of the layer.

Metall-Basissubstrat, Leistungsmodul und Verfahren zum Herstellen eines Metall-Basissubstrats

Ein Metall-Basissubstrat der vorliegenden Erfindung enthält eine Kupferplatte (1) aus Kupfer, eine Metallschicht (2), die auf der Kupferplatte (1) gebildet ist und aus einem anderen Metall als Kupfer gemacht ist, eine isolierende Kunstharzplatte (4), die durch Verbinden einer Platte aus einem isolierenden Kunstharz mit der Metallschicht (2) gebildet ist, und ein auf der isolierenden Kunstharzplatte (4) gebildetes Schaltungsmuster (5).

Klammerbasiertes Halbleitergehäuse zum Ausweiten freiliegedner Anschlussleitungen

Ein Halbleitergehäuse beinhaltet einen Leiterrahmen mit einem Klammerfußteil, wobei der Klammerfußteil eine erste Verbindungsleiste aufweist, eine leitfähige Klammer, die sich über dem Leiterrahmen befindet, wobei die leitfähige Klammer eine erste Arretierungsgabel mit wenigstens zwei Zinken um die erste Verbindungsleiste herum aufweist, so dass die leitfähige Klammer an dem Klammerfußteil des Leiterrahmens fixiert wird. Die leitfähige Klammer beinhaltet eine zweite Arretierungsgabel mit wenigstens zwei Zinken um eine zweite Verbindungsleiste des Klammerfußteils herum. Die leitfähige Klammer ist elektrisch mit dem Klammerfußteil des Leiterrahmens gekoppelt. Der Klammerfußteil des Leiterrahmens beinhaltet freiliegende Anschlussleitungen. Das Halbleitergehäuse beinhaltet außerdem wenigstens eine Halbleitervorrichtung, die sich auf dem Leiterrahmen befindet. Die wenigstens eine Halbleitervorrichtung ist mit einem integrierten Treiberschaltkreis gekoppelt, der sich auf dem Leiterrahmen befindet ...

Used for making the chip package, the chip package and crystalline circular level packaging

Electrically insulating thermal interface on the discontinuity of an encapsulation structure

Method for manufacturing an electronic semiconductor package, in which method an electronic chip () is coupled to a carrier, the electronic chip is at least partially encapsulated by means of an encapsulation structure having a discontinuity, and the carrier is partially encapsulated, and at least one part of the discontinuity and a volume connected thereto adjoining an exposed surface section of the carrier are covered by an electrically insulating thermal interface structure, which electrically decouples at least one part of the carrier with respect to its surroundings. 1. Method for manufacturing an electronic semiconductor package , wherein the method comprises:coupling an electronic chip to a carrier;encapsulating the electronic chip at least partially and encapsulating the carrier partially by an encapsulation structure having a discontinuity;covering at least a part of the discontinuity and a volume connected thereto, which adjoins an exposed surface section of the carrier, with an electrically insulating thermal interface structure, which electrically decouples at least a part of the carrier with respect to a surrounding.2. Method in accordance with claim 1 , wherein the thermal interface structure for providing a thermal coupling is formed between the carrier and a heat dissipation element claim 1 , which is connectable to the thermal interface structure.3. Method in accordance with claim 1 , wherein the method comprises a formation of the discontinuity during the encapsulation.4. Method in accordance with claim 3 , wherein the discontinuity is formed by a protrusion claim 3 , at an encapsulation tool claim 3 , shaped inversely to the discontinuity claim 3 , whereby encapsulation material is precluded from flowing into the discontinuity.5. Method in accordance with claim 1 , wherein the method comprises a formation of the discontinuity after the encapsulation.6. Method in accordance with claim 5 , wherein the discontinuity is formed by removing material of ...

Surface mounting electron device

Electronic Device with Multi-Layer Contact

An electric device with a multi-layer contact is disclosed. In an embodiment, the electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

Wire Support For A Leadframe

A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of dies electrically connected by at least one wire. A support bracket extends between the die pads and includes a surface for maintaining the at least one wire at a predetermined distance from the die pads during overmolding of the leadframe.

Semiconductor device

A semiconductor device that includes a first die pad, an adhesive, and a second die pad fixed to the top surface of the first die pad via the adhesive. The second die pad includes a body portion and a protrusion portion provided on a side surface of the body portion. A semiconductor chip is fixed to a top surface of the second die pad, and a lead is electrically connected to the semiconductor chip. The semiconductor device further includes a package material that covers the first die pad, the second die pad, the semiconductor chip, and the lead. The first die pad is substantially as thick as the lead.

Leadless semiconductor packages, leadframes therefor, and methods of making

A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.

Verfahren zur Herstellung eines elektronischen Bauelements

Verfahren zur Herstellung eines elektronischen Bauelements (10), wobei das Verfahren Folgendes umfasst:Bereitstellung eines Halbleiter-Substrats (2);Abscheiden einer Einzelelementschicht aus Al direkt auf das Halbleiter-Substrat (2) zum Bilden einer elektrischen Kontaktschicht (3.1) auf dem Halbleiter-Substrat (2);Abscheiden von Ti oder einer Ti aufweisenden Legierung direkt auf die elektrische Kontaktschicht (3.1) zum Bilden einer Funktionsschicht (3.2);Abscheiden von Ni direkt auf die Funktionsschicht (3.2) zum Bilden einer Haftschicht (3.3);Abscheiden einer Einzelelementschicht aus Sn direkt auf die Haftschicht (3.3) zum Bilden einer Lötschicht (3.4);Abscheiden einer Schutzschicht (43.5) auf der Lötschicht (3.4); Bereitstellung eines Trägers (1, 41), wobei die Oberfläche des Trägers (1, 41) mit einer oder mehreren Metallschichten (41.1) beschichtet ist, und wobei die Metallschicht oder die oberste der mehreren Metallschichten (41.1) Ni als Grundmaterial umfasst; undBonden des Halbleiter-Substrats ...

Halbleitervorrichtung, Verfahren zum Herstellen einer Halbleitervorrichtung und Positionslehre

Eine Aufgabe der vorliegenden Erfindung besteht darin, eine Halbleitervorrichtung 200 bereitzustellen, die eine Vielzahl von kleinformatigen Halbleiter-Chips umfasst, die parallelgeschaltet zwischen einer isolierten Leiterplatte 3, die ein Leiterbild aufweist, und einer Anschlussklemme 19 angeordnet sind, wobei die Halbleitervorrichtung 200 beim Positionieren der Halbleiter-Chips eine hohe Genauigkeit aufweist. Die vorliegende Erfindung stellt auch ein Verfahren zum Herstellen einer derartigen Halbleitervorrichtung 200 und eine Positionslehre 100 zur Verwendung bei der Herstellung der Halbleitervorrichtung 200 bereit. Die Halbleitervorrichtung 200 umfasst: eine isolierte Leiterplatte 3, die ein Leiterbild aufweist; einen ersten Halbleiter-Chip mit einer rechteckigen Form, der über ein erstes Fügematerial mit dem Leiterbild verbunden ist; einen zweiten Halbleiter-Chip mit einer rechteckigen Form, der auf dem Leiterbild getrennt von dem ersten Halbleiter-Chip angeordnet und über ein zweites ...

SEMICONDUCTOR DEVICE PACKAGE

3D-CHIP-ANORDNUNGEN UNTER VERWENDUNG GESTAPELTER ANSCHLUSSLEITERRAHMEN

Eine gestapelte Chip-Anordnung umfasst eine Mehrzahl von IC-Chips oder -Dies, die gestapelt sind, und eine Mehrzahl von gestapelten Anschlussleitern. Anschlussleiter von separaten Anschlussleiterrahmen können zusammengebondet werden, um die entsprechenden Metall-Merkmale der verschiedenen Chips an eine gleiche Masse, ein gleiches Signal oder eine gleiche Leistungsschiene zu binden. Jeder Anschlussleiterrahmen kann ein Zentrum-Paddle umfassen, das zwischen zwei Chips in dem Stapel angeordnet ist. Das Zentrum-Paddle kann als eines oder mehreres von einer thermischen Leitung und einer gemeinsamen elektrischen Schiene (z.B. Masse) funktionieren. Die Anschlussleiterrahmen können ohne die Verwendung von irgendwelchen Bonddrähten verwendet werden, wobei die Anschlussleiter direkt an die Bondanschlussflächen der Chips gebondet sind. Ein erster IC-Chip kann an einem Basis-Anschlussleiterrahmen befestigt sein und nachfolgende Die-Anbringungs-Anschlussleiterrahmen und IC-Chips sind auf den ersten ...

Geformtes Flipchip-Halbleitergehäuse

Ein geformtes Flipchip-Halbleitergehäuse umfasst einen Leiterrahmen mit gegenüberliegender erster und zweiter Hauptoberfläche, einer ersten Metallisierung auf der ersten Hauptoberfläche, einer zweiten Metallisierung auf der zweiten Hauptoberfläche, vertieften Regionen, die sich von der ersten Hauptoberfläche in Richtung der ersten Hauptoberfläche erstrecken, sowie voneinander beabstandeten Anschlüssen, die zwischen Spalten in der ersten Metallisierung chemisch in den Leiterrahmen geätzt werden. Das Gehäuse umfasst ferner einen Halbleiter-Nacktchip, der eine Vielzahl von Kontaktstellen, die den Anschlüssen des Leiterrahmens zugewandt und an diesen befestigt sind, eine erste Formmasse, welche die vertieften Regionen füllt, und eine zweite Formmasse umfasst, die den Halbleiter-Nacktchip umgibt und den Zwischenraum zwischen den Anschlüssen füllt, sodass die zweite Formmasse an die erste Formmasse angrenzt. A ist die Gesamtdicke des Leiterrahmens, B ist der Abstand zwischen angrenzenden der ...

Electronic device with multi-layer contact

The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

Addition-curable silicone composition

Provided is an addition-curable silicone composition having little shrinkage or change in hardness due to heat, a cured silicone product of which obtained has excellent adhesiveness and appearance and makes it possible to protect metals, especially silver, from corrosion. An addition-curable silicone composition containing 100 parts by mass of polyorganosiloxane having an alkenyl group, polyorganohydrogensiloxane in an amount to make 0.9-3.0 mol of hydrogen atoms bonded to silicon atoms per 1 mol total amount of this alkenyl group, a catalytic amount of hydrosilylation catalyst, 0.01-10 parts by mass of adhesiveness-imparting agent, and 0.001-0.015 parts by mass, calculated in terms of metal atoms, of carboxylic acid metal salt indicated by (R3COO)kM (M indicates a metal atom selected from Ce, Fe, Cr, La, Nd, Pr, and Sm, k indicates a positive number of 2-4, and R3 indicates a substituted or unsubstituted hydrocarbon group having 4-10 carbon atoms).

Package structure and fabricating method thereof

A package structure includes a first carrier plate, a second carrier plate, a pin group and an encapsulant member. A power component is disposed on a first top surface of the first carrier plate. The second carrier plate is disposed on the first top surface of the first carrier plate. A driving circuit is disposed on a second top surface of the second carrier plate for driving the power component. An opening runs through the second carrier plate, and the power component is accommodated within the opening. The pin group is assembled on the first carrier plate and/or the second carrier plate. The encapsulant member encapsulates the first carrier plate, the second carrier plate, a part of the first pin group and a part of the second pin group, so that the first pin group and the second pin group are partially exposed outside the encapsulant member.

Semiconductor Package Structure and Manufacturing Method Thereof

A semiconductor package structure and manufacturing method thereof are provided, and the semiconductor package structure includes a semiconductor element, a top substrate, a bottom substrate, an insulating layer, and two metal conductive layers. The top substrate is mainly made of a conductive metal, and having a first separated portion on the top substrate, the first separated portion divides the top substrate into two blocks which are not electrically connected to each other. The bottom substrate is mainly made of the conductive metal, and having a second separated portion on the to bottom substrate. The second separated portion divides the bottom substrate into two blocks which are not electrically connected to each other. The insulating layer is disposed between the top substrate and the bottom substrate. The metal conductive layer is disposed at two sides of the insulating layer and connected to the top substrate and the bottom substrate. The semiconductor element is contacted with the top substrate and the bottom substrate. 1. A semiconductor package structure , comprising:a semiconductor element;a top substrate, being mainly made of a conductive metal, and having a first separated portion on the top substrate, the first separated portion divides the top substrate into two blocks which are not electrically connected to each other;a bottom substrate, being mainly made of a conductive metal, and having a second separated portion on the bottom substrate, the second separated portion divides the bottom substrate into two blocks which are not electrically connected to each other;a insulating layer, disposed between the top substrate and the bottom substrate; andtwo metal conductive layers, disposed at two sides of the insulating layer, and connected to the top substrate and the bottom substrate;wherein, the semiconductor element is contacted with the top substrate and the bottom substrate.2. The semiconductor package structure of claim 1 , wherein the top substrate ...

Semiconductor device, method of manufacturing semiconductor device, positioning jig

반도체 장치의 제조 방법 및 반도체 장치

... 일 실시 형태에 의한 반도체 장치의 제조 방법에서는, 인접하는 디바이스 영역의 사이에서 연결된 제1 리드와 제2 리드의 각각의 하면을 연통되도록 홈부가 형성된 리드 프레임을 준비한다. 이어서, 제1 블레이드를 사용하여 상기 제1 및 제2 리드의 연결부의 일부를 절삭한 후, 상기 홈부 내에 형성된 금속 칩을 제거한다. 이어서, 상기 금속 칩을 제거한 후, 상기 제1 및 제2 리드의 노출면에 도금법에 의해 금속막을 형성한 후, 제2 블레이드를 사용하여 제1 및 제2 리드의 연결부의 잔류부를 절단한다. 이때, 상기 제2 블레이드가 상기 홈부에 접촉하지 않도록 절단한다.

Power semiconductor module and composite module

A power semiconductor module includes a wiring member that electrically connects a front surface electrode of a semiconductor element and a circuit board of an insulating substrate in a housing. A resin provided in the housing covers the wiring member, and has a height in the vicinity of the wiring member. A cover covering the periphery of external terminals is provided between the resin and a first lid in the housing. A second lid is provided further outside the first lid in an aperture portion of the housing, and the space between the second lid and the first lid is filled with another resin.

POWER MODULE

A power module capable of increasing structural stability and reliability at high temperatures includes: an upper substrate having a metal layer; a lower substrate spaced apart from the upper substrate and having a metal layer facing the metal layer of the upper substrate; a semiconductor element configured to be disposed between the upper substrate and the lower substrate; and at least one leg portion formed on at least one of the metal layer of the upper substrate and the metal layer of the lower substrate to make the upper substrate and the lower substrate be spaced apart from each other at a predetermined interval, in which the leg portion may be electrically connect the semiconductor element to the metal layer of the upper substrate or the metal layer of the lower substrate. 111-. (canceled)12. A power module , comprising:an upper substrate having an upper insulating layer and a metal layer formed on a bottom surface of the upper insulating layer;a lower substrate spaced apart from the upper substrate, and having a lower insulating layer, and a metal layer formed on a top surface of the lower insulating layer;a semiconductor element connected to a connection layer of the upper substrate and a connection layer of the lower substrate, respectively; andat least one leg portion bent from the metal layer of the lower substrate toward the upper substrate,wherein the leg portion has a bonding end part bonded to the metal layer of the upper substrate.13. The power module according to claim 12 , wherein the bonding end part of the leg portion is bonded to the metal layer of the upper substrate by an adhesive.14. The power module according to claim 12 , wherein the leg portion is formed to be bent at an edge of the metal layer of the lower substrate claim 12 , and an interval between a bottom surface of the upper substrate and a top surface of the lower substrate is determined based on a height of the leg portion. This application claims the benefit of Korean Patent ...

SEMICONDUCTOR DEVICE

A semiconductor device according to an embodiment includes a first metal part. A semiconductor chip is mounted on the first metal part and includes a first electrode on a top surface thereof. A solder is provided on the first electrode of the semiconductor chip. A connector is provided on the solder and includes a first portion provided around the solder on a first surface thereof. The first surface faces the first electrode. A contact angle with the solder in the first portion is larger than a contact angle with the solder in a region other than the first portion of the connector. A resin is provided around the semiconductor chip. 1. A semiconductor device comprising:a first metal part;a semiconductor chip on the first metal part, the semiconductor chip including a first electrode;a solder on the first electrode of the semiconductor chip;a connector on the solder, the connector including a first portion around the solder on a first surface of the connector, the first surface facing the first electrode, a contact angle with the solder in the first portion being larger than a contact angle with the solder in a region other than the first portion of the connector; anda resin around the semiconductor chip.2. The device of claim 1 , wherein a planar shape of a region of the connector enclosed by the first portion is substantially similar to that of the first electrode claim 1 , anda geometric center or a center of gravity of the planar shape of the region of the connector enclosed by the first portion substantially matches a geometric center or a center of gravity of the planar shape of the first electrode when viewed from above a surface of the semiconductor chip.3. The device of claim 1 , wherein the solder is interposed between the region of the connector enclosed by the first portion and the first electrode.4. The device of claim 2 , wherein the solder is interposed between the region of the connector enclosed by the first portion and the first electrode.5. The ...

IC package with integrated inductor

Semiconductor device

SEMICONDUCTOR DEVICE

A semiconductor device of the present invention includes a resin package, a semiconductor chip sealed in the resin package, and having first and second pads on a front surface, a lead integrated island sealed in the resin package, to one surface of which a back surface of the semiconductor chip is bonded, and the other surface of an opposite side to the one surface of which is partially exposed from a bottom surface of the resin package as a first pad connecting terminal for electrical connection between the first pad and outside and a back connecting terminal for electrical connection between the back surface of the semiconductor chip and outside separately from each other, and a lead formed separately from the lead integrated island, sealed in the resin package, one surface of which is connected with the second pad by a wire, and the other surface of an opposite side to the one surface of which is exposed from a bottom surface of the resin package as a second pad connecting terminal for electrical connection between the second pad and outside, and the semiconductor chip is, on the one surface of the lead integrated island, disposed at a position one-sided to the first pad connecting terminal side, and the first pad and the one surface of the lead integrated island are connected by a wire.

SEMICONDUCTOR DEVICE FOR ELECTRIC POWER

Herein provided are: a ceramic board; a semiconductor element for electric power, on one surface of which an electrode is formed, and the other surface of which is bonded to the ceramic board; a lead terminal, one end side of which is bonded to the electrode, and the other end side of which is to be electrically connected to an outside thereof; and a sealing member by which the semiconductor element for electric power is sealed together with a part, in the lead terminal, bonded to the electrode; wherein, near an end in said one end side of the lead terminal, an inclined surface is formed which becomes farther from the circuit board as it becomes closer to the end. 1. A semiconductor device for electric power , comprising:a circuit board;a semiconductor element for electric power, on one surface of which an electrode is formed, and the other surface of which is bonded to the circuit board;a lead terminal, one end side of which is bonded to the electrode, and the other end side of which is to be electrically connected to an outside thereof; anda sealing member by which the semiconductor element for electric power is sealed together with a part, in the lead terminal, bonded to the electrode;wherein, near an end in said one end side of the lead terminal, an inclined surface is formed which becomes farther from the circuit board as it becomes closer to the end.2. The semiconductor device for electric power according to claim 1 , wherein the lead terminal is bent near the end so as to form the inclined surface.38-. (canceled)9. The semiconductor device for electric power according to claim 1 , wherein claim 1 , the lead terminal has a wall thickness that becomes thinner toward the end so as to form the inclined surface.10. The semiconductor device for electric power according to claim 2 , wherein claim 2 , the lead terminal has a wall thickness that becomes thinner toward the end so as to form the inclined surface.11. The semiconductor device for electric power according ...

Singulation method for semiconductor package with plating on side of connectors

A method of singulating semiconductor packages, the method comprising: providing a plurality of semiconductor dies coupled to a single common leadframe, wherein a molding compound at least partially encases the semiconductor dies and the leadframe; singulating the plurality of semiconductor dies, wherein the leadframe is at least partially cut between adjacent semiconductor dies, thereby forming exposed side surfaces on leads of the leadframe; and plating the exposed side surfaces of the leads with a plating material, wherein the plating material is a different material than the leads. In some embodiments, singulating the plurality of semiconductor dies comprises performing a full cut of the leadframe. In some embodiments, singulating the plurality of semiconductor dies comprises performing separate partial cuts of the leadframe.

SEMICONDUCTOR DEVICE

A semiconductor device includes a resin package, a semiconductor chip sealed in the package and having first and second pads on a front surface. An island of the device has a projecting terminal sealed in the package, to one surface of which a back surface of the chip is bonded, and the other surface of which is partially exposed from a bottom surface of the package as a first terminal. A lead separate from the island is sealed in the package and has one surface electrically connected with the second pad, and another surface exposed from the package bottom surface as a second terminal capable of electrical connection between the second pad and outside. A mass center of the chip is away from a center of the package, the projecting terminal is as large as the lead, and solder under the device spreads to the island projecting terminal.

Clip based semiconductor package for increasing exposed leads

Semiconductor packaging identifier

Described is a semiconductor package frame including a material comprising wire openings a die-mounting surface area with a die-mounting surface and identification markings included within the die-mounting surface. The identification markings uniquely identify the semiconductor package frame from among other semiconductor package frames comprising different identification markings.

INTEGRATED CIRCUIT DEVICE WITH PLATING ON LEAD INTERCONNECTION POINT AND METHOD OF FORMING THE DEVICE

An integrated circuit (IC) device includes an IC die and a plurality of leads. Each lead includes an unplated proximal end including a first material, and an unplated distal end including the first material. A plated bond wire portion extends between the proximal and distal ends and includes the first material and a plating of a second material thereon. A plurality of bond wires extend between the IC die and the plated bond wire portions of the leads. An encapsulation material surrounds the IC die and bond wires so that the unplated proximal end and plated bond wire portion of each lead are covered by the encapsulation material. 1. An integrated circuit (IC) device comprising:an IC die; an unplated proximal end comprising a first material,', 'an unplated distal end comprising the first material, and, 'a plurality of leads, each lead comprising'}a plated bond wire portion between the proximal and distal ends and comprising the first material and a plating of a second material thereon;a plurality of bond wires, each bond wire extending between said IC die and the plated bond wire portion of a respective lead;an encapsulation material surrounding said IC die and plurality of bond wires so that the unplated proximal end and plated bond wire portion of each lead are covered by said encapsulation material.2. The IC device of wherein each lead further comprises an unplated intermediate portion between said plated bond wire portion and said unplated distal end; and wherein said encapsulation material also covers the unplated intermediate portion of each lead.3. The IC device of wherein the first material comprises copper.4. The IC device of wherein the second material comprises silver.5. The IC device of wherein each of said plurality of bond wires comprises the first material.6. The IC device of wherein each of said plurality of bond wires comprises copper.7. The IC device of wherein each unplated distal end extends in a range of 100 to 300 microns.8. The IC device of ...

Electrically insulating thermal interface on discontinuity of encapsulation structure

Semiconductor device and method of making a semiconductor device

A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside. The semiconductor device also includes at least one metal layer extending across the backside of the substrate. A peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface. This can prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier.

Method for manufacturing a chip package, a method for manufacturing a wafer level package, a chip package and a wafer level package

A method for manufacturing a chip package is provided. The method includes forming a layer over a carrier; forming further carrier material over the layer; selectively removing one or more portions of the further carrier material thereby releasing one or more portions of the layer from the further carrier material; and adhering a chip including one or more contact pads to the carrier via the layer.

Power module

A power module capable of increasing structural stability and reliability at high temperatures includes: an upper substrate having a metal layer; a lower substrate spaced apart from the upper substrate and having a metal layer facing the metal layer of the upper substrate; a semiconductor element configured to be disposed between the upper substrate and the lower substrate; and at least one leg portion formed on at least one of the metal layer of the upper substrate and the metal layer of the lower substrate to make the upper substrate and the lower substrate be spaced apart from each other at a predetermined interval, in which the leg portion may be electrically connect the semiconductor element to the metal layer of the upper substrate or the metal layer of the lower substrate.

반도체 장치

... 수지 패키지와, 제1 및 제2 패드를 표면에 갖는 반도체 칩과, 한쪽 면에 상기 반도체 칩의 이면이 접합되고, 반대측의 다른 쪽 면이, 상기 제1 패드와 외부와의 전기 접속을 위한 제1 패드 접속 단자 및 상기 반도체 칩의 이면과 외부와의 전기 접속을 위한 이면 접속 단자로서 서로 분리되고, 상기 수지 패키지의 저면으로부터 부분적으로 노출되는 리드 일체형 아일랜드와, 한쪽 면이, 상기 제2 패드와 와이어에 의해 접속되고, 반대측의 다른 쪽 면이, 상기 제2 패드와 외부와의 전기 접속을 위한 제2 패드 접속 단자로서, 상기 수지 패키지의 저면으로부터 노출되는 리드를 포함하고, 상기 반도체 칩은, 상기 제1 패드 접속 단자측으로 치우친 위치에 배치되고, 상기 제1 패드와 상기 리드 일체형 아일랜드의 상기 한쪽 면이 와이어에 의해 접속되어 있는 반도체 장치.

PACKAGING SOLUTIONS FOR DEVICES AND SYSTEMS COMPRISING LATERAL GaN POWER TRANSISTORS

Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof In the packaging assembly, a GaN die, comprising one or more lateral GaN power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling. Preferred embodiments facilitate alignment and registration of high current/low inductance interconnects for lateral GaN devices, in which contact areas or pads for source, drain and gate contacts are provided on the front-side of the GaN die. By eliminating wirebonding, and using low inductance interconnections with high electrical and thermal conductivity, PQFN technology can be adapted for packaging GaN die comprising one or more lateral GaN power transistors. 1. A semiconductor device structure comprising an assembly of:a lateral GaN power transistor fabricated on a semiconductor substrate (GaN die) and packaging components comprising first and second leadframe layers;the GaN die comprising a front surface providing source, drain and gate contact areas for the lateral GaN power transistor and a back surface for die-attach;the GaN die being sandwiched between the first and second leadframe layers;the first leadframe layer being patterned to provide source, drain and gate portions corresponding to source, drain and gate contact areas on the front surface of the GaN die;the second leadframe layer comprising a thermal pad and a die-attach area for the back surface of the GaN die;the back surface of the GaN die being attached to the die-attach area of the second leadframe layer by a low inductance layer of an electrically and thermally conductive attachment material;the source, drain and gate contact areas of ...

Packaging structure and manufacture method thereof

本发明公开了一种封装结构及其制造方法。该封装结构包含一第一载板、一第二载板、一引导组件及一封装体；第一载板的一第一上表面上设置至少一功率器件；第二载板设置于第一上表面上，且包含一驱动电路组件及至少一贯穿孔，其中驱动电路组件设置于第二载板的一第二上表面上，用以驱动功率器件，贯穿孔与功率器件相对应设置，当第二载板设置于第一上表面上时，贯穿孔供功率器件穿设；导引组件与第一载板及/或第二载板组接；封装体包覆第一载板、第二载板、部份导引组件，且导引组件部份外露于封装体。本发明的封装结构具备较小尺寸及较佳散热效率的优势，减少线路阻抗及寄生参数。

Verfahren zur Herstellung einer Chipkapselung, Verfahren zur Herstellung einer Wafer-Level-Kapselung, Chipkapselung und Wafer-Level-Kapselung

Es wird ein Verfahren (100) zur Herstellung einer Chipkapselung bereitgestellt. Das Verfahren (100) weist auf das Bilden (110) einer Schicht über einem Träger; Bilden (120) von weiterem Trägermaterial über der Schicht; selektives Entfernen (130) eines oder mehrerer Teile des weiteren Trägermaterials, um dadurch einen oder mehrere Teile der Schicht von dem weiteren Trägermaterial loszulösen; und Kleben (140) eines Chips, der eine oder mehrere Kontaktstellen aufweist, an den Träger über die Schicht.

SEMICONDUCTOR DEVICE

A semiconductor device includes a resin package, a semiconductor chip sealed in the package and having first and second pads on a front surface. An island of the device has a projecting terminal sealed in the package, to one surface of which a back surface of the chip is bonded, and the other surface of which is partially exposed from a bottom surface of the package as a first terminal. A lead separate from the island is sealed in the package and has one surface electrically connected with the second pad, and another surface exposed from the package bottom surface as a second terminal capable of electrical connection between the second pad and outside. A mass center of the chip is away from a center of the package, the projecting terminal is as large as the lead, and solder under the device spreads to the island projecting terminal. 1. A semiconductor device comprising:a resin package;a semiconductor chip sealed in the resin package, and having first and second pads on a front surface;an island with a projecting terminal, sealed in the resin package, to one surface of which a back surface of the semiconductor chip is bonded, and another surface of which is partially exposed from a bottom surface of the resin package as a first terminal; anda lead formed separately from the island with the projecting terminal, sealed in the resin package, one surface of the lead being electrically connected with the second pad, and another surface of which being exposed from the bottom surface of the resin package as a second terminal capable of providing electrical connection between the second pad and outside, whereina center of mass of the semiconductor chip is away from a center of the resin package and the projecting terminal is equally as large as the lead.2. The semiconductor device according to claim 1 , further comprising a connecting member electrically connecting the lead with a second pad.3. The semiconductor device according to claim 1 , wherein a groove is formed in the ...

Wire support for a leadframe

A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of dies electrically connected by at least one wire. A support bracket extends between the die pads and includes a surface for maintaining the at least one wire at a predetermined distance from the die pads during overmolding of the leadframe.

Electronic Device and a Method for Fabricating an Electronic Device

The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

Matrix Lid Heatspreader for Flip Chip Package

A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array () designed for direct attachment to an array of integrated circuit die () by including a thermal interface adhesion layer () to each die () and encapsulating the attached heat spreader lid array () and array of integrated circuit die () with mold compound () except for planar upper lid surfaces of the heat spreader lids (). 110-. (canceled)11. A semiconductor package , comprising:a substrate having first and second surfaces;a die having first and second surfaces, where the first surface of the die is flip-chip bonded to the first surface of the substrate;a compressed, laterally expansive, thermally conductive interface layer formed to cover the second surface of the die; anda heat spreader lid comprising an exposed heat dissipation surface layer and a plurality of connection spars extending laterally from the heat dissipation surface layer, where the heat dissipation surface layer contacts the compressed, laterally expansive, thermally conductive interface layer and is positioned apart from the substrate to define an encapsulation molding region in which encapsulation mold compound material is located to permanently attach the substrate, die, and heat spreader lid.12. The semiconductor package of claim 11 , where the plurality of connection spars extend laterally to be co-planar with the exposed heat dissipation surface layer.13. The semiconductor package of claim 11 , where the plurality of connection spars extend laterally as downset connection spars that are not co-planar with the exposed heat dissipation surface layer.14. The semiconductor package of claim 11 , where the heat spreader lid is formed with a thermally conductive layer of copper claim 11 , nickel or an alloy thereof.15. The semiconductor package of claim 11 , where the exposed heat dissipation surface layer has a thermal contact surface that is at ...

Method for Producing Electronic Device With Multi-Layer Contact

A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer. 1. A method for fabricating an electronic device , the method comprising:providing a carrier, the carrier having a metallic layer disposed on its surface, wherein the metallic layer comprises Ni or NiNiP;providing a semiconductor substrate; directly depositing an electrical contact layer on the semiconductor substrate, the electrical contact layer being a single elemental Al layer;', 'directly depositing a functional layer on the electrical contact layer, the functional layer comprising Ti or an alloy containing Ti;', 'directly depositing an adhesion layer on the functional layer, the adhesion layer comprising Ni or NiV;', 'directly depositing a solder layer on the adhesion layer, the solder layer being a single element Sn layer or a noble metal free alloy layer containing Sn; and', 'directly depositing a protective layer on the solder layer, the protection layer being an Ag layer; and, 'forming a layer stack on the semiconductor substrate bybonding the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer, the intermetallic phase comprising a binary alloy of Ni/Sn.2. The method according to claim 1 , wherein the electrical contact layer has a thickness in a range from 100 nm to 1 μm.3.The method according to claim 2 , wherein the functional layer has a thickness in a range from 50 nm to 200 nm.4382. The method according to claim claim 2 , wherein the solder layer has a thickness in ...

BOTTOM PACKAGE EXPOSED DIE MEMS PRESSURE SENSOR INTEGRATED CIRCUIT PACKAGE DESIGN

A MEMS pressure sensor packaged with a molding compound. The MEMS pressure sensor features a lead frame, a MEMS semiconductor die, a second semiconductor die, multiple pluralities of bonding wires, and a molding compound. The MEMS semiconductor die has an internal chamber, a sensing component, and apertures. The MEMS semiconductor die and the apertures are exposed to an ambient atmosphere. A method is desired to form a MEMS pressure sensor package that reduces defects caused by mold flashing and die cracking. Fabrication of the MEMS pressure sensor package comprises placing a lead frame on a lead frame tape; placing a MEMS semiconductor die adjacent to the lead frame and on the lead frame tape with the apertures facing the tape and being sealed thereby; attaching a second semiconductor die to the MEMS semiconductor die; attaching pluralities of bonding wires to form electrical connections between the MEMS semiconductor die, the second semiconductor die, and the lead frame; and forming a molding compound. 19.-. (canceled)10. A package containing a MEMS sensor circuit , comprising:a lead frame having an open region in a middle of the lead frame and a first surface exposed to an ambient atmosphere;a MEMS semiconductor die being laterally adjacent to the lead frame, the MEMS semiconductor die having an exposed outer surface thereof exposed to the ambient atmosphere, the exposed outer surface having a plurality of apertures, the plurality of apertures exposing an internal chamber of the MEMS semiconductor die to the ambient atmosphere;a second semiconductor die attached to the MEMS semiconductor die;a first plurality of bonding wires connected between the lead frame and the second semiconductor die;a second plurality of bonding wires connected at least between one of the lead frame and the MEMS semiconductor die or the MEMS semiconductor die and the second semiconductor die; anda molding compound partially covering the MEMS semiconductor die and the lead frame and ...

Semiconductor device manufacturing method

This invention enhances reliability of an electrical test. A semiconductor device manufacturing method in which a potential (first potential) is supplied by bringing a plurality of first and second test terminals into contact with a plurality of leads, respectively in the step of supplying the potential to the leads (first leads) to carry out the electrical test. The first test terminals come into contact with the leads, individually, and the second test terminals come into contact with the leads in one batch.

WFCQFN (Very-Very Thin Flip Chip Quad Flat No Lead) with Embedded Component on Leadframe and Method Therefor

A quad flat no lead package is provided comprising at least one first integrated circuit die embedded in a recess in a die paddle of a metal leadframe and a second integrated circuit chip die attached to the at least one first integrated circuit die wherein the first and second integrated circuit dies are electrically connected to each other and wherein the second integrated circuit die is connected to leads of the leadframe through copper pillars. 1. A quad flat no lead package comprising:at least one first integrated circuit die embedded in a recess in a die paddle portion of a metal leadframe; anda second integrated circuit die attached to said at least one first integrated circuit die wherein said first and second integrated circuit dies are electrically connected to each other and wherein said second integrated circuit die is connected to leads of said leadframe through copper pillars.2. The package according to wherein said at least one first integrated circuit die is an integrated passive device and wherein said second integrated circuit die is a mother die.3. The package according to wherein said first and second integrated circuit dies are electrically connected to each other through solder bumps.4. The package according to wherein said package contains no wire bonds.5. The package according to wherein a top surface of said second integrated circuit is exposed to minimize the package profile and to dissipate heat.6. A method of fabricating a quad flat no lead package comprising:providing a leadframe having at least one recess formed in a top surface of a die paddle portion of said leadframe;embedding at least one first integrated circuit die in said at least one recess;forming solder bumps on said at least one first integrated circuit die;forming copper pillars on said leadframe and on leads of said leadframe;dispensing an underfill material surrounding said solder bumps and said copper pillars on said die paddle portion of said leadframe; andthereafter ...

Semiconductor Package Having Etched Foil Capacitor Integrated Into Leadframe

A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls. The angularly shaped capacitors are attached to surface portions of the leadframe structures. The angularly shaped capacitors have sidewalls coplanar with structure sidewalls. The angularly shaped capacitors includes a conductive material attached to the structure surface. The conductive material having pores covered by oxide and filled with conductive polymer. The angularly shaped capacitors topped by electrodes are made of a second metal. 114-. (canceled)15. A packaged semiconductor device comprising:a leadframe made of a first metal, the leadframe having structures with surfaces and sidewalls; and sidewalls coplanar with structure sidewalls;', 'a conductive material attached to a structure surface, the conductive material having pores covered by oxide and filled with conductive polymer; and', 'an electrode top made of a second metal., 'a plurality of angularly shaped capacitors attached to surface portions of the leadframe structures, the plurality of angularly shaped capacitors comprising16. The device of claim 15 , further comprising a plurality of elongated capacitors.17. The device of wherein the conductive material is a foil.18. The device of wherein the leadframe structures include a chip pad and a plurality of leads.19. The device of wherein the conductive material is selected from a group comprising aluminum claim 15 , tin claim 15 , doped silicon claim 15 , and doped germanium.20. The device of wherein the first metal is selected from a group comprising copper claim 15 , copper alloys claim 15 , aluminum claim 15 , and iron-nickel alloys.21. The device of wherein the second metal is selected from a group comprising silver claim 15 , copper claim 15 , and alloys thereof.22. The device of further including a semiconductor chip having bond pads claim 15 , metal wires connecting the bond pads to ...

PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF

A package structure includes a first carrier plate, a second carrier plate, a pin group and an encapsulant member. A power component is disposed on a first top surface of the first carrier plate. The second carrier plate is disposed on the first top surface of the first carrier plate. A driving circuit is disposed on a second top surface of the second carrier plate for driving the power component. An opening runs through the second carrier plate, and the power component is accommodated within the opening. The pin group is assembled on the first carrier plate and/or the second carrier plate. The encapsulant member encapsulates the first carrier plate, the second carrier plate, a part of the first pin group and a part of the second pin group, so that the first pin group and the second pin group are partially exposed outside the encapsulant member. 1. A package structure , comprising:a first carrier plate, wherein at least a power component is disposed on a first top surface of the first carrier plate;a second carrier plate disposed on the first top surface of the first carrier plate, wherein a driving circuit is disposed on a second top surface of the second carrier plate for driving the power component, wherein at least an opening runs through the second carrier plate and corresponds to the power component, and the power component is accommodated within the opening when the second carrier plate is disposed on the first top surface of the first carrier plate;a pin group assembled on the first carrier plate and/or the second carrier plate, wherein the pin group comprises a first pin group and a second pin group; andan encapsulant member encapsulating the first carrier plate, the second carrier plate, a part of the first pin group and a part of the second pin group, so that the first pin group and the second pin group are partially exposed outside the encapsulant member,wherein both of the first pin group and the second pin group are assembled on the first carrier plate ...

LEAD FRAME CONSTRUCT FOR LEAD-FREE SOLDER CONNECTIONS

An electronics packaging arrangement, a lead frame construct for use in an electronics packaging arrangement, and a method for manufacturing an electronics packaging arrangement. A lead frame made of copper, for example, includes a metallic barrier layer of nickel, for example, to prevent oxidation of the metal of the lead frame. A relatively thin wetting promoting layer of copper, for example, is provided on the metallic barrier layer to promote uniform wetting of a solder, such as a lead-free, zinc-based solder, onto the lead frame during a die connect process by which a chip is connected to the lead frame. A copper/zinc intermetallic layer is formed during the flow and solidification of the solder. Substantially all of the copper in the copper layer is consumed during formation of the copper/zinc intermetallic layer, and the intermetallic layer is sufficiently thin to resist internal cracking failure during manufacture and subsequent use of the electronics packaging arrangement. 110-. (canceled)11. A lead frame construct , comprising:a lead frame having a surface;a metallic barrier layer disposed on said surface of said lead frame; anda wetting promoting layer disposed on said metallic barrier layer.12. The construct of claim 11 , wherein the wetting promoting layer is selected from copper and a copper alloy.13. The construct of claim 11 , wherein the wetting promoting layer is selected from zinc claim 11 , bismuth claim 11 , tin claim 11 , indium claim 11 , gold claim 11 , silver claim 11 , palladium claim 11 , platinum and alloys thereof.14. The construct of wherein said wetting promoting layer has a thickness between 1 μm and 10 μm.15. The construct of claim 11 , wherein said metallic barrier layer comprises one of nickel and a nickel alloy claim 11 , and has a thickness between 1 μm and 10 μm.16. The construct of claim 11 , wherein the metallic barrier layer is a discontinuous layer over a plurality of die pad areas of the lead frame.17. An electronics ...

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE

A semiconductor package includes a first metal plate having a first surface, a semiconductor chip including a first electrode and a second electrode, on the first surface, and a second metal plate on the semiconductor chip. The first metal plate has a first surface. The first electrode is connected to the first metal plate. The second metal plate includes a second surface and first and second side surfaces respectively on opposite sides of the second metal plate and connected to the second surface. The first side surface has a first recessed portion extending in a direction which crosses the first and second surfaces, and the second side surface has a second recessed portion extending in the second direction that crosses the first and second surfaces. 1. A semiconductor package comprising:a first metal plate having a first surface;a semiconductor chip on the first surface, the semiconductor chip including a first electrode and a second electrode, wherein the first electrode is connected to the first metal plate; anda second metal plate on the semiconductor chip, wherein the second metal plate has a second surface and first and second side surfaces respectively on opposite sides of the second metal plate and connected to the second surface, and is connected to the second electrode, the first side surface having a first recessed portion extending in a direction which crosses the first and second surfaces, and the second side surface having a second recessed portion extending in the second direction that crosses the first and second surfaces.2. The package according to claim 1 , wherein the first recessed portion extends inwardly of the first side surface and the second recessed portion extends inwardly of the second side surface.3. The package according to claim 2 , wherein a portion of the semiconductor chip is exposed by each of the first and second recessed portions.4. The package according to claim 3 , whereinthe semiconductor chip has sidewalls and at least two ...

Electronic Device with Multi-Layer Contact and System

An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow. 1. A semiconductor device comprising:a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface;an electrical contact layer disposed directly on the first electrode terminal, the electrical contact layer consisting essentially of Al;a functional layer directly disposed on the electrical contact layer, the functional layer consisting essentially of Ti or an alloy containing Ti;an adhesion layer directly disposed on the functional layer, the adhesion layer consisting essentially of Ni or NiV;a solder layer directly disposed on the adhesion layer, the solder layer consisting essentially of Sn; anda protection layer directly disposed on the solder layer,wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.2. The device according to claim 1 , wherein the electrical contact layer has a thickness in a range from 100 nm to 1 μm claim 1 , wherein the functional layer has a thickness in a range from 50 nm to 200 nm claim 1 , wherein the adhesion layer has a thickness in a range from 200 nm to 2 μm claim 1 , ...

Semiconductor device having two encapsulants

A semiconductor device includes a substrate, a semiconductor die mounted on and electrically connected to the substrate, and first and second encapsulants that are different from each other. The first encapsulant covers the die and at least part of the substrate. The second encapsulant covers the first encapsulant and a portion of the substrate that is not covered by the first encapsulant.

DIE ATTACHMENT FOR PACKAGED SEMICONDUCTOR DEVICE

A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects. 115-. (canceled)16. A packaged semiconductor device , comprising:a package substrate comprising a plurality of protrusions extending from a top surface of the package substrate, each protrusion having a to surface;a plurality of die attach material portions, each die attach material portion in contact with each top surface of the plurality of protrusions;a semiconductor die over the plurality of protrusions, wherein the semiconductor die is spaced apart from the top surface of the package substrate, wherein the semiconductor die has a bottom surface having no bond pads, the bottom surface is in contact with the plurality of die attach material portions, and wherein the plurality of protrusions define a region between the semiconductor die and the package substrate and around the protrusions;an underfill material within the region and between each protrusion, wherein the underfill material contacts the top surface of the package substrate and the bottom surface of the semiconductor die between the plurality of die attach material portions; andan encapsulant over the semiconductor die.17. The packaged semiconductor device of claim 16 , wherein the underfill material is a part of the encapsulant claim 16 , wherein the encapsulant contacts a top surface and the bottom surface of the semiconductor die.18. The packaged semiconductor device of ...

LEADLESS SEMICONDUCTOR PACKAGES, LEADFRAMES THEREFOR, AND METHODS OF MAKING

A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer. 1. A method of making a semiconductor device , comprising:providing at least four semiconductor die;providing a plurality of contacts adjacent to each of the semiconductor die;providing at least four tie bars adjacent to each of the semiconductor die;depositing an encapsulant over the at least four semiconductor die and the plurality of contacts; andforming at least four trenches in a first surface of the encapsulant for a full vertical thickness of the plurality of contacts to expose the plurality of contacts.2. The method of claim 1 , further including forming a conductive layer over the flank of the contact for the full vertical thickness of the contact.3. The method of claim 1 , further including forming a second trench in the first surface of the encapsulant between the semiconductor die and the contact.4. The method of claim 1 , further including disposing a die pad under the semiconductor die claim 1 , wherein the at least four tie bars extend from the second surface of the encapsulant to the die pad.5. The method of claim 1 , further including forming a bond wire extending from the first surface or the second surface of the encapsulant.6. The method of claim 1 , wherein a depth of the second trench into the encapsulant is approximately equal to half of a ...

Leadless semiconductor packages, leadframes therefor, and methods of making

A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.

Bottom package exposed die mems pressure sensor integrated circuit package design

A MEMS pressure sensor packaged with a molding compound. The MEMS pressure sensor features a lead frame, a MEMS semiconductor die, a second semiconductor die, multiple pluralities of bonding wires, and a molding compound. The MEMS semiconductor die has an internal chamber, a sensing component, and apertures. The MEMS semiconductor die and the apertures are exposed to an ambient atmosphere. A method is desired to form a MEMS pressure sensor package that reduces defects caused by mold flashing and die cracking. Fabrication of the MEMS pressure sensor package comprises placing a lead frame on a lead frame tape; placing a MEMS semiconductor die adjacent to the lead frame and on the lead frame tape with the apertures facing the tape and being sealed thereby; attaching a second semiconductor die to the MEMS semiconductor die; attaching pluralities of bonding wires to form electrical connections between the MEMS semiconductor die, the second semiconductor die, and the lead frame; and forming a molding compound.

SEMICONDUCTOR DEVICE AND METHOD OF MAKING A SEMICONDUCTOR DEVICE

A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside. The semiconductor device also includes at least one metal layer extending across the backside of the substrate. A peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface. This can prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier. 1. A semiconductor device comprising:a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside; andat least one metal layer extending across the backside of the substrate,wherein a peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface, to prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier.2. The semiconductor device of claim 1 , wherein an edge of the substrate between the backside and at least one of the side surfaces is curved claim 1 , and wherein the peripheral part of the at least one metal layer extends along the curved edge of the substrate.3. The semiconductor device of claim 1 , wherein an edge of the substrate between the backside and at least one of the side surfaces slants upwards at an angle 180°>α>90° relative to a surface normal of the backside claim 1 , and wherein the peripheral part of the at least one metal layer extends along the slanted edge of the substrate.4. The semiconductor device of claim 1 , wherein an edge of the substrate ...

CHIP PACKAGE AND A WAFER LEVEL PACKAGE

Various embodiments provide for a chip package including a carrier; a layer over the carrier; a further carrier material over the layer, the further carrier material comprising a foil; one or more openings in the further carrier material, wherein the one or more openings expose at least one or more portions of the layer from the further carrier material; and a chip comprising one or more contact pads, wherein the chip is adhered to the carrier via the one or more exposed portions of the layer. 1. A chip package , comprising:a carrier;a layer over the carrier;a further carrier material over the layer, the further carrier material comprising a foil;one or more openings in the further carrier material, wherein the one or more openings expose at least one or more portions of the layer from the further carrier material; anda chip comprising one or more contact pads, wherein the chip is adhered to the carrier via the one or more exposed portions of the layer.2. The chip package of claim 1 , wherein the one or more exposed portions of the layer provides an electrically conductive interface between the chip and the carrier.3. The chip package of claim 2 , wherein the electrically conductive interface extends between an entire side of the chip and the carrier.4. The chip package of claim 1 , wherein the carrier comprises at least one material from the group consisting of: copper claim 1 , nickel claim 1 , iron claim 1 , silver claim 1 , gold claim 1 , palladium claim 1 , copper alloy claim 1 , nickel alloy claim 1 , iron alloy claim 1 , silver alloy claim 1 , gold alloy claim 1 , and palladium alloy.5. The chip package of claim 1 , wherein the carrier has a thickness ranging from about 50 μm to about 1000 μm.6. The chip package according to claim 1 , wherein the layer comprises an electrically conductive material comprising at least one material from the group consisting of: silver claim 1 , silver alloy claim 1 , gold claim 1 , gold alloy claim 1 , nickel claim 1 , and ...

3D CHIP ASSEMBLIES USING STACKED LEADFRAMES

A stacked-chip assembly including a plurality of IC chips or die that are stacked, and a plurality of stacked leads. Leads from separate leadframes may be bonded together so as to tie corresponding metal features of the various chips to a same ground, signal, or power rail. Each leadframe may include a center paddle, which is disposed between two chips in the stack. The center paddle may function as one or more of a thermal conduit and common electrical rail (e.g., ground). The leadframes may be employed without the use of any bond wires with leads bonded directly to bond pads of the chips. A first IC chip may be mounted to a base leadframe and subsequent die-attach leadframes and IC chips are stacked upon the first IC chip and base leadframe. The die-attach leadframes may be iteratively bonded to an underlying leadframe and the bonded stacked leads stamped out of their respective leadframe sheets. 1. An integrated circuit (IC) chip assembly , comprising:a first IC chip;a second IC chip in a stack with the first IC chip;a paddle between the first and second IC chips, wherein the paddle comprises metal and includes a paddle end that is coupled to at least one of a metal feature at a periphery of the stack, or a heat sink.2. The IC chip assembly of claim 1 , wherein the paddle end is coupled to a metal feature at a periphery of the stack claim 1 , and wherein the paddle makes electrical contact to a metal feature on one or both of the first and second IC chips.3. The IC chip assembly of claim 2 , wherein the paddle electrically couples each of the IC chips to a common reference voltage rail.4. The IC chip assembly of claim 2 , further comprising a substrate including a ground pad claim 2 , and where the paddle end is bonded to the ground pad.5. The IC chip assembly of claim 1 , wherein:the paddle is a first paddle and the assembly further comprises a second paddle;the second paddle comprises a metal,a paddle end of the first paddle is bonded to a paddle end of the ...

Integrated Circuit Package For Assembling Various Dice In A Single IC Package

An integrated circuit IC package with one or more pins protruding from the IC package for electrically connecting the IC package with a printed circuit board PCB is presented. The IC package has a first die with a first electronic component, a second die with a second electronic component, and a conductive plate having a plane surface. The first electronic component may be a semiconductor power device and the second electronic component may be a control circuit. The plane surface of the conductive plate is electrically connected to both a plane surface of the first die and one or more pins such that an electrical connection is established between the first die and the one or more pins. The second die may be arranged on top of the conductive plate. Alternatively, a third die with a third electronic component may be arranged on top of the conductive plate. 2. The IC package according to claim 1 , wherein the one or more pins are electrically connected to the plane surface of the conductive plate.3. The IC package according to claim 1 , wherein the first electronic component is a transistor and the second electronic component is a control circuit configured to control operation of the transistor.4. The IC package according to claim 1 , wherein at least two pins are electrically connected within the IC package via a pinframe claim 1 , and the plane surface of the conductive plate is electrically connected to said pinframe.5. The IC package according to claim 1 , further comprising at least one control pin claim 1 , wherein the second die is wire bonded with the at least one control pin for establishing an electrical contact with the PCB claim 1 , and the at least one control pin is isolated from the one or more pins which are electrically connected to the conductive plate.6. The IC package according to claim 1 , wherein the electrical connection between the first die and the one or more pins is only established via the conductive plate.7. The IC package to claim 1 , ...

POWER MODULE

A power module capable of increasing structural stability and reliability at high temperatures includes: an upper substrate having a metal layer; a lower substrate spaced apart from the upper substrate and having a metal layer facing the metal layer of the upper substrate; a semiconductor element configured to be disposed between the upper substrate and the lower substrate; and at least one leg portion formed on at least one of the metal layer of the upper substrate and the metal layer of the lower substrate to make the upper substrate and the lower substrate be spaced apart from each other at a predetermined interval, in which the leg portion may be electrically connect the semiconductor element to the metal layer of the upper substrate or the metal layer of the lower substrate. 1. A power module , comprising:an upper substrate having a metal layer;a lower substrate spaced apart from the upper substrate and having a metal layer facing the metal layer of the upper substrate;a semiconductor element disposed between the upper substrate and the lower substrate; andat least one leg portion formed on at least one of the metal layer of the upper substrate and the metal layer of the lower substrate to make the upper substrate and the lower substrate be spaced apart from each other at a predetermined interval,wherein the leg portion is configured to electrically connect the semiconductor element to the metal layer of the upper substrate or the metal layer of the lower substrate.2. The power module according to claim 1 , wherein a top surface and a bottom surface of the semiconductor element are electrically connected to the metal layer of the upper substrate and the metal layer of the lower substrate by an adhesive.3. The power module according to claim 1 , wherein a top surface of the upper substrate and a bottom surface of the lower substrate are each provided with a cooling module.4. A power module claim 1 , comprising:an upper substrate having an upper insulating layer ...

FLIP-CHIP ON LEADFRAME HAVING PARTIALLY ETCHED LANDING SITES

A flip-chip on leadframe package includes a leadframe having a plurality of leads with each lead including an inner leadfinger portion, wherein at least a landing region of all of the inner leadfinger portions are in a single common level (or plane) and include etched areas providing bump pads having concave landing sites (landing sites). A semiconductor die (die) having an active top side surface with functional circuitry including bond pads has bumps or pillars thereon. An area of the landing sites is greater than an area of the bumps or pillars. A distal end of the bumps or pillars is within and electrically coupling to the landing sites. A mold material encapsulates the die and at least a portion of the inner leadfinger portions. The package can be a leaded package or a leadless package. 1. An integrated circuit (IC) package , comprising:a leadframe comprising a plurality of leads with each said lead including an inner leadfinger portion, wherein at least a landing region of all of said inner leadfinger portions include partially-etched areas providing bump pads having concave landing sites (landing sites);a semiconductor die (die) having an active top side surface with functional circuitry including bond pads with bumps or pillars thereon;wherein an area of said landing sites is greater than an area of said bumps or pillars;wherein a distal end of said bumps or pillars is within and electrically coupled to said landing sites, anda mold material encapsulating said die and at least a portion of said inner leadfinger portions.2. The IC package of claim 1 , wherein said leads each include an external lead portion connected to said inner leadfinger portion extending out from said mold material.3. The IC package of claim 1 , wherein said leads consist of said inner leadfinger portions claim 1 , and a periphery of said inner leadfinger portions on a bottom of said IC package are exposed from said mold material.4. The IC package of claim 1 , wherein said landing sites ...

Power Module of Square Flat Pin-Free Packaging Structure

A power module of a square flat pin-free packaging structure for suppressing the power module from being excessively high in local temperature. The power module includes an insulating resin, a driving chip, a plurality of power chips, and a plurality of metal electrode contacts. The driving chip, the power chips, and the metal electrode contacts are electrically connected through a metal lead according to a predetermined circuit. A plurality of metal heat dissipating disks used for heat dissipation of the power chips and a driving chip lead frame are disposed at the bottom of the insulating resin. A plurality of metal power chip lead frames are disposed on the metal heat dissipating disks, the power chips are disposed on the power chip lead frames, and the drain electrodes of the power chips are electrically connected to the metal heat dissipating disks.

Method Of Making A Wire Support Leadframe For A Semiconductor Device

A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of dies electrically connected by at least one wire. A support bracket extends between the die pads and includes a surface for maintaining the at least one wire at a predetermined distance from the die pads during overmolding of the leadframe. 1. An integrated circuit , comprising:a pair of die pads;a pair of dies secured to the pair of die pads, the pair of dies electrically connected by at least one wire having a middle portion;a support bracket extending between the die pads and having a surface for maintaining the middle portion of the at least one wire no lower than a height from the die pads during overmolding of the integrated circuit, the height preventing electrical arcing between the dies and the at least one wire; andelectrically insulating material overmolded over the pair of die pads, the at least one wire, and the pair of dies.2. The integrated circuit recited in claim 1 , wherein the support bracket includes a middle portion including the surface and spaced equidistant from the die pads.3. The integrated circuit recited in claim 1 , wherein the surface of the support bracket is planar.4. The integrated circuit recited in claim 1 , wherein the surface of the support bracket extends parallel to the die pads.5. The integrated circuit recited in claim 1 , wherein the support bracket extends from a first end to a second end claim 1 , each first and second end having a triangular shape.6. The integrated circuit recited in claim 1 , wherein the support bracket is coated with a solder resistant layer.7. The integrated circuit recited in claim 1 , wherein the support bracket includes a plurality of spaced apart middle portions that each includes a surface for supporting the at least one wire.8. The integrated circuit recited in claim 1 , wherein the surface of the support bracket has a width of about 4 mm. ...

Chip package and a wafer level package

Various embodiments provide for a chip package consisting of a layer over a carrier, further carrier material over the layer, wherein one or more portions of the further carrier material is removed, and a chip with one or more contact pads, where the chip is adhered to the carrier via the layer. A wafer level package consisting of a plurality of chips adhered to the carrier via a plurality of portions of the layer released from the further carrier material is also provided for.

SEMICONDUCTOR DEVICE AND PORTABLE APPARATUS USING THE SAME

The present invention provides a semiconductor device that can achieve miniaturization or thinning of the size of the package while maintaining the characteristic of the MOSFET and reducing the on-resistance value, and a portable apparatus using the same. The gate electrodes and of the semiconductor chip are disposed in the vicinity of the two side surfaces of the longitudinal direction (the x axis direction on the page) of the package and the gate terminal and that is mounted with the gate electrodes and in a flip-chip manner are extended in the longitudinal direction of the package and are derived to the outside from the two side surfaces A and B. Based on the configuration, it is capable of maximizing the size of the semiconductor chip with respect to the size of the package, and it is able to realize the high performance of the element characteristic for the module. 1. A semiconductor device , comprising:a frame;a semiconductor chip having a main surface mounted on the frame in a flip-chip manner;an integrated circuit (IC) chip stacked and fixed on a surface of the semiconductor chip opposite to the main surface;metal wires electrically connected to the semiconductor chip and the IC chip; anda package encapsulating the frame, the semiconductor chip, the IC chip, and the metal wires,wherein the package has two side surfaces opposite to each other in the longitudinal direction of the package,wherein the semiconductor chip is formed with a first transistor and a second transistor, a gate electrode of the first transistor formed on the main surface is arranged beside one of the side surfaces of the package, and a gate electrode of the second transistor formed on the main surface is arranged beside the other one of the side surfaces of the package.2. The semiconductor device according to claim 1 , wherein a portion of the frame where the gate electrode of the first transistor is mounted extends along the longitudinal direction and is exposed from the one of the side ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

In a method of manufacturing a semiconductor device according to an embodiment, a lead frame is provided, the lead frame having a trench part formed thereon so as to communicate bottom surfaces of a first lead and a second lead, which are coupled to each other between device regions adjacent to each other. Then, after a part of a coupling part between the first and second leads is cut by using a first blade, metal wastes formed inside the trench part are removed. Then, after the metal wastes are removed, a metal film is formed on exposed surfaces of the first and second leads by a plating method, and then, a remaining part of the coupling part between the first and second leads is cut by using a second blade. At this time, the cutting is performed so that the second blade does not contact the trench part. 1. A method of manufacturing a semiconductor device comprising the steps of:(a) providing a lead frame including: a first device region having a first chip mounting part having a top surface with a first semiconductor chip mounted thereon and a plurality of leads including a first lead arranged in vicinity of the first chip mounting part; a second device region having a second chip mounting part having a top surface with a second semiconductor chip mounted thereon and a plurality of leads including a second lead arranged in vicinity of the second chip mounting part and coupled to the first lead, the second device region being arranged adjacent to the first device region; and a sealing body collectively sealing the first device region and the second device region, the lead frame having such a trench part formed thereon as extending in a first direction so as to communicate with a first lead bottom surface of each of the first lead and the second lead extending in the first direction and having a narrower width in a second direction orthogonal to the first direction than a width of the first lead bottom surface of each of the first lead and the second lead;(b) ...

INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING THE SAME

A method of making an integrated circuit package includes: (a) forcing a circuit layered structure that includes a metal substrate and a circuit pattern, the metal substrate having opposite first and second surfaces, the circuit pattern including at least two spaced apart die contacts that protrude from the first surface of the metal substrate, the metal substrate directly interconnecting the die contacts; (b) bonding first and second terminal contacts of an electronic die to the die contacts, respectively; and (c) forming an insulator layer on the first surface of the metal substrate to encapsulate the die and the die contacts after step (b). 1. A method of making an integrated circuit package , comprising:(a) forming a circuit layered structure that includes a metal substrate and a circuit pattern, the metal substrate having opposite first and second surfaces, the circuit pattern including at least two spaced apart die contacts that protrude from the first surface of the metal substrate, the metal substrate directly interconnecting the die contacts;bonding first and second terminal, contacts of an electronic die to the die contacts, respectively, so as to form an assembly of the electronic die and the circuit layered structure having the metal substrate directly interconnecting the die contacts; andforming a first insulator layer on the first surface of the metal substrate of the assembly of the electronic die and the circuit layered structure having the metal substrate directly interconnecting the die contacts to encapsulate the die and the die contacts after step (b).2. The method of claim 1 , further comprising etching the metal substrate from the second surface of the metal substrate toward the first surface of the metal substrate after step (c) so as to form the metal substrate into a interconnection sub-structure that includes a patterned first interconnection layer and at least one first contact claim 1 , the first interconnection layer having upper and ...

POWER SEMICONDUCTOR MODULE AND COMPOSITE MODULE

A power semiconductor module includes a wiring member that electrically connects a front surface electrode of a semiconductor element and a circuit board of an insulating substrate in a housing. A resin provided in the housing covers the wiring member, and has a height in the vicinity of the wiring member. A cover covering the periphery of external terminals is provided between the resin and a first lid in the housing. A second lid is provided further outside the first lid in an aperture portion of the housing, and the space between the second lid and the first lid is filled with another resin. 1. A power semiconductor module , comprising:a housing having an aperture portion;a circuit board housed in an interior of the housing;a semiconductor element having an electrode on a front surface, a back surface being fixed to the circuit board;a wiring member electrically connecting the electrode of the semiconductor element and the circuit board;a first lid fixed in the aperture portion of the housing;a second lid fixed in the aperture portion of the housing and provided further outside the first lid;a first resin disposed between the first lid and the second lid;a second resin covering the wiring member and having an exposed surface, the exposed surface being located closer to the wiring member than the first lid;an external terminal having one end electrically and mechanically connected to the circuit board, and another end protruding further outside the second lid; anda cover covering the external terminal, and disposed between the exposed surface of the second resin and the first lid.2. The power semiconductor module according to claim 1 , wherein the external terminal is sealed with the first resin between the first lid and the second lid.3. The power semiconductor module according to claim 1 , wherein the wiring member includesa conductive plate provided to face the semiconductor element and the circuit board, anda conductive post having one end electrically and ...

Semiconductor device

A semiconductor device that includes a first die pad, an adhesive, and a second die pad fixed to the top surface of the first die pad via the adhesive. The second die pad includes a body portion and a protrusion portion provided on a side surface of the body portion. A semiconductor chip is fixed to a top surface of the second die pad, and a lead is electrically connected to the semiconductor chip. The semiconductor device further includes a package material that covers the first die pad, the second die pad, the semiconductor chip, and the lead. The first die pad is substantially as thick as the lead.

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device that includes an insulated circuit board having a conductive pattern, a first semiconductor chip with a rectangular shape connected through a first joining material to the conductive pattern, a second semiconductor chip with a rectangular shape disposed on the conductive pattern separated from the first semiconductor chip and connected through a second joining material to the conductive pattern, a terminal disposed above the semiconductor chips, respectively connected to the first and second semiconductor chips through third and fourth joining materials, the terminal having a through-hole above a place between the first and second semiconductor chips, the method including a positioning step in which the first and second semiconductor chips are respectively positioned at at least three positioning places, and at least one of the positioning places is positioned with a positioning member inserted into the through-hole. 1. A method of manufacturing a semiconductor device that comprises: an insulated circuit board having a conductive pattern; a first semiconductor chip with a rectangular shape connected through a first joining material to the conductive pattern; a second semiconductor chip with a rectangular shape disposed on the conductive pattern separated from the first semiconductor chip and connected through a second joining material to the conductive pattern; a terminal disposed above the first semiconductor chip and the second semiconductor chip , connected to the first semiconductor chip through a third joining material , and connected to the second semiconductor chip through a fourth joining material; the terminal having a through-hole above a place between the first semiconductor chip and the second semiconductor chip ,the method comprising a positioning step in whichthe first semiconductor chip is positioned at at least three positioning places,the second semiconductor chip is positioned at at least three ...

PACKAGING SOLUTIONS FOR DEVICES AND SYSTEMS COMPRISING LATERAL GaN POWER TRANSISTORS

Packaging solutions for large area, GaN die comprising one or more lateral GaN power transistor devices and systems are disclosed. Packaging assemblies comprise an interposer sub-assembly comprising the lateral GaN die and a leadframe. The GaN die is electrically connected to the leadframe using bump or post interconnections, silver sintering, or other low inductance interconnections. Then, attachment of the GaN die to the substrate and the electrical connections of the leadframe to contacts on the substrate are made in a single process step. The sub-assembly may be mounted in a standard power module, or alternatively on a substrate, such as a printed circuit board. For high current applications, the sub-assembly also comprises a ceramic substrate for heat dissipation. This packaging scheme provides interconnections with lower inductance and higher current capacity, simplifies fabrication, and enables improved thermal matching of components, compared with conventional wirebonded power modules. 1. A semiconductor device structure comprising an assembly of:a lateral GaN power transistor fabricated on a semiconductor substrate (GaN die) and packaging components comprising a leadframe and a substrate;the GaN die comprising a front surface providing source, drain and gate contact areas for the lateral GaN power transistor and a back surface for die-attach;the leadframe comprising copper, or other metal or metal alloy, having high electrical conductivity and thermal conductivity, the leadframe being patterned to provide source, drain and gate portions corresponding to source, drain and gate contact areas on the front surface of the GaN die;the source, drain and gate contact areas of the GaN die being attached and electrically connected to respective source, drain and gate portions of one side of the leadframe by low inductance connections to form an interposer sub-assembly;source, drain and gate leads of the leadframe extending laterally and vertically from the GaN die to ...

ASSEMBLY COMPRISING A VERTICAL POWER COMPONENT ASSEMBLED ON A METAL CONNECTION PLATE

A vertical power component includes a semiconductor substrate, a first electrode in contact with a lower surface of the substrate, and a second electrode in contact with an upper surface of the substrate. The vertical component is mounted to a metal connection plate via a metal spacer. The metal spacer includes a lower surface soldered to the metal connection plate and an upper surface soldered to the first electrode of the vertical power component. The metal spacer is made of a same metal as the metal connection plate. A surface are of the metal spacer mounted to the first electrode is smaller than a surface area of the first electrode. 1. An assembly , comprising:a vertical power component comprising a semiconductor substrate doped with a first conductivity type and having a lower surface, a region within the semiconductor substrate at the lower surface that is doped with a second conductivity type, a first electrode in contact with said region at the lower surface, and a second electrode in contact with an upper surface of the semiconductor substrate;a metal connection plate; anda metal spacer comprising a lower surface soldered to the metal connection plate and an upper surface soldered to a lower surface of the first electrode of the vertical power component, the metal spacer being made of a same metal as the metal connection plate;wherein a surface area of the upper surface of the metal spacer is smaller than a surface area of the lower surface of the first electrode and smaller than a surface area of said region at the lower surface of the semiconductor substrate.2. The assembly of claim 1 , wherein the same metal of the metal spacer and the metal connection plate is copper.3. The assembly of claim 1 , wherein a solder layer made of a material comprising one or more of tin claim 1 , lead claim 1 , and silver forms an interface between the lower surface of the metal spacer and the metal connection plate.4. The assembly of claim 1 , wherein the metal spacer has ...

STRUCTURE AND METHOD FOR STABILIZING LEADS IN WIRE-BONDED SEMICONDUCTOR DEVICES

A semiconductor device having a leadframe including a pad () surrounded by elongated leads () spaced from the pad by a gap () and extending to a frame, the pad and the leads having a first thickness () and a first and an opposite and parallel second surface; the leads having a first portion () of first thickness near the gap and a second portion () of first thickness near the frame, and a zone () of reduced second thickness () between the first and second portions; the second surface (a) of the first lead portions is coplanar with the second surface (a) of the second portions. A semiconductor chip () with a terminal is attached the pad. A metallic wire connection () from the terminal to an adjacent lead includes a stitch bond () attached to the first surface of the lead. 1. A leadframe comprising:a metallic pad surrounded by a plurality of leads, each of the plurality of leads including a first surface and an opposite second surface, the first surface being adapted to connect a bond wire:wherein each of the plurality of leads including a first portion, a second portion and a third portion, wherein the first portion includes a first section with a first thickness and a second section with a second thickness, the second portion includes the second thickness, and the third portion includes the first thickness.2. The leadframe of claim 1 , wherein the metallic pad and the plurality of leads include a base metal selected from a group consisting of copper claim 1 , copper alloys claim 1 , aluminum claim 1 , aluminum alloys claim 1 , iron-nickel alloys claim 1 , and Kovar.3. The leadframe of claim 2 , wherein the first surface includes a layer of nickel plated on the base metal and a layer of palladium plated on the nickel layer claim 2 , and a layer of gold plated on the palladium layer.4. A semiconductor device comprising:a metallic pad; anda semiconductor chip, attached to the metallic pad, and electrically connected to a first surface of each of a plurality of leads, ...

ELECTRONIC APPARATUS WITH POCKET OF LOW PERMITTIVITY MATERIAL TO REDUCE ELECTROMAGNETIC INTERFERENCE

An electronics apparatus including a first substrate having a first surface and a second surface, a first switch connected to a second switch and soldered in series on the first surface of the first substrate creating a connection to allow switching between the first switch and the second switch at high frequency, an insulation having a third surface attached to the second surface of the first substrate, and a second substrate having a pocket of low permittivity located between the first switch and the second switch on a fourth surface of the insulation, the fourth surface being opposite to the third surface where the first switch and the second switch are located. 1: An electronics apparatus comprising:a first substrate including a first surface and a second surface;a first switch connected to a second switch and soldered in series with the first switch on the first surface of the first substrate creating an electrical connection to allow high frequency switching between the first switch and the second switch;insulation including a first surface attached to the second surface of the first substrate; anda second substrate having a pocket of low permittivity material located between the first switch and the second switch on a second surface of the insulation, the second surface of the insulation being opposite to the first surface of the insulation where the first switch and the second switch are located.2: The apparatus according to claim 1 , wherein the pocket of low permittivity material formed of an air pocket is completely enclosed by the insulation and the second substrate.3: The apparatus according to claim 2 , wherein the air pocket is substantially rectangular in shape located directly below the electrical connection.4: The apparatus according to claim 2 , wherein the air pocket extends along the length of the second substrate.5: The apparatus according to claim 1 , wherein the first substrate is made of copper.6: The apparatus according to claim 1 , wherein ...

Flat No-Leads Package With Improved Contact Pins

According to an embodiment of the present disclosure, a method for manufacturing an integrated circuit (IC) device may include mounting an IC chip onto a center support structure of a leadframe. The leadframe may include: a plurality of pins extending from the center support structure; a groove running perpendicular to the individual pins of the plurality of pins around the center support structure; and a bar connecting the plurality of pins remote from the center support structure. The method may further include: bonding the IC chip to at least some of the plurality of pins; encapsulating the leadframe and bonded IC chip, including filling the groove with encapsulation compound; removing the encapsulation compound from the groove, thereby exposing at least a portion of the individual pins of the plurality of pins; plating the exposed portion of the plurality of pins; and cutting the IC package free from the bar by sawing through the encapsulated lead frame along the groove using a first saw width less than a width of the groove. 1. A method for manufacturing an integrated circuit (IC) device in a flat no-leads package , the method comprising: a plurality of pins extending from the center support structure;', 'a groove running perpendicular to the individual pins of the plurality of pins around the center support structure; and', 'a bar connecting the plurality of pins remote from the center support structure;, 'mounting an IC chip onto a center support structure of a leadframe, the leadframe includingbonding the IC chip to at least some of the plurality of pins;encapsulating the leadframe and bonded IC chip, including filling the groove with encapsulation compound;removing the encapsulation compound from the groove, thereby exposing at least a portion of the individual pins of the plurality of pins;plating the exposed portion of the plurality of pins; andcutting the IC package free from the bar by sawing through the encapsulated lead frame along the groove using a ...

Waterproof Electronic Device and Manufacturing Method Thereof

A waterproof electronic device includes: an electronic component module having an electronic component including a semiconductor element, a heat dissipating member provided on the electronic component in a thermally conductive manner, and an insulating material that surrounds the electronic component in such a manner that one surface of the heat dissipating member is exposed; and a waterproof film that is formed at least on whole surfaces in regions of the electronic component module that are to be immersed in a coolant. 1. A waterproof electronic device , comprising:an electronic component module having an electronic component including a semiconductor element, a heat dissipating member provided on the electronic component in a thermally conductive manner, and an insulating material that surrounds the electronic component in such a manner that one surface of the heat dissipating member is exposed; anda waterproof film that is formed at least on whole surfaces in regions of the electronic component module that are to be immersed in a coolant.2. The waterproof electronic device according to claim 1 , wherein:the heat dissipating member has a plurality of cooling fins and the waterproof film is formed to cover surfaces of the cooling fins.3. The waterproof electronic device according to claim 1 , wherein:the waterproof film is made of a metal material.4. The waterproof electronic device according to claim 1 , wherein:the waterproof film is made of a metal material having a smaller ionization tendency than that of hydrogen, or a metal material having a surface on which an oxidation film is formed.5. The waterproof electronic device according to claim 1 , wherein:the electronic component module has a plurality of leads that are connected to electrodes of the semiconductor element and extend to outside from one side surface of the insulating material and from another side surface opposite to the one side surface, respectively.6. The waterproof electronic device according ...

SEMICONDUCTOR LEAD FRAME, SEMICONDUCTOR PACKAGE, AND MANUFACTURING METHOD THEREOF

A semiconductor lead frame includes a metal plate and a semiconductor chip mounting area provided on a top surface of the metal plate. A first plating layer for an internal terminal is provided around the semiconductor chip mounting area. A second plating layer for an external terminal is provided on a back surface of the metal plate at a location opposite to the semiconductor chip mounting area. The first plating layer includes a fall-off prevention structure for preventing the first plating layer from falling off from an encapsulating resin when the top surface of the metal plate is encapsulated in the encapsulating resin. The second plating layer does not include the fall-off prevention structure. 1. A semiconductor lead frame comprising:a metal plate;a semiconductor chip mounting area provided on a top surface of the metal plate;a first plating layer for an internal terminal provided around the semiconductor chip mounting area; anda second plating layer for an external terminal provided on a back surface of the metal plate at a location opposite to the semiconductor chip mounting area,wherein the first plating layer includes a fall-off prevention structure for preventing the first plating layer from falling off from an encapsulating resin when the top surface of the metal plate is encapsulated in the encapsulating resin, andwherein the second plating layer does not include the fall-off prevention structure.2. The semiconductor lead frame as claimed in claim 1 , wherein the fall-off prevention structure of the first plating layer includes a reverse tapered lateral surface that causes a cross-sectional shape of the first plating layer to be formed into an inversed trapezoid shape tapered toward the metal plate.3. The semiconductor lead frame as claimed in claim 2 , wherein a taper angle of the reverse tapered lateral surface is in a range of 30 to 70 degrees.4. The semiconductor lead frame as claimed in claim 1 , wherein the fall-off prevention structure of the ...

SEMICONDUCTOR DEVICE PACKAGE

A semiconductor device package which decrease deterioration on characteristics of the chip is provided. 1. A semiconductor device package , comprising:a chip having a plurality of electrodes and a circuit, each of the electrodes provided on a first surface of the chip, the circuit being connected to the electrodes;a resin member provided on the first surface of the chip; andan encapsulating member encapsulating the chip and the resin member;wherein elastic modulus of the resin member is set in a prescribed range such that drift of an output voltage of the circuit is in a range within not less than 0.0 mV and not more than 1.5 mV.2. The package according to claim 1 , whereinthe elastic modulus of the resin member is not less than 0.1 GPa and not more than 0.1 GPa.3. package according to claim 1 , whereinthe elastic modulus of the resin member is not less than 0.00 GPa and not more than 0.02 GPa.4. The package according to claim 2 , whereinthe elastic modulus of the resin member is not less than 0.00 GPa and not more than 0.02 GPa.5. The package according to claim 1 , whereinthe resin member covers the chip including the electrodes.6. The package according to claim 1 , whereinthe resin member is provided near an end portion of the chip.7. The package according to claim 1 , whereinThe resin member is provided to be corresponding to a surface of the circuit.8. The package according to claim 2 , whereinthe resin member covers the chip including the electrodes.9. The package according to claim 2 , whereinthe resin member is provided near an end portion of the chip.10. package according to claim 2 , whereinThe resin member is provided to be corresponding to a surface of the circuit.11. The package according to claim 3 , whereinthe resin member covers the chip including the electrodes.12. The package according to claim 3 , whereinthe resin member is provided near an end portion of the chip.13. The package according to claim 3 , whereinThe resin member is provided to be ...

PACKAGE FOR A SURFACE-MOUNT SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A method for manufacturing a surface-mount electronic device includes making a first partial cut from a bottom of an assembly that includes a first semiconductor body that is disposed on a first die pad, a second semiconductor body that is disposed on a second die pad, and a plurality of terminal regions that is disposed between the first and second die pads. The first partial cut forms a recess by removing a portion of each of the terminal regions. The recess is defined by a transverse wall, a first sidewall, and a second sidewall. The first and second sidewalls and the transverse wall are coated with an anti-oxidation layer. A second partial cut is made from the top, where the second partial cut removes the transverse wall, separates the first and second semiconductor bodies, and has a width that is greater than a width of the first partial cut. 1. A method for manufacturing a surface-mount electronic device , comprising:making a first partial cut of an assembly including at least a first die pad and at least a second die pad and a first semiconductor body and a second semiconductor body, the first semiconductor body disposed on the first die pad and the second semiconductor body disposed on the second die pad, said assembly further including a plurality of terminal regions disposed between the first and second die pads, and a dielectric region overlying the first and second semiconductor bodies and the plurality of terminal regions, each terminal region being delimited by a first region surface and by a second region surface disposed opposite the first region surface, the first region surface facing the dielectric region, said first partial cut forming a recess by removing a portion of each of said terminal regions starting from the respective second region surfaces, said recess defined by a transverse wall and a first sidewall and a second sidewall;coating the first and second sidewalls of each terminal region with an anti-oxidation layer; andmaking a second ...

SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor package includes a lower package including a lower substrate, a lower semiconductor chip, and a lower molding layer exposing an upper surface of the lower semiconductor chip, bumps on the lower substrate, the bumps being spaced apart from the lower semiconductor chip, a lead frame on the lower semiconductor chip and on the bumps, the lead frame being electrically connected to the bumps and having a thermal conductivity of about 100 W/mk to about 10,000 W/mk, and an upper package on the lead frame and electrically connected to the lead frame. 1. A semiconductor package , comprising:a lower package including a lower substrate, a lower semiconductor chip, and a lower molding layer exposing an upper surface of the lower semiconductor chip;bumps on the lower substrate, the bumps being spaced apart from the lower semiconductor chip;a lead frame on the lower semiconductor chip and on the bumps, the lead frame being electrically connected to the bumps; andan upper package on the lead frame and electrically connected to the lead frame, a portion of the lead frame on the bumps being further recessed toward the lower substrate than a portion of the lead frame on the lower semiconductor chip.2. The semiconductor package as claimed in claim 1 , wherein the lead frame has a thermal conductivity of about 100 W/mk to about 10 claim 1 ,000 W/mk.3. The semiconductor package as claimed in claim 1 , wherein the lead frame includes copper or aluminum.4. The semiconductor package as claimed in claim 1 , wherein an uppermost surface of the bumps has a lower level than an upper surface of the lower semiconductor chip.5. The semiconductor package as claimed in claim 1 , wherein:the lead frame includes a lead part for power supply and a lead part for signal transmission;the bumps include a bump for power supply and a bump for signal transmission; andthe lead part for power supply is electrically connected to the bump for power supply, and the lead part for signal transmission ...

Integrated Circuit Device with Plating on Lead Interconnection Point and Method of Forming the Device

An integrated circuit (IC) device includes an IC die and a plurality of leads. Each lead includes an unplated proximal end including a first material, and an unplated distal end including the first material. A plated bond wire portion extends between the proximal and distal ends and includes the first material and a plating of a second material thereon. A plurality of bond wires extend between the IC die and the plated bond wire portions of the leads. An encapsulation material surrounds the IC die and bond wires so that the unplated proximal end and plated bond wire portion of each lead are covered by the encapsulation material. 1. An integrated circuit (IC) device , comprising:an IC die; an unplated proximal end comprising a first material;', 'an unplated distal end comprising the first material; and', 'a plated bond wire portion between the unplated proximal end and the unplated distal end and comprising the first material and a plating comprising a second material on the first material, a length of the plated bond wire portion along the lead extension direction being greater than a length of the unplated proximal end along the lead extension direction;, 'a plurality of leads, each lead of the plurality of leads extending along a lead extension direction and comprisinga plurality of bond wires, each bond wire of the plurality of bond wires extending between the IC die and the plated bond wire portion of a respective lead; andan encapsulation material surrounding the IC die and the plurality of bond wires such that the unplated proximal end and plated bond wire portion of each lead are covered by the encapsulation material.2. The IC device of claim 1 , wherein:each lead further comprises an unplated intermediate portion between the plated bond wire portion and the unplated distal end; andthe encapsulation material also covers the unplated intermediate portion of each lead.3. The IC device of claim 1 , wherein each of the plurality of bond wires comprises the first ...

WAFER-LEVEL CHIP-SCALE PACKAGE INCLUDING POWER SEMICONDUCTOR AND MANUFACTURING METHOD THEREOF

A wafer-level chip-scale package includes: a power semiconductor comprising a first semiconductor device formed on a semiconductor substrate, and a second semiconductor device formed on the semiconductor substrate; a common drain electrode connected to the first semiconductor device and the second semiconductor device; a first source metal bump formed on a surface of the first semiconductor device; and a second source metal bump formed on the surface of the second semiconductor device; wherein the first source metal bump, the common drain electrode, and the second source metal bump form a current path in an order of the first source metal bump, the common drain electrode, and the second source metal bump. 1. A wafer-level chip-scale package comprising: a first semiconductor device formed on a semiconductor substrate, and', 'a second semiconductor device formed on the semiconductor substrate;, 'a power semiconductor comprising'}a common drain electrode connected to the first semiconductor device and the second semiconductor device;a first source metal bump formed on a surface of the first semiconductor device; anda second source metal bump formed on the surface of the second semiconductor device,wherein the first source metal bump, the common drain electrode, and the second source metal bump form a current path in an order of the first source metal bump, the common drain electrode, and the second source metal bump.2. The wafer-level chip-scale package of claim 1 , wherein:the first semiconductor device further comprises first source pads and first gate pads;the second semiconductor device further comprises second source pads and second gate pad;the first source pad and the second source pad are respectively connected to the first source bump and the second source bump; andthe first source pads and the second source pads are physically separated.3. The wafer-level chip-scale package of claim 1 , further comprising:a back metal layer formed on a bottom of the power ...

LEADLESS SEMICONDUCTOR PACKAGES, LEADFRAMES THEREFOR, AND METHODS OF MAKING

A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer. 1. A semiconductor device , comprising:at least four semiconductor die;a plurality of contacts adjacent to each of the at least four semiconductor die;at least four tie bars adjacent to each of the at least four semiconductor die;an encapsulant coupled at least partially over the at least four semiconductor die and the plurality of contacts; andat least four trenches in a first surface of the encapsulant laterally adjacent to the plurality of contacts for a full vertical thickness of the plurality of contacts to expose the plurality of contacts, the at least four trenches extending only partially into a thickness of the encapsulant.2. The device of claim 1 , further comprising a conductive layer over a flank of each of the plurality of contacts for the full vertical thickness of each of the plurality of contacts.3. The device of claim 1 , further comprising a second plurality of trenches in the first surface of the encapsulant between each of the at least four semiconductor die and each of the plurality of contacts.4. The device of claim 1 , further comprising a die pad under each of the at least four semiconductor die claim 1 , wherein the at least four tie bars extend from a second surface of the encapsulant to each of the resulting at least four die pads.5. The ...

Semiconductor device with island and associated leads

A semiconductor part includes a resin package and an exposed portion exposed from a bottom surface of the resin package. The exposed portion has a first diagonal line perpendicular to both first and third sides of the package as viewed from the bottom surface. The exposed portion also has a second diagonal line perpendicular to both the second fourth side in the bottom view. A first lead terminal portion opposes the exposed portion and has a first shape in the bottom view. A second lead terminal portion, also opposing the exposed portion, has a second shape in the bottom view. A third lead terminal portion opposing the exposed portion, also has the second shape in the bottom view. A fourth lead terminal portion, similarly opposed to the exposed portion, likewise has the second shape in the bottom view.

Matrix lid heatspreader for flip chip package

A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array ( 310 ) designed for direct attachment to an array of integrated circuit die ( 306 ) by including a thermal interface adhesion layer ( 308 ) to each die ( 306 ) and encapsulating the attached heat spreader lid array ( 310 ) and array of integrated circuit die ( 306 ) with mold compound ( 321 ) except for planar upper lid surfaces of the heat spreader lids ( 312 ).

Method for manufacturing semiconductor device and semiconductor device

일 실시 형태에 의한 반도체 장치의 제조 방법에서는, 인접하는 디바이스 영역의 사이에서 연결된 제1 리드와 제2 리드의 각각의 하면을 연통되도록 홈부가 형성된 리드 프레임을 준비한다. 이어서, 제1 블레이드를 사용하여 상기 제1 및 제2 리드의 연결부의 일부를 절삭한 후, 상기 홈부 내에 형성된 금속 칩을 제거한다. 이어서, 상기 금속 칩을 제거한 후, 상기 제1 및 제2 리드의 노출면에 도금법에 의해 금속막을 형성한 후, 제2 블레이드를 사용하여 제1 및 제2 리드의 연결부의 잔류부를 절단한다. 이때, 상기 제2 블레이드가 상기 홈부에 접촉하지 않도록 절단한다.

Method for manufacturing semiconductor device and semiconductor device

在一个实施方式所涉及的半导体器件的制造方法中，准备以与在相邻的器件区域之间连结的第1引线和第2引线各自的下表面连通的方式形成有槽部的引线框架。然后，使用第1刀具将上述第1引线及第2引线的连结部的一部分切削后，去除在上述槽部内形成的金属屑。然后，在去除上述金属屑后，利用镀敷法在上述第1引线及第2引线的露出面上形成金属膜，之后，使用第2刀具切断第1引线及第2引线的连结部的残留部。此时，上述第2刀具以不与上述槽部接触的方式进行切断。

Assembly comprising a vertical power component mounted on a metal connection plate

Assemblage comportant un composant vertical de puissance monté sur une plaque métallique de connexion La présente description concerne un assemblage comportant : - un composant vertical de puissance (100) comportant un substrat semiconducteur (101), une première électrode (A2) en contact avec une face inférieure du substrat (101), et une deuxième électrode (A1) en contact avec une face supérieure du substrat (101) ; - une plaque métallique de connexion (150) disposée du côté de la face inférieure du substrat (101) ; et - une entretoise métallique (140) comportant une face inférieure soudée à la plaque métallique de connexion (150) et une face supérieure soudée à la première électrode (A2) du composant vertical de puissance, l'entretoise métallique (140) étant en le même métal que la plaque métallique de connexion (150). Figure pour l'abrégé : Fig. 1 Assembly comprising a vertical power component mounted on a metal connection plate The present description relates to an assembly comprising: - a vertical power component (100) comprising a semiconductor substrate (101), a first electrode (A2) in contact with a face lower side of the substrate (101), and a second electrode (A1) in contact with an upper face of the substrate (101); - a metal connection plate (150) disposed on the side of the lower face of the substrate (101); and - a metal spacer (140) comprising a lower face welded to the metal connection plate (150) and an upper face welded to the first electrode (A2) of the vertical power component, the metal spacer (140) being in the same metal as the metal connection plate (150). Figure for the abstract: Fig. 1

The matrix lid radiator of Flip-Chip Using

本公开涉及倒装芯片封装的矩阵盖散热器。提供一种方法和装置以用于制作基于引线框的热增强倒装芯片封装，其中带有散热器盖阵列（310），其通过将热界面粘附层（308）包括在每个芯片（306）以及用模塑化合物（321）封装除了所述散热器（312）的平面上盖表面的附着的散热器盖阵列（310）和集成电路管芯（306）阵列而被设计为直接附着于一个集成电路管芯（306）阵列。

IC PACKAGE WITH INTEGRATED INDUCTANCE AND METHOD OF MANUFACTURE THEREOF

Halbleitergehäuse (102, 402, 502), aufweisend:einen integrierten Schaltkreis (IC) (110, 310, 410, 510), der an einem Chipkontaktierungssegment (331, 431, 531) eines ersten strukturierten leitfähigen Trägers (330, 430, 530) befestigt ist;wobei der IC (110, 310, 410, 510) mit einem Schaltknotensegment (314, 414, 514) des ersten strukturierten leitfähigen Trägers (330, 430, 530) durch einen elektrischen Verbinder (338, 438, 538) gekoppelt ist;einen zweiten strukturierten leitfähigen Träger (340, 440, 540), der über dem IC (110, 310, 410, 510) angeordnet ist;ein magnetisches Material (350, 450, 590), das über dem zweiten strukturierten leitfähigen Träger (340, 440, 540) angeordnet ist;einen dritten strukturierten leitfähigen Träger (360, 460, 560), der Finger (362, 364, 366) aufweist, die über dem magnetischen Material (350, 450, 590) angeordnet sind, und Beine (372, 374, 376) aufweist, die im Wesentlichen senkrecht zu den Fingern (362, 364, 366) angeordnet sind und sich über eine Dicke des magnetischen Materials erstrecken;wobei der zweite strukturierte leitfähige Träger (340, 440, 540) und der dritte strukturierte leitfähige Träger (360, 460, 560) elektrisch gekoppelt sind, indem Enden der Beine (372, 374, 376) mittels elektrisch leitfähigem Klebematerial (358), insbesondere mittels leitfähigem Epoxid, einem Lötmittel, einem leitfähigen gesinterten Material oder einem durch Diffusion gebondetem Material, mit dem zweiten strukturierten leitfähigen Träger (340, 440, 540) verbunden sind, um Wicklungen einer integrierten Induktivität (104, 304, 404, 504) in dem Halbleitergehäuse zu bilden (102, 402, 502). A semiconductor package (102, 402, 502) comprising: an integrated circuit (IC) (110, 310, 410, 510) attached to a die bonding segment (331, 431, 531) of a first patterned conductive carrier (330, 430, 530) the IC (110, 310, 410, 510) being coupled to a switch node segment (314, 414, 514) of the first patterned conductive support (330, 430, 530) by an electrical connector ...

Packaging solutions for devices and systems comprising lateral GaN power transistors

Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof. In the packaging assembly, a GaN die, comprising one or more lateral GaN power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling. Preferred embodiments facilitate alignment and registration of high current/low inductance interconnects for lateral GaN devices, in which contact areas or pads for source, drain and gate contacts are provided on the front-side of the GaN die. By eliminating wirebonding, and using low inductance interconnections with high electrical and thermal conductivity, PQFN technology can be adapted for packaging GaN die comprising one or more lateral GaN power transistors.

Semiconductor device, method of manufacturing a semiconductor device, and positioning jig

本发明提供可提高各半导体芯片的定位精度的半导体装置，该半导体装置在带有导电图案的绝缘基板与端子之间并联连接有多个小型半导体芯片。本发明还提供这种半导体装置的制造方法、以及在该制造方法中使用的定位治具。本发明的半导体装置具有：带有导电图案的绝缘基板；通过第1接合材料连接于导电图案的矩形的第1半导体芯片；在导电图案上与第1半导体芯片隔开间隔地配置、通过第2接合材料连接于导电图案的矩形的第2半导体芯片；以及配置于第1半导体芯片以及第2半导体芯片的上方、通过第3接合材料连接于第1半导体芯片、且通过第4接合材料连接于第2半导体芯片的端子。该端子在第1半导体芯片与第2半导体芯片之间的上方具有贯通孔。

Integrated circuit device with plating on lead interconnection point and method of forming the device

本发明涉及在引线互连点上具有镀层的集成电路器件及其形成方法。一种集成电路(IC)器件包括IC裸片和多个引线。每个引线包括：包含第一材料的未镀制的近端和包含该第一材料的未镀制的远端。镀制的键合线部分在近端和远端之间延伸并且包含第一材料和在第一材料上的第二材料的镀层。多个键合线在IC裸片和引线的镀制的键合线部分之间延伸。包封材料包围IC裸片和键合线，使得每个引线的未镀制的近端和镀制的键合线部分被该包封材料覆盖。

Semiconductor device

A semiconductor device that includes a first die pad, an adhesive, and a second die pad fixed to the top surface of the first die pad via the adhesive. The second die pad includes a body portion and a protrusion portion provided on a side surface of the body portion. A semiconductor chip is fixed to a top surface of the second die pad, and a lead is electrically connected to the semiconductor chip. The semiconductor device further includes a package material that covers the first die pad, the second die pad, the semiconductor chip, and the lead. The first die pad is substantially as thick as the lead.

Addition-curable silicone composition

　Provided is an addition-curable silicone composition having little shrinkage or change in hardness due to heat, a cured silicone product of which obtained has excellent adhesiveness and appearance and makes it possible to protect metals, especially silver, from corrosion. An addition-curable silicone composition containing 100 parts by mass of polyorganosiloxane having an alkenyl group, polyorganohydrogensiloxane in an amount to make 0.9-3.0 mol of hydrogen atoms bonded to silicon atoms per 1 mol total amount of this alkenyl group, a catalytic amount of hydrosilylation catalyst, 0.01-10 parts by mass of adhesiveness-imparting agent, and 0.001-0.015 parts by mass, calculated in terms of metal atoms, of carboxylic acid metal salt indicated by (R 3 COO) k M (M indicates a metal atom selected from Ce, Fe, Cr, La, Nd, Pr, and Sm, k indicates a positive number of 2-4, and R 3 indicates a substituted or unsubstituted hydrocarbon group having 4-10 carbon atoms).

Integrated antenna package

提供一种集成电路IC封装，具有从所述IC封装伸出，用于将所述IC封装与印刷电路板PCB电性连接的一个或多个引脚。所述IC封装具有带有第一电子元件的第一管芯、带有第二电子元件的第二管芯、以及具有平面表面的导电板。所述第一电子元件可以是半导体电源装置而所述第二电子元件可以是控制电路。所述导电板的平面表面被同时电性连接到所述第一管芯的平面表面以及一个或更多个引脚，从而在所述第一管芯和所述一个或更多个引脚之间建立电性连接。所述第二管芯可以被布置在所述导电板的顶部。作为备选方案，具有第三电子元件的第三管芯可以被布置在所述导电板的顶部。

Semiconductor device manufacturing method

This invention enhances reliability of an electrical test. A semiconductor device manufacturing method in which a potential (first potential) is supplied by bringing a plurality of first and second test terminals into contact with a plurality of leads, respectively in the step of supplying the potential to the leads (first leads) to carry out the electrical test. The first test terminals come into contact with the leads, individually, and the second test terminals come into contact with the leads in one batch.

Addition-curing silicone composition

得られるシリコーン硬化物が、優れた接着性、外観を有するとともに、金属、特に銀を腐食から保護することができ、かつ熱による収縮および硬さの変化が少ない付加硬化型シリコーン組成物を提供する。アルケニル基を有するポリオルガノシロキサン１００質量部、ポリオルガノハイドロジェンシロキサンを、上記アルケニル基の合計量１モルに対してケイ素原子に結合した水素原子が０．９〜３．０モルとなる量、ヒドロシリル化反応触媒の触媒量、接着性付与剤の０．０１〜１０質量部、および（Ｒ３ＣＯＯ）ｋＭ（Ｍは、Ｃｅ、Ｆｅ、Ｃｒ、Ｌａ、Ｎｄ、Ｐｒ、Ｓｍから選ばれる金属原子を、ｋは２〜４の正数を、Ｒ３は置換または非置換の炭素数４〜１０の炭化水素基を示す。）で示されるカルボン酸金属塩を金属原子換算で０．００１〜０．０１５質量部、含有する付加硬化型シリコーン組成物。 Provided is an addition-curable silicone composition in which the obtained silicone cured product has excellent adhesion and appearance, can protect metals, particularly silver, from corrosion, and has little shrinkage and change in hardness due to heat. . 100 parts by mass of polyorganosiloxane having an alkenyl group, an amount in which hydrogen atoms bonded to silicon atoms of polyorganohydrogensiloxane are 0.9 to 3.0 mol with respect to 1 mol of the total amount of alkenyl groups, hydrosilyl The catalytic amount of the oxidization reaction catalyst, 0.01 to 10 parts by mass of the adhesion-imparting agent, and (R3COO) kM (M is a metal atom selected from Ce, Fe, Cr, La, Nd, Pr, and Sm, k Represents a positive number of 2 to 4, and R3 represents a substituted or unsubstituted hydrocarbon group having 4 to 10 carbon atoms.) 0.001 to 0.015 parts by mass in terms of metal atom And an addition-curable silicone composition.

Manufacturing method of semiconductor device and semiconductor device

Flat no-leads package with improved contact leads

According to an embodiment of the present disclosure, a method for manufacturing an integrated circuit (IC) device may include mounting an IC chip onto a center support structure of a leadframe. The leadframe may include: a plurality of pins extending from the center support structure; a groove running perpendicular to the individual pins of the plurality of pins around the center support structure; and a bar connecting the plurality of pins remote from the center support structure. The method may further include: bonding the IC chip to at least some of the plurality of pins; encapsulating the leadframe and bonded IC chip, including filling the groove with encapsulation compound; removing the encapsulation compound from the groove, thereby exposing at least a portion of the individual pins of the plurality of pins; plating the exposed portion of the plurality of pins; and cutting the IC package free from the bar by sawing through the encapsulated lead frame along the groove using a first saw width less than a width of the groove.

Method of manufacturing semiconductor device and semiconductor device

In a method of manufacturing a semiconductor device according to an embodiment, a lead frame is provided, the lead frame having a trench part formed thereon so as to communicate bottom surfaces of a first lead and a second lead, which are coupled to each other between device regions adjacent to each other. Then, after a part of a coupling part between the first and second leads is cut by using a first blade, metal wastes formed inside the trench part are removed. Then, after the metal wastes are removed, a metal film is formed on exposed surfaces of the first and second leads by a plating method, and then, a remaining part of the coupling part between the first and second leads is cut by using a second blade. At this time, the cutting is performed so that the second blade does not contact the trench part.

Flip-Chip Package Assembly

In a described example, a method includes: forming cavities in a die mount surface of a package substrate, the cavities extending into the die mount surface of the package substrate at locations corresponding to post connects on a semiconductor die to be flip-chip mounted to the package substrate; placing flux in the cavities; placing solder balls on the flux; and performing a thermal reflow process and melting the solder balls to form solder pads in the cavities on the package substrate.

半導体装置

樹脂パッケージと、第１および第２のパッドを表面に有する半導体チップと、一方面に前記半導体チップの裏面が接合され、反対側の他方面が、前記第１のパッドと外部との電気接続のための第１のパッド接続端子および前記半導体チップの裏面と外部との電気接続のための裏面接続端子として互いに分離して、前記樹脂パッケージの底面から部分的に露出するリード一体型アイランドと、一方面が、前記第２のパッドとワイヤにより接続され、反対側の他方面が、前記第２のパッドと外部との電気接続のための第２のパッド接続端子として、前記樹脂パッケージの底面から露出するリードとを含み、前記半導体チップは、前記第１のパッド接続端子側に片寄った位置に配置され、前記第１のパッドと前記リード一体型アイランドの前記一方面とがワイヤにより接続されている半導体装置。

半導体装置

【課題】パッドとリードとの間にワイヤを良好に架設することができながら、樹脂パッケージの平面積（実装面積）の低減を図ることができる、半導体装置を提供すること。【解決手段】樹脂パッケージ４と、第１および第２のパッド６５，６６を表面に有する半導体チップ３と、樹脂パッケージ４に封止され、樹脂パッケージ４の底面から部分的に露出するリード一体型アイランド５と、リード一体型アイランド５と分離して形成されており、樹脂パッケージ４に封止され、樹脂パッケージ４の底面から露出するリード６とを含み、半導体チップ３の重心が、樹脂パッケージ４の重心からずれている、半導体装置１を提供する。半導体装置１において、リード一体型アイランド５のリード部分８は、リード６と同じ大きさで形成されている。【選択図】図１

Semiconductor device

A semiconductor device of the present invention includes a resin package, a semiconductor chip sealed in the resin package, and having first and second pads on a front surface, a lead integrated island sealed in the resin package, to one surface of which a back surface of the semiconductor chip is bonded, and the other surface of an opposite side to the one surface of which is partially exposed from a bottom surface of the resin package as a first pad connecting terminal for electrical connection between the first pad and outside and a back connecting terminal for electrical connection between the back surface of the semiconductor chip and outside separately from each other, and a lead formed separately from the lead integrated island, sealed in the resin package, one surface of which is connected with the second pad by a wire, and the other surface of an opposite side to the one surface of which is exposed from a bottom surface of the resin package as a second pad connecting terminal for electrical connection between the second pad and outside, and the semiconductor chip is, on the one surface of the lead integrated island, disposed at a position one-sided to the first pad connecting terminal side, and the first pad and the one surface of the lead integrated island are connected by a wire.

半導体装置

【課題】パッドとリードとの間にワイヤを良好に架設することができながら、樹脂パッケージの平面積（実装面積）の低減を図ることができる、半導体装置を提供すること。 【解決手段】樹脂パッケージ４と、第１および第２のパッド６５，６６を表面に有する半導体チップ３と、樹脂パッケージ４に封止され、樹脂パッケージ４の底面から部分的に露出するリード一体型アイランド５と、リード一体型アイランド５と分離して形成されており、樹脂パッケージ４に封止され、樹脂パッケージ４の底面から露出するリード６とを含み、半導体チップ３の重心が、樹脂パッケージ４の重心からずれている、半導体装置１を提供する。 【選択図】図１

Semiconductor device

A semiconductor device of the present invention includes a resin package, a semiconductor chip sealed in the resin package, and having first and second pads on a front surface, a lead integrated island sealed in the resin package, to one surface of which a back surface of the semiconductor chip is bonded, and the other surface of an opposite side to the one surface of which is partially exposed from a bottom surface of the resin package as a first pad connecting terminal for electrical connection between the first pad and outside and a back connecting terminal for electrical connection between the back surface of the semiconductor chip and outside separately from each other, and a lead formed separately from the lead integrated island, sealed in the resin package, one surface of which is connected with the second pad by a wire, and the other surface of an opposite side to the one surface of which is exposed from a bottom surface of the resin package as a second pad connecting terminal for electrical connection between the second pad and outside, and the semiconductor chip is, on the one surface of the lead integrated island, disposed at a position one-sided to the first pad connecting terminal side, and the first pad and the one surface of the lead integrated island are connected by a wire.

半導体装置

【課題】パッドとリードとの間にワイヤを良好に架設することができながら、樹脂パッケージの平面積（実装面積）の低減を図ることができる、半導体装置を提供すること。【解決手段】底面視において、第１側面１０、第２側面１１、第３側面１７および第４側面１８を有する樹脂パッケージ４と、樹脂パッケージ４の底面から露出し、第１側面１０、第２側面１１、第３側面１７および第４側面１８と平行ではない複数の辺を有するアイランド部分７と、アイランド部分７に対向して配置され、底面視において第１の形状を有するパッド接続端子４１と、アイランド部分７に対向して配置され、底面視において第２の形状を有するパッド接続端子２７，５２，６３とを含む、半導体装置１を提供する。【選択図】図２