Tunneldiode und Speicheranordnung mit derselben

Memristive Einheit auf Grundlage einer Alkali-Dotierung von Übergangsmetalloxiden

Eine memristive Einheit beinhaltet eine erste leitfähige Materialschicht. Eine Oxidmaterialschicht ist auf der ersten leitfähigen Schicht angeordnet. Eine zweite leitfähige Materialschicht ist auf der Oxidmaterialschicht angeordnet, wobei die zweite leitfähige Schicht eine Metall-Alkali-Legierung aufweist.

Integrated circuit for memory module of e.g. portable computer, has resistance switching rods electrically connected with pair of electrodes and embedded partly in thermal check matrix with material having high electrical resistance

The circuit has a switching element (10) for switching between two states with different electrical resistances. A set of resistance switching rods (18a-18d) is electrically connected with a pair of electrodes (12, 20) and is embedded partly in a thermal check matrix. The thermal check matrix has a material with a high specific electrical resistance and a low dielectric constant. The thermal check matrix includes an exposable material and polyimide. The resistance switching rod exhibits a length ranging between 10 and 100 nanometers. Independent claims are also included for the following: (1) a memory component with a memory cell (2) a method for production of a resistance switching element.

Glaszusammensetzung

Halbleiterwiderstandsspeicherbauelement und Herstellungsverfahren

Halbleiterwiderstandsspeicherbauelement mit einem Substrat (1) mit einer Oberseite, Wortleitungsstegen (5), die parallel im Abstand zueinander auf der Oberseite angeordnet sind, Bitleitungen (BLi), die im Abstand zueinander quer zu den Wortleitungen (WLk) angeordnet sind, Source-/Drain-Bereichen, die als dotierte Bereiche jeweils benachbart zu einem Wortleitungssteg (5) und zu einem Zwischenraum zwischen Wortleitungsstegen (5) ausgebildet sind, Aussparungen (13) des Substrates (1), die in jedem zweiten Zwischenraum zwischen den Wortleitungsstegen (5) gebildet sind, wobei die benachbart zu einem betreffenden Zwischenraum angeordneten Source-/Drain-Bereiche jeweils an eine Seitenwand der betreffenden Aussparung (13) angrenzen und die Bitleitungen (BLi) Anteile aufweisen, die in den Aussparungen (13) angeordnet sind, Widerstandsschichten (17), die an den Seitenwänden der Aussparungen (13) jeweils zwischen einem Source-/Drain-Bereich und einem Anteil einer Bitleitung (BLi) angeordnet und aus ...

Verfahren zum Herstellen von Speicherzellen, die durch eine hohlraumfreie dielektrische Struktur getrennt sind

Verschiedene Ausführungsformen der vorliegenden Anmeldung sind auf einen integrierten Chip mit Speicherzellen gerichtet, die durch eine hohlraumfreie dielektrische Struktur getrennt sind. Bei einigen Ausführungsformen wird ein Paar Speicherzellenstrukturen auf einer dielektrischen Durchkontaktierungsschicht hergestellt, wobei die Speicherzellenstrukturen durch einen Zwischenzellenbereich getrennt sind. Eine Zwischenzellen-Füllschicht wird so hergestellt, dass sie die Speicherzellenstrukturen und die dielektrische Durchkontaktierungsschicht bedeckt und außerdem den Zwischenzellenbereich füllt. Die Zwischenzellen-Füllschicht wird ausgespart, bis sich eine Oberseite der Zwischenzellen-Füllschicht unter einer Oberseite des Paars Speicherzellenstrukturen befindet und der Zwischenzellenbereich teilweise geleert ist. Eine dielektrische Verbindungsschicht wird so hergestellt, dass sie die Speicherzellenstrukturen und die Zwischenzellen-Füllschicht bedeckt und außerdem einen geleerten Teil des Zwischenzellenbereichs ...

Elektronisches, bistabiles sperrschichtfreies Halbleiterschaltelement und Verfahren zu seiner Herstellung

Halbleiterelement

Stromsteuervorrichtung

METHOD OF FORMING GLASS LAYERS

... 1342544 Depositing a chalcogenide glass STANDARD TELEPHONES & CABLES Ltd 28 Oct 1971 50082/71 Heading C1M A method of depositing on a substrate, such as silicon, a layer of a glass which contains selenium, tellurium and/or sulphur on a substrate in which a plasma is established by means of an applied electric field adjacent said surface in an atmosphere containing a mixture of compounds each including an element of the layer. Preferably the compounds are the hydroxides of each element. The atmosphere may additionally include a doping element and is maintained at a pressure below atmospheric. The electric field is applied by an alternating voltage preferably of radio frequency. Deposition may be controlled by a magnetic field to give even cover or concentrated in particular areas. Specific glasses described are Te 48 As 30 Ge 10 Si 12 ; Te 33 As 27 Ge 20 Si 20 and As 5 Se 6 Te 3 .

THRESHOLS SWITCH

... 1411604 Glass compositions for glass-metal seals STANDARD TELEPHONES & CABLES Ltd 6 Dec 1973 [14 Dec 1972] 57671/72 Heading C1M [Also in Division H1] The subject-matter of this Specification is substantially the same as that of Specification 1,361,487, but titanium dioxide is used instead of cupric oxide as a constituent of the glass.

Cross-point nonvolatile memory devices using binary metal oxide layer as data storage material layer, and methods of fabricating the same

A cross-point non-volatile memory device using a binary metal oxide layer as a data storage material layer includes spaced apart doped lines 106 disposed in a substrate. Spaced apart upper electrodes 116 cross over the doped lines such that cross points C are formed where the upper electrodes overlap the doped lines. Lower electrodes 110' are disposed at the cross points between the doped lines and the upper electrodes. A binary metal oxide layer 114 is provided between the upper electrodes and the lower electrodes as a data storage material layer. The binary metal oxide layer may comprise a transition metal oxide or aluminium oxide. Doped regions 108' are provided between the lower electrodes and the doped lines and have an opposite conductivity type to the doped lines in order to form diodes together with the doped lines to reduce crosstalk between adjacent memory cells caused by leakage currents.

Power distribution unit

Semi-conductor element

... 1,108,274. Semi-conductor devices. DANFOSS A/S. 3 March. 1966 [3 March, 1965|. No. 9387/66..Heading H1K. ' A semi-conductor device having high and low resistance states comprises a semi-conductor body without barrier layers and having a negative temperature coefficient of resistance in the high resistivity state in, which the leakage current is uniformly distributed, and such that a localized drop in resistance is concentrated in a narrow channel whose cross-sectional area increases with increased current. As shown. Fig. 5, a semi-conductor element 9, having a resistance-temperature characteristic of the shape illustrated in Fig. 4 (not shown), is mounted on an electrode 8 and provided with a strip-shaped electrode 10 one end 11 of which extends below the surface of element 9 to define an initiating point. At high currents the conduction channel spreads along a curved path beneath electrode 10. . The semi-conductor material may be an alloy e.g. As-S-Se, As-P-Se, Zn-As-Si, Zn-As-Ge, Cd-As-Si ...

Programmable current for correlated electron switch

REPRODUCIBLE RESISTANCE VARIABLE ISOLATION MEMORY ARRANGEMENTS AND MANUFACTURING PROCESS FOR IT

THIN FILM MEMORY MODULE WITH VARIABLE RESISTANCE

Speicher-Sensoranordnung mit einem Sensorelement und einem Speicher

The invention concerns a storage device-sensor arrangement (1) with a sensor element (2) and a storage device, which is characterized by at least one series circuit of a sensor element (2) which varies its resistance under the influence of physical and/or chemical values to be detected, with a multistable electric cell (3) which varies its resistance value when defined voltages are applied and retains it even if these defined voltages are absent.

CURRENTDEPENDENT RESISTIVES ELEMENT

Procedure for the production of a voltage-controlled semiconductor switch

BILATERAL CONTROLLABLE ONE SEMICONDUCTOR SWITCH

Layer Halbmentallwiderstand with negative voltage characteristic

Porous SIO

IMPROVED THIN-FILM STRUCTURE FOR CHALCOGENIDE ELECTRICAL SWITCHING DEVICES AND PROCESS THEREFOR

Disclosed herein is a novel thin-film structure for solid state thin-film electrical switching device fabricated of chalcoge- nide material that overcomes a number of design weaknesses existing in the prior art. The novel structure of the instant invention employs a thin layer of insulating material (16) beneath the body of chalcogenide material (3) so as to carefully define the fila- ment location. Since the filament location has been fixed, switching, due to edge conduction pathways has been substantially eli- minated. At the same time, the use of a thin insulating layer precludes step coverage faults of the prior art. The requirement for the thin layer of insulator material to withstand the switching voltage is addressed through the use of a second thicker layer of in- sulator material (2) which is deposited only after the chalcogenide material (3) has been formed. This improved structure demon- strates the advantages of higher fabrication yields and more repeatable electrical switching ...

THRESHOLD SWITCHING DEVICE

THRESHOLD SWITCHING DEVICE This invention relates to a method of forming a threshold switching device which exhibits negative differential resistance and to the devices formed thereby. The method comprises depositing a silicon dioxide film derived from hydrogen silsesqulioxane resin between at least two electrodes and then applying a voltage above a threshold voltage across the electrodes.

Kontaktanordnung für Festkörperschalter

Speicheranordnung

Elektrische Schaltung mit einem elektrisch isolierenden Träger und Verfahren zu deren Herstellung

Elektronisches Festkörperschaltelement und Verfahren zu seiner Herstellung

Elektronisches, bistabiles Halbleiterschaltelement

Symmetrisches umschaltbares Halbleiterbauelement

Elektronisches, bistabiles Halbleiterschaltelement und Verfahren zu seiner Herstellung

Halbleiter-Schaltungselement

Stromsteuervorrichtung

Sperrschichtfreies Halbleiterbauelement für Schaltzwecke

Three-demensional semiconductor memory devices having double-intersection array and methods of fabricating the same

Memory cell with an asymmetrical area

Power distribution unit (PDU)

Non-volatile memory and method for manufacturing same

Access devices to correlated electron switch

Electronic device and manufacturing method thereof

The resistance change of the resistance change of a device memory and method of forming

Nonvolatile semiconductor storage device

3D RESISTIVE MEMORY

USE OF LACUNAR SPINELS HAS TETRAHEDRAL CLUSTERS Of METAL TRANSITION FROM TYPE AM4X8 IN a REWRITEABLE NONVOLATILE MEMORY FROM ELECTRONIC DATA, AND CORRESPONDING MATERIAL.

SWITCHING DEVICE INCLUDING SILICON AND CARBON

Amorphous semiconductor devices unaffected by nuclear radiation - using active glass contg. tellurium, arsenic, germanium and sulphur

GENERATOR OF DELAYS USING A PROGRAMMABLE RESISTANCE CONTAINING MATERIAL HAS PHASE SHIFT

METHOD OF MAKING A COMPUTER RUNNING A RECURRENT NEURAL NETWORKS

METHOD FOR MANUFACTURING A FERROELECTRIC MEMORY AND METHOD FOR CO-FABRICATION OF A FERROELECTRIC MEMORY AND A RESISTIVE MEMORY

USE OF LACUNAR SPINELS HAS TETRAHEDRAL CLUSTERS Of METAL TRANSITION FROM TYPE AM4X8 IN a REWRITEABLE NONVOLATILE MEMORY FROM ELECTRONIC DATA, AND CORRESPONDING MATERIAL.

Utilisation de spinelles lacunaires à agrégats tétraédriques d'élément de transition du type AM4X8 dans une mémoire non volatile réinscriptible de données électroniques, et matériau correspondant. L'invention a pour objet l'utilisation d'un matériau appartenant à la famille des spinelles lacunaires à agrégats tétraédriques d'élément de transition AM4X8 comme matériau actif d'une mémoire non volatile de données électroniques, dans lequel : - A comprend l'un au moins des éléments suivants : Ga, Ge, Zn ; - M comprend l'un au moins des éléments suivants : V, Nb, Ta, Mo ; - X comprend l'un au moins des éléments suivants : S, Se.

CELL MEMORY

La présente invention a pour objet une cellule mémoire (10) non volatile comportant au moins deux zones mémoire (17) distinctes et formée chacune dans un matériau à changement de résistivité (14), la cellule mémoire (10) comportant au moins un moyen de chauffage (16) pour chaque zone mémoire (17), chaque moyen de chauffage (16) présentant au moins deux extrémités dont l'une est connectée à une ligne d'alimentation (V1, V2,.., VN) et dont l'autre est mise en contact avec le matériau à changement de résistivité (14), caractérisée en ce que le matériau à changement de résistivité est arrangé en un bloc unique (34) commun à chacune des zones mémoire (17) de la cellule mémoire (10) de sorte à créer localement chacune des zones mémoires (17) distinctes.

METAL-INSULATOR PHASE TRANSITION FLIP-FLOP

... 금속-절연체 상전이(MIT) 플립-플롭은 MIT 플립-플롭의 논리 상태를 표현하기 위해 쌍안정 작동 상태의 쌍 중의 선택된 작동 상태를 채용한다. MIT 플립-플롭은 쌍안정 작동 상태의 쌍을 제공하기 위해 전류-제어된 음의 미분 저항(CC-NDR)을 갖는 MIT 디바이스를 포함한다. 쌍안정 작동 상태의 쌍의 쌍안정 작동 상태는 프로그래밍 전압에 의해 선택될 수 있다. 쌍안정 작동 상태가 선택된 후, 쌍안정 작동 상태는 MIT 디바이스에 인가된 바이어스 전압에 의해 유지될 수 있다.

유-무기 하이브리드 페로브스카이트를 저항변화층으로 구비하는 저항변화 메모리 소자 및 그의 제조방법

... 저항 변화 메모리 소자 및 그의 제조방법을 제공한다. 상기 저항 변화 메모리 소자는 제1 전극과 제2 전극을 구비한다. 상기 제1 전극과 상기 제2 전극 사이에 위치하는 페로브스카이트 결정구조를 갖는 유기 금속 할라이드를 구비하는 저항 변화층이 배치된다.

상변화 메모리 디바이스들에서의 재료들 및 컴포넌트들

... 상변화 재료와, 그것과의 옴 접촉을 형성하는 전극을 가지는 상변화 메모리 셀들, 구조체들, 및 디바이스들이 개시되고 설명된다. 이러한 전극들은 10에서 100 mOhmㆍcm까지의 비저항을 가질 수 있다.

NON-VOLATILE MEMORY DEVICE INCLUDING A VARIABLE RESISTANCE MATERIAL, CAPABLE OF IMPROVING A STRUCTURE OF AN ELECTRODE BY USING STABLE BIPOLAR SWITCHING CHARACTERISTICS

PURPOSE: A non-volatile memory device including a variable resistance material is provided to obtain stable bipolar switching characteristics by performing a simple manufacturing process at low temperature. CONSTITUTION: An intermediate layer(22) is formed on a lower electrode(21). The intermediate layer is formed with one of HfO, ZnO, InZnO, and ITO. A variable resistance material layer(23) is formed in the intermediate layer and includes an Ni oxide. A top electrode(24) is formed on the variable resistance material layer. The lower electrode is formed with Pt, Ru, Ir, Ni, Co, Cr, W, and Cu or an alloy of Pt, Ru, Ir, Ni, Co, Cr, W, and Cu. The top electrode is formed with Pt, Ru, Ir, Ni, Co, Cr, W, and Cu or an alloy of Pt, Ru, Ir, Ni, Co, Cr, W, and Cu. The intermediate layer has a thickness of 1 to 50nm. The variable resistance material layer has a thickness of 1 to 100nm. © KIPO 2008 ...

NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

NONVOLATILE MEMORY ELEMENT AND METHOD OF MANUFACTURING THE SAME

Resistive memory device and method of fabricating the same

VOLATILE NEGATIVE DIFFERENTIAL RESISTANCE DEVICE USING METAL NANO PARTICLES EMPLOYING ORGANIC LAYER MADE OF ORGANIC MATERIAL

PURPOSE: A volatile negative differential resistance device using metal nano particles is provided to simplify the manufacturing process and reduce a manufacture cost by employing an organic layer made of an organic material having the metal nano particles. CONSTITUTION: A negative differential resistance device(100) has an organic layer(20) that is sandwiched between an upper electrode(10) and a lower electrode(30). The organic layer includes metal nano particles(25) having a constant size below a 10 nano-meter diameters and distributed uniformly therein. The chemical formula of the nano particle is CH3(CH2)_nSH(n is a integer between 3 and 19). © KIPO 2007 ...

MEMORY CELL FORMED USING A RECESS AND METHODS FOR FORMING THE SAME

스위치 소자 및 기억 장치

... 기술의 일 실시 형태의 스위치 소자는, 제1 전극과, 제1 전극에 대향 배치된 제2 전극과, 제1 전극과 제2 전극의 사이에 형성됨과 함께, 텔루륨(Te), 셀레늄(Se) 및 황(S)으로부터 선택되는 적어도 1종의 칼코겐 원소, 붕소(B), 탄소(C) 및 규소(Si)로부터 선택되는 적어도 1종의 제1 원소, 및, 산소(O) 및 질소(N) 중 적어도 한쪽을 포함하는 제2 원소 중, 적어도 칼코겐 원소 및 제1 원소를 포함하는 스위치층을 구비한다.

METHOD OF MAKING DAMASCENE DIODES USING SACRIFICIAL MATERIAL

SEMICONDUCTOR CELL AND A FORMING METHOD THEREOF, A CELL ARRAY, A SEMICONDUCTOR DEVICE, A SEMICONDUCTOR MODULE, A SEMICONDUCTOR SYSTEM, AN ELECTRONIC UNIT, AND AN ELECTRONIC SYSTEM

PURPOSE: A semiconductor cell and a forming method thereof, a cell array, a semiconductor device, a semiconductor module, a semiconductor system, an electronic unit, and an electronic system are provided to improve characteristics of the semiconductor device by controlling a coupling effect generated between a bit line and a contact plug. CONSTITUTION: A semiconductor substrate(100) includes a cell region. A storage electrode contact plug(116) is formed on the semiconductor substrate. A bit line(136) is formed between storage electrode contact plugs. An air gap(128) is connected to a bottom sidewall of the bit line. The air gap is extended in a perpendicular direction to a direction that the bit line is extended. COPYRIGHT KIPO 2013 ...

TRANSPARENT MEMORY FOR TRANSPARENT ELECTRONICS, CAPABLE OF PREVENTING DAMAGE DUE TO AN EXTERNAL FORCE BY USING A FLEXIBLE SUBSTRATE

PURPOSE: A transparent memory for transparent electronics is provided to increase a memory capacity while reducing the size of a memory by forming a resistance change material layer in multiple layers. CONSTITUTION: A lower transparent electrode layer(120) is successively formed on a transparent substrate. A data storage region(130) is formed by at least one transparent resistance change material layer. The transparent resistance change material layer has switching characteristics due to resistance change according to a voltage supplied to a lower transparent electrode layer and an upper transparent electrode layer. The transparent resistance change material layer has an optical band-gap of 3V and visible light transmission rate of 80%. COPYRIGHT KIPO 2010 ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device of the present invention comprises: a first word line and a second word line extending in a first direction in parallel with each other; a bit line extending between the first and second word lines in a second direction intersecting with the first direction; a first lower electrode formed on one side of the first word line; a first ovonic threshold switch (OTS) formed on the first lower electrode; a first intermediate electrode formed on the first OTS; a first phase change memory (PCM) formed on the first intermediate electrode; a first upper electrode formed between the first PCM and the other side of the bit line and having a width in the second direction, smaller than the width of the first intermediate electrode in the second direction; a second lower electrode formed on one side of the bit line; a second OTS formed on the second lower electrode; a second intermediate electrode formed ...

NON VOLATILE MEMORY CELL AND SEMICONDUCTOR MEMORY DEVICE

An electric element comprises: a first electrode (1); a second electrode (3); and a layer (2) connected between the first electrode and the second electrode and having a diode characteristic and a variable resistance characteristic. The layer (2) conducts a substantial electric current in a forward direction extending from one of the first electrode (1) and the second electrode (3) to the other electrode as compared to a reverse direction opposite of the forward direction. The resistance value of the layer (2) for the forward direction increases or decreases according to a predetermined pulse voltage applied between the first electrode (1) and the second electrode (3). © KIPO & WIPO 2008 ...

METHOD FOR FABRICATING HIGH DENSITY PILLAR STRUCTURES BY DOUBLE PATTERNING USING POSITIVE PHOTORESIST

PRECURSOR SOLUTION USED FOR MOCVD PROCESS AND METHOD FOR CONTROLLING THE COMPOSITION OF MOCVD DEPOSITED PCMO

PURPOSE: A precursor solution and a method for controlling the composition of MOCVD deposited PCMO are provided, thereby controlling the composition of the PCMO thin film materials, the ratio of the metals with respect to each other, fine tuning the deposition ratios, and determining the affects of changes in vaporizer temperature or substrate temperature on the deposition rates of different precursors. CONSTITUTION: The single solution MOCVD precursor for depositing PCMO comprises a Pr(tmhd)3 precursor, a Mn(tmhd)3 precursor and a calcium precursor dissolved in an organic solvent, wherein the calcium precursor is Ca(tmhd)2 or Ca(hfac)2; the organic solvent comprises buytlether and tetraglyme in a volumetric ratio of between 2:1 and 5:1, preferably 3:1; the organic solvent comprises a solvent selected from the group consisting of octane, THF, butyl acetate, and iso-propanol; and the Pr(tmhd)3 precursor, the Mn(tmhd)3 precursor and the calcium precursor provide between 0.05 and 0.5 M/L of ...

NON-VOLATILE MEMORY DEVICE AND A MANUFACTURING METHOD THEREOF FOR AT THE SAME TIME MANUFACTURING MEMORY CELLS OF A LAMINATING STRUCTURE

PURPOSE: A non-volatile memory device and a manufacturing method thereof comprise a first conductive layer within a first electrode and semiconductor layer. The electric resistance increase caused by the length increase of the first electrode can be controlled. CONSTITUTION: A semiconductor layer(114) having the first conductivity type on substrate is formed. One or more first electrodes(110) comprises the first conductive layer(112) having the resistivity lower than the semiconductor layer. The second semiconductor layer(140) has the opposite of the first conductivity type second conductive type. One or more second electrodes(150) includes the second semiconductor layer. And it is arranged in order to be crossed toward one or more first electrode. A data storing layer(130) is in the crossing potion of the second semiconductor layer and semiconductor layer an interpose. COPYRIGHT KIPO 2010 ...

DIODE STRUCTURE AND RESISTIVE RANDOM ACCESS MEMORY DEVICE COMPRISING THE SAME, CAPABLE OF MAXIMIZING THE EFFECTIVE AREA OF A DIODE STRUCTURE

PURPOSE: A diode structure and resistive random access memory device comprising the same are provided to maximize an effective area by forming a diode structure in a three dimensional structure. CONSTITUTION: An insulating layer(12) is formed on a bottom electrode(11). An opening of a hole type is formed on the insulating layer to exposes the bottom electrode. The diode structure of a three dimensional structure is formed on the exposed bottom electrode. The diode structure is formed in the side and the lower part of the opening. The diode structure comprises a first layer having a receiving part and also includes a second layer which is formed inside the receiving part of the fist layer. COPYRIGHT KIPO 2011 ...

METHODS, STRUCTURES AND DEVICES FOR INCREASING MEMORY DENSITY

Memory device, method of performing read or write operation and memory system including the same

Fully self-aligned pore-type memory cell having diode access device

Memory devices are described along with methods for manufacturing. A memory device as describe herein includes a plurality of memory cell. Each memory cell in the plurality of memory cells comprises a diode comprising doped semiconductor material and a dielectric spacer on the diode and defining an opening, the dielectric spacer having sides self-aligned with sides of the diode. Each memory cell further comprises a memory element on the dielectric spacer and including a portion within the opening contacting a top surface of the diode.

Carbon-based resistivity-switching materials and methods of forming the same

Memory devices including a carbon-based resistivity-switchable material, and methods of forming such memory devices are provided, the methods including introducing a processing gas into a processing chamber, wherein the processing gas includes a hydrocarbon compound and a carrier gas, and generating a plasma of the processing gas to deposit a layer of the carbon-based switchable material on a substrate within the processing chamber. Numerous additional aspects are provided.

Thin film memory device having a variable resistance

A thin film storage device includes a first electrode (3), a first variable resistance thin film (2), and a second electrode (1). The first electrode (3) is formed over a surface of a substrate (4). The first variable resistance thin film (2) is formed over a surface of the first electrode (3). The second electrode (1) is formed over a surface of the first variable resistance thin film (2). The first variable resistance thin film (2) comprises a material whose resistance in a bulk state changes in accordance with at least one of a lattice strain and a change of charge-order.

Electric element, memory device, and semiconductor integrated circuit

A first electrode layer includes first electrode wires (W1, W2) extending parallel. A state change layer is formed on the first electrode layer and includes state change bodies (60-11, 60-12, 60-21, 60-22) each exhibiting a diode characteristic and a variable resistance characteristic. A second electrode layer is formed on the state change layer and includes second electrode wires (B1, B2) extending parallel. The first electrode wires cross the second electrode wires (not connected) when viewed from above, with the state change layer interposed therebetween. The state change body (60-11) is formed between the first and second electrode wire at the position where the first electrode wire (W1) crosses the second electrode wire (B1) (not connected).

Method for manufacturing a narrow structure on an integrated circuit

A method of manufacturing for providing a narrow line, such as a phase change bridge, on a substrate having a top surface, includes first forming a layer of first material on the substrate. Then a layer of a pattern material is applied on the layer of first material, and a pattern is defined. The pattern includes a ledge having a sidewall extending substantially to the layer of first material. A sidewall etch mask is formed on the ledge, and used to define a line of the first material on the substrate having a width substantially determined by the width of the sidewall etch mask.

Phase change access device for memories

A memory may have access devices formed using a chalcogenide material. The access device does not induce a snapback voltage sufficient to cause read disturbs in the associated memory element being accessed. In the case of phase change memory elements, the snapback voltage may be less than the threshold voltage of the phase change memory element.

Memory devices and methods of fabricating the same

Semiconductor structure and manufacturing method thereof

MEMORY CELLS HAVING RESISTORS AND FORMATION OF THE SAME

Resistive memory with a thermally insulating region

Miim diodes having stacked structure

RESISTANCE CHANGE ELEMENT AND RESISTANCE CHANGE TYPE MEMORY USING THE SAME

There are provided a resistance change element exhibiting an excellent thermal processing stability under an atmosphere containing hydrogen, and a resistance change type memory that is excellent in resistance law and in productivity. The resistance change element, which has two or more different electrical resistance value states, is responsive to an application of a predetermined voltage or current to change from one state, which is selected from the two or more states, to another. The resistance change element includes a pair of electrodes and an oxide semiconductor layer that is sandwiched by the pair of electrodes and has a Perovskite structure and an n-type conductivity. The resistance change type memory has the resistance change element.

DUAL INSULATING LAYER DIODE WITH ASYMMETRIC INTERFACE STATE AND METHOD OF FABRICATION

An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. The diode is a metal-insulator diode having a first metal layer, a first insulating layer, a second insulating layer and a second metal layer. At least one asymmetric interface state is provided at the intersection of at least two of the layers to increase the ratio of the diode's on-current to its reverse bias leakage current. In various examples, the asymmetric interface state is formed by a positive or negative sheet charge that alters the barrier height and/or electric field at one or more portions of the diode. Two-terminal devices such as passive element memory cells can utilize the diode as a steering element in series with a state change element. The devices can be formed using pillar structures at the intersections of upper and lower conductors.

REWRITEABLE MEMORY CELL COMPRISING A TRANSISTOR AND RESISTANCE-SWITCHING MATERIAL IN SERIES

A nonvolatile memory cell is provided, the cell comprising a transistor in series with resistance- switching material, which can be switched between at least two stable resistance states, for example a high-resistance state and a low-resistance state. In preferred embodiments the transistor is a TFT, having a channel region not formed in a monocrystalline wafer substrate. In preferred embodiments the transistor may have' either a vertically oriented ch'annel or a laterally oriented channel. Either embodiment can be formed in a monolithic three dimensional memory array in which multiple memory levels can be formed above a single substrate, forming a highly dense nonvolatile memory array.

METHOD FOR MANUFACTORING A CARBON-BASED MEMORY ELEMENT AND MEMORY ELEMENT

A method for manufacturing a resistive memory element (1) comprises: providing a storage layer (2) comprising a resistance changeable material; said resistance changeable material comprising carbon; providing contact layers (3, 4) for contacting the storage layer (2), wherein the storage layer (2) is disposed between a bottom contact layer (3) and a top contact layer (4); and doping the resistance changeable material with a dopant material. A resistive memory element (1) includes a bottom contact layer (3), a top contact layer (4) and a storage layer (2) disposed between the bottom contact layer (3) and the top contact layer (4), wherein the storage layer (2) comprises a resistance changeable material that is doped with a dopant material.

3-DIMENSIONAL NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING SAME

Embodiments according to the present invention relate to a 3-dimensional non-volatile memory device and a method of manufacturing same. The 3-dimensional non-volatile memory device according to an embodiment includes: a plurality of conductive lines spaced apart from each other in parallel; a plurality of flat plates crossing the plurality of conductive lines, and being spaced apart from each other in parallel; and non-volatile information storage layer patterns respectively disposed between intersecting areas of the plurality of conductive lines and the plurality of conductive flat plates.

NANOPARTICLE ASSEMBLY-BASED SWITCHING DEVICE

The present invention relates to a switching device fabricated by using nanoparticles and a preparation method thereof. The present invention ensures the mass production of switching devices (e.g., memristor) by use of nanoparticles that exhibits reversible switching behavior at current of less than mA and at room temperature (25°C) 〧 250°C in a more convenient and economical manner. Predictions of the high potential of memristors based on nanoparticle assemblies are supported by the tremendous versatility to tune the electrical behavior of nanoparticles by controlling their nanoscale characteristics such as size, composition, dimension, surface area, and chemical potential.

STACKABLE NON-VOLATILE RESISTIVE SWITCHING MEMORY DEVICE AND METHOD

A memory device includes a first plurality of memory cells arranged in a first crossbar array, a first thickness of dielectric material overlying the first plurality of memory cells, and a second plurality of memory cells arranged in a second crossbar array overlying the first thickness of dielectric material. The memory device further includes a second thickness of dielectric material overlying the second plurality of memory cells. In a specific embodiment, the memory device further includes a Nth thickness of dielectric material overlying an Nth plurality of memory cells, where N is an integer ranging from 3 to 8. 1. A memory device , comprising:a first plurality of memory cells arranged in a first crossbar array;a first thickness of dielectric material overlying the first plurality of memory cells; anda second plurality of memory cells arranged in a second crossbar array overlying the first thickness of dielectric material.2. The memory device of further comprises a second thickness of dielectric material overlying the second plurality of memory cells.3. The memory device of further comprises a Nth thickness of dielectric material overlying the Nth plurality of memory cells claim 1 , where N is an integer ranging from 3 to 8. The present application incorporates by reference and claims priority to the following pending patent application: U.S. patent application Ser. No. 12/861,650, filed Aug. 23, 2010.The present invention is generally related to resistive switching devices. More particularly, embodiments according to the present invention provide a method and a structure for forming a stacked or vertically stacked resistive switching device. The present invention can be applied to non-volatile memory devices but it should be recognized that the present invention can have a much broader range of applicabilityThe success of semiconductor devices has been mainly driven by an intensive transistor down-scaling process. However, as field effect transistors (FET) ...

METHOD FOR FABRICATION OF A MAGNETIC RANDOM ACCESS MEMORY (MRAM) USING A HIGH SELECTIVITY HARD MASK

A self-aligned via of a MRAM cell that connects a memory element including a top electrode, a memory element stack having a plurality of layers, and a bottom electrode to a bit line running over array of the memory elements. The self-aligned via also serves as a hard mask for memory element etching. The hard mask material has high selectivity in the etching ambient to maintain enough remaining thickness. It is also selectively removed during dual damascene process to form a self-aligned via hole. In one embodiment, Aluminum oxide or Magnesium oxide is adapted as the hard mask. 1. A magnetic random access memory (MRAM) cell comprising: a magneto tunnel junction (MTJ) formed on top of a substrate;', 'a top electrode formed on top of the MTJ; and, 'a MRAM element including,'}a self-aligned via also serving as an etching hard mask;a metal line connected to said MRAM element with said self-aligned via serving as an etching hard mask.2. The MRAM cell of wherein said etching hard mask that is made of aluminum oxide.3. The MRAM cell of wherein said etching hard mask that is made of magnesium oxide.4. A magnetic random access memory (MRAM) cell comprising: a magneto tunnel junction (MTJ) formed on top of a substrate;', 'a top electrode formed on top of the MTJ; and, 'a MRAM element including,'}an electrically conductive remaining etching hard mask;a metal line connected to said MRAM element with said hard mask.5. The MRAM cell of wherein said electrically conductive etching hard mask is made of aluminum.6. The MRAM cell of wherein said etching hard mask is made of copper. This application claims priority to U.S. Provisional Application No. 61/441,228, filed on Feb. 9, 2011, by Kimihiro Satoh, et al., and entitled “A Method For Fabrication of a Magnetic Random Access Memory (MRAM) Using a High Selectivity Hard Mask.1. Field of the InventionThe present invention relates to the fabrication of a Magnetic Random Access Memory (MRAM) magneto tunnel junction (MTJ), and, more ...

RESISTIVE MEMORY AND METHODS OF PROCESSING RESISTIVE MEMORY

Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include conformally forming a cell material in an opening in an interlayer dielectric such that a seam is formed in the cell material, forming a conductive pathway by modifying the seam, and forming an electrode on the cell material and the seam. 1. A method of processing a memory cell , comprising:forming a seam in a cell material;wherein the seam is formed in the cell material by conformally forming the cell material.2. The method of claim 1 , wherein the method includes forming a conductive pathway in the seam.3. The method of claim 2 , wherein the method includes heating the conductive pathway after forming the conductive pathway in the seam.4. The method of claim 1 , wherein the method includes removing a portion of the cell material after forming the seam in the cell material.5. The method of claim 4 , wherein the method includes forming an electrode on the cell material and the seam after removing the portion of the cell material.6. A method of processing a memory cell claim 4 , comprising:conformally forming a cell material such that a seam is formed in the cell material;wherein the seam is an opening in the cell material.7. The method of claim 6 , wherein the method includes modifying the seam.8. The method of claim 7 , wherein modifying the seam includes forming a filament in the seam.9. The method of claim 8 , wherein the method includes forming the filament in the seam such that the filament completely fills the seam.10. A method of processing a memory cell claim 8 , comprising:conformally forming a cell material such that a seam is formed in the cell material;forming a conductive pathway in the seam; andremoving a portion of the conductive pathway.11. The method of claim 10 , wherein the method includes diffusing atoms from the conductive pathway into the cell material after forming the conductive pathway in the ...

NONVOLATILE MEMORY ELEMENT, METHOD OF MANUFACTURING NONVOLATILE MEMORY ELEMENT, METHOD OF INITIAL BREAKDOWN OF NONVOLATILE MEMORY ELEMENT, AND NONVOLATILE MEMORY DEVICE

A nonvolatile memory element includes a current steering element which bidirectionally rectifies current in response to applied voltage and a variable resistance element connected in series with the current steering element. The current steering element includes an MSM diode and an MSM diode which are connected in series and each of which bidirectionally rectifies current in response to applied voltage. The MSM diode and the MSM diode include a lower electrode, a first current steering layer, a first metal layer, a second current steering layer, and an upper electrode which are stacked in this order. The current steering element has a breakdown current which is larger than an initial breakdown current which flows in the variable resistance element at the time of initial breakdown. 1. A nonvolatile memory element comprising:a current steering element which bidirectionally rectifies current in response to applied voltage; anda variable resistance element which is connected in series with the current steering element and reversibly changes between a high resistance state and a low resistance state according to a polarity of applied voltage,wherein the current steering element includes a first bidirectional diode and a second bidirectional diode which are connected in series and each of which bidirectionally rectifies current in response to applied voltage,the first bidirectional diode and the second bidirectional diode include a first electrode, a first current steering layer, a first metal layer, a second current steering layer, and a second electrode which are stacked in this order, andthe current steering element has a breakdown current which is larger than an initial breakdown current which flows in the variable resistance element at a time of initial breakdown which changes the variable resistance element from an initial state to a state in which the variable resistance element can reversibly change between the high resistance state and the low resistance state, ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

According to one embodiment, a semiconductor device includes first to n-th semiconductor layers (n is a natural number equal to or more than 2) being stacked in order from a surface of an insulating layer in a first direction perpendicular to the surface of the insulating layer, the first to n-th semiconductor layers extending in a second direction parallel to the surface of the insulating layer, the first to n-th semiconductor layers being insulated from each other, a common electrode connected to the first to n-th semiconductor layers in a first end of the second direction thereof, and a layer select transistor which uses the first to n-th semiconductor layers as channels and which selects one of the first to n-th semiconductor layers. 1. A semiconductor device comprising:a semiconductor substrate;an insulating layer on the semiconductor substrate;first to n-th semiconductor layers (n is a natural number equal to or more than 2) being stacked in order from a surface of the insulating layer in a first direction perpendicular to the surface of the insulating layer, the first to n-th semiconductor layers extending in a second direction parallel to the surface of the insulating layer, the first to n-th semiconductor layers being insulated from each other;a common electrode connected to the first to n-th semiconductor layers in a first end of the second direction thereof; anda layer select transistor which uses the first to n-th semiconductor layers as channels and which selects one of the first to n-th semiconductor layers,wherein the layer select transistor comprisesfirst to m-th gate electrodes (m=n+k, k is an even number) which are arranged in order from the first end of the second direction of the first to n-th semiconductor layers toward a second end of the second direction of the first to n-th semiconductor layers, and which extend in the first direction along side surfaces of the first to n-th semiconductor layers exposing in a third direction perpendicular to ...

Selector Device for Memory Applications

The present disclosure is related to a selector device for memory applications. The selector device for selecting a memory element in a memory array comprises an MIT element and a decoupled heater, thermally linked to the MIT element. The MIT element comprises a MIT material component and a barrier component and is switchable from a high to a low resistance state by heating the MIT element above a transition temperature with the decoupled heater. The barrier component is provided to increase the resistance of the MIT element in the high resistance state.

NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

A nonvolatile memory device includes a substrate, a lower electrode formed above said substrate, a second variable resistance layer formed above said lower electrode and comprising a second transitional metal oxide, a first variable resistance layer formed above said second variable resistance layer and comprising a first transitional metal oxide having an oxygen content that is lower than an oxygen content of the second transitional metal oxide, and an upper electrode formed above said first variable resistance layer. A step is formed in an interface between said lower electrode and said second variable resistance layer. The second variable resistance layer is formed covering the step and has a bend above the step. 111-. (canceled)12. A nonvolatile memory device comprising:a substrate;a lower electrode formed above said substrate;a second variable resistance layer formed above said lower electrode and comprising a second transitional metal oxide;a first variable resistance layer formed above said second variable resistance layer and comprising a first transitional metal oxide having an oxygen content that is lower than an oxygen content of the second transitional metal oxide; andan upper electrode formed above said first variable resistance layer,wherein a step is formed in an interface between said lower electrode and said second variable resistance layer, andwherein said second variable resistance layer is formed covering the step and has a bend above the step.13. The nonvolatile memory device of claim 12 , wherein the bend of said second variable resistance layer is straight-shaped when said second variable resistance layer is seen from above.14. The nonvolatile memory device of claim 12 , wherein the bend of said second variable resistance layer is ring-shaped when said second variable resistance layer is seen from above.15. The nonvolatile memory device of claim 12 , wherein the step includes plural steps claim 12 , and there is a crossing point at which the ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device in accordance with an embodiment includes a plurality of first word lines, a plurality of bit lines, a resistance varying material, a plurality of second word lines and an insulating film. The bit lines intersect the first word lines. The resistance varying material is disposed at respective intersections of the first word lines and the bit lines. The second word lines intersect the bit lines. The insulating film is disposed at respective intersections of the second word lines and the bit lines. One of the first word lines and one of the second word lines are disposed so as to sandwich the bit lines. The second word lines, the bit lines, and the insulating film configure a field-effect transistor at respective intersections of the second word lines and the bit lines. The field-effect transistor and the resistance varying material configure one memory cell. 17-. (canceled)8. A semiconductor memory device , comprising:a semiconductor substrate;a plurality of first word lines extending in a stacking direction perpendicular to the semiconductor substrate, the first word lines being arranged having a certain pitch in a first direction parallel to a surface of the semiconductor substrate and being arranged having a certain pitch in a second direction parallel to the surface of the semiconductor substrate and orthogonal to the first direction;a plurality of bit lines extending in the first direction and arranged having a certain pitch in the second direction and the stacking direction, the bit lines being configured to intersect the first word lines such that a first surface of the bit lines faces the first word lines;a resistance varying material disposed at respective intersections of the first word lines and the bit lines;a plurality of second word lines extending in the stacking direction and arranged having a certain pitch in the first direction and the second direction, the second word lines being configured to intersect the bit lines so ...

VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF FORMING THE SAME

A variable resistance memory device comprises a bit line extended in a first direction, a vertical electrode extended vertically in a third direction and configured to be vertically aligned with the bit line in the third direction, a variable resistance layer disposed on a part of the vertical electrode, multiple word lines disposed on the variable resistance layer and stacked in the third direction, wherein each of multiple word lines are extended in a second direction, and a selection transistor including a first dopant injection region electrically connected to the vertical electrode, and a second dopant injection region electrically connected to the bit line. 1. A variable resistance memory device comprising:a bit line extended in a first direction;a vertical electrode extended vertically in a third direction and configured to be vertically aligned with the bit line;a variable resistance layer disposed on a part of the vertical electrode;multiple word lines disposed on the variable resistance layer and stacked in the third direction, wherein each of multiple word lines are extended in a second direction; anda selection transistor including a first dopant injection region electrically connected to the vertical electrode and a second dopant injection region electrically connected to the bit line.2. The variable resistance memory device of claim 1 , further comprising:an active pattern disposed over the bit line, wherein the first dopant injection region and the second dopant injection region are disposed in the active pattern; anda bit line node contact disposed on the bit line, being electrically connected with the second dopant injection region.3. The variable resistance memory device of claim 2 , wherein the vertical electrode includes a first sub-vertical electrode disposed on the first dopant injection region claim 2 , a first pad disposed on the first sub-vertical electrode and a second sub-vertical electrode disposed on the pad.4. The variable resistance ...

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME

Semiconductor devices, and methods of manufacturing the same, include a field region in a semiconductor substrate to define an active region. An interlayer insulating layer is on the semiconductor substrate. A semiconductor pattern is within a hole vertically extending through the interlayer insulating layer. The semiconductor pattern is in contact with the active region. A barrier region is between the semiconductor pattern and the interlayer insulating layer. The barrier region includes a first buffer dielectric material and a barrier dielectric material. The first buffer dielectric material is between the barrier dielectric material and the semiconductor pattern, and the barrier dielectric material is spaced apart from both the semiconductor pattern and the active region. 1. A semiconductor device , comprising:a field region in a semiconductor substrate to define an active region;an interlayer insulating layer on the semiconductor substrate;a semiconductor pattern within a hole vertically extending through the interlayer insulating layer, the semiconductor pattern being in contact with the active region; anda barrier region between the semiconductor pattern and the interlayer insulating layer, the barrier region including a first buffer dielectric material and a barrier dielectric material,wherein the first buffer dielectric material is between the barrier dielectric material and the semiconductor pattern, and the barrier dielectric material is spaced apart from both the semiconductor pattern and the active region.2. The device of claim 1 , wherein the semiconductor pattern includes a first semiconductor region and a second semiconductor region under the first semiconductor region claim 1 ,wherein the first semiconductor region includes impurities of a first conductivity type, and the second semiconductor region includes impurities of a second conductivity type different from the first conductivity type of the first semiconductor region.3. The device of claim 1 , ...

SEMICONDUCTOR DEVICE

A semiconductor device according to the present invention includes: an unit element which includes a first switch and a second switch, wherein each of the first switch and the second switch includes an electrical resistance changing layer whose state of electrical resistance is changed according to a polarity of an applied voltage, and each of the first switch and the second switch has two electrodes, and wherein one electrode of the first switch and one electrode of the second switch are connected each other to form a common node, and the other electrode of the first switch forms a first node, and the other electrode of the second switch forms a second node; a first wiring which is connected with the first node and forms a signal transmission line; and a second wiring which is connected with the second node and is connected with the first wiring through the unit element. 121.-. (canceled)22. A semiconductor device , comprising:an unit element which includes a first switch and a second switch, whereineach of the first switch and the second switch includes an electrical resistance changing layer whose state of electrical resistance is changed corresponding to a polarity of an applied voltage, and each of the first switch and the second switch has two electrodes, and whereinone electrode of the first switch and one electrode of the second switch are connected each other to form a common node, and the other electrode of the first switch forms a first node, and the other electrode of the second switch forms a second node;a first wiring which is connected with the first node, and forms a signal transmission line; anda second wiring which is connected with the second node, and is connected with the first wiring through the unit element.23. The semiconductor device according to claim 22 , whereinthe first wiring and the second wiring are skewed each other.24. The semiconductor device according to claim 22 , whereina plurality of wirings which include at least one of the ...

High Consistency Resistive Memory and Manufacturing Method Thereof

The present invention relates to the technical field of memories, and in particular to a highly-consistent resistive memory and method of fabricating the same. The resistive memory comprises: a lower electrode which is formed in a first dielectric layer by patterning; a second dielectric layer formed on the lower electrode and the first dielectric layer and provided with an opening for exposing the lower electrode to perform patterning; an edge wall formed in the opening of the second dielectric layer for covering a border area of the lower electrode and the first dielectric layer so that only the middle area of the lower electrode is partially or totally exposed; a storage medium layer formed by performing oxidization with the second dielectric layer and the edge wall as mask; and an upper electrode. The resistive memory exhibits good consistency and high reliability; moreover, unit size is mall, which is advantageous for improving storage characteristic. When an array of memories is formed by the resistive memories, a good consistency is obtained among multiple resistive memories. 1. A resistive memory , characterized by comprising:a lower electrode which is formed in a first dielectric layer by patterning;a second dielectric layer formed on the lower electrode and the first dielectric layer and provided with an opening for pattern-exposing the lower electrode;an edge wall formed in the opening of the second dielectric layer for covering a border area of the lower electrode and the first dielectric layer so that only the middle area of the lower electrode is partially or totally exposed;a storage dielectric layer formed by performing oxidization with the second dielectric layer and the edge wall as mask; andan upper electrode.2. The resistive memory according to claim 1 , characterized in that the resistive memory is integrated in a copper interconnect structure claim 1 , and the storage medium layer is a CuO storage medium layer claim 1 , wherein 1 Подробнее

Self-Isolated Conductive Bridge Memory Device

A conductive-bridge random access memory device is disclosed comprising a second metal layer configured to provide second metal cations; a layer of insulator adjacent to the second metal layer; the layer of insulator comprising a layer of first insulator and a layer of second insulator; the layer of second insulator being adjacent to the second metal layer; a first metal layer adjacent to the layer of first insulator, the first metal layer being opposite to the second metal layer; wherein the density of the layer of second insulator is higher than the density of the layer of first insulator. 1. A conductive-bridge random access memory device comprising:a second metal layer configured to provide second metal cations;a layer of insulator adjacent to the second metal layer, the layer of insulator comprising a layer of first insulator and a layer of second insulator, the layer of second insulator being adjacent to the second metal layer; anda first metal layer adjacent to the layer of first insulator, the first metal layer being opposite to the second metal layer, wherein a density of the layer of second insulator is higher than a density of the layer of first insulator.2. The conductive-bridge random access memory device according to claim 1 , wherein the layer of first insulator and the layer of second insulator consist of a same insulating material.3. The conductive-bridge random access memory device according to claim 1 , further comprising a buffer layer in between the second metal and the layer of second insulator.4. The conductive-bridge random access memory device according to claim 1 , wherein the layer densities are chosen such that filament growth speed is lower in the layer of second insulator than in the layer of first insulator.5. The conductive-bridge random access memory device according to claim 1 , wherein layer density of the layer of second insulator is 85% or more of bulk density of the layer of second insulator and layer density of the layer of ...

POST-FABRICATION SELF-ALIGNED INITIALIZATION OF INTEGRATED DEVICES

Defining an active region of a phase change memory (PCM) cell including depositing a first layer of material having a first chemical composition. A second layer of material having a second chemical composition is deposited on top of the first layer of material. An electrical current pulse is applied to locally heat a region of the first layer of material and the second layer of material to cause at least one of an inter-diffusion and a liquid mixing of the first layer of material and the second layer of material. This results in in the PCM cell containing a self-aligned region that includes a phase change material that is a mixture of the first chemical composition and the second chemical composition. 1. A method of defining an active region of a phase change memory (PCM) cell comprising:depositing a first layer of material having a first chemical composition;depositing a second layer of material having a second chemical composition on top of the first layer of material, andapplying an electrical current pulse to locally heat a region of the first layer of material and the second layer of material to cause at least one of an inter-diffusion and a liquid mixing of the first layer of material and the second layer of material, resulting in the PCM cell comprising a self-aligned region comprising a phase change material that is a mixture of the first chemical composition and the second chemical composition.2. The method of claim 1 , wherein the applying the electrical current pulse causes an electrical current to flow from a first electrode to a second electrode claim 1 , the electrical current passing through at least the first layer of material.3. The method of claim 1 , wherein the first layer of material is an amorphous threshold switching material having high electrical resistivity at low electric field strength and substantially reduced electrical resistivity at electric field strengths above a threshold.4. The method of claim 1 , wherein the first layer of ...

Resistive Memory Arrangement and a Method of Forming the Same

According to embodiments of the present invention, a resistive memory arrangement is provided. The resistive memory arrangement includes a nanowire, and a resistive memory cell including a resistive layer including a resistive changing material, wherein at least a section of the resistive layer is arranged covering at least a portion of a surface of the nanowire, and a conductive layer arranged on at least a part of the resistive layer. According to further embodiments of the present invention, a method of forming a resistive memory arrangement is also provided. 1. A resistive memory arrangement comprising:a nanowire; and a resistive layer comprising a resistive changing material, wherein at least a section of the resistive layer is arranged covering at least a portion of a surface of the nanowire; and', 'a conductive layer arranged on at least a part of the resistive layer., 'a resistive memory cell comprising2. The resistive memory arrangement as claimed in claim 1 , wherein the nanowire has a longitudinal axis claim 1 , and wherein the surface of the nanowire is arranged at least substantially parallel to a plane which intersects the longitudinal axis.3. The resistive memory arrangement as claimed in claim 1 , wherein the nanowire has a longitudinal axis claim 1 , and wherein at least a portion of the resistive layer is arranged around the longitudinal axis and at least substantially surrounding the nanowire.4. The resistive memory arrangement as claimed in claim 3 , wherein at least a portion of the conductive layer is arranged at least substantially surrounding the portion of the resistive layer.5. The resistive memory arrangement as claimed in claim 3 , wherein the portion of the resistive layer is arranged at least substantially surrounding a partial portion of the nanowire.6. The resistive memory arrangement as claimed in claim 1 , wherein the nanowire is doped.7. The resistive memory arrangement as claimed in claim 1 , wherein the nanowire comprises a ...

Memory Cells and Memory Cell Arrays

Some embodiments include memory cells. The memory cells may have a first electrode, and a trench-shaped programmable material structure over the first electrode. The trench-shape defines an opening. The programmable material may be configured to reversibly retain a conductive bridge. The memory cell may have an ion source material directly against the programmable material, and may have a second electrode within the opening defined by the trench-shaped programmable material. Some embodiments include arrays of memory cells. The arrays may have first electrically conductive lines, and trench-shaped programmable material structures over the first lines. The trench-shaped structures may define openings within them. Ion source material may be directly against the programmable material, and second electrically conductive lines may be over the ion source material and within the openings defined by the trench-shaped structures. 122-. (canceled)23. An array of memory cells , comprising:a first electrically conductive line extending along a first direction;a plurality of trench-shaped programmable material structures over the first electrically conductive line; the trench-shaped programmable material structures extending along a second direction which intersects the first direction; individual trench-shaped programmable material structures having openings defined therein;ion source material directly against the trench-shaped programmable material structures;second electrically conductive lines that extend into the openings; individual memory cells comprising regions of programmable material and ion source material between the first and second electrically conductive lines; andwherein the first and second electrically conductive lines, and the programmable material and ion source material between the first and second electrically conductive lines, together form a first level of the array; the level having a vertical arrangement from the first electrically conductive line to ...

VARIABLE RESISTIVE MEMORY DEVICE AND METHOD OF FABRICATING AND DRIVING THE SAME

Provided are a variable resistive memory device, and methods of fabricating and driving the same. The variable resistive memory device includes a plurality of memory cells arranged in a first direction and in a second direction different from the first direction, each of the plurality of memory cells comprising a variable resistor and a selection device serially connected to the variable resistor. A common wiring is electrically connected to first ends of the plurality of memory cells to apply a common reference voltage. Each wiring line of a plurality of wiring lines is electrically connected to second ends of the plurality of memory cells arranged n the plurality of rows oriented in the first direction. A plurality of selection lines are respectively connected to the selection devices of the plurality of memory cells to select any one of the plurality of memory cells via the plurality of wiring lines. 1. A variable resistive memory device comprising:a plurality of memory cells arranged in a first direction and in a second direction different from the first direction, each of the plurality of memory cells comprising a variable resistor and a selection device serially connected to the variable resistor;a common wiring electrically connected to first ends of the plurality of memory cells to apply a common reference voltage;a plurality of wiring lines, wherein each wiring line of the plurality of wiring lines is electrically connected to second ends of the plurality of memory cells arranged n the plurality of rows oriented in the first direction; anda plurality of selection lines respectively connected to the selection devices of the plurality of memory cells to select any one of the plurality of memory cells via the plurality of wiring lines.2. The variable resistive memory device of claim 1 , wherein the common wiring comprises a plurality of sub-lines electrically connected to one another.3. The variable resistive memory device of claim 1 , wherein the common ...

NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film. 1. A nonvolatile storage device , comprising:a first conductive layer formed on a semiconductor substrate, and extended in a first direction along a main surface of the semiconductor substrate;a select element formed on the first conductive layer, and electrically connected to the first conductive layer;a stacked film including (N+1) (N is an integer of N≧1) first insulator films and N second conductive layers alternately stacked on the select element;a first semiconductor layer and a memory material layer which are formed on a sidewall of the stacked film through a second insulator film, and electrically connected to the select element;a third conductive layer formed on the stacked film, and electrically connected to the first semiconductor layer; anda fourth conductive layer formed on the third conductive layer, electrically connected to the third conductive layer, and extended in a second direction orthogonal to the first direction.2. The nonvolatile storage device according to claim 1 , wherein a second semiconductor layer is formed between the first semiconductor layer and the second insulator film.3. The nonvolatile storage device according to claim 2 , wherein an uppermost surface of the second semiconductor layer is located in a region higher than a height of an uppermost surface of the second insulator film.4. The nonvolatile storage device according to claim 1 , wherein the third conductive layer comes in direct contact with the fourth conductive ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device according to an embodiment comprises a semiconductor layer, a variable resistance layer, a sidewall layer, and a buried layer. The semiconductor layer functions as a rectifying device. The variable resistance layer is provided above or below the semiconductor layer and reversibly changes its resistance. The sidewall layer is in contact with a sidewall of the semiconductor layer. The buried layer is embedded in the sidewall layer and is made of material different from that of the sidewall layer. These configurations may adjust the electrical characteristics of the rectifying device to any value. 1. A semiconductor memory device comprising:a semiconductor layer functioning as a rectifying device;a variable resistance layer provided above or below the semiconductor layer, and reversibly changing its resistance;a sidewall layer contacting a sidewall of the semiconductor layer; anda buried layer embedded in the sidewall layer, and being made of material different from that of the sidewall layer.2. The semiconductor memory device according to claim 1 , whereinthe buried layer is formed in a plurality in a dot pattern.3. The semiconductor memory device according to claim 1 , whereinthe buried layer is continuously formed to cover the semiconductor layer.4. The semiconductor memory device according to claim 1 , whereinthe buried layer is made of material having a charge generation property.51. The semiconductor memory device according to claim claim 1 , whereinthe sidewall layer comprises:a sidewall semiconductor layer contacting a sidewall of the semiconductor layer; anda sidewall insulating layer provided on a side surface of the sidewall semiconductor layer via the buried layer.6. The semiconductor memory device according to claim 5 , whereinthe sidewall semiconductor layer is made of silicon,the sidewall insulating layer is made of silicon nitride, andthe buried layer is made of silicon dioxide.7. The semiconductor memory device according ...

SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THE SAME

A diode layer includes a first impurity semiconductor layer that includes a first impurity acting as an acceptor and a second impurity semiconductor layer that includes a second impurity acting as a donor. One end of a first electrode layer contacts the diode layer. One end of a polysilicon layer contacts the other end of the first electrode layer. One end of a variable resistance layer contacts the other end of the polysilicon layer and is able to change a resistance value. A second electrode layer contacts the other end of the variable resistance layer. At least one of a first area and a second area contains a third impurity. The first area includes one end of the polysilicon layer, the second area includes the other end of the polysilicon layer. The third impurity differs from the first impurity and the second impurity. 1. A semiconductor storage device comprising:a diode layer that comprising a first impurity semiconductor layer and a second impurity semiconductor layer, the first impurity semiconductor layer containing a first impurity acting as an acceptor, the second impurity semiconductor layer containing a second impurity acting as a donor;a first electrode layer having one end contacting the diode layer;a polysilicon layer having one end contacting the other end of the first electrode layer;a variable resistance layer having one end contacting the other end of the polysilicon layer, and being able to change a resistance value; anda second electrode layer contacting the other end of the variable resistance layer,at least one of a first area and a second area containing a third impurity, the first area including one end of the polysilicon layer, the second area including the other end of the polysilicon layer,the third impurity being different from the first impurity and the second impurity.2. The semiconductor storage device according to claim 1 , wherein the third impurity causes the polysilicon layer to generate a crystal defect.3. The semiconductor ...

Resistive Memory Cells and Devices Having Asymmetrical Contacts

A memory cell includes a plug-type first electrode in a substrate, a magneto-resistive memory element disposed on the first electrode, and a second electrode disposed on the magneto-resistive memory element opposite the first electrode. The second electrode has an area of overlap with the magneto-resistive memory element that is greater than an area of overlap of the first electrode and the magneto-resistive memory element. The first surface may, for example, be substantially circular and have a diameter less than a minimum planar dimension (e.g., width) of the second surface. The magneto-resistive memory element may include a colossal magneto-resistive material, such as an insulating material with a perovskite phase and/or a transition metal oxide. 1. A memory device comprising:respective pluralities of parallel electrode lines disposed on a substrate at respective levels, wherein pluralities of electrode lines on adjacent levels extend transverse to one another;respective insulating layers between the pluralities of electrode lines of adjacent levels;respective pluralities of resistive memory elements disposed between adjacent ones of the insulating layers and the pluralities of electrode lines; andrespective pluralities of electrode plugs penetrating respective ones of the insulating layers at intersections of the electrode lines and coupling the electrode lines to the resistive memory elements.2. The memory device of claim 1 , wherein the electrode plugs have a diameter smaller than a width of the electrode lines.3. The memory device of claim 1 , wherein the resistive memory elements comprise a colossal magneto-resistive material.4. The memory device of claim 1 , wherein the resistive memory elements comprise an insulating material with a perovskite phase and/or a transition metal oxide.5. The memory device of claim 1 , wherein the resistive memory elements comprise layer patterns having substantially the same shape as the electrode lines. The present ...

NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

A nonvolatile memory device includes a first and second conductive unit and a memory layer. The memory layer is provided between the first conductive unit and the second conductive unit. The memory layer includes a material expressed by (M11−uM2u)xX+yα+zβ (M1 and M2 include at least one selected from the group consisting of Mg, Al, Sc, Y, Ga, Ti, Zr, Hf, Si, Ge, Sn, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Nb, Ta, Mo, W, Ru, Rh, Ca, Sr, Ba, and Ln (a lanthanoid element), X includes at least one of O and N, α includes at least one of Li, Na, K, Rb, Cs, and Fr, β includes at least one of F, Cl, Br, and I, 0.1≦x≦1.1, 0.0001≦y≦0.2, 0.9≦y/z≦1.1). 1. A nonvolatile memory device comprising:a first conductive unit;a second conductive unit; anda memory layer provided between the first conductive unit and the second conductive unit and capable of reversibly transitioning between a first state and a second state due to a current supplied via the first conductive unit and the second conductive unit, a resistance of the second state being higher than a resistance of the first state.{'sub': 1-u', 'u', 'x, 'the memory layer including a material expressed by (M1M2)X+yα+zβ (M1 and M2 include at least one selected from the group consisting of Mg, Al, Sc, Y, Ga, Ti, Zr, Hf, Si, Ge, Sn, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Nb, Ta, Mo, W, Ru, Rh, Ca, Sr, Ba, and Ln (a lanthanoid element), X includes at least one of O and N, α includes at least one of Li, Na, K, Rb, Cs, and Fr, β includes at least one of F, Cl, Br, and I, 0.1≦x≦1.1, 0.0001≦y≦0.2, 0.9≦y/z≦1.1).'}2. The device according to claim 1 , whereinthe memory layer includes at least one kind of cation element and at least one kind of anion element,the at least one kind of cation element is a transition element having a d orbital partially filled with an electron(s), andan average shortest distance between adjacent cations of the cation element is 0.32 nm or less.3. The device according to claim 1 , wherein the memory layer has a crystal structure ...

RESISTANCE CHANGE ELEMENT AND NONVOLATILE MEMORY DEVICE

A resistance change element includes a first conductive layer, a second conductive layer, and a memory layer. The memory layer is provided between the first conductive layer and the second conductive layer. The memory layer is capable of reversibly transitioning between a first state and a second state due to at least one of a voltage and a current supplied via the first conductive layer and the second conductive layer. A resistance of the second state is higher than a resistance of the first state. The memory layer includes niobium oxide. One of a (100) plane, a (010) plane, and a (110) plane of the memory layer is oriented in a stacking direction from the first conductive layer toward the second conductive layer. 1. A resistance change element comprising:a first conductive layer;a second conductive layer; anda memory layer provided between the first conductive layer and the second conductive layer and capable of reversibly transitioning between a first state and a second state due to at least one of a voltage and a current supplied via the first conductive layer and the second conductive layer, a resistance of the second state being higher than a resistance of the first state,the memory layer including niobium oxide, one of a (100) plane, a (010) plane, and a (110) plane being oriented in a stacking direction from the first conductive layer toward the second conductive layer.2. The resistance change element according to claim 1 , wherein a ratio of an intensity at a binding energy of 205 eV to an intensity at a binding energy of 207.5 eV of X-ray photoelectron spectroscopy of Nb included in the memory layer is 0.062 or less.3. The resistance change element according to claim 2 , wherein the binding energy is energy necessary to separate an atomic nucleus of Nb and an electron in a 3dorbital.4. The resistance change element according to claim 1 , wherein the memory layer includes NbO(1.8 Подробнее

SOLID ELECTROLYTE MEMORY ELEMENTS WITH ELECTRODE INTERFACE FOR IMPROVED PERFORMANCE

A memory element can include a first electrode; a second electrode; and a memory material programmable between different resistance states, the memory material disposed between the first electrode and the second electrode and comprising a solid electrolyte with at least one modifier element formed therein; wherein the first electrode is an anode electrode that includes an anode element that is ion conductible in the solid electrolyte, the anode element being different than the modifier element. 1. A memory element , comprising:a first electrode;a second electrode; anda memory material programmable between different resistance states, the memory material disposed between the first electrode and the second electrode and comprising a solid electrolyte with at least one modifier element formed therein; whereinthe first electrode is an anode electrode that includes an anode element that is ion conductible in the solid electrolyte, the anode element being different than the modifier element.2. The memory element of claim 1 , wherein:the modifier element comprises a transition metal.3. The memory element of claim 1 , wherein:the modifier element comprises titanium.4. The memory element of claim 1 , wherein:the modifier element comprises a post-transition metal.5. The memory element of claim 5 , wherein:the modifier element comprises aluminum.6. The memory element of claim 1 , wherein:the modifier element comprises a non-metal.7. The memory element of claim 1 , wherein:the solid electrolyte is selected from the group of: a chalcogen based solid electrolyte and a metal oxide.8. A method of fabricating a memory element claim 1 , comprising:forming a first electrode;forming a second electrode; andforming a memory layer between the first and second electrodes, the memory layer comprising a solid electrolyte layer programmable between different resistance states, at least a portion of the solid electrolyte layer having a modifier element formed therein; whereinthe first ...

METHODS INVOLVING MEMORY WITH HIGH DIELECTRIC CONSTANT ANTIFUSES ADAPTED FOR USE AT LOW VOLTAGE

Methods involve using a memory array having memory cells comprising a diode and an antifuse, in which the antifuse is made smaller and programmed at lower voltage by using an antifuse material having a higher dielectric constant and a higher acceleration factor than those of silicon dioxide, and in which the diode is made of a material having a lower band gap than that of silicon. Such memory arrays can be made to have long operating lifetimes by using the high acceleration factor and lower band gap materials. Antifuse materials having dielectric constants between 5 and 27, for example, hafnium silicon oxynitride or hafnium silicon oxide, are particularly effective. Diode materials with band gaps lower than that of silicon, such as germanium or a silicon-germanium alloy, are particularly effective. 1. A method of programming an array of memory cells each comprising an antifuse in series with a diode , each antifuse comprising an insulator having a dielectric constant above 5 , each diode comprising a thin film semiconductor material with a band gap smaller than that of silicon , the method comprising:programming a selected one of the memory cells by applying a first voltage in a direction opposite that of natural current flow through the diode of the selected memory cell, the first voltage being sufficient to short the antifuse.2. The method of claim 1 , further comprising:applying a second voltage to word lines contacting unselected ones of the memory cells; andapplying a third voltage to bit lines contacting the unselected ones of the memory cells, wherein the second and third voltages are substantially equal.3. The method of claim 2 , wherein the second and third voltages are approximately half the first voltage applied to the selected one of the memory cells.4. A method of programming a memory cell comprising an antifuse in series with a diode claim 2 , the antifuse comprising an insulator having a dielectric constant above 5 claim 2 , the diode comprising a ...

Memory Cells, Methods of Programming Memory Cells, and Methods of Forming Memory Cells

Some embodiments include methods of programming a memory cell. A plurality of charge carriers may be moved within the memory cell, with an average charge across the moving charge carriers having an absolute value greater than 2. Some embodiments include methods of forming and programming an ionic-transport-based memory cell. A stack is formed to have programmable material between first and second electrodes. The programmable material has mobile ions which are moved within the programmable material to transform the programmable material from one memory state to another. An average charge across the moving mobile ions has an absolute value greater than 2. Some embodiments include memory cells with programmable material between first and second electrodes. The programmable material includes an aluminum nitride first layer, and includes a second layer containing a mobile ion species in common with the first layer.

NON-VOLATILE MEMORY DEVICE HAVING MULTI-LEVEL CELLS AND METHOD OF FORMING THE SAME

A non-volatile memory device including multi-level cells is provided. The device includes first and second conductive patterns. Additionally, the device includes an electrode structure and a data storage pattern between the first and second conductive patterns. The data storage pattern may include a phase change material and a first vertical thickness of a first portion of the data storage pattern may be less than a second vertical thickness of a second portion of the data storage pattern. The electrode structure may include first and second electrodes and a vertical thickness of the first electrode may be greater than that of the second electrode. 115.-. (canceled)16. A non-volatile memory device , comprising:a first conductive pattern on a substrate;a switching device on the first conductive pattern;an electrode structure on the switching device;a data storage pattern self-aligned to the electrode structure; anda second conductive pattern on the data storage pattern,wherein the electrode structure comprises a first electrode, which is electrically connected to the switching device and in contact with the data storage pattern, and a second electrode, which is electrically connected to the switching device and in contact with the data storage pattern, and the second electrode has a resistivity greater than that of the first electrode.17. The non-volatile memory device according to claim 16 , wherein the second electrode comprises a material having a resistivity greater than a material comprising the first electrode.18. The non-volatile memory device according to claim 16 , further comprising:a first resistive pattern between the first electrode and the second electrode; anda second resistive pattern on a surface of the second electrode opposite the first resistive pattern.19. The non-volatile memory device according to claim 16 , wherein the first and second resistive patterns comprise a material having a resistivity greater than that of the first and second ...

Memory Arrays and Methods of Forming Memory Cells

Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction. The second electrically conductive lines interconnect the pillars along the second direction. 131-. (canceled)32. A method of forming a plurality of memory cells , comprising:forming a stack over a semiconductor base; the stack comprising a homogeneous n-type doped region, a p-type doped region, and an ovonic material over the p-type doped region;patterning the stack into rails, with the rails extending along a first direction, the rails being spaced from one another by first trenches;filling the first trenches with first electrically insulative material;patterning the rails into pillars, the patterning into the pillars comprising etching into but not entirely through the homogeneous n-type doped region to form a portion of the homogeneous n-type doped region into segments within the pillars, and to leave some of the homogeneous n-type doped region as first conductive lines interconnecting the pillars along the first direction; the patterning forming second trenches which extend along a second direction that intersects ...

SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME

A semiconductor device includes a plurality of first insulating layers and a plurality of second layers alternately and vertically stacked on a substrate. Each of the plurality of second layers includes a horizontal electrode horizontally separated by a second insulating layer. A contact plug penetrates the plurality of first insulating layers and the second insulating layer of the plurality of second layers. 1. A semiconductor device , comprising:a plurality of horizontal electrodes vertically stacked on a substrate;a plurality of first insulating layers, each of which is disposed between a corresponding pair of the plurality of horizontal electrodes;a plurality of second insulating layers, each of which is disposed between a corresponding pair of the plurality of first insulating layers and is disposed at the same vertical level as a corresponding one of the plurality of horizontal electrodes; anda contact structure penetrating the first and second insulating layers,wherein the contact structure is in contact with the first insulating layers and the second insulating layers.2. The device of claim 1 , wherein the plurality of second insulating layers is in contact with the corresponding pair of the plurality of first insulating layers.3. The device of claim 1 , wherein the plurality of second insulating layers has etch selectivity with respect to the plurality of first insulating layers.4. The device of claim 3 , wherein the plurality of first insulating layers comprises a silicon oxide layer claim 3 , and the plurality of second insulating layers comprises a silicon nitride layer claim 3 , a silicon oxynitride layer claim 3 , or a polysilicon layer.5. The device of claim 1 , wherein the contact structure comprises a metal layer claim 1 , a metal silicide layer claim 1 , or a conductive metal nitride layer.6. The device of claim 1 , further comprising a first conductive region disposed in the substrate claim 1 , wherein the contact structure is connected to the ...

VARIABLE RESISTANCE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

A variable resistance memory device includes a plurality of first conductive lines extended in a first direction, a plurality of second conductive lines arranged over or under the first conductive lines and extended in a second direction crossing the first direction, an insulating layer disposed between the first conductive lines and the second conductive lines and having a trench extended in the second direction and defined by a first side wall and a second sidewall facing each other and a bottom surface connecting the first sidewall and the second sidewall, and a variable resistance material layer formed on the first and second sidewalls and the bottom surface of the trench, wherein the first and second sidewalls of the trench overlap two adjacent second conductive lines, respectively. 1. A variable resistance memory device comprising:a plurality of first conductive lines extended in a first direction;a plurality of second conductive lines arranged over or under the first conductive lines and extended in a second direction crossing the first direction;an insulating layer disposed between the first conductive lines and the second conductive lines and having a trench extended in the second direction and defined by a first sidewall and a second side all facing each other and a bottom surface connecting the first side all and the second sidewall; anda variable resistance material layer formed on the first and second sidewalls and the bottom surface of the trench,wherein the first and second sidewalls of the trench overlap two adjacent second conductive lines, respectively.2. The variable resistance memory device of claim 1 , further comprising first conductive contacts disposed at the intersections between the first and second conductive lines and interposed between the variable resistance material layer and the first conductive lines.3. The variable resistance memory device of claim 1 , further comprising second conductive contacts disposed at the intersections ...

MANUFACTURING METHOD OF NON-VOLATILE STORAGE DEVICE, AND NON-VOLATILE STORAGE DEVICE

A manufacturing method includes forming a laminated body on a substrate. A mask layer is formed on the laminated body, and then a portion of the mask layer is removed to form an opening. Then, using the mask layer as a template, a first portion of the laminated body is removed to expose a portion of the substrate beneath the laminated body. The substrate is processed to alter the ratio between the size of mask opening and the removed first portion. A variable resistance layer is then deposited on exposed portions of the mask layer, the laminated body, and the substrate. Then the variable resistance layer is processed to remove at least a portion covering the substrate to permit contact with the underlying substrate. A second electrode layer is deposited to fill the removed portions of the laminated body. 1. A method of removing a coating layer from the base of an aperture extending inwardly of a film layer , comprising;forming a protective layer to protect the coating layer from exposure to directional etching elements; andetching at least a portion of the coating layer from the base of the aperture.2. The method of claim 1 , further including a masking layer disposed at the opening of the aperture claim 1 , and increasing the size of the masking layer to cause the masking layer to extend over claim 1 , but not block claim 1 , the opening of the aperture.3. The method of claim 1 , wherein increasing the size of the masking layer includes oxidizing the masking layer.4. The method of claim 1 , wherein the aperture includes side walls which are spaced from one another across the width of the aperture claim 1 , and adjacent apertures form therebetween a feature having sidewalls claim 1 , and forming a protective layer includes:providing a masking layer over the top of the feature; anddecreasing the width of the feature overlaid by the masking layer by removing material from the sidewalls of the feature prior to depositing the coating layer thereon.5. The method of claim ...

VARIABLE RESISTANCE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

A method for fabricating a variable resistance device includes: providing a first insulating layer having a first electrode; forming a first oxide layer including a variable resistance material over the first electrode and the first insulating layer; forming a sacrifice pattern over the first oxide layer; forming a second oxide layer by reacting the first oxide layer exposed by the sacrifice pattern with oxygen; removing the sacrifice pattern; and forming a second electrode over the second oxide layer and the first oxide layer so as to be coupled to the first oxide layer. 1. A method for fabricating a variable resistance memory device , comprising:providing a first insulating layer having a first electrode;forming a first oxide layer including a variable resistance material over the first electrode and the first insulating layer;forming a sacrifice pattern over the first oxide layer;forming a second oxide layer by reacting the first oxide layer exposed by the sacrifice pattern with oxygen;removing the sacrifice pattern; andforming a second electrode over the second oxide layer and the first oxide layer so as to be coupled to the first oxide layer.2. The method of claim 1 , wherein the forming of the second oxide layer is performed by an oxygen ion implantation process.3. The method of claim 1 , wherein the forming of the second oxide layer is performed by a plasma treatment under an oxygen atmosphere.4. The method of claim 1 , wherein the forming of the second oxide layer is performed by an annealing process under an oxygen atmosphere at an atmospheric pressure or more.5. The method of claim 1 , wherein the second oxide layer is a stoichiometric material claim 1 , andwherein an oxygen amount of the first oxide layer is smaller than that of the second oxide layer.6. The method of claim 1 , wherein the sacrifice pattern is formed of a photoresist or an insulating layer.7. The method of claim 1 , wherein the first electrode extends in a first direction claim 1 ,wherein ...

PHASE CHANGE MEMORY STRUCTURES AND METHODS

Methods, devices, and systems associated with phase change material memory are described herein. In one or more embodiments, a method of forming a phase change material memory cell includes forming a number of memory structure regions, wherein the memory structure regions include a bottom electrode material and a sacrificial material, forming a number of insulator regions between the number of memory structure regions, forming a number of openings between the number of insulator regions and forming a contoured surface on the number of insulator regions by removing the sacrificial material and a portion of the number of insulator regions, forming a number of dielectric spacers on the number of insulator regions, forming a contoured opening between the number of insulator regions and exposing the bottom electrode material by removing a portion of the number of dielectric spacers, and forming a phase change material in the opening between the number of insulator regions. 119.-. (canceled)20. A memory cell , comprising:a first electrode;a phase change material, wherein the phase change material contacts the first electrode in an opening between a number of insulator regions, and wherein the contact area between the first electrode and the phase change material is defined by a distance between the number of insulator regions; anda second electrode, wherein the top electrode is over the phase change material.21. The memory cell of claim 20 , wherein the phase change material contacts the first electrode in a self-aligned opening between the number of insulator regions.22. The memory device of claim 20 , wherein the spacers are on the number of insulator regions and further define the distance between the number of insulator regions.23. The memory device of claim 20 , wherein the number of insulator regions include spacers with contoured surfaces.24. The memory device of claim 20 , wherein an amount of phase change material in the memory device is defined by the distance ...

MEMORY CELL STRUCTURES

The present disclosure includes memory cell structures and method of forming the same. One such memory cell includes a first electrode having sidewalls angled less than 90 degrees in relation to a bottom surface of the first electrode, a second electrode, including an electrode contact portion of the second electrode, having sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode, wherein the second electrode is over the first electrode, and a storage element between the first electrode and the electrode contact portion of the second electrode. 1. A memory cell , comprising:a first electrode having sidewalls angled less than 90 degrees in relation to a bottom surface of the first electrode;a second electrode, including an electrode contact portion of the second electrode, having sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode, wherein the second electrode is over the first electrode; anda storage element between the first electrode and the electrode contact portion of the second electrode.2. The memory cell of claim 1 , wherein an electrode contact portion of the second electrode has sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode.3. The memory cell of claim 1 , wherein the first electrode has a trapezoidal cross-sectional area and sidewalls that are selected from the group consisting of straight claim 1 , concave claim 1 , or convex.4. The memory cell of claim 3 , wherein a top surface of the trapezoidal cross-sectional area of the first electrode is an electrode contact portion of the first electrode and is in contact with the storage element.5. The memory cell of claim 1 , wherein the first electrode has a triangular cross-sectional area and sidewalls that are selected from the group consisting of straight claim 1 , concave claim 1 , or convex.6. The memory cell of claim 1 , wherein the storage element includes a resistance variable ...

THREE-DIMENSIONAL NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING REPLACEMENT GATE

The disclosed technology relates generally to semiconductor devices and more particularly to three dimensional semiconductor memory devices, such as vertical three dimensional non-volatile memory devices. In one aspect, a vertical three-dimensional semiconductor memory device comprises a memory block comprising at least one memory hole formed through a stack of alternating layers of control gate layers and dielectric layers, wherein the memory hole is filled with a plurality of materials forming at least one memory cell. The semiconductor memory device additionally includes at least one trench formed through the stack so as to define part of a boundary of the memory block, wherein a sidewall of the trench comprises the control gate layers each having at least a portion that is in part laterally recessed relative to vertically adjacent dielectric layers, and wherein the trench is filled with an electrically conductive material. 1. A vertical three-dimensional semiconductor memory device , comprising:a memory block comprising at least one memory hole formed through a stack of alternating layers of control gate layers and dielectric layers, wherein the memory hole is filled with a plurality of materials forming at least one memory cell; andat least one trench formed through the stack so as to define part of a boundary of the memory block, wherein a sidewall of the trench comprises the control gate layers each having at least a portion that is in part laterally recessed relative to vertically adjacent dielectric layers, and wherein the trench is filled with an electrically conductive material.2. The memory device of claim 1 , wherein the control gate layers comprise semiconductor layers claim 1 , and wherein the electrically conductive material comprises a metallic material.3. The memory device of claim 1 , wherein the electrically conductive material comprises one or more of tungsten claim 1 , tungsten nitride claim 1 , tantalum claim 1 , tantalum nitride claim 1 , ...

SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME

A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode. 1. A semiconductor memory comprising:a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate;a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate;a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate; andwherein the layers are patterned in self-alignment with each other,intersections of the active areas and the first gate electrode form a plurality of memory cells, andthe plurality of memory cells in an intersecting plane share the first gate electrode.2. The memory according to claim 1 , wherein the first and second gate electrodes are formed by one layer.3. The memory according to claim 1 , wherein the first and second gate electrodes are connected to interconnections and driven independently of each other.4. The memory according to claim 1 , wherein the second gate electrode is formed parallel to the active areas claim 1 , and shared by the plurality of memory cells in a plane parallel to the active areas and perpendicular to the substrate.5. The memory according to claim 1 , wherein a ...

SELECT DEVICE FOR MEMORY CELL APPLICATIONS

The present disclosure includes select devices and methods of using select device for memory cell applications. An example select device includes a first electrode having a particular geometry, a semiconductor material formed on the first electrode and a second electrode having the particular geometry with formed on the semiconductor material, wherein the select device is configured to snap between resistive states in response to signals that are applied to the select device. 1. A memory cell , comprising: a first electrode having a particular geometry;', 'a first heater formed on the first electrode;', 'a semiconductor material formed on the first heater;', 'a second heater formed on the semiconductor material; and', 'a second electrode having the particular geometry formed on the second heater; and, 'a select device includinga storage element coupled in series to the select device.2. The memory cell of claim 1 , wherein a width of the semiconductor material is less than approximately 20 nanometers.3. The memory cell of claim 1 , wherein a width of the particular geometry is based on an operating voltage associated with the memory cell.4. The memory cell of claim 1 , wherein a composition of the semiconductor material is based on an operating voltage associated with the memory cell.5. The memory cell of claim 1 , wherein the select device is configured to support bi-directional current flow therethrough.6. The memory cell of claim 1 , wherein the particular geometry is a circular geometry.7. The memory cell of claim 1 , wherein the particular geometry is a quasi-square geometry.8. A memory cell claim 1 , comprising: a first heater;', 'a first electrode on the first heater;', 'a semiconductor material on the first electrode;', 'a second electrode on the semiconductor material; and', 'a second heater on the second electrode; and, 'a select device includinga storage element coupled in series to the select device.9. The memory cell of claim 8 , wherein a vacuum is ...

DIFFUSED RESISTIVE MEMORY CELL WITH BURIED ACTIVE ZONE

An apparatus for non-volatile memory, and more specifically a ReRAM device with a buried resistive memory cell. The memory cell includes a first contact disposed on a substrate, an active layer, a second contact, a first diffused zone disposed within the active layer, a second diffused zone disposed within the active layer, and an active switching zone disposed within the active layer in between the first diffused zone and the second diffused zone. In one embodiment, the active zone may be doped by diffusion or ion implantation and/or may be fabricated utilizing a self-aligned process. In another embodiment, the memory cell may combine a deep implant and shallow diffusion well to create the active zone. The vertically and laterally isolated buried resistive memory cell concentrates the electric field away from the edges of the device and eliminates the effects of interface impurities and contaminants. 1. A ReRAM device , comprising:a first contact;a second contact; and a first diffused zone adjacent the first contact, wherein the first diffused zone has a first composition;', 'a second diffused zone adjacent the second contact, wherein the second diffused zone has a second composition; and', 'an active zone disposed between the first diffused zone and the second diffused zone, wherein the active zone has a third composition different from the first composition of the first diffused zone., 'an active layer disposed between the first contact and the second contact, wherein the active layer comprises2. The device of claim 1 , wherein the active zone comprises a binary or complex metal oxide material selected from the group consisting of tantalum oxide claim 1 , hafnium oxide claim 1 , titanium oxide claim 1 , zirconium dioxide claim 1 , aluminum oxide claim 1 , titanium dioxide claim 1 , zinc oxide claim 1 , manganates claim 1 , cuprates claim 1 , or nickelates.3. The device of claim 1 , wherein the first diffused zone comprises a metal or metal alloy selected from the ...

RESISTIVE MEMORY CELL HAVING A COMPACT STRUCTURE

The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material. 1. A memory cell comprising:a selection transistor having a control gate and a first conduction terminal; a semiconductor substrate,', 'a first insulating layer covering the semiconductor substrate, and', 'a semiconductor active layer covering the insulating layer, the control gate being formed on the active layer and having a lateral flank,, 'a variable-resistance element connected to the first conduction terminal, the selection transistor and variable-resistance element being formed in a wafer that includesa second insulating layer covering the lateral flank of the control gate,a first trench formed through the active layer at a lateral flank of the active layer, along the lateral flank of the gate, and reaching the first insulating layer, wherein the variable-resistance element includes a layer of variable-resistance material positioned in the first trench along the lateral flank of the active layer, anda trench conductor formed in the first trench and against a lateral flank of the layer of variable-resistance material along the lateral flank of the active layer.2. The memory cell according to claim 1 , comprising adjacent trench isolations claim 1 , in which ...

Two-Terminal Switching Devices Comprising Coated Nanotube Elements

An improved switching material for forming a composite article over a substrate is disclosed. A first volume of nanotubes is combined with a second volume of nanoscopic particles in a predefined ration relative to the first volume of nanotubes to form a mixture. This mixture can then be deposited over a substrate as a relatively thick composite article via a spin coating process. The composite article may possess improved switching properties over that of a nanotube-only switching article. A method for forming substantially uniform nanoscopic particles of carbon, which contains one or more allotropes of carbon, is also disclosed. 1. A two-terminal switching device comprising:a first electrode;a second electrode; anda switching composite article disposed between and in constant electrical communication with each of said first electrode and said second electrode of said two terminal switching device, wherein said composite article is comprised of comprises a plurality of nanotube elements and a volume of nanoscopic particles;wherein said volume of nanoscopic particles is miscible with said plurality of nanotube elements and forms a continuous material around at least one of said nanotube elements.2. The two-terminal switching device of wherein substantially all of said nanotube elements are coated in a continuous material formed from said nanoscopic particles.3. The two-terminal switching device of wherein said continuous material coating increases the distance between said nanotube elements within said composite article.4. The two-terminal switching device of wherein said continuous material coating improves the switching functionality of said two-terminal switching device.5. The two-terminal switching device of wherein said volume of nanoscopic particles includes silicon oxide particles.6. The two-terminal switching device of wherein said volume of nanoscopic particles includes silicon nitride particles.7. The two-terminal switching device of wherein said nanotube ...

INTERCONNECTION FOR MEMORY ELECTRODES

Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level. 1. (canceled)2. An apparatus , comprising:a first access line and a second access line extending in a same direction, wherein at least a portion of the first access line extends beyond a portion of the second access line, and wherein the first access line comprises a first jog segment and the second access line comprises a second jog segment; anda connector coupled with the first jog segment, or the second jog segment, or both.3. The apparatus of claim 2 , further comprising:a socket region comprising a first socket coupled with the first access line and a second socket coupled with the second access line, wherein the first access line extends beyond a boundary of the socket region, and wherein the second access line is located entirely within the boundary of the socket region.4. The apparatus of claim 2 , wherein a distance between the first jog segment and the second jog segment is greater than a distance between another portion of the first access line and another portion of the second access line.5. The apparatus of claim 2 , further comprising:a third access line extending in a different direction than the first access line and the second access line, wherein at least a portion of the third access line intersects at least a portion of the first access line, at least a portion of the second access line, or both.6. The apparatus of claim 2 , wherein the first access line and the second access line are formed at a first vertical level of a stack.7. The apparatus of claim 6 , further comprising:a second vertical level of the stack comprising a fourth access line and a fifth access line extending in a second direction.8. ...

RESISTANCE VARIABLE MEMORY DEVICE WITH NANOPARTICLE ELECTRODE AND METHOD OF FABRICATION

A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle. 1. An apparatus , comprising:a processor; a first electrode;', 'an aluminum layer in contact with the first electrode, the aluminum layer comprising at least one nanochannel that extends through the aluminum layer to the first electrode;', 'at least one nanoparticle in contact with the aluminum layer, within the at least one nanochannel, or both;', 'a first germanium selenide layer in contact with the aluminum layer and the at least one nanoparticle; and', 'a second electrode in contact with the first germanium selenide layer., 'a memory circuit configured to communicate with the processor, the memory circuit comprising2. The apparatus of claim 1 , further comprising:a layer of nanoparticle material in contact with the first germanium selenide layer, wherein a thickness of the layer of nanoparticle material is the same as a thickness of the at least one nanochannel in the aluminum layer.3. The apparatus of claim 1 , further comprising:a metal chalcogenide layer in contact with the first germanium selenide layer; anda second germanium selenide layer in contact with the metal chalcogenide layer.4. The apparatus of claim 3 , further comprising:a metal layer in contact with the second germanium selenide layer, wherein at least a portion of the metal layer comprises silver; anda third germanium selenide layer in contact with the metal layer.5. The apparatus of claim 4 , wherein the metal chalcogenide layer comprises a chalcogenide glass.6. The apparatus of claim 5 , wherein the chalcogenide glass comprises at least a portion of the metal chalcogenide layer.7. The apparatus of claim 1 , wherein the first electrode and the second electrode each comprise at least one of tungsten ...

MEMORY ELEMENT WITH A REACTIVE METAL LAYER

A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals. 1. A memory plug comprising: a conductive layer; and', 'a reactive metal that reacts with the conductive layer, the memory plug being capable of reversibly switching from a first resistive state to a second resistive state., 'a multi-resistive state element, wherein the multi-resistive state element comprises2. The memory plug of claim 1 , wherein the reactive metal is fully reacted with the conductive layer.3. The memory plug of claim 1 , wherein the memory plug can be exposed to a range of voltages without disturbing the resistive state of the memory plug.4. The memory plug of claim 1 , further comprising:at least two electrodes.5. The memory plug of claim 4 , wherein at least one of the electrodes is Pt.6. The memory plug of claim 1 , wherein the conductive layer is a conductive metal oxide.7. The memory plug of claim 1 , wherein the reactive metal is one or more of Al claim 1 , Ti claim 1 , Mg claim 1 , W claim 1 , Fe claim 1 , Cr claim 1 , Vn claim 1 , Zn claim 1 , Ta or Mo.8. The memory plug of claim 1 , wherein the multi-resistive state element has a non-ohmic characteristic such that the multi-resistive state element exhibits:a high resistance regime for a range of voltages; anda resistance indicative of the first resistive state or the second resistive state for voltages outside of the range of voltages.9. The memory plug of claim 8 , further comprising:a non-ohmic device electrically in series with the multi-resistive state element and ...

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME

A semiconductor device includes bit line structures on a substrate, the bit line structures extending along a first direction and being spaced apart from each other along a second direction perpendicular to the first direction, contact plugs spaced apart from each other along the first direction and being on active regions of the substrate between adjacent bit line structures, a linear spacer on each longitudinal sidewall of a bit line structure, landing pads on the contact plugs, respectively, the landing pads being electrically connected to the contact plugs, respectively, and landing pads that are adjacent to each other along the first direction being offset with respect to each other along the second direction, as viewed in a top view, a conductive pad between each of the contact plugs and a corresponding active region, a vertical axes of the conductive pad and corresponding active region being horizontally offset. 1. A semiconductor device , comprising:a plurality of bit line structures on a substrate, the plurality of bit line structures extending along a first direction and being spaced apart from each other along a second direction perpendicular to the first direction, and each of the bit line structures including a bit line and a hard mask pattern;a plurality of contact plugs spaced apart from each other along the first direction, the plurality of contact plugs being on active regions of the substrate between adjacent ones of plurality of bit line structures;a linear spacer on each longitudinal sidewall of a bit line structure of the plurality of bit line structures, the linear spacer being between the bit line structure of the plurality of bit line structures and the plurality of contact plugs;a plurality of landing pads on the plurality of contact plugs, respectively, the plurality of landing pads being electrically connected to the plurality of contact plugs, respectively, and landing pads of the plurality of landing pads that are adjacent to each other ...

METHODS OF FORMING RESISTIVE MEMORY ELEMENTS

A resistive memory element comprises a first electrode, an active material over the first electrode, a buffer material over the active material and comprising longitudinally extending, columnar grains of crystalline material, an ion reservoir material over the buffer material, and a second electrode over the ion reservoir material. A memory cell, a memory device, an electronic system, and a method of forming a resistive memory element are also described. 1. A method of forming a resistive memory element , comprising:forming a switchable resistivity material over an electrode, the switchable resistivity material comprising one or more of a metal oxide and a chalcogenide;{'sub': x', 'x', 'x', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y, 'forming a buffer material over the switchable resistivity material, the buffer material comprising longitudinally extending, columnar grains of one or more of TiN, TaN, WN, TiNC, TaNC, WNC, TiNB, TaNB, WNB, TiNSi, TaNSi, and WNSi;'}forming a material over the buffer material, the material comprising a chalcogen and one or more of Cu, Ag, and Al; andforming another electrode over the material.2. The method of claim 1 , wherein forming a switchable resistivity material over an electrode comprises forming one or more of SiO claim 1 , AlO claim 1 , HfO claim 1 , HfSiO claim 1 , ZrO claim 1 , ZrSiO claim 1 , TiO claim 1 , TiSiO claim 1 , TaO claim 1 , TaSiO claim 1 , NbO claim 1 , NbSiO claim 1 , VO claim 1 , VSiO claim 1 , WO claim 1 , WSiO claim 1 , MoO claim 1 , MoSiO claim 1 , CrO claim 1 , and CrSiOover the electrode.3. The method of claim 1 , wherein forming a buffer material over the switchable resistivity material comprises forming the buffer material to further comprise one or more of O claim 1 , S claim 1 , Se claim 1 , and Te.4. The method of claim 1 , wherein forming a buffer material over the switchable resistivity material comprises forming the buffer material to have a thickness ...

STRUCTURES INCORPORATING AND METHODS OF FORMING METAL LINES INCLUDING CARBON

Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element. The memory cell stack further includes an electrode interposed between the at least one of the upper and lower conductive lines and the closer of the first and second active elements. 1. A method , comprising:forming a lower conductive line extending in a first direction by patterning a lower conductive material over a substrate;forming an upper conductive line extending in a second direction by patterning an upper conductive material over the lower conductive line;forming a memory cell between the lower conductive line and the upper conductive line, the memory cell including at least one active element, wherein the lower conductive line and the at least one active element are patterned in the first direction using a single mask process, and the upper conductive line and the at least one active element are patterned in the second direction using a single mask process, such that the at least one active element is isolated in both first and second directions after forming the memory cell; andwherein the upper conductive line, ...

RRAM CELL STRUCTURE WITH CONDUCTIVE ETCH-STOP LAYER

The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode. 1. A resistive random access memory (RRAM) device comprising:a semiconductor substrate;a metal interconnect structure disposed within a low-k dielectric layer and disposed over the semiconductor substrate;a conductive etch-stop layer (CESL) abutting an upper surface of the metal interconnect structure;a bottom electrode structure over the CESL;a variable resistance dielectric structure over the bottom electrode structure;a top electrode structure over the variable resistance dielectric structure;sidewall spacers about outer sidewalls of the top electrode structure; andwherein outer sidewalls of the bottom electrode structure are spaced apart by a first distance, and outer sidewalls of the top electrode structure are spaced apart by a second distance which is less than the first distance;wherein the CESL is a transitional metal nitride layer having an etch-selectivity that differs from an etch-selectivity of the bottom electrode structure.2. The RRAM device of claim 1 , wherein the bottom electrode structure is a single conductive electrode layer.3. The RRAM device of claim 1 , ...

PROGRAMMABLE CURRENT FOR CORRELATED ELECTRON SWITCH

Subject matter disclosed herein may relate to programmable current for correlated electron switches. 123-. (canceled)24. A method , comprising:providing a programmable current to a correlated electron switch at least in part to cause a transition in the correlated electron switch from a first impedance state to a second impedance state, including controlling the programmable current to a specified compliance current level.25. The method of claim 24 , wherein the first and second impedance states respectively include particular approximate resistance and capacitance characteristics claim 24 , wherein the capacitance of the first impedance state exceeds the capacitance of the second impedance state.26. The method of claim 24 , wherein the providing the programmable current to the correlated electron switch comprises generating the programmable current at least in part in accordance with a digital code.27. The method of claim 26 , wherein the digital code specifies a particular current level of a plurality of current levels available from a programmable current source.28. The method of claim 27 , wherein the generating the programmable current at least in part in accordance with the digital code comprises generating a programmable current having a level that is a multiple of a unit current level claim 27 , wherein the multiple is determined at least in part by the digital code.29. The method of claim 27 , wherein the first impedance state comprises a higher impedance state and the second impedance state comprises a lower impedance state claim 27 , and wherein the generating the programmable current at least in part in accordance with the digital code comprises the controlling the programmable current to the specified compliance current level.30. The method of claim 29 , wherein the generating the programmable current at least in part in accordance with the digital code comprises generating the current sufficient to achieve a set condition and limited to the specified ...

CORRELATED ELECTRON SWITCH PROGRAMMABLE FABRIC

Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices. 123-. (canceled)24. A method , comprising:selectively connecting or disconnecting one or more portions of an integrated circuit to one or more other portions of the integrated circuit at least in part by selectively applying a programming voltage to one or more correlated electron switch devices to cause a transition in the one or more correlated electron switch devices from a first impedance state to a second impedance state, wherein the one or more correlated electron switch devices are respectively positioned between one or more electrodes of a first metallization layer and one or more electrodes of a second metallization layer.25. The method of claim 24 , wherein the selectively connecting or disconnecting the one or more portions of the integrated circuit to the one or more other portions of the integrated circuit comprises compensating for manufacturing errors in the integrated circuit.26. The method of claim 24 , wherein the selectively connecting or disconnecting the one or more portions of the integrated circuit to the one or more other portions of the integrated circuit comprises compensating for design errors in the integrated circuit.27. The method of claim 24 , wherein the selectively connecting or disconnecting the one or more portions of the integrated circuit to the one or more other portions of the integrated circuit comprises reducing power consumption in the integrated circuit at least in part by selectively disconnecting a supply voltage from the one or more portions of the integrated circuit.28. The method of claim 24 , wherein the selectively connecting or disconnecting the one or more portions of the integrated circuit to the one or more other portions of the integrated circuit comprises adjusting clock skew between specified portions of the integrated circuit.29. The method of claim 28 , wherein the integrated circuit comprises a ...

NEURAL NETWORK CIRCUIT

A neural network circuit includes: multiple storage portions that include a memristor; multiple D/A converters that receive data, causing a signal voltage to be applied to multiple voltage input terminals of the storage portions; multiple drive amplifiers that are connected between to the D/A converters and the voltage input terminals; multiple I/V conversion amplifiers that are connected to at least one current output terminal of the storage portions; multiple A/D converters; and a series circuit of a first switch and a second switch that is disposed in a feedback loop of each of the drive amplifiers; and a series circuit of a third switch and a fourth switch that is disposed in a feedback loop of each of the I/V conversion amplifiers. 1. A neural network circuit comprising:a plurality of storage portions that include a memristor, the memristor being a variable resistance element as a storage element and being connected in a lattice shape;a plurality of D/A converters that receive data, causing a signal voltage to be applied to a plurality of voltage input terminals of the storage portions;a plurality of drive amplifiers that are connected between to the D/A converters and the voltage input terminals;a plurality of I/V conversion amplifiers that are connected to at least one current output terminal of the storage portions and are configured to convert a current flowing in the current output terminal into voltage to be output as a signal voltage;a plurality of A/D converters that are configured to perform A/D conversion of the signal voltage, which is converted by the I/V conversion amplifiers;a series circuit of a first switch and a second switch that is disposed in a feedback loop of each of the drive amplifiers; anda series circuit of a third switch and a fourth switch that is disposed in a feedback loop of each of the I/V conversion amplifiers,wherein:a common connection point of the first switch and the second switch is connected to one end of the memristor;a ...

RRAM MEMORY CELL WITH MULTIPLE FILAMENTS

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a conductive element disposed within a dielectric structure over the substrate. The conductive element has a top surface extend between outermost sidewalls of the conductive element. A first resistive random access memory (RRAM) element is arranged within the dielectric structure and has a first data storage layer directly contacting the top surface of the conductive element. A second RRAM element is arranged within the dielectric structure and has a second data storage layer directly contacting the top surface of the conductive element. 1. An integrated chip , comprising:a conductive element disposed within a dielectric structure over a substrate, wherein the conductive element comprises a top surface extending between outermost sidewalls of the conductive element;a first resistive random access memory (RRAM) element arranged within the dielectric structure and having a first data storage layer directly contacting the top surface of the conductive element; anda second RRAM element arranged within the dielectric structure and having a second data storage layer directly contacting the top surface of the conductive element.2. The integrated chip of claim 1 , wherein a bottom surface of the conductive element has smaller width than the top surface of the conductive element.3. The integrated chip of claim 2 , further comprising:one or more lower interconnect layers disposed within a lower inter-level dielectric (ILD) structure that is between the bottom surface of the conductive element and the substrate.4. The integrated chip of claim 3 , wherein the conductive element is a different material than the one or more lower interconnect layers.5. The integrated chip of claim 3 , further comprising:an insulating layer disposed over the lower ILD structure and laterally surrounding a part of the conductive element, wherein the conductive element has a lower surface that is ...

FIN SELECTOR WITH GATED RRAM

A method of fabricating a fin selector with a gated RRAM and the resulting device are disclosed. Embodiments include forming a bottom electrode layer and a hardmask on a semiconductor substrate; etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure; forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively; forming spacers on vertical surfaces of the first and second dummy gate stacks; forming an ILD surrounding the spacers; removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure; forming an RRAM layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; and filling each of the first and second cavities with a top electrode. 1. A phase-change random access memory (PCRAM) comprising:a semiconductor substrate;a heater layer formed on the semiconductor substrate, the heater layer and the semiconductor substrate forming a fin-like structure;an interlayer dielectric (ILD) formed on side surfaces of the fin-like structure;{'sub': 2', '2', '5, 'a GeSbTe(GST) material formed in contact with the heater layer; and'}a top electrode formed on the GST layer, to form the PCRAM.2. The PCRAM according to claim 1 , comprising:a hardmask on the heater layer, the GST layer on a top surface of the ILD on each side of the fin-like structure and on each side surface of the heater layer and the hardmask, and a top electrode on each side of the fin-like structure; orthe GST layer on the heater layer, and the top electrode over the GST layer and the ILD on each side of the fin-like structure.3. The PCRAM according to claim 1 , wherein the heater layer comprises: TaN claim 1 , TiN claim 1 , titanium tungsten (TiW) claim 1 , titanium silicon nitride (TiSiN) claim 1 , or tantalum silicon nitride (TaSiN) claim 1 , and formed to a thickness of 3 to 20 nm ...

CHALCOGENIDE MEMORY DEVICE COMPONENTS AND COMPOSITION

Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A memory device, such as a selector device, may be made of a chalcogenide material composition. A chalcogenide material may have a composition that includes one or more elements from the boron group, such as boron, aluminum, gallium, indium, or thallium. A selector device, for instance, may have a composition of selenium, arsenic, and at least one of boron, aluminum, gallium, indium, or thallium. The selector device may also be composed of germanium or silicon, or both. The relative amount of boron, aluminum, gallium, indium, or thallium may affect a threshold voltage of a memory component, and the relative amount may be selected accordingly. A memory component may, for instance have a composition that includes selenium, arsenic, and some combination of germanium, silicon, and at least one of boron, aluminum, gallium, indium, or thallium. 1. (canceled)2. A composition of matter , comprising:silicon;germanium; andat least one element selected from a group of consisting of boron, aluminum, gallium, indium, and thallium, wherein a combination of the silicon, the germanium, and the at least one element selected from the group consisting of boron, aluminum, gallium, indium, and thallium is in an amount greater than or equal to 20% by weight, relative to a total weight of the composition.3. The composition of claim 2 , further comprising selenium.4. The composition of claim 3 , wherein the selenium is in an amount greater than or equal to 40% by weight claim 3 , relative to the total weight of the composition.5. The composition of claim 2 , further comprising arsenic.6. The composition of claim 5 , wherein the arsenic is in an amount ranging from 10% to 35% by weight claim 5 , relative to the total weight of the composition.7. The composition of claim 2 , wherein the at least one element selected from the group consisting of boron claim 2 , aluminum claim ...

HIGH DENSITY MEMORY ARCHITECTURE USING BACK SIDE METAL LAYERS

A microelectronic memory having metallization layers formed on a back side of a substrate, wherein the metallization layers on back side may be used for the formation of source lines and word lines. Such a configuration may allow for a reduction in bit cell area, a higher memory array density, and lower source line and word line resistances. Furthermore, such a configuration may also provide the flexibility to independently optimize interconnect performance for logic and memory circuits. 1. A microelectronic memory comprising:a substrate comprising a single material structure, wherein the substrate has a front surface and an opposing back surface,a memory bitcell transistor on the substrate front surface, wherein the memory bitcell transistor includes at least one source/drain structure formed in the substrate, wherein the source line is electrically connected to the at least one source/drain structure;a word line formed on the substrate back surface;a word line strap comprising the word line on the substrate back surface electrically connected to a word line within a memory bitcell transistor;a source line positioned between the word line and the substrate; anda memory cell transistor array on the substrate front surface.2. The microelectronic memory of claim 1 , wherein the source line is electrically connected to the at least one source/drain structure through a deep diffusion contact within the substrate.3. The microelectronic memory of claim 1 , wherein the word line on the substrate back surface is electrically connected to a word line within a memory bitcell transistor through a source/drain structure and a deep diffusion contact within the substrate.4. The microelectronic memory of claim 1 , wherein the memory cell transistor array comprises a plurality of resistance based memory transistors.5. The microelectronic memory of claim 1 , further including the source line directly contacting the substrate back surface.6. The microelectronic memory of claim 1 , ...

CORRELATED ELECTRON SWITCH STRUCTURES AND APPLICATIONS

Subject matter disclosed herein may relate to devices formed from correlated electron material. 123-. (canceled)24. A method , comprising:providing a programmable current specified at least in part by a digital code to a correlated electron switch device, wherein a first plurality of bits of the digital code to specify a coarse tuning of the programmable current at least in part to enable a transition in the correlated electron switch from a first impedance state to a second impedance state, and wherein a second plurality of bits of the digital code to further specify a fine tuning of the programmable current.25. The method of claim 24 , wherein the second plurality of bits of the digital code to further specify the fine tuning of the programmable current at least in part to enable a subsequent transition in the correlated electron switch from the second impedance state to the first impedance state.26. The method of claim 24 , further comprising generating the programmable current specified at least in part by the digital code.27. The method of claim 26 , wherein the generating the programmable current specified at least in part by the digital code comprises the controlling the programmable current to a specified compliance current level.29. The method of claim 27 , wherein the generating the programmable current specified at least in part by the digital code at least in part to enable the transition in the correlated electron switch from the first impedance state to the second impedance state comprises generating a current sufficient to achieve a set condition.30. The method of claim 29 , wherein the generating the current sufficient to achieve the set condition comprises generating a current limited to the specified compliance current level to establish a particular threshold current density level in the correlated electron switch for a subsequent operation to transition the correlated electron switch from the second impedance state to the first impedance state.31 ...

PROGRAMMABLE CURRENT FOR CORRELATED ELECTRON SWITCH

Subject matter disclosed herein may relate to programmable current for correlated electron switches. 123-. (canceled)24. A method , comprising:providing a programmable current specified at least in part by a digital code to a correlated electron switch device, wherein a first plurality of bits of the digital code to specify a coarse tuning of the programmable current at least in part to enable a transition in the correlated electron switch from a first impedance state to a second impedance state, and wherein a second plurality of bits of the digital code to further specify a fine tuning of the programmable current.25. The method of claim 24 , wherein the second plurality of bits of the digital code to further specify the fine tuning of the programmable current at least in part to enable a subsequent transition in the correlated electron switch from the second impedance state to the first impedance state.26. The method of claim 24 , further comprising generating the programmable current specified at least in part by the digital code.27. The method of claim 26 , wherein the generating the programmable current specified at least in part by the digital code comprises the controlling the programmable current to a specified compliance current level.29. The method of claim 27 , wherein the generating the programmable current specified at least in part by the digital code at least in part to enable the transition in the correlated electron switch from the first impedance state to the second impedance state comprises generating a current sufficient to achieve a set condition.30. The method of claim 29 , wherein the generating the current sufficient to achieve the set condition comprises generating a current limited to the specified compliance current level to establish a particular threshold current density level in the correlated electron switch for a subsequent operation to transition the correlated electron switch from the second impedance state to the first impedance ...

STORAGE DEVICE WITH COMPOSITE SPACER AND METHOD FOR MANUFACTURING THE SAME

A storage device includes a first electrode, a stacked feature, a spacer and a barrier structure. The stacked feature is position over the first electrode, and includes a storage element and a second electrode over the storage element. The spacer is positioned on a sidewall of the stacked feature, the spacer having a notch positioned on a top surface of the spacer, in which the notch of the spacer has a surface which is continuous with a top surface of the stacked feature. The barrier structure is embedded in a lateral of the spacer. The barrier structure has a top extending upwards past a bottom of the notch. 1. A storage device , comprising:a first electrode;a stacked feature over the first electrode and comprising a storage element and a second electrode over the storage element;a spacer positioned on a sidewall of the stacked feature, the spacer having a notch positioned on a top surface of the spacer, wherein the notch of the spacer comprises a surface which is continuous with a top surface of the stacked feature; anda barrier structure embedded in a lateral of the spacer, wherein the barrier structure has a top extending upwards past a bottom of the notch.2. The storage device according to claim 1 , wherein the spacer is directly attached to the sidewall of the second electrode and a sidewall of the storage element.3. The storage device according to claim 1 , wherein the spacer comprises a bottom portion and a standing portion extending upwards from the bottom portion claim 1 , and the bottom portion has a width greater than a width of the standing portion.4. The storage device according to claim 3 , wherein the bottom portion is positioned on and in contact with a top surface of the first electrode.5. The storage device according to claim 3 , wherein the barrier structure stands on the bottom portion and in contact with the standing portion.6. The storage device according to claim 3 , wherein the width of the bottom portion of the spacer is approximately 5-30 ...

MEMORY CELL WITH INDEPENDENTLY-SIZED ELECTRODE

Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode. 120.-. (canceled)21. An apparatus , comprising:a first electrode extending a first distance in a first lateral dimension;a second electrode coupled to the first electrode, the second electrode extending a second distance in the first lateral dimension; anda third electrode coupled to the second electrode, the third electrode extending the first distance in the first lateral dimension.22. The apparatus of claim 21 , wherein the second electrode is formed from a material that is different than a material used to form the first electrode or a material used to form the third electrode.23. The apparatus of claim 21 , wherein the second distance in the first lateral dimension is less than the first distance in the first lateral dimension.24. The apparatus of claim 21 , wherein:the first electrode extends a first distance in a second lateral dimension,the second electrode extends a second distance in the second lateral dimension, andthe third electrode extends the first distance in the second lateral dimension.25. The apparatus of claim 24 , wherein the second distance in the second lateral dimension is less than the first distance in the second lateral dimension.26. The apparatus of claim 21 , wherein the second electrode is formed of a material having a higher etch rate than a material of which at least one of the first electrode and the second electrode is formed.27. The apparatus of claim 21 , wherein the second electrode is self-aligned with a conductive line coupled to the first ...

Resistive Switching Random Access Memory with Asymmetric Source and Drain

A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain of the FET has a higher doping concentration than the source of the FET. The resistive memory element is coupled with the drain via a portion of an interconnect structure. 1. A resistive random access memory (RRAM) structure , comprising: a top electrode;', 'a bottom electrode; and', 'a resistive material layer positioned between the top electrode and the bottom electrode; and, 'a resistive memory element formed on a semiconductor substrate, wherein the resistive element includesa field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain, wherein the drain of the FET has a higher doping concentration than the source of the FET;wherein the resistive memory element is coupled with the drain via a portion of an interconnect structure.2. The RRAM structure of claim 1 , wherein the source and drain are designed asymmetrically such that a voltage drop over the FET during a forming operation and an off-state leakage current are collectively optimized.3. The RRAM structure of claim 1 , wherein the FET further includes:a channel region formed in the semiconductor substrate; anda gate vertically disposed over the channel region and horizontally interposed between the source and drain,wherein the source and drain of the FET further include light doped drain (LDD) source and drain features that are asymmetric.4. The RRAM structure of claim 3 , wherein:the LDD source feature has a first doping concentration; andthe LDD drain feature has a second doping concentration different from the first doping ...

CEM SWITCHING DEVICE

Subject matter herein disclosed relates to a method for the manufacture of a switching device comprising a silicon-containing correlated electron material. In embodiments, processes are described for forming the silicon-containing correlated electron material. These processes may use comparatively lower temperatures as compared to those used for forming a correlated electron material comprising a transition metal oxide. 1. A CEM switching device comprising a correlated electron material (CEM) layer provided on a conductive substrate , wherein the CEM layer comprises a silicon-containing CEM layer comprising a silicate of formula MSiO:dopant , wherein M is a d- or f-block element , the dopant comprises carbon , halogen , nitrogen , sulfur or phosphorus and x , y and z are greater than zero and not necessarily integers.2. The CEM switching device according to claim 1 , further comprising a conductive overlay provided on the silicon-containing CEM layer.3. The CEM switching device according to claim 1 , wherein the silicon-containing CEM layer has a silicon content between 1 atom % and 20 atom %.4. The CEM switching device according to claim 3 , wherein the silicon-containing CEM layer has a dopant content which is less than the silicon content.5. The CEM switching device according to claim 1 , wherein the metal M is selected from the group consisting of aluminum claim 1 , cadmium claim 1 , chromium claim 1 , cobalt claim 1 , copper claim 1 , gold claim 1 , iron claim 1 , manganese claim 1 , mercury claim 1 , molybdenum claim 1 , nickel claim 1 , palladium claim 1 , rhenium claim 1 , silver claim 1 , tantalum claim 1 , tin claim 1 , titanium claim 1 , vanadium claim 1 , rhenium claim 1 , ruthenium claim 1 , silver claim 1 , tantalum claim 1 , tin claim 1 , titanium claim 1 , vanadium claim 1 , yttrium claim 1 , ytterbium and zinc.6. The CEM switching device according to claim 1 , wherein the silicon-containing CEM layer is amorphous.7. The CEM switching device ...

CONTROLLING DOPANT CONCENTRATION IN CORRELATED ELECTRON MATERIALS

Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) device. In embodiments, after formation of the one or more CEM traces, a spacer may be deposited in contact with the one or more CEM traces. The spacer may operate to control an atomic concentration of dopant within the one or more CEM traces by replenishing dopant that may be lost during subsequent processing and/or by forming a seal to reduce further loss of dopant from the one or more CEM traces. 121-. (canceled)22. A device , comprising:a plurality of correlated electron material (CEM) traces formed over a first level, one or more individual CEM traces of the plurality of CEM traces to comprise an electron back-donating material to include a dopant; anda spacer formed to fill at least a portion of a trench separating adjacent individual CEM traces of the plurality of CEM traces, the spacer to control an atomic concentration of the dopant within the one or more individual CEM traces of the plurality of CEM traces at least in part by enabling diffusion of the dopant from the spacer into the one or more individual CEM traces to thereby impart particular impedance switching characteristics within the one or more individual CEM traces of the plurality of CEM traces.23. The device of claim 22 , wherein the spacer is adapted to diffuse the dopant into the one or more individual CEM traces of the plurality of CEM traces to maintain the atomic concentration of the dopant within the one or more individual CEM traces in a range of about 0.1% to about 10.0%.24. The device of claim 23 , wherein the dopant to comprise a carbon-containing dopant species or a nitrogen-containing dopant species claim 23 , or a combination thereof.25. The device of claim 22 , wherein the spacer to comprise an atomic concentration of at least 50.0% silicon nitride (SiN).26. The device of claim 22 , wherein the spacer to comprise an atomic concentration of at least 50.0% silicon nitride (SiO).27. The ...

SEMICONDUCTOR DEVICES

A semiconductor device includes a stacked structure of cell structures, an electrode structure, and a heating electrode. Each cell structure includes a capping layer, a selection layer, a buffer layer, a variable resistance layer, and a upper electrode layer sequentially stacked. The electrode structure is in an opening passing through the stacked structure, is electrically isolated from the buffer layer, the variable resistance layer, and the upper electrode layer, and is electrically connected to the selection layer. The heating electrode is between the variable resistance layer and the upper electrode layer and operates to transfer heat to the variable resistance layer. 1. A semiconductor device , comprising:a stacked structure including a plurality of cell structures stacked on a substrate, each of the plurality of cell structures including a capping layer, a selection layer, a buffer layer, a variable resistance layer, and a upper electrode layer sequentially stacked;an electrode structure in an opening through the stacked structure, the electrode structure being electrically isolated from the buffer layer, the variable resistance layer, and the upper electrode layer and being electrically connected to the selection layer; anda heating electrode between the variable resistance layer and the selection layer, the heating electrode to transfer heat to the variable resistance layer.2. The semiconductor device as claimed in claim 1 , wherein each of the selection layer and the variable resistance layer includes a chalcogenide-based material.3. The semiconductor device as claimed in claim 1 , wherein:the selection layer includes an Ovonic threshold switch (OTS) material, andthe variable resistance layer includes a GST material including germanium (Ge), antimony (Sb), and/or tellurium (Te) in a predetermined ratio.4. The semiconductor device as claimed in claim 1 , wherein the heating electrode directly contacts a portion of a surface of the variable resistance layer. ...

VARIABLE RESISTIVE ELEMENT, STORAGE DEVICE AND DRIVING METHOD THEREOF

An element according to an embodiment can transit between at least two states including a low-resistance state and a high-resistance state. The element comprises a first electrode, a second electrode, a first layer and a second layer. The first electrode includes metal elements. The first layer is located between the first electrode and the second electrode while contacting with the first electrode. The second layer is located between the first layer and the second electrode. At the low-resistance state, a density of the metal elements in the first layer is higher than that of the metal elements in the second layer. The density of the metal elements in the first layer at the low-resistance state is higher than that of the metal elements in the first layer at the high-resistance state. A relative permittivity of the second layer is higher than a relative permittivity of the first layer. 1. A variable resistive element capable of transiting between at least two states including a low-resistance state and a high-resistance state , the variable resistive element comprising:a first electrode including metal elements;a second electrode;a first variable resistive layer located between the first electrode and the second electrode; anda second variable resistive layer located between the first variable resistive layer and the second electrode, whereinat the low-resistance state, a density of the metal elements in the first variable resistive layer is higher than a density of the metal elements in the second variable resistive layer,the density of the metal elements in the first variable resistive layer at the low-resistance state is higher than a density of the metal elements in the first variable resistive layer at the high-resistance state, anda relative permittivity of the second variable resistive layer is higher than a relative permittivity of the first variable resistive layer.2. The element according to claim 1 , whereinthe metal elements includes at least one of Ag, ...

CEM SWITCHING DEVICE

Subject matter herein disclosed relates to an improved CEM switching device and methods for its manufacture. In this device, a conductive substrate and/or conductive overlay comprises a primary layer of a conductive material and a secondary layer of a conductive material. The primary layer contacting the CEM layer is substantially inert to the CEM layer and/or acts as an oxygen barrier for the secondary layer at temperatures used for the manufacture of the device. 1. A method for the manufacture of a CEM switching device , which method comprises forming a conductive substrate and forming a layer of a correlated electron material (CEM) on the conductive substrate , wherein the forming of the conductive substrate comprises forming a primary layer of a conductive material and forming a secondary layer of a conductive material such that the primary layer contacts the CEM layer and wherein the forming of the conductive material of the primary layer is substantially resistant to diffusion or migration of oxygen ion from the CEM layer to the secondary layer.2. The method according to claim 1 , wherein the method further comprises forming a conductive overlay on the CEM layer claim 1 , the conductive overlay being a single layer of a conductive material which is resistant to diffusion or migration of oxygen ion.3. The method according to claim 1 , wherein the primary layer of the conductive substrate is more resistant to etching as compared to the CEM layer.4. The method according to claim 1 , wherein the work function of the primary layer is matched with that of the CEM layer.5. The method according to claim 1 , wherein the forming of the primary layer comprises forming a plurality of sub-layers of different noble metals and/or noble metal oxides.6. The method according to claim 1 , wherein the forming of the primary layer comprises forming monolayers comprising more than one noble metal and/or noble metal oxide.7. The method according to claim 1 , wherein the conductive ...

CEM SWITCHING DEVICE

Subject matter herein disclosed relates to a method for the manufacture of a CEM switching device providing that the CEM layer comprises a doped metal compound substantially free from metal wherein ions of the same metal element are present in different oxidation states. The method may provide a CEM layer which is born on and capable of switching with operating voltages below 2.0V. 1. A method for the manufacture of a CEM switching device , which method comprises forming a conductive substrate and forming a layer of correlated electron material (CEM) on or over the conductive substrate , wherein the forming of the CEM layer comprises forming a layer of a correlated electron material comprising a doped metal compound of a d- or f-block element comprising ions of the same d- or f-block element in different oxidation states and less than 5 atom % of free d- or f-block element , the free d- or f-block element being unbound and in a zero oxidation state.2. The method according to claim 1 , wherein the doped metal compound comprises two different ions of the same d- or f-block element.3. The method according to claim 2 , wherein the doped metal compound comprises three different ions of the same d- or f-block element.4. The method according to claim 1 , wherein the different ions of the same d- or f-block element have oxidation states +2 and +3.5. The method according to claim 1 , wherein the doped metal compound is a doped nickel oxide comprising Niand Niions.6. The method according to claim 1 , wherein the doped metal compound is a doped nickel oxide comprising Ni claim 1 , Ni and Niions.7. The method according to or claim 1 , wherein the doped nickel oxide is absent a peak in the X-ray photoelectron spectroscopy spectrum of the CEM layer corresponding to unbound nickel in zero oxidation state.8. The method according to claim 1 , further comprising forming a conductive overlay on the CEM layer.9. The method according to claim 1 , wherein the dopant is carbonyl ligand.10 ...

MEMORY DEVICE HAVING STITCHED ARRAYS OF 4 F² MEMORY CELLS

A memory device comprises a semiconductor substrate having a plurality of parallel trenches therein, a memory region formed in the substrate including an array of memory cells having a plurality of vertical selection transistors with respective channels formed in trench sidewalls, a plurality of buried source electrodes in trench bottoms, a plurality of paired gate electrodes formed on paired trench sidewalls, a first and second stitch region disposed adjacent the memory region along a trench direction including a first and second row of gate contacts, respectively, and a row of source contacts disposed in the first or second stitch region with each of the source contacts coupled to a respective one of the source electrodes. One of each pair of the gate electrodes is coupled to a respective one of the first row of gate contacts and the other one of each pair of gate electrodes is coupled to a respective one of the second row of gate contacts. 1. A memory device comprising:a semiconductor substrate having a plurality of parallel trenches therein, each of said trenches having a respective one of a plurality of trench bottoms and a respective pair of a plurality of paired trench sidewalls;a memory region formed in said semiconductor substrate, said memory region including an array of memory cells having a plurality of vertical selection transistors with respective channels formed in said trench sidewalls;a plurality of buried source electrodes formed in said trench bottoms, said buried source electrodes coupled to said memory cells along a first direction substantially parallel to said trenches;a plurality of parallel bit lines coupled to said memory cells along a second direction substantially orthogonal to said first direction;a plurality of paired gate electrodes formed on said paired trench sidewalls, said gate electrodes coupled to said memory cells along said first direction;a first and a second stitch region disposed adjacent said memory region along said first ...

COMPACT RRAM STRUCTURE WITH CONTACT-LESS UNIT CELL

A RRAM device having a diode device structure coupled to a variable resistance layer is disclosed. The diode device structure can either be embedded into or fabricated over the substrate. A memory device having an array of said RRAM devices can be fabricated with multiple common bit lines and common word lines. 1. A memory cell comprising:a substrate;a bottom electrode disposed on the substrate;a doped layer disposed on the substrate, wherein the doped layer and bottom electrode form a diode;a storage layer; anda top electrode, wherein the storage layer is disposed between the top and bottom electrodes on the substrate.2. The device in claim 1 , wherein the storage layer comprises variable resistance material.3. The device in claim 1 , wherein the bottom electrode comprises a conductive word line conductively coupled to the diode.4. The device in claim 1 , wherein the doped layer comprises a first polarity type dopants which is opposite to a second polarity type dopants of the bottom electrode.5. The device in claim 1 , wherein the doped layer is disposed on the bottom electrode.6. A RRAM device claim 1 , comprising:a substrate with an active region;a conductive bit line electrode;a variable resistance layer positioned between said conductive bit line electrode and said active region;a diffusion region in the substrate in the active region positioned under said variable resistance layer;a first semiconductor layer having first polarity type dopants; anda second semiconductor layer having second polarity type dopants wherein said first semiconductor layer is positioned between said conductive bit line electrode and said second semiconductor material.7. The device in claim 6 , wherein said first and second semiconductor layers form a diode device coupled to said bit line electrode.8. The device in claim 6 , wherein said diffusion region comprises a conductive word line conductively coupled to said variable resistance layer.9. The device in claim 6 , wherein said first ...

Semiconductor device structures including ferroelectric memory cells

A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.

VARIABLE RESISTANCE MEMORY DEVICE

The present invention relates to a variable resistance memory device and a method for forming the same. A variable resistance memory device according to the present invention includes a first electrode; a second electrode spaced apart from the first electrode; a resistance variable layer and a metal-insulator transition layer provided between the first electrode and the second electrode; and a heat barrier layer provided (i) between the first electrode and the metal-insulator transition layer, (ii) between the metal-insulator transition layer and the resistance variable layer, or (iii) between the second electrode and the metal-insulator transition layer. The present invention prevents dissipation of heat generated in the metal-insulator transition layer using a thermal boundary resistance (TBR) phenomenon, and thus current and voltage to operate the variable resistance memory device can be reduced. 1. A variable resistance memory device comprising:a first electrode;a second electrode spaced apart from the first electrode;a resistance variable layer and a metal-insulator transition layer provided between the first electrode and the second electrode; anda heat barrier layer provided between the first electrode and the metal-insulator transition layer, between the metal-insulator transition layer and the resistance variable layer, or between the second electrode and the metal-insulator transition layer.2. The variable resistance memory device of claim 1 , wherein the heat barrier layer includes a material having a Debye temperature that is different from that of the metal-insulator transition layer.3. The variable resistance memory device of claim 1 , wherein the heat barrier layer includes metal claim 1 , oxide claim 1 , nitride claim 1 , or a combination thereof.4. The variable resistance memory device of claim 1 , wherein the heat barrier layer includes a plurality of different layers claim 1 , at least one of the different layers being formed of a different ...

INTERCONNECTION FOR MEMORY ELECTRODES

Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level. 1. (canceled)2. An apparatus , comprising: a plurality of memory cells; and', a first electrode line of the plurality of electrode lines terminates at a first socket region; and', 'a second electrode line of the plurality of electrode lines terminates at a second socket region; and, 'a plurality of electrode lines each coupled with one or more of the plurality of memory cells, the plurality of electrode lines each extending in a first direction, wherein], 'a memory array comprisinga vertical connector coupled with the second electrode line, wherein the vertical connector is within the first socket region.3. The apparatus of claim 2 , further comprising:a second vertical connector; a third electrode line of the second plurality of electrode lines terminates at a third socket region; and', 'a fourth electrode line of the second plurality of electrode lines terminates at a fourth socket region; and, 'a second plurality of electrode lines each coupled with one or more of the plurality of memory cells, the second plurality of electrode lines each extending in a second direction, wherein, 'wherein the memory array further comprises'}wherein the second vertical connector is coupled with the fourth electrode line and is within the third socket region.4. The apparatus of claim 3 , wherein:the second electrode line crosses at least two boundaries of the first socket region; and the fourth electrode line crosses at least two boundaries of the third socket region.5. The apparatus of claim 3 , further comprising:a first driver coupled with the vertical connector and the second electrode line, wherein the first driver is included in a ...

Method for forming a flat bottom electrode via (beva) top surface for memory

Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

THREE DIMENSIONAL MEMORY ARRAYS

In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material. 1. A memory array , comprising:a plurality of first dielectric materials and a plurality of stacks, wherein each respective first dielectric material and each respective stack alternate, and wherein each respective stack comprises a first conductive material and a storage material on only one side of the first conductive material; anda second conductive material passing through the plurality of first dielectric materials and the plurality of stacks such that a major axis of the second conductive material is perpendicular to a major axis of the storage material;wherein each respective stack further comprises a second dielectric material between the first conductive material and the second conductive material.2. The memory array of claim 1 , further comprising a third dielectric material between the second conductive material and the plurality of stacks and between the second conductive material and the plurality of first dielectric materials.3. The memory array of claim 2 , wherein the third dielectric material is in direct physical contact with the plurality of stacks claim 2 , the plurality of first dielectric materials claim 2 , and the second conductive material.4. The memory array of claim 1 , wherein each respective stack further comprises a third dielectric material between the first conductive material and the storage material.5. The memory array of claim 1 , wherein the first conductive material and the storage ...

METHODS OF FORMING MEMORY CELLS AND SEMICONDUCTOR DEVICES

A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described. 1. A method of forming a memory cell , the method comprising:forming a threshold switching material comprising amorphous silicon between a pair of electrodes;forming at least one dielectric material between the threshold switching material and at least one electrode of the pair of electrodes;doping the at least one dielectric material; andforming a memory material adjacent at least one of the electrodes of the pair of electrodes.2. The method of claim 1 , wherein forming a threshold switching material comprises forming the threshold switching material to comprise amorphous silicon doped with at least one of boron claim 1 , aluminum claim 1 , gallium claim 1 , nitrogen claim 1 , or phosphorus.3. The method of claim 1 , wherein forming at least one dielectric material between the threshold switching material and at least one electrode of the pair of electrodes comprises forming a dielectric material between the threshold switching material and each electrode of the pair of electrodes.4. The method of claim 1 , wherein forming at least one dielectric material between the threshold switching material and at least one electrode of the pair of electrodes comprises:forming a first dielectric material between the threshold switching material and a first ...

MEMORY DEVICE

A memory device includes a bottom electrode, a resistance switching element, a top electrode, a first spacer, and a metal-containing compound layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element. The first spacer is disposed along a sidewall of the resistance switching element. The metal-containing compound layer is disposed along a sidewall of the first spacer, in which the first spacer is between the metal-containing compound layer and the resistance switching element. 1. A memory device , comprising:a bottom electrode;a resistance switching element over the bottom electrode;a top electrode over the resistance switching element;a first spacer disposed along a sidewall of the resistance switching element; anda metal-containing compound layer disposed along a sidewall of the first spacer, wherein the first spacer is between the metal-containing compound layer and the resistance switching element.2. The memory device of claim 1 , wherein a bottom of the metal-containing compound layer is over a top of the bottom electrode.3. The memory device of claim 1 , further comprising:a second spacer disposed along a sidewall of the metal-containing compound layer.4. The memory device of claim 3 , wherein a bottom of the second spacer is over a top of the bottom electrode.5. The memory device of claim 3 , wherein the metal-containing compound layer has a first portion between the first spacer and the second spacer.6. The memory device of claim 5 , wherein the metal-containing compound layer has a second portion between a top of the bottom electrode and a bottom of the second spacer.7. The memory device of claim 5 , wherein the metal-containing compound layer has a second portion between the top electrode and the second spacer.8. The memory device of claim 3 , wherein a top of the metal-containing compound layer is higher than a top of the second spacer.9. A memory device claim 3 , comprising:a bottom ...

METHOD FOR MANUFACTURING MEMORY DEVICE

A method includes depositing a bottom electrode layer, a resistance switching element layer, and a top electrode layer over a first dielectric layer; etching the top electrode layer and the resistance switching element layer to form a resistance switching element over the bottom electrode layer and a top electrode over the resistance switching element; depositing a metal-containing compound layer over the top electrode, the resistance switching element, and the bottom electrode layer; and etching the metal-containing compound layer and the bottom electrode layer to form a bottom electrode over the first dielectric layer. 1. A method , comprising:depositing a bottom electrode layer, a resistance switching element layer, and a top electrode layer over a first dielectric layer;etching the top electrode layer and the resistance switching element layer to form a resistance switching element over the bottom electrode layer and a top electrode over the resistance switching element;depositing a metal-containing compound layer over the top electrode, the resistance switching element, and the bottom electrode layer; andetching the metal-containing compound layer and the bottom electrode layer to form a bottom electrode over the first dielectric layer.2. The method of claim 1 , further comprising:prior to depositing the metal-containing compound layer, depositing a spacer layer over the top electrode, the resistance switching element, and the bottom electrode layer; andetching the spacer layer to form a spacer surrounding the resistance switching element.3. The method of claim 2 , wherein etching the spacer layer is performed such that a top of the spacer is higher than a bottom of the top electrode.4. The method of claim 1 , further comprising:prior to etching the metal-containing compound layer and the bottom electrode layer, depositing a spacer layer over the metal-containing compound layer; andetching the spacer layer to form a spacer disposed along a sidewall of the metal ...

METHODS OF FORMING A FERROELECTRIC MEMORY CELL AND RELATED SEMICONDUCTOR DEVICE STRUCTURES

A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material. 1. A method of forming a ferroelectric memory cell , comprising:forming an electrode material exhibiting a desired dominant crystallographic orientation;forming a hafnium-based material over the electrode material; andcrystallizing the hafnium-based material to induce formation of a ferroelectric material having a desired crystallographic orientation.2. The method of claim 1 , wherein forming an electrode material exhibiting a desired dominant crystallographic orientation comprises forming crystalline titanium nitride.3. The method of claim 1 , wherein forming an electrode material exhibiting a desired dominant crystallographic orientation comprises forming titanium nitride in a dominant (111) crystallographic orientation.4. The method of claim 3 , wherein forming titanium nitride in a dominant (111) crystallographic orientation comprises forming the titanium nitride in the dominant (111) crystallographic orientation using an organometallic precursor.5. The method of claim 3 , wherein forming titanium nitride in a dominant (111) crystallographic orientation comprises forming the titanium nitride in the dominant (111) crystallographic orientation by atomic layer deposition.6. The method of claim 3 , wherein forming titanium nitride in a dominant (111) crystallographic orientation comprises forming the titanium nitride in the dominant (111) crystallographic orientation using titanium tetrachloride and ammonia.7. The method of claim 3 , wherein crystallizing the hafnium-based material comprises ...

Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Comprising Resistive Change Material and Method of Operating

A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.

3D VERTICAL MEMORY ARRAY CELL STRUCTURES WITH INDIVIDUAL SELECTORS AND PROCESSES

Three-dimensional vertical memory array cell structures and processes. In an exemplary embodiment, a 3D vertical memory array structure is formed by performing operations that include forming an array stack having alternating metal layers and insulator layers, forming a hole through the array stack to expose internal surfaces of the metal layers and internal surfaces of the insulator layers, and performing a metal-oxidation process on the internal surfaces of the metal layers to form selector devices on the internal surfaces of the metal layers. The operations also include depositing one of resistive material or phase-change material within the hole on the selector devices and the internal surfaces of the insulator layers, such that the hole is reduced to a smaller hole, and depositing conductor material in the smaller hole. 1. A 3D vertical memory array structure , comprising:an array stack having alternating metal layers and insulator layers, and wherein the array stack includes a hole that exposes internal surfaces of the metal layers and internal surfaces of the insulator layers;metal-oxidation on the internal surfaces of the metal layers that forms selector devices on the internal surfaces of the metal layers;one of resistive material or phase-change material within the hole and coupled to the selector devices, and wherein the hole is reduced to a smaller hole; andconductor material in the smaller hole and coupled to the resistive material or the phase-change material.2. The structure of claim 1 , wherein the metal layers comprise one of Tantalum (Ta) claim 1 , Niobium (Nb) claim 1 , Titanium (Ti) claim 1 , Zirconium (Zr) claim 1 , Vanadium-Chromium (VCr) claim 1 , and wherein based on the metal layer the metal-oxidation comprises one of TaOx claim 1 , NbOx claim 1 , TiOX claim 1 , ZrOx claim 1 , or VCrOx claim 1 , respectively.3. The structure of claim 1 , wherein the resistive material comprises one of HfOx claim 1 , LiSiOx claim 1 , ZrSiOx claim 1 , WOx ...

Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Comprising Resistive Change Material and Method of Operating

A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating. 120-. (canceled)21. A semiconductor memory array comprising: a capacitorless transistor having a floating body configured to store data when power is applied to said memory cell; and', 'a non-volatile memory comprising a bipolar resistive change element configured to store data stored in said floating body upon transfer thereto during a shadowing operation;', 'wherein said floating body is configured to be charged to a level indicative of a state of said memory cell based on resistivity of said bipolar resistive change element when a restore operation is performed;', 'wherein said memory cell is configured so that a reset operation is performed on said non-volatile memory upon completion of said restore operation;', 'wherein current flow through said memory cell during said reset operation is the opposite of current flow through said memory cell during said shadowing operation;', 'wherein said shadowing, restore, and reset operations are performed on at least two of said at least two memory cells in parallel., 'a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include22. The semiconductor memory array of claim 21 , wherein each of said at least two of said memory cells functions as volatile memory upon restoration of power thereto.23. The semiconductor memory array of claim 21 , wherein said floating body is configured to a predetermined state prior to being charged based on said resistivity of said bipolar resistive change element.24. The semiconductor memory array of claim 21 , wherein said bipolar resistive change element is configured to a predetermined resistivity during said reset operation after said floating body is charged to a ...

RRAM MEMORY CELL WITH MULTIPLE FILAMENTS

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element over a substrate. The first RRAM element has a first terminal and a second terminal. A second RRAM element is arranged over the substrate and has a third terminal and a fourth terminal. The third terminal is electrically coupled to the first terminal of the first RRAM element. A reading circuit is coupled to the second terminal and the fourth terminal. The reading circuit is configured to read a single data state from both a first non-zero read current received from the first RRAM element and a second non-zero read current received from the second RRAM element. 1. An integrated chip , comprising:a first resistive random access memory (RRAM) element over a substrate, wherein the first RRAM element has a first terminal and a second terminal;a second RRAM element arranged over the substrate and having a third terminal and a fourth terminal, wherein the third terminal is electrically coupled to the first terminal of the first RRAM element; anda reading circuit coupled to the second terminal and the fourth terminal, wherein the reading circuit is configured to read a single data state from both a first non-zero read current received from the first RRAM element and a second non-zero read current received from the second RRAM element.2. The integrated chip of claim 1 , further comprising:a control device having a fifth terminal and a sixth terminal, the sixth terminal being coupled to the first terminal and the third terminal, wherein the first non-zero read current and the second non-zero read current are respectively proportional to a voltage applied to the fifth terminal of the control device.3. The integrated chip of claim 1 , wherein the first RRAM element comprises a data storage structure disposed between a bottom electrode and a top electrode claim 1 , the bottom electrode having a top surface that ...

METHOD FOR FORMING A FLAT BOTTOM ELECTRODE VIA (BEVA) TOP SURFACE FOR MEMORY

Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached. 1. An integrated circuit (IC) comprising:a first conductive feature;a memory cell overlying the first conductive feature; anda second conductive feature extending from the memory cell to the first conductive feature and comprising a lower conductive body, an upper conductive body, and a conductive liner, wherein the upper conductive body fully covers the lower conductive body when viewed in profile, and wherein the conductive liner extends along a bottom surface of the lower conductive body and individual sidewalls of the lower and upper conductive bodies.2. The IC according to claim 1 , wherein the first and second conductive features are respectively a wire and a via.3. The IC according to claim 1 , wherein the lower and upper conductive bodies are different materials.4. The IC according to claim 1 , wherein upper conductive body discretely increases in width at a top surface of the conductive liner.5. The IC according to claim 1 , wherein the via directly contacts the first conductive feature at an interface claim 1 , and wherein the via has a lesser width than the first conductive feature at the interface.6. The IC according ...

Method for manufacturing resistive random access memory structure

A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a bottom electrode layer over a substrate and forming a dielectric layer over the bottom electrode layer. The method for manufacturing a semiconductor structure further includes forming a top electrode layer over the dielectric layer and patterning the bottom electrode layer, the dielectric layer, and the top electrode layer to form a dielectric structure between a bottom electrode and a top electrode. The method for manufacturing a semiconductor structure further includes etching the bottom electrode from a sidewall of the bottom electrode to partially expose a bottom surface of the dielectric structure.

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction, a plurality of stacked films respectively provided between the first interconnects and the second interconnects, each of the plurality of stacked films including a variable resistance film, a first inter-layer insulating film provided in a first region between the stacked films, and a second inter-layer insulating film provided in a second region having a wider width than the first region. The second inter-layer insulating film includes a plurality of protrusions configured to support one portion of the plurality of second interconnects on the second region. A protruding length of the protrusions is less than a stacking height of the stacked films. 1forming a plurality of stacked films to extend in a first direction to be respectively stacked on a plurality of first interconnects extending in the first direction, each of the plurality of stacked films including a variable resistance film;forming a first inter-layer insulating film in a first region between the stacked films;forming a second inter-layer insulating film in a second region having a wider width than the first region;forming a plurality of second interconnects on the stacked films, on the first inter-layer insulating film, and on the second inter-layer insulating film to extend in a second direction crossing the first direction; andetching the stacked films and the first inter-layer insulating film under a space between the second interconnects,the second inter-layer insulating film under the space between the second interconnects being etched at an etching rate lower than an etching rate of the first inter-layer insulating film in the etching of the stacked films and the first inter-layer insulating film.. A method for manufacturing a semiconductor memory device, comprising: This application is a ...

RESISTANCE CHANGE MEMORY

A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectifying element connected in series between the first and second conductive lines, and a control circuit which is connected to both of the first and second conductive lines. The control circuit controls a voltage to change a resistance of the memory element between first and second values reversibly. The rectifying element is a diode including an anode layer, a cathode layer and an insulating layer therebetween. 1. (canceled)2. A resistance change memory comprising:a first conductive line extending in a first direction;a second conductive line extending in a second direction which is crossed to the first direction;a cell unit including a memory element and a rectifying element connected in series between the first and second conductive lines; anda control circuit which is connected to both of the first and second conductive lines,wherein the control circuit is configured to control a voltage to change a resistance of the memory element between first and second values reversibly,wherein the rectifying element is a diode including a first metal layer, a first insulating layer, a second insulating layer, a second metal layer,wherein the first insulating layer, and the second insulating layer are sandwiched between the first metal layer and the second metal layer, andwherein the first insulating layer is sandwiched between the first metal layer and the second insulating layer.3. The memory according to claim 2 , wherein barrier height of the first insulating layer differs from barrier height of the second insulating layer.4. The memory according to claim 3 , wherein the barrier height of the first insulating layer is higher than that of the second insulating layer.5. The memory according to claim 2 , wherein electron affinity of the ...

Using saturated and unsaturated ALD processes to deposit oxides as ReRAM switching layer

A nonvolatile memory device contains a resistive switching memory element with improved device switching performance and lifetime by custom tailoring the average concentration of defects in the resistive switching film and methods of forming the same. The nonvolatile memory element includes a first electrode layer, a second electrode layer, and a resistive switching layer disposed between the first electrode layer and the second electrode layer. The resistive switching layer comprises a first sub-layer and a second sub-layer, wherein the first sub-layer has more defects than the first sub-layer. A method includes forming a first sub-layer on the first electrode layer by a first ALD process and forming a second sub-layer on the first sub-layer by a second ALD process, where the first sub-layer has a different amount of defects than the second sub-layer. 1. A method of forming a resistive switching layer over a first electrode layer , the method comprising: 'wherein the first ALD process controls an average concentration of defects in the first sub-layer; and', 'forming a first sub-layer on the first electrode layer by a first ALD process,'} wherein the second ALD process controls an average concentration of defects in the second sub-layer, and', 'wherein the average concentration of defects in the first sub-layer is different than the average concentration of defects in the second sub-layer., 'forming a second sub-layer on the first sub-layer by a second ALD process'}2. The method of claim 1 , wherein the first sub-layer has a higher average concentration of defects than the second sub-layer.3. The method of claim 1 , wherein the second sub-layer has a higher average concentration of defects than the first sub-layer.4. The method of claim 1 , wherein the first ALD process and the second ALD process comprise at least one of the following combinations:a first combination wherein a selected one of the first and the second ALD process is a saturated ALD process and the ...

Controlling ReRam Forming Voltage with Doping

An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode. 1. A resistive memory device comprisinga first electrode having a first work function; 'wherein the first work function is different from the second work function;', 'a second electrode having a second work function,'} wherein the dielectric layer is disposed between the first and second electrodes,', 'wherein the dielectric layer is operable as a switching layer,', 'wherein the dielectric layer comprises at least one charged layer., 'a dielectric layer,'}2. A resistive memory device as in wherein the work function difference between the first and second electrode is greater than 1 eV.3. A resistive memory device as in wherein the at least one charged layer comprises two adjacent charged layers of opposite polarities to form a dipole layer.4. A resistive memory device as in wherein the two adjacent charged layers are immediately next to each other.5. A resistive memory device as in wherein the separation between the two adjacent charges layers is between 0.3 and 3 nm.6. A resistive memory device as inwherein the at least one charged layer comprises elements having lower valence than that of a metal element of the dielectric layer, and wherein the elements having lower valence than that of a metal element of the dielectric layer can substitute on the metal element site;wherein the at least one charged layer comprises elements ...

Resistive Switching Random Access Memory with Asymmetric Source and Drain

A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain has a zero-tilt doping profile and the source has a tilted doping profile. The resistive memory element is coupled with the drain via a portion of an interconnect structure. 1. A resistive random access memory (RRAM) structure , comprising: a top electrode;', 'a bottom electrode; and', 'a resistive material layer positioned between the top electrode and the bottom electrode; and, 'a resistive memory element formed on a semiconductor substrate, wherein the resistive element includesa field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain, wherein the drain has a zero-tilt doping profile and the source has a tilted doping profile;wherein the resistive memory element is coupled with the drain via a portion of an interconnect structure.2. The RRAM structure of claim 1 , wherein the source and drain are designed asymmetrically such that a voltage drop over the FET during a forming operation and an off-state leakage current are collectively optimized.3. The RRAM structure of claim 1 , wherein the FET further includes:a channel region formed in the semiconductor substrate; anda gate vertically disposed over the channel region and horizontally interposed between the source and drain,wherein the source and drain of the FET further include light doped drain (LDD) source and drain features that are asymmetric.4. The RRAM structure of claim 3 , wherein:the LDD source feature has a first doping concentration; andthe LDD drain feature has a second doping concentration different from the first doping ...

Resistance memory device and memory apparatus and data processing system

A resistance memory device and a memory apparatus and data processing apparatus having the same are provided. The resistance memory device includes a pair of electrode layers and a variable resistance layer interposed between the pair of electrode layers. The variable resistance layer includes at least one variable resistance material layer and a piezoelectric material layer coupled to the at least one variable resistance material layer.

ACCESS DEVICES TO CORRELATED ELECTRON SWITCH

Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices. 1. A device comprising:one or more first layers comprising a metallic oxide comprising a correlated electron switch (CES);one or more terminals; andone or more second layers formed between a first terminal of the one or more terminals and the one or more first layers to form a first access device to the CES, the first access device comprising a metal-insulator-metal (MIM) diode, a tunnel diode or a varistor, or a combination thereof.2. (canceled)3. The device of claim 1 , wherein at least one of the one or more second layers comprises zinc oxide doped with bismuth.4. The device of claim 1 , wherein the device comprises a correlated electron random access memory (CeRAM) element in a crosspoint memory array.5. The device of claim 1 , wherein the one or more first layers and the one or more second layers are formed from a correlated electron material (CEM) claim 1 , and wherein at least one of the one or more first layers is p-type doped claim 1 , wherein the CES comprises a bulk switch in which a majority of material forming the CES is switchable from an insulative/higher impedance state to a conductive/lower impedance state claim 1 , or from a conductive/lower impedance state to an insulative/higher impedance state.6. The device of claim 5 , wherein at least one of the one or more second metallic oxide layers is n-type doped.7. The device of claim 5 , wherein at least one of the one or more second metallic oxide layers comprises the CEM in an intrinsic state.8. The device of claim 1 , and further comprising one or more third layers formed between a second terminal of the one or more terminals and the one or more first layers to form a second access device to the CES.9. The device of claim 8 , wherein the one or more first metal oxide layers are separated from the one or more second metallic oxide layers by a first metallic layer claim 8 , and wherein the ...

Correlated electron material devices using dopant species diffused from nearby structures

Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, a correlated electron material may be doped using dopant species derived from one or more precursors utilized to fabricate nearby structures such as, for example, a conductive substrate or a conductive overlay.

Vertical bjt for high density memory

Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled to a source line of the memory device. A base region is formed over the collector region and has a second conductivity type. A gate structure is coupled to the base region and acts as a shared word line for first and second neighboring memory cells of the memory device. First and second emitter regions are formed over the base region and have the first conductivity type. The first and second emitter regions are arranged on opposite sides of the gate structure. First and second contacts extend upwardly from the first and second emitter regions, respectively, and couple the first and second emitter regions to first and second data storage elements, respectively, of the first and second neighboring memory cells, respectively.

METHODS AND RELATED DEVICES FOR OPERATING A MEMORY ARRAY

Methods of operating memory arrays, as well as the memory arrays, are described. In various embodiments, a method includes determining a pattern to be written to a memory array, the pattern comprising both data bits having sensitive information to be stored and data bits having a state that is unimportant to the sensitive information to be stored, and writing the pattern to the memory array. Other methods of operation and memory devices are also described. 1. A method of operating a memory array , the method comprising:determining a pattern to be written to the memory array, the pattern comprising both data bits having sensitive information to be stored and data bits having a state that is unimportant to the sensitive information to be stored; andwriting the pattern to the memory array.2. The method of claim 1 , wherein the data bits having a state that is unimportant to the sensitive information to be stored are incorporated inside a same logic packet as the data bits having sensitive information to be stored.3. The method of claim 2 , wherein the logic packets are selected from at least one packet type including packet types of nibbles claim 2 , bytes claim 2 , words claim 2 , double words claim 2 , and long words.4. The method of claim 1 , further comprising defining a starting condition for each cell in the memory array prior to storing a plurality of bits in the memory array claim 1 , the starting condition being defined by providing either one or more hard reset pulses or one or more soft reset pulses to each of the cells in the memory array.5. The method of claim 4 , further comprising programming the one or more hard reset pulses with a first pulse amplitude claim 4 , and programming the one or more soft reset pulses with a second pulse amplitude that is different from the first pulse amplitude.6. The method of claim 4 , further comprising:writing a logical “0” using the one or more hard reset pulses to one or more selected cells in the memory array; ...

PROTUBERANT CONTACTS FOR RESISTIVE SWITCHING DEVICES

Embodiments of the invention provide a method of forming a crossbar array. The method includes forming conductive row electrode lines and forming conductive column electrode lines. The conductive column electrode lines form a plurality of crosspoints at intersections between the conductive row electrode lines and the conductive column electrode lines. An RSD is formed at each of the plurality of crosspoints, wherein the RSD includes a first terminal, a second terminal, an active region having a switchable conduction state, and a protuberant contact communicatively coupled to the first terminal. The protuberant contact communicatively couples the first terminal through a first barrier liner to a first one of the conductive row electrode lines. The protuberant contact can be positioned with respect to the first barrier liner such that the first barrier liner does not impact the switchable conduction state of the active region. 1. A method of forming a crossbar array , the method comprising:forming a set of conductive row electrode lines;forming a set of conductive column electrode lines configured to form a plurality of crosspoints at intersections between the set of conductive row electrode lines and the set of conductive column electrode lines;forming a resistive switching device (RSD) at each of the plurality of crosspoints; a first terminal;', 'a second terminal;', 'an active region having a switchable conduction state; and', 'a protuberant contact communicatively coupled to the first terminal; and, 'wherein the RSD comprisesconfiguring the protuberant contact to communicatively couple the first terminal through a first barrier liner to a first one of the set of conductive row electrode lines.2. The method of further comprising positioning the protuberant contact with respect to the first barrier liner such that the first barrier liner does not impact the switchable conduction state of the active region.3. The method of further comprising positioning the ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M<2×N×k is satisfied. 1. (canceled)2. A semiconductor memory device , comprising:a substrate:a first wiring extending in a first direction parallel to a surface of the substrate;a second wiring being apart from the first wiring in a second direction crossing the first direction, the second wiring extending in the first direction;a third wiring being provided between the first wiring and the second wiring, the third wiring extending in a third direction crossing in the first and the second directions;a fourth wiring being apart from the third wiring in the second direction, the fourth wiring extending in the third direction:a first memory cell being provided between the first wiring and the third wiring;a second memory cell being provided between the second wiring and the third wiring;a third memory cell being provided between the second wiring and the fourth wiring;a fifth wiring being connected to the third wiring and extending in the second direction;a sixth wiring being connected to the fourth wiring and extending in the second direction; anda circuit including a first decoder and a second decoder, the first decoder being connected to the fifth wiring and the sixth wiring, the second decoder being connected to the first wiring, ...

MULTI-TIME PROGRAMMABLE DEVICE

Devices and methods for forming a device are presented. The device includes a substrate having a device region and first and second isolation regions surrounding the device region. The device includes a multi-time programmable (MTP) memory cell having a single transistor disposed on the device region. The transistor includes a gate having a gate electrode over a gate dielectric which includes a programmable resistive layer. The gate dielectric is disposed over a channel region having first and second sub-regions in the substrate. The gate dielectric disposed above the first and second sub-regions has different characteristics such that when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming relative to portion of the programmable resistive above the other first or second sub-region. 1. A memory device comprising:a substrate comprising a device region and first and second isolation regions surrounding the device region; and a gate having a gate electrode disposed on a programmable resistive layer, wherein the gate electrode covers an entire top surface of the programmable resistive layer, the programmable resistive layer is disposed over a transistor channel region having first and second channel sub-regions in the device region, wherein a first portion of the programmable resistive layer overlaps the first channel sub-region and a second portion of the programmable resistive layer overlaps the second channel sub-region,', 'wherein the first portion of the programmable resistive layer directly contacts a top surface of the substrate, and', 'wherein the second portion of the programmable resistive layer is more susceptible for programming relative to the first portion of the programmable resistive layer., 'a multi-time programmable (MTP) memory cell having a single transistor, wherein the transistor includes'}2. The memory device of comprising a buffer layer ...

SEMICONDUCTOR DEVICES AND RELATED METHODS

Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nmover and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts. 1. A semiconductor device , comprising:electrodes in a dielectric material;electrical contacts over and electrically coupled to respective electrodes, each of the electrical contacts comprising a conductive material;at least one volume of a first dielectric material adjacent to and in contact with respective electrical contacts; andat least one volume of a second dielectric material different from the first dielectric material, adjacent to and in contact with the respective electrical contacts; andat least one volume of a cell material over and electrically coupled to respective electrical contacts.2. The semiconductor device of claim 1 , further comprising other electrodes formed over and electrically coupled to the at least one volume of the cell material.3. The semiconductor device of claim 1 , further comprising a substrate comprising a semiconductor material and access devices claim 1 , wherein the electrodes are located over the substrate and are electrically coupled to respective access ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction, a plurality of stacked films respectively provided between the first interconnects and the second interconnects, each of the plurality of stacked films including a variable resistance film, a first inter-layer insulating film provided in a first region between the stacked films, and a second inter-layer insulating film provided in a second region having a wider width than the first region. The second inter-layer insulating film includes a plurality of protrusions configured to support one portion of the plurality of second interconnects on the second region. A protruding length of the protrusions is less than a stacking height of the stacked films. 1. (canceled)2. A semiconductor memory device , comprising:a plurality of first interconnects extending in a first direction, the first interconnects arranged in a second direction crossing to the first direction;a plurality of second interconnects extending in the second direction, the second interconnects arranged in the first direction;a first layer being provided on at least one of the first interconnects, the first layer including metal material, the first layer extending in the first direction;a plurality of stacked films respectively provided between the first interconnects and the second interconnects in a third direction crossing to the first direction and the second direction, the plurality of stacked films respectively including a variable resistance film, the stacked films arranged in the first direction and the second direction;a first insulating film being provided between one of the stacked films and another one of the stacked films in the first direction, the first insulating film extending at least in the third direction, the one of the stacked films and the another one of the stacked films being provided ...

Memory Cells

Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state. 128-. (canceled)29. A memory cell , comprising:a switching region located between a pair of electrodes and comprising a first discrete portion and a second discrete portion, with the first discrete portion having a thickness within a range of from greater than 0 angstroms to less than or equal to about 20 angstroms and not having a non-oxygen component in common with any composition directly against the first discrete portion in a high resistive state of the memory cell, at least one of the first and second discrete portions being formed by atomic layer deposition which provides enhanced switchability and retention of the cell.30. The memory cell of wherein one of first and second discrete portions is thicker than the other.31. The memory cell of wherein one of the first and second discrete portions of the switching region comprises one or more of aluminum claim 29 , hafnium claim 29 , silicon claim 29 , titanium and zirconium.32. The memory cell of wherein one of the first and second discrete portions of the switching region has a thickness of less than one monolayer.33. The memory cell of wherein:the first discrete portion consists of ...

Methods for Resistive Random Access Memory (RRAM)

Methods for a resistive random access memory (RRAM) device are disclosed. A bottom electrode is formed over a substrate. A top electrode is formed over the bottom electrode. A resistive switching layer is formed interposed between the top electrode and the bottom electrode. The resistive switching is made of a composite of a metal, Si, and O, formed by oxidation of a metal silicide of a metal, co-deposition of the metal and silicon in oxygen ambiance, co-deposition of a metal oxide of the metal and silicon, or co-deposition of a metal oxide of the metal and silicon oxide. There may be an additional tunnel barrier layer between the top electrode and the bottom electrode. The top electrode and the bottom electrode may comprise multiple sub-layers. 1. A method for fabricating a resistive random access memory (RRAM) , comprising:forming a bottom electrode on a substrate; oxidation of a metal silicide of a metal,', 'co-deposition of the metal and silicon in oxygen ambiance,', 'co-deposition of a metal oxide of the metal and silicon, or', 'co-deposition of a metal oxide of the metal and silicon oxide, wherein the resistive switching layer is made of a composite of a metal, Si, and O; and, 'forming a resistive switching layer over the bottom electrode by a process comprisingforming a top electrode over the resistive switching layer.2. The method of claim 1 , further comprising claim 1 , before forming the top electrode claim 1 , forming a continuous tunnel barrier layer over the bottom electrode.3. The method of claim 1 , wherein the metal in the resistive switching layer comprises a material selected from a group consisting essentially of W claim 1 , Ta claim 1 , Ti claim 1 , Ni claim 1 , Co claim 1 , Hf claim 1 , Ru claim 1 , Zr claim 1 , Zn claim 1 , Fe claim 1 , Sn claim 1 , Al claim 1 , Cu claim 1 , Ag claim 1 , Mo claim 1 , Cr claim 1 , or combinations thereof.4. The method of claim 1 , wherein the bottom electrode comprises a material claim 1 , selected from a group ...

MEMORY CELL WITH INDEPENDENTLY-SIZED ELEMENTS

Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element. 1. A memory cell comprising:a memory element in series with a chalcogenide switch element, wherein the memory element comprises etched sidewalls;a first electrode between and in physical contact with the chalcogenide switch element and the memory element, wherein the first electrode comprises etched sidewalls; andwherein the sidewalls of the chalcogenide switch element are etched such that a smallest lateral dimension between the etched sidewalls of the chalcogenide switch element is less than a smallest lateral dimension between the etched sidewalls of the first electrode.2. The memory cell of claim 1 , wherein the sidewalls of the chalcogenide switch element are etched such that the smallest lateral dimension between the etched sidewalls of the chalcogenide switch element is greater than a smallest lateral dimension between the etched sidewalls of the memory element.3. The memory cell of claim 1 , the memory cell further comprising a second electrode in physical contact with the memory element claim 1 , wherein the sidewalls of the second electrode are etched.4. The memory cell of claim 1 , the memory cell further comprising a third electrode between and in physical contact with the chalcogenide switch element and a word line claim 1 , wherein the sidewalls of the third electrode are etched.5. The memory cell of claim 1 , wherein the sidewalls of the chalcogenide switch element are etched such that the smallest lateral dimension between the etched sidewalls of the chalcogenide switch element is less than a smallest lateral dimension between the etched sidewalls of the second electrode and less than a smallest lateral dimension between the etched sidewalls of the ...