ЭЛЕКТРОННОЕ ПЕРЕКЛЮЧАЮЩЕЕ УСТРОЙСТВО И СПОСОБ ИЗГОТОВЛЕНИЯ ЭТОГО УСТРОЙСТВА

Изобретение относится к электронным переключающим устройствам. Сущность изобретения: электронное переключающее устройство содержит электроды истока и стока, полупроводниковую структуру, обеспечивающую полупроводниковый канал между электродами истока и стока, и электрод затвора, отделенный от полупроводниковой структуры структурой диэлектрика затвора, причем структура диэлектрика затвора включает первый, неконформный полимерный диэлектрический слой, расположенный в контакте с полупроводниковой структурой, и второй, конформный диэлектрический слой, расположенный между первым диэлектрическим слоем и электродом затвора. Изобретение обеспечивает снижение дефектов тонкопленочных транзисторных структур из-за короткого замыкания через диэлектрик затвора. 2 н. и 7 з.п. ф-лы, 4 ил.

СПОСОБ ИСПОЛЬЗОВАНИЯ ЦЕЛЛЮЛОЗНОГО НАТУРАЛЬНОГО, СИНТЕТИЧЕСКОГО ИЛИ СМЕШАННОГО МАТЕРИАЛА В КАЧЕСТВЕ ОДНОВРЕМЕННО НЕСУЩЕГО И ДИЭЛЕКТРИЧЕСКОГО ОСНОВАНИЯ В САМОСТОЯТЕЛЬНЫХ ЭЛЕКТРОННЫХ И ОПТОЭЛЕКТРОННЫХ УСТРОЙСТВАХ С ПОЛЕВЫМ ЭФФЕКТОМ

... 1. Способ изготовления электронного или оптоэлектронного устройства с полевым эффектом, отличающийся тем, что натуральные, синтетические или смешанные волокна соединяют в слои, соединяемые в тонкую пленку (2), используемую в указанном устройстве одновременно в качестве несущего основания и диэлектрика (2), чем обеспечивается самостоятельность указанного устройства. ! 2. Способ по предыдущему пункту, отличающийся тем, что волокна, слои или волокна и слои соединяют между собой посредством клеящего вещества, способного модифицировать электроотрицательность и ионность. ! 3. Способ по п.1 или 2, отличающийся тем, что дополнительно наносят активные полупроводники толщиной в 10-100 раз меньше толщины указанных волокон. ! 4. Способ по п.1 или 2, отличающийся тем, что указанные слои волокон механически сжимают с получением способности накапливать электрические и ионные заряды на единицу площади, зависящей от характера распределения волокон, их взаимосвязи и соединения в различных механически сжатых ...

ДИЭЛЕКТРИЧЕСКИЙ СЛОЙ ЗАТВОРА ДЛЯ ЭЛЕКТРОННЫХ УСТРОЙСТВ

... 1. Диэлектрический слой затвора, находящийся в контакте с полупроводниковым слоем в электронном устройстве, где указанный диэлектрический слой затвора включает полициклоолефиновый полимер или полимерную композицию, содержащую полициклоолефиновый полимер.2. Диэлектрический слой затвора по п. 1, в котором полициклоолефиновый полимер является полимером норборненового типа.3. Диэлектрический слой затвора по п. 1, в котором полициклоолефиновый полимер содержит первый тип повторяющейся единицы, имеющей боковую, способную к сшиванию группу.4. Диэлектрический слой затвора по п. 3, в котором боковая, способная к сшиванию группа является латентной, способной к сшиванию группой.5. Диэлектрический слой затвора по п. 3, в котором боковая, способная к сшиванию группа является малеимидной, 3-моноалкилмалеимидной, 3,4-диалкилмалеимидной, эпоксидной, винильной, ацетильной, инденильной, циннаматной или кумариновой группой, или боковая способная к сшиванию группа содержит замещенный или незамещенный малеимидный ...

MANUFACTURING PROCESS FOR AN ORGANIC ELECTRONIC CONSTRUCTION UNIT WITH HIGH-DISSOLVED STRUCTURING

Procedure for the use of natural cellulosic material, synthetic material or mixed natural and synthetic material, simultaneously as physical and dielectric support in self-sustainable field effect electronic and optoelectronic devices

SOLUTION PROCESSING

... ²²²A method for forming on a substrate an electronic device including an ²electrically conductive or semiconductive material in a plurality of regions, ²the operation of the device utilising current flow from a first region to a ²second region, the method comprising: forming a mixture by mixing the material ²with a liquid; forming on the substrate a confinement structure including a ²first zone in a first area of the substrate and a second zone in a second area ²of the substrate, the first zone having a greater repellence for the mixture ²than the second zone, and a third zone in a third area of the substrate spaced ²from the second area by the first area, the first zone having a greater ²repellence for the mixture than the third zone, and depositing the material on ²the substrate by applying the mixture over the substrate whereby the deposited ²material may be confined by the relative repellence of the first zone to ²spaced apart regions defining the said first and second regions of the ...

SOLUTION PROCESSING

A method for forming on a substrate an electronic device including an electrically conductive or semiconductive material in a plurality of regions, the operation of the device utilising current flow from a first region to a second region, the method comprising: forming a mixture by mixing the material with a liquid; forming on the substrate a confinement structure including a first zone in a first area of the substrate and a second zone in a second area of the substrate, the first zone having a greater repellence for the mixture than the second zone, and a third zone in a third area of the substrate spaced from the second area by the first area, the first zone having a greater repellence for the mixture than the third zone, and depositing the material on the substrate by applying the mixture over the substrate whereby the deposited material may be confined by the relative repellence of the first zone to spaced apart regions defining the said first and second regions of the device and being ...

CELLULOSES AND DEVICES THEREOF

... ²²²² An electronic device including a dielectric layer including a cellulose ²derivative is disclosed.² ...

JUNCTION FIELD EFFECT TRANSISTORS ON PAPER-BASED SUBSTRATE WITH MEMORY AND PROCESS FOR MAKING THEREOF

The present invention refers to the use and creation of materials based on natural cellulose fibbers, synthetic fibbers, or mixed fibbers as physical support and storing medium or storage inducer of electrical and ionic charges in self-sustaining discrete or complementary field-effect transistors with non-volatile memory by using organic or inorganic active semiconductors for the manufacture of the channel regions that are deposited on the fibbers of the paper material as well as metals or passive semiconductors for manufacturing drain and source allowing the interconnection of fibbers, in addition to the gate electrode contact existing on the other side-face of the paper, p or n type respectively, in monolithic or hybrid forms.

DIELECTRIC COMPOSITION FOR THIN-FILM TRANSISTORS

An electronic device, such as a thin-film transistor, includes a substrate and a dielectric layer formed from a dielectric composition. The dielectric composition includes a dielectric material, a crosslinking agent, and an infrared absorbing agent. In particular embodiments, the dielectric material comprises a lower-k dielectric material and a higher-k dielectric polymer. When deposited, the lower-k dielectric material and the higher-k dielectric material form separate phases. The infrared absorbing agent allows the dielectric composition to attain a temperature that is significantly greater than the temperature attained by the substrate during curing. This difference in temperature allows the dielectric layer to be cured at relatively high temperatures and/or shorter time periods, permitting the selection of lower- cost substrate materials that would otherwise be deformed by the curing of the dielectric layer.

ELECTRONIC DEVICES COMPRISING STRUCTURED ORGANIC FILMS

An electronic device comprising a structured organic film with an added functionality comprising a plurality of segments and a plurality of linkers arranged as a covalent organic framework, wherein the structured organic film may be multi-segment think structured organic film.

PROCESS FOR PREPARING STRUCTURED ORGANIC FILMS (SOFS) VIA A PRE-SOF

A process for preparing structured organic film (SOF) comprising a plurality of segments and plurality of linkers arranged as a covalent organic framework, wherein the structured organic film may be multi-segment think structured organic film by reaction of pre-SOF.

PROCESS FOR PREPARING STRUCTURED ORGANIC FILMS (SOFS) VIA A PRE-SOF

A process for preparing structured organic film (SOF) comprising a plurality of segments and plurality of linkers arranged as a covalent organic framework, wherein the structured organic film may be multi-segment think structured organic film by reaction of pre-SOF.

Active matrix display device.

Le dispositif daffichage (1) est à matrice active. Il comprend un substrat inférieur (2), un substrat supérieur transparent (3), un cadre de scellement des substrats définissant une cavité fermée pour une substance (7) dont les propriétés optiques changent en présence dun champ électrique. Une électrode unique transparente (4) est disposée sur une face intérieure du substrat supérieur, alors quune face intérieure du substrat inférieur porte une matrice délectrodes (11). Les électrodes de la matrice sont disposées en rangées et en colonnes en étant commandées chacune par un transistor à couches minces respectif (T). Le drain (11) de chaque transistor est relié à lélectrode correspondante. Les grilles (12) des transistors sont reliées dans chaque colonne de la matrice par une piste conductrice de commande respective, alors que les sources des transistors étant reliées dans chaque rangée de la matrice par une piste conductrice de données respective. Des première et seconde couches dalignement ...

Procedure for the use of natural cellulosic material, synthetic material or mixed natural and synthetic material, simultaneously as physical and dielectric support in self-sustainable field effect electronic and optoelectronic devices

Embodiments of the present disclosure provide for the use and creation of natural cellulosic material, synthetic or mixed fibers hereafter designated as paper and the corresponding production process to be used simultaneously as physical and dielectric support in the creation of new field effect electronic or optoelectronic devices, called C- MOS structured electronic devices, whose paper electronic is now on called interstrate in which its functionality depends on the electrical charge capacity per unit area of the paper to accumulate electronic and ionic charges, function of how the forming fibers are distribute and compacted along the paper surface and thickness, as well as how the upmost surface close fibers are coated by an active ionic or covalent semiconductor and allowing the production of flexible self sustained devices, disposable devices, based on the new interstrate integrated concept, of monolithic or hybrid types.

Composition for forming gate dielectric film of thin film transistor

Insulating layer, electronic device, field effect transistor, and polyvinylthiophenol

The invention provides an insulting layer which enables to improve device characteristics when used in an electronic device. A polymer insulator containing a repeating unit represented by the formula below is contained in the insulating layer. In the formula, R represents a direct bond or an arbitrary linking group; Ar represents an optionally substituted divalent aromatic group; and R represents a hydrogen atom, a fluorine atom or a monovalent organic group.

REDUCTION IN the EFFECTS OF CAPS DUE TO the LASER ABLATION Of a METAL LEVEL PER USE Of a LAYER OF POLYMER PHOTOOU THERMO-RETICULABLE NOT RETICLE

METHOD FOR PREPARING A CROSSLINKED FLUORINE-CONTAINING POLYMER FILM

Thin-Layer Chemical Transistor and Making Method

Composite structured organic films

... 본 발명은 공유 유기 골격체로서 배열된 다수의 세그먼트와 다수의 링커를 포함하는, 추가 기능을 갖는 구조화 유기 필름에 관한 것이며, 여기서, 상기 구조화 유기 필름은 멀티-세그먼트 두께의 구조화 유기 필름일 수 있다.

앰비언트-로버스트 용액을 이용한 나노단위 유기적 강유전체 막의 제조방법

... 본 발명의 강유전체 히스테리시스 특성을 갖는 강유전체 막을 제조하는 방법은, (a) 용매 및 상기 용매에 용해된 유기적 강유전체 폴리머를 포함하는 조성물을 수득하는 단계; (b) 상기 조성물을 75 ℃ 초과 내지 상기 용매의 끓는점 이하의 온도로 가열하는 단계; (c) 상기 가열한 조성물을 기판 상에 증착하는 단계; (d) 상기 가열한 조성물을 어닐링하여 강유전체 히스테리시스 특성을 가지며, 두께가 400nm 이하인 강유전체 막을 제조하는 단계;를 포함한다.

POLYMERIC GATE DIELECTRICS FOR THIN FILM TRANSISTORS

A thin film transistor comprises a layer of organic semiconductor material and spaced apart first and second contact means or electrodes in contact with said material. A multilayer dielectric comprises a first dielectric layer having a thickness of 200 nm to 500 nm, in contact with the gate electrode and a second dielectric layer in contact with the organic semiconductor material, and wherein the first dielectric layer comprise a continuous first polymeric material having a relatively higher dielectric constant less than 10 and the second dielectric layer comprises a continuous second non-fluorinated polymeric material having a relatively lower dielectric constant greater than 2.3. Further disclosed is a process for fabricating such a thin film transistor device, preferably by sublimation or solution-phase deposition onto a substrate, wherein the substrate temperature is no more than 100°C. © KIPO & WIPO 2008 ...

PERFLUOROALKYLENEOXY GROUP SUBSTITUTED PHENYLETHYLSILANE COMPOUND WITH EXCELLENT THERMAL AND CHEMICAL STABILITIES, A PERFLUORO-POLYMER PREPARED BY POLYMERIZING THE SAME AND AN ORGANIC THIN FILM TRANSISTOR COMPRISING AN INSULATION LAYER PREPARED FROM THE POLYMER

PURPOSE: A novel phenylethylsilane compound is provided to show excellent thermal and chemical stabilities, thereby being capable of being subject to a solution process. A perfluoro-polymer prepared by thermal polymerization of the novel compound is provided to show excellent resistance to an organic solvent. An insulation film obtained from the polymer is provided to show improved thermal and physical characteristics, thereby being applied to an organic thin film transistor with excellent on off ratio. CONSTITUTION: A phenylethylsilane compound where a perfluoroalkyleneoxy group is substituted is represented by the formula(1), wherein R1, R2 and R3 are same or different from each other and are selected from the group consisting of H, F, C1-4 alkyl, and one to six fluorine atom(s) substituted C1-4 fluoroalkyl, provided that at least one of the R1, R2 and R3 is F or fluoroalkyl; Z1, Z2 and Z3 are same or different from each other and are selected from the group consisting of H and C1-4 alkyl ...

OTFT using paper as substrate and silk protein as dielectric material and method for manufacturing the same

An organic thin film transistor (OTFT) using paper as a substrate and silk protein as a dielectric material and methods for manufacturing the same are disclosed. The OTFT of the present invention comprises: a paper substrate; a gate disposed on the paper substrate; a gate insulating layer containing silk protein, which is disposed on the paper substrate and covers the gate; an organic semiconductor layer; and a source and a drain, wherein the organic semiconductor layer, the source and the drain are disposed over the gate insulating layer.

Organic thin film transistor and manufacturing method thereof

An organic thin film transistor and a manufacturing method thereof are provided. The organic thin film transistor includes, on a substrate, a gate electrode, an organic semiconductor layer, a gate insulating layer, a source electrode and a drain electrode, wherein the organic semiconductor layer includes an organic semiconductor, and a resin (C) having one or more groups selected from a group consisting of a group having a fluorine atom, a group having a silicon atom, an alkyl group having one or more carbons (or an alkoxycarbonyl group having two or more carbons), a cycloalkyl group, an aralkyl group, an aryloxy carbonyl group, an aromatic ring group substituted with at least one alkyl group, and an aromatic ring group substituted with at least one cycloalkyl group. The manufacturing method of the organic thin film transistor coats a coating liquid containing the organic semiconductor and the resin (C) so as to unevenly distribute the resin (C).

Ether-based polymers as photo-crosslinkable dielectrics

The present invention provides polymers comprising at least one unit of formula wherein n is 0 or 1, m and p are independently from each other 0, 1, 2, 3, 4, 5 or 6, provided that the sum of n, m and p is at least 2, and n and p are not 0 at the same time, Ar1 and Ar2 are independently from each other C6-14-arylene or C6-14-aryl, which may be substituted with 1 to 4 substituents independently selected from the group consisting of C1-30-alkyl, C2-30-alkenyl, C2-30-alkynyl, C5-8-cycloalkyl, C6-14-aryl and 5 to 14 membered heteroaryl, and X1, X2 and X3 are independently from each other and at each occurrence O or S, compositions comprising these polymers, and electronic devices comprising a layer formed from the compositions. Preferably, the electronic device is an organic field effect transistor and the layer is the dielectric layer.

Mononuclear star-branched polymer dielectric material and organic thin film transistor

PROCESS FOR PREPARING STRUCTURED ORGANIC FILMS (SOFS) VIA A PRE-SOF

A process for preparing structured organic film (SOF) comprising a plurality of segments and plurality of linkers arranged as a covalent organic framework, wherein the structured organic film may be multi-segment think structured organic film by reaction of pre-SOF.

POLYIMIDES AS DIELECTRIC

The present invention provides a process for the preparation of a transistor on a substrate, which transistor comprises a layer, which layer comprises polyimide B, which process comprises the steps of i) forming a layer comprising photocurable polyimide A by applying photocur- able polyimide A on a layer of the transistor or on the substrate ii) irradiating the layer comprising photocurable polyimide A with light of a wavelength of > = 360 nm in order to form the layer comprising polyimide B, and a transistor obtainable by that process.

ORGANIC THIN FILM TRANSISTORS

A method of forming an organic thin film transistor comprising: providing a structure comprising source (2) and drain (4) electrodes with a channel region therebetween, a gate electrode (1), and a dielectric layer (10) disposed between the source (2) and drain (4) electrodes and the gate electrode (1); and patterning the dielectric layer (10) using the source (2) and drain (4) electrodes as a mask to form a region of dielectric material in the channel region which is thinner than regions of dielectric material adjacent the channel region.

ORGANIC SEMICONDUCTOR MATERIAL

The present invention relates to a novel compounds useful as organic semiconductor material, and semiconductor devices containing said organic semiconductor material.

FIELD EFFECT TRANSISTOR USING ORGANIC SEMICONDUCTOR MATERIAL AND METHOD FOR MANUFACTURING THE SAME

Disclosed is a field effect transistor comprising a semiconductor layer (14) containing an organic semiconductor material, a gate electrode (12), and a gate insulating film arranged between the semiconductor layer (14) and the gate electrode (12). The gate insulating film contains an organic insulating film (13) exhibiting spontaneous polarization. Also disclosed is a method for manufacturing a field effect transistor, which comprises a step for forming a gate insulating film which contains an organic insulating film exhibiting spontaneous polarization.

ELECTRONIC DEVICES

A method for forming an electronic device in a multilayer structure comprising the steps of: defining a topographic profile in a laterally extending first layer; depositing at least one non-planarizing layer on top of the first layer such that the topographic profile of the surface of the or each non-planarizing layer conforms to that of the laterally extending first layer; and depositing a pattern of at least one additional layer onto the top-most non-planarizing layer, such that the lateral location of the additional layer is defined by the shape of the topographic profile of the non-planarizing layer, and whereby the additional layer is laterally aligned with the topographic profile in the first layer.

ELECTRONIC DEVICES

An electronic device including at least first and second transistors integrated together on a substrate and each including an organic semiconductor region, wherein the first and second transistors are either both n-type or both p-type but wherein one of the first and second transistors is a normally-ON transistor and the other of the first and second transistors is a normally-OFF transistor.

INKJET-FABRICATED INTEGRATED CIRCUITS

A method for forming an integrated circuit including at least two interconnected electronic switching devices, the method comprising forming at least part of the electronic switching devices by ink-jet printing.

TRANSISTOR MANUFACTURING METHOD AND TRANSISTOR

A transistor manufacturing method includes: forming a first insulator layer of which formation material is a fluorine-containing resin, on a substrate having a source electrode, a drain electrode, and a semiconductor layer so as to cover the semiconductor layer; forming a second insulator layer to cover the first insulator layer; forming a base film on at least part of a surface of the second insulator layer; and after depositing a metal which is an electroless plating catalyst on a surface of the base film, forming a gate electrode on the surface of the base film by electroless plating, wherein the forming of the base film is performed by applying a liquid substance which is a formation material of the base film to the surface of the second insulator layer, and the second insulator layer has a higher lyophilic property with respect to the liquid substance than the first insulator layer.

Resin and photosensitive resin composition

A resin and a photosensitive resin composition whereby a cured film exhibiting high extensibility, reduced stress, and high adhesion to metals can be obtained are provided. A resin (A) including a polyamide structure and at least any structure of an imide precursor structure and an imide structure, wherein at least any of the structures of the resin (A) include a diamine residue having an aliphatic group.

Field-effect transistor and method for manufacturing the same

A field-effect transistor includes a semiconductor layer containing carbon nanomaterials; a first electrode and a second electrode formed in contact with the semiconductor layer; a third electrode for controlling current flowing between the first electrode and the second electrode; and an insulating layer formed between the semiconductor layer and the third electrode. The insulating layer contains an aromatic polyamide comprising a substituent containing 1 to 20 carbon atoms.

COMPOSITION FOR FORMING GATE INSULATING FILM, ORGANIC THIN FILM TRANSISTOR, ELECTRONIC PAPER, AND DISPLAY DEVICE

The present invention provides a composition for forming a gate insulating film, which improves the insulation reliability of an organic thin film transistor without greatly reducing the mobility of the organic thin film transistor, an organic thin film transistor, electronic paper, and a display device. The composition for forming a gate insulating film of the present invention contains an insulating material and a migration inhibitor selected from the group consisting of a compound represented by any of Formulae (1) to (8), a polymer compound (X) containing a repeating unit represented by Formula (A), and a polymer compound (Y) containing a repeating unit represented by Formula (B) and a repeating unit represented by Formula (C). 7. The composition for forming a gate insulating film according to claim 1 ,wherein the migration inhibitor is the polymer compound (Y) containing a repeating unit represented by Formula (B) and a repeating unit represented by Formula (C).8. The composition for forming a gate insulating film according to .wherein in the repeating unit represented by Formula (B), B represents a monovalent group, which is formed as a result of removing one hydrogen atom (here, a hydrogen atom of a hydroxyl group is excluded) from the compound represented by Formula (Y-1) or the compound represented by Formula (Y-6), or the group represented by Formula (25).10. The composition for forming a gate insulating film according to claim 1 ,wherein the migration inhibitor is the polymer compound (X) containing a repeating unit represented by Formula (A).12. An organic thin film transistor prepared by using the composition for forming a gate insulating film according to .13. Electronic paper using the organic thin film transistor according to .14. A display device using the organic thin film transistor according to . This application is a Continuation of PCT International Application No. PCT/JP2014/064528 filed on May 30, 2014, which claims priority under 35 U.S.C. § ...

Forming interconnects

A method for forming an electronic device, comprising: forming a first conductive or semiconductive layer; forming a sequence of at least on insulating layer and at least one semiconducting layer over the first conductive or semiconductive layer; locally depositing solvents at a localized region of the insulating layer so as to dissolve the sequence of insulating and semiconducting layers in the region to leave a void extending through the sequence of layer; and depositing conductive or semiconductive material in the void.

POLAR SEMICONDUCTOR HOLE TRANSPORTING MATERIAL

A semiconductive hole transport material containing polar substituent groups, the polar substituent groups substantially not affecting the electronic properties of the hole transport material and the hole transport material being soluble in a polar solvent.

PHOTOSENSITIVE COMPOSITION AND ORGANIC THIN-FILM TRANSISTOR

In the formula (1), Ar1 represents a phenyl group or a naphthyl group, and in the formula (2), Ar2 represents a phenyl group or a naphthyl group. l and m are numbers satisfying that 1≥15 and l+m>90 when the total amount of all repeating units contained in the above-described polymer compound is taken as 100.

SEMICONDUCTOR ELEMENT AND INSULATING LAYER-FORMING COMPOSITION

Provided is a semiconductor element having a semiconductor layer and an insulating layer adjacent to the semiconductor layer, in which the insulating layer is formed of a crosslinked product of a polymer compound having a repeating unit (IA) represented by the following General Formula (IA) and a repeating unit (IB) represented by the following General Formula (IB). 2. The semiconductor element according to claim 1 , wherein Lis represented by the following Formula (1a) claim 1 ,{'br': None, 'sup': 1a', '3a, '*-Ar-L** \u2003\u2003Formula (1a)'}{'sup': 3a', '1a', '1a', '2a, 'in Formula (1a), Lrepresents a single bond or a linking group, Arrepresents an aromatic ring, * indicates the bonding position of the carbon atom to which Rin the repeating unit (IA) is bonded, and ** indicates the bonding position of Lin the repeating unit (IA).'}3. The semiconductor element according to claim 2 , wherein Aris a benzene ring.6. The semiconductor element according to claim 1 , wherein the crosslinkable group X is an epoxy group claim 1 , an oxetanyl group claim 1 , a hydroxymethyl group claim 1 , an alkoxymethyl group claim 1 , a (meth)acryloyloxy group claim 1 , a styryl group claim 1 , or a vinyl group.7. The semiconductor element according to claim 1 , wherein the crosslinkable group X is a hydroxymethyl group or an alkoxymethyl group.8. The semiconductor element according to claim 1 , wherein the crosslinked product is a crosslinked product by a crosslinking reaction between the crosslinkable group X of the repeating unit (IA) and the repeating unit (IB).9. The semiconductor element according to claim 8 , wherein the crosslinked product has a crosslinked portion where a hydroxymethyl group or an alkoxymethyl group as a crosslinkable group is formed by a reaction.10. The semiconductor element according to claim 1 , wherein the semiconductor layer contains an organic semiconductor. This application is a Continuation of PCT International Application No. PCT/JP2015/058775 filed ...

ELECTROLYTE-GATED TRANSISTORS FOR DETECTION OF MOLECULES

The disclosure describes methods, devices, and system that measure chemisorption potentiometrically for detection of target molecules. In one example, a device includes a semiconductor, an ionic conducting electronic insulator coupled to the semiconductor, a floating gate electrode comprising a first portion and a second portion, the first portion being coupled to the semiconductor via the ionic conducting electronic insulator, an aqueous buffer, and a primary gate electrode coupled to the second portion of the floating gate electrode via the aqueous buffer. The second portion of the floating gate electrode may comprise a probe configured to react with a target chemical composition of a molecule to detect the presence of the molecule. Reaction with the target chemical composition may change an electrical property of the device and indicate the presence of the molecule in the aqueous buffer.

Organic insulator composition including a hydroxyl group-containing polymer, dielectric film and organic thin film transistor using the same

An organic insulator composition including a crosslinking agent and a hydroxyl group-containing oligomer or hydroxyl group-containing polymer is provided. A dielectric film and an organic thin film transistor (OTFT) using an organic insulator composition are also provided. A dielectric film may include a compound having hydroxyl group-containing oligomers or hydroxyl group-containing polymers linked by crosslinking using a crosslinking agent having at least two vinyl ether groups. An organic thin film transistor may include a gate electrode on a substrate, a gate insulating layer on the gate electrode, source and drain electrodes on the gate insulating layer and an organic semiconductor layer contacting the gate insulating layer, wherein the gate insulating layer includes an dielectric film as described above.

MIXED SOLVENT PROCESS FOR PREPARING STRUCTURED ORGANIC FILMS

Thin film transistor comprising novel conductor and dielectric compositions

The invention relates to thin film transistors comprising novel dielectric layers and novel electrodes comprising metal compositions that can be provided by a dry thermal transfer process.

ASSEMBLY AND ELECTRONIC DEVICES INCLUDING THE SAME

СПОСОБ ИСПОЛЬЗОВАНИЯ ЦЕЛЛЮЛОЗНОГО НАТУРАЛЬНОГО, СИНТЕТИЧЕСКОГО ИЛИ СМЕШАННОГО МАТЕРИАЛА В КАЧЕСТВЕ ОДНОВРЕМЕННО НЕСУЩЕГО И ДИЭЛЕКТРИЧЕСКОГО ОСНОВАНИЯ В САМОСТОЯТЕЛЬНЫХ ЭЛЕКТРОННЫХ И ОПТОЭЛЕКТРОННЫХ УСТРОЙСТВАХ С ПОЛЕВЫМ ЭФФЕКТОМ

Изобретение относится к использованию материала, состоящего из натуральных, синтетических или смешанных волокон на основе целлюлозы, соединенных физически и химически водородными связями, и обычно называемого бумагой, в его различных формах и составах. В способе изготовления электронного или оптоэлектронного устройства с полевым эффектом натуральные, синтетические или смешанные диэлектрические волокна на основе целлюлозы соединяют физически и химически водородными связями в слои, после чего полученные слои соединяют путем механического сжатия с получением тонкой бумажной пленки, способной накапливать электрические и ионные заряды на единицу площади в зависимости от характера распределения волокон, их взаимосвязи и соединения в различных механически сжатых плоскостях, причем указанную бумажную пленку используют в указанном устройстве одновременно в качестве несущего основания и диэлектрика. Изобретение обеспечивает возможность использования бумаги при изготовлении устройств, основанных на ...

Vernetzbare polymere Materialien für dielektrische Schichten in elektronischen Bauteilen

Elektronische Bauteile, welche mindestens eine elektrische Schicht aufweisen, welche wenigstens eine Polymere der allgemeinen Formelmit olefinischen Oligo-dihydrodicyclopentadienylfunktionalitäten enthalten.

Organic electronic device with additional copolymer interlayer

Organic thin film transistors

Improvements in organic field-effect transistors

Transistor Devices

Organic transistor

An organic transistor comprising: source and drain electrodes; a gate electrode; an organic insulating layer between the gate electrode and the source and drain electrodes; and an organic semiconductive region between the insulating layer and the source and drain electrodes; wherein the organic semiconductive region comprises (a) a high mobility layer of an organic semiconductor and (b) a blocking layer of organic material positioned between the high mobility layer and the source and drain electrodes, in which the ionisation potential of the organic material of the blocking layer exceeds the workfunction of the source and drain electrodes so as to inhibit charge injection from the source electrode into the blocking layer in the off-state.

ORGANIC FIELD-EFFECT TRANSISTOR WITH ORGANIC DIELECTRIC

DETENTION LAYER ON FLUORIDATED POLYMERS

ORGANIC POLYMERS, ELECTRONIC DEVICES AND PROCEDURES

Forming interconnects

MIXED SOLVENT PROCESS FOR PREPARING STRUCTURED ORGANIC FILMS

A mixed solvent process for preparing structured organic film comprising a plurality of segments and a plurality of linkers arranged as a covalent organic framework, wherein the structured organic film may be a multi-segment thick structured organic film.

MIXED SOLVENT PROCESS FOR PREPARING STRUCTURED ORGANIC FILMS

A mixed solvent process for preparing structured organic film comprising a plurality of segments and a plurality of linkers arranged as a covalent organic framework, wherein the structured organic film may be a multi-segment thick structured organic film.

PROCESS FOR THE USE OF NATURAL, SYNTHETIC OR MIXED CELLULOSIC MATERIAL, SIMULTANEOUSLY AS PHYSICAL AND DIELECTRIC SUPPORT IN SELF-SUSTAINABLE FIELD-EFFECT ELECTRONIC AND OPTOELECTRONIC DEVICES

Embodiments of the present disclosure provide for the use and creation of natural cellulosic material, synthetic or mixed fibers hereafter designated as paper and the corresponding production process to be used simultaneously as physical and dielectric support in the creation of new field effect electronic or optoelectronic devices, called C- MOS structured electronic devices, whose paper electronic is now on called interstrate in which its functionality depends on the electrical charge capacity per unit area of the paper to accumulate electronic and ionic charges, function of how the forming fibers are distribute and compacted along the paper surface and thickness, as well as how the upmost surface close fibers are coated by an active ionic or covalent semiconductor and allowing the production of flexible self sustained devices, disposable devices, based on the new interstrate integrated concept, of monolithic or hybrid types.

SOLUTION PROCESSED DEVICES

A method for forming a transistor, comprising: depositing a first material from solution in a first solvent to form a first layer of the transistor; and subsequently whilst the first material remains soluble in the first solvent, forming a second layer of the transistor by depositing over the first material a second material from solution in a second solvent in which the first material is substantially insoluble.

Anchor group for monolayers of organic compounds on metal and component produced therewith by means of organic electronics

The invention relates to a novel anchor group for organic dielectric compounds as they are especially used in the production of organically based capacitors. The capacitors referred to are those that can be produced in a parallel process on a prepeg or other common printed circuit board substrate without additional metallisation on copper. The pre-fabricated capacitor layer can then be built into the printed circuit board, thereby gaining on space and cost for the surface of the printed circuit board.

Organic field effect transistor and making method

In an organic field effect transistor with an electrical conductor-insulator-semiconductor structure, the semiconductor layer is made of an organic compound, and the insulator layer is made of a polymer obtained through polymerization or copolymerization of 2-cyanoethyl acrylate and/or 2-cyanoethyl methacrylate.

Thin film semiconductor device and field effect transistor

Disclosed is a thin film semiconductor device comprising a semiconductor thin film (1) which is arranged on a gate electrode (13) through a gate insulating film (15). The semiconductor thin film (1) has a multilayer structure and contains at least two semiconductor layers (a, a'). In this semiconductor thin film (1), an intermediate layer (b), which is composed of a material different from that of the semiconductor layers (a, a'), is sandwiched between the two semiconductor layers (a, a'). The two semiconductor layers (a, a') are composed of the same material, and the intermediate layer (b) is composed of an insulating material. The materials constituting such a multilayer structure are organic materials. Consequently, lowering of mobility due to heating and deterioration in characteristics caused thereby can be suppressed, and thus the thin film semiconductor device is improved in heat resistance. Also disclosed is a field effect transistor.

Photocurable polymeric dielectrics and methods of preparation and use thereof

Method of making organic thin film transistors using a laser induced thermal transfer printing process

ELECTRONIC DEVICE AND METHOD OF MAKING SAME

ORGANIC TRANSISTOR IN THIN LAYERS, DISPLAY DEVICE HAS LIQUID CRYSTALS USING THIS TRANSISTOR, AND THEIR MANUFACTORING PROCESS

SLEEP HANGS ON FLUORINATED POLYMERS

Cette couche est réalisée en polymère fluoré dont une partie au moins de la surface est recouverte d'un polymère présentant au moins une fonction fluorée et au moins une fonction acide ou base.

Organic insulator, thin film transistor array panel comprising the organic insulator and manufacturing method thereof

POLYIMIDES AS DIELECTRIC

Use of crosslinked PVDF-HFP for accelerated thermal crosslinking OTFT through the addition of organic bases and gate dielectric materials for PVDF-HFP devices

ORGANIC THIN FILM TRANSISTOR HAVING FLUORINE-BASED POLYMER THIN FILM TO EASILY FORM ORGANIC SEMICONDUCTOR LAYER AND INSULATION LAYER BY WET ETCH PROCESS

PURPOSE: An organic thin film transistor having a fluorine-base polymer thin film is provided to greatly improve charge mobility and Ion/Ioff by forming a fluorine-based polymer thin film on the interface between a gate insulation layer and an organic semiconductor layer. CONSTITUTION: A gate electrode(2) is formed on a substrate(1). An insulation layer(3) is formed on the gate electrode. A thin film(4) composed of a fluorine-based polymer material is formed on the insulation layer. A polymer semiconductor(5) is formed on the fluorine-based polymer thin film, functioning as an organic semiconductor layer. A source electrode(6) and a drain electrode(7) are formed on the resultant structure. © KIPO 2006 ...

뱅크 구조물을 갖는 유기 전자 디바이스의 제조 방법, 이에 의해 제조된 뱅크 구조물 및 전자 디바이스

... 본 발명은 유기 전자 디바이스의 제조 방법으로서, 특정 및 웰 정의된 영역에서 반도체 재료의 성막을 허용하는 뱅크 구조물들을 형성하기 위하여 층이 팽윤 용매로 선택적으로 팽윤되는, 그러한 유기 전자 디바이스의 제조 방법에 관한 것이다. 본 발명은 또한, 상기 방법에 의해 제조된 뱅크 구조물, 유기 전자 디바이스 및 제품 또는 어셈블리에 관한 것이다.

COATING LIQUID FOR GATE INSULATING FILM, GATE INSULATING FILM AND ORGANIC TRANSISTOR

Disclosed is a coating liquid for gate insulating films which can be fired at a low temperature not more than 180°C. Also disclosed is a gate insulating film which can be easily formed by coating and has excellent solvent resistance and good characteristics such as resistivity and semiconductor mobility when an entire device is produced only by coating. Further disclosed is an organic transistor using such a gate insulating film. Specifically disclosed is a coating liquid for gate insulating films which is characterized by containing a polyimide obtained by dehydration ring closing of a polyamide acid having a repeating unit of a specific structure. Also specifically disclosed are a gate insulating film using the coating liquid and an organic transistor using such a gate insulating film. © KIPO & WIPO 2009 ...

MEMORY DEVICE HAVING MOLECULE ABSORPTION LAYER USING CHARGE STORAGE LAYER

PURPOSE: A memory device having a molecule absorption layer is provided to improve the operation stability by using a charge storage layer being used as a memory region. CONSTITUTION: A source electrode(13) and a drain electrode(14) are formed on a substrate(10). The source electrode and the drain electrode are isolated to each other. A carbon nanotube(20) electrically connects the source electrode to the drain electrode. A memory cell(30) is contacted to the carbon nanotube to store charges therefrom. A gate electrode(40) is installed on the memory cell. The memory cell is comprised of a first dielectric(32) on the carbon nanotube, a molecule absorption layer(34) formed on the first dielectric, and a second dielectric(36) on the molecule absorption layer. © KIPO 2006 ...

THIN-FILM CHEMICAL TRANSISTOR AND FABRICATING METHOD THEREOF TO DECREASE PROBABILITY OF TFT DEFECT

PURPOSE: A thin-film chemical transistor is provided to fabricate a thin-film chemical transistor easily by printing technology like an ink-jet process by forming a solid electrolyte layer and a semiconductor layer made of a compound capable of being melted in an organic solvent. CONSTITUTION: A thin-film chemical transistor has a structure composed of metal, solid electrolyte and semiconductor, wherein a solid electrolyte layer(3) and a semiconductor layer(4) are made of a compound capable of being melted in an organic solvent. The ion conductivity of the compound constituting the solid electrolyte layer is greater than 1 10^-5 S/centimeter. © KIPO 2006 ...

선택적 도핑 방법을 이용한 반도체 소자 및 이의 제조 방법

... 본 발명의 바람직한 실시예에 따른 선택적 도핑 방법을 이용한 반도체 소자 및 이의 제조 방법은, 고분자 반도체에 선택적 도핑 방법을 적용하여 전극을 구현함으로써, 동종 접합으로 이루어지는 유연한 반도체 소자를 제조할 수 있어, 반도체 소자의 구조 및 제조 공정을 단순화할 수 있고, 또한, 본 발명은 가교제를 이용하여 전자 재료 구성 층간 계면 가교를 구현함으로써, 높은 계면 접착력을 가지게 되어 기계적 변형이 가해져도 접착을 유지할 수 있는 유연한 반도체 소자를 제조할 수 있다.

Thin-film transistor

A thin-film transistor is provided, including on a substrate: a gate electrode, a semiconductor layer, a gate insulating layer disposed between the gate electrode and the semiconductor layer, and a source electrode and a drain electrode disposed in contact with the semiconductor layer and connected to each other through the semiconductor layer, wherein the gate insulating layer contains an organic polymer having no amide bond and imide bond, and the gate insulating layer has a water content of 0.01 to 1000 ppm.

Gate insulator layer for organic electronic devices

Embodiments in accordance with the present invention provide for the use of polycycloolefins in electronic devices and more specifically to the use of such polycycloolefins as gate insulator layers used in the fabrication of electronic devices, the electronic devices that encompass such polycycloolefin gate insulator and processes for preparing such polycycloolefin gate insulator layers and electronic devices.

ORGANIC THIN FILM TRANSISTOR AND ORGANIC THIN FILM LIGHT EMITTING TRANSISTOR

In an organic thin film transistor, at least three terminals, which are a gate electrode, a source electrode and a drain electrode, an insulator layer and an organic semiconductor layer are arranged on a substrate, and a current between the source and the drain is controlled by applying a voltage to the gate electrode. The organic semiconductor layer includes a specified organic compound having an aromatic heterocyclic group at the center. Light is emitted by using the current flowing between the source and the drain, and light emission is controlled by applying a voltage to the gate electrode. Response speed is high and furthermore, an on/off ratio is large. An organic thin film light emitting transistor using such organic thin film transistor is also provided.

ORGANIC SEMICONDUCTING FORMULATION

The invention generally relates to formulations for use in organic semiconductor layers of organic electronic devices, and more specifically in organic field effect transistors, to organic semiconductor layers prepared from such formulations, and to organic electronic devices and organic field effect transistors encompassing such organic semiconductor layers.

ELECTRONIC DEVICE

The invention relates to an organic electronic (OE) device, in particular a transistor, comprising an interlayer (7) between the gate insulator (4) and the gate electrode (5), to novel processes for preparing the device, and to dielectric materials for use in the interlayer.

FERRODIELECTRIC MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

The present invention relates to a ferrodielectric memory device and a method for manufacturing the same that provide stable memory operations by considerably enhancing characteristics of hysteresis and remanent polarization in ferrodielectrics applied to memory devices. In the present invention, PVDF having crystal structure of β-phase is used as a ferrodielectric substance applied to the ferrodielectric memory. The PVDF membrane in accordance with the present invention has excellent hysteresis characteristics that show a polarity of about 5µC/cm2 or more at about 1V as the polarity is increased with increasing of an applied voltage in about 0 to 1V1 and have another polarity of about -5µC/cm2 or less at about -1 V as the polarity is decreased with decreasing of an applied voltage in about -1V.

METHOD OF MANUFACTURING A FLEXIBLE ELECTRONIC DEVICE AND FLEXIBLE DEVICE

An electrical element, such as a thin-film transistor, is defined on a flexible substrate (1),in at the substrate (1) is attached to a carrier (20) by an adhesive layer (15), and is delaminated after definition of the transistor. This is for instance due to illumination by UV-radiation. An opaque coating (3, 24) is provided to protect any semiconductor material (5). A heat treatment is preferably given before application of the layers of the transistor to reduce stress in the adhesive layer.

METHOD OF FABRICATING A SEMICONDUCTOR DEVICE

A method of fabricating an electrode structure for a multilayer semiconductor device comprising a semiconductor layer having a first electrode layer in contact therewith and a second electrode layer separated there-from by a dielectric layer (8), the method comprising the steps of; applying a patterning material (20) only to selected areas of a support layer within the device so as to define the arrangement of the first electrode layer thereon; applying to the support layer a catalyst (24) adapted to be responsive to the patterning material (20); applying a conductive material (26) to the support layer so as to form the first electrode layer thereon; wherein the support layer, the patterning material (20) and the catalyst (24) cooperate such that the conductive material (26) is only deposited on the selected areas of the support layer to which the catalyst (24) has been applied. An thin film transistor (2) having a gate insulator layer (8) comprising an epoxide material.

METHOD AND SYSTEM FOR MOLECULAR CHARGE STORAGE FIELD EFFECT TRANSISTOR

A method and/or system and/or apparatus for a molecular-based FET device (an m-FET) uses charge storing molecules (120) between a gate (110) and channel (105) of an FET-type transistor. Further embodiments describe fabrication methods for using combinations of standard practices in lithography and synthetic chemistry and novel elements.

High-k dielectrics with a low-k interface for solution processed devices

A device, including a substrate, an electronically active component on the substrate, an interface dielectric on the semiconductor, and a relaxor dielectric on the interface dielectric. The relaxor dielectric includes a surfactant that is solid at room temperature.

Thin-film semiconductor device and field-effect transistor

A semiconductor thin film (1) that is laminated on a gate electrode (13) with a gate insulation film (15) therebetween is included. The semiconductor thin film (1) has a layered structure and includes at least two semiconductor layers (a, a). In the semiconductor thin film (1), for example, an intermediate layer (b) composed of a material different from the two semiconductor layers (a, a) is sandwiched between the semiconductor layers (a, a). The two semiconductor layers (a, a) are composed of an identical material and the intermediate layer (b) is composed of an insulation material. A material constituting such a layered structure is composed of an organic material. Thus, a thin-film semiconductor device and a field-effect transistor in which a decrease in the mobility caused by heating and degradation of characteristics caused by the decrease can be suppressed and the heat resistance is enhanced are provided.

PHOTO-CROSSLINKABLE MATERIAL FOR ORGANIC THIN FILM TRANSISTOR INSULATING LAYER

A problem of the present invention is to provide an organic thin film transistor insulating layer material which is capable of forming a cross-linked structure without conducting a treatment at higher temperature, and which enables an organic thin film transistor to have a small absolute value of threshold voltage (Vth) when it is used for the formation of a gate insulating layer. The means for solving the problem is an organic thin film transistor insulating layer material including a macromolecular compound that has a repeating unit having a group containing a fluorine atom and a repeating unit having a photodimerization-reactive group.

Thin-film transistor

There is provided herein a performance-enhancing composition comprising inorganic nanoparticles dispersed in a polymer selected from the group consisting of polysiloxane, polysilsesquioxane, and mixtures thereof. This composition, when applied to a thin-film transistor, such as a bottom-gate thin-film transistor, as an overcoat or top layer, improves the carrier mobility and current on/off ratio of the thin film transistor. Also provided is the thin-film transistor produced utilizing this process and/or composition.

Organic field-effect transistor, production method and intermediate structure therefor, and organic field-effect device

An organic field-effect transistor normally includes: a source electrode and a drain electrode; an organic semiconductor layer in contact with the source electrode and the drain electrode; a gate insulating layer adjacent to the organic semiconductor layer; and a gate electrode in contact with the gate insulating layer. The gate insulating layer according to the present invention is in a liquid state, constituted with a material containing no glue or thickener, a sole or main component of which is an ionic liquid. Thus the capacitance of the ionic liquid corresponding to a gate voltage modulation frequency of 10 Hz is reduced to 1/10 at a frequency of 10 kHz of higher. As a result, an organic field-effect transistor capable of operating at low voltage and assuring ample current gain and high-speed response (the capacitance of the ionic liquid corresponding to a gate voltage modulation frequency of 10 Hz is reduced to 1/10 at a frequency of 10 kHz of higher) is provided.

n-Type semiconductor element, complementary type semiconductor device and method for manufacturing same, and wireless communication device in which same is used

An excellent complementary semiconductor device is provided using a simple process. An n-type drive semiconductor device including a substrate; and a source electrode, a drain electrode, a gate electrode, a gate insulating layer, and a semiconductor layer on the substrate; and including a second insulating layer on the opposite side of the semiconductor layer from the gate insulating layer; in which the second insulating layer contains an organic compound containing a bond between a carbon atom and a nitrogen atom; and in which the semiconductor layer contains a carbon nanotube composite having a conjugated polymer attached to at least a part of the surface thereof.

Field effect transistor having a structure in which an organic semiconductor that forms a channel is made of a single crystal or a polycrystal of organic molecules

A TFT having a large mobility of carriers that are conducted through a channel as compared with a conventional organic TFT, and a method of manufacturing the TFT inexpensively and easily are provided. The channel is formed of a semiconductor organic molecular crystal thin film which is highly oriented, and a TFT that is large in the mobility of the carriers that are conducted through the channel, and a lyophilic TFT pattern that is surrounded by a lyophobic region on a substrate are formed, and the configuration of the pattern is featured, whereby a solution of the semiconductor organic molecules which is supplied to an appropriate region of a substrate surface including the channel is spontaneously dried in an anisotropic fashion, and highly oriented crystal is grown in the drying process.

FIELD-EFFECT TRANSISTOR AND MANUFACTURING PROCESS THEREOF

A field-effect transistor includes a gate, a source and a drain; a semiconductor layer between the source and the drain; and a gate insulator between the gate and the semiconductor layer. The gate insulator comprises a first layer adjoining the semiconductor layer; and a second layer. The first layer is formed from an amorphous fluoropolymer having a first dielectric constant and a first thickness. The second layer has a second dielectric constant and a second thickness. The first dielectric constant is smaller than 3, the first thickness is smaller than 200 nm, the second dielectric constant is higher than 5, and the second thickness is smaller than 500 nm. 1. A field-effect transistor comprising:a gate, a source and a drain;a semiconductor layer between said source and said drain; anda gate insulator between said gate and said semiconductor layer; a first layer adjoining said semiconductor layer; and', 'a second layer;', 'said first layer formed from an fluoropolymer having a first dielectric constant and a first thickness;', 'said second layer having a second dielectric constant and a second thickness,', 'said first dielectric constant being smaller than 3, said first thickness being smaller than 200 nm, said second dielectric constant being higher than 5, and said second thickness being smaller than 500 nm., 'wherein said gate insulator comprises2. (canceled)3. The field-effect transistor of claim 1 , wherein the fluoropolymer is an amorphous fluoropolymer that has a glass transition temperature above 80 degrees Celcius and is selected from the group consisting of a copolymer of: fluorinated 1 claim 1 ,3-dioxole and tetrafluoroethylene (TFE) claim 1 , a copolymer of perfluorofuran (PFF) and tetrafluoroethylene (TFE) claim 1 , a homo- or copolymer of perfluoro(4-vinyloxyl)-1-alkenes claim 1 , and combinations thereof.46-. (canceled)7. The field-effect transistor of claim 3 , wherein the second layer is formed from an inorganic material claim 3 , said inorganic ...

ORGANIC INSULATING LAYER COMPOSITION, METHOD OF FORMING ORGANIC INSULATING LAYER, AND ORGANIC THIN FILM TRANSISTOR INCLUDING THE ORGANIC INSULATING LAYER

An organic insulating layer composition includes a polymer mixture including 50 parts to 90 parts by volume of an organic polymer and 10 parts to 50 parts by volume of an amorphous polymer, wherein the organic polymer includes at least a first repeating unit and a second repeating unit, the first and second repeating units each being substituted with at least one of fluorine or chlorine, a total number of fluorine and chlorine atoms in the first repeating unit being different from a total number of fluorine and chlorine atoms in the second repeating unit, and an organic solvent. 1. An organic insulating layer composition , comprising:a polymer mixture including 50 parts to 90 parts by volume of an organic polymer and 10 parts to 50 parts by volume of an amorphous polymer, wherein the organic polymer includes at least a first repeating unit and a second repeating unit, the first and second repeating units each being substituted with at least one of fluorine or chlorine, a total number of fluorine and chlorine atoms in the first repeating unit being different from a total number of fluorine and chlorine atoms in the second repeating unit; andan organic solvent.2. The organic insulating layer composition as claimed in claim 1 , wherein the organic polymer includes at least one selected from poly(vinylidene fluoride-trifluoroethylene) claim 1 , poly(vinylidene fluoride-trifluoroethylene-chlorofluoroethylene) claim 1 , poly(vinylidene fluoride-trifluoroethylene-chlorodifluoroethylene) claim 1 , poly(vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene) claim 1 , and poly(vinylidene fluoride-trifluoroethylene-hexafluoropropylene).3. The organic insulating layer composition as claimed in claim 1 , wherein a number average molecular weight of the organic polymer is 5 claim 1 ,000 to 1 claim 1 ,000 claim 1 ,000.4. The organic insulating layer composition as claimed in claim 1 , wherein the organic polymer is poly(vinylidene fluoride-trifluoroethylene).5. The organic ...

SILK TRANSISTOR DEVICES

The invention relates to ecosustainable and biocompatible, low cost, ambient friendly electronic and optoelectronic devices, such as transistors and light-emitting transistors, made with silk fibroin or blended with other biopolymers, methods for fabrication and methods of using the silk-based electronics and optoelectronics. The silk-based electronics and optoelectronics can be implanted in vivo and in vitro for biomedical applications, such as for drug discovery or drug screening assays and devices. The silk-based devices may be used in the food industry and embedded in packaging for tracking and sensing, for security purposes or exploited as disposable not harmful for the environment efficient general electronic and optoelectronic devices. 1. A silk-based transistor comprising:a substrate including a gate contact;a silk dielectric layer positioned over the substrate;at least one active layer comprising an organic semiconducting material positioned over the silk dielectric layer; andsource and drain contacts positioned over the active layer.2. The silk-based transistor of claim 1 , wherein the source claim 1 , drain and gate contacts claim 1 , substrate claim 1 , active layer and silk dielectric layer are biocompatible.3. The silk-based transistor of claim 1 , wherein the source claim 1 , drain claim 1 , or gate contact is a metal or metal oxide selected from the group consisting of gold claim 1 , copper claim 1 , iron claim 1 , aluminum claim 1 , indium-tin-oxide claim 1 , and combination thereof.4. The silk-based transistor of claim 1 , wherein the active layer is p-type claim 1 , n-type or p-n junction type.5. The silk-based transistor of claim 1 , wherein the active layer is a combination of multiple layers which present charge transport and/or light emitting properties.6. The silk-based transistor of claim 1 , wherein the organic semiconducting material is selected from a group consisting of: thiophene derivatives claim 1 , perylene derivatives claim 1 , ...

Apparatus and method for aerosol deposition of nanoparticles on a substrate

Provided is an apparatus for aerosol deposition of nanoparticles on a substrate. The apparatus includes: an aerosol generator for generating an aerosol of micron-sized droplets, each droplet having a limited number of nanoparticles; and a deposition chamber for receiving the aerosol from the aerosol generator. The deposition chamber having an electrostatic field for attracting droplets in the aerosol to the substrate. The electrostatic field being substantially perpendicular to the substrate. The apparatus allows for films/networks of nanoparticles to be patterned on the substrate to sub-millimeter feature sizes, which allows the fabrication of transistor devices for printable electronics applications. Also provided are methods for depositing nanoparticles on a substrate and materials having networks of such nanoparticles.

THIN FILM STRUCTURE INCLUDING DIELECTRIC MATERIAL LAYER AND ELECTRONIC DEVICE EMPLOYING THE SAME

Disclosed are a thin film structure and an electronic device including the same. The disclosed thin film structure includes a dielectric material layer between a first material layer and a second material layer. The dielectric material layer includes a dopant in a matrix material having a fluorite structure. The dielectric material layer is uniformly doped with a low concentration of the dopant, and has ferroelectricity. 1. A thin film structure comprising:a first material layer;a dielectric material layer having ferroelectricity on the first material layer, the dielectric material layer including a matrix material having a fluorite structure and a dopant, a ratio of a concentration mean to a concentration standard deviation of the dopant in a thickness direction of the dielectric material layer is 8 or greater, and a thickness uniformity of the dielectric material layer is 90% or greater; anda second material layer on the dielectric material layer.2. The thin film structure of claim 1 , wherein the matrix material of the dielectric material layer is formed by atomic layer deposition.3. The thin film structure of claim 2 , wherein the matrix material of the dielectric material layer is an oxide claim 2 , andwherein the atomic layer deposition includes sequential injection cycles of a precursor and an oxidant, and an injection of the dopant between a precursor injection cycle and an oxidant injection cycle of at least one of the sequential injection cycles.4. The thin film structure of claim 3 , wherein the oxide includes a metal oxide.5. The thin film structure of claim 4 , wherein the matrix material of the dielectric material layer includes at least one of HfO claim 4 , ZrO claim 4 , and CeO.6. The thin film structure of claim 5 , wherein the dopant includes at least one of Al claim 5 , Si claim 5 , Zr claim 5 , Y claim 5 , La claim 5 , Gd claim 5 , and Sr.7. The thin film structure of claim 4 , wherein the dopant includes at least one of Al claim 4 , Si claim 4 , ...

A METHOD FOR ENHANCING THE PERFORMANCE OF PENTACENE ORGANIC FIELD-EFFECT TRANSISTOR AND THE STRUCTURE OF PENTACENCE ORGANIC FIELD-EFFECT TRANSISTOR

A method for enhancing the performance of pentacene organic field-effect transistor (OFET): an n-type semiconductor thin film was set as a buffer layer between pentacene and polymer electret in the OFET with the structure of gate-electrode/insulating layer/polymer/pentacene/source (drain) electrode. The thickness of n-type organic buffer layer is 1˜100 nm. The induced electrons at the interface lead to the reduction of the height of the hole-barrier formed at the interface, thus effectively reducing the programming/erasing (P/E) gate voltages of pentacene OFET. The widened distribution region of positive space charges caused by ionized donors in n-type organic buffer layer effectively restricts the back-transfer of holes from polymer to pentacene, thus improving the performance of pentacene OFET, such as the P/E speeds, P/E endurance and retention characteristics. 1. A structure configured to enhance performance of pentacene organic field-effect transistor (OFET) memorythe structure of the OFET is the bottom-gate type: the structure from the bottom to the top is gate-electrode/insulating layer/polymer/pentacene/source (drain)-electrode;or the structure of the OFET also can be the top-gate type: the structure from the bottom to the top is source(drain)-electrode/pentacene/polymer/insulating layer/gate-electrode[[. Its characteristics are as followed:an n-type semiconductor thin film is set as a buffer layer between pentacene and polymer electret;the gate electrode is a conductor which resistivity is less than 0.005 Ω·cm, and the insulating layer is an insulator;the polymer is a charge-trapping dielectric, and selected from polystyrene, poly(2-vinyl naphthalene) (PVN) and poly(α-methylstyrene) (PαMS);the thickness of polymer layer is 1-100 nm;N-type semiconductor thin film is a buffer layer, which is an n-type inorganic semiconductor thin film or an n-type organic semiconductor thin film, and its thickness is 1-100 nm;the thickness of pentacene is 1-100 nm; The ...

ORGANIC SEMICONDUCTOR ELEMENT, MANUFACTURING METHOD THEREOF, COMPOUND, ORGANIC SEMICONDUCTOR COMPOSITION, ORGANIC SEMICONDUCTOR FILM, AND MANUFACTURING METHOD THEREOF

Objects of the present invention are to provide an organic semiconductor element in which carrier mobility is high, variation of mobility is suppressed, and temporal stability under high temperature and high humidity is excellent, and a manufacturing method thereof, to provide a novel compound suitable for an organic semiconductor, and to provide an organic semiconductor film in which mobility is high, variation of mobility is suppressed, and temporal stability under high temperature and high humidity is excellent, a manufacturing method thereof, and an organic semiconductor composition that can suitably form the organic semiconductor film. 5. The organic semiconductor element according to claim 4 , further comprising:{'sup': '−1', 'a gate insulating film having a surface energy of 50 to 75 mNm.'}6. The organic semiconductor element according to claim 1 , that is an organic thin film transistor.10. The compound according to claim 7 , that is an organic semiconductor compound.11. An organic semiconductor composition comprising:{'claim-ref': {'@idref': 'CLM-00007', 'claim 7'}, 'the compound according to , and'}a solvent.13. An organic semiconductor film comprising the compound according to .15. A method of manufacturing an organic semiconductor film claim 7 , comprising:{'claim-ref': {'@idref': 'CLM-00011', 'claim 11'}, 'a coating step of coating a substrate with the organic semiconductor composition according to .'}16. A method of manufacturing an organic semiconductor film claim 7 , comprising:{'sup': '−1', 'claim-ref': {'@idref': 'CLM-00012', 'claim 12'}, 'a coating step of coating a gate insulating film having a surface energy of 50 to 75 mNmwith the organic semiconductor composition according to .'}17. A method of manufacturing an organic semiconductor element claim 7 , comprising:{'claim-ref': {'@idref': 'CLM-00011', 'claim 11'}, 'a coating step of coating a substrate with the organic semiconductor composition according to .'}18. A method of manufacturing an ...

METHOD FOR MANUFACTURING ARRAY SUBSTRATE, ARRAY SUBSTRATE, AND DISPLAY DEVICE

The present disclosure provides a method for manufacturing an array substrate, an array substrate, and a display device. The method for manufacturing the array substrate includes: forming a light-shielding layer and a buffer layer in sequence on a base substrate; forming an active layer on the buffer layer, and forming a first via hole in the active layer; forming an interlayer dielectric layer on the active layer; forming a second via hole in the interlayer dielectric layer at a position corresponding to the first via hole and a third via hole in the buffer layer at a position corresponding to the first via hole by a single patterning process; forming a source/drain electrode layer on the interlayer dielectric layer, in which the source/drain electrode layer is electrically connected to the light-shielding layer through the second via hole, the first via hole and the third via hole in sequence. 1. A method for manufacturing an array substrate , comprising:forming a light-shielding layer and a buffer layer in sequence on a base substrate;forming an active layer on a side of the buffer layer facing away from the base substrate and forming a first via hole in the active layer;forming an interlayer dielectric layer on a side of the active layer facing away from the base substrate;forming a second via hole in the interlayer dielectric layer at a position corresponding to the first via hole and forming a third via hole in the buffer layer at a position corresponding to the first via hole by a single patterning process, wherein a critical dimension of the second via hole is greater than critical dimensions of the first via hole and the third via hole, and orthogonal projections of the first via hole and the third via hole on the base substrate fall into a range of an orthogonal projection of the second via hole on the base substrate; andforming a source/drain electrode layer on a side of the interlayer dielectric layer facing away from the base substrate, wherein the ...

3D STATIC RAM CORE CELL HAVING VERTICALLY STACKED STRUCTURE, AND STATIC RAM CORE CELL ASSEMBLY COMPRISING SAME

Disclosed is a 3D static RAM core cell having a vertically stacked structure, including six thin-film transistors each having a gate electrode, a source electrode and a drain electrode, the static RAM core cell including two switching thin-film transistors, each connected to a bit line and a word line to select recording and reading of data, and four data-storage thin-film transistors connected to a power supply voltage (Vdd) or a ground voltage (Vss) to record and read data, the static RAM core cell including a first transistor layer including two thin-film transistors selected from among the six thin-film transistors, a second transistor layer disposed on the first transistor layer and including two thin-film transistors selected from among the remaining four thin-film transistors, and a third transistor layer disposed on the second transistor layer and including the remaining two thin-film transistors, at least one electrode of the first transistor layer and at least one electrode of the second transistor layer being electrically connected to each other, and at least one electrode of the second transistor layer and at least one electrode of the third transistor layer being electrically connected to each other. Thereby, the static RAM core cell is configured such that organic transistors of the same type are arranged in the same plane and are vertically stacked, thus omitting a complicated patterning process for forming organic transistors of different types upon fabrication of a memory element, and also reducing the area occupied by the memory element to thereby increase the degree of integration of semiconductor circuits. 1. A 3D (three-dimensional) static RAM (Random-Access Memory) core cell having a vertically stacked structure , comprising six thin-film transistors each comprising a gate electrode , a source electrode , and a drain electrode ,the static RAM core cell comprising:two switching thin-film transistors each connected to a bit line and a word line ...

LAYERED METAL OXIDE FIELD EFFECT MATERIAL AND ITS APPLICATION

A layered metal oxide field effect material forms a heterojunction from metal oxides with different band gaps, and defines a band gap difference (ΔE)≥1 eV. Band bending is generated at the interface of the heterojunction, such that a potential barrier is formed on the side with the larger band gap and a triangular potential well is formed on the side with the smaller band gap, and under the induction of a gate electric field, a polarized charge is generated at the interface of the heterojunction, and a large number of carriers are accumulated. Therefore, the present layered metal oxide field effect material has high carrier mobility higher than 10cm/V·s, and overcomes the problem that the carrier mobility of a conventional metal oxide field effect material is low, it is required to fabricate the metal oxide field effect material into a crystal phase structure with a relatively high cost, and even that a substrate thereof with a crystal phase structure is required. 1. A layered metal oxide field effect material with a sandwich structure which sequentially comprises a first surface layer , a core layer and a second surface layer , the core layer being a metal oxide layer with a wide band gap , the first surface layer and the second surface layer being metal oxide layers with narrow band gaps; wherein , the band gap of the metal oxide in the core layer is ≥3 eV , the band gaps of the metal oxides in the first surface layer and the second surface layer are independently ≤3 eV , and the difference between the band gap of the metal oxide in the core layer and the band gap of the metal oxide in the first surface layer is ≥1 eV.2. The layered metal oxide field effect material according to claim 1 , wherein the thickness of the layered metal oxide field effect material is ≤30 nm.3. The layered metal oxide field effect material according to claim 1 , wherein the thicknesses of the first surface layer claim 1 , the second surface layer and the core layer are independently ≤10 ...

ELECTRONIC DEVICE INSULATING LAYER, AND METHOD FOR PRODUCING ELECTRONIC DEVICE INSULATING LAYER

An object of the present invention is to provide an electronic device insulating layer which may improve characteristics of an electronic device. The means for solving the object is an electronic device insulating layer comprising a first insulating layer formed from a first insulating layer material and a second insulating layer formed on the first insulating layer from a second insulating layer material, the first insulating layer material being an insulating layer material comprising a photosensitive resin material (A), a tungsten (V) alkoxide (B) and a basic compound (C), the second insulating layer material being an insulating layer material comprising a polymer compound (D) which contains a repeating unit containing a cyclic ether structure and a repeating unit having an organic group capable of producing a phenolic hydroxyl group by the action of an acid. 2. The electronic device insulating layer according to claim 1 , wherein said first insulating layer material further comprises a basic compound (C).3. The electronic device insulating layer according to claim 1 , wherein said photosensitive resin material (A) is a positive photosensitive resin material (A-1) or a negative photosensitive resin material (A-2).5. The electronic device insulating layer according to claim 4 , wherein said first functional group is at least one group selected from the group consisting of an isocyanato group blocked with a blocking agent and an isothiocyanato group blocked with a blocking agent.10. The electronic device insulating layer according to claim 8 , wherein said polymer compound (G) contains at least one repeating unit selected from the group consisting of repeating units containing a first functional group defined below.first functional group: a functional group capable of affording, by the action of electromagnetic waves or heat, a second functional group capable of reacting with active hydrogen.11. The electronic device insulating layer according to claim 1 , wherein ...

ORGANIC LIGHT-EMITTING DEVICE

An organic light-emitting device is provided. The organic light-emitting device includes: a first electrode; a second electrode facing the first electrode; and an organic layer between the first electrode and the second electrode, the organic layer including an emission layer and a first compound represented by Formula 1 and a second compound represented by Formula 2. 3. The organic light-emitting device of claim 1 , wherein:{'sub': 10', '20', '30, 'R, R, and Rare each independently selected from hydrogen, deuterium, —F, —Cl, —Br, —I, a methyl group, an ethyl group, an n-propyl group, an iso-propyl group, an n-butyl group, a sec-butyl group, an iso-butyl group, a tert-butyl group, a methoxy group, an ethoxy group, an n-propoxy group, an iso-propoxy group, an n-butoxy group, a sec-butoxy group, an iso-butoxy group, and a tert-butoxy group;'}a methyl group, an ethyl group, an n-propyl group, an iso-propyl group, an n-butyl group, a sec-butyl group, an iso-butyl group, a tert-butyl group, a methoxy group, an ethoxy group, an n-propoxy group, an iso-propoxy group, an n-butoxy group, a sec-butoxy group, an iso-butoxy group, and a tert-butoxy group, each substituted with at least one selected from deuterium, —F, —Cl, —Br, —I, a cyano group, a phenyl group, and a biphenyl group; and{'sub': 1', '2', '3', '1', '2', '3', '1', '2', '1', '2, '—Si(Q)(Q)(Q), —Ge(Q)(Q)(Q), —B(Q)(Q) and —N(Q)(Q).'}4. The organic light-emitting device of claim 1 , wherein claim 1 , in a case where a30 is 0 claim 1 , at least one of the R(s) in the number of b30 is selected from —Si(Q)(Q)(Q) claim 1 , —Ge(Q)(Q)(Q) claim 1 , —B(Q)(Q) claim 1 , and N(Q)(Q).7. The organic light-emitting device of claim 1 , wherein Aand Aare each independently selected from a benzene group claim 1 , an indene group claim 1 , a naphthalene group claim 1 , an anthracene group claim 1 , a fluorene group claim 1 , a phenanthrene group claim 1 , a triphenylene group claim 1 , a pyrene group claim 1 , a chrysene group claim 1 ...

ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF

A electronic device includes: a control electrode formed on a base substrate ; an insulation layer adapted to cover the control electrode and formed of an organic insulation material; an active layer formed on the insulation layer , formed of an organic semiconductor material, and subjected to patterning; and a first electrode A and a second electrode B formed on the active layer , in which a chemical composition of a surface of a region A (A) that is a region of the insulation layer not formed with the active layer differs from a chemical composition of a region B (B) that is a region of the insulation layer located under the active layer 1. An electronic device comprising:a control electrode formed on a base substrate;an insulation layer configured to cover the control electrode and formed of an organic insulation material;an active layer formed on the insulation layer, formed of an organic semiconductor material, and subjected to patterning; anda first electrode and a second electrode formed on the active layer,wherein a chemical composition of a surface of a region A that is a region of the insulation layer not formed with the active layer differs from a chemical composition of a region B that is a region of the insulation layer located under the active layer.2. An electronic device comprising:a control electrode formed on a base substrate;an insulation layer configured to cover the control electrode and formed of an organic insulation material;a first electrode and a second electrode formed on the insulation layer; andan active layer formed on at least a portion of the insulation layer located between the first electrode and the second electrode, formed of an organic semiconductor material, and subjected to patterning,wherein a chemical composition of a surface of a region A that is a region of the insulation layer not formed with the first electrode, the second electrode, and the active layer differs from a chemical composition of a region B that is a region ...

Photo-patternable gate dielectrics for ofet

Articles utilizing polymeric dielectric materials for gate dielectrics and insulator materials are provided along with methods for making the articles. The articles are useful in electronics-based devices that utilize organic thin film transistors.

Semiconductor device

The oxide semiconductor film has the top and bottom surface portions each provided with a metal oxide film containing a constituent similar to that of the oxide semiconductor film. An insulating film containing a different constituent from the metal oxide film and the oxide semiconductor film is further formed in contact with a surface of the metal oxide film, which is opposite to the surface in contact with the oxide semiconductor film. The oxide semiconductor film used for the active layer of the transistor is an oxide semiconductor film highly purified to be electrically i-type (intrinsic) by removing impurities such as hydrogen, moisture, a hydroxyl group, and hydride from the oxide semiconductor and supplying oxygen which is a major constituent of the oxide semiconductor and is simultaneously reduced in a step of removing impurities.

ORGANIC THIN FILM TRANSISTOR ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF

The present invention discloses an organic thin film transistor array substrate and a fabrication method thereof. The fabrication method is that a metal layer is first deposited successively on a substrate and followed by depositing a layer of Indium Tin Oxide (ITO), and then a photoresist layer is covered thereon to form a data line, a source electrode, a drain electrode and a pixel electrode by a first mask process. Subsequently, an organic semiconductor layer, a gate electrode, a scanning line, and a passivation layer are formed successively. Finally, a region where the pixel electrode, i.e. an anode of an OLED device, is situated and covered with the passivation layer is excavated an opening and allowing the underlying pixel electrode to be exposed to the outside. Then, a layer of OLED material is deposited on the exposed ITO pixel electrode to form an OLED device. 1. (canceled)2. (canceled)3. A method of fabricating an OTFT array substrate comprising the steps of:providing a base substrate;depositing a metal layer and an ITO layer on the base substrate, subsequently covering a photoresist layer thereon and then forming a data line, a source electrode, a drain electrode and a pixel electrode by a first mask process;coating an organic semiconductor layer on the array substrate having the data line, the source electrode, the drain electrode, and the pixel electrode formed thereon and then forming an active layer by a patterning process, subsequently coating an organic insulating layer on the organic semiconductor layer to cover the organic insulating layer on an entire surface of the work-in-progress array substrate;depositing a metal layer on the organic insulating layer and then forming a gate electrode and a scanning line by a third mask process, subsequently coating an organic insulating layer on the entire surface of the work-in-progress array substrate to form a passivation layer so that the passivation layer covers on the entire surface of the work-in- ...

Organic Electronic Compositions and Device Thereof

The present invention relates to organic electronic devices, and more specifically to organic field effect transistors, comprising a dielectric layer that comprises a polycycloolefinic polymer with an olefinic side chain. 24.-. (canceled)6. The OE device according to claim 1 , wherein the polycycloolefinic polymer is a copolymer comprising two or more repeating units claim 1 , each repeating unit comprising a different isomeric form of the same pendant alkenyl group.8. The OE device according to claim 1 , wherein the polycycloolefinic polymer comprises units P with a terminal pendant alkenyl group and units Pi with an isomerized pendant alkenyl group claim 1 , wherein the ratio of units P to units Pi is from 1:6 to 20:1.10. A dielectric layer in an OE device claim 1 , said dielectric layer comprising claim 1 , or being obtained through the use of claim 1 , a polycycloolefinic polymer as defined in .11. The OE device according to claim 1 , which is an Organic Field Effect Transistor (OFET) claim 1 , Organic Thin Film Transistor (OTFT) claim 1 , Organic Light Emitting Diode (OLED) or Organic Photovoltaic (OPV) device or Organic Photodetector (OPD).12. The OE device according to claim 11 , which is a top gate OFET or bottom gate OFET.13122345ab. The top gate OFET according to claim 11 , which comprises a substrate () claim 11 , source and drain electrodes ( claim 11 , ) claim 11 , an organic semiconductor (OSC) layer () claim 11 , a dielectric layer () comprising a polycycloolefinic polymer as defined in one or more of to and serving as gate insulator claim 11 , and gate electrode ().14. A process for preparing an OFET according to claim 13 , which comprises:{'b': 2', '2', '1, 'i': a', 'b, 'A) forming source and drain electrodes (, ) on a substrate (),'}{'b': 3', '2', '2, 'i': a', 'b, 'B) forming an OSC layer () by deposition of an OSC material on the source and drain electrodes (, ),'}{'b': 4', '3, 'claim-ref': [{'@idref': 'CLM-00001', 'claims 1'}, {'@idref': 'CLM- ...

Self-aligned vertical cnt array transistor

A transistor device includes an array of fin structures arranged on a substrate, each of the fin structures being vertically alternating stacks of a first isoelectric point material having a first isoelectric point and a second isoelectric point material having a second isoelectric point that is different than the first isoelectric point; one or more carbon nanotubes (CNTs) suspended between the fin structures and contacting a side surface of the second isoelectric point material in the fin structures; a gate wrapped around the array of CNTs; and source and drain contacts arranged over the fin structures; wherein each of the fin structures have a trapezoid shape or parallel sides that are oriented about 90° with respect to the substrate.

STRONGLY POLARIZED MOLECULE, AND SINGLE MOLECULE FIELD EFFECT TRANSISTOR PREPARED THEREFROM

The application relates to a strongly-polarized molecule of the following general formula: wherein A denotes a group having a polarizability greater than 2 C·m/V; Rand Rare respectively hydrogen, halogen, a hydroxyl group, an amino group, a cyano group, a nitro group, a carboxyl group, a Calkyl group, a Calkoxy group, a halogenated Calkyl group, a halogenated Calkoxy group, a hydroxyl Calkyl group, a hydroxyl Calkoxy group, or a Calkyl amino group; xand xdenote 0 or an integer no less than 1, respectively; and yand ydenote 0 or an integer no less than 1, respectively. The application further relates to a strongly-polarized molecule-graphene molecule heterojunction, and a single molecule field effect transistor comprising a substrate, a gate, a dielectric layer and the strongly-polarized molecule-graphene molecule heterojunction; and the dielectric layer is located between the gate and the strongly-polarized molecule-graphene molecule heterojuction. The single molecule field effect transistor provided by the application can realize highly-efficient gate modulation. 5. A strongly-polarized molecule-graphene molecule heterojunction claim 1 , wherein the molecule heterojunction comprises the strongly-polarized molecule according to bridging between layers of two-dimensional single-layer graphene with a nanogap via amide covalent bonds.6. A single molecule field effect transistor 5 , comprising a substrate 5 , a gate 5 , a dielectric layer 5 , and the strongly-polarized molecule-graphene molecule heterojunction according to claim 5 , wherein the dielectric layer is located between the gate and the strongly-polarized molecule-graphene molecular heterojunction.7. The single molecule field effect transistor according to claim 6 , wherein the material of the gate is one of graphene or metal aluminum.8. The single molecule field effect transistor according claim 6 , wherein the material of the dielectric layer is one of hafnium oxide claim 6 , zirconium oxide claim 6 , ...

Carbon nanotube thin film transistor and manufacturing method thereof

A carbon nanotube thin film transistor and a manufacturing method thereof are provided in the embodiments of the present disclosure. The carbon nanotube thin film transistor includes: a base substrate; a gate electrode, a semiconductor layer, a source electrode and a drain electrode, which are disposed on the base substrate, the semiconductor layer includes a poly(3-hexylthiophene) layer and a mixing layer of semiconducting carbon nanotube and poly(3-hexylthiophene) which are stacked. The semiconducting carbon nanotube thin film transistor has a high purity, thus the metallic carbon nanotubes are substantially cleared out and the electrical property of the thin film transistor is ensured, so that the manufactured carbon nanotube thin film transistor has good electrical properties.

n-TYPE SEMICONDUCTOR ELEMENT, COMPLEMENTARY TYPE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME, AND WIRELESS COMMUNICATION DEVICE IN WHICH SAME IS USED

An excellent complementary semiconductor device is provided using a simple process. An n-type drive semiconductor device including a substrate; and a source electrode, a drain electrode, a gate electrode, a gate insulating layer, and a semiconductor layer on the substrate; and including a second insulating layer on the opposite side of the semiconductor layer from the gate insulating layer; in which the second insulating layer contains an organic compound containing a bond between a carbon atom and a nitrogen atom; and in which the semiconductor layer contains a carbon nanotube composite having a conjugated polymer attached to at least a part of the surface thereof. 1. An n-type semiconductor device comprising:a substrate;a source electrode, a drain electrode, and a gate electrode;a semiconductor layer in contact with the source electrode and the drain electrode;a gate insulating layer insulating the semiconductor layer from the gate electrode; anda second insulating layer in contact with the semiconductor layer on the opposite side of the semiconductor layer from the gate insulating layer;wherein the semiconductor layer contains a carbon nanotube composite having a conjugated polymer attached to at least a part of the surface thereof; andwherein the second insulating layer contains an organic compound containing a bond between a carbon atom and a nitrogen atom.2. The n-type semiconductor device according to claim 1 , wherein the conjugated polymer comprises claim 1 , in the repeating units thereof claim 1 , a fused heteroaryl unit having a nitrogen-containing double bond in the ring thereof and a thiophene unit.4. The n-type semiconductor device according to claim 3 , wherein Rto Rin the general formulae (1) to (8) are hydrocarbon groups.5. The n-type semiconductor device according to claim 1 , wherein the second insulating layer comprises an amine compound having a ring structure.6. The n-type semiconductor device according to claim 3 , wherein the second ...

FIELD EFFECT TRANSISTOR

There is provided a field effect transistor which comprises a gate insulating layer, a gate electrode, a semiconductor layer, a source electrode and a drain electrode. The gate insulating layer contains an organic compound that contains a silicon-carbon bond and a metal compound that contains a bond between a metal atom and an oxygen atom; and the metal atoms are contained in the gate insulating layer in an amount of 10 to 180 parts by weight with respect to 100 parts by weight of the total of carbon atoms and silicon atoms. This field effect transistor (FET) has high mobility and a low voltage of the threshold value, while being suppressed in leak current. 1. A field effect transistor comprising:a gate insulating layer,a gate electrode,a semiconductor layer,a source electrode, anda drain electrode,wherein the gate insulating layer contains an organic compound containing a silicon-carbon bond and a metal compound containing a bond between a metal atom and an oxygen atom; andwherein the metal atoms are contained in the gate insulating layer in an amount of 10 to 180 parts by weight with respect to 100 parts by weight of the total of carbon atoms and silicon atoms.2. The field effect transistor according to claim 1 , wherein the metal atoms are contained in the gate insulating layer in an amount of 17 to 30 parts by weight with respect to 100 parts by weight of the total of carbon atoms and silicon atoms.3. The field effect transistor according to claim 1 , wherein the metal atom is aluminum.4. The field effect transistor according to claim 1 , wherein a film thickness of the gate insulating layer is 0.05 μm to 5 μm.5. The field effect transistor according to claim 1 , wherein the semiconductor layer contains a single-walled carbon nanotube.6. The field effect transistor according to claim 5 , wherein the single-walled carbon nanotube contains a highly semiconductor enriched single-walled carbon nanotube in an amount of 90% by weight or more.7. A composition ...

MANUFACTURING METHOD AND APPARATUS OF ORGANIC THIN FILM TRANSISTOR

A manufacturing method of an organic thin film transistor includes: forming source and drain electrodes on a substrate; irradiating a photosensitive outer surface with a first charge of a photosensitive roller by laser to pattern the photosensitive outer surface and forming a channel pattern area without charge; spraying an atomized organic material solution with a third charge having same polarity as the first charge onto the channel pattern area to make the organic material solution be absorbed onto the channel pattern area and thereby form a channel region layer; attaching a fourth charge having an opposite polarity to the third charge onto a surface of the substrate disposed with the source and drain electrodes; and transferring a channel pattern in the channel region layer onto the substrate and connected with the source and drain electrodes and thereby forming a channel region. A manufacturing apparatus also is provided. 1. A manufacturing apparatus of an organic thin film transistor , wherein the manufacturing apparatus comprises: a photosensitive roller , an exposure assembly , a developing assembly and a driven roller;the photosensitive roller comprises a photosensitive outer surface with a first charge and a photosensitive inner surface with a second charge, the first charge and the second charge have opposite polarities;the exposure assembly is configured for irradiating a laser with graphic information to the photosensitive outer surface and thereby forming a pattern area without charge on the photosensitive outer surface;the developing assembly comprises a bump for outputting an organic material solution and a high-pressure nozzle with an electrode pairs, the organic material solution ejected from the high-pressure nozzle in operation carries a third charge having a polarity same as that of the first charge and the ejected organic material solution then is absorbed onto the pattern area;an outer circumferential surface of the driven roller and the ...

ORGANIC THIN FILM TRANSISTORS AND THE USE THEREOF IN SENSING APPLICATIONS

The present invention relates to organic thin film transistors and the preparation and use thereof in sensing applications, and in particular in glucose sensing applications. 1. An organic thin film transistor based sensor device , the device including:(i) a gate electrode;(ii) a dielectric layer;(iii) a semiconducting layer including at least one organic compound;(iv) a source electrode;(v) a drain electrode; and(vi) a substrate; and(vii) an enzyme located in, or forming part of any one of (i)-(vi),wherein the device has top gate bottom contact configuration such that the gate electrode is disposed above the dielectric layer, and the dielectric layer is disposed above the semiconducting layer.2. The device of any claim 1 , wherein the semiconducting layer is disposed above and in between the source electrode and the drain electrode.3. The device of any claim 1 , wherein the source electrode and the drain electrode are disposed above the substrate.4. The device of any one of to claim 1 , wherein the gate electrode is disposed above claim 1 , and in direct contact with claim 1 , the dielectric layer.5. The device of any one of to claim 1 , wherein the dielectric layer is disposed above claim 1 , and in direct contact with claim 1 , the semiconducting layer.6. The device of any one of to claim 1 , wherein the semiconducting layer is disposed above and in between the source electrode and the drain electrode claim 1 , and in direct contact with claim 1 , the source electrode and the drain electrode.7. The device of any one of to claim 1 , wherein the source electrode and the drain electrode are disposed above claim 1 , and in direct contact with claim 1 , the substrate.8. The device of any one of to claim 1 , wherein the gate electrode comprises a porous matrix.9. The device of claim 8 , wherein the porous matrix is a sulfonated tetrafluoroethylene-based fluoropolymer-copolymer.10. The device of claim 9 , wherein the sulfonated tetrafluoroethylene-based fluoropolymer- ...

METHOD OF MANUFACTURING A FIELD EFFECT TRANSISTOR USING CARBON NANOTUBES AND A FIELD EFFECT TRANSISTOR

In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure including CNTs embedded in a semiconductor layer is formed, a sacrificial gate structure is formed over the fin structure, the semiconductor layer is doped at a source/drain region of the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, and a source/drain contact layer is formed over the doped source/drain region of the fin structure. 1. A semiconductor device having a gate-all-around field effect transistor (GAA FET) , comprising:carbon nanotubes (CNTs) disposed over a substrate;a gate structure formed around each of the CNTs in a channel region;a doped semiconductor layer wrapping around each of the CNTs in a source/drain region; anda source/drain contact formed over the semiconductor layer.2. The semiconductor device of claim 1 , wherein the doped semiconductor layer is crystalline silicon.3. The semiconductor device of claim 1 , wherein an impurity concentration in the doped semiconductor layer is in a range from 1×10atoms/cmto 1×10atoms/cm.4. The semiconductor device of claim 1 , wherein the GAA FET is an n-type FET and the doped semiconductor layer contains at least one of P and As as impurities.5. The semiconductor device of claim 1 , wherein the GAA FET is a p-type FET and the doped semiconductor layer contains at least one of B and Ga as impurities.6. The semiconductor device of claim 1 , wherein a semiconductor layer having a lower impurity concentration than the doped semiconductor layer is disposed between the doped semiconductor layer and the gate structure.7. The semiconductor device of claim 1 , wherein:the CNTs include multiple groups of CNTs,the CNTs in a same group are located at a same height, andthe multiple groups are located at different heights from each other.8. The semiconductor device of claim 7 , wherein one group is separated from an adjacent group by a distance ...

STACK PATTERNING

A technique of forming a stack of layers defining electrical circuitry and comprising a plurality of inorganic conductor levels, wherein the method comprises: forming a conductor for at least one of the conductor levels in stages before and after a step of patterning an underlying organic layer. 1. A method of forming a stack of layers defining electrical circuitry and comprising a plurality of inorganic conductor levels , wherein the method comprises:forming a conductor for at least one of the conductor levels in stages before and after a step of patterning an underlying organic layer.2. The method according to claim 1 , comprising:between two stages of forming the conductor, using the conductor as a mask to pattern the underlying organic layer.3. A method according to :wherein one stage of forming the conductor comprises forming a conductor pattern that provides a mask for creating via-holes through the underlying organic layer in one or more interconnect regions at which the conductor is to contact another conductor at a lower conductor level; andwherein another stage of forming the conductor comprises depositing conductor material at least in the region of the via-holes.4. The method according to :wherein patterning the underlying organic layer comprises depositing a solution of organic photoresist material; andwherein one stage of forming the conductor before patterning the underlying organic layer comprises forming a layer of inorganic conductor material in all areas in which the solution of organic photoresist material is to be deposited.5. The method according to :wherein the conductor comprises a gate conductor pattern for a transistor array, and the underlying organic layer comprises an organic polymer dielectric layer.6. The method according to claim 1 , wherein the underlying organic layer comprises a non-cross-linked polymer layer.7. The method according to claim 3 , wherein the conductor pattern and the conductor material have substantially the same ...

PATTERNING METHOD FOR PREPARING TOP-GATE, BOTTOM-CONTACT ORGANIC FIELD EFFECT TRANSISTORS

The present invention relates to a process for the preparation of a top-gate, bottom-contact organic field effect transistor on a substrate, which organic field effect transistor comprises source and drain electrodes, a semiconducting layer, a cured first dielectric layer and a gate electrode, and which process comprises the steps of: i) applying a composition comprising an organic semiconducting material to form the semiconducting layer, ii) applying a composition comprising a first dielectric material and a crosslinking agent carrying at least two azide groups to form a first dielectric layer, iii) curing portions of the first dielectric layer by light treatment, iv) removing the uncured portions of the first dielectric layer, and v) removing the portions of the semiconducting layer that are not covered by the cured first dielectric layer, wherein the first dielectric material comprises a star-shaped polymer consisting of at least one polymer block A and at least two polymer blocks B, wherein each polymer block B is attached to the polymer block A, and wherein at least 60 mol % of 9. The process of claim 1 , wherein the weight ratio of polymerblock A/total polymer_blocks B is from 60/40 to 96/4.10. The process of claim 1 , wherein the star-shaped polymers have a number average molecular weight Mn of at least 60000 g/mol and a weight average molecular weight Mw of at least 70000 g/mol claim 1 , both as determined by gel permeation chromatography.13. The process of further comprising step vi) of applying a composition comprising a second dielectric material on top of the cured first dielectric layer to form a second dielectric layer.14. The process of claim 13 , wherein the cured first dielectric layer and the semiconducting layer cover the path between the source and drain electrodes claim 13 , and optionally also partially or completely covers the source and drain electrodes.15. The process of claim 13 , wherein the composition comprising a second dielectric ...

ORGANIC THIN FILM TRANSISTORS AND METHODS FOR THEIR MANUFACTURING AND USE

Methods of forming an organic thin film transistor are provided. The methods include providing a substrate and depositing and patterning a gate electrode on a first surface of the substrate. The methods include dispensing a first droplet of an insulating material on the gate electrode on the substrate and dispensing a second droplet of a semiconductor material on a first surface of the first droplet. The second droplet forms a hydrophobic structure having a central cavity. The methods also include dispensing a third droplet of a conductor material on a first surface of the second droplet such that the conductor material substantially fills the central cavity of the hydrophobic structure and forms a conductor material layer around the central cavity to define a source electrode and a drain electrode of the organic thin film transistor. 1. A method of forming an organic thin film transistor , the method comprising:providing a substrate;depositing and patterning a gate electrode on a first surface of the substrate;dispensing a first droplet of an insulating material on the first surface of the substrate;dispensing a second droplet of a semiconductor material on a first surface of the first droplet, wherein the second droplet forms a hydrophobic structure having a central cavity; anddispensing a third droplet of a conductor material on a first surface of the second droplet, wherein the conductor material substantially fills the central cavity of the hydrophobic structure and forms a conductor material layer around the central cavity to define a source electrode and a drain electrode of the organic thin film transistor.2. The method of claim 1 , wherein the substrate comprises a rigid substrate claim 1 , or a flexible substrate.3. The method of claim 2 , wherein the substrate comprises glass claim 2 , silicon claim 2 , polyethylene terephthalate (PET) claim 2 , polyethylene naphthalate (PEN) claim 2 , or combinations thereof.4. The method of claim 1 , wherein the gate ...

RADIATION CURABLE POLYMER FORMULATION AND METHODS FOR THE PREPARATION THEREOF

Disclosed is a radiation curable polymer formulation and methods of producing a dielectric film having such a formulation. The radiation curable polymer formulation includes an acrylic monomer; a cross linking agent; and a photoinitiator. The polymer formulation is insoluble with an organic solvent, which is preferable in low cost high volume manufacturing of thin film transistors for flexible electronics. 1. A radiation curable polymer formulation comprising:an acrylic monomer;a cross linking agent; anda photoinitiator,wherein the cured polymer is insoluble in an organic solvent.2. The radiation curable polymer formulation of claim 1 , wherein the organic solvent is isopropanol claim 1 , acetone claim 1 , ethanol claim 1 , methanol claim 1 , other alcohols claim 1 , ketones claim 1 , polar and non-polar organic solvents or combinations thereof.3. The radiation curable polymer formulation of claim 1 , wherein the cured polymer is insoluble in an aqueous solvent.4. The radiation curable polymer formulation of claim 1 , wherein the cured polymer has a dielectric constant greater than 3.8.5. The radiation curable polymer formulation of claim 1 , wherein the acrylic monomer is isobutyl acrylate claim 1 , tert-butyl acrylate claim 1 , butyl acrylate claim 1 , butyl methacrylate claim 1 , isobornyl acrylate claim 1 , hexyl acrylate claim 1 , 2-ethylhexyl acrylate or 2-hydroxyethyl acrylate.6. The radiation curable polymer formulation of claim 1 , wherein the cross linking agent is glycerol 1 claim 1 ,3-diglycerolate diacrylate claim 1 , 1 claim 1 ,6-hexanediol diacrylate claim 1 , 1 claim 1 ,6-hexanediol dimethacrylate claim 1 , trimethylolpropane triacrylate claim 1 , pentaerythritol triacrylate claim 1 , pentaerythritol tetraacrylate claim 1 , di(trimethylolpropane) tetraacrylate or trimethylolpropane propoxylate triacrylate.7. The radiation curable polymer formulation of claim 1 , wherein the photoinitiator is 4 claim 1 ,4′-bis(dimethylamino)benzophenone or 9 claim 1 , ...

ELECTRONIC ASSEMBLIES INCORPORATING LAMINATE SUBSTRATES AND METHODS OF FABRICATING THE SAME

Electronics assemblies including laminate substrates and methods of manufacture are disclosed. In one embodiment, an electronics assembly (A) includes a glass-based substrate () having a thickness of less than or equal to 300 μm, a first surface () and a second surface, at least one gate electrode () disposed on the first surface () of the glass-based substrate (), and a polymer layer () disposed on the first surface () of the glass-based substrate (). The polymer layer () contacts at least a portion of the at least one gate electrode (). The electronics assembly (A) further includes at least one source electrode (), at least one drain electrode (), and a semiconductor material () disposed on the polymer layer (). The semiconductor material () contacts at least a portion of the at least one source electrode () and the at least one drain electrode (). The polymer layer () is configured to act as a dielectric material between the at least one gate electrode () and the semiconductor material (). 1. An electronics assembly comprising:a glass-based substrate having a thickness of less than or equal to 300 μm, the glass-based substrate comprising a first surface and a second surface;at least one gate electrode disposed on the first surface of the glass-based substrate;a polymer layer disposed on the first surface of the glass-based substrate such that the polymer layer contacts at least a portion of the at least one gate electrode, wherein the polymer layer comprises a polymer surface;a semiconductor material disposed on the polymer surface;at least one source electrode; and the polymer layer is configured to act as a dielectric material between the at least one gate electrode and the semiconductor material; and', 'the at least one gate electrode, a portion of the polymer layer, the at least one source electrode, the at least one drain electrode, and the semiconductor material define at least one electronic device., 'at least one drain electrode, wherein2. The electronics ...

COMPOSITION, ELECTRONIC DEVICE, AND THIN FILM TRANSISTOR

A composition includes a product of a condensation reaction between a thermal cross-linking agent and a product of hydrolysis and condensation polymerization of a compound represented by Chemical Formula 1. 2. The thin film transistor according to claim 1 , wherein R claim 1 , R claim 1 , and Rare independently a Cto Calkoxy group.3. The thin film transistor according to claim 1 , wherein Land Lare independently a Cto Calkylene group.4. The thin film transistor according to claim 1 , wherein Lis —(C═O)—NR″— (wherein claim 1 , R″ is one of hydrogen and a Cto Chydrocarbon radical).5. The thin film transistor according to claim 1 , wherein Ris one of hydrogen and a methyl group.6. The thin film transistor according to claim 1 , wherein the thermal cross-linking agent is at least one metal acetate compound claim 1 , the metal selected from a group consisting of aluminum claim 1 , zirconium claim 1 , titanium claim 1 , magnesium claim 1 , hafnium claim 1 , and tin.7. The thin film transistor according to claim 1 , wherein the thermal cross-linking agent is at least one selected from a group consisting of aluminum acetoacetate claim 1 , zirconium acetoacetate claim 1 , titanium acetoacetate claim 1 , magnesium acetoacetate claim 1 , hafnium acetoacetate claim 1 , and tin acetoacetate.8. The thin film transistor according to claim 1 , wherein the thermal cross-linking agent is included in an amount of less than or equal to about 40 parts by weight based on 100 parts by weight of the product of hydrolysis and condensation polymerization of the compound represented by Chemical Formula 1.9. The thin film transistor according to claim 1 , wherein the thermal cross-linking agent is included in an amount of about 0.01 to 30 parts by weight based on 100 parts by weight of the product of hydrolysis and condensation polymerization of the compound represented by Chemical Formula 1.10. The thin film transistor according to claim 1 , further comprising:a nanoparticle linked to the ...

Thin film transistor

A thin film transistor is provided. The thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, a transition layer, an insulating layer and a gate electrode. The drain electrode is spaced apart from the source electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconductor layer by the insulating layer. The transition layer is sandwiched between the insulating layer and the semiconductor layer. The transition layer is a silicon-oxide cross-linked polymer layer including a plurality of Si atoms. The plurality of Si atoms is bonded with atoms of the insulating layer and atoms of the semiconductor layer.

Hybrid high electron mobility transistor and active matrix structure

Hybrid high electron mobility field-effect transistors including inorganic channels and organic gate barrier layers are used in some applications for forming high resolution active matrix displays. Arrays of such high electron mobility field-effect transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes. The organic gate barrier layers are operative to suppress both electron and hole transport between the inorganic channel layer and the gate electrodes of the high electron mobility field-effect transistors.

DUAL GATE DEVICE AND MANUFACTURING METHOD THEREOF

The embodiment of the disclosure discloses a method of manufacturing the dual gate device, comprising: forming a first metal layer on a substrate; patterning the first metal layer through a first mask to form a bottom gate electrode; coating a first organic isolation layer on the bottom gate electrode and the substrate; sputtering a second metal layer on the first organic isolation layer; patterning the second metal layer to form a source-drain electrode; disposing an organic semiconductor layer, a second organic isolation layer and a third metal layer sequentially on the source-drain electrode and the first organic isolation layer; and patterning the organic semiconductor layer, the second organic isolation layer and the third metal layer through a third mask to form a top gate electrode. The top gate electrode overlapping the source-drain electrode makes the dual gate device to reduce the device contact resistance and saves the power consumption. 1. A method of manufacturing a dual gate device , comprising:forming a first metal layer on a substrate;patterning the first metal layer through a first mask to form a bottom gate electrode;coating a first organic isolation layer on the bottom gate electrode and the substrate;sputtering a second metal layer on the first organic isolation layer;patterning the second metal layer through a second mask to form a source-drain electrode;disposing an organic semiconductor layer, a second organic isolation layer and a third metal layer sequentially on the source-drain electrode and the first organic isolation layer; andpatterning the organic semiconductor layer, the second organic isolation layer and the third metal layer through a third mask to form a top gate electrode.2. The method of manufacturing the dual gate device according to claim 1 , wherein the first organic isolation layer covers the bottom gate electrode; the organic semiconductor layer covers the source-drain electrode; the top gate electrode overlaps the source- ...

TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

The present invention relates to a transistor and a method for manufacturing the same. The transistor according to an embodiment of the present invention includes a substrate, a drain electrode formed on the substrate, a source electrode formed on the substrate and spaced apart from the drain electrode, a channel layer formed on the substrate and including a channel region electrically connecting the drain electrode and the source electrode to each other, a gate electrode formed on the substrate and spaced apart from the channel region, and a liquid crystal layer formed on the substrate to connect the channel layer and the gate electrode to each other. 1. A transistor comprising:a substrate;a drain electrode on the substrate;a source electrode on the substrate, the source electrode being spaced apart from the drain electrode;a channel layer on the substrate, the channel layer comprising a channel region electrically connecting the drain electrode and the source electrode to each other;a gate electrode on the substrate, the gate electrode being spaced apart from the channel region; anda liquid crystal layer on the substrate, the liquid crystal layer connecting the channel layer and the gate electrode to each other.2. The transistor of claim 1 , wherein the liquid crystal layer is in contact with both a top surface of the channel region and the gate electrode.3. The transistor of claim 1 , wherein the gate electrode is disposed in a region opposite to the channel region with respect to the drain electrode or the source electrode.4. The transistor of claim 1 , wherein the liquid crystal layer comprises liquid crystal molecules of which molecular orientations are changed according to a voltage of the gate electrode.5. The transistor of claim 1 , wherein the liquid crystal layer comprises nematic liquid crystal molecules.6. The transistor of claim 1 , wherein the liquid crystal layer comprises 4-cyano-4′pentylbiphenyl.7. The transistor of claim 1 , wherein the channel ...

ORGANIC THIN FILM TRANSISTOR, AND FABRICATING METHOD THEREOF

In accordance with various embodiments of the disclosed subject matter, an organic thin film transistor, and a fabricating method thereof are provided. In some embodiments, the method for forming an organic thin film transistor (OTFT), comprising: forming a transparent gate layer on a transparent base substrate; forming a first initial silicone polymer layer on the transparent gate layer; and performing an oxidization process to partially oxidize the first initial silicone polymer layer to form a gate insulating layer, including an oxidized inorganic sub-layer that contacts the transparent gate layer, and a non-oxidized organic sub-layer 126-. (canceled)27. A method for forming an organic thin film transistor (OTFT) , comprising:forming a transparent gate layer on a transparent base substrate;forming a first initial silicone polymer layer on the transparent gate layer; andperforming an oxidization process to partially oxidize the first initial silicone polymer layer to form a gate insulating layer, including an oxidized inorganic sub-layer that contacts the transparent gate layer, and a non-oxidized organic sub-layer.28. The method of claim 27 , wherein forming a first initial silicone polymer layer on the transparent gate comprises:forming a polydimethylsiloxane film, or a derivative of polydimethylsiloxane film on the transparent gate.29. The method of claim 28 , wherein the derivative of polydimethylsiloxane film is a hydroxylated polydimethylsiloxane film.30. The method of claim 27 , wherein performing an oxidization process to partially oxidize the first initial silicone polymer layer comprises:{'sub': '2', 'performing an ultraviolet radiation treatment to partially oxidize the first initial silicone polymer layer to form the gate insulating layer, wherein the oxidized inorganic sub-layer is a SiOsub-layer, and the non-oxidized organic sub-layer is an initial silicone polymer sub-layer; and'}performing a low-temperature solidifying process to cure the gate ...

SEMICONDUCTOR DEVICE AND INSULATING LAYER-FORMING COMPOSITION

Provided is a semiconductor device which includes a semiconductor layer and an insulating layer adjacent to the semiconductor layer, in which the insulating layer is formed of a crosslinked product of a polymer compound that has a repeating unit (IA) represented by the following Formula (IA) and a repeating unit (IB) represented by the following Formula (IB); and an insulating layer-forming composition which is used for forming an insulating layer of a semiconductor device and contains a polymer compound that has the following repeating units (IA) and (IB). 4. The thin-film transistor according to claim 1 ,wherein X represents an epoxy group or an oxetanyl group.7. The thin-film transistor according to claim 1 ,{'sup': '1b', 'wherein Lrepresents a single bond.'}8. The thin-film transistor according to claim 1 ,wherein the semiconductor layer contains an organic semiconductor. This application is a Continuation of PCT International Application No. PCT/JP2015/062066 filed on Apr. 21, 2015, which claims priority under 35 U.S.C. §119 (a) to Japanese Patent Application No. JP2014-097186 filed in Japan on May 8, 2014. Each of the above applications is hereby expressly incorporated by reference, in its entirety, into the present application.1. Field of the InventionThe present invention relates to a semiconductor device and an insulating layer-forming composition.2. Description of the Related ArtDisplay devices such as a liquid crystal display, an organic EL display, and an electrophoretic display include a semiconductor device such as a thin-film transistor (hereinafter, referred to as a “TFT”).A TFT includes a gate electrode, a gate insulating layer, a source electrode, and a drain electrode and has a structure in which the source electrode and the drain electrode are connected to each other through a semiconductor layer. In the TFT, if a voltage is applied to the gate electrode, a channel of a current is formed on the interface between the semiconductor layer between ...

DISPLAY PANEL, DISPLAY DEVICE AND DRIVING METHOD THEREOF

The present disclosure discloses a display panel, a display device and a driving method thereof. The display panel comprises: a first substrate and a second substrate arranged opposite to each other, and liquid crystals disposed between the first substrate and the second substrate, the first substrate comprising a plurality of gate lines and a plurality of data lines, wherein the first substrate is provided with a plurality of pixel regions distributed in an array, each of the plurality of pixel regions being provided with liquid crystals having four initial pretilt angles and comprising a first sub-pixel region and a second sub-pixel region arranged in a scanning direction, each of the first sub-pixel region and the second sub-pixel region being provided with one thin film transistor; each of the plurality of gate lines is connected to gates of all the thin film transistors in a row of pixel regions, each of the plurality of data lines being connected to a first electrode of all the thin film transistors in a column of pixel regions, the first electrode being one of a source and a drain; and the display panel further comprises a driving circuit for providing different gate turn-on voltages to two adjacent gate lines. 1. A display panel , comprising: a first substrate and a second substrate arranged opposite to each other , and liquid crystals disposed between the first substrate and the second substrate , the first substrate comprising a plurality of gate lines and a plurality of data lines , whereinthe first substrate is provided with a plurality of pixel regions distributed in an array, each of the plurality of pixel regions being provided with liquid crystals having four initial pretilt angles and comprising a first sub-pixel region and a second sub-pixel region arranged in a scanning direction, and each of the first sub-pixel region and the second sub-pixel region being provided with one thin film transistor;each of the plurality of gate lines is connected to ...

ORGANIC THIN FILM TRANSISTORS AND THE USE THEREOF IN SENSING APPLICATIONS

The present invention relates to organic thin film transistors and the preparation and use thereof in sensing applications, and in particular in glucose sensing applications. 1. An organic thin film transistor based sensor device , the device including:(i) a gate electrode;(ii) a dielectric layer;(iii) a semiconducting layer including at least one organic compound;(iv) a source electrode;(v) a drain electrode;(vi) a substrate; and(vii) an enzyme located in, or forming part of any one of (i)-(vi),wherein the device has top gate bottom contact configuration such that the gate electrode is disposed above the dielectric layer, and the dielectric layer is disposed above the semiconducting layer.2. The device of claim 1 , wherein the semiconducting layer is disposed above and in between the source electrode and the drain electrode.3. The device of claim 1 , wherein the source electrode and the drain electrode are disposed above the substrate.4. The device of claim 1 , wherein the gate electrode comprises a porous matrix.5. The device of claim 4 , wherein the porous matrix is a sulfonated tetrafluoroethylene-based fluoropolymer-copolymer.6. The device of claim 5 , wherein the sulfonated tetrafluoroethylene-based fluoropolymer-copolymer is a copolymer comprising a tetrafluoroethylene backbone and perfluoroalkyl ether groups terminated with sulfonate groups.7. The device of claim 6 , wherein the sulfonated tetrafluoroethylene-based fluoropolymer-copolymer is ethanesulfonic acid claim 6 , 2-[1-[difluoro[(1 claim 6 ,2 claim 6 ,2-trifluoroethenyl)oxy]methyl]-1 claim 6 ,2 claim 6 ,2 claim 6 ,2-tetrafluoroethoxy]-1 claim 6 ,1 claim 6 ,2 claim 6 ,2-tetrafluoro- claim 6 , polymer with 1 claim 6 ,1 claim 6 ,2 claim 6 ,2-tetrafluoroethene.8. The device of claim 1 , wherein the dielectric layer comprises poly(4-vinylphenol) or lithium perchlorate-doped poly(4-vinylpyridine).9. The device of claim 1 , wherein the enzyme is located in claim 1 , or forms part of claim 1 , the gate ...

LIQUID CRYSTAL DISPLAY DEVICE

The present invention provides a liquid crystal display device including: a liquid crystal panel including a viewing surface side substrate, a liquid crystal layer, and a back surface side substrate; and a backlight including a reflector facing the back surface side substrate, wherein the liquid crystal panel in a plan view includes multiple pixel regions and a non-display region between the pixel regions, in the pixel regions, color filters are disposed, in the non-display region, a gate electrode layer, a source-drain electrode layer, and a semiconductor layer are disposed, the back surface side substrate includes a reflective surface facing the backlight in at least part of the non-display region, and the reflective surface is constituted by a metal material having a higher reflectance than a metal material contained in portions of the source-drain electrode layer that are connected to the semiconductor layer. 1. A liquid crystal display device comprising: a viewing surface side substrate,', 'a liquid crystal layer, and', 'a back surface side substrate; and, 'a liquid crystal panel including'}a backlight including a reflector facing the back surface side substrate,wherein the liquid crystal panel in a plan view includes multiple pixel regions and a non-display region between the pixel regions,in the pixel regions, color filters are disposed,in the non-display region, a gate electrode layer, a source-drain electrode layer, and a semiconductor layer are disposed,the back surface side substrate includes a reflective surface facing the backlight in at least part of the non-display region, andthe reflective surface is constituted by a metal material having a higher reflectance than a metal material contained in portions of the source-drain electrode layer that are connected to the semiconductor layer.2. The liquid crystal display device according to claim 1 ,wherein the semiconductor layer contains an oxide semiconductor.3. The liquid crystal display device according ...

COMPOSITION FOR SURFACE-MODIFYING INSULATOR, METHOD FOR SURFACE-MODIFYING INSULATOR, INSULATOR, AND THIN FILM TRANSISTOR

A composition includes a compound including a structural unit represented by the above Chemical Formula 1, and a structural unit represented by the above Chemical Formula 2 on at least one terminal end. 2. The composition of claim 1 , wherein the composition includes one of a compound represented by the following Chemical Formula 3 claim 1 , a compound represented by the following Chemical Formula 4 claim 1 , and a combination thereof:{'br': None, 'sup': a', 'b', 'c', '1', '1', 'a', 'b', 'c, 'sub': 2', '2', '4', 'o', '2', 'p', '2', '2, 'RRRSi-L-CH(CFO)(CFO)CFCH-L-SiRRR\u2003\u2003[Chemical Formula 3]'}{'br': None, 'sub': 2', '4', 'o', '2', 'p', '2', '2, 'sup': 1', 'a', 'b', 'c, 'F—(CFO)(CFO)CFCH-L-SiRRR\u2003\u2003[Chemical Formula 4]'}wherein, in Chemical Formulae 3 and 4,{'sup': a', 'c', 'a', 'c, 'sub': 1', '10', '1', '30, 'each of Rto Rare independently one of a Cto Calkyl group, provided that at least one of Rto Ris a Cto Calkoxy group, a halogen, a hydroxy group, and a carboxyl group,'}{'sup': '1', 'sub': 1', '30', '3', '30', '2', '30', '6', '30, 'Lis one of a single bond, —O—, a substituted or unsubstituted Cto Calkylene group, a substituted or unsubstituted Cto Ccycloalkylene group, a substituted or unsubstituted Cto Calkenylene group, a substituted or unsubstituted Cto Carylene group, and a combination thereof, and'}the o and p are independently integers of 1 or more.3. The composition of claim 2 , wherein the o and p are independently integers of 1 to 100.4. The composition of claim 2 , wherein the o and p are independently integers of 1 to 50.5. The composition of claim 2 , wherein the composition includes the compound represented by Chemical Formula 4.6. The composition of claim 2 , wherein the composition includes the compound represented by Chemical Formula 3.7. The composition of claim 2 , wherein the composition includes both the compound represented by Chemical Formula 3 and the compound represented by Chemical Formula 4.8. The composition of claim 7 ...

NEGATIVE DIFFERENTIAL RESISTANCE DEVICE

A negative differential resistance device includes a dielectric layer having a first surface and a second surface opposing the first surface, a first semiconductor layer that includes a first degenerated layer that is on the first surface of the dielectric layer and has a first polarity, a second semiconductor layer that includes a second degenerated layer that has a region that overlaps the first semiconductor layer and has a second polarity, a first electrode electrically connected to the first semiconductor layer, a second electrode electrically connected to the second semiconductor layer, and a third electrode on the second surface of the dielectric layer and which has a region overlapping at least one of the first semiconductor layer or the second semiconductor layer. 1. A negative differential resistance device , comprising:a dielectric layer comprising a first surface and a second surface opposing the first surface;a first semiconductor layer comprising a first degenerated layer that is on the first surface of the dielectric layer and has a first polarity;a second semiconductor layer comprising a second degenerated layer that comprises a region that overlaps the first semiconductor layer and has a second polarity;a first electrode electrically connected to the first semiconductor layer;a second electrode electrically connected to the second semiconductor layer; anda third electrode on the second surface of the dielectric layer and comprising a region that overlaps at least one of the first semiconductor layer or the second semiconductor layer.2. The negative differential resistance device of claim 1 ,wherein the first semiconductor layer comprises a p-type semiconductor layer and the second semiconductor layer comprises an n-type semiconductor layer, or the first semiconductor layer comprises an n-type semiconductor layer and the second semiconductor layer comprises a p-type semiconductor layer.3. The negative differential resistance device of claim 2 , ...

THIN-FILM TRANSISTOR, DISPLAY PANEL, AND METHOD FOR PRODUCING A THIN-FILM TRANSISTOR

A thin-film transistor including: a gate electrode that is located above a substrate; a gate insulating layer that faces the gate electrode; a partition that defines an opening and has higher liquid repellency than liquid repellency of the gate insulating layer, the opening having a surface of the gate insulating layer therewithin; a semiconductor layer that faces the gate electrode with the gate insulating layer interposed therebetween and is formed within the opening by an application method; a source electrode and a drain electrode that are electrically connected to the semiconductor layer; and an intermediate layer that is made of the same material as a material of the partition and is located between the gate insulating layer and the semiconductor layer, wherein the intermediate layer is discretely present above the gate insulating layer. 1. A thin-film transistor comprising:a gate electrode that is located above a substrate;a gate insulating layer that faces the gate electrode;a partition that defines an opening and has higher liquid repellency than liquid repellency of the gate insulating layer, a surface of the gate insulating layer being located in the opening;a semiconductor layer that faces the gate electrode with the gate insulating layer interposed therebetween, and is formed within the opening by an application method;a source electrode and a drain electrode that are electrically connected to the semiconductor layer; andan intermediate layer that is made of the same material as a material of the partition and is located between the gate insulating layer and the semiconductor layer,wherein the intermediate layer is discretely present above the gate insulating layer.2. The thin-film transistor according to claim 1 ,wherein the gate insulating layer on which the intermediate layer is formed has a contact angle against water that is smaller than a contact angle against water of the partition.3. The thin-film transistor according to claim 1 ,wherein the ...

METHOD OF MANUFACTURING A FIELD EFFECT TRANSISTOR USING CARBON NANOTUBES AND A FIELD EFFECT TRANSISTOR

In a method of forming a gate-all-around field effect transistor (GAA FET), a bottom support layer is formed over a substrate and a first group of carbon nanotubes (CNTs) are disposed over the bottom support layer. A first support layer is formed over the first group of CNTs and the bottom support layer such that the first group of CNTs are embedded in the first support layer. A second group of carbon nanotubes (CNTs) are disposed over the first support layer. A second support layer is formed over the second group of CNTs and the first support layer such that the second group of CNTs are embedded in the second support layer. A fin structure is formed by patterning at least the first support layer and the second support layer. 19-. (canceled)10. A method of forming a gate-all-around field effect transistor (GAA FET) , the method comprising:forming a fin structure, in which carbon nanotubes (CNTs) are embedded in a support material, over a substrate;forming a sacrificial gate structure over the fin structure;forming a dielectric layer over the sacrificial gate structure and the fin structure;removing the sacrificial gate structure so that a part of the fin structure is exposed;removing the support material from the exposed part of the fin structure so that channel regions of CNTs are exposed; andforming a gate structure around the exposed channel regions of CNTs.11. The method of claim 10 , wherein the support material includes a polycrystalline or amorphous material of one of Si claim 10 , Ge and SiGe.12. The method of claim 10 , wherein the support material includes a dielectric material different from the dielectric layer.13. The method of claim 10 , further comprising:forming an opening in the dielectric layer and the support material so that source/drain regions of the CNTs are exposed; andforming one or more conductive layers in the opening around the exposed source/drain regions of the CNTs.14. The method of claim 10 , wherein in the fin structure claim 10 , ...

RESIN AND PHOTOSENSITIVE RESIN COMPOSITION

A resin and a photosensitive resin composition whereby a cured film exhibiting high extensibility, reduced stress, and high adhesion to metals can be obtained are provided. A resin (A) including a polyamide structure and at least any structure of an imide precursor structure and an imide structure, wherein at least any of the structures of the resin (A) include a diamine residue having an aliphatic group. 1. A resin (A) comprising a polyamide structure and at least any structure of an imide precursor structure and an imide structure , wherein at least any of the structures of the resin (A) comprises a diamine residue having an aliphatic group.3. The resin according to claim 1 , wherein the diamine residue having an aliphatic group comprises a structural unit of the general formula (6) and wherein the content of the structural unit derived from the diamine having an aliphatic group is in a range of 5% to 40% by mole based on 100% by mole of structural units derived from all diamines:{'br': None, 'sup': 3', '4', '5', '6, 'sub': a', 'b', 'c, '*\ue8a0R—O\ue8a0\ue8a0R—O\ue8a0\ue8a0R—O\ue8a0R—*\u2003\u2003(6)'} [{'sup': 3', '6, 'sub': 2', '10, 'Rto Reach independently represent a C-Calkylene group;'}, 'a, b, and c each are a integer number within a range of 1≤a≤20, 0≤b≤20, and 0≤c≤20;', 'the sequence of repeating units may be in a block manner or in a random manner; and, in the general formula (6), * represents a chemical bond., 'wherein in the general formula (6),'}4. The resin according to claim 3 , wherein the number average molecular weight of the structural unit of the general formula (6) is 150 to 2 claim 3 ,000.5. A method for producing the resin according to claim 1 , comprising the step of copolymerizing a polyamide structure obtained by polymerization at a temperature of 70° C. to 200° C. with at least any structure of the imide precursor structure and the imide structure.6. A photosensitive resin composition comprising the resin according to and a ...

SOLUBLE CYCLIC IMIDES CONTAINING POLYMERS AS DIELECTRICS IN ORGANIC ELECTRONIC APPLICATIONS

The present invention relates to an electronic device comprising a dielectric material, which dielectric material comprises a copolymer comprising styrene and maleimic acid and derivatives thereof as structural units, a process for the preparation of the electronic device and to the use of the copolymer as dielectric material, especially as dielectric layer in printed electronic devices such as capacitors and organic field-effect transistors. 2. The electronic device of claim 1 , wherein the device is selected from a capacitor claim 1 , a transistor claim 1 , an organic field effect transistor claim 1 , or a device comprising said capacitor claim 1 , said transistor claim 1 , or said organic field effect transistor; where the dielectric layer is in contact with a semiconductor layer.315.-. (canceled)16. The electronic device of claim 1 , wherein the structural units of formulae (I) and (II) are present in a mole ratio of (I) to (II) in a range of from 20:1 to 1:5.17. The electronic device of claim 1 , wherein R claim 1 , R claim 1 , R claim 1 , Rare H and wherein Ris H or halogen claim 1 , linear or branched Calkyl claim 1 , formyl claim 1 , Calkyl-carbonyl claim 1 , Calkenyl claim 1 , Calkynyl claim 1 , Calkenyl-carbonyl claim 1 , Ccycloalkyl claim 1 , Ccycloalkenyl claim 1 , Caryl claim 1 , Carylalkyl or Calkylaryl claim 1 , each of which carbon atom chains is either uninterrupted or interrupted by one or more oxygen atoms claim 1 , —C(O)O— claim 1 , —OC(O)— claim 1 , —S— claim 1 , —SO— claim 1 , —N(H)— claim 1 , —N(Calkyl)- and/or —C(O)N(H)— claim 1 , and each of which is unsubstituted or substituted one or more times by one or more moieties —OR claim 1 , —NH claim 1 , —N(H)R claim 1 , —NR claim 1 , —N claim 1 , -halogen and/or —SOH.18. The electronic device of claim 1 , wherein R claim 1 , R claim 1 , Rare H and wherein Rand Rform a cyclic structure with each other having from 5 to 8 C atoms claim 1 , optionally interrupted by one or more oxygen atoms claim 1 , ...

NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

A non-volatile memory device includes a gate electrode, a data storage layer provided on the gate electrode, and a source electrode and a drain electrode provided on the data storage layer and spaced apart from each other. The data storage layer comprises three layers that form hetero-interfaces and have different permittivities from one another. 1. A non-volatile memory device comprising:a gate electrode;a data storage layer provided on the gate electrode; anda source electrode and a drain electrode provided on the data storage layer and spaced apart from each other,wherein the data storage layer comprises three layers which form hetero-interfaces and have different permittivities from one another.2. The non-volatile memory device of claim 1 , wherein the three layers are a gate dielectric layer claim 1 , an interlayer claim 1 , and an organic semiconductor layer claim 1 , which are sequentially stacked on the gate electrode and each have a different dielectric constant from one another.3. The non-volatile memory device of claim 2 , wherein a dielectric constant of the interlayer is greater than a dielectric constant of the gate dielectric layer and a dielectric constant of the organic semiconductor layer.4. The non-volatile memory device of claim 3 , wherein the dielectric constant of the interlayer is in a range of about 12 to about 16 claim 3 , and the dielectric constants of the gate dielectric layer and the organic semiconductor layer are each in a range of about 1 to about 5.5. The non-volatile memory device of claim 4 , wherein the interlayer comprises a self-doped polymer or a polyacetylene derivative.6. The non-volatile memory device of claim 5 , wherein the interlayer comprises a self-doped aniline derivative.7. The non-volatile memory device of claim 6 , wherein the interlayer is self-doped poly(o-anthranilic acid).8. The non-volatile memory device of claim 4 , wherein the gate dielectric layer comprises an organic polymer.9. The non-volatile memory ...

FORMING DIELECTRIC FOR ELECTRONIC DEVICES

A method of forming a stack of layers defining one or more electronic devices, the method comprising: depositing a first thickness of curable, dielectric or dielectric precursor material over an area of a workpiece; thereafter exposing the workpiece to curing conditions at least over said area of said workpiece; and without any intermediate patterning operation, thereafter depositing a second thickness of said curable material over said area of said workpiece; and thereafter again exposing the workpiece to curing conditions at least over said area of said workpiece. 1. A method of forming a stack of layers defining one or more electronic devices , the method comprising: depositing a first thickness of curable , dielectric or dielectric precursor material over an area of a workpiece; thereafter exposing the workpiece to curing conditions at least over said area of said workpiece; and without any intermediate patterning operation , thereafter depositing a second thickness of said curable material over said area of said workpiece; and thereafter again exposing the workpiece to curing conditions at least over said area of said workpiece.2. The method according to claim 1 , wherein said one or more electronic devices include one or more transistors and said dielectric or dielectric precursor material is a gate dielectric or gate dielectric precursor material.3. The method according to claim 1 , wherein exposing the workpiece to curing conditions comprises exposing the workpiece to curing radiation at least over said area of said workpiece.4. The method according to claim 1 , wherein the first and second thicknesses are substantially equal.5. The method according to claim 3 , wherein the curable material is a cross-linkable material claim 3 , and the curing radiation is at one or more wavelengths that induce cross-linking of the cross-linkable material.6. The method according to claim 1 , comprising: after said first curing and before depositing said second thickness of ...

THIN FILM TRANSISTOR

A thin film transistor according to the inventive concept includes: a substrate; an insulating layer provided on the substrate; a superlattice channel layer provided on the insulating layer; and a source electrode and a drain electrode configured to cover a pair of opposite lateral surfaces of the superlattice channel layer, wherein the superlattice channel layer includes alternately stacked semiconductor layers and organic layers. A thickness of each semiconductor layer may be greater than about 3 nm to less than about 5 nm, and a thickness of each organic layer may be about 1 Å to about 1 nm. 1. A thin film transistor , comprising:a substrate;an insulating layer provided on the substrate;a superlattice channel layer provided on the insulating layer; anda source electrode and a drain electrode configured to cover a pair of opposite lateral surfaces of the superlattice channel layer, whereinthe superlattice channel layer comprises alternately stacked semiconductor layers and organic layers,a thickness of each semiconductor layer being greater than about 3 nm to less than about 5 nm, anda thickness of each organic layer being about 1 Å to about 1 nm.2. The thin film transistor of claim 1 , whereinthe semiconductor layers comprise first to third semiconductor layers, which are separated vertically,the organic layers comprise first to fourth organic layers, which are separated vertically, anda ratio of a thickness of any one among the organic layers with respect to a thickness of any one among the semiconductor layers is about 0.1 to about 0.25.3. The thin film transistor of claim 1 , wherein the semiconductor layers comprise a metal oxide or a transition metal dichalcogenide.5. The thin film transistor of claim 1 , whereinthe source electrode comprises a first part provided on a top of the superlattice channel layer, and a second part connected with the first part and extended in parallel to the lateral surface of the superlattice channel layer, andthe second part of ...

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

In a method of manufacturing a gate-all-around field effect transistor, a trench is formed over a substrate. Nano-tube structures are arranged into the trench, each of which includes a carbon nanotube (CNT) having a gate dielectric layer wrapping around the CNT and a gate electrode layer over the gate dielectric layer. An anchor layer is formed in the trench. A part of the anchor layer is removed at a source/drain (S/D) region. The gate electrode layer and the gate dielectric layer are removed at the S/D region, thereby exposing a part of the CNT at the S/D region. An S/D electrode layer is formed on the exposed part of the CNT. A part of the anchor layer is removed at a gate region, thereby exposing a part of the gate electrode layer of the gate structure. A gate contact layer is formed on the exposed part of the gate electrode layer. 1. A semiconductor device having a gate-all-around field effect transistor , comprising:nano-tube structures, each having a source/drain region and a channel region;a gate dielectric layer wrapping around the channel region of each of the nano-tube structure;a gate electrode layer disposed over the gate dielectric layer and wrapping around the channel region of each of the nano-tube structure,wherein the nano-tube structures with the gate dielectric layer and the gate electrode layer are disposed in a trench formed above a substrate.2. The semiconductor device of claim 1 , wherein each of the nano-tube structures includes a carbon nanotube (CNT).3. The semiconductor device of claim 2 , wherein ends of the nano-tube structures are embedded in an anchor layer disposed in the trench.4. The semiconductor device of claim 3 , wherein the trench is formed in a first insulating layer made of a first insulating material.5. The semiconductor device of claim 4 , wherein:the trench has a width W, a length L and a depth D, andL is in a range from 50 nm to 2000 nm, W is in a range from 10 nm to 100 nm, and D is in a range from 20 nm to 200 nm.6. ...

Transistor with Organic Semiconductor Interface

A method is provided for preparing an interface surface for the deposition of an organic semiconductor material, in the fabrication of an organic thin film transistor (OTFT). A substrate is provided and a gate electrode is formed overlying the substrate. A gate dielectric is formed overlying the gate electrode. Then, source (S) and drain (D) electrodes are formed overlying the gate dielectric, exposing a gate dielectric channel interface region between the S/D electrodes. Subsequent to exposing the OTFT to a Hor Nplasma, a self-assembled organic monolayer is formed overlying the S/D electrodes. Finally, an active organic semiconductor layer is formed over the S/D electrodes and gate dielectric channel interface. The OTFT may be exposed to plasma either before or after the formation of the S/D electrodes. 115-. (canceled)16. A printed organic thin film transistor (OTFT) comprising:a substrate;a gate electrode printed over the substrate;a gate dielectric printed over the gate electrode;source (S) and drain (D) electrodes printed over the gate dielectric;a self-assembled organic monolayer overlying the S and D electrodes;an active organic semiconductor layer printed over the S and D electrodes and gate dielectric channel interface; and,{'sup': 2', '2, 'wherein the OTFT has a linear mobility of greater than about 0.6 square centimeters per volt second (cm/Vs), and a saturation mobility of greater than about 0.6 cm/Vs.'}17. The OTFT of wherein the gate dielectric is a material selected from a group consisting of organic semiconductors claim 16 , ultra violet (UV) cross-linked organic polymers claim 16 , and thermally cross-linked polymers.18. The OTFT of wherein the active organic semiconductor is a material selected from a group consisting of small molecule organic semiconductors claim 16 , polymeric organic semiconductors claim 16 , and blends of the above-mentioned materials.19. A printed organic thin film transistor (OTFT) claim 16 , the OTFT comprising:a substrate;a ...

FIELD-EFFECT TRANSISTOR COMPRISING A LEAKAGE-CURRENT LIMITER

A field-effect transistor including at least one lower substrate having two electrodes deposited thereon, respectively a source electrode and a drain electrode, a dielectric layer made of a dielectric material, and a gate electrode deposited on the dielectric layer. It includes an intermediate layer, made of a material comprising molecules having a dipole moment complying with specific direction criteria, deposited between the gate electrode and the dielectric layer, said intermediate layer extending at least under the entire surface area taken up by the gate electrode, the intermediate layer being made of an organic compound comprising at least one binding function for the gate electrode. 1. A field-effect transistor comprising at least one lower substrate having two electrodes deposited thereon , respectively a source electrode and a drain electrode , a dielectric layer made of a dielectric material , and a gate electrode deposited on the dielectric layer ,wherein it comprises an intermediate layer, made of a material comprising molecules having a dipole moment complying with specific direction criteria, deposited between the gate electrode and the dielectric layer, said intermediate layer extending at least under the entire surface area taken up by the gate electrode,and wherein the intermediate layer is made of an organic compound comprising at least one binding function for the gate electrode.2. The field-effect transistor of claim 1 , wherein the organic compound forming the intermediate layer further comprises a spacer formed of a linear claim 1 , branched claim 1 , or cyclic carbon chain and also capable of comprising at least one heteroatom.3. The field-effect transistor of claim 1 , wherein the gate electrode is metallic and wherein the organic compound comprises at least one organosulfur compound.4. The field-effect transistor of claim 1 , wherein at least part of the molecules of the material forming the intermediate layer have a dipole moment directed ...

Curable Polymeric Materials and Their Use for Fabricating Electronic Devices

The present teachings relate to curable linear polymers that can be used as active and/or passive organic materials in various electronic, optical, and optoelectronic devices. In some embodiments, the device can include an organic semiconductor layer and a dielectric layer prepared from such curable linear polymers. In some embodiments, the device can include a passivation layer prepared from the linear polymers described herein. The present linear polymers can be solution-processed, then cured thermally (particularly, at relatively low temperatures) and/or photochemically into various thin film materials with desirable properties. 3. The electronic device of claim 2 , wherein X is CH.8. The electronic device of claim 1 , wherein the linear polymer is partially hydrogenated.9. The electronic device of claim 8 , wherein the linear polymer is partially hydrogenated such that no more than about 50% of the unsaturated bonds in the backbone of the linear polymer are hydrogenated.10. The electronic device of claim 1 , wherein the linear polymer is end-functionalized with a photocrosslinkable moiety selected from the group consisting of an acrylate group and a cinnamate group.11. The electronic device of claim 1 , wherein the organic material comprises a crosslinked matrix of the linear polymer.12. The electronic device of claim 1 , wherein the organic material comprising the linear polymer having a repeating unit of formula (A) is present in an organic layer coupled to the semiconductor layer claim 1 , the gate electrode claim 1 , or the source and drain electrodes claim 1 , the organic layer functioning as a passivation layer or a surface-modifying layer.13. The electronic device of claim 1 , wherein the organic material comprising the linear polymer having a repeating unit of formula (A) is present as an additive in the semiconductor layer.14. The electronic device of claim 1 , wherein the field-effect transistor comprises a dielectric layer coupled to the semiconductor ...

Thin-Film Lead Assemblies And Neural Interfaces

The present disclosure relates to thin-film lead assemblies and neural interfaces, and methods of microfabricating thin-film lead assemblies and neural interfaces. Particularly, aspects of the present disclosure are directed to a thin-film neural interface that includes a proximal end, a distal end, a supporting structure that extends from the proximal end to the distal end, one or more of conductive traces formed on a portion of the supporting structure, one or more electrodes formed on the front side of the supporting structure in electrical connection with the one or more conductive traces, and a backing formed on the back side of the supporting structure. The supporting structure comprises one or more features to facilitate mechanical adhesion between the supporting structure and the backing. 1. A thin-film neural interface comprising:a supporting structure comprised of one or more layers of dielectric material, wherein the supporting structure comprises a front side and a back side;one or more conductive traces formed on the one or more layers of dielectric material;one or more electrodes formed on the front side of the supporting structure in electrical connection with the one or more conductive traces; anda backing formed on the back side of the supporting structure,wherein the backing is comprised of a medical grade polymer material, the supporting structure includes one or more through holes, and the medical grade polymer material fills at least a portion of each of the one or more through holes.25-. (canceled)6. The thin-film neural interface of claim 1 , wherein the supporting structure further comprises opposing edges claim 1 , the backing wraps around the opposing edges from the back side of the supporting structure claim 1 , and the backing is coplanar with the front side of the supporting structure.7. The thin-film neural interface of claim 1 , wherein the supporting structure further comprises opposing edges claim 1 , and the backing wraps around the ...

HIGH DIELECTRIC CONSTANT COMPOSITE MATERIAL AND APPLICATION THEREOF

A high dielectric constant composite material and method for preparing organic thin film transistor using the material as dielectric. The method includes: using sol-gel method, hydrolyzing terminal group-containing silane coupling agent to form functional terminal group-containing silica sol, cross-linked with organic polymer to form composite sol as material of dielectric of organic thin film transistor; forming film by solution method such as spin coating, dip coating, inkjet printing, 3D printing, etc., forming dielectric after curing; preparing semiconductor and electrode respectively to prepare organic thin film transistor device, which, based on composite dielectric material, has mobility of 5 cm2/V·s, exceeding that of using SiO2, having low threshold voltage and no hysteresis effect. Compared with traditional processes like SiO2 thermal oxidation, above method has advantages of simple process, low cost, suitable for large-area preparation, with great market application value. 110-. (canceled)11. A method for preparing a dielectric material , comprising a sol-gel method , a silane coupling agent containing terminal group is co-hydrolyzed under an action of a catalyst to form a silica sol containing functional terminal group , then mixed with an organic polymer to form an organic-inorganic composite sol after a cross-linking reaction , the organic-inorganic composite sol is applied as a material of a dielectric in an organic thin film transistor.12. The method according to claim 11 , wherein the silane coupling agent containing terminal group is selected from a group consisting of: γ-aminopropyltrimethoxysilane claim 11 , aminopropyltriethoxysilane claim 11 , 3-glycidoxypropyltrimethoxysilane claim 11 , γ-methacryloxypropyltrimethoxysilane (KH570) claim 11 , vinyltriethoxysilane claim 11 , vinyltrimethoxysilane claim 11 , N-β-aminoethyl)-γ-aminopropyltriethoxysilane claim 11 , N-β-aminoethyl)-γ-aminopropyltrimethoxysilane claim 11 , γ- ...

THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, DISPLAY SUBSTRATE, AND DISPLAY APPARATUS

Provided is a thin film transistor and a manufacturing method thereof, a display substrate and a display apparatus. The thin film transistor includes a source electrode pattern and a drain electrode pattern arranged on a same layer and a heat dissipation layer arranged between the source electrode pattern and the drain electrode pattern. 1. A thin film transistor , comprising a source electrode pattern and a drain electrode pattern arranged on a same layer , wherein the thin film transistor further comprises:a heat dissipation layer arranged between the source electrode pattern and the drain electrode pattern.2. The thin film transistor according to claim 1 , wherein the heat dissipation layer is made of a polymer carbon nanotube composite material.3. The thin film transistor according to claim 2 , wherein the polymer carbon nanotube composite material is an insulative material.4. The thin film transistor according to claim 1 , wherein a top surface of the heat dissipation layer is coated with a hydrophobic organic film layer; or the top surface of the heat dissipation layer is subjected to plasma treatment.5. The thin film transistor according to claim 1 , further comprising:a substrate; anda buffer layer arranged on the substrate,wherein the source electrode pattern, the drain electrode pattern and the heat dissipation layer are arranged on the buffer layer.6. The thin film transistor according to claim 1 , further comprising:an organic semiconductor layer arranged on the source electrode pattern, the drain electrode pattern and the heat dissipation layer;a first organic dielectric insulation layer arranged on the organic semiconductor layer; anda gate electrode layer arranged on the first organic dielectric insulation layer.7. The thin film transistor according to claim 6 , further comprising:a second organic dielectric insulation layer arranged between the first organic dielectric insulation layer and the gate electrode layer.8. The thin film transistor ...

PHOTO-PATTERNABLE GATE DIELECTRICS FOR OFET

Articles utilizing polymeric dielectric materials for gate dielectrics and insulator materials are provided along with methods for making the articles. The articles are useful in electronics-based devices that utilize organic thin film transistors. 154-. (canceled)55. A formulation comprising:a photo-curable organic polymeric material, a cationic photoinitiator, and propylene glycol monomethyl ether acetate, wherein the photo-curable organic polymeric material has epoxide functional groups.56. The formulation of claim 55 , wherein the photo-curable organic polymeric material has an amount of 4.8 wt %˜12 wt % claim 55 , the cationic photoinitiator has an amount of 0.048 wt %˜0.12 wt % claim 55 , and propylene glycol monomethyl ether acetate has an amount of 87.88 wt %˜95.152 wt % claim 55 , based on the total weight of the formulation.57. The formulation of claim 55 , wherein the photo-curable organic polymeric material comprises poly[(2-oxiranyl)-1 claim 55 ,2-cyclohexanediol]-2-ethyl-2-(hydroxymethyl)-1 claim 55 ,3-propanediol ether and a low molecular weight tetraepoxide both.58. The formulation of claim 57 , wherein the poly[(2-oxiranyl)-1 claim 57 ,2-cyclohexanediol]-2-ethyl-2-(hydroxymethyl)-1 claim 57 ,3-propanediol ether has an amount of 4 wt %˜10 wt % claim 57 , based on the total weight of the formulation.60. The formulation of claim 55 , wherein the cationic photoinitiator is composed of a mixture of triarylsulfonium hexafluoroantiminate salts.61. A dielectric layer comprising the formulation of .62. An article comprising:a substrate having a first surface and a second surface;an organic semiconductor layer;a gate, a source, and a drain electrode; anda dielectric layer,{'claim-ref': {'@idref': 'CLM-00061', 'claim 61'}, 'wherein the dielectric layer is the dielectric layer of .'} This application is a divisional of U.S. patent application Ser. No. 15/066,548 filed on Mar. 10, 2016, which claims the benefit of priority under 35 U.S.C. § 119 of U.S. ...

CROSSLINKABLE POLYMERIC MATERIALS FOR DIELECTRIC LAYERS IN ELECTRONIC DEVICES

Compositions for providing a dielectric layer in an electronic device wherein the composition comprises a polymer which polymer contains one or more building blocks, wherein at least 25 mol % of the total number of building blocks in the polymer are of the general formula having olefinic oligo-dihydrodicyclopentadienyl functionalities. 2. The composition according to claim 1 , wherein{'sub': '1', 'Lis selected from the group consisting of carbonyl, carbonyloxyethyl, carbonyloxyisopropyl, carbonyloxyethylamide, phenyl and benzyl groups;'}{'sub': '2', 'X is CH;'}{'sub': '3', 'R independently is CHor H;'}n is 0.3. The composition according to claim 1 , wherein{'sub': '1', 'Lis a carbonyl or carbonyloxyethyl group;'}{'sub': '3', 'R is CHor H'}n is 0.4. The composition according to claim 1 , wherein{'sub': '1,2', 'Lis a carbonyl unit;'}{'sub': '2', 'X is CH;'}R is H.n is 0.56-. (canceled)7. The composition according to claim 1 , wherein the polymer further comprises a unit derived from a methacrylate having a linear claim 1 , branched or cyclic hydrocarbon group which comprises 1-18 carbon atoms.8. The composition according to claim 1 , wherein the polymer further comprises a unit derived from any of to claim 1 , characterized in that a further unit comprises styrene claim 1 , ethylene claim 1 , methyl vinyl ether or octadecene.1015-. (canceled)16. The composition according to claim 7 , wherein at least some hydrogen atoms of the hydrocarbon group are substituted with fluorine atoms.19. The electronic device according to claim 17 , further comprising an additional polymer.20. The electronic device according to claim 17 , further comprising one or more of a free radical photoinitiator claim 17 , a stabilizer claim 17 , and an adhesion promoter. All of the documents cited in the present patent application are incorporated by reference in their entirety into the present disclosure.The present invention relates to crosslinkable polymers, dielectric layers comprising them, ...

COATING LIQUID FOR GATE INSULATING FILM, GATE INSULATING FILM AND ORGANIC TRANSISTOR

To provide a coating fluid for a gate insulating film, which can be baked at a low temperature of at most 180° C.; a gate insulating film having excellent solvent resistance and further having good characteristics in e.g. specific resistance or semiconductor mobility; and an organic transistor employing the gate insulating film. 110-. (canceled)12. The process according to claim 11 , wherein in the formula (1) claim 11 , A is a tetravalent organic group having an alicyclic structure.14. The process according to claim 11 , wherein in the formula (1) claim 11 , B1 represents the above formula (2) claim 11 , (4) claim 11 , (6) or (8).15. The process according to claim 11 , wherein in the formula (1) claim 11 , Rin B1 represents a methyl group or a trifluoromethyl group.16. The process according to claim 11 , wherein the baking process is carried out at most 150° C.17. The process according to claim 11 , wherein in the organic-solvent soluble polyimide has an imidated ratio of at least 50%.18. The process according to claim 11 , wherein the solvent in the solution containing the organic-solvent soluble polyimide has a boiling point of at most 200° C.19. The process according to claim 11 , wherein in the organic-solvent soluble polyimide comprises a polyimide having a weight average molecular weight from 15 claim 11 ,100 to 16 claim 11 ,900.20. The process according to claim 11 , comprising a polyimide having repeating units B1 in formula (1) at least one selected from the group consisting of the above formula (2) claim 11 , (3) claim 11 , (4) or (5).21. The process according to claim 11 , comprising a polyimide having repeating units B1 in formula (1) at least one selected from the group consisting of the above formula (6) or (7).22. The process according to claim 11 , comprising a polyimide having repeating units B1 in formula (1) at least one selected from claim 11 , the group consisting of the above formula (8) or (9).23. The process according to claim 11 , wherein ...

A SUBSTRATE WITH A POLAR ELASTOMER DIELECTRIC AND A METHOD OF COATING A SUBSTRATE WITH A POLAR ELASTOMER DIELECTRIC

A polar elastomer dielectric layer is formed on a substrate by dynamically dispensing a solution containing the polar elastomer on the substrate and curing it at an elevated temperature. The polar elastomer can include poly(vinylidene fluoride-co-hexa-fluoropropylene) (e-PVDF-HFP). They dynamic dispensing process can include spinning the substrate at a first speed, depositing the polar elastomer solution on the substrate, and spinning the substrate at a second speed. 1. A method of coating a substrate with a polar elastomer , comprising:spinning the substrate at a first speed, wherein the first speed is greater than 0 rpm;depositing the polar elastomer at a center of the substrate;dispersing the polar elastomer across the substrate to form a coated substrate; andspinning the substrate at a second speed based at least in part on the polar elastomer dispersing across the substrate.2. The method of claim 1 , wherein the second speed is greater than the first speed.3. The method of claim 2 , wherein the second speed is approximately 25% or more faster than the first speed.4. The method of claim 1 , wherein the substrate is at least three inches in diameter.5. The method of claim 1 , wherein the polar elastomer forms a coating on the substrate having a thickness that varies no more than ±25%.6. The method of claim 1 , wherein the first speed is approximately 25 rpm to approximately 600 rpm.7. The method of claim 1 , wherein the second speed is approximately 500 rpm to 5 claim 1 ,000 rpm.8. The method of claim 1 , further comprising:crosslinking the polar elastomer.9. The method of claim 1 , wherein the polar elastomer comprises a fluoroelastomer.10. The method of claim 1 , wherein the polar elastomer comprises poly(vinylidene fluoride-co-hexafluoropropylene) (e-PVDF-HFP).11. The method of claim 1 , wherein dispersing the polar elastomer across the substrate comprises:dispersing the polar elastomer in an open air ambient atmosphere.12. The method of claim 1 , further ...

VAPOR-DEPOSITED NANOSCALE IONIC LIQUID GELS AS GATE INSULATORS FOR LOW-VOLTAGE HIGH-SPEED THIN FILM TRANSISTORS

Described are materials and methods for fabricating low-voltage MHz ion-gel-gated thin film transistor devices using patternable defect-free ionic liquid gels. Ionic liquid gels made by the initiated chemical vapor deposition methods described herein exhibit a capacitance of about 1 μF cmat about 1 MHz, and can be as thin as about 20 nm to about 400 nm. 1. A film comprising a crosslinked polymer and an ionic liquid , wherein the ionic liquid is dispersed in the crosslinked polymer; the crosslinked polymer comprises a plurality of residues of a monomer and a plurality of residues of a crosslinker; the film has a thickness of about 20 nm to about 1000 nm; and the film has a capacitance of about 1 μF/cmto about 5 μF/cmat a frequency of about 1 MHz.2. The film of claim 1 , wherein the ionic liquid is selected from the group consisting of: 1-butyl-2 claim 1 ,3-dimethylimidazolium tetrafluoroborate claim 1 , 1-butyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide claim 1 , 1-butyl-3-methylimidazolium hexafluorophosphate claim 1 , 1-butyl-3-methylimidazolium tetrafluoroborate claim 1 , 1-butyl-3-methylpyridinium bis(trifluoromethylsulfonyl)imide claim 1 , 1-butyl-1-methylpyrrolidinium bis(trifluoromethylsulfonyl)imide claim 1 , 1 claim 1 ,2-dimethyl-3-propylimidazolium bis(trifluoromethylsulfonyl)imide claim 1 , 1 claim 1 ,2-dimethyl-3-propylimidazolium tris(trifluoromethylsulfonyl)methide claim 1 , 1-dodecyl-3-methylimidazolium iodide claim 1 , 1-ethyl-2 claim 1 ,3-dimethylimidazolium trifluoromethanesulfonate claim 1 , 1-ethyl-3-methylimidazolium bis(pentafluoroethyl sulfonyl)imide claim 1 , 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide claim 1 , 1-ethyl-3-methylimidazolium dicyanamide claim 1 , 1-ethyl-3-methylimidazolium nitrate claim 1 , 1-ethyl-3-methylimidazolium tetrachloroaluminate claim 1 , 1-ethyl-3-methylimidazolium tetrafluoroborate claim 1 , 1-ethyl-3-methylimidazolium thiocyanate claim 1 , 1-ethyl-3-methylimidazolium ...

SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR ELEMENT MANUFACTURING METHOD

In an organic TFT (), a material used for uppermost layers () of a source electrode () and a drain electrode () has a smaller difference in work function relative to a material used for a semiconductor layer () than does a material used for layers of the source electrode () and the drain electrode () other than the uppermost layers (). The top surfaces and side faces of the uppermost layers of the source electrode () and the drain electrode () contact the semiconductor layer () directly, and the layers of the source electrode () and the drain electrode () other than the uppermost layers are separated from the semiconductor layer () by a second gate insulating layer (). 1. A semiconductor element , comprising:a substrate;a gate electrode on the substrate;a first gate insulating layer disposed on the substrate so as to cover the gate electrode;a source electrode and a drain electrode formed with a gap therebetween on the first gate insulating layer such that, in a plan view, the source electrode and the drain electrode are disposed on respective sides of the gate electrode and both partially overlap the gate electrode through the first gate insulating layer;a second gate insulating layer formed on the first gate insulating layer in at least a region between the source electrode and the drain electrode; anda semiconductor layer formed on the second gate insulating layer and on the source electrode and the drain electrode, said semiconductor layer overlapping the gate electrode through the first gate insulating layer and the second gate insulating layer,wherein the source electrode and the drain electrode each include a plurality of layers,wherein, in each of the source electrode and the drain electrode, an uppermost layer is formed of a material that has a smaller difference in work function relative to the semiconductor layer as compared to other layers respectively constituting the source electrode and the drain electrode, andwherein respective top and side faces of ...

Carbon Enabled Vertical Organic Light Emitting Transistors

Devices, structures, materials and methods for carbon enabled vertical light emitting transistors (VLETs) and light emitting displays (LEDs) are provided. In particular, architectures for vertical polymer light emitting transistors (VPLETs) for active matrix organic light emitting displays (AMOLEDs) and AMOLEDs incorporating such VPLETs are described. Carbon electrodes (such as from graphene) alone or in combination with conjugated light emitting polymers (LEPs) and dielectric materials are utilized in forming organic light emitting transistors (OLETs). Combinations of thin films of ionic gels, LEDs, carbon electrodes and relevant substrates and gates are utilized to construct LETs, including heterojunction VOLETs. 1. A carbon enabled vertical light emitting transistor , comprising:a light emitting cell comprised of a light emitting layer formed of at least one light emitting material, the light emitting layer having first and second sides in conductive relation to a conductive drain electrode and a source electrode;at least one capacitor comprised of a dielectric layer formed of at least one dielectric material, the at least one dielectric layer having first and second sides in conductive relation to one of either the conductive source or drain electrodes, and a conductive gate electrode; andat least one substrate in supportive relation with each of said drain and gate electrodes;wherein the drain and source electrodes are the cathode and anode of the light emitting cell; andwherein at least the electrode disposed between the light emitting layer and the dielectric layer is a gate tunable carbon electrode.2. The vertical light emitting transistor of claim 1 , wherein all of the electrodes are formed of a transparent carbon material.3. The vertical light emitting transistor of claim 1 , wherein the carbon electrode is formed of one or more layers selected from the group of graphene claim 1 , graphene oxide claim 1 , fluorographene claim 1 , graphane claim 1 , ...

ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

An organic light-emitting display apparatus including a substrate; a display unit which defines an active area of the substrate and includes a thin film transistor; concave-convex portions protruded from the substrate in an area outside the active area; and an encapsulation layer which encapsulates the display unit. The thin film transistor includes an active layer, a gate insulating layer on the active layer, a gate electrode, a source electrode, a drain electrode, and an interlayer insulating layer between the gate electrode and the source electrode, and between the gate electrode and the drain electrode. The concave-convex portions include portions of the gate insulating layer and the interlayer insulating layer, and the encapsulation layer covers the concave-convex portions. 1. An organic light-emitting display apparatus comprising:a substrate;a display unit which defines an active area of the substrate, and comprises a thin film transistor and an organic light-emitting device which are connected to each other; andan encapsulation layer which is in the active area and encapsulates the display unit, the encapsulating layer in the active area disposing each of the thin film transistor and the organic light-emitting device between the substrate and the encapsulation layer,wherein a gate insulating layer extending to an area outside the active area, and', 'an interlayer insulating layer on the gate insulating layer and extending to the area outside the active area,, 'the thin film transistor comprisesconcave-convex portions are defined by the interlayer insulating layer in the area outside the active area, andthe encapsulation layer in the active area is extended from the active area to the area outside the active area to contact each of the concave-convex portions, a top surface of the encapsulation layer in the active area being further from the substrate than a top surface of the encapsulation layer outside the active area.2. The organic light-emitting display ...

CARBON NANOTUBE INTERLAYER, MANUFACTURING METHOD THEREOF, AND THIN FILM TRANSISTOR USING THE SAME

The present invention relates to a carbon nanotube interlayer, a manufacturing method thereof, and a thin film transistor using the same. More specifically, the present invention provides a carbon nanotube interlayer, a manufacturing method thereof, and a thin film transistor using the same, where the carbon nanotube interlayer is a layer constituting an organic thin film transistor and comprising a conjugated polymer and a single-walled carbon nanotube between an organic semiconductor layer and a source/drain electrode. The conjugated polymer selectively wraps the single-walled carbon nanotube having semiconducting properties. 1. A carbon nanotube interlayer being a layer constituting an organic thin film transistor ,the carbon nanotube interlayer being a layer comprising a conjugated polymer and a single-walled carbon nanotube between an organic semiconductor layer and a source/drain electrode,wherein the conjugated polymer selectively wraps the single-walled carbon nanotube having semiconducting properties.2. The carbon nanotube interlayer as claimed in claim 1 , wherein the conjugated polymer is fluorene or thiophene polymer.3. The carbon nanotube interlayer as claimed in claim 1 , wherein the carbon nanotube interlayer comprises 0.0001 to 0.015 mg/ml of the single-walled carbon nanotube.4. A method for manufacturing a carbon nanotube interlayer claim 1 , which is a method for manufacturing a layer included in a thin film transistor claim 1 , the method comprising:mixing a conjugated polymer and a single-walled carbon nanotube in a solvent;performing an ultrasonication on the mixed solution;performing a centrifugation using a centrifugal separator to take a supernate; andusing the supernate to form a carbon nanotube interlayer between an organic semiconductor layer and a source/drain electrode,wherein the carbon nanotube interlayer comprises a conjugated polymer and a single-walled carbon nanotube having semiconducting properties,wherein the conjugated polymer ...

CONDUCTIVE ORGANIC SEMICONDUCTOR COMPOUND, METHOD FOR PREPARING THE SAME AND ORGANIC THIN-FILM TRANSISTOR INCLUDING THE SAME

The present disclosure provides an organic semiconductor compound, which has superior charge mobility, low band gap, wide light absorption area and adequate molecular energy level. The conductive organic semiconductor compound of the present disclosure can be used as a material for various organic optoelectric devices such as an organic photodiode (OPD), an organic light-emitting diode (OLED), an organic thin-film transistor (OTFT), an organic solar cell, etc. In addition, it can be prepared into a thin film via a solution process, can be advantageously used to fabricate large-area devices and can reduce the cost of device fabrication. 5. The conductive organic semiconductor compound according to claim 1 , wherein the conductive organic semiconductor compound has an electron mobility of 1×10cm/V·s or higher.6. The conductive organic semiconductor compound according to claim 1 , wherein the conductive organic semiconductor compound has a band gap of 1.0-3.0 eV.7. An organic semiconductor thin film comprising one or more conductive organic semiconductor compound according to .8. An organic thin-film transistor claim 1 , comprising:a substrate;a gate electrode formed on the substrate;an insulating layer formed on the gate electrode;{'claim-ref': {'@idref': 'CLM-00007', 'claim 7'}, 'the organic semiconductor thin film according to formed on the insulating layer; and'}a source electrode layer and a drain electrode layer formed on the organic semiconductor thin film.9. The organic thin-film transistor according to claim 8 , wherein the organic thin-film transistor has a top-contact or bottom-contact structure.10. The organic thin-film transistor according to claim 8 , wherein the gate electrode claim 8 , the source electrode and the drain electrode are selected from a group consisting of gold claim 8 , silver claim 8 , aluminum claim 8 , nickel claim 8 , chromium and indium tin oxide.11. The organic thin-film transistor according to claim 8 , wherein the substrate is ...

COMPOSITION, ELECTRONIC DEVICE, AND THIN FILM TRANSISTOR

A composition includes a product of a condensation reaction between a thermal cross-linking agent and a product of hydrolysis and condensation polymerization of a compound represented by Chemical Formula 1. 2. The composition according to claim 1 , wherein R claim 1 , R claim 1 , and Rare independently a Cto Calkoxy group.3. The composition according to claim 1 , wherein Land Lare independently a Cto Calkylene group.4. The composition according to claim 1 , wherein Lis —(C═O)—NR″— (wherein claim 1 , R″ is one of hydrogen and a Cto Chydrocarbon radical).5. The composition according to claim 1 , wherein Ris one of hydrogen and a methyl group.6. The composition according to claim 1 , wherein the thermal cross-linking agent is at least one metal acetate compound claim 1 , the metal selected from a group consisting of aluminum claim 1 , zirconium claim 1 , titanium claim 1 , magnesium claim 1 , hafnium claim 1 , and tin.7. The composition according to claim 1 , wherein the thermal cross-linking agent is at least one selected from a group consisting of aluminum acetoacetate claim 1 , zirconium acetoacetate claim 1 , titanium acetoacetate claim 1 , magnesium acetoacetate claim 1 , hafnium acetoacetate claim 1 , and tin acetoacetate.8. The composition according to claim 1 , wherein the thermal cross-linking agent is included in an amount of less than or equal to about 40 parts by weight based on 100 parts by weight of the product of hydrolysis and condensation polymerization of the compound represented by Chemical Formula 1.9. The composition according to claim 1 , wherein the thermal cross-linking agent is included in an amount of about 0.01 to 30 parts by weight based on 100 parts by weight of the product of hydrolysis and condensation polymerization of the compound represented by Chemical Formula 1.10. The composition according to claim 1 , further comprising:a nanoparticle linked to the product of hydrolysis and condensation polymerization of the compound represented by ...

PROCESS TO REDUCE PLASMA INDUCED DAMAGE

Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode is disposed over the gate dielectric layer. The gate dielectric layer has a Dof about 5ecmeVto about 5ecmeVand a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm. 1. A method of fabricating a thin film transistor (TFT) , comprising:flowing a deposition gas at a deposition gas flow rate into a process volume of a chamber;applying a radio frequency (RF) power to the deposition gas for an initial interval at an initial power level forming an intermediate layer of a gate dielectric layer, the intermediate layer having a first surface contacting a semiconductor layer at an interface with the first surface; and a thickness consisting essentially of the intermediate layer and the bulk layer, the intermediate layer is not greater than about 20% of the thickness and has a density not greater than the density of the bulk layer; and', {'sub': 'it', 'sup': 10', '−2', '−1', '11', '−2', '−1, 'a breakdown field between about 6 MV/cm and about 10 MV/cm, an interface trap density (D) of about 5ecmeVto about 5ecmeV, and a hysteresis of about 0.10 V to about 0.30 V.'}], 'applying the RF power for a final interval at a final power level different than the first power level forming a bulk layer of the gate dielectric layer having a second surface to contact a gate electrode and an ILD layer to be formed, the gate electrode having2. The method of claim 1 , further comprising forming initial layers of the TFT on a substrate before flowing the deposition gas at the deposition gas flow ...

Flexible and stretchable semiconductor devices with reduced footprints and methods therefor

A method of making flexible and stretchable semiconductor devices with reduced footprints can include coating a gate electrode layer having a first composition over an elastomer layer, solidifying a portion of the gate electrode layer by irradiation to form a gate electrode, coating a dielectric layer having a second composition over the gate electrode layer, solidifying a portion of the dielectric layer by the irradiation to form a gate dielectric, coating a semiconductor layer having a third composition over the dielectric layer, solidifying a portion of the semiconductor layer by the irradiation to form a device core, coating a terminal layer having the first composition over the dielectric layer, and solidifying a portion of the terminal layer by the irradiation to form a source electrode and a drain electrode contacting the semiconductor layer.

PATTERNING METHOD FOR PREPARING TOP-GATE, BOTTOM-CONTACT ORGANIC FIELD EFFECT TRANSISTORS

The present invention relates to a process for the preparation of a top-gate, bottom-contact organic field effect transistor on a substrate, which organic field effect transistor comprises source and drain electrodes, a semiconducting layer, a cured first dielectric layer and a gate electrode, and which process comprises the steps of: i) applying a composition comprising an organic semiconducting material to form the semiconducting layer, ii) applying a composition comprising a first dielectric material and a crosslinking agent carrying at least two azide groups to form a first dielectric layer, iii) curing portions of the first dielectric layer by light treatment, iv) removing the uncured portions of the first dielectric layer, and v) removing the portions of the semiconducting layer that are not covered by the cured first dielectric layer, wherein the first dielectric material comprises a star-shaped polymer consisting of at least one polymer block A and at least two polymer blocks B, wherein each polymer block B is attached to the polymer block A, and wherein at least 60 mol % of the repeat units of polymer block B are selected from the group consisting of Formulas (1A), (1B), (1C), (1D), (1E) and (1F), wherein R, R, R, R, R, R, Rand Rare independently and at each occurrence H or C-C-alkyl. 9. The process of any of to , wherein the weight ratio of polymer block A/total polymer blocks B is from 60/40 to 96/4.10. The process of any of to , wherein the star-shaped polymers have a number average molecular weight Mn of at least 60000 g/mol and a weight average molecular weight Mw of at least 70000 g/mol , both as determined by gel permeation chromatography.13. The process of any of to further comprising step vi) of applying a composition comprising a second dielectric material on top of the cured first dielectric layer to form a second dielectric layer.14. The process of claim 13 , wherein the cured first dielectric layer and the semiconducting layer cover the path ...

ELECTRODE FOR SOURCE/DRAIN OF ORGANIC SEMICONDUCTOR DEVICE, ORGANIC SEMICONDUCTOR DEVICE USING SAME, AND METHOD FOR MANUFACTURING SAME

The present disclosure provides fine electrodes in which an organic semiconductor does not easily change with time, and which can be applied to manufacturing of a practical integrated circuit of an organic semiconductor device. The present disclosure relates to electrodes for source/drain of an organic semiconductor device, comprising 10 or more sets of electrodes, wherein a channel length between the electrodes in each set is 200 μm or less, and the electrodes in each set have a surface with a surface roughness Rq of 2 nm or less. 1. Electrodes for source/drain of an organic semiconductor device , comprising:10 or more sets of electrodes,wherein a channel length between the electrodes in each set is 200 μm or less, and the electrodes in each set have a surface with a surface roughness Rq of 2 nm or less.2. The electrodes for source/drain according to claim 1 , wherein the parallelism of the channel length between the electrodes in the each set is 1 degree or less.3. The electrodes for source/drain according to claim 1 , further comprising a protective film claim 1 , wherein the protective film is composed of an insulating polymer having a thickness of 1 μm or less and a glass transition point of 80° C. or more claim 1 , attached to surfaces opposite to the surfaces of the electrodes in the each set by electrostatic force claim 1 , and extending in at least a part of the channel in the each set.4. The electrodes for source/drain according to claim 1 , wherein the electrodes comprise plating.5. An organic semiconductor device comprising: a gate electrode claim 1 , a gate insulating film claim 1 , an organic semiconductor film claim 1 , and the electrodes for source/drain according to .6. The organic semiconductor device according to claim 5 , wherein a surface roughness Rq of a surface of the organic semiconductor film in contact with the electrodes in each set is equal to or less than 2 nm.7. A method for manufacturing electrodes for source/drain of an organic ...

Organic Dielectric Layer and Organic Electronic Device

The present invention relates to organic dielectric layers comprising a polycycloolefinic polymer with a pendent chromophoric group having an absorption maximum in the wavelength range from 230 to 290 nm, and to organic electronic devices comprising them. 2. The OE device according to claim 1 , wherein the pendent groups are selected from C-Caryl claim 1 , C-Caralkyl claim 1 , C-C-aralkyoxy claim 1 , C-Cheteroaryl claim 1 , C-Cheteroaralkyl and C-Cheteroaralkyloxy claim 1 , all of which are optionally substituted.3. The OE device according to claim 1 , wherein one or more of Rdenote the pendent group which is of formula A:{'br': None, 'sub': 2', 'a', 'o, '—(CH)—(O)-aryl\u2003\u2003A'}whereina is 0 or an integer from 1 to 12,o is 0 or 1,“aryl” denotes an aryl group with 6 to 20 C atoms which is optionally substituted by one or more groups L,{'sub': 2', '2, 'sup': 0', '0', '00', '0', '00', '1', '2, 'L is selected from F, Cl, —OH, —CN, or straight-chain, branched or cyclic alkyl with 1 to 25 C atoms, in which one or more CHgroups are optionally replaced by —O—, —S—, —C(═O)—, —C(═S)—, —C(═O)—O—, —O—C(═O)—, —NR—, —SiRR—, —CF—, —CR═CR—, —CY═CY— or —C≡C— in such a manner that O and/or S atoms are not linked directly to one another, and in which one or more H atoms are optionally replaced by F, Cl, Br, I or CN,'}{'sup': 1', '2, 'Yand Yindependently of each other denote H, F, Cl or CN, and'}{'sup': 0', '00, 'R, Rindependently of each other denote H or straight-chain or branched alkyl with 1 to 20 C atoms that is optionally fluorinated.'}4. The OE device according to claim 1 , wherein Z is —CH—.5. The OE device according to claim 1 , wherein Z is —CH— and m is 0.6. The OE device according to claim 5 , wherein one or more of Rdenote a group having an absorption maximum in the range from 230 to 290 nm which is selected from C-Caryl claim 5 , C-Caralkyl claim 5 , C-C-aralkyoxy claim 5 , C-Cheteroaryl claim 5 , C-Cheteroaralkyl and C-Cheteroaralkyloxy claim 5 , all of which are ...

Organic thin film transistor and method of manufacturing organic thin film transistor

Provided are an organic thin film transistor that has high bendability and can suppress a decrease in carrier mobility caused by a pinhole of an insulating film or leveling properties and a method of manufacturing the organic thin film transistor. The organic thin film transistor includes: a gate electrode; an insulating film that is formed to cover the gate electrode; an organic semiconductor layer that is formed on the insulating film, and a source electrode and a drain electrode that are formed on the organic semiconductor layer, in which the insulating film includes an inorganic film consisting of SiNH.

THIN FILM TRANSISTOR AND METHOD FOR MAKING THE SAME

The disclosure relates to a thin film transistor and a method for making the same. The thin film transistor includes a substrate; a semiconductor layer on the substrate, wherein the semiconductor layer includes nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are on the substrate, spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer on the semiconductor layer, wherein the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer stacked on one another, and the first sub-dielectric layer is a first oxide dielectric layer grown by magnetron sputtering; and a gate in direct contact with the first sub-dielectric layer. The thin film transistor almost has no current hysteresis. 1. A thin film transistor , comprising:a substrate;a semiconductor layer on the substrate, wherein the semiconductor layer comprises a plurality of nano-scaled semiconductor materials;a source and a drain, wherein the source and the drain are on the substrate, spaced apart from each other, and electrically connected to the semiconductor layer;a dielectric layer on the semiconductor layer, wherein the dielectric layer comprises a first sub-dielectric layer and a second sub-dielectric layer stacked on one another, and the first sub-dielectric layer is a first oxide dielectric layer grown by magnetron sputtering; anda gate in direct contact with the first sub-dielectric layer.2. The thin film transistor of claim 1 , wherein the first oxide dielectric layer is a metal oxide dielectric layer.3. The thin film transistor of claim 2 , wherein the metal oxide dielectric layer is an aluminum oxide (AlO) layer.4. The thin film transistor of claim 1 , wherein the first oxide dielectric layer is a silicon dioxide (SiO) layer.5. The thin film transistor of claim 1 , wherein the second sub-dielectric layer is a second oxide dielectric layer or a nitride dielectric layer grown by a method ...

THIN FILM TRANSISTOR AND METHOD FOR MAKING THE SAME

The disclosure relates to a thin film transistor and a method for making the same. The thin film transistor includes a substrate; a gate on the substrate; a dielectric layer on the gate, wherein the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer stacked on one another, and the first sub-dielectric layer is a first oxide dielectric layer formed by magnetron sputtering and in direct contact with the gate; a semiconductor layer on the dielectric layer, wherein the semiconductor layer includes nano-scaled semiconductor materials; and a source and a drain, wherein the source and the drain are on the dielectric layer, spaced apart from each other, and electrically connected to the semiconductor layer. The thin film transistor almost has no current hysteresis. 1. A thin film transistor , comprising:a substrate;a gate on the substrate;a dielectric layer on the gate, wherein the dielectric layer comprises a first sub-dielectric layer and a second sub-dielectric layer stacked on one another, and the first sub-dielectric layer is a first oxide dielectric layer formed by magnetron sputtering and in direct contact with the gate;a semiconductor layer on the dielectric layer, wherein the semiconductor layer comprises a plurality of nano-scaled semiconductor materials; anda source and a drain, wherein the source and the drain are on the dielectric layer, spaced apart from each other, and electrically connected to the semiconductor layer.2. The thin film transistor of claim 1 , wherein the first oxide dielectric layer is a metal oxide dielectric layer.3. The thin film transistor of claim 2 , wherein the metal oxide dielectric layer is an aluminum oxide (AlO) layer.4. The thin film transistor of claim 1 , wherein the first oxide dielectric layer is a silicon dioxide (SiO) layer.5. The thin film transistor of claim 1 , wherein the second sub-dielectric layer is a second oxide dielectric layer or a nitride dielectric layer formed by a method ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate, a channel layer at least one of on or in the substrate, an insulation layer on the substrate, a ferroelectric layer on the insulation layer, a fixed charge layer on an interface between the insulation layer and the ferroelectric layer, the fixed charge layer including charges of a first polarity, and a gate on the ferroelectric layer. 1. A semiconductor device comprising:a substrate;a channel layer at least one of on or in the substrate;an insulation layer on the substrate;a ferroelectric layer on the insulation layer;a fixed charge layer on an interface between the insulation layer and the ferroelectric layer, the fixed charge layer including charges of a first polarity; anda gate on the ferroelectric layer.2. The semiconductor device of claim 1 ,wherein the fixed charge layer has a charge density that generates a negative capacitance effect in response to the channel layer being in an inversion state.3. The semiconductor device of claim 2 ,wherein at least one of the semiconductor device includes a PMOS structure and the fixed charge layer has a negative (−) charge density in the PMOS structure, orthe semiconductor device includes an NMOS structure and the fixed charge layer has a positive (+) charge density in the NMOS structure.4. The semiconductor device of claim 2 ,{'sup': '2', 'wherein the fixed charge layer has a charge density greater than −5 μC/cmand less than 0, or'}{'sup': '2', 'the fixed charge layer has a charge density greater than 0 and less than +5 μC/cm.'}5. The semiconductor device of claim 1 ,wherein the fixed charge layer includes at least one of dopants or an oxygen vacancy.6. The semiconductor device of claim 5 ,wherein the dopants include at least one selected from Al, P, Ca, Sc, V, Cr, Sr, Y, Nb, Mo, Tm, Yb, Lu, Ta, and W.7. The semiconductor device of claim 1 ,wherein the channel layer is in an upper ...

Double-Gate Carbon Nanotube Transistor and Fabrication Method

A method includes depositing a dielectric layer over a substrate, forming carbon nanotubes on the dielectric layer, forming a dummy gate stack on the carbon nanotubes, forming gate spacers on opposing sides of the dummy gate stack, and removing the dummy gate stack to form a trench between the gate spacers. The carbon nanotubes are exposed to the trench. The method further includes etching a portion of the dielectric layer underlying the carbon nanotubes, with the carbon nanotubes being suspended, forming a replacement gate dielectric surrounding the carbon nanotubes, and forming a gate electrode surrounding the replacement gate dielectric. 1. A method comprising:depositing a dielectric layer over a substrate;forming carbon nanotubes on the dielectric layer;forming a dummy gate stack on the carbon nanotubes;forming gate spacers on opposing sides of the dummy gate stack;removing the dummy gate stack to form a trench between the gate spacers, wherein the carbon nanotubes are exposed to the trench;etching a portion of the dielectric layer underlying the carbon nanotubes, wherein the carbon nanotubes are suspended;forming a replacement gate dielectric surrounding the carbon nanotubes; andforming a gate electrode surrounding the replacement gate dielectric.2. The method of claim 1 , wherein the forming the replacement gate dielectric comprises:depositing an interfacial layer encircling the carbon nanotubes, wherein portions of the interfacial layer encircling different ones of the carbon nanotubes are joined to form a continuous interfacial layer; anddepositing a high-k dielectric layer encircling the interfacial layer.3. The method of claim 1 , wherein the forming the replacement gate dielectric comprises:depositing an interfacial layer encircling the carbon nanotubes; anddepositing a high-k dielectric layer encircling the interfacial layer, wherein portions of the interfacial layer encircling different ones of the carbon nanotubes are physically separated from each ...

ULTRALOW POWER CARBON NANOTUBE LOGIC CIRCUITS AND METHOD OF MAKING SAME

A method of fabricating a CMOS logic device with SWCNTs includes forming a plurality of local metallic gate structures on a substrate by depositing a metal on the substrate; forming a plurality of contacts on the substrate; and depositing the SWCNTs on the substrate, and doping a certain area of the SWCNTs to form the CMOS logic device having at least one NMOS transistor and at least one PMOS transistor. Each of the NMOS and PMOS transistors has a gate formed by one of the local metallic gate structures, and a source and a drain formed by two of the contacts respectively. The gate of each PMOS transistor and the gate of each NMOS transistor are configured to alternatively receive at least one input voltage. At least one of the drain of the PMOS transistor and the drain of the NMOS transistor is configured to output an output voltage. 1. A method of fabricating a complementary metal-oxide-semiconductor (CMOS) logic device with single-walled carbon nanotubes (SWCNTs) , comprising:forming a plurality of local metallic gate structures on a substrate by depositing a metal on the substrate;forming a plurality of contacts on the substrate; anddepositing the SWCNTs on the substrate, and doping a certain area of the SWCNTs to form the CMOS logic device having at least one n-type metal-oxide-semiconductor (NMOS) transistor and at least one p-type metal-oxide semiconductor (PMOS) transistor, wherein each of the at least one NMOS transistor and each of the at least one PMOS transistor has a gate formed by one of the local metallic gate structures, and a source and a drain formed by two of the contacts respectively;wherein the gate of each of the at least one PMOS transistor and the gate of each of the at least one NMOS transistor is configured to alternatively receive at least one input voltage; and{'sub': 'OUT', 'wherein at least one of the drain of the at least one PMOS transistor and the drain of the at least one NMOS transistor is configured to output an output voltage V.'} ...

Screen Printing Systems and Techniques for Creating Thin-Film Transistors Using Separated Carbon Nanotubes

A method of fabricating a thin film transistor, the method includes applying a first ink containing metallic particles to a first screen mask, and using the first screen mask to deposit the first ink to form a source electrode and a drain electrode on a substrate bearing a layer of carbon nanotubes (CNT). The method includes applying a second ink containing a dielectric material to a second screen mask, and using the second screen mask to deposit the second ink to form a layer of the dielectric material on the layer of CNT between the source electrode and the drain electrode. The method includes applying a third ink containing metallic particles to a third screen mask, and using the third screen mask to deposit the first ink to form a metallic gate electrode on the layer of the dielectric material to form the thin film transistor. 1. A method of fabricating a thin film transistor , the method comprising:applying a first ink containing metallic particles to a first screen mask;using the first screen mask to deposit the first ink to form a source electrode and a drain electrode on a substrate bearing a layer of carbon nanotubes (CNT);applying a second ink containing a dielectric material to a second screen mask;using the second screen mask to deposit the second ink to form a layer of the dielectric material on the layer of CNT between the source electrode and the drain electrode; andapplying a third ink containing metallic particles to a third screen mask;using the third screen mask to deposit the first ink to form a metallic gate electrode on the layer of the dielectric material to form the thin film transistor.2. The method of claim 1 , further comprising etching away CNT from regions of the substrate not covered by the source electrode claim 1 , the drain electrode and the dielectric material.3. The method of claim 1 , further comprising depositing the CNT on the substrate by immersing the substrate in a solution of CNT.4. The method of claim 3 , wherein the ...

Organic thin film transistor, method of manufacturing organic thin film transistor, organic semiconductor composition, organic semiconductor film, and method of manufacturing organic semiconductor film

An object of the present invention is to provide an organic thin film transistor exhibiting high carrier mobility and a low threshold voltage and having excellent heat resistance, a method of manufacturing an organic thin film transistor, an organic semiconductor composition, an organic semiconductor film, and a method of manufacturing an organic semiconductor film. The organic thin film transistor according to the present invention includes, on a substrate, a gate electrode; an organic semiconductor layer containing an organic semiconductor compound; a gate insulating layer provided between the gate electrode and the organic semiconductor layer; and a source electrode and a drain electrode which are provided to be in contact with the organic semiconductor layer and are connected to each other via the organic semiconductor layer, in which the organic semiconductor layer is in contact with a block copolymer layer containing a block copolymer or further contains the block copolymer, and in which the organic semiconductor compound has a molecular weight of 2,000 or greater and has a repeating unit represented by Formula (1).

TRANSISTOR AND MANUFACTURING METHOD OF TRANSISTOR

A transistor and a manufacturing method of a transistor which prevents a decrease in mobility, prevents a decrease in a withstand voltage of the insulating layer, and prevents a short circuit between a gate electrode and a semiconductor layer due to curvature. A substrate having insulating properties, a source electrode and a drain electrode disposed in a surface direction of a main surface of the substrate by being separated from each other, a gate electrode disposed between the source electrode and the drain electrode in the surface direction of the substrate, a semiconductor layer disposed in contact with the source electrode and the drain electrode, and an insulating film disposed between the gate electrode and the semiconductor layer in a direction perpendicular to the main surface of the substrate are included, and a gap region is formed between the semiconductor layer and the insulating film. 1. A transistor , comprising:a substrate having insulating properties;a source electrode and a drain electrode disposed in a surface direction of a main surface of the substrate by being separated from each other;a gate electrode disposed between the source electrode and the drain electrode in the surface direction of the substrate;a semiconductor layer disposed in contact with the source electrode and the drain electrode; andan insulating film disposed between the gate electrode and the semiconductor layer in a direction perpendicular to the main surface of the substrate,wherein a gap region is formed between the semiconductor layer and the insulating film.2. The transistor according to claim 1 ,wherein the gate electrode is formed on the substrate,the insulating film is formed to cover at least a part of the substrate and the gate electrode,the source electrode and the drain electrode are formed on the insulating film, andthe semiconductor layer is disposed to be in contact with upper surfaces of the source electrode and the drain electrode.3. The transistor according ...

ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

An organic light-emitting display apparatus including a substrate; a display unit which defines an active area of the substrate and includes a thin film transistor; concave-convex portions protruded from the substrate in an area outside the active area; and an encapsulation layer which encapsulates the display unit. The thin film transistor includes an active layer, a gate insulating layer on the active layer, a gate electrode, a source electrode, a drain electrode, and an interlayer insulating layer between the gate electrode and the source electrode, and between the gate electrode and the drain electrode. The concave-convex portions include portions of the gate insulating layer and the interlayer insulating layer, and the encapsulation layer covers the concave-convex portions. 1. An organic light-emitting display apparatus comprising:a substrate;a display unit which defines an active area of the substrate, and comprises a thin film transistor and an organic light-emitting device which are connected to each other; andan encapsulation layer which comprises at least a region in the active area and encapsulates the display unit, the encapsulating layer in the active area disposing each of the thin film transistor and the organic light-emitting device between the substrate and the encapsulation layer,wherein a gate insulating layer extending to an area outside the active area, and', 'an interlayer insulating layer on the gate insulating layer and extending to the area outside the active area,, 'the thin film transistor comprisesconcave-convex portions comprising a metal layer in the area outside the active area, andthe encapsulation layer in the active area is extended from the active area to the area outside the active area, a top surface of the encapsulation layer in the active area being further from the substrate than a top surface of the encapsulation layer in the area outside the active area.2. The organic light-emitting display apparatus of claim 1 , wherein the ...

CONFORMAL ORGANIC FIELD-EFFECT TRANSISTOR, TRANSISTOR ARRAY, AND PREPARATION METHOD THEREOF

A conformal organic field-effect transistor includes an elastic substrate, a gate electrode, a polymer insulating layer, an organic semiconductor layer, and a source electrode and a drain electrode from the bottom up, the source electrode and the drain electrode being embedded in the organic semiconductor layer. A method of forming the conformal organic field-effect transistor includes depositing an organic semiconductor on a substrate surface to form an organic semiconductor layer, the source electrode and the drain electrode are embedded in the organic semiconductor layer; then preparing the polymer insulating layer on a surface of the organic semiconductor layer; transferring the gate electrode from the substrate; forming hydroxyl groups on a metal electrode surface of the gate electrode, a polymer insulating layer surface of the source electrode, and a polymer insulating layer surface of the drain electrode, respectively; and then performing alignment and heating to obtain the conformal organic field-effect transistor. 1. A conformal organic field-effect transistor , comprising an elastic substrate , a gate electrode , a polymer insulating layer , an organic semiconductor layer , and a source electrode and a drain electrode from the bottom up ,wherein the source electrode and the drain electrode are embedded in the organic semiconductor layer.2. The conformal organic field-effect transistor according to claim 1 , wherein the elastic substrate is formed of an elastic insulating material claim 1 , which is organosilicone claim 1 , polymethylsiloxane claim 1 , polydimethylsiloxane claim 1 , or polyurethane.3. The conformal organic field-effect transistor according to claim 1 , wherein the polymer insulating layer is formed by an insulating polymer claim 1 , which is organosilicone claim 1 , polymethylsiloxane claim 1 , polydimethylsiloxane claim 1 , polyurethane claim 1 , or polyvinyl alcohol.4. A preparation method of the conformal organic field-effect transistor ...

N-TYPE THIN FILM TRANSISTOR

An thin film transistor includes an insulating substrate, an MgO layer, a semiconductor carbon nanotube layer, a functional dielectric layer, a source electrode, a drain electrode, and a gate electrode. The semiconductor carbon nanotube layer is sandwiched between the MgO layer and the functional dielectric layer. The source electrode and the drain electrode electrically connect the semiconductor carbon nanotube layer. The gate electrode is sandwiched between the insulating substrate and the MgO layer.

N-TYPE THIN FILM TRANSISTOR

An N-type semiconductor layer includes an insulating substrate, an MgO layer, a semiconductor carbon nanotube layer, a functional dielectric layer, a source electrode, a drain electrode, and a gate electrode. The semiconductor carbon nanotube layer is sandwiched between the MgO layer and the functional dielectric layer. The source electrode and the drain electrode electrically connect the semiconductor carbon nanotube layer. The gate electrode is on the functional dielectric layer and insulated from the semiconductor carbon nanotube layer. 1. An N-type thin film transistor , comprising:an insulating substrate;an MgO layer on the insulating substrate;a semiconductor carbon nanotube layer on the MgO layer, wherein the semiconductor carbon nanotube layer comprises a first surface and a second surface opposite to the first surface, and the first surface is in direct contact with the MgO layer;a functional dielectric layer on the second surface;a source electrode and a drain electrode electrically connected to the semiconductor carbon nanotube layer, wherein the source electrode and the drain electrode are spaced from each other; anda gate electrode on the functional dielectric layer, wherein the gate electrode is insulated from the semiconductor carbon nanotube layer.2. The N-type thin film transistor of claim 1 , wherein the semiconductor carbon nanotube layer is sandwiched between the MgO layer and the functional dielectric layer.3. The N-type thin film transistor of claim 2 , wherein the MgO layer entirely covers the first surface claim 2 , and the functional dielectric layer entirely cover the second surface.4. The N-type thin film transistor of claim 3 , wherein the semiconductor carbon nanotube layer is sealed by the MgO layer and the functional dielectric layer.5. The N-type thin film transistor of claim 1 , wherein a thickness of the MgO layer ranges from about 1 nanometer to about 10 nanometers.6. The N-type thin film transistor of claim 1 , wherein the ...

N-TYPE THIN FILM TRANSISTOR

An N-type thin film transistor includes an insulating substrate, a semiconductor carbon nanotube layer, an MgO layer, a functional dielectric layer, a source electrode, a drain electrode, and a gate electrode. The semiconductor carbon nanotube layer is located on the insulating substrate. The source electrode and the drain electrode electrically connect the semiconductor carbon nanotube layer, wherein the source electrode and the drain electrode are spaced from each other, and a channel is defined in the semiconductor carbon nanotube layer between the source electrode and the drain electrode. The MgO layer is located on the semiconductor carbon nanotube layer. The functional dielectric layer covers the MgO layer. The gate electrode is located on the functional dielectric layer. 1. An N-type thin film transistor , comprising:an insulating substrate;a semiconductor carbon nanotube layer located on the insulating substrate;a source electrode and a drain electrode electrically connected to the semiconductor carbon nanotube layer; wherein the source electrode and the drain electrode are spaced from each other, and a channel is defined in the semiconductor carbon nanotube layer between the source electrode and the drain electrode;an MgO layer on the semiconductor carbon nanotube layer;a functional dielectric layer covering the MgO layer; anda gate electrode on the functional dielectric layer.2. The N-type thin film transistor of claim 1 , wherein the semiconductor carbon nanotube layer comprises a first surface and a second surface opposite to the first surface claim 1 , the first surface is in contact with the insulating substrate claim 1 , and the MgO layer entirely covers the second surface.3. The N-type thin film transistor of claim 1 , wherein a thickness of the MgO layer ranges from about 1 nanometer to about 15 nanometers.4. The N-type thin film transistor of claim 1 , wherein the semiconductor carbon nanotube layer comprises a plurality of carbon nanotubes.5. The ...

N-type thin film transistor

An N-type thin film transistor includes an insulating substrate, a gate electrode, an insulating layer, a semiconductor carbon nanotube layer, an MgO layer, a functional dielectric layer, a source electrode, and a drain electrode. The gate electrode is located on a surface of the insulating substrate. The insulating layer is located on the gate electrode. The semiconductor carbon nanotube layer is located on the insulating layer. The source electrode and the drain electrode electrically connect the semiconductor carbon nanotube layer, wherein the source electrode and the drain electrode are spaced from each other, and a channel is defined in the semiconductor carbon nanotube layer between the source electrode and the drain electrode. The MgO layer is located on the semiconductor carbon nanotube layer. The functional dielectric layer covers the MgO layer.

METHOD OF MANUFACTURING ORGANIC SEMICONDUCTOR DEVICE

A method of manufacturing an organic semiconductor device is provided. The method includes providing a substrate, forming a sacrificial layer on the substrate, forming a patterned organic semiconductor layer on the sacrificial layer, forming an insulating layer on the patterned organic semiconductor layer, forming a gate electrode on the insulating layer, separating the sacrificial layer and the substrate from the patterned organic semiconductor layer, and forming a source/drain electrode on the patterned organic semiconductor layer, so as to provide a simple and effective method of manufacturing the organic semiconductor device. 1. A method of manufacturing an organic semiconductor device , comprising:providing a substrate;forming a sacrificial layer on the substrate;performing a patterned surface treatment to the sacrificial layer and forming a patterned lyophobic area on the sacrificial layer;forming a patterned organic semiconductor layer on the sacrificial layer, wherein a pattern of the patterned lyophobic area of the sacrificial layer and a pattern of the patterned organic semiconductor layer are same or complementary to each other;forming an insulating layer on the patterned organic semiconductor layer, wherein the insulating layer is an organic insulating layer;forming a gate electrode on the insulating layer;separating the sacrificial layer and the substrate from the patterned organic semiconductor layer; andforming a source/drain electrode on the patterned organic semiconductor layer, wherein the source/drain electrode is a patterned nano silver wire or patterned carbon nanotube.2. The method of manufacturing the organic semiconductor device according to claim 1 , further comprising etching the sacrificial layer by using a fluorine-containing gas.3. The method of manufacturing the organic semiconductor device according to claim 1 , further comprising performing the patterned surface treatment to the sacrificial layer by using octadecyltrichlorosilane.4. ...

PHOTOPATTERNABLE COMPOSITIONS, PATTERNED HIGH K THIN FILM DIELECTRICS AND RELATED DEVICES

The present teachings relate to a photopatternable composition including a vinylidene fluoride-based polymer, a photosensitive non-nucleophilic base, and a crosslinking agent. The photopatternable composition can be used to prepare a patterned thin film component for use in an electronic, optical, or optoelectronic device such as an organic thin film transistor. The patterned thin film component can be used as a gate dielectric with a high dielectric constant, for example, a dielectric constant greater than 10. 4. The method of claim 1 , wherein the vinylidene fluoride-based polymer is a copolymer selected from the group consisting of a copolymer of vinylidene fluoride and trifluoroethylene (P(VDF-TrFE)) claim 1 , a copolymer of vinylidene fluoride and chlorotrifluoroethylene (P(VDF-CTFE)) claim 1 , and a copolymer of vinylidene fluoride and hexafluoropropylene (P(VDF-HFP)) claim 1 , or a terpolymer selected from the group consisting of poly(vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene) claim 1 , poly(vinylidene fluoride-trifluoroethylene-chlorofluoroethylene) claim 1 , poly(vinylidene fluoride-trifluoroethylene-hexafluoropropylene) claim 1 , poly(vinylidene fluoride-trifluoroethylene-vinyl fluoride) claim 1 , and poly(vinylidene fluoride-trifluoroethylene-vinylidene chloride).6. The method of claim 5 , wherein x is between about 55 mol % and about 75 mol % claim 5 , and y is between about 15 mol % and about 35 mol %.7. The method of claim 1 , wherein the crosslinking agent comprises two or more crosslinking groups independently selected from the group consisting of maleimide claim 1 , amine claim 1 , thiol claim 1 , phenol claim 1 , cinnamate and coumarin groups; wherein optionally claim 1 , the crosslinking agent is selected from the group consisting of a bisphenol claim 1 , a diamine claim 1 , a bismaleimide claim 1 , a multifunctional thiol claim 1 , and a bis(cinnamate).8. The method of claim 1 , wherein the crosslinking agent does not absorb ...

BIOSENSOR WITH POROUS WICKING LAYER

The present invention relates to organic thin film sensors and the preparation and use thereof in sensing applications, and in particular in glucose sensing. The sensor is characterised by a layered structure comprising a porous wicking layer whose surface is configured to receive a liquid sample. An enzyme is disposed on or within the porous layer for facilitating the generation of a charge carrier from an analyte. A polymer layer in contact with the porous layer is connected to an ohmic conductor for applying a gate voltage to the polymer layer, the polymer layer being conductive to the charge carrier; and an organic semiconducting layer is connected to a source electrode and a drain electrode. 1. An organic thin film transistor based sensor for detecting the presence of an analyte in a liquid sample , the sensor including:a porous wicking layer having a first surface and a second surface, wherein the first surface is configured to receive a liquid sample;an enzyme disposed on or within the porous layer, the enzyme for facilitating the generation of a charge carrier from an analyte;a polymer layer in contact with the second surface of the porous layer, and configured to be connected to an ohmic conductor for applying a gate voltage to the polymer layer, the polymer layer being conductive to the charge carrier; andan organic semiconducting layer configured to be connected to a source electrode and a drain electrode.2. The sensor of claim 1 , wherein the porous layer has a thickness of from 50 nm up to about 500 μm.3. The sensor of claim 1 , wherein the porous layer is formed from a material such that the contact angle of the liquid on the first surface of the porous layer is 60° or less.4. The sensor of claim 1 , wherein the contact angle is 50° or less.5. The sensor or claim 4 , wherein the contact angle is 40° or less.6. The sensor of claim 1 , wherein the pore size is from 50 nm to 2000 nm.7. The sensor of claim 6 , wherein the pore size is from 100 nm to 1000 ...

UV CROSSLINKING OF PVDF-BASED POLYMERS FOR GATE DIELECTRIC INSULATORS OF ORGANIC THIN-FILM TRANSISTORS

A method includes preparing a mixture having an organic solvent, a fluorine-containing polymer, at least one organic base, and a crosslinker component; depositing the mixture over a substrate to form a first layer; and crosslinking the first layer by light treatment to form a crosslinked gate dielectric layer, such that the fluorine-containing polymer is at least one of homopolymers of vinylidene fluoride or copolymers of vinylidene fluoride with fluorine-containing ethylenic monomers. A transistor includes a crosslinked gate dielectric layer disposed over a substrate; an organic semiconductor layer disposed over the substrate and being in direct contact with the crosslinked gate dielectric layer; a source and a drain in contact with the organic semiconductor layer and defining the ends of a channel through the organic semiconductor layer; and a gate superposed with the channel, such that the crosslinked gate dielectric layer separates the gate from the organic semiconductor layer. 1. A method , comprising:preparing a mixture comprising: an organic solvent, a fluorine-containing polymer, at least one organic base, and a crosslinker component;depositing the mixture over a substrate to form a first layer;crosslinking the first layer by light treatment to form a crosslinked gate dielectric layer,wherein the fluorine-containing polymer is at least one of homopolymers of vinylidene fluoride, copolymers of vinylidene fluoride with fluorine-containing ethylenic monomers, or a combination thereof.2. The method of claim 1 , wherein the fluorine-containing polymer is a copolymer of vinylidene fluoride with at least one fluorine-containing ethylenic monomers.3. The method of claim 2 , wherein the at least one fluorine-containing ethylenic monomers are represented by Formula (1) or Formula (2):{'br': None, 'sub': 2', 'f1, 'CF═CF—R\u2003\u2003(Formula 1)'} [{'sub': f1', '3', 'f2, 'Ris selected from: —F; —CF; and —OR; and'}, {'sub': 'f2', 'claim-text': {'br': None, 'sub': 2', 'f3 ...

CNT Thin Film Transistor With High K Polymeric Dielectric

A thin film transistor (TFT) has a gate electrode; a gate insulation layer, a semiconducting channel separated from the gate electrode by the gate insulation layer; a source electrode and a drain electrode. The gate insulation layer is a cross-linked cyanoethylated polyhydroxy polymer, e.g. a cross-linked cyanoethylated pullulan, having a high dielectric constant and the semiconducting channel has a network of semiconducting carbon nanotubes. The semiconducting channel is adhered to the gate insulation layer through a polymeric material. The carbon nanotubes adhere to the polymeric material and the polymeric material reacts or interacts with the gate insulation layer. TFTs have high mobilities while maintaining good on/off ratios. 1. A thin film transistor comprising: a gate electrode; a gate insulation layer comprising a cyanoethylated polyhydroxy polymer cross-linked by a cross-linker and adhered to the gate electrode; a polymeric material that reacts or interacts with the gate insulation layer; a semiconducting channel comprising a network of semiconducting carbon nanotubes adhered to the polymeric material and separated from the gate electrode by the gate insulation layer; a source electrode; and , a drain electrode.2. The thin film transistor according to claim 1 , wherein the cyanoethylated polyhydroxy polymer comprises a cyanoethylated pullulan.3. The thin film transistor according to claim 2 , wherein the cyanoethylated pullulan comprises cyanoethyl pullulan or cyanoethyl dihydroxypropyl pullulan (CEDHPP).4. The thin film transistor according to claim 1 , wherein the cross-linker comprises ethylenediaminetetraacetic dianhydride (EDT) claim 1 , benzophenone-3 claim 1 ,3′ claim 1 ,4 claim 1 ,4′-tetracarboxylic dianhydride (BPT) claim 1 , diethylenetriaminepentaaceticdianhydride (DAPD) claim 1 , biphenyl-4 claim 1 ,4′-dicarboxylic acid (BCA) claim 1 , suberoyl chloride or any mixture thereof.5. The thin film transistor according to claim 1 , wherein the ...

METHOD FOR MANUFACTURING FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING WIRELESS COMMUNICATION DEVICE

Provided is a method for manufacturing a field-effect transistor, the method including the steps of: forming a gate electrode on the surface of a substrate; forming a gate insulating layer on the gate electrode; forming a conductive film containing a conductor and a photosensitive organic component by a coating method on the gate insulating layer; exposing the conductive film from the rear surface side of the substrate with the gate electrode as a mask; developing the exposed conductive film to form a source electrode and a drain electrode; and forming a semiconductor layer by a coating method between the source electrode and the drain electrode. This method makes it possible to provide an FET, a semiconductor device, and an RFID which can be prepared by a simple process, and which have a high mobility, and have a gate electrode and source/drain electrodes aligned with a high degree of accuracy. 1. A method for manufacturing a field-effect transistor , the method comprising the steps of: forming a gate electrode on a surface of a substrate; forming a gate insulating layer on the gate electrode; forming a conductive film containing a conductor and a photosensitive organic component by a coating method on the gate insulating layer; exposing the conductive film from a rear surface side of the substrate with the gate electrode as a mask; developing the exposed conductive film to form a source electrode and a drain electrode; and forming a semiconductor layer by a coating method between the source electrode and the drain electrode.2. A method for manufacturing afield-effect transistor , the method comprising the steps of: forming a source electrode and a drain electrode on a surface of a substrate; forming a semiconductor layer by a coating method between the source electrode and the drain electrode; forming a gate insulating layer on the source electrode , the drain electrode , and the semiconductor layer; forming a conductive film containing a conductor and a ...

STRUCTURE FOR TRANSISTOR SWITCHING SPEED IMPROVEMENT UTILIZING POLAR ELASTOMERS

An organic thin film transistor comprising a first gate, a second gate, a semiconducting layer located between the first gate and second gate and configured to operate as a channel and a source electrode and a drain electrode connected to opposing sides of the semiconductor layer. The organic thin film transistor also comprises a first dielectric layer located between the first gate and the semiconducting layer in a direction of current flow through the semiconductor layer, the first dielectric layer comprising a polar elastomeric dielectric material that exhibits a double layer charging effect when a set voltage is applied to the first gate and a second dielectric layer located between the second gate and the semiconducting layer. 1. An organic thin film transistor comprising:a first gate;a second gate;a semiconducting layer located between the first gate and second gate and configured to operate as a channel;a source electrode and a drain electrode connected to opposing sides of the semiconductor layer;a first dielectric layer located between the first gate and the semiconducting layer in a direction of current flow through the semiconductor layer, the first dielectric layer comprising a polar elastomeric dielectric material that exhibits a double layer charging effect when a set voltage is applied to the first gate; anda second dielectric layer located between the second gate and the semiconducting layer.2. The organic thin film transistor of claim 1 , wherein the set voltage is configured to induce free carriers in the semiconductor layer claim 1 , and wherein the free carriers increase a switching speed of the organic thin film transistor.3. The organic thin film transistor of claim 1 , wherein the organic thin film transistor has a coplanar configuration or a staggered configuration.4. The organic thin film transistor of claim 1 , wherein the organic thin film transistor has a top gate or a bottom gate configuration.5. The organic thin film transistor of claim ...

TRANSISTOR DEVICE WITH VERTICAL CARBON NANOTUBE (CNT) ARRAYS OR NON-VERTICAL TAPERED CNT ARRAYS

A transistor device includes an array of fin structures arranged on a substrate, each of the fin structures being vertically alternating stacks of a first isoelectric point material having a first isoelectric point and a second isoelectric point material having a second isoelectric point that is different than the first isoelectric point; one or more carbon nanotubes (CNTs) suspended between the fin structures and contacting a side surface of the second isoelectric point material in the fin structures; a gate wrapped around the array of CNTs; and source and drain contacts arranged over the fin structures; wherein each of the fin structures have a trapezoid shape or parallel sides that are oriented about 90° with respect to the substrate. 1. A method of making a transistor device , the method comprising:forming an array of fin structures, the array of fin structures being arranged on a substrate and each having a pair of layers, the pair of layers comprising a first isoelectric point material having a first isoelectric point and a second isoelectric point material having a second isoelectric point that is different than the first isoelectric point;wrapping a gate around carbon nanotubes (CNTs) between the fin structures to suspend the CNTs in the gate, the CNTs contacting a side surface of the second isoelectric point material in the fin structures; andforming source and drain contacts over the fin structures;wherein the CNTs are arranged in a substantially vertical array or a non-vertical tapered array within the gate.2. The method of claim 1 , wherein a gate dielectric material surrounds the CNTs and is hafnium oxide.3. The method of claim 1 , wherein a gate dielectric material surrounds the CNTs and is aluminum oxide.4. The method of claim 1 , wherein the CNTs are anchored in the source and drain contacts.5. The method of claim 1 , wherein the gate comprises a metal gate material separated from the source and drain contacts by a gate spacer.6. The method of claim ...

PROCESS OF SURFACE MODIFICATION OF DIELECTRIC STRUCTURES IN ORGANIC ELECTRONIC DEVICES

The invention relates to a process of modifying the surface energy of dielectric structures, like for example dielectric layers or bank structures, in organic electronic (OE) devices, more specifically in organic field effect transistors (OFETs). 1. A process of surface treatment of a dielectric structure in an organic electronic (OE) device , comprising the step of exposing the surface of the dielectric structure , or specific parts of said surface , to a solvent blend comprisinga first solvent selected from the group consisting of aliphatic or aromatic alcohols, anda second solvent selected from the group consisting of aliphatic esters and aliphatic ketones.2. The process according to claim 1 , wherein the first solvent is selected from the group consisting of methanol claim 1 , cyclohexanol claim 1 , isopropanol claim 1 , benzyl alcohol.3. The process according to claim 1 , wherein the second solvent is selected from the group consisting of methyl acetate claim 1 , ethyl acetate claim 1 , methyl n-amyl ketone.4. The process according to claim 1 , wherein the dielectric structure comprises a crosslinked organic polymer.5. The process according to claim 1 , wherein the dielectric structure comprises a crosslinked and fluorinated organic polymer comprising one or more crosslinkable groups.6. The process according to claim 1 , wherein the dielectric structure comprises a polycycloolefinic polymer.7. The process according to claim 6 , wherein the polycycloolefinic polymer is a norbornene-type polymer.8. The process according to claim 6 , wherein the polycycloolefinic polymer comprises two or more distinct types of repeating units.9. The process according to claim 6 , wherein the polycycloolefinic polymer comprises a first type of repeating unit having a pendant fluorinated group.10. The process according to claim 9 , wherein the polycycloolefinic polymer comprises a first type of repeating unit having a pendant alkyl claim 9 , aryl or aralkyl group that is fluorinated ...

FLEXIBLE VERTICAL CHANNEL ORGANIC THIN FILM TRANSISTOR AND MANUFACTURE METHOD THEREOF

Provided is a flexible vertical channel organic thin film transistor and a manufacture method thereof, which change the traditional configuration of the horizontal channel organic TFT and use the vertical channel configuration to tremendously shorten the channel length so that the TFT can obtain the larger source-drain current under the lower drive voltage; by using the flawless, high conductive and high transparent graphene material to manufacture the gate, the electronic performance of the TFT can be better; by using the hexagonal boron nitride material to manufacture the gate insulation layer to interact with the gate made by graphene, the electronic performance of the TFT can be promoted; because both the graphene and the hexagonal boron nitride materials are two dimension atomic layer structure material with better bendability and the channel layer uses the flexible organic semiconductor layer, the bendability of the entire TFT can be significantly promoted. 1. A manufacture method of a flexible vertical channel organic thin film transistor , comprising steps of:step 1, providing a rigid substrate, and forming a flexible substrate on the rigid substrate, and forming a gate on the flexible substrate;step 2, forming a gate insulation layer on the gate, and a dimension of the gate insulation layer is smaller than a dimension of the gate;forming a source on the gate insulation layer, and a dimension of the source is smaller than or equal to the dimension of the gate insulation layer;step 3, forming an organic semiconductor layer on the source, and a dimension of the organic semiconductor layer is smaller than the dimension of the source;forming a drain on the organic semiconductor layer, and a dimension of the drain is smaller than or equal to the dimension of the organic semiconductor layer;forming a source contact electrode which is separately located with the organic semiconductor layer on the source;forming a gate contact electrode which is separately located ...

FLEXIBLE ARRAY SUBSTRATE STRUCTURE AND MANUFACTURING METHOD FOR THE SAME

A flexible array substrate structure and manufacturing method thereof are disclosed, in which the patterning process of an organic semi-conductive layer is achieved by using the inside wall of the opening of a color film layer as a bank, so that one mask can be saved. Also, a process for manufacturing a device can be simplified by an improved device structure, so that the flexible array substrate structure of the invention can be obtained by only using four masks. 1. A flexible array substrate structure , comprising:a substrate comprising a source electrode area, a drain electrode area, a common electrode area, and a channel area between the source electrode area and the drain electrode area;a source electrode layer disposed on the source electrode area of the substrate;a drain electrode layer disposed on the drain electrode area of the substrate;a common electrode layer disposed on the common electrode area of the substrate;a color film layer covered on the source electrode layer, the drain electrode layer, and the common electrode layer, and the color film layer having a via hole and an opening exposing the channel area of the substrate; anda first transparent conductive layer disposed on the color film layer, and the first transparent conductive layer being electrically connected to the drain electrode layer by way of the via hole,wherein there are an organic semi-conductive layer, an organic insulative layer, a second transparent conductive layer, and a gate electrode layer in the opening, the organic semi-conductive layer is disposed on the channel area of the substrate, and contacts the source electrode layer and the drain electrode layer, the organic insulative layer is disposed on the organic semi-conductive layer, the second transparent conductive layer is disposed on the organic insulative layer, the gate electrode layer is disposed on the second transparent conductive layer, and surfaces of the color film layer and the organic semi-conductive layer have ...