Schalterloser Leitungs-DI/MIC-Vorverstärker-Eingang

Eine schalterlose Vorverstärker-Eingangsschaltung enthält einen Audio-Eingangsanschluss, welcher eine erste Audiovorrichtung, welche bei einer ersten Impedanz betriebsfähig ist, und eine zweite Audiovorrichtung, welche bei einer zweiten Impedanz betriebsfähig ist, welche niedriger ist als die erste Impedanz, empfängt. Eine Vorverstärkerschaltung gibt ein vorverstärktes Audiosignal in Reaktion auf eine Verstärkung von einem ersten Audiosignal, welches durch die erste Audiovorrichtung erzeugt ist, oder einem zweiten Audiosignal, welche durch die zweite Audiovorrichtung erzeugt ist, aus. Die schalterlose Vorverstärker-Eingangsschaltung enthält ferner eine Impedanz-Auswahlschaltung, welche eine Impedanz am Ausgang derart einstellt, dass die zweite Impedanz in Reaktion auf eine Verbindung der zweiten Audiovorrichtung mit dem Audio-Eingangsanschluss erreicht wird, und die Impedanz am Ausgang derart einstellt, dass die erste Impedanz in Reaktion auf eine Verbindung der ersten Audiovorrichtung ...

Dualbandsender mit schaltbaren Anpassungsschaltung

Leitungstreiber oder Verstärker mit frequenzabhängig variabler Schein-Impedanz

Leitungstreiber oder Verstärker mit künstlich erzeugter Schein-Ausgangsimpedanz, wobei die Erzeugung der Ausgangsimpedanz dadurch bewirkt wird, dass mindestens eine Rückführung des Treiberausgangssignals nach mindestens einem Widerstand, welcher mindestens einer Ausgangsverstärkerstufe nachgeschaltet ist, auf mindestens einen Eingang mindestens eines Summen- oder Differenz- oder Operationsverstärkers erfolgt, welcher direkt über diese Ausgangsverstärkerstufe verfügt oder mindestens eine solche indirekt über weitere Schaltungselemente ansteuert, wodurch sich eine von der tatsächlichen Ausgangsimpedanz der Ausgangsverstärkerstufe und des Widerstands unterschiedliche künstliche Schein-Ausgangsimpedanz des Leitungstreibers oder Verstärkers aus Sicht der Last oder Leitung ergibt, dadurch gekennzeichnet, dass in mindestens ein Rückführungssignal oder in die mit diesem gebildete Mitkopplungschleife mindestens ein Multiplizierer dessen Bauvarianten multiplizierender Digital-/Analog-Wandler, Variable ...

Broadband power amplifier systems and methods

High current low-cost dc coupled dac follower low pass filter headphone amplifier

A device, method and computer program product for amplification of an input signal

A device 1100 for amplification of an input signal includes amplification circuitry 1004 comprising a plurality of switchable transistors (Fig.4, 4000a-c), a variable voltage input, e.g. power supply 1010, connected to the amplification circuitry, and controller circuitry 1002. The variable voltage input may comprise a DC power supply 1010a and a buck-boost converter 1010b. The controller circuitry is configured to set a target output power level of the device and, in accordance with a load impedance of an output of the amplification circuitry, amplify the input signal to the target output power level for that load impedance by controlling a level of the variable voltage input and/or controlling a state of connection between the plurality of switchable transistors to change an effective physical dimension of the amplification circuitry, e.g. gate or channel width. A plurality of input terminals 1012a-d and output terminals 1020a-d may be included, each selectively connectable to the amplification ...

Multi-input amplifier with programmable embedded attenuators

Balanced RF amplifier using a common mode choke

AMPLIFIER DEVICE

ENVELOPE ADJUSTING REINFORCEMENT ARRANGEMENT

Tuned damping circuit for power amplifier output

Dual band power amplifier circuit for microwave ablation

A dual band power amplifier includes a power amplifier (420), a first matching circuit (450), a first auxiliary circuit (470), a second matching circuit (440), and a second auxiliary circuit (460). The power amplifier (420) has inputs and outputs, and is configured to amplify input signals at a first and second frequency. The first matching circuit (450) is electrically connected to the output of the power amplifier (420) and configured to match a load impedance to an output impedance at the first frequency. The first matching circuit (450) and the first auxiliary circuit (470) are configured to match the load impedance to the output impedance at the second frequency. The second matching circuit (440) is electrically connected to the input of the power amplifier (420) and configured to match a source impedance to an input impedance at the first frequency. The second matching circuit (440) and the second auxiliary circuit (460) are configured to match the source impedance to the input impedance ...

Field effect transistor (FET) structure with integrated gate connected diodes

A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: a source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.

AMPLIFIER CIRCUIT WITH CROSS WIRING OF DIRECT-CURRENT SIGNALS AND MICROWAVE SIGNALS

Disclosed is an amplifier circuit with cross wiring of direct-current signals and microwave signals. The circuit comprises a circuit network unit comprising a direct-current feeding circuit and a microwave power signal circuit. The direct-current feeding circuit starts from a high electron mobility transistor (HEMT) drain power-up bonding point (211), and is connected to a feeding end of a tail-level HEMT pipe core (250) via a corresponding line after being connected to a first MIM capacitor (221) in parallel, connected to a first micro-strip inductor (222) and a symmetrical micro-strip (223) in series, and connected to one of electrodes of second MIM capacitors (231, 234) in series. The microwave power signal circuit starts from a signal end of the tail-level HEMT pipe core (250), is combined into two paths by a corresponding line, the two paths being respectively connected to two third MIM capacitors (241, 242) in parallel, being respectively connected to the other electrode of the second ...

Broadband power combining arrangement

Die Erfindung betrifft einen Leistungskombinierer (20A) sowie einen Generator, der einen Leistungskombinierer (20A) aufweist. Der Leistungskombinierer (20A) weist eine Vielzahl von Eingängen (38a bis 38n) auf, wobei jeder Eingang (38a bis 38n) zum Empfangen eines jeweiligen Leistungssignals mit einem jeweiligen Leistungsverstärker (16a bis 16n) verbindbar ist. Eine Vielzahl von Impedanzanpassungsschaltungszweigen (30a bis 30n) ist mit einem jeweiligen einen der Vielzahl von Eingängen (38a bis 38n) verbunden. Jeder Impedanzanpassungsschaltungszweig (30a bis 30n) weist mindesten einen Hochpassfilterabschnitt (34a bis 34n) und mindestens einen Tiefpassfilterabschnitt (36a bis 36n) auf, durch die das jeweilige Leistungssignal verläuft. Die Impedanzanpassungsschaltungszweige (30a bis 30n) sind verbunden, um die Leistungssignale aus jedem Leistungsverstärker (16a bis 16n) zu kombinieren. Ein Ausgang (40) ist zum Ausgeben des kombinierten Leistungssignals vorgesehen. Ferner betrifft die Erfindung ...

Balanced Doherty power amplifier circuit and wireless transmitter

Switch-less bidirectional amplifier

A bi-directional amplifier, transceiver, integrated circuit, mobile unit, telecommunication infrastructure for amplification of signals received or signals to be transmitted in a communication circuit and a method for bi-directional amplification comprising amplifying signals in a bi-directional amplifier and directing a signal between two or more different paths comprising at least one first biased semiconductor amplification element (230, 340, 450, 550) connected to a at least one first impedance matching network (210, 310, 410, 510), at least one second biased semiconductor amplification element (240, 350, 460, 560) connected to a second impedance matching network (220, 330, 430, 530), a first device for biasing the at least one first biased semiconductor amplification element and a second device for biasing the at least one second biased semiconductor amplification element where the direction of signal amplification in said bi-directional amplifier is controlled by the first or second ...

A high power integrated RF amplifier

An integrated HF-amplifier structure comprises in a first direction (FD) in the order mentioned: an input bond pad (IBP), a plurality of cells (CE1, CE2) being displaced with respect to each other in the first direction (FD), and an output bond pad (OBP). Each one of the cells (CE1, CE2) comprises an amplifier having an input pad (GP1, GP2), an active area (A1, A2), and an output pad (DP1, DP2). The active area (A1, A2) is arranged in- between the input pad (GP1, GP2) and the output pad (DP1, DP2), and the input pad (GP1, GP2), the active area (A1, A2), and the output pad (DP1, DP2) are displaced with respect to each other in a second direction (SD) substantially perpendicular to the first direction (FD). A first network (Nl) comprises first interconnecting means (Li, Ci; Li1, Li2, Ci1) to interconnect input pads (GP1, GP2) of adjacent ones of the plurality of cells (CE1, CE2), and extends in the first direction (FD). A second network (N2) comprises second interconnecting means (Lo, Co; ...

Power combining circuit of radio-frequency power amplifier

RF power amplifier and RF power module using the same

The RF power amplifier circuit including multiple amplification stages has a previous-stage amplifier, a next-stage amplifier and a controller. The previous-stage amplifier responds to an RF transmission input signal. The next-stage amplifier responds to an amplification signal output by the previous-stage amplifier. In response to an output-power-control voltage, the controller controls the former- and next-stage amplifiers in quiescent current and gain. In response to the output-power-control voltage, the quiescent current and gain of the previous-stage amplifier are continuously changed according to a first continuous function, whereas those of the next-stage amplifier are continuously changed according to a second continuous function. The second continuous function is higher than the first continuous function by at least one in degree. The RF power amplifier circuit brings about the effect that the drop of the power added efficiency in low and middle power modes is relieved.

ENHANCING ISOLATION AND IMPEDANCE MATCHING IN HYBRID-BASED CANCELLATION NETWORKS AND DUPLEXERS

Doherty amplifier

RF power amplifier and RF power module using the same

AMPLIFIER MATCHING CIRCUIT LOW NOISE AND LOW NOISE AMPLIFIER COMPRISING SUCH A CIRCUIT

PROCEEDED Of ADAPTATION Of IMPEDANCE Of ANTENNA MULTIBANDES AND CHAIN Of EMISSION OR RECEPTION ADAPTATION HAS AUTOMATIC.

구리 배선 인터페이스 회로

... 구리 배선 인터페이스 회로가 제공되며, 전류 출력 증폭기(10)가 포트 임피던스 컴포넌트(11)와 송신단에 연결되고, 전류 출력 증폭기(10)가 송신될 신호를 증폭하도록 구성되어 있으며; 포트 임피던스 컴포넌트(11)는 하이패스 필터(12)에 연결되고, 하이패스 필터(12)에 의해 수행되는 임피던스 변환을 거친 후, 포트 임피던스 컴포넌트(11)의 임피던스는 케이블과 부하의 등가 임피던스와의 임피던스 정합을 수행하기 위해 이용되며; 하이패스 필터(12)는 포트 임피던스 컴포넌트(11)와 케이블에 연결되고, 하이패스 필터(12)는 송신될 신호 또는 수신된 신호를 필터링하고 포트 임피던스 컴포넌트(11)에 대해 임피던스 변환을 수행하도록 구성되어 있고; 에코 제거 모듈(13)은 포트 임피던스 컴포넌트(11)와 수신단에 연결된다.

POWER AMPLIFIER

Wideband harmonic matching network

REDUCTION OF POWER CONSUMPTION IN INTEGRAL ULTRA-WIDEBAND POWER AMPLIFIERS

Operational amplifying device with auto-adjustment output impedance

The invention provides an operational amplifying device with auto-adjustment output impedance, including a operational amplifier, a first signal path, a second signal path, and a third signal path. The output of the operational amplifier is connected to the inverted input of the operational amplifier, and non-inverted input of the operational amplifier receives an input signal. The first signal path is high resistance, and the second and the third signal paths are low resistance. Each end of the first, second, and third signal paths is connected to the output of the operational amplifier, and each the other end of the first, second, and third signal paths is connected to a first output node. The first signal path is normally on and the second and the third signal paths are normally off. When the input signal is in a steady state, the second and the third signal paths are turned off. When the input signal is in a transition state, the second or the third signal paths is turned on to reduce ...

Amplifier with base current reuse

An RF amplifier module that has a plurality of amplifiers wherein at least one of the amplifiers is powered via an envelope tracking module. The biasing input of at least one of the amplifiers is provided to the first amplifier to power the first amplifier to reduce power consumption. The first amplifier may also be powered via fixed biasing to provide greater stability of the module.

Amplifier

RADIO FREQUENCY SIGNAL AMPLIFICATION DEVICE AND FRONT-END MODULE

HIGH EFFICIENCY LINEAR POWER AMPLIFIERS WITH LOAD COMPENSATION

The present invention addresses the problem to extend the dynamic power range where the amplifier operates linearly for a full input amplitude swing with improved efficiency. According to the present invention, the above presented problem is solved by changing the delivered power to the load by changing the value of the load and still keeping the amplifier in its linear condition. The invention enables the amplifier to maintain high efficiency over a wider power range.

LOAD-LINE ADAPTATION

According to the general concept disclosed herein a circuit for adaptive matching of a load impedance to a predetermined load-line impedance of a load-line connected to a power amplifier output comprises a fixed matching network between the power transistor and an adaptive matching network, whereby the fixed matching network acts as an impedance inverter which results in a relatively low insertion loss at high power. Results indicate that the impedance-inverting network can be used over more than a factor of 10 in impedance variation. Further, the usage of the fixed matching network, close to the power transistor, allows for the implementation of transmission zeros and/or for a well defined load impedance at a predetermined harmonic frequency, independent of the (variable) load impedance at the fundamental frequency.

VSWR COMPENSATION CIRCUITS FOR RF TRANSMIT CHAIN

The present invention provides a method and apparatus for compensating the output of a transmitter stage (50) of a communications system. A communications apparatus has a transmitter stage (50) providing a variable control voltage which varies the power of the transmitter stage. The impedance at the output of the transmitter stage.(50) varies as the power varies. A control generation circuit compares a reference voltage to the variable control voltage to produce a control signal (VvswrC). A compensated load (40) coupled to the output of the transmitter stage (50) has active component (s) whose' impedance varies in response to the control signal (VvsweC) so as to compensate for the impedance at the output of the transmitter stage (50).

METHOD AND ARRANGEMENT IN A MOBILE COMMUNICATIONS SYSTEM

The invention is based on the fact that the current output from a DDB controlled amplifier in backoff, i.e. for low amplitudes, is reduced more or less linearly with the amplitude of the signal to be amplified. Therefore, it is enough to use smaller amplifiers which are able to output the necessary RF current. Hence, according to the present invention, the total DDB amplifier is divided into smaller parts that are coupled to the output only when needed.

RECONFIGURABLE TUNABLE RF POWER AMPLIFIER

A multi-band, multi-standard programmable power amplifier having tunable impedance matching input and output networks and programmable device characteristics. The impedance of either or both of the impedance matching input and output networks is tunable responsive to one or more control signals. In one example, the programmable power amplifier incorporates a feedback control loop and the control signal(s) are varied responsive to the feedback loop.

METHOD AND APPARATUS PROVIDING INTEGRATED LOAD MATCHING USING ADAPTIVE POWER AMPLIFIER COMPENSATION

An RF power amplifier module can be used without a matching device between the power amplifier module and an antenna. The power amplifier module is constructed and operated to detect, protect and maintain the performance of the power amplifier in the presence of severe VSWR load mismatches, without requiring the use of external circuitry. The RF power amplifier module includes integral detection circuitry for generating a first detection signal having a value that is indicative of the current flowing through an output power transistor and a second detection signal having a value that is indicative the voltage appearing at the output of the output power transistor, as well as integral compensation circuitry for controlling the generation of a plurality of bias current and bias voltage signals to have values that are a function of the values of the first and second detection signals, as well as the current output power level of the RF power amplifier module. Also included is an integral impedance ...

RF POWER AMPLIFIERS WITH LINEARIZATION

Designs and techniques associated with power amplifiers for amplifying RF signals to provide variable power amplification and improved linearity in various RF amplification circuits, including power amplifiers operated under the power back-off conditions.

HIGH-GAIN LOW NOISE FIGURE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR AMPLIFIER WITH LOW CURRENT CONSUMPTION

A radio frequency low noise amplifier circuit with a receive signal input, a receive signal output, and a voltage source include a low noise amplifier and a coupled inductor circuit with a primary inductive chain connected to the output of the low noise amplifier and to the voltage source. The coupled inductor circuit further includes a secondary inductive chain with a first inductor electromagnetically coupled to the primary inductive chain, and a second inductor in series with the first inductor and magnetically coupled to the primary inductive chain. The second inductor is connected to a feedback node of the low noise amplifier. There is an output matching network connected to the first inductor of the secondary inductive chain and to the receive signal output.

Reducing power amplifier gain drift during a data burst

A bias circuit provides additional bias current for power amplifiers during data bursts to compensate for the gain droop caused by a rise in the power amplifier temperature during the data burst. A bias circuit includes a difference amplifier and switches coupled to the difference amplifier. The switches operate the bias circuit in a first mode when a transmit data burst is detected and operate the bias circuit in a second mode after the bias circuit has operated in the first mode for a predetermined period of time. In the first mode, the bias circuit charges a storage capacitor and sets an output current to zero. In the second mode, the bias circuit outputs the output current that increases above the initial value of zero as the PA warms up, where the excursion of this increase of current is determined by a register. The switches disable the bias circuit when the transmit data burst ends.

Combined output matching network and filter for power amplifier with concurrent functionality

Disclosed are systems and methods related to reducing intermodulation products in an RF output signal by matching an impedance of the power amplifier to an impedance of the antenna and concurrently blocking signals having a second fundamental frequency received by the antenna when the antenna is transmitting to inhibit intermodulation products of the first and second fundamental frequencies from re-radiating from the antenna. The matching and blocking are performed concurrently by a single circuit with combined matching and blocking functionality.

Power amplifying apparatus and mobile communication terminal

A power amplifying apparatus includes an input terminal configured to receive an input signal, a first power amplifier biased for class A or class AB operation which is configured to amplify the input signal, an output terminal connected to an output of the first power amplifier, a second power amplifier biased for class C operation which is configured to receive and amplify a part of the input signal, and a switch connected between an output of the second power amplifier and the output terminal.

Load-Line Adaptation

According to the general concept disclosed herein, a circuit for adaptive matching of a load impedance to a predetermined load-line impedance of a load-line connected to a power amplifier output includes a fixed matching network between the power transistor and an adaptive matching network, whereby the fixed matching network acts as an impedance inverter which results in a relatively low insertion loss at high power. Results indicate that the impedance-inverting network can be used over more than a factor of 10 in impedance variation. Further, the usage of the fixed matching network, close to the power transistor, allows for the implementation of transmission zeros and/or for a well defined load impedance at a predetermined harmonic frequency, independent of the (variable) load impedance at the fundamental frequency.

High-frequency amplifier

It is an object of this invention to provide a high-frequency amplifier which can efficiently amplify an input signal in a plurality of different frequency bands in a simple configuration. The high-frequency amplifier is configured such that an RF signal having n frequencies (f 1 >f 2 , , , >fn) applied to the amplifier is converted by an impedance conversion circuit to a higher impedance than the output impedance of the amplifier, and is branched into the highest frequency f 1 and lower frequencies lower than that by a high-pass filter and a low-pass filter. Frequency f 1 passes high-pass filter 31 , and is thereby converted to 50 ohms. The frequencies lower than frequency f 1 filtered by the low-pass filter are converted to a high impedance by an impedance conversion circuit, and are branched into the second highest frequency f 2 and lower frequencies by high-pass filter 32 and low-pass filter 42 . In the same manner, impedance conversion circuits are added, while the signals are branched ...

Amplifier Dynamic Bias Adjustment for Envelope Tracking

An envelope tracking amplifier having stacked transistors is presented. The envelope tracking amplifier uses dynamic bias voltages at one or more gates of the stacked transistors in addition to a dynamic bias voltage at a drain of a transistor.

Power detector

A power detector circuit for measuring output power of an amplifier circuit includes a mirror amplification stage having mirror circuit components substantially similar and corresponding to original circuit components of an amplification stage of the amplifier circuit, and a power sensor circuit coupled to an output node of the mirror amplification stage.

SEMICONDUCTOR DEVICE

A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor.

VARIABLE OUTPUT RESISTANCE IN A PLAYBACK PATH WITH OPEN-LOOP PULSE-WIDTH MODULATION DRIVER

A system may include a digital modulator configured to modulate an input signal received at an input of the digital modulator to generate a modulated input signal at an output of the digital modulator, a digital gain element having a digital gain and coupled to the digital modulator, an open-loop Class-D amplifier coupled to an output of the digital modulator and configured to amplify the modulated input signal, wherein the open-loop Class-D amplifier is powered from a variable power supply having a variable supply voltage which is variable in response to one or more characteristics of the input signal, and a control circuit configured to control the digital gain to approximately cancel changes in an analog gain of the open-loop Class-D amplifier due to variation in the variable supply voltage in response to the one or more characteristics of the input signal.

Flip-chip amplifier with termination circuit

Disclosed are devices and methods for improving power added efficiency and linearity of radio-frequency power amplifiers implemented in flip-chip configurations. In some embodiments, a harmonic termination circuit can be provided so as to be separate from an output matching network configured to provide impedance matching at a fundamental frequency. The harmonic termination circuit can be configured to terminate at a phase corresponding to a harmonic frequency of the power amplifier output. Such a configuration of separate fundamental matching network and harmonic termination circuit allows each to be tuned separately to thereby improve performance parameters such as power added efficiency and linearity.

Tunable power amplifier using laminate MEMS capacitors

For use in a wireless network, a tunable power amplifier circuit includes a power amplifier transistor and a plurality of laminate MEMS (microelectromechanical system) capacitors coupled to the power amplifier transistor. The laminate MEMS capacitors are arranged in a tunable matching network and configured to provide a matching impedance for the power amplifier transistor. In some embodiments, the laminate MEMS capacitors are arranged in a binary array.

Power amplification module

A power amplification module includes a first transistor which amplifies and outputs a radio frequency signal input to its base; a current source which outputs a control current; a second transistor connected to an output of the current source, a first current from the control current input to its collector, a control voltage generation circuit connected to the output and which generates a control voltage according to a second current from the control current; a first FET, the drain being supplied with a supply voltage, the source being connected to the base of the first transistor, and the gate being supplied with the control voltage; and a second FET, the drain being supplied with the supply voltage, the source being connected to the base of the second transistor, and the gate being supplied with the control voltage.

Independent PA biasing of a driver stage and a final stage

A radio frequency (RF) communications system, which includes power amplifier (PA) control circuitry and PA bias circuitry, is disclosed. The PA control circuitry identifies a selected communications mode of the RF communications system and a target output power from RF PA circuitry. The PA control circuitry selects a PA bias level of a driver stage of the RF PA circuitry and a PA bias level of a final stage of the RF PA circuitry based on the selected communications mode and the target output power. The PA bias circuitry establishes a PA bias level for the driver stage and a PA bias level for the final stage based on the selected PA bias levels of the driver stage and the final stage, respectively.

Transistor with shield structure, packaged device, and method of manufacture

A transistor includes a semiconductor substrate having an intrinsic active device, a first terminal, and a second terminal. The transistor also includes an interconnect structure formed of layers of dielectric material and electrically conductive material on the semiconductor substrate. The interconnect structure includes a pillar, a tap interconnect, and a shield structure positioned between the pillar and the tap interconnect formed from the electrically conductive material and extending through the dielectric material. The pillar contacts the first terminal and connects to a first runner. The tap interconnect contacts the second terminal and connects to a second runner. The shield structure includes a base segment, a first leg, and a second leg extending from opposing ends of the base segment, wherein the first and second legs extend from opposing ends of the base segment in a direction that is antiparallel to a length of the base segment.

INCREASED OUTPUT IMPEDANCE SWITCHING AMPLIFIER AND LOW-SIDE RECYCLE MODE

An audio amplifier has a first H bridge and a second H bridge, to drive a speaker as a load. The second H bridge drives the speaker through resistors for increased output impedance. Control logic operates the first H bridge as a class D amplifier for larger amplitudes of audio signal, and operates the second H bridge as a class D amplifier for smaller amplitudes of audio signal. Other aspects are also described and claimed.

Solder bump placement for thermal management in flip chip amplifiers

Metal pillars are placed adjacent to NPN transistor arrays that are used in the power amplifier for RF power generation. By placing the metal pillars in intimate contact with the silicon substrate, the heat generated by the NPN transistor arrays flows down into the silicon substrate and out the metal pillar. The metal pillar also forms an electrical ground connection in close proximity to the NPN transistors to function as a grounding point for emitter ballast resistors, which form an optimum electrothermal configuration for a linear SiGe power amplifier.

Power amplifier circuitry and method

A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals.

Control systems and methods for power amplifiers operating in envelope tracking mode

Control systems and methods for power amplifiers operating in envelope tracking mode are presented. A set of corresponding functions and modules are described and various possible system configurations using such functions and modules are presented.

SEMICONDUCTOR INTEGRATED CIRCUIT, COMMUNICATION MODULE, AND SMART METER

A semiconductor integrated circuit includes a low-noise amplifier circuit, a transformer, and an BSD protection circuit. The low-noise amplifier circuit amplifies a radio signal that is supplied to an input terminal. The transformer includes a first winding and a second winding and functions as an input impedance matching circuit for the low-noise amplifier circuit, in which at least one end of the second winding is connected to the input terminal of the low-noise amplifier circuit. The ESP protection circuit is connected to a center tap of the first winding.

POWER AMPLIFIER MODULE

A power amplifier module includes an amplifier that amplifies an input signal and outputs the amplified signal, a harmonic termination circuit that is disposed subsequent to the amplifier and that attenuates a harmonic component of the amplified signal, the harmonic termination circuit including at least one field effect transistor (FET), and a control circuit that controls a gate voltage of the at least one FET to adjust a capacitance value of a parasitic capacitance of the at least one FET. The control circuit adjusts the capacitance value of the parasitic capacitance of the at least one FET, and thereby a resonance frequency of the harmonic termination circuit is adjusted.

Overlay class F choke

Embodiments of the present disclosure relate to an overlay class F choke of a radio frequency (RF) power amplifier (PA) stage and an RF PA amplifying transistor of the RF PA stage. The overlay class F choke includes a pair of mutually coupled class F inductive elements, which are coupled in series between a PA envelope power supply and a collector of the RF PA amplifying transistor. In one embodiment of the RF PA stage, the RF PA stage receives and amplifies an RF stage input signal to provide an RF stage output signal using the RF PA amplifying transistor. The collector of the RF PA amplifying transistor provides the RF stage output signal. The PA envelope power supply provides an envelope power supply signal to the overlay class F choke. The envelope power supply signal provides power for amplification.

Signal transceiver

A signal transceiver includes a first power amplifier coupled to a chip output port of a chip; an impedance transforming circuit; a switching circuit arranged to selectively couple the chip output port to a first port of the impedance transforming circuit; and a receiving amplifier coupled to a second port of the impedance transforming circuit.

CURRENT CONTROL USING POWER CELL ISOLATION

A radio-frequency device comprises a first radio-frequency signal node, a second radio-frequency signal node, a first power cell path coupled between the first radio-frequency signal node and a ground reference node, the first power cell path including a first transistor having an input terminal coupled to the second radio-frequency signal node, and a second power cell path coupled in parallel with the first power cell path between the first radio-frequency signal node and the ground reference node, the second power cell path including a second transistor having an input terminal coupled to the second radio-frequency signal node and an output terminal that is electrically isolated from an output terminal of the first transistor.

Broadband power amplifier having high efficiency

A wideband power amplifier module includes a plurality of switch mode amplifiers and a plurality of impedance amplifier modules. Each switch mode amplifier includes an input to receive an input signal, and an RF output to output an RF power signal. The switch mode amplifier includes at least one semiconductor switch formed from gallium nitride (GaN). Each impedance amplifier module includes an output electrically connected to the RF output of a respective switch mode amplifier. The impedance amplifier module is configured to inject at least one impedance control signal to each RF output.

Power amplifier

According to an embodiment, a power amplifier includes: an MMIC substrate; a high frequency probe pad disposed on the MMIC substrate; and a metal plate disposed on the MMIC substrate so as to adjoin to the high frequency probe pad, and connected to an MMIC external circuit via a bonding wire.

Apparatus and method for controlling impedance tuning by using hybrid control algorithm

An impedance tuning control apparatus has a processing circuit and an output circuit. The processing circuit determines a first control setting according to a first performance metric, and performs a search operation with a search start point set by the first control setting to find a second control setting according to a second performance metric. The second performance metric is different from the first performance metric. The output circuit outputs a final control setting to a tuner, wherein the final control setting is derived from the second control setting.

RADIO FREQUENCY POWER DELIVERY SYSTEM

A system and method are provided for delivering power to a dynamic load. The system includes a power supply providing DC power having a substantially constant power open loop response, a power amplifier for converting the DC power to RF power, a sensor for measuring voltage, current and phase angle between voltage and current vectors associated with the RF power, an electrically controllable impedance matching system to modify the impedance of the power amplifier to at least a substantially matched impedance of a dynamic load, and a controller for controlling the electrically controllable impedance matching system. The system further includes a sensor calibration measuring module for determining power delivered by the power amplifier, an electronic matching system calibration module for determining power delivered to a dynamic load, and a power dissipation module for calculating power dissipated in the electrically controllable impedance matching system.

Multifunctional radio frequency systems and methods for UV sterilization, air purification, and defrost operations

Example systems have a defrost system that can receive a first RF signal at a first frequency to defrost a load. An air treatment device can receive a second RF signal at a second frequency and perform an air treatment process. An RF signal source has a power output, and a switching arrangement selectively electrically connects the defrost system and the first air treatment device to the power output of the RF signal source. A controller can electrically connect one of the defrost system and the first air treatment device to the power output of the RF signal source. When the defrost system is electrically connected, the RF signal source outputs the first RF signal at the first frequency, and when the first air treatment device is electrically connected, the RF signal source outputs the second RF signal at the second frequency.

RADIO-FREQUENCY MODULE AND COMMUNICATION DEVICE

A radio-frequency module includes a first power amplifier, a second power amplifier, a switch, a plurality of first filters, and a second filter. The first power amplifier amplifies a transmission signal of a first frequency band and outputs the amplified transmission signal. The second power amplifier amplifies a transmission signal of a second frequency band and outputs the amplified transmission signal. The pass bands of the plurality of first filters are contained within the first frequency band. The pass band of the second filter is contained within the second frequency band. The second power amplifier has a greater output power level than the first power amplifier. The first output terminal of the first power amplifier is switchably connectable to the plurality of first filters via the switch. The second output terminal of the second power amplifier is connected to the second filter without the switch interposed therebetween.

POWER AMPLIFIER WITH CO-EXISTENCE FILTER

DOHERTY POWER AMPLIFICATION APPARATUS AND METHOD

A high efficiency UHF linear power amplifier

An RF amplifier for a phase and envelope varying signal employs a class C operated device (110) for high efficiency. In order to improve the linearity of the class C operated device (110), a signal (s2(t)) corresponding to the envelope of the amplifier output is formed and a portion thereof is fedback to an envelope modulation element such as a pulse width modulator (140) connected to the class C operated device (110) to reduce distortion at the amplifier output.

MULTIBAND RADIO DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To obtain a multiband and multimode radio device using a frequency band of 800 MHz to 10 GHz without increasing the circuit scale nor the cost. SOLUTION: When the radio device is switched from a 800 MHz-band mobile phone system to a 9 GHz-band UWB communication system, a reactance element determined to match a load Z of a high-pass filter is connected to a transmission power amplifier output terminal in response to a signal for switching between the high-pass filter and a low-pass filter. COPYRIGHT: (C)2008,JPO&INPIT ...

MATCHING CIRCUIT

PROBLEM TO BE SOLVED: To provide a matching circuit which performs impedance matching in a plurality of frequency bands and can be designed in a small size. SOLUTION: A first matching part 110, a second matching part 120, and a third matching part 130 are connected in series between a circuit element 199 of which the impedance has a frequency characteristic and a circuit 198 having a fixed impedance. The second matching part 120 has an impedance conversion function. The first matching part 110 is operated as an element having a reactance value corresponding to each frequency band by exclusive on/off switching of switches 118 and 119, and the third matching part 130 is operated as an element having a reactance value corresponding to each frequency band by on/off switching of a switch 133, whereby matching is performed in each frequency band. Since design of a seventh reactance means 131 is determined by correlation with design of a fifth reactance means 115 and an eighth reactance means ...

СХЕМА ИЗМЕНЕНИЯ ЗНАЧЕНИЙ ПАССИВНЫХ КОМПОНЕНТОВ В ЭЛЕКТРОННЫХ ЦЕПЯХ (ВАРИАНТЫ)

Изобретение относится к пассивным электронным компонентам с переменными характеристиками. В настоящей системе предусмотрено изменение значения пассивных компонентов в электронных цепях. Технический результат: повышение контроля над точностью параметров или точно установленных значений характеристик компонентов или рабочих характеристик и изменение их значений в результате старения компонента, истории работы и изменений условий окружающей среды. Пассивные компоненты могут быть выбраны в диапазоне от стандартных резисторов, конденсаторов и индуктивностей до сложных структур, таких как линии передачи и объемные резонаторы. Выбор значения и его изменений может осуществляться либо динамически при работе схемы, или как одновременная часть процесса изготовления, определяемая требованиями конкретного применения. Схему цифроаналогового преобразователя (ЦАП) используют для цифрового ввода данных выбора значения и для управляемого выбора значения с разрешением этого значения в зависимости от разрешающей ...

УСИЛИТЕЛЬ МОЩНОСТИ ДЛЯ УСИЛЕНИЯ РАДИОЧАСТОТНОГО СИГНАЛА

УСИЛИТЕЛЬ МОЩНОСТИ С МОДИФИЦИРОВАННОЙ ТОПОЛОГИЕЙ ДОГЕРТИ

... 1. Усилитель мощности с модифицированной топологией (1) Догерти, приспособленный, чтобы возбуждать нагрузку (4), содержащий основную схему (2), в свою очередь, содержащую основной усилитель (20), и по меньшей мере одну вспомогательную схему (3), в свою очередь, содержащую вспомогательный усилитель (30), отличающийся тем, что он содержит схему (5) со спаренными линиями (57, 58) передачи, которая приспособлена, чтобы соединять упомянутую основную схему (2) с упомянутой вспомогательной схемой (3).2. Усилитель мощности с модифицированной топологией Догерти по п. 1, отличающийся тем, что упомянутая схема (5) со спаренными линиями (57, 58) передачи предусматривает импедансный инвертор.3. Усилитель мощности с модифицированной топологией Догерти по п. 2, отличающийся тем, что упомянутая схема (5) со спаренными линиями передачи соединяется с инверсным импедансом (6), чтобы предоставлять упомянутый импедансный инвертор.4. Усилитель мощности с модифицированной топологией Догерти по п. 1, отличающийся ...

Breitband-Doherty-Verstärkerschaltung mit Konstantimpedanzkombinierer

Es wird eine Dreiwege-Breitband-Doherty-Verstärkerschaltung bereitgestellt, welche einen ersten Spitzenverstärker (120), welcher betreibbar ist, bei einem ersten Leistungspegel einzuschalten, einem zweiten Spitzenverstärker (110), welcher betreibbar ist, bei einem zweiten Leistungspegel unterhalb des ersten Leistungspegels einzuschalten, und einen Hauptverstärker (100), welcher betreibbar ist, bei allen Leistungspegeln eingeschaltet zu sein, umfasst. Der Hauptverstärker (100) weist einen lastmodulierten Zustand hoher Impedanz auf, wenn der erste und der zweite Spitzenverstärker ausgeschaltet sind. Die Dreiwege-Breitband-Doherty-Verstärkerschaltung umfasst weiterhin einen Konstantimpedanzkombinierer (130), welcher mit einem jeweiligen Ausgang jedes Verstärkers (120, 110, 100) verbunden ist. Der Konstantimpedanzkombinierer (130) weist eine charakteristische Impedanz auf, welche der Impedanz des Hauptverstärkers (100) in dem lastmodulierten Zustand hoher Impedanz angepasst ist, wobei eine ...

Power supply pre-distortion

Power amplification circuit and method for supplying power at a plurality of desired power output levels

Radio frequency integrated circuit

Pre-amplifier circuit including microphone pre-amplifier stage

Broadband power combining arrangement

Apparatus and methods for biasing of power amplifiers

Radio frequency integrated circuit

MICROWAVE POWER AMPLIFIERS

A radio frequency power amplifier

Multi-input amplifier with programmable embedded attenuators

DIFFERENCE OUTPUT STAGE FOR ELECTRONIC CIRCUIT THE REMOTE SUPPLY OF A TERMINAL PERMITS

PROCEDURE FOR THE BROADBAND ADJUSTMENT AND AN APPROPRIATE NET ELEMENT

POWER AMPLIFICATION FOR FRAGMENTED TRANSCEIVERSYSTEME

High efficiency switch-mode power amplifier

DUAL BAND POWER AMPLIFIER CIRCUIT FOR MICROWAVE ABLATION

A dual band power amplifier includes a power amplifier (420), a first matching circuit (450), a first auxiliary circuit (470), a second matching circuit (440), and a second auxiliary circuit (460). The power amplifier (420) has inputs and outputs, and is configured to amplify input signals at a first and second frequency. The first matching circuit (450) is electrically connected to the output of the power amplifier (420) and configured to match a load impedance to an output impedance at the first frequency. The first matching circuit (450) and the first auxiliary circuit (470) are configured to match the load impedance to the output impedance at the second frequency. The second matching circuit (440) is electrically connected to the input of the power amplifier (420) and configured to match a source impedance to an input impedance at the first frequency. The second matching circuit (440) and the second auxiliary circuit (460) are configured to match the source impedance to the input impedance ...

SEMICONDUCTOR AMPLIFIER BIAS CIRCUIT AND SEMICONDUCTOR AMPLIFIER DEVICE

A semiconductor amplifier bias circuit includes a first transmission line, a first grounded capacitor, a second transmission line and a power supply terminal. The first transmission line is connected to an output end part of the output matching circuit and the external load. The second transmission line includes one end part connected to the first transmission line and the other end part connected to the first grounded shunt capacitor. An electrical length of the second transmission line is approximately 900 at a center frequency of a band. The one end part is connected to the first transmission line at a position apart from the output end part by an electrical length of approximately 45° at the center frequency. The power supply terminal is connected to a connection point of the first grounded shunt capacitor and the other end part of the second transmission line.

MICROWAVE POWER AMPLIFIERS

P/8693/MSW MICROWAVE POWER AMPLIFIERS A microwave power amplifier having application in multiple beam phased antenna array systems and including biasing means connection to the base of a microwave transistor and responsive to radio frequency signals applied to the amplifier to automatically adjust the transistor bias level to maintain constant amplifier gain. The biasing means includes two voltage regulators with their outputs capacitively coupled via a fixed resistor of value determined by the characteristics of the transistor, the base of the transistor being connected to the biasing means at the junction of the resistor and the capacitive coupling of one of the regulators. The mode of operation of the power amplifier gives rise to a highly efficient linear system while under effective Class B (non-linear) bias.

Amplifying circuit, controller and transceiver circuit

Adjustable radio front-end and method

Power amplifier spontaneous thermal compensation circuit

Calibrate output matching for correct output power

A calibration unit calibrates a power amplifier load impedance to achieve a nominal amplifier load impedance after the connection of one or more external elements, e.g., antenna, to improve the accuracy and effectiveness of output power calibration. The calibration unit comprises an adaptive impedance unit and a controller. The adaptive impedance unit includes first and second variable impedance elements connected between the amplifier and the external load, e.g., antenna. The controller independently calibrates the imaginary and real parts of the load impedance by respectively selecting first and second calibration values for the first and second variable impedance elements based on a reference voltage. More particularly, the controller selects calibration values for the first and second variable impedance elements from a plurality of impedance values based on a comparison between a reference voltage and the calibrated voltages produced at the output of the power amplifier responsive to the impedance values.

Distributed power amplifier with active matching

A distributed power amplifier arranged to operate over a bandwidth. An input side with an input terminal is arranged to receive an input signal and connected to an input transmission line. An output side with an output terminal is adapted to deliver an output signal and connected to an output transmission line. A power splitter is connected to the input terminal, thus being arranged to divide the input signal in a first path to the input transmission line and in a second path to an input of an active matching circuit. The active matching circuit has an output connected to the output transmission line. The other end of the output transmission line is connected to the output terminal. A method to design a distributed power amplifier and to modify existing distributed power amplifiers.

Power amplification systems and methods

A power amplifier system includes a power amplifier element that provides a power output signal in response to a bias signal, and a voltage converter. The voltage converter provides at least one discrete voltage output level to the power amplifier element, where the discrete voltage output level is used to develop the bias signal.

Amplifier providing power recovery from a narrow-band antenna

A method, amplifier and system are provided for enabling power recovery from a narrow-band antenna when a signal having bandwidth exceeding that of the antenna is utilized. The amplifier provides amplification of a source signal to the antenna and recovery of power stored in the antenna during periods when the impedance of the antenna is negative to enable reverse current through the amplifier to a direct current (DC) power source.

Output stage formed inside and on top of an soi-type substrate

A method for controlling an output amplification stage comprising first and second complementary SOI-type power MOS transistors, in series between first and second power supply rails, the method including the steps of: connecting the bulk of the first transistor to the first rail when the first transistor is maintained in an off state; connecting the bulk of the second transistor to the second rail when the second transistor is maintained in an off state; and connecting the bulk of each of the transistors to the common node of said transistors, during periods when this transistor switches from an off state to an on state.

Power Amplification Based on Phase Angle Controlled Frequency Reference Signal and Amplitude Control Signal

Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of constant envelope constituent signals. The constituent signals are amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal. Embodiments also perform frequency up-conversion.

Impedance matching arrangement for amplifier having split shunt capacitor and amplifier including the same

An amplifier having an operating frequency includes: an input port and an output port; three gain elements, each having an input terminal and an output terminal; an input matching network; and an output matching network. The input matching network includes: a first microstrip line which is connected to the input port and is an inductor at the operating frequency; a second microstrip line extending between the input terminals of the three gain elements; and a first split shunt capacitor connecting the first microstrip line to the second microstrip line. The output matching network includes: a third microstrip line which is connected to the output port and is an inductor at the operating frequency; a fourth microstrip line extending between the output terminals of the three gain elements; and a second split shunt capacitor connecting the third microstrip line to the fourth microstrip line.

Dc-dc converter semiconductor die structure

A direct current (DC)-DC converter having a DC-DC converter semiconductor die and an alpha flying capacitive element is disclosed. The DC-DC converter semiconductor die includes a first series alpha switching element, a second series alpha switching element, a first alpha flying capacitor connection node, which is about over the second series alpha switching element, and a second alpha flying capacitor connection node, which is about over the first series alpha switching element. The alpha flying capacitive element is electrically coupled between the first alpha flying capacitor connection node and the second alpha flying capacitor connection node. By locating the first alpha flying capacitor connection node and the second alpha flying capacitor connection node about over the second series alpha switching element and the first series alpha switching element, respectively, lengths of transient current paths may be minimized, thereby reducing noise and potential interference.

System and method for adjusting gain frequency response of rf power amplifier

A radio frequency (RF) amplifier is disclosed including an active device adapted to amplify an input signal in accordance with a gain frequency response to generate an output signal, and a dissipative circuit adapted to modify the gain frequency response by dissipating the input or output signal more so at a first frequency range than at a second frequency range. The dissipative circuit may include a resistive element, and an open circuit adapted to operate as an open at a specified frequency to substantially minimize the dissipation of the input or output signal through the resistive element at the specified frequency. The open circuit may include an open-ended transmission line having an electrical length of a half wavelength or multiple thereof at the specified frequency. Alternatively, the open circuit may include a short-ended transmission line having an electrical length of a quarter wavelength or odd multiple thereof at the specified frequency.

High frequency power amplifier

A high frequency power amplifier includes: a first transistor for amplifying an input high-frequency signal; a second transistor for amplifying an output signal of the first transistor; a third transistor connected in parallel with the first transistor and for amplifying the input high-frequency signal; a first switching element connected between an output of the first transistor and an input of the second transistor; a second switching element connected between an output of the third transistor and the first switching element; third and fourth switching elements connected in series between the output of the first transistor and an output of the second transistor, and between the second switching element and the output of the second transistor; and a first capacitor connected between the third switching element and the fourth switching element.

Closed loop bias control

This disclosure relates to radio frequency (RF) amplification devices and methods for amplifying an RF input signal. To set the quiescent operating level of the RF output signal, a bias signal to be applied to the RF input signal is received prior to amplifying the RF input signal. The bias signal is amplified to generate the RF output signal at the quiescent operating level and a feedback signal is received that is indicative of the quiescent operating level of the RF output signal. Prior to amplifying the RF input signal, the bias signal level of the bias signal is adjusted such that the quiescent operating level is set to a reference signal level based on the feedback signal level. This allows for adjustments to be made to the quiescent operating level and maintain the quiescent operating level at a desired value.

Current-Mode Active Termination

Embodiments of the present invention, as further described below, provide active termination circuits that can be used with power transmitter circuits. Embodiments reduce power loss due to impedance matching and increase power efficiency in power transmitter circuits. In particular, embodiments provide active termination circuits that can be configured to draw minimal amounts of the output current generated by the power transmitter circuits. At the same time, embodiments achieve optimal impedance matching, thus enabling optimal power transfer to the load. Further, embodiments can be controlled adaptively in real time to reduce parasitic effects on power transfer and to optimize impedance matching. Embodiments can be implemented using various transistor technologies (e.g., MOSFET, BJT, etc.), and can be used with a variety of power transmitter circuits, including, for example, power DACs, analog/digital RF transmitters, and analog/digital PAs.

Variable Impedance Device

A variable impedance device includes a passive tuner that includes at least one variable component, which is controllable to apply a variable impedance value to an input signal of the passive tuner. A low noise amplifier is configured to supply the input signal to the passive tuner by amplifying an input RF (radio frequency) signal.

Multiple power mode amplifier

A multiple power mode amplifier includes: N amplifiers connected in series via switches; and a control circuit for controlling the N amplifiers in accordance with the output modes. P amplifiers out of the N amplifiers constitute a driver amplifier, and constitute a negative feedback amplifier including a feedback circuit for negatively feeding back its own output signal to its own input side. N−P amplifiers constitute a final stage amplifier connected in series to the negative feedback amplifier in a disconnectable manner. The control circuit is configured to: in a first output mode, disconnect the final stage amplifier from the negative feedback amplifier, and disable the feedback circuit; and in a second output mode, connect the final stage amplifier in series to the negative feedback amplifier, and enable the feedback circuit.

Amplifying apparatus

An amplifying apparatus includes a first amplifier that amplifies a first signal of a constant amplitude; a second amplifier that amplifies a second signal identical in amplitude and differing in phase with respect to the first signal; a first transmission line of which, a first end is connected to an output terminal of the first amplifier; a second transmission line differing in length with respect to the first transmission line and of which, a first end is connected to an output terminal of the second amplifier and a second end is connected to a second end of the first transmission line; and an amplitude balance adjusting element connected to the first or the second transmission line. The amplifying apparatus outputs from a connection node of the first and the second transmission lines, a signal that is a combination of output signals of the first amplifier and of the second amplifier.

High frequency power amplifier

Provided is a compact high frequency power amplifier having a high degree of freedom of design with respect to a gain fluctuation immediately after start-up of an amplifier. The high frequency power amplifier includes a speed-up circuit that transiently increases a reference voltage during rise of a control voltage to increase an amount of bias supplied to an amplification transistor from a bias circuit. The speed-up circuit includes a capacitor and an overshoot control circuit. The overshoot control circuit determines an increasing amount of the reference voltage when the reference voltage is transiently increased according to a charge amount charged in the capacitor, and the overshoot control circuit also determines a time constant in charging and discharging the capacitor.

Rf power amplifier

A reduction is achieved in the primary-side input impedance of a transformer (voltage transformer) as an output matching circuit without involving a reduction in Q-factor. An RF power amplifier includes transistors, and a transformer as the output matching circuit. The transformer has a primary coil and a secondary coil which are magnetically coupled to each other. To the input terminals of the transistors, respective input signals are supplied. The primary coil is coupled to each of the output terminals of the transistors. From the secondary coil, an output signal is generated. The primary coil includes a first coil and a second coil which are coupled in parallel between the respective output terminals of the transistors, and each magnetically coupled to the secondary coil. By the parallel coupling of the first and second coils of the primary coil, the input impedance of the primary coil is reduced.

Circuits for providing class-e power amplifiers

In some embodiments, circuits for providing Class-E power amplifiers are provided, the circuits comprising: a first switch having a first side and a second side; a first Class-E load network coupled to the first side of the first switch; a second Class-E load network: and a second switch having a first side and a second side, the first side of the second switch being coupled the second side of the first switch and the second Class-E load network. In some embodiments, the circuits further comprise: a third switch having a first side and a second side; a third Class-E load network coupled to the first side of the third switch; a fourth Class-E load network; and a fourth switch having a first side and a second side, the first side of the fourth switch being coupled the second side of the third switch and the fourth Class-E load network.

Matching network for transmission circuitry

The present disclosure relates to transmission circuitry of a wireless communication device. The transmission circuitry includes power amplifier circuitry, an output matching network, and impedance control circuitry. The power amplifier circuitry amplifies a radio frequency (RF) input signal to provide an amplified RF output signal, which is passed through the output matching network and transmitted via one or more antennas. As the center frequency of the RF input signal and conditions of operating parameters change, the impedance control circuitry adjusts the values of one or more variable impedance elements of the output matching network in a desired fashion. The values of the variable impedance elements are adjusted such that the output matching network concurrently and dynamically presents the desired load impedances at the center frequency and at one or more harmonics of the RF input signal to achieve a given performance specification.

Efficient Linear Integrated Power Amplifier Incorporating Low And High Power Operating Modes

A novel and useful radio frequency (RF) front end module (FEM) circuit that provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 WLAN, 3G and 4G cellular standards, Bluetooth, ZigBee, etc. The configuration of the FEM circuit permits the use of common, relatively low cost semiconductor fabrication techniques such as standard CMOS processes. The FEM circuit includes a power amplifier made up of one or more sub-amplifiers having high and low power circuits and whose outputs are combined to yield the total desired power gain. An integrated multi-tap transformer having primary and secondary windings arranged in a novel configuration provide efficient power combining and transfer to the antenna of the power generated by the individual sub-amplifiers.

Doherty amplifier

A Doherty amplifier comprises a first amplifier, one or more second amplifiers and a third amplifier to receive inputs of high-frequency signals in parallel, wherein the first amplifier serving as a carrier amplifier amplifies the high-frequency signal, each of the second amplifiers serving as the carrier amplifiers or peaking amplifiers amplifies the high-frequency signal, and the third amplifier serving as the peaking amplifier amplifies the high-frequency signal.

SEMICONDUCTOR PACKAGES HAVING WIRE BOND WALL TO REDUCE COUPLING

A device (e.g., a Doherty amplifier) housed in an air cavity package includes one or more isolation structures over a surface of a substrate and defining an active circuit area. The device also includes first and second adjacent circuits within the active circuit area, first and second leads coupled to the isolation structure(s) between opposite sides of the package and electrically coupled to the first circuit, third and fourth leads coupled to the isolation structure(s) between the opposite sides of the package and electrically coupled to the second circuit, a first terminal over the first side of the package between the first lead and the third lead, a second terminal over the second side of the package between the second lead and the fourth lead, and an electronic component coupled to the package and electrically coupled to the first terminal, the second terminal, or both the first and second terminals. 1. A device housed in an air cavity package , the device comprising:a substrate having a top surface;one or more isolation structures over the top surface of the substrate, wherein an area over the top surface of the substrate within sidewalls of the one or more isolation structures defines an active circuit area;a first circuit over the top surface of the substrate within the active circuit area;a second circuit over the top surface of the substrate within the active circuit area and adjacent to the first circuit;a first lead coupled to a portion of the one or more isolation structures that is proximate to a first side of the package, wherein the first lead is electrically coupled to the first circuit;a second lead coupled to a portion of the one or more isolation structures that is proximate to a second side of the package, wherein the second lead is electrically coupled to the first circuit;a third lead coupled to the portion of the one or more isolation structures that is proximate to the first side of the package, wherein the third lead is electrically ...

RADIO-FREQUENCY MODULE AND COMMUNICATION APPARATUS

A radio-frequency module is capable of being connected to an external substrate and includes a mounting substrate having a main face and a main face, which are opposed to each other, multiple ground terminals with which the mounting substrate is electrically connected to the external substrate, a PA mounted on the main face, and an LNA mounted on the main face. A communication apparatus includes the radio-frequency module. 1. A radio-frequency module comprising:a mounting substrate having a first main face and a second main face, which are opposed to each other;a transmission power amplifier mounted on the first main face; anda low noise reception amplifier mounted on the second main face.2. The radio-frequency module of claim 1 , wherein the radio-frequency module is configured to be electrically connected to an external substrate.3. The radio-frequency module of claim 1 , further comprising:an antenna connection terminal;a transmission power amplifier; andan antenna switch that is connected to the antenna connection terminal and is configured to controllably switch between connection and non-connection states between the antenna connection terminal and the transmission power amplifier,wherein the antenna switch is arranged on the second main face.4. The radio-frequency module of claim 3 , further comprising:an impedance matching circuit arranged on the first main face, and connected to an output terminal of the transmission power amplifier.5. The radio-frequency module of claim 4 , further comprising:a reception switch connected to an input terminal of the low noise reception amplifier, and arranged on the second main face.6. The radio-frequency module according to claim 1 ,wherein, in a plan view of the radio-frequency module in a direction vertical to the first main face and the second main face, a footprint of the transmission power amplifier does not overlap a footprint of the low noise reception amplifier.7. The radio-frequency module according to claim 1 , ...

RADIO-FREQUENCY MODULE AND COMMUNICATION APPARATUS

A radio-frequency module including a mounting substrate that has mounting faces opposed to each other; a PA that is mounted on the mounting face, that is a radio-frequency component, and that has an emitter terminal; a through electrode that is connected to the emitter terminal of the PA and that passes through the mounting faces of the mounting substrate; and a ground terminal connected to the through electrode. 1. A radio-frequency module comprising:a mounting substrate having a first face and a second face, which is opposed to the first face;a transmission power amplifier mounted on the first face, the transmission power amplifier including an emitter terminal;an electrode connected to the emitter terminal of the transmission power amplifier, wherein the electrode passes through the mounting substrate between the first face and the main face; anda ground terminal connected to the electrode.2. The radio-frequency module of claim 1 , whereinthe radio-frequency module is connected to an external substrate, andthe ground terminal is connected to the external substrate.3. The radio-frequency module of claim 1 , further comprising:first resin formed on the first main face that covers at least part of the transmission power amplifier.4. The radio-frequency module of claim 3 , further comprising:a circuit component mounted on the second face; andsecond resin formed on the second face that covers at least part of the circuit component.5. The radio-frequency module of claim 4 , whereinthe ground terminal is arranged on the second resin.6. The radio-frequency module of claim 5 , further comprising:a ground electrode layer formed of a planar wiring pattern in the mounting substrate; anda first shield electrode layer formed to cover a top face and side faces of the first resin and connected to the ground electrode layer at side faces of the mounting substrate.7. The radio-frequency module of claim 5 , further comprising:a second shield electrode layer formed on side faces of ...

INDUCTOR AND POWER AMPLIFIER MODULE

An inductor includes first and second wirings respectively formed in a substantially spiral shape on first and second surfaces of a multilayer substrate. The multilayer substrate includes plural dielectric layers stacked on each other in a predetermined direction. The multilayer substrate includes a first layer having the first surface, which is an end surface in the predetermined direction, and a second layer having the second surface within the multilayer substrate. The width of the second wiring is smaller than that of the first wiring. The first and second wirings are electrically connected in parallel with each other. The inductance of the first wiring and that of the second wiring are substantially equal to each other. When the first and second wirings are projected on the first surface in the predetermined direction, entirety of a projected image of the second wiring is contained within that of the first wiring. 1. An inductor comprising:a first wiring that is formed in a substantially spiral shape on a surface of a first dielectric layer of a multilayer substrate; anda second wiring that is formed in a substantially spiral shape on a surface of a second dielectric layer of the multilayer substrate, wherein:the multilayer substrate comprises the first dielectric and the second dielectric layer, the first dielectric layer and the second dielectric layer being stacked on each other in a predetermined direction, the surface of the first dielectric layer being an end surface in the predetermined direction, and the surface of the second dielectric layer being within the multilayer substrate,a width of the second wiring is less than a width of the first wiring,the first wiring and the second wiring are electrically connected in parallel with each other, andwhen the first wiring and the second wiring are projected in the predetermined direction, a projected image of the first wiring completely overlaps a projected image of the second wiring.2. The inductor according ...

BIAS CIRCUIT

Provided is a bias circuit that supplies a first bias current or voltage to an amplifier that amplifies a radio frequency signal. The bias circuit includes: an FET that has a power supply voltage supplied to a drain thereof and that outputs the first bias current or voltage from a source thereof; a first bipolar transistor that has a collector thereof connected to a gate of the FET, that has a base thereof connected to the source of the FET, that has a common emitter and that has a constant current supplied to the collector thereof; and a first capacitor that has one end thereof connected to the collector of the first bipolar transistor and that suppresses variations in a collector voltage of the first bipolar transistor. 1. A bias circuit that supplies a first bias current or voltage to an amplifier that amplifies a radio frequency signal , the bias circuit comprising:a field-effect transistor (FET), wherein a power supply voltage is supplied to a drain of the FET and a source of the FET outputs the first bias current or voltage;a first bipolar transistor, wherein a collector of the first bipolar transistor is connected to a gate of the FET, a base of the first bipolar transistor is connected to the source of the FET, the first bipolar transistor has a common emitter, and a constant current is supplied to the collector of the first bipolar transistor; anda first capacitor, wherein a first end of the first capacitor is connected to the collector of the first bipolar transistor and the first capacitor suppresses variations in a collector voltage of the first bipolar transistor.2. The bias circuit according to claim 1 ,wherein a second end of the first capacitor is connected to the base of the first bipolar transistor.3. The bias circuit according to claim 1 ,wherein a second end of the first capacitor is grounded.4. The bias circuit according to claim 1 ,wherein a second end of the first capacitor is connected to the source of the FET.5. The bias circuit according to ...

DOHERTY AMPLIFIER CIRCUITS

A Doherty amplifier circuit comprising: a splitter having: a splitter-input-terminal for receiving an input signal; a main-splitter-output-terminal; and a peaking-splitter-output-terminal; a main-power-amplifier having a main-power-input-terminal and a main-power-output-terminal, wherein; the main-power-input-terminal is connected to the main-splitter-output-terminal; and the main-power-output-terminal is configured to provide a main-power-amplifier-output-signal; a peaking-power-amplifier having a peaking-power-input-terminal and a peaking-power-output-terminal, wherein: the peaking-power-input-terminal is connected to the peaking-splitter-output-terminal; and the peaking-power-output-terminal is configured to provide a peaking-power-amplifier-output-signal. The splitter, the main-power-amplifier and the peaking-power-amplifier are provided by means of an integrated circuit. 1. A Doherty amplifier circuit comprising: a splitter-input-terminal for receiving an input signal;', 'a main-splitter-output-terminal; and', 'a peaking-splitter-output-terminal;, 'a splitter having the main-power-input-terminal is connected to the main-splitter-output-terminal; and', 'the main-power-output-terminal is configured to provide a main-power-amplifier-output-signal;, 'a main-power-amplifier having a main-power-input-terminal and a main-power-output-terminal, wherein the peaking-power-input-terminal is connected to the peaking-splitter-output-terminal; and', 'the peaking-power-output-terminal is configured to provide a peaking-power-amplifier-output-signal;, 'a peaking-power-amplifier having a peaking-power-input-terminal and a peaking-power-output-terminal, whereinan integrated circuit;wherein the splitter, the main-power-amplifier and the peaking-power-amplifier are provided by means of the integrated circuit.2. The Doherty amplifier circuit of claim 1 , wherein:the splitter-input-terminal is connected to the main-splitter-output-terminal, andthe splitter comprises a splitter- ...

IMPEDANCE MATCHING CIRCUIT FOR RADIO-FREQUENCY AMPLIFIER

Impedance matching circuit for radio-frequency amplifier. In some embodiments, an impedance matching circuit can include a primary metal trace having a first end configured to be capable of being coupled to a voltage source for the power amplifier, and a second end configured to be capable of being coupled to an output of the power amplifier. The impedance matching circuit can further include a secondary metal trace having first end coupled to the second end of the primary metal trace, and a second end configured to be capable of being coupled to an output node. The impedance matching circuit can further include a capacitance implemented between the first and second ends of the secondary metal trace, and be configured to trap a harmonic associated with an amplified signal at the output of the power amplifier. 1. An impedance matching circuit for a power amplifier , comprising:a primary metal trace having a first end configured to be capable of being coupled to a voltage source for the power amplifier, and a second end configured to be capable of being coupled to an output of the power amplifier;a secondary metal trace having a first end coupled to the second end of the primary metal trace, and a second end configured to be capable of being coupled to an output node; anda capacitance implemented between the first and second ends of the secondary metal trace, the capacitance configured to trap a harmonic associated with an amplified signal at the output of the power amplifier.2. The impedance matching circuit of further comprising a harmonic trap circuit implemented between the output of the power amplifier and a ground.3. The impedance matching circuit of wherein the harmonic trap circuit includes a series combination of a capacitance and an inductance.4. The impedance matching circuit of wherein the capacitance and the inductance of the harmonic trap are configured to trap a second harmonic associated with the amplified signal.5. The impedance matching circuit of ...

POWER AMPLIFICATION CIRCUIT

Provided is a power amplification circuit that includes: an amplifier that amplifies an input signal and outputs an amplified signal; a first bias circuit that supplies a first bias current or voltage to the amplifier; a second bias circuit that supplies a second bias current or voltage to the amplifier; a first control circuit that controls the first bias current or voltage; and a second control circuit that controls the second bias current or voltage. The current supplying capacity of the first bias circuit is different from the current supplying capacity of the second bias circuit. 1. A power amplification circuit comprising:an amplifier that amplifies an input signal and outputs an amplified signal;a first bias circuit that supplies a first bias current or voltage to the amplifier;a second bias circuit that supplies a second bias current or voltage to the amplifier;a first control circuit that controls a level of the first bias current or voltage; anda second control circuit that controls a level of the second bias current or voltage;wherein a current supplying capacity of the first bias circuit is different from a current supplying capacity of the second bias circuit,wherein the first control circuit outputs a first current that controls the first bias current or voltage,wherein the second control circuit outputs a second current that controls the second bias current or voltage,wherein the first bias circuit comprises a field effect transistor that outputs the first bias current or voltage in accordance with the first current,wherein the second bias circuit comprises a second bipolar transistor that outputs the second bias current or voltage in accordance with the second current,wherein the first bias circuit further comprises a third transistor, andwherein a collector of the third transistor is connected to a gate of the field effect transistor, a base of the third transistor is connected to a source of the field effect transistor, the emitter of the third ...

AMPLIFIER

A conventional Doherty amplifier requires a load modulation line having an electrical length of 90 degrees, a frequency compensation line having an electrical length of an integral (n) multiple of 180 degrees, and an input phase adjustment line having an electrical length corresponding to a difference (180°×n−90°) between the electrical length of the load modulation line and the electrical length of the frequency compensation line. Thus, the conventional Doherty amplifier has a problem of an increase in circuit size. 1. A Doherty amplifier comprising:a transistor for a carrier amplifier;a transistor for a peak amplifier;a transmission line connected between an output terminal of the transistor for the carrier amplifier and an output terminal of the transistor for the peak amplifier;a stub that is connected in parallel to the output terminal of the transistor for the peak amplifier and that is capacitive and inductive in a working frequency band; andan output matching circuit connected to the output terminal of the transistor for the peak amplifier, the transmission line, and an output load, the output matching circuit to transform an impedance of the output load into an impedance lower than the impedance of the output load.2. The Doherty amplifier according to claim 1 , wherein the transmission line has an electrical length of less than 90°.3. The Doherty amplifier according to claim 2 , wherein the transmission line has a characteristic impedance higher than a real part of an output impedance of the transistor for the carrier amplifier.4. The Doherty amplifier according to claim 3 , wherein the stub is an open stub having an electrical length of an integral multiple of 180° at one frequency in the working frequency band.5. The Doherty amplifier according to claim 3 , wherein the stub is a short stub having an electrical length of an integral multiple of 90° at one frequency in the working frequency band. This application is a Continuation of PCT International ...

AMPLIFYING APPARATUS

The disclosure provides an amplifying apparatus including a plurality of amplifying circuits and an adjusting circuit. The input terminals of the amplifying circuits are coupled to a first common node. The output terminals of the amplifying circuits are coupled to a second common node. The adjusting circuit adjusts an input signal to generate an adjusted signal to the first common node; the adjusting circuit adjusts the signal of the second common node; or the adjusting circuit adjusts the input signal to generate the adjusted signal to the first common node and adjusts the signal of the second common node. The first control signal and the second control signal respectively control the amplifying circuits and the adjusting circuit to determine the gain, the linear power, and the output current of the amplifying apparatus. 1. An amplifying apparatus , comprising:a plurality of amplifying circuits, wherein an input terminal of each of the plurality of amplifying circuits is coupled to a first common node and an output terminal of each of the plurality of amplifying circuits is coupled to a second common node; andan adjusting circuit, wherein the adjusting circuit is configured to adjust an input signal to generate an adjusted signal to the first common node, the adjusting circuit is configured to adjust a signal of the second common node, or the adjusting circuit is configured to adjust the input signal to generate the adjusted signal to the first common node and adjust the signal of the second common node;wherein the plurality of amplifying circuits are controlled by a first control signal, the adjusting circuit is controlled by a second control signal, the first control signal and the second control signal are used to determine a first operating mode and a second operating mode of the amplifying apparatus, and a gain and an output current of the amplifying apparatus in the first operating mode is greater than the gain and the output current of the amplifying ...

Digital Wireless Transmitter With Merged Cell Switching And Linearization Techniques

A vector distribution method for operation of a power amplifier of a wireless transmitter including receiving, by a first amplifier circuit, a first input vector and a second input vector. The first input vector includes data derived from an input signal of the wireless transmitter and the second input vector includes other data derived from the input signal of the wireless transmitter. The method includes, in response to receiving the input signal, instructing the first amplifier circuit to output an output signal at a high voltage. 120-. (canceled)21. A digital-to-analog converter , comprising:a plurality of digital amplifier cells connected in parallel, each digital amplifier cell is configured to receive a digital input signal and includes a switching circuit driving one or more capacitors;the switching circuit has a first supply voltage and a second supply voltage designed to differ from each other in amplitude by a predefined ratio, wherein the switching circuit is configured to cancel an error between the predefined ratio and a ratio of the amplitude of the first supply voltage and the amplitude of the second supply voltage while outputting a voltage to the one or more capacitors; anda control circuit interfaced with each digital amplifier cell in the plurality of digital amplifier cells and operable to supply the digital input signals to the plurality of digital amplifier cells.22. The digital-to-analog converter of where the switching circuit cancels the error by averaging output voltage from two distinct switched subcircuits.23. The digital-to-analog converter of wherein each digital amplifier cell includes a phase compensation circuit and the phase compensation circuit is configured to compensate for phase difference between the two switched subcircuits.24. The digital-to-analog converter digital wireless transmitter of wherein the predefined ratio is two to one.25. The digital-to-analog converter of wherein the switching circuit includes three or more ...

Generation And Synchronization Of Pulse-Width Modulated (PWM) Waveforms For Radio-Frequency Applications

Described are concepts, systems, circuits and techniques directed toward methods and apparatus for generating one or more pulse width modulated (PWM) waveforms with the ability to dynamically control pulse width and phase with respect to a reference signal.

Envelope tracking frontend device and switch thereof

An envelope tracking frontend device and a switch thereof are provided. The envelope tracking frontend device includes a power amplifier coupled, a switch and an envelope tracking module including an envelope tracking bias supply coupled between the signal generator and the switch. The switch includes a transmit-receive port, a transmit port coupled to the power amplifier, a receive port, a first terminal and a second terminal in series connection, and a third transistor and a fourth transistor as shunt transistors. The envelope tracking bias supply is configured to provide an envelope forward bias signal to the gate of the second transistor and the gate of the fourth transistor, and provide an envelope reverse bias signal to the gate of the first transistor and the gate of the third transistor such that an amplified signal is modulated before being provided by the switch.

HIGH GAIN RESONANT AMPLIFIER FOR RESISTIVE OUTPUT IMPEDANCE

In some implementations, there is provided an apparatus comprising a resonant amplifier circuit including a first inductor having a first inductive input and a first inductive output; a second inductor having a second inductive input and a second inductive output; a first switch coupled to the first inductive output; and a second switch coupled to the second inductive output, wherein the first switch and the second switched are driven out of phase, wherein the first inductor is configured to be resonant with a first capacitance associated with the first switch, and wherein the second inductor is configured to be resonant with a second capacitance associated with the second switch. Related systems and articles of manufacture are also provided. 1. A resonant amplifier circuit comprising:a first inductor having a first inductive input and a first inductive output;a second inductor having a second inductive input and a second inductive output;a first switch coupled to the first inductive output; anda second switch coupled to the second inductive output, wherein the first switch and the second switched are driven out of phase, wherein the first inductor is configured to be resonant with a first capacitance associated with the first switch, and wherein the second inductor is configured to be resonant with a second capacitance associated with the second switch.2. The resonant amplifier of claim 1 , wherein a first terminal of the first switch and a first terminal of the second switch are coupled to a power source.3. The resonant amplifier of further comprising:a power source having a first output and a second output.4. The resonant amplifier of claim 3 , wherein the first output comprises a negative output of the power source claim 3 , wherein the second output comprises a positive output of the power source claim 3 , wherein the positive output is coupled in parallel to the first inductive input and the second inductive input.5. The resonant amplifier of claim 4 , wherein ...

RADIO FREQUENCY SWITCH APPARATUS WITH IMPROVED HARMONIC ATTENUATION CHARACTERISTICS

A radio frequency (RF) switch apparatus includes a signal input terminal; a signal output terminal; a first transistor including a first input terminal connected to the signal input terminal, a first output terminal connected to the signal output terminal, a first gate terminal, and a first body terminal, wherein one of the first input terminal and the first output terminal is a source terminal and another one of the first input terminal and the first output terminal is a drain terminal; a first capacitor circuit connected between the first input terminal and the first body terminal; and a second capacitor circuit connected between the first body terminal and the first output terminal; wherein a first capacitance of the first capacitor circuit is greater than a second capacitance of the second capacitor circuit. 1. A radio frequency (RF) switch apparatus comprising:a signal input terminal;a signal output terminal;a first transistor comprising a first input terminal connected to the signal input terminal, a first output terminal connected to the signal output terminal, a first gate terminal, and a first body terminal, wherein one of the first input terminal and the first output terminal is a source terminal and another one of the first input terminal and the first output terminal is a drain terminal;a first capacitor circuit connected between the first input terminal and the first body terminal; anda second capacitor circuit connected between the first body terminal and the first output terminal;wherein a first capacitance of the first capacitor circuit is greater than a second capacitance of the second capacitor circuit.2. The radio frequency switch apparatus of claim 1 , wherein the first capacitor circuit comprises:a first junction capacitor connected between the first body terminal and the first input terminal; anda first phase compensating capacitor connected in parallel with the first junction capacitor.3. The radio frequency switch apparatus of claim 2 , ...

LOW NOISE DIFFERENTIAL AMPLIFIER

In one general aspect, an amplifier can include an input amplifier circuit configured to receive a bias current and receive, as an input, a signal pair connected differentially to the input amplifier circuit, the input amplifier circuit configured to output a differential output signal pair based on the received differential input signal pair, a feedback amplifier circuit configured to receive an average of the differential output signal pair and configured to provide a bias setting output for controlling the bias current, and an output buffer circuit configured to buffer the differential output signal pair, the buffering resulting in a buffered differential output signal pair capable of driving a resistive load. 1. A pre-amplifier comprising: a feedback amplifier circuit configured to control an output voltage swing of an output differential signal pair in relation to a bias current by providing a constant output voltage signal gain for the output differential signal pair;', 'an input amplifier circuit configured to receive the bias current and configured to receive, as an input, an input differential signal pair connected differentially to the input amplifier circuit through a blocking capacitor, the input amplifier circuit configured to output the output differential signal pair based on the input differential signal pair and the bias current, the input amplifier circuit including a transistor and resistor block controllable to switch output load resistors to the input amplifier circuit; and, 'a first stage including 'a buffer circuit configured to amplify an output signal of the output differential signal pair to generate a buffered output signal configured to drive a resistive load included in a gain module.', 'a second stage including2. The pre-amplifier of claim 1 , further comprising a DC bias module configured to set a high pass filter frequency for the amplifier.3. The pre-amplifier of claim 2 , wherein the DC bias module includes a plurality of resistors ...

Multi-input amplifier with variable gain for individual inputs

Described herein are variable gain amplifiers and multiplexers that embed programmable attenuators into switchable paths to provide variable gain for individual amplifier inputs. The variable gain for an individual input is provided using a amplification stage that is common for each input of the amplifier. A variable attenuation is provided for individual inputs through a combination of a band selection switch and an attenuation selection branch. The attenuation can be tailored for individual inputs and can depend on a gain mode of the amplifier.

HIGH-FREQUENCY AMPLIFIER

A high-frequency amplifier includes: a carrier amplifier which amplifies a first signal; a peak amplifier which amplifies a second signal; a first matching circuit which is connected to the output terminal of the carrier amplifier; a second matching circuit which is connected to the output terminal of the peak amplifier; a first transmission line which is connected between the first matching circuit and the second matching circuit, and has an electric length that is less than ¼ of the wavelength of the center frequency of a predetermined frequency band. The phase rotation by a series inductor which is included in each of the first matching circuit and the second matching circuit and has one end that has been grounded is opposite to the phase rotation by the first transmission line. 1. A high-frequency amplifier which amplifies a first signal and a second signal in a predetermined frequency band to output amplified signals from an output terminal , the high-frequency amplifier comprising:a first amplifier which amplifies the first signal;a second amplifier which amplifies the second signal;a first matching circuit which is connected to an output terminal of the first amplifier;a second matching circuit which is connected to an output terminal of the second amplifier;a first transmission line which is connected between an output terminal of the first matching circuit and an output terminal of the second matching circuit, the first transmission line having an electric length that is less than ¼ of a wavelength of a center frequency of the predetermined frequency band;a second transmission line which is connected to an input terminal of the second amplifier, the second transmission line having an electric length that is less than ¼ of the wavelength of the center frequency of the predetermined frequency band; anda third transmission line which is connected between one end of the first transmission line and the output terminal of the high-frequency amplifier, the third ...

POWER AMPLIFICATION CIRCUIT AND SEMICONDUCTOR DEVICE

A power amplification circuit includes a first amplifier that amplifies a signal split from an input signal, a second amplifier that amplifies a signal having a different phase from the aforementioned signal, third and fourth amplifiers, and a matching network. The matching network includes a first wiring having a first end connected to an output terminal of the first amplifier and a second end connected to an input terminal of the third amplifier, a second wiring having a first end connected to the input terminal of the third amplifier, and electromagnetically coupled to the first wiring, a third wiring having a first end connected to an output terminal of the second amplifier and a second end connected to an input terminal of the fourth amplifier, and a fourth wiring having a first end connected to the input terminal of the fourth amplifier, and electromagnetically coupled to the third wiring. 1. A power amplification circuit comprising:a first amplifier that is input with a first signal and that is configured to output a first amplified signal from an output terminal of the first amplifier, the first signal being split from an input signal, and the first amplified signal being obtained by amplifying the first signal;a second amplifier that is input with a second signal and that is configured to output a second amplified signal from an output terminal of the second amplifier, the second signal being split from the input signal and having a different phase than the first signal, and the second amplified signal being obtained by amplifying the second signal;a third amplifier comprising an input terminal to which the first amplified signal is input, and that is configured to amplify the first amplified signal and to output a third amplified signal;a fourth amplifier comprising an input terminal to which the second amplified signal is input, and that is configured to amplify the second amplified signal and to output a fourth amplified signal; anda matching network ...

IMPEDANCE ELEMENT WITH BUILT-IN ODD-MODE OSCILLATION SUPPRESSION

A transistor package for a power amplifier is provided. The transistor package includes a plurality of radio frequency, RF, paths that includes a first RF path and second RF path. Each RF path includes a transistor-carrying die and at least one impedance element. The transistor package includes a circuit portion electrically coupling a first impedance element in the first RF path to a second impedance element in the second RF path where the circuit portion includes at least one resistor. 1. A transistor package for a power amplifier , the transistor package comprising: a transistor-carrying die; and', 'at least one impedance element; and', 'a circuit portion electrically coupling a first impedance element in the first RF path to a second impedance element in the second RF path, the circuit portion including at least one resistor., 'a plurality of radio frequency, RF, paths including a first RF path and second RF path, each RF path including2. The transistor package of claim 1 , wherein the at least one resistor is configured to suppress odd mode signal components associated with the first and second RF paths.3. The transistor package of claim 1 , wherein the at least one resistor includes at least a first resistor and a second resistor claim 1 , the first resistor being electrically coupled to the first impedance element claim 1 , the second resistor being electrically coupled to the second impedance element claim 1 , and the first and second resistors being electrically coupled to each other.4. The transistor package of claim 1 , wherein the at least one resistor includes at least a first resistor and a second resistor claim 1 , the first resistor being integrated with the first impedance element claim 1 , the second resistor being integrated with the second impedance element claim 1 , and the first and second resistors being electrically coupled to each other.5. The transistor package of claim 1 , wherein the circuit portion includes at least one of:at least one ...

MATCHING CIRCUIT WITH SWITCHABLE LOAD LINES, LOAD LINE SWITCHING METHOD AND POWER AMPLIFIER

The present invention discloses a matching circuit with switchable load lines, a load line switching method and a power amplifier. The matching circuit matches the output impedance of the power amplifier, which amplifies an input signal and outputs an amplified signal. The matching circuit comprises a filter circuit and a switch group for load line selection, the output end of the filter circuit is connected to the switch group. The switch group comprises at least two independent switches, each switch independently constitutes a signal line, and each switch is configured with an external control signal to control on/off. The matching circuit provided by the invention adopts a switch group composed of at least two independent switches, and each independent switch forms a signal line to connect loads, so that multiple loads can be connected at the same time. 1. A matching circuit with switchable load lines , the matching circuit matches an input impedance and an output impedance of a power amplifier , the power amplifier amplifies an input signal and outputs an amplified signal;characterized by comprising a filter circuit and a switch group for load line selection, an output end of the filter circuit is connected to the switch group; the switch group comprises at least two independent switches, each switch independently constitutes a signal line, and each switch is configured with an external control signal to control on/off.2. The matching circuit with switchable load lines of claim 1 , wherein the filter circuit has one of the following structures:1) the filter circuit comprises a low-pass filter A and a low-pass filter B, and the ground of the low-pass filter A is separated from the ground of the low-pass filter B;2) the filter circuit comprises a low-pass filter and a high-pass filter, and the ground of the low-pass filter is separated from the ground of the high-pass filter;3) the filter circuit comprises a low-pass trapper A and a low-pass trapper B, and the ...

POWER AMPLIFICATION CIRCUIT AND TRANSMITTER

Embodiments for a power amplifier that can increase a low-frequency resonance frequency are provided. The power amplifier includes a power amplifying transistor die, a first metal oxide semiconductor capacitor, a direct current decoupling capacitor, and an output matching network, where: a drain of the power amplifying transistor die is connected to a first end of the first metal oxide semiconductor capacitor by using a bonding wire, and a second end of the first metal oxide semiconductor capacitor is grounded; the drain of the power amplifying transistor die is directly connected to the output matching network by using a bonding wire; a source of the power amplifying transistor die is grounded; the first end of the first metal oxide semiconductor capacitor is connected to one end of the direct current decoupling capacitor by using a bonding wire; and the other end of the direct current decoupling capacitor is grounded. 1. A power amplifier , comprising a power amplifying transistor die , a first metal oxide semiconductor capacitor , a direct current decoupling capacitor , and an output matching network , wherein:a drain of the power amplifying transistor die is connected to a first end of the first metal oxide semiconductor capacitor by a first bonding wire, and a second end of the first metal oxide semiconductor capacitor is grounded;the drain of the power amplifying transistor die is directly connected to the output matching network by a second bonding wire, and a source of the power amplifying transistor die is grounded;the first end of the first metal oxide semiconductor capacitor is connected to a first end of the direct current decoupling capacitor by a third bonding wire; anda second end of the direct current decoupling capacitor is grounded.2. The power amplifier according to claim 1 , wherein the first end of the first metal oxide semiconductor capacitor is connected claim 1 , by the third bonding wire claim 1 , to a microstrip on a printed circuit board ...

APPARATUS AND METHODS FOR TUNABLE POWER AMPLIFIERS

A power amplifier is described. The power amplifier including at least a first amplifier stage, and at least a first tunable matching network. The first tunable matching network is configured to couple between a first impedance and a second impedance. The first matching network including at least one first set of metal oxide semiconductor variable capacitor arrays. 1. A power amplifier comprising:at least a first amplifier stage; andat least a first tunable matching network configured to couple between a first impedance and a second impedance, said first matching network including at least one first set of metal oxide semiconductor variable capacitor arrays.2. The power amplifier of claim 1 , further comprising a second amplifier stage.3. The power amplifier of claim 1 , wherein said first tunable matching network is configured to shape the waveform of output of said first power amplifier.4. The power amplifier of claim 2 , wherein said first tunable matching network is coupled with an output of said second amplifier stage.5. The power amplifier of claim 2 , wherein said first tunable matching network is coupled between said first amplifier stage and said second amplifier stage.6. The power amplifier of claim 5 , further comprising at least a second tunable matching network.7. The power amplifier of claim 6 , wherein said second tunable matching network is coupled with an output of said second amplifier stage.8. The power amplifier of claim 6 , wherein at least one of said first tunable matching network and said second tunable matching network is configured to tune a matching impedance claim 6 , said first tunable matching network and said second tunable matching network including at least one set of metal oxide semiconductor variable capacitor arrays.9. The power amplifier of claim 3 , wherein said first tunable matching network is an LC resonator.10. The power amplifier of claim 1 , wherein said at least one first set of metal oxide semiconductor variable ...

MATCHING NETWORK FOR LOAD LINE CHANGE

An amplifier circuit that includes a first power amplifier configured to drive a load and a second power amplifier configured to drive the load through an impedance step-up network. The impedance step-up network is connected to an output of the second power amplifier. The impedance step-up network is configured to switch into a first mode to present an increased impedance to the first power amplifier, and switch into a second mode in which the impedance step-up network steps-up an impedance seen by the second power amplifier looking into the impedance step-up network. 1. An amplifier circuit , comprising:a first power amplifier configured to drive a load;a second power amplifier configured to drive the load through an impedance step-up network; and i) switch into a first mode to present an increased impedance to the first power amplifier; and', 'ii) switch into a second mode in which the impedance step-up network steps up an impedance seen by the second power amplifier looking into the impedance step-up network., 'the impedance step-up network, wherein the impedance step-up network is connected to an output of the second power amplifier, the impedance step-up network being configured to2. The amplifier circuit of claim 1 , wherein the impedance step-up network comprises an inductor and a first capacitor that step up an impedance seen at the output of the second power amplifier looking into the impedance step-up network when the second power amplifier drives the load.3. The amplifier circuit of claim 2 , wherein the impedance step-up network further comprises a switch that switches the impedance step-up network into the first mode to decrease a loading of the impedance step-up network at an output node of the first power amplifier when the first power amplifier drives the load.4. The amplifier circuit of claim 3 , wherein the impedance step-up network further comprises a second capacitor configured to be selectively connected in parallel with the inductor with ...

MULTIPLE-PATH RF AMPLIFIERS WITH ANGULARLY OFFSET SIGNAL PATH DIRECTIONS, AND METHODS OF MANUFACTURE THEREOF

An embodiment of a Doherty amplifier module includes a substrate, an RF signal splitter, a carrier amplifier die, and a peaking amplifier die. The RF signal splitter divides an input RF signal into first and second input RF signals, and conveys the first and second input RF signals to first and second splitter output terminals. The carrier amplifier die includes one or more first power transistors configured to amplify, along a carrier signal path, the first input RF signal to produce an amplified first RF signal. The peaking amplifier die includes one or more second power transistors configured to amplify, along a peaking signal path, the second input RF signal to produce an amplified second RF signal. The carrier and peaking amplifier die are coupled to the substrate so that the RF signal paths through the carrier and peaking amplifier die extend in substantially different (e.g., orthogonal) directions. 1. An amplifier module comprising:a substrate with a mounting surface, wherein a plurality of non-overlapping zones is defined at the mounting surface, including a first-die mounting zone and a second-die mounting zone;a first amplifier die in the first-die mounting zone, wherein the first amplifier die includes one or more first power transistors configured to amplify, along a first signal path, a first input RF signal to produce an amplified first RF signal; anda second amplifier die in the second-die mounting zone, wherein the second amplifier die includes one or more second power transistors configured to amplify, along a second signal path, a second input RF signal to produce an amplified second RF signal, wherein the first amplifier die and the second amplifier die are coupled to the substrate so that the first and second signal paths through the first amplifier die and the second amplifier die extend in substantially different directions.2. The module of claim 1 , further comprising:a first wirebond array coupled between an RF output terminal of the first ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor substrate, a transistor, and a first harmonic termination circuit. The transistor is formed at the semiconductor substrate. The transistor amplifies an input signal supplied to an input end and outputs an amplified signal through an output end. The first harmonic termination circuit attenuates a harmonic component included in the amplified signal. The first harmonic termination circuit is formed at the semiconductor substrate such that one end of the first harmonic termination circuit is connected to the output end of the transistor and the other end of the first harmonic termination circuit is connected to a ground end of the transistor. 1. A semiconductor device comprising:a semiconductor substrate;a transistor that amplifies an input signal supplied to an input end and outputs an amplified signal through an output end, the transistor being on or in the semiconductor substrate, and the transistor being a multi-finger transistor having a plurality of unit transistors;a first harmonic termination circuit that is configured to attenuate a harmonic component of an amplified signal output from an output end of a first unit transistor, the first harmonic termination circuit being on the semiconductor substrate such that a first end of the first harmonic termination circuit is connected to the output end of the first unit transistor and a second end of the first harmonic termination circuit is connected to a ground end of the first unit transistor; anda second harmonic termination circuit configured to attenuate a harmonic component of an amplified signal output from an output end of a second unit transistor, the second harmonic termination circuit being on the semiconductor substrate such that a first end of the second harmonic termination circuit is connected to the output end of the second unit transistor and a second end of the second harmonic termination circuit is connected to a ground end of the second unit ...

CMOS WIDEBAND RF AMPLIFIER WITH GAIN ROLL-OFF COMPENSATION FOR EXTERNAL PARASITICS

The present disclosure relates to an integrated wideband Radio Frequency (RF) amplifier, based on a complementary metal oxide semiconductor (CMOS) technology. In an embodiment the amplifier addresses the shortcomings of conventional wideband amplifiers and is based on a distributed amplifier (DA) topology which typically exhibit severe performance degradation when externally loaded with parasitic circuit elements. In an embodiment of the present invention a buffer amplifier at the output of a conventional DA is able to compensate the impact of parasitic elements. The disclosed circuit can be implemented by fabricating the wideband RF amplifier integrated circuit (IC) on a 130 nm CMOS technology or other comparable CMOS technologies. 1. A wideband RF amplifier comprising:a distributed amplifier comprising plurality of first gain stages, wherein each of the first gain stages comprises a first and a second transistor connected in cascode between an input transmission line and an output transmission line, wherein gate of the first transistor is connected to the input transmission line and source of the first transistor is grounded and drain of the first transistor is connected to the second transistor with an intermediate inductor, and wherein gate of the second transistor is connected to an input filter and drain of the second transistor is connected to the output transmission line; anda buffer amplifier cascaded with the distributed amplifier, wherein the buffer amplifier comprises a plurality of second gain stages connected in parallel, and wherein each of the second gain stages comprises a pair of a third and a fourth transistor connected in cascode with an intermediate inductor, wherein the buffer amplifier incorporates one or more resonant networks and wherein the one or more resonant networks are designed to provide a positive gain slope at higher frequencies.2. The amplifier of claim 1 , wherein the buffer amplifier is connected between the distributed amplifier ...

INVERTED DOHERTY POWER AMPLIFIER WITH LARGE RF FRACTIONAL AND INSTANTANEOUS BANDWIDTHS

Apparatus and methods for an inverted Doherty amplifier operating at gigahertz frequencies are described. RF fractional bandwidth and signal bandwidth may be increased over a conventional Doherty amplifier configuration when impedance-matching components and an impedance inverter in an output network of the inverted Doherty amplifier are designed based on characteristics of the main and peaking amplifier and asymmetry factor of the amplifier. 2. The inverted Doherty amplifier of , wherein Zconsists of a real resistance Rand the impedance value Ris within 20% of the expression in .3. The inverted Doherty amplifier of claim 1 , further comprising an impedance inverter connected in the second circuit branch between the peaking amplifier and the combining node claim 1 , wherein the impedance inverter comprises a microstrip transmission line.4. The inverted Doherty amplifier of claim 3 , wherein the microstrip transmission line has a characteristic impedance that is approximately equal to the impedance at the combining node multiplied by (1+α)/α.5. The inverted Doherty amplifier of claim 3 , wherein the impedance inverter adds a phase delay of approximately 270 degrees.6. The inverted Doherty amplifier of claim 1 , wherein an RF fractional bandwidth of the inverted Doherty amplifier claim 1 , defined by an S11 scattering parameter at the output of the main amplifier looking toward the combining node with the peaking amplifier in a non-amplifying state is between 7% and 25% when an asymmetry factor for the inverted Doherty amplifier is 1.7. The inverted Doherty amplifier of claim 1 , wherein the combining node is arranged to connect directly to a load having an impedance approximately equal to 50 ohms.8. The inverted Doherty amplifier of claim 3 , further comprising:a coupler arranged to divide an input signal into a first signal provided to the first circuit branch and a second signal provided to the second circuit branch and to add a first phase delay to the first ...

MULTIPLE-STAGE POWER AMPLIFIERS IMPLEMENTED WITH MULTIPLE SEMICONDUCTOR TECHNOLOGIES

A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die. 1. A multiple-stage amplifier comprising:a first die that includes a first type of semiconductor substrate, a first radio frequency (RF) signal input terminal, a first RF signal output terminal, a first bias voltage terminal, and a first amplification path between the first RF signal input terminal and the first RF signal output terminal, wherein the first amplification path includes a first transistor, wherein the first transistor has a control terminal and a current-carrying terminal, the control terminal of the first transistor is electrically coupled to the first RF signal input terminal, and the current-carrying terminal of the first transistor is electrically coupled to the first RF signal output terminal and to the first bias voltage terminal, and wherein the first bias voltage terminal is configured to provide a first bias voltage to the first current-carrying terminal; anda second die that is distinct from the first die and that includes a second type of semiconductor substrate that is different from the first type of ...

POWER AMPLIFIER AND RADIO FREQUENCY DEVICE COMPRISING THE SAME

A power amplifier is disclosed for amplifying an input signal and providing an amplified signal to a load at a junction node. The power amplifier comprises a splitter network, a carrier amplifier path and a peaking amplifier path. The peaking amplifier path comprises a first impedance transformer coupled between a peaking output matching network and the junction node to enhance the off-state impedance of the peaking amplifier. The carrier amplifier path comprises a second impedance transformer coupled between a carrier output matching network and the junction node. 1. A power amplifier comprising:a splitter network configured to split an input signal into a carrier input signal and a peaking input signal;a carrier amplifier path comprising at least a carrier amplifier configured to amplify the carrier input signal and carrier input and output matching networks; anda peaking amplifier path combined at a junction node with the carrier amplifier path and comprising at least a peaking amplifier configured to amplify the peaking input signal and peaking input and output matching networks;wherein the peaking amplifier path further comprises a first impedance transformer coupled between an output of the peaking output matching network and the junction node to enhance the off-state impedance of the peaking amplifier; andwherein the carrier amplifier path further comprises a second impedance transformer coupled between an output of the carrier output matching network and the junction node.2. The power amplifier according to claim 1 , wherein the saturation output power ratio between the peaking amplifier and the carrier amplifier is equal to or greater than one.3. The power amplifier according to claim 2 , wherein the first impedance transformer is configured to transform a first output impedance seen from the output of the peaking output matching network into a second output impedance seen from an output of the first impedance transformer claim 2 , the second output ...

BROADBAND HARMONIC LOAD MODULATION DOHERTY AMPLIFIERS

A Doherty power amplifier comprises a splitter network, a first amplifier path comprising at least a first sub-amplifier and a first output matching network; and a second amplifier path comprising at least a second sub-amplifier amplifier and a second output matching network. The Doherty power amplifier further comprises a load modulation network comprising four transmission lines. Each transmission line is a quarter wavelength line at a fundamental frequency of the input signal. 1. A power amplifier comprising:a splitter network configured to split an input signal into a first input signal and a second input signal;a first amplifier path comprising at least a first sub-amplifier configured to amplify the first input signal and a first output matching network;a second amplifier path comprising at least a second sub-amplifier configured to amplify the second input signal and a second output matching network; and a first transmission line coupled between the first output matching network and a first interconnection node;', 'a second transmission line coupled between the second output matching network and a second interconnection node;', 'a third transmission line coupled between the first interconnection node and a power supply; and', 'a fourth transmission line coupled between the first interconnection node and the second interconnection node; wherein each transmission line is a quarter wavelength line at a fundamental frequency of the input signal and wherein the second interconnection node is an output terminal of the power amplifier., 'a load modulation network; wherein the load modulation network comprises2. The power amplifier according to claim 1 , wherein the first transmission line has a characteristic impedance of Z claim 1 , the second transmission line has a characteristic impedance of Z·√{square root over (VSWR/r)} claim 1 , the fourth transmission line has a characteristic impedance of Z·√{square root over (VSWR·r)} claim 1 , and wherein the first claim ...

Doherty amplifier

A package ( 1 ) includes first and second input terminals ( 2,3 ) which are adjacent to each other, and first and second output terminals ( 4,5 ) which are adjacent to each other. A first input matching circuit ( 6 ), a first delay circuit ( 7 ), a second input matching circuit ( 8 ), a first amplifier ( 9 ), and a first output matching circuit ( 10 ) are sequentially connected between the first input terminal ( 2 ) and the first output terminal ( 4 ) inside the package ( 1 ). A third input matching circuit ( 11 ), a second amplifier ( 12 ), a second output matching circuit ( 13 ), a second delay circuit ( 14 ), and a third output matching circuit ( 15 ) are sequentially connected between the second input terminal ( 3 ) and the second output terminal ( 5 ) inside the package ( 1 ). First to fourth matching circuits ( 16 - 19 ) are respectively connected to the first input terminal ( 2 ), the second input terminal ( 3 ), the first output terminal ( 4 ) and the second output terminal ( 5 ) outside the package ( 1 ).

Cascode Amplifier Bias Circuits

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit. 1. An amplifier circuit including:(a) a cascode amplifier having at least two serially connected field effect transistor (FET) stages, each FET stage having a gate, a drain, and a source, the bottom FET stage having an input configured to be coupled to an RF input signal to be amplified, and the top FET stage of the cascode amplifier having an output for providing an amplified RF input signal;(b) a cascode reference circuit having at least two serially connected FET stages, each FET having a gate, a drain, and a source, the gates of the bottom two FET stages of the cascode reference circuit being coupled to the corresponding gates of the bottom two FET stages of the cascode amplifier, for biasing the cascode amplifier to output a final current approximately equal to a multiple of a mirror current in the cascode reference circuit;(c) a current source, coupled to the drain of the top FET stage of the cascode reference circuit; and(d) a source follower FET having a gate, a drain, and a source, the drain of the source follower FET ...

POWER AMPLIFIER CIRCUIT

A power amplifier circuit includes a first amplifier that amplifies an input signal and outputs a first amplified signal, a second amplifier that is disposed subsequent to the first amplifier and that amplifies the first amplified signal and outputs a second amplified signal, and a clamp circuit that is disposed between ground and a signal line extending between the first amplifier and the second amplifier and that suppresses an amplitude of the first amplified signal. 1. A power amplifier circuit comprising:a first amplifier configured to amplify an input signal and to output a first amplified signal;a second amplifier that is subsequent to the first amplifier along a signal line, and that is configured to amplify the first amplified signal and to output a second amplified signal; anda clamp circuit that is between ground and the signal line, and that is configured to suppress an amplitude of the first amplified signal.2. The power amplifier circuit according to claim 1 , wherein the clamp circuit comprises:a diode section comprising a first diode having an anode connected to a signal line side of the diode section, and a cathode connected to a ground side of the diode section, anda transistor section comprising a first transistor having a base, a collector connected to the signal line, and an emitter connected to ground, wherein a signal is input to the base of the first transistor via the diode section.3. The power amplifier circuit according to claim 2 , wherein the diode section comprises a plurality of diodes connected in series with each other claim 2 , the plurality of diodes including the first diode.4. The power amplifier circuit according to claim 2 , wherein the diode section further comprises a resistance element connected in series with the first diode.5. The power amplifier circuit according to claim 3 , wherein the diode section further comprises a resistance element connected in series with the first diode.6. The power amplifier circuit according to ...

HIGH FREQUENCY MODULE AND COMMUNICATION DEVICE

A high frequency module includes a first amplifier circuit, a second amplifier circuit, a first matching circuit connected to the first amplifier circuit, and a second matching circuit connected to the second amplifier circuit, wherein the first matching circuit and the second matching circuit are arranged adjacent to each another. The first matching circuit may be provided on an output side of the first amplifier circuit. 1. A high frequency module comprising:a first amplifier circuit;a second amplifier circuit;a first matching circuit connected to the first amplifier circuit; anda second matching circuit connected to the second amplifier circuit, whereinthe first matching circuit and the second matching circuit are arranged adjacent to each another.2. The high frequency module according to claim 1 , whereinthe first matching circuit is connected to an output port of the first amplifier circuit, andthe second matching circuit is connected to an output port of the second amplifier circuit.3. The high frequency module according to claim 1 , whereinthe first matching circuit includes a first element,the second matching circuit includes a second element, andthe first element and the second element are coupled by at least one of electrical coupling or magnetic coupling.4. The high frequency module according to claim 2 , whereinthe first matching circuit includes a first element,the second matching circuit includes a second element, andthe first element and the second element are coupled by at least one of electrical coupling or magnetic coupling.5. The high frequency module according to claim 3 , whereinthe first element is a first inductive element connected between an input port and an output port of the first matching circuit,the second element is a second inductive element connected between an input port and an output port of the second matching circuit, andthe first inductive element and the second inductive element are magnetically coupled.6. The high frequency ...

Integrated RF Front End with Stacked Transistor Switch

A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal. A preferred embodiment of the RF transceiver IC includes two distinct PA circuits, two distinct receive signal amplifier circuits, and a four-way antenna switch to selectably couple a single antenna connection to any one of the four circuits. 1. A module comprising: at least one integrated RF Power Amplifier (PA) circuit; an input node to accept an input signal with respect to a reference voltage, the input node connected to a first gate of a first MOSFET, wherein a source of the first MOSFET is connected to the reference voltage;', 'one or more MOSFETs connected in series with the first MOSFET to form a transistor stack, wherein the first MOSFET comprises a bottom transistor of the transistor stack, and the one or more MOSFETs comprise intermediate transistors and/or a top transistor of the transistor stack, wherein the transistor stack is configured to control conduction between the reference voltage and an output drive node, and wherein the output drive node is connected to a drain of the top transistor of the transistor stack; and', 'one or more predominantly capacitive elements connected directly between a corresponding gate of the one or ...

INTEGRATED RF FRONT END SYSTEM

Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements. 1. (canceled)2. A semiconductor device for an integrated front-end module comprising:a high-resistivity bulk silicon substrate having a first impurity type and a top surface that lies in a top plane;a silicon germanium bipolar transistor disposed above the high-resistivity bulk silicon substrate;a well located between the silicon germanium bipolar transistor and a passive device, the well providing at least partial electrical isolation between the bipolar transistor and the passive device; anda trench disposed between a sub-collector region of the silicon germanium bipolar transistor and the well, the trench a distance away from the sub-collector region and configured to impede movement across the trench of carriers in the high-resistivity bulk silicon substrate.3. The semiconductor device of wherein the sub-collector region is of a second impurity type that differs from the first impurity type.4. The semiconductor device of further comprising a low-resistivity epitaxial layer disposed adjacent to the top surface and lying in a plane parallel to the top plane.5. The semiconductor device of wherein a resistivity of the low-resistivity epitaxial layer is within a range of around 1-100 Ohms*cm.6. The semiconductor device of wherein the low-resistivity epitaxial layer is of a second impurity type that differs from the first impurity type.7. The semiconductor device of wherein a resistivity of the high-resistivity bulk silicon substrate is at least approximately 1000 Ohms*cm.8. The semiconductor device of wherein the well has a ...

POWER AMPLIFICATION MODULE

Provided is a power amplification module that includes: an amplification transistor that has a constant power supply voltage supplied to a collector thereof, a bias current supplied to a base thereof and that amplifies an input signal input to the base thereof and outputs an amplified signal from the collector thereof; a first current source that outputs a first current that corresponds to a level control voltage that is for controlling a signal level of the amplified signal; and a bias transistor that has the first current supplied to a collector thereof, a bias control voltage connected to a base thereof and that outputs the bias current from an emitter thereof. 1. A power amplification module comprising:an amplification transistor that has a constant power supply voltage supplied to a collector of the amplification transistor, that has a bias current supplied to a base of the amplification transistor and that amplifies an input signal input to the base of the amplification transistor and outputs an amplified signal from the collector of the amplification transistor;a first current source that outputs a first current that corresponds to a level control voltage that controls a signal level of the amplified signal; anda bias transistor that has the first current supplied to a collector of the bias transistor, a bias control voltage connected to a base of the bias transistor and that outputs the bias current from an emitter of the bias transistor.2. The power amplification module according to claim 1 , wherein when the level control voltage is at a second level claim 1 , a rate of change of the first current is larger than a rate of change of the first current when the level control voltage is at a first level claim 1 , the second level being higher than the first level.3. The power amplification module according to claim 1 , further comprising:a first voltage source that supplies a constant first voltage to the collector of the bias transistor.4. The power ...

Control Circuit and Method for Controlling an Operation of a Power Amplifier

A control circuit and a method for controlling an operation of a power amplifier core are provided. The power amplifier core is switchable between an envelope tracking operation mode and a non-envelope tracking operation mode. The control circuit is configured to provide a control signal for controlling the operation of the power amplifier core or to process an amplified signal received from the power amplifier core in dependence on the operation mode of the power amplifier core.

Amplifier circuits

Radio Frequency (RF) amplifier circuits are disclosed which may exhibit improved video/instantaneous bandwidth performance compared to conventional circuits. For example, disclosed RF amplifier circuits may employ a baseband decoupling network connected in parallel with a low-pass RF matching network of the amplifier circuit.

INVERTED DOHERTY POWER AMPLIFIER WITH LARGE RF FRACTIONAL AND INSTANTANEOUS BANDWIDTHS

Apparatus and methods for an inverted Doherty amplifier operating at gigahertz frequencies are described. RF fractional bandwidth and signal bandwidth may be increased over a conventional Doherty amplifier configuration when impedance-matching components and an impedance inverter in an output network of the inverted Doherty amplifier are designed based on characteristics of the main and peaking amplifier and asymmetry factor of the amplifier. 1. An inverted Doherty amplifier comprising:a main amplifier in a first circuit branch;a peaking amplifier in a second circuit branch;a combining node located where a first portion of the first circuit branch after the main amplifier connects with a second portion of the second circuit branch after the peaking amplifier;{'sub': 'comb', 'a first impedance-matching component connected in the first portion of the first circuit branch between the main amplifier and the combining node, the first impedance-matching component comprising an output impedance of R; and'}{'sub': 'comb', 'an impedance inverter connected in the second portion of the second circuit branch between the peaking amplifier and the combining node, the impedance inverter comprising an impedance value of R/α, where a is an asymmetry factor for the inverted Doherty amplifier, and the asymmetry factor is a ratio of a maximum power output by the peaking amplifier to a maximum power output by the main amplifier.'}2. The inverted Doherty amplifier of claim 1 , further comprising an output port connected to the combining node and configured to connect to an external circuit with no impedance-matching component located between the output port and the combining node.3. The inverted Doherty amplifier of claim 1 , wherein an impedance on the second circuit branch before the combining node is R/α claim 1 , an impedance after the combining node is R/β claim 1 , and β is 1+α.5. The inverted Doherty amplifier of claim 1 , wherein the impedance inverter adds a phase delay of ...

Source Switched Split LNA

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

Automatic impedance matching using true power information

Aspects of this disclosure relate to systems and methods of performing dynamic impedance tuning. Certain aspects may be performed by or include a dynamic impedance matching network. The dynamic impedance matching network can determine a desired output power for a power amplifier, true power information for the power amplifier, and an output power delivered to a load by the power amplifier. In addition, the dynamic impedance matching network can determine whether the output power satisfies the true power information. Responsive to this determination, the dynamic impedance matching network may modify a load line impedance for the power amplifier using an impedance tuning network.

RADIO FREQUENCY (RF) TRANSCEIVER AND OPERATING METHOD THEREOF

A radio frequency (RF) transceiver includes a first oscillator configured to generate a first oscillation frequency associated with an RF signal, a second oscillator configured to generate a second oscillation frequency associated with a clock frequency, a counter configured to generate a counter output signal using the first oscillation frequency and the second oscillation frequency, and a comparer configured to generate a digital output signal associated with the RF signal by comparing an output value of the counter output signal to a reference value. 1. A radio frequency (RF) transceiver comprising:a first oscillator configured to generate a first oscillation frequency associated with an RF signal;a second oscillator configured to generate a second oscillation frequency associated with a clock frequency;a counter configured to generate a counter output signal using the first oscillation frequency and the second oscillation frequency; anda comparer configured to generate a digital output signal associated with the RF signal by comparing an output value of the counter output signal to a reference value.2. The RF transceiver of claim 1 , wherein the counter output signal is associated with a ratio of the first oscillation frequency to the second oscillation frequency.3. The RF transceiver of claim 1 , wherein the first oscillator comprises:an antenna configured to receive the RF signal;a negative R-generator electrically connected to the antenna; anda capacitor bank connected in parallel with the antenna and the negative R-generator.4. The RF transceiver of claim 1 , further comprising:a quenching wave generator configured to generate a quenching signal that controls a negative R-generator of the first oscillator using the second oscillation frequency.5. The RF transceiver of claim 4 , further comprising:an auto gain calibration controller configured to disable the quenching wave generator and the negative R-generator in response to an input power of the RF signal ...

Field effect transistor (fet) structure with integrated gate connected diodes

A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: a source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.

Phase-Switched Impedance Modulation Amplifier

Described is a phase-switched phase-switched, impedance modulation amplifier (PSIM). The PSIM has an input that can be coupled to a source and an output that can be coupled to a load. The PSIM includes one or more phase-switched reactive elements and a controller. The controller provides a control signal to each of the one or more phase-switched reactive elements. In response to one or more control signals provided thereto, each phase-switched reactive element provides a corresponding selected reactance value such that an impedance presented to an input or output port of an RF amplifier may be varied. 1an RF amplifier having an input port coupled to the input port of the RF amplifier system and having an output port; anda phase-switched tunable impedance network coupled between the output port of the RF amplifier and an output port of the RF amplifier system, the phase-switched tunable impedance network configured such that in response to input signal provided thereto, the phase-switched tunable impedance network varies an impedance thereof to modulate an impedance presented to the output port of the RF amplifier.. A radio frequency (RF) amplifier system having an input port and an output port, the RF amplifier system comprising: This application is a continuation of U.S. application Ser. No. 14/975,742 filed on Dec. 19, 2015 which is a continuation of and claims the benefit under 35 U.S.C. § 120 of U.S. application Ser. No. 14/974,563, filed on Dec. 18, 2015, now U.S. Pat. No. 9,755,576 and which claims the benefit under 35 U.S.C. § 119(e) of U.S. provisional application No. 62/094,144, filed on Dec. 19, 2014. Each of the above applications are hereby incorporated herein by reference in its entireties.Impedance matching networks are commonly used for maximizing power transfer within many radio frequency (RF) and microwave systems. For example, in RF transmitters, impedance matching networks might be used to provide an impedance match from an output impedance of an ...

Integrated Ultra-Compact VSWR Insensitive Coupler

A ultra-compact coupler designed to sample the actual output power of a power amplifier and which is “VSWR insensitive”, such that reflected power is essentially not coupled to a detector circuit and only forward power is detected and processed. In a first embodiment, a coupler is situated between the final amplifier stage of a power amplifier and an output impedance matching network, and is specially configured for operation in a low impedance environment in conjunction with a detector circuit, thereby substantially reducing the areal size of the coupler. In a second embodiment, a coupler is integrated within an output impedance matching network coupled to the final amplifier stage of a power amplifier so as to share an inductor between the coupler and the output impedance matching network, thereby further substantially reducing the areal size of the coupler.

ULTRA COMPACT MULTI-BAND TRANSMITTER WITH ROBUST AM-PM DISTORTION SELF-SUPPRESSION TECHNIQUES

A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. The final stage can include an output passive network that suppresses suppress an amplitude modulation-to-phase modulation (AM-PM) distortion. During a back-off power mode a bias of a capacitive unit of the output power network component can be adjusted to minimize an overall capacitance variation. A output passive network can further generate a flat-phase response between dual resonances of operation. 1. An apparatus of a mobile device for amplifying radio frequency signals , comprising:a plurality of n-bit binary weighted differential amplifier cells coupled to an output passive network and respectively comprise a pair of amplification transistors and a pair of cascode transistors, wherein the pair of amplification transistors comprises a smaller gate than the pair of cascode transistors;the output passive network comprising a transformer and a plurality of capacitive units coupled in parallel with one another; anda processing circuitry configured to power on or off the at least one of the pair of cascode transistors based on an amplification setting or a voltage threshold.2. The apparatus of claim 1 , wherein the pair of cascode transistors are connected to drain terminals of the pair of amplification transistors claim 1 , respectively.3. The apparatus of claim 1 , wherein the output passive network comprises at least two inductors.4. The apparatus of claim 1 , wherein the pair of amplification transistors comprise thin transistors and the pair of cascode transistors comprise thick transistors that comprise a greater gate width than the thin transistors.5. The apparatus of claim 1 , wherein the transformer of the output passive network comprises a single transformer connected directly to the plurality of n-bit binary weighted ...

POWER AMPLIFIER WITH EACH OF MULTIPLE IN-PARALLEL CIRCUITS HAVING POWER AMPLIFICATION AND IMMITTANCE CONVERSION

Exemplary aspects are directed to a power-amplification circuit including multiple in-parallel circuit paths, each including a power amplifier driving an immittance converter. Current from each output of the respective immittance converters is combined for delivery to a load. In a more specific example, a control circuit may be used to modulate, such as by enabling or disabling power delivered from, one or more of the power amplifiers for fast, coarse resetting of the overall power delivered to the load, and/or to modulate one or more of the modulate immittance converters (e.g., via a phase or signal-timing adjustment) to finely tune the resetting of the overall power delivered to the load. Using the control circuit for providing both the coarse adjustment and the fine adjustment, and fast acting precise delivery of overall power delivered to a load may be realized for any of a variety of applications. 1. A power-amplification circuit comprising:a plurality of power amplifiers arranged in parallel to drive a plurality of immittance converters also in parallel, wherein each of the plurality of immittance converters has an input driven by an output of at least one of the plurality of power amplifiers;current-combining circuitry to combine current, provided in response to output ports of the plurality of immittance converters, at an output node; andload circuitry coupled to the current-combining circuitry via the output node.2. The power-amplification circuit of claim 1 , further including a control circuit having an input port coupled to the load and having at least one output port in a feedback path to control at least one of the plurality of power amplifiers arranged in parallel.3. The power-amplification circuit of claim 1 , wherein current-combining circuitry to combine current includes a plurality of transformers to couple the current for combination on a load side of the plurality of transformers claim 1 , and wherein the output node is between the load side of ...

DOHERTY POWER AMPLIFIER CIRCUIT

A Doherty power amplifier circuit having a main power amplification device, an auxiliary power amplification device arranged in parallel with the main power amplification device, and a load modulation circuit comprising a harmonic injection circuit connected with respective outputs of the main power amplification device and the auxiliary power amplification device. The harmonic injection circuit is arranged to transfer harmonic components generated at the main power amplification device to the auxiliary power amplification device and harmonic components generated at the auxiliary power amplification device to the main power amplification device, when both o the main and auxiliary power amplification devices are operating, for modulating the respective outputs of the main power amplification device and the auxiliary power amplification device. 1. A Doherty power amplifier circuit , comprising:a main power amplification device;an auxiliary power amplification device arranged in parallel with the main power amplification device; anda load modulation circuit comprising a harmonic injection circuit connected with respective outputs of the main power amplification device and the auxiliary power amplification device,wherein the harmonic injection circuit is arranged to transfer harmonic components generated at the main power amplification device to the auxiliary power amplification device and harmonic components generated at the auxiliary power amplification device to the main power amplification device, when both the main and auxiliary power amplification devices are operating, for modulating the respective outputs of the main power amplification device and the auxiliary power amplification device.2. The Doherty power amplifier circuit of claim 1 , wherein the Doherty power amplifier circuit is free of additional power amplification device for amplifying harmonic components generated by the main power amplification device and the auxiliary power amplification device.3. ...

LINEARIZING CIRCUIT AND METHOD FOR AMPLIFIER

Linearizing circuit and method for amplifier. In some embodiments, a biasing circuit assembly for an amplifier can include a biasing circuit configured to provide a first bias signal or a second bias signal through a common node and a ballast to an input path of an amplifying transistor for operation in a first mode or a second mode, respectively. The biasing circuit assembly can further include a linearizing circuit implemented to couple the common node and a node along the input path. The linearizing circuit can be configured to improve linearity of the amplifying transistor operating in the first mode while allowing the ballast to be sufficiently robust for the amplifying transistor operating in the second mode. 1. A biasing circuit assembly for an amplifier , comprising:a biasing circuit configured to provide a first bias signal or a second bias signal through a common node and a ballast to an input path of an amplifying transistor for operation in a first mode or a second mode, respectively; anda linearizing circuit implemented to couple the common node and a node along the input path, and configured to improve linearity of the amplifying transistor operating in the first mode while allowing the ballast to be sufficiently robust for the amplifying transistor operating in the second mode.2. The biasing circuit assembly of wherein the ballast includes a DC ballasting resistor.3. The biasing circuit assembly of wherein the amplifying transistor is part of a power amplifier.4. The biasing circuit assembly of wherein the amplifying transistor is part of a second stage of a two-stage power amplifier.5. The biasing circuit assembly of wherein the amplifying transistor is a bipolar-junction transistor having a base claim 1 , a collector claim 1 , and an emitter claim 1 , such that the input path is connected to the base.6. The biasing circuit assembly of wherein the linearizing circuit includes a capacitance.7. The biasing circuit assembly of wherein the linearizing ...

BALUN TRANSFORMER

A balun includes a dielectric layer having first and second sides, an electrically conductive plate on the second side of the dielectric layer, a first electrically conductive line on the first side and comprising a first end electrically connected to a first terminal and a second end, a second electrically conductive line on the second side and comprising a third end electrically coupled to a second terminal and a fourth end connected to an unbalanced terminal and a micro strip line comprising a fifth end electrically connected to the third end and a sixth end. The first electrically conductive line overlaps the second electrically conductive line. The second and the sixth ends are electrically coupled to the electrically conductive plate. The electrically conductive plate is hollowed in at least a region corresponding to an overlap area of the first electrically conductive line and second electrically conductive line. 1. A balun for transforming signals between an unbalanced impedance and a balanced impedance , comprising:a stack of at least an electrically conductive plate, and a dielectric layer having a first side and a second side opposite to the first side;a first electrically conductive line comprising a first end and a second end, arranged on the dielectric layer at the first side of the dielectric layer;a second electrically conductive line comprising a third end and a fourth end, arranged on the dielectric layer at the second side of the dielectric layer such that the first electrically conductive line substantially overlaps the second electrically conductive line; anda micro strip line comprising a fifth end electrically coupled to the third end and a sixth end electrically coupled to the electrically conductive plate; whereinthe electrically conductive plate is arranged on the dielectric layer at the second side,the first end is electrically coupled to the balanced impedance, the second end is electrically coupled to the electrically conductive plate, ...

DIVERSITY RECEIVER FRONT END SYSTEM WITH AMPLIFIER PHASE COMPENSATION

Diversity receiver front end system with amplifier phase compensation. A receiving system can include a first amplifier disposed along a first path, corresponding to a first frequency band, between an input of the receiving system and an output of the receiving system. The receiving system can include a second amplifier disposed along a second path, corresponding to a second frequency band, between the input of the receiving system and the output of the receiving system. The receiving system can include a first phase-shift component disposed along the first path and configured to phase-shift the second frequency band of a signal passing through the first phase-shift component based on a phase-shift caused by the first amplifier at the second frequency band. 1. A receiving system comprising:a first amplifier disposed along a first path, corresponding to a first frequency band, between an input of the receiving system and an output of the receiving system;a second amplifier disposed along a second path, corresponding to a second frequency band, between the input of the receiving system and the output of the receiving system; anda first phase-shift component disposed along the first path and configured to phase-shift the second frequency band of a signal passing through the first phase-shift component based on a phase-shift caused by the first amplifier at the second frequency band.2. The receiving system of further comprising a second phase-shift component disposed along the second path and configured to phase-shift the first frequency band of a signal passing through the second phase-shift component based on a phase-shift caused by the second amplifier at the first frequency band.3. The receiving system of wherein the first phase-shift component is further configured to phase-shift a third frequency band of the signal passing through the first phase-shift component based on a phase-shift caused by the first amplifier at the third frequency band.4. The receiving ...

Integrated Passive Device for RF Power Amplifier Package

The present disclosure relates to a radio frequency (RF) power transistor package. It further relates to a mobile telecommunications base station comprising such an RF power transistor package, and to an integrated passive die suitable for use in an RF power amplifier package. In example embodiments, an in-package impedance network is used that is connected to an output of the RF power transistor arranged inside the package. This network comprises a first inductive element having a first and second terminal, the first terminal being electrically connected to the output of the RF transistor, a resonance unit electrically connected to the second terminal of the first inductive element, and a second capacitive element electrically connected in between the resonance unit and ground, where the first capacitive element is arranged in series with the second capacitive element. 1. A radio frequency (RF) power amplifier package , comprising:a package;a first semiconductor die arranged inside the package, wherein the first semiconductor die comprises an RF power transistor that has an output capacitance (Cds) and is configured to amplify signals at an operational frequency; [{'b': '1', 'a first inductive element (L) having a first terminal and a second terminal, the first terminal being electrically connected to an output of the RF transistor;'}, {'b': '1', 'a resonance unit being electrically connected to the second terminal of L; and'}, {'b': '2', 'a second capacitive element (C) electrically connected in between the resonance unit and a ground terminal;'}], 'an impedance network arranged inside the package and comprising{'b': 2', '2', '1', '1', '1', '1, 'wherein the resonance unit comprises (i) a second inductive element (L) electrically connected in between C and L and (ii) a first capacitive element (C) having a first terminal and a second terminal, the first terminal of C being electrically connected to the second terminal of L;'}{'b': 2', '1, 'wherein the capacitance ...

BROADBAND MATCHING NETWORK

The invention describes a broadband matching network for coupling to an output of an amplifying device for amplifiers with a nominal operating frequency between 1 MHz and 100 MHz. The broadband matching network comprises a planar transformer with a primary winding arranged on a primary side of the broadband matching network and a secondary winding arranged on a secondary side of the broadband matching network. The primary winding is arranged to be electrically connected to the output of the amplifying device. The broadband matching network is characterized by a center frequency and a bandwidth with a frequency range of at least +/−3%. A first parallel resonance frequency and a second parallel resonance frequency of the broadband matching circuit are arranged around the series resonance frequency such that a frequency dependence of a load impedance provided by the broadband matching network for the amplifying device is reduced. 1. A broadband matching network for coupling to an output of an amplifying device for an amplifier arrangement with a nominal operating frequency between 1 MHz and 100 MHz , more preferably between 5 MHz and 85 MHz and an output power of at least 100 W , more preferably at least 200 W and most preferably at least 250 W , wherein the broadband matching network comprises a planar transformer with a primary winding arranged on a primary side of the broadband matching network and a secondary winding arranged on a secondary side of the broadband matching network , wherein the primary winding is arranged to be electrically connected to the output of the amplifying device , wherein the broadband matching network is characterized by a center frequency and a bandwidth with a frequency range of at least +/−3% , preferably at least +/−5% , more preferably at least +/−7% around the center frequency , wherein the center frequency corresponds to the nominal operating frequency , and wherein the broadband matching network is arranged such that a series ...

Logarithmic Detector Amplifier System for Use as High Sensitivity Selective Receiver Without Frequency Conversion

A logarithmic detector amplifying (LDA) system is provided for use as a high sensitivity receive booster or replacement for a low noise amplifier in a receive chain of a communication device. The LDA system includes an amplifying circuit configured to receive an input signal having a first frequency and generate an oscillation based on the input signal, a sampling circuit coupled to the amplifying circuit and configured to terminate the oscillation based on a predetermined threshold to periodically clamp and restart the oscillation to generate a series of pulses modulated by the oscillation and by the input signal, and one or more resonant circuits coupled with the amplifying circuit and configured to establish a frequency of operation and to generate an output signal having a second frequency, the second frequency being substantially the same as the first frequency. 1. A system for use in a receive chain of a communication device , the system comprising: an amplifying circuit configured to receive a first LDA input signal at the first LDA input from a system input having a first frequency and to generate an oscillation based on the first LDA input signal;', 'a sampling circuit coupled to the amplifying circuit and configured to terminate the oscillation based on a predetermined threshold so as to periodically clamp and restart the oscillation to generate a series of voltage spikes as a first LDA output signal at the first LDA output, wherein the series of voltage spikes have a frequency, wherein the frequency of the voltage spikes varies substantially with a logarithm of a power of the first LDA input signal; and', 'a resonant circuit coupled to the amplifying circuit and configured to generate a second LDA output signal at the second LDA output; and', 'a phase lock loop (PLL) coupled between the first LDA output, the second LDA output and a second LDA input, the phase lock loop including a comparator, a switch and a low pass filter, the comparator being configured ...

Matching network circuit and Radio-Frequency Power Amplifier with Odd Harmonic Rejection and Even Harmonic Rejection and Method of Adjusting Symmetry of Differential Signals

A radio-frequency (RF) power amplifier includes a matching network comprising at least one matching network circuit corresponding to at least one symmetry node, at least one detector for detecting power of a detected signal at the symmetry node of the matching network, and generating at least on control signal according to the power of the detected signal, wherein the detected signal is an odd harmonic of an RF signal when the RF power amplifier operates in a differential mode or an even harmonic of the RF signal when the RF power amplifier operates in a common mode, and at least one adjusting circuit for adjusting the RF signal according to the at least one control signal. 1. A radio-frequency (RF) power amplifier , comprising:a matching network comprising at least one matching network circuit corresponding to at least one symmetry node, for receiving an RF signal amplified by the RF power amplifier;at least one detector, coupled to the at least one symmetry node corresponding to the at least one matching network circuit, for detecting power of a detected signal at the symmetry node of the matching network, and generating at least on control signal according to the power of the detected signal, wherein the detected signal is an odd harmonic of the RF signal when the RF power amplifier operates in a differential mode or an even harmonic of the RF signal when the RF power amplifier operates in a common mode; andat least one adjusting circuit, coupled to the power detector, for adjusting the RF signal according to the at least one control signal.2. The RF power amplifier of claim 1 , wherein the at least one detector is a power detector claim 1 , a voltage detector claim 1 , or a current detector claim 1 , and the at least one signal corresponds to a power claim 1 , a voltage or a current of the detected signal.3. The RF power amplifier of claim 1 , wherein the at least one detector is frequency selective to detect the detected signal with a differential resonant ...

AMPLIFIER WITH INTEGRATED TEMPERATURE SENSOR

A device includes a semiconductor die including a transistor. The transistor includes a plurality of parallel transistor elements. Each transistor element includes a drain region, a source region, and a gate region. The semiconductor die includes a first temperature sensor between a first transistor element in the plurality of transistor elements and a second transistor element in the plurality of transistor elements. The first temperature sensor is configured to generate a first output signal having a magnitude that is proportional to a temperature of the first temperature sensor. 1. A system , comprising: a transistor formed in an active area of the semiconductor die, the transistor including an output terminal and a control terminal,', 'a first temperature sensor contact pad, and', 'a first temperature sensor, wherein a first portion of the active area is on a first side of the first temperature sensor and a second portion of the active area is on a second side of the first temperature sensor opposite the first side, the first temperature sensor is between the control terminal and the output terminal, the first temperature sensor is coupled to the first temperature sensor contact pad, and the first temperature sensor is configured to generate a first output signal at the first temperature sensor contact pad, wherein a magnitude of the first output signal is proportional to a temperature of the first temperature sensor; and, 'a semiconductor die, including determine that a magnitude of the first output signal of the first temperature sensor has passed a threshold, and', 'in response to determining the magnitude of the first output signal of the first temperature sensor has passed the threshold, modify an operation of the transistor., 'a control circuit coupled to the first temperature sensor contact pad, wherein the control circuit is configured to2. The system of claim 1 , wherein the transistor includes a plurality of drain regions coupled to the output terminal ...

DIRECT SUBSTRATE TO SOLDER BUMP CONNECTION FOR THERMAL MANAGEMENT IN FLIP CHIP AMPLIFIERS

Solder bumps are placed in direct contact with the silicon substrate of an amplifier integrated circuit having a flip chip configuration. A plurality of amplifier transistor arrays generate waste heat that promotes thermal run away of the amplifier if not directed out of the integrated circuit. The waste heat flows through the thermally conductive silicon substrate and out the solder bump to a heat-sinking plane of an interposer connected to the amplifier integrated circuit via the solder bumps. 1. A device comprising:an amplifier including at least one transistor formed over a silicon substrate; anda metal pillar formed with respect to the silicon substrate such that a portion of the metal pillar is in direct contact with the silicon substrate, heat generated during operation of the at least one transistor being transferred through the silicon substrate to the portion of the metal pillar.2. The device of further comprising a first resistor in communication with an emitter of the at least one transistor and with the metal pillar.3. The device of further comprising a second resistor in communication with a base of the at least one transistor.4. The device of wherein the metal pillar is formed within a cavity etched into the silicon substrate.5. The device of wherein the metal pillar protrudes outward and upward from the cavity.6. The device of wherein the portion of the metal pillar in direct contact with the silicon substrate is a bottom and at least a portion of sides of the metal pillar7. The device of wherein the portion of the metal pillar in direct contact with the silicon substrate is a bottom of the metal pillar.8. The device of wherein the metal pillar is configured to provide a flip chip interconnection for the amplifier.9. The device of wherein the metal pillar is adjacent to the at least one transistor.10. A method to implement an emitter-ballasted amplifier in a flip chip configuration claim 1 , the method comprising:forming an amplifier including at ...

AMPLIFIER

An amplifier according to an embodiment of the present disclosure includes a first transistor and a first matching circuit. The first matching circuit is connected between an input terminal and a control terminal of the first transistor. A first terminal of the first transistor is connected to a ground. A second terminal of the first transistor is connected to a power supply and an output terminal. The first matching circuit includes a first inductor, a second inductor, and a first switch. The first inductor has an end connected to the control terminal. The second inductor has an end connected to the other end of the first inductor. The first switch is configured to selectively switch between electrical continuity between the input terminal and the other end of the first inductor and electrical continuity between the input terminal and the other end of the second inductor. 1. An amplifier having an input terminal and an output terminal , for amplifying a signal input from the input terminal and outputting an amplified signal from the output terminal , comprising:a first transistor including a control terminal, a first terminal, and a second terminal; anda first matching circuit connected between the input terminal and the control terminal of the first transistor, wherein:the first terminal of the first transistor is connected to a ground,the second terminal of the first transistor is connected to a power supply and the output terminal, and a first inductor having a first end and a second end, the first end of the first inductor being connected to the control terminal,', 'a second inductor having a first end and a second end, the first end of the second inductor being connected to the second end of the first inductor, and', 'a first switch configured to selectively connect the input terminal to the second end of the first inductor or the second end of the second inductor., 'the first matching circuit comprises2. The amplifier according to claim 1 , wherein the first ...

Power generation systems and methods for plasma stability and control

Embodiments are described herein for power generation systems and methods that use quadrature splitters and combiners to facilitate plasma stability and control. For one embodiment, a quadrature splitter receives an input signal and generates a first and second signals as outputs with the second signal being ninety degrees out of phase with respect to the first signal. Two amplifiers then generate a first and second amplified signals. A quadrature combiner receives the first and second amplified signals and generates a combined amplified signal that represents re-aligned versions of the first and second amplified signals. The power amplifiers can be combined into a system to generate a high power output to a processing chamber. Further, detectors can generate measurements used to monitor and control power generation. The power amplifiers, system, and methods provide significant advantages for high-power generation delivered to process chambers for plasma generation during plasma processing.

WIDE BANDPASS FILTERING POWER AMPLIFIER

A wide bandpass filtering power amplifier using discriminating coupling is disclosed, which comprises a DC bias circuit, an input impedance matching circuit, a transistor and an output impedance matching circuit. The DC bias circuit is connected to the input impedance matching circuit which is further connected to the transistor, and the transistor is further connected to the output impedance matching circuit which comprises a tuning microstrip line and a bandpass filter. The complexity and the area of the impedance matching circuit in the power amplifier are effectively reduced. At the same time, the filtering PA has good frequency selectivity by using the discriminating coupling BPF. Meanwhile the work efficiency and bandwidth of the filtering power amplifier are effectively improved by taking both of the extended continuous mode theory and filter synthesis theory into account. 1. A wide bandpass filtering power amplifier comprising a DC bias circuit , an input impedance matching circuit , a transistor and an output impedance matching circuit , wherein the DC bias circuit is connected to the input impedance matching circuit which is further connected to the transistor , and the transistor is further connected to the output impedance matching circuit which comprising a tuning microstrip line and a bandpass filter , wherein the tuning microstrip line is connected between the transistor and the bandpass filter.2. The wide bandpass filtering power amplifier according to claim 1 , wherein the bandpass filter comprises a first resonator and a second resonator parallelly coupled with each other.3. The wide bandpass filtering power amplifier according to claim 2 , wherein the first resonator comprises a first short end and a first open end claim 2 , and the second resonator comprises a second short end and a second open end claim 2 , wherein the first resonator has a coupling region of ⅔ L1 starting from the first short end and the second resonator has a coupling region ...

Baseband frequency selective magnitude and phase adjustment for wideband doherty power amplifier

A method and transmitter for a Doherty power amplifier are provided. According to one aspect, a radio transmitter includes, for each carrier frequency, a filter, a main path and a peak path. The filter suppresses signals outside the selected frequency band to produce a filter output. The main path is configured to make a first adjustment of a magnitude and phase of the filter output to produce a main path signal. The peak path is configured to make a second adjustment of the magnitude and phase of the filter output to produce a peak path signal, a difference between the first adjustment and the second adjustment being dependent on the carrier frequency. Main path signals for each carrier frequency produce a composite main path signal. Peak path signals for each carrier frequency produce a composite peak path signal.

Dynamic error vector magnitude duty cycle correction

Aspects of this disclosure relate to dynamic error vector magnitude (DEVM) compensation. In one embodiment, an apparatus includes an amplifier, a low pass filter, and a bias circuit. The amplifier, such as a power amplifier, can amplify an input signal. The low pass filter, such as an integrator, can generate a correction signal based at least partly on an indication of a duty cycle of the amplifier. The indication of the duty cycle of the amplifier can be an enable signal for the amplifier, for example. The bias circuit can generate a bias signal based at least partly on the correction signal and provide the bias signal to the amplifier to bias the amplifier.

POWER AMPLIFICATION SYSTEM WITH PROGRAMMABLE LOAD LINE

Disclosed herein are power amplification (PA) systems configured to amplify a signal, such as a radio-frequency signal. The PA system includes a plurality of power amplifiers that are configured to amplify a signal received at a signal input and to output the amplified signal at a signal output. The power amplifiers are configured to receive a supply voltage that is a combination of a battery voltage and an envelope tracking signal. The PA system includes a PA controller configured to control the power amplifiers based at least in part on the battery voltage or a power output of the power amplifiers. The PA controller can be configured to alter impedance matching components of the PA system to reconfigure a load line of the power amplifiers. 1. A power amplification system comprising:a plurality of power amplifiers connected in parallel between a signal input terminal and a signal output terminal, each one of the plurality of power amplifiers including a power amplifier input terminal coupled to the signal input terminal, a power amplifier output terminal coupled to the signal output terminal, and an enable terminal for receiving an enable signal; anda power amplifier controller configured to selectively provide an enable signal to one or more of the plurality of power amplifiers based on an output impedance at the signal output terminal.2. The power amplification system of wherein the plurality of power amplifiers is powered by a supply voltage.3. The power amplification system of wherein the supply voltage is unregulated by a DC-DC converter.4. The power amplification system of wherein the supply voltage is combined with an envelope tracking signal to power the plurality of amplifiers.5. The power amplification system of wherein the supply voltage and envelope tracking signal are combined by an LC combiner.6. The power amplification system of further comprising a blocking inductor disposed between the LC combiner and the signal output terminal.7. The power ...

ACTIVE BIAS CIRCUIT FOR POWER AMPLIFIER, AND MOBILE TERMINAL

An active bias circuit for a power amplifier and a mobile terminal are disclosed. The circuit includes a proportional to absolute temperature (PTAT) current source circuit, a reference voltage circuit, an isolation voltage stabilizing circuit, and a bias voltage circuit. An input end of the PTAT current source circuit is connected to a voltage source (Vbat), and an output end is connected to the reference voltage circuit. The reference voltage circuit generates a reference voltage that is in proportion to a current and a temperature. The isolation voltage stabilizing circuit isolates the reference voltage circuit from the bias voltage circuit, and supplies a stabilized voltage to the bias voltage circuit by using a negative feedback loop. The bias voltage circuit receives the voltage of the isolation voltage stabilizing circuit, and is also connected to the voltage source (Vbat). 1. An active bias circuit for a power amplifier , comprising a proportional to absolute temperature (PTAT) current source circuit , a reference voltage circuit , an isolation voltage stabilizing circuit , and a bias voltage circuit , whereinan input end of the PTAT current source circuit is connected to a voltage source, and an output end is connected to the reference voltage circuit, to generate a current that is in proportion to the voltage source and a temperature;the reference voltage circuit generates a reference voltage that is in proportion to the current and the temperature;the isolation voltage stabilizing circuit isolates the reference voltage circuit from the bias voltage circuit, and supplies a stabilized voltage to the bias voltage circuit by using a negative feedback loop; andthe bias voltage circuit receives the voltage of the isolation voltage stabilizing circuit, and is also connected to the voltage source, to generate a bias voltage of a power-amplifier tube.2. The active bias circuit according to claim 1 , wherein the PTAT current source circuit comprises two groups of ...

ENCAPSULATED SEMICONDUCTOR DEVICE PACKAGE WITH HEATSINK OPENING

Embodiments include packaged semiconductor devices and methods of manufacturing packaged semiconductor devices. A semiconductor die includes a conductive feature coupled to a bottom surface of the die. The conductive feature only partially covers the bottom die surface to define a conductor-less region that spans a portion of the bottom die surface. The die is encapsulated by attaching the encapsulant material to the bottom die surface (e.g., including over the conductor-less region). The encapsulant material includes an opening that exposes the conductive feature. After encapsulating the die, a heatsink is positioned within the opening, and a surface of the heatsink is attached to the conductive feature. Because the heatsink is attached after encapsulating the die, the heatsink sidewalls are not directly bonded to the encapsulant material. 1. A method of manufacturing a packaged semiconductor device , the method comprising the steps of:encapsulating a semiconductor die in encapsulant material, wherein the semiconductor die has a top die surface, a bottom die surface, and a first conductive feature coupled to the bottom die surface, wherein the first conductive feature only partially covers the bottom die surface to define a first conductor-less region that spans a first portion of the bottom die surface, and wherein encapsulating includes attaching encapsulant material to the bottom die surface wherein the encapsulant material includes a first opening that exposes the first conductive feature, and wherein the first opening has encapsulant sidewalls extending from an outer surface of the encapsulant material toward the bottom die surface;after encapsulating the semiconductor die, positioning a heatsink within the first opening, wherein the heatsink has a first heatsink surface, a second heatsink surface, and heatsink sidewalls extending between the first and second heatsink surfaces; andattaching the first heatsink surface to the first conductive feature.2. The ...

POWER AMPLIFIER MODULE

A power amplifier module includes a first amplifier that amplifies an input signal to generate a first amplified signal and outputs the first amplified signal, a second amplifier that amplifies the first amplified signal to generate a second amplified signal and outputs the second amplified signal, and a matching network disposed between an output terminal of the first amplifier and an input terminal of the second amplifier. The first amplifier is provided on a first chip, and the second amplifier is provided on a second chip. The matching network has an impedance transformation characteristic adjustable in accordance with a control signal. 1. A power amplifier module comprising:a first amplifier that amplifies an input signal and outputs a first amplified signal;a second amplifier that amplifies the first amplified signal and outputs a second amplified signal; anda matching network disposed between an output terminal of the first amplifier and an input terminal of the second amplifier, the matching network having an impedance transformation characteristic adjustable in accordance with a control signal, whereinthe first amplifier is provided on a first chip, andthe second amplifier is provided on a second chip.2. The power amplifier module according to claim 1 , whereinthe first chip is a complementary metal-oxide semiconductor chip having a metal-oxide-semiconductor field-effect transistor, andthe second chip is a heterojunction bipolar transistor chip having a heterojunction bipolar transistor.3. The power amplifier module according to claim 1 , further comprising a control circuit provided on the first chip claim 1 , whereinthe control circuit outputs the control signal in accordance with a frequency band of the input signal to adjust the impedance transformation characteristic of the matching network.4. The power amplifier module according to claim 3 , whereinthe matching network comprises a first variable capacitor or a first variable inductor, anda capacitance ...

AMPLIFICATION CIRCUIT

Provided is an amplification circuit that amplifies an input signal and outputs an amplified signal. The amplification circuit includes: an amplification element that outputs the amplified signal from an output terminal thereof; an inductor having one end to which a power supply voltage is supplied and another end that is connected to the output terminal of the amplification element; a variable resistor that is connected in parallel with the inductor; and a resistance value adjusting circuit that adjusts a resistance value of the variable resistor in accordance with the temperature. 1. An amplification circuit that amplifies an input signal and outputs an amplified signal , the amplification circuit comprising:an amplification element that outputs the amplified signal from an output terminal;an inductor having one end to which a power supply voltage is supplied and another end that is connected to the output terminal of the amplification element;a variable resistance element that is connected in parallel with the inductor; anda resistance value adjusting circuit that is configured to adjust a resistance value of the variable resistance element in accordance with a temperature of the amplification circuit.2. The amplification circuit according to claim 1 ,wherein the variable resistance element comprises a first field-effect transistor (FET), andthe resistance value adjusting circuit is configured to adjust a gate voltage of the first FET in accordance with the temperature.3. The amplification circuit according to claim 2 , a first current generating circuit configured to generate a first current,', 'a second FET that is diode connected and through which the first current flows, and', 'a first voltage generating circuit configured to generate a first voltage that changes in accordance with a gate voltage of the second FET, and, 'wherein the resistance value adjusting circuit compriseswherein the resistance value adjusting circuit is configured to adjust the gate ...

Adjustable Gain Power Amplifier, Gain Adjustment Method and Mobile Terminal

An adjustable gain power amplifier, a gain adjustment method and a mobile terminal are disclosed. The adjustable gain power amplifier comprises an input matching circuit, a gain adjustment circuit, a biasing circuit, a main amplification circuit, and an output matching circuit; the input matching circuit is connected between an input end and the gain adjustment circuit; the gain adjustment circuit is connected between the input matching circuit and the input end of the main amplification circuit; the output end of the main amplification circuit is connected to the output matching circuit, a positive power source end thereof is connected to a power supply source, a negative power source end thereof is connected to the biasing circuit; the biasing circuit provides different biasing voltages for the main amplification circuit; and the gain adjustment circuit and the biasing circuit are respectively connected to a gain adjustment control voltage (Vctrl). 1. An adjustable gain power amplifier , comprising an input matching circuit , a gain adjustment circuit , a biasing circuit , a main amplification circuit , and an output matching circuit , wherein ,the input matching circuit is connected between an input end and the gain adjustment circuit;the gain adjustment circuit is connected between the input matching circuit and an input end of the main amplification circuit;an output end of the main amplification circuit is connected to the output matching circuit; a positive power source end thereof is connected to a power supply source and a negative power source end thereof is connected to the biasing circuit;the biasing circuit provides different biasing voltages for the main amplification circuit; andthe gain adjustment circuit and the biasing circuit are respectively connected to a gain adjustment control voltage.2. The adjustable gain power amplifier according to claim 1 , wherein the gain adjustment circuit comprises at least one stage of gain adjustment branch;the gain ...

Broadcast Receiving Device of a Motor Vehicle

A broadcast receiving device for a motor vehicle includes at least one antenna having a given antenna impedance, an antenna amplifier having a given amplifier impedance and a matching circuit which is configured to adapt the antenna impedance to the amplifier impedance. The broadcast receiving device is characterized in that the matching circuit is arranged outside of the amplifier core of the antenna amplifier. 113.-. (canceled)14. A broadcast receiving device for a motor vehicle , comprising:at least one antenna having a given antenna impedance;an antenna amplifier having an amplifier core and a given amplifier impedance; anda matching circuit which is configured to adapt the antenna impedance to the amplifier impedance, whereinthe matching circuit is arranged externally to the amplifier core of the antenna amplifier.15. The broadcast receiving device according to claim 14 , whereinthe amplifier core is arranged in a housing.16. The broadcast receiving device according to claim 14 , whereinthe matching circuit is an integral constituent of a signal transmission structure, which signal transmission structure connects the antenna to the antenna amplifier or to the amplifier core.17. The broadcast receiving device according to claim 14 , whereinthe matching circuit is arranged on or in a carrier, on or in which the antenna is provided.18. The broadcast receiving device according to claim 17 , whereincomponents of the matching circuit are printed onto the carrier using a conductive material of a specific conductivity.19. The broadcast receiving device according to claim 17 , whereincomponents of the matching circuit are produced from a conductive foil by a subtractive process, wherein the foil is flush-bonded to the carrier.20. The broadcast receiving device according to claim 17 , whereincomponents of the matching circuit are applied to the carrier in the form of discrete, soldered, components.21. The broadcast receiving device according to claim 14 , ...

AMPLIFIER DEVICE FOR AN ANTENNA-LIKE MRI TRANSDUCER AND CORRESPONDING MRI APPARATUS

The invention relates to an amplifier device () adapted for an antenna-like transducer for MRI applications, especially for an RF coil, wherein the amplifier device () comprises at least one amplifier channel () including: 2. An amplifier device as claimed in claim 1 , wherein the switches are configured to effect an even number of segments coupled to the distal end of the adjusted line length between the amplifier and the load and switchable connect said even number of segments to ground provided the even number of segments form an odd number of pairs of segments.3. The amplifier device according to claim 1 , wherein the impedance matching circuit comprises a series of line segments of the given characteristic impedance Zcoupled by switches to establish the electric line of adjustable line length.4. The amplifier device according to claim 1 , further comprising a software defined radio unit or other control unit providing a digital interface claim 1 , which control unit measures the loading condition from the amplifier unit and controls the matching circuit.5. The amplifier device according to claim 4 , wherein the control unit directly controls the switches of the impedance matching circuit.6. The amplifier device according to claim 1 , wherein the impedance matching circuit is operable in a high magnetic Bfield of a corresponding MRI apparatus.7. The amplifier device according to claim 1 , further comprising a printed circuit board claim 1 , wherein the RF amplifier unit and the matching circuit are arranged on said printed circuit board.8. The amplifier device according to one claim 1 , wherein the impedance matching circuit further comprises at least one capacitive component of adjustable capacity and/or at least one inductive component of adjustable inductance.9. The amplifier device according to claim 1 , wherein the at least one amplifier channel includes a further matching circuit for impedance matching.10. The amplifier device according to claim 9 , ...

Power amplifier harmonic matching network

An output network connected to an output of a nonlinear unmatched power amplifier that provides an amplified voltage signal at a fundamental frequency. The output network includes multiple acoustic resonators configured to match multiple harmonic frequencies of the amplified voltage signal to one of substantially zero impedance, appearing as a short, or substantially infinite impedance, appearing as an open, resulting in zero voltage or zero current, respectively, to avoid power distribution at the higher harmonic frequencies. Each higher harmonic frequency is higher than a first harmonic frequency of the multiple harmonic frequencies, which is a fundamental frequency.

DYNAMIC ERROR VECTOR MAGNITUDE COMPENSATION

Aspects of this disclosure relate to compensating for dynamic error vector magnitude. A compensation circuit can generate a compensation signal based at least partly on an amount of time that an amplifier, such as a power amplifier, is turned off between successive transmission bursts of the amplifier. For example, the compensation circuit can charge a capacitor based at least partly on an amount of time that the amplifier is turned off between successive transmission bursts and generate the compensation signal based at least partly on an amount of charge stored on the capacitor. A bias circuit can receive the compensation signal, generate a bias signal based at least partly on the compensation signal, and provide the bias signal to the amplifier to bias the amplifier. 1. (canceled)2. An amplifier system comprising:a radio frequency amplifier including an amplifying transistor, the radio frequency amplifier configured to receive a bias signal and to amplify a radio frequency signal;a compensation circuit configured to generate a compensation signal based at least partly on an amount of time between successive bursts of the radio frequency amplifier; anda bias circuit including a reference transistor, the bias circuit configured to generate the bias signal based at least partly on the compensation signal so as to compensate for a change in an effective ratio between the reference transistor and the amplifying transistor due to a change in temperature difference between the reference transistor and the amplifying transistor.3. The amplifier system of wherein the bias signal increases gain of the amplifying transistor at a beginning of a burst.4. The amplifier system of wherein the compensation circuit is configured to generate the compensation signal such that the compensation signal has a first magnitude associated with a first duty cycle of the radio frequency amplifier and a second magnitude associated with a second duty cycle of the radio frequency amplifier claim ...

REDUCING POWER AMPLIFIER GAIN DRIFT DURING A DATA BURST

A bias circuit provides additional bias current for power amplifiers during data bursts to compensate for the gain droop caused by a rise in the power amplifier temperature during the data burst. A bias circuit includes a difference amplifier and switches coupled to the difference amplifier. The switches operate the bias circuit in a first mode when a transmit data burst is detected and operate the bias circuit in a second mode after the bias circuit has operated in the first mode for a predetermined period of time. In the first mode, the bias circuit charges a storage capacitor and sets an output current to zero. In the second mode, the bias circuit outputs the output current that increases above the initial value of zero as the PA warms up, where the excursion of this increase of current is determined by a register. The switches disable the bias circuit when the transmit data burst ends. 1. (canceled)2. A power amplifier system , comprising:a power amplifier configured to amplify a radio frequency signal; anda sampling circuit configured to charge a storage capacitor for a time period when a data burst is detected and to provide an indication of a change in temperature of the power amplifier when the time period has elapsed.3. The power amplifier system of further comprising a temperature sensor configured to provide an indication of temperature of the power amplifier to the sampling circuit.4. The power amplifier system of further comprising a bias circuit configured to generate a bias compensation signal based at least in part on the indication of the change in temperature of the power amplifier.5. The power amplifier system of wherein an output current of the bias circuit increases as the temperature of the power amplifier increases during the data burst.6. The power amplifier system of wherein the bias compensation signal compensates for a change in gain of the power amplifier during the data burst.7. The power amplifier system of wherein the data burst is ...

DUAL-MODE WIRELESS TRANSCEIVER DEVICE

A wireless transceiver device includes an operation amplification circuit, a transmitter circuit, a receiver circuit, and a transceiver control circuit. The operation amplification circuit, according to a rate parameter and a filtering parameter, filters and amplifies an input signal and outputs a processed signal. The transmitter circuit selectively uses a first ratio or second ratio as the amplification parameter, converts an input signal into an analog signal, inputs the analog signal into the operation amplification circuit, mixes the processed signal with a local oscillating frequency and then output an output signal. The receiver circuit mixes an external signal with another local oscillating frequency, inputs the mixed signal into the operation amplification circuit, and converts the processed signal into a digital signal. The transceiver control circuit selectively and electrically connects the operation amplification circuit with the transmitter circuit or the receiver circuit. 1. A dual-mode wireless transceiver device , comprising:a digital-to-analog conversion circuit, adapted to be operated in a first mode and a second mode, wherein in the first mode, the digital-to-analog conversion circuit is configured to convert a first input signal into an input analog signal; and in the second mode, the digital-to-analog conversion circuit is configured to convert a second input signal into the input analog signal;a second mixer circuit, adapted to be operated in a third mode and a fourth mode, wherein in the third mode, the second mixer circuit is configured to mix a first external signal and a third local frequency to output an intermediate-frequency signal; and in the fourth mode, the second mixer circuit is configured to mix a second external signal and a fourth local frequency to output the intermediate-frequency signal;a filter amplifier circuit, adapted to be operated in the first, the second, the third, and the fourth mode, wherein in the first and the ...

COMBINED IMPEDANCE MATCHING AND RF FILTER CIRCUIT

What is specified is a combined impedance matching and RF filter circuit having improved impedance matching in conjunction with good frequency-tunability of the filter circuit. The circuit comprises a reactance elimination circuit for reducing the reactance and a tunable RF filter circuit, which is frequency-tunable and can carry out a resistance matching. 2. The circuit according to claim 1 , wherein the tunable RF filter circuit comprises a resistance matching circuit on the input or output side or the input and output side.3. The circuit according to claim 1 , wherein the tunable RF filter circuit comprises at least one of tunable capacitive or inductive elements for the frequency tuning.4. The circuit according to claim 1 , wherein the tunable RF filter circuit is constructed from passive circuit elements.5. The circuit according to claim 1 , wherein the reactance elimination circuit comprises at least one of capacitive or inductive elements.6. The circuit according to claim 5 , wherein the reactance elimination circuit comprises at least one of tunable capacitive or inductive elements for reducing the absolute value of the reactance.7. The circuit according to claim 1 , wherein the tunable RF filter circuit comprises a filter corehaving a first impedance element in a first signal route andhaving electromagnetically coupled impedance elements interconnected in series in a second signal route interconnected in parallel with the first signal route.8. The circuit according to claim 1 , which is interconnected in a receiving or transmitting path of a mobile communication device.9. The circuit according to claim 1 , which is interconnected together with a further circuit according to in a mobile communication device claim 1 , wherein the two tunable RF filter circuits together form a duplexer.10. The circuit according to claim 1 , comprising two reactance elimination circuits and a tunable RF filter circuit interconnected between the two reactance elimination ...

Mismatch Detection using Replica Circuit

An apparatus for detecting difference in operating characteristics of a main circuit by using a replica circuit is presented. In one exemplary case, a sensed difference in operating characteristics of the two circuits is used to drive a tuning control loop to minimize the sensed difference. In another exemplary case, several replica circuits of the main circuit are used, where each is isolated from one or more operating variables that affect the operating characteristic of the main circuit. Each replica circuit can be used for sensing a different operating characteristic, or, two replica circuits can be combined to sense a same operating characteristic. 1. (canceled)2. A method for operating a first radio frequency (RF) circuit path comprising a first active circuit , the method:providing a second RF circuit path comprising a second active circuit that is a reduced size replica of the first active circuit;coupling one or more sensing points of the first RF circuit path to a sensing circuit;coupling one or more sensing points of the second RF circuit path to the sensing circuit;based on the coupling and the coupling, sensing a difference between one or more operating characteristics of the first RF circuit path, sensed at the one or more sensing points of the first RF circuit path, and one or more reference operating characteristics of the second RF circuit path, sensed at the one or more sensing points of the second RF circuit path; andcontrolling operation of the first RF circuit path based on the sensing.3. The method according to claim 2 , wherein:the one or more operating characteristics of the first RF circuit path are affected by a set of operating variables, andthe second RF circuit path is configured so that one or more reference operating characteristics of the second RF circuit path are substantially isolated from a subset of the operating variables.4. The method according to claim 3 , wherein the set of operating variables comprises variables selected ...

BROADBAND, HIGH-EFFICIENCY, NON-MODULATING POWER AMPLIFIER ARCHITECTURE

Apparatus and methods for a no-load-modulation power amplifier are described. No-load-modulation power amplifiers can comprise multiple amplifiers connected in parallel to amplify a signal that has been divided into parallel circuit branches. One of the amplifiers can operate as a main amplifier in a first amplification class and the remaining amplifiers can operate as peaking amplifiers in a second amplification class. The main amplifier can see essentially no modulation of its load between the power amplifier's fully-on and fully backed-off states. The power amplifiers can operate in symmetric and asymmetric modes. Improvements in bandwidth and drain efficiency over conventional Doherty amplifiers are obtained. Further improvements can be obtained by combining signals from the amplifiers with hybrid couplers. 1. A power amplifier comprising:a main amplifier connected in parallel with a first peaking amplifier in a first circuit branch;a second peaking amplifier connected in parallel with a third peaking amplifier in a second circuit branch that is in parallel with the first circuit branch; anda first impedance inverter in the first circuit branch and a second impedance inverter in the second circuit branch, wherein:current ratios for the peaking amplifiers with respect to the main amplifier set a load impedance seen by the main amplifier to approximately a same value when the peaking amplifiers are fully amplifying received signals and when the peaking amplifiers are not amplifying received signals.2. The power amplifier of claim 1 , further comprising:an output port of the power amplifier configured to connect to a load having an impedance value R, wherein:the first impedance inverter has a characteristic impedance value of R±0.05R; andthe second impedance inverter has a characteristic impedance value of R±0.05R.3. The power amplifier of claim 1 , wherein a load impedance seen by the main amplifier is approximately R when the peaking amplifiers are fully ...