Verfahren zur Minimierung einer Impedanzfehlanpassung zwischen einer Übertragungsleitung und einer an diese angekoppelten Ausgangstreiber-Schaltungsanordnung sowie Ausgangstreiber-Schaltungsanordnung zu dessen Durchführung

Ausgangsschaltung einer Halbleitervorrichtung

Eine Ausgangsschaltung eines Halbleiters hat Einheitspuffer, jeder Einheitspuffer hat Transistoren und Widerstände, die zwischen einen Stromquellenanschluss VDDQ und einen Ausgangsanschluss DQ geschaltet ist, und Transistoren und Widerstände, die zwiusgangsanschluss DQ geschaltet sind. Die Ein-Widerstandswerte der in den Einheitspuffern enthaltenen Transistoren sind einander im Wesentlichen gleich und die Widerstandswerte der in den Einheitspuffern enthaltenen Widerstände sind zueinander unterschiedlich. Eine Abweichung der Impedanzen als Eigenschaft eines Stromquellenwiderstands kann basierend auf einer Differenz zwischen den Widerstandswerten der Widerstände ausgeglichen werden.

Performance optimization through topology dependent compensation

A method and apparatus for compensating system components based on system topology. The present invention provides a method and apparatus for performance optimization through topology dependent compensation. In one embodiment, one or more components of a computer system are coupled to a bus (210) via self-compensated buffer(s) (220). The self-compensated buffer(s) (220) allow operating characteristics to be set via external signals (650, 651, 655, 656, 660, 661, 665, 666, 670, 671, 675, 676) such as voltage levels. System components have compensation units (230) that receive external signals (650, 651, 655, 656, 660, 661, 665, 666, 670, 671, 675, 676) from a configuration unit (240) to configure the operating characteristics of the self-compensated buffer(s) (220). In this manner a system designer may set operating characteristics for various system components based on the topology of the specific system rather than designing for a worst-case scenario.

A logic circuit capable of adjusting the switching threshold level

An adaptive threshold logic circuit 9 is provided in which the switching threshold levels of the logic circuit are automatically changed to accommodate variations in the level of applied data signals to the switching circuit. A detector stage 11 detects the voltage level of the incoming data signals and selectively adjusts the threshold level of a threshold adaptor stage 13 in accordance with the output of the detector stage 11. The threshold adaptor stage is essentially a CMOS inverter having various switching paths turned on or off in accordance with the output of the detector stage 11. Dependent claims are included for a memory device and a processor system incorporating the adaptive threshold logic circuit 9.

Methods and devices for matching transmission linecharacteristics using stacked metal oxide semicon ductor (mos) transistors

Methods and devices for matching transmission linecharacteristics using stacked metal oxide semicon ductor (mos) transistors

Methods and devices for matching transmission linecharacteristics using stacked metal oxide semicon ductor (mos) transistors

SYSTEM AND PROCEDURE FOR ACTIVE LEITUNGSABSCHLUSS

PROGRAMMABLE BUFFER CIRCUIT

Superconducting tunable coupler

A superconducting system is provided that includes a coplanar superconducting circuit. The coplanar superconducting circuit includes a first ground plane region, a second ground plane region electrically isolated from the first ground plane region by portions of the coplanar superconducting circuit, and a tunable coupler having a first port and a second port. The tunable coupler comprises a variable inductance coupling element coupled between the first port and the second port, a first termination inductor having a first end coupled between a first end of the variable inductance element and a second end coupled to the first ground plane region, and a second termination inductor having a first end coupled between a second end of the variable inductance element and a second end coupled to the second ground plane region.

SYSTEM AND METHOD FOR TRANSMISSION-LINE TERMINATION BY SIGNAL CANCELLATION, AND APPLICATIONS THEREOF

An active terminating device (30) for an electrical transmission line with optional line-receiving and line-driving capabilities is disclosed. The basic device is a two-terminal unit, denoted as a Signal Canceling Unit (SCU), which senses the signal available at its terminals (34a, 34b), and applies negative feedback in order to cancel and absorb the signal. When applied to the end of a transmission line (15a, 15b) as part of wired communication network, the SCU functions as a terminator. When connected in the middle of such wired transmission line, the SCU splits the transmission line into two separate and isolated segments. In such a configuration, the SCU can be used to isolate a portion of a network from signal degradation due to noise or bridge-tap. Furthermore, the two isolated segments may each employ independent communications, such that no interference exists between the segments. In another embodiment, line receiver functionality is integrated into the SCU, designated as a Signal ...

ADJUSTABLE IMPEDANCE DRIVER NETWORK

ADJUSTABLE IMPEDANCE DRIVER NETWORK A variable impedance driver network comprises a plurality of transmission gates connected in parallel between a voltage source and an output. Each transmission gate has a predetermined nominal impedance and by turning on selective gates the overall impedance of the network may be adjusted to match that required at the output.

AUTOMATIC SYSTEM FOR ADJUSTING THE OUTPUT IMPEDANCE OF FAST CMOS DRIVERS

Buffer with compensating drive strength

Signal sensing circuit

A signal sensing circuit converts a received current input into a voltage output and provides the voltage output to an analog-to-digital converter (ADC) to generate a digital output signal. The voltage output is associated with a circuit having a first reference impedance, and a reference voltage of the ADC is associated with a circuit having a second reference impedance, wherein the circuit having the first reference impedance and the circuit having the second reference impedance are formed by the same material, so that the ratio between the changes in the current input and the changes in the value of the digital output signal is a constant.

Method and device for impedance matching for a transmitter and/or receiver, integrated circuit and transmission system utilizing same [...].

BIDIRECTIONAL CONNECTION CMOS BIPOINT ADAPTEE IN RECEPTION AND EMISSION

INPUT PORT CONFIGURABLE COMPUTER ELECTRONIC VEHICLE

ACTIVE TERMINATING DEVICE WITH OPTIONAL LINE-RECEIVING AND LINE-DRIVING CAPABILITIES

programmable impedance Control circuit in semiconductor device and impedance range shifting method therefor

On Die Termination circuit improving performance in high frequency

IMPEDANCE REGULATING CIRCUIT AND METHOD THEREOF, ESPECIALLY COMPRISING FIRST AND SECOND OUTPUT BUFFERS WITH VARIABLE IMPEDANCE

PURPOSE: An impedance regulating circuit and a method thereof are provided to regulate impedance of an output buffer of a DDR2 memory from a memory controller easily, by comprising an OCD(Off-Chip Driver) impedance regulation function. CONSTITUTION: A semiconductor device comprises an output buffer outputting a differential signal from an output pair. The impedance of the output buffer is set variably. A circuit disconnects two ports receiving the differential signal while the impedance of the semiconductor device is regulated. A comparator(12) compares the voltage of a shorted point with a reference voltage. A control circuit performs to change the impedance of the output buffer on the basis of the comparison result. © KIPO 2007 ...

METHOD AND APPARATUS FOR OPERATING A MEMORY DEVICE TO PERFORM A CLOCK ENABLE OPERATION USING A CKE PIN

PURPOSE: A method and apparatus for operating a memory device are provided to issue a command according to the level of a control signal inputted through a control pin. CONSTITUTION: ODT signals(ODT0,ODT2,ODT3,ODT3) are received through an ODT pin. A command is issued or an ODT circuit is controlled. The resistance of the final resistor in the ODT circuit is changed or the ODT circuit is turned on or off. The command is issued in response to the ODT signal when the level of the ODT signal is toggled at each edge of a clock signal. COPYRIGHT KIPO 2013 ...

OUTPUT BUFFER CIRCUIT

PURPOSE: To provide an output buffer circuit that is operated at a low voltage, has a pre-emphasis function with a small propagation delay time suitable for a high-speed operation, and to provide its control system. CONSTITUTION: A 1st buffer B1 consists of a 1st P-channel field effect transistor P1, whose source electrode is connected to a high-level power supply VDD and of a 1st N-channel field effect transistor N1 whose source electrode is connected to a low-level power supply VSS, and a 2nd buffer B2 consists of a 2nd P-channel field effect transistor P2, whose source electrode is connected to the high level power supply VDD and of a 2nd N-channel field effect transistor N2, whose source electrode is connected to the low-level power supply VSS. The drive capability of the P-channel field effect transistor P1 is set higher than the drive capability of the N-channel field effect transistor N2, and the drive capability of the N-channel field effect transistor N1 is set higher than the ...

SEMICONDUCTOR DEVICE, CAPABLE OF IMPROVING A DATA OUTPUT PROPERTY AND SUFFICIENTLY SECURING THE SIZE OF A DATA WINDOW AND A TIMING MARGIN

PURPOSE: A semiconductor device is provided to sufficiently secure the size of a data window and a timing margin by securing the full swing of a pull-up driving signal and a pull-down driving signal. CONSTITUTION: A pre-drive part(41) generates a pull-up driving signal and a pull-down driving signal corresponding to an output data signal and transmits the signals to a first and a second transmission line. A main drive part(42) drives output data in response to the pull-up drive signal and the pull-down drive signal, which are transmitted through the first and the second transmission line. A termination part terminates the first and the second transmission line after receiving termination power. COPYRIGHT KIPO 2011 ...

Serializing transmitter

Buffer for driving and receiving operation and bi-direction buffer

SWITCHING APPARATUS

A switching apparatus for connecting between a common terminal and an individual terminal selected from a plurality of individual terminals. The apparatus comprises a plurality of common-terminal-side switches which are provided correspondingly to the plurality of individual terminals and each disposed between the common terminal and the corresponding individual terminal; a plurality of ground-side switches which are provided correspondingly to the plurality of individual terminals and each disposed between the ground and a wiring between the corresponding individual terminal and the common-terminal-side switches; and a controlling section which, when terminating the common terminal, turns on at least one ground-side switch and controls a resistance value of at least one common terminal-side switch connected to the ground-side switch that has been turned on, thereby controlling the resistance between the common terminal and the ground to be a termination resistance.

COMMUNICATION INTERFACE WITH TERMINATED TRANSMISSION LINES

Structures and methods for providing more reliable communications between circuits within a given system and more flexible apparatus for implementation. In particular, an illustrative embodiment of the present invention includes a driver/receiver circuit that comprises a channel connection, a receiver and a driver. The receiver has a receiver input and a receiver output, and the receiver input is connected to the channel connection. The driver has a driver input and a driver output. The driver output is connected to the receiver input and to the channel connection and the driver provides a transmission line matching impedance to the channel connection when the driver is placed in an active state.

CONTROLLING ON-DIE TERMINATION IN A NONVOLATILE MEMORY

A memory controller transmits a plurality of control values to a non-volatile memory device together with one or more programming commands. The plurality of control values include (i) a first control value that specifies a first termination resistance to be applied to an I/O node of the non-volatile memory device during an interval in which a first data signal transmitted on a bidirectional signaling line coupled to the I/O node is to be received within the non-volatile memory device and (ii) a second control value that specifies a second termination resistance to be applied to the I/O node during an interval in which a second data signal is transmitted on the bidirectional signaling line by another non-volatile memory device.

Semiconductor device

The present invention is directed to adjust a resistance value of an output buffer on the basis of a resistance value of an external resistor. A potential according to a resistance ratio between an external resistor and each of resistance adjusters is detected by a code generator. In the code generator, code signals for adjusting resistance are adjusted in accordance with the detection result. The resistance value of each of the resistance adjusters is adjusted to an external resistor. Further, by code signals with which the resistance value of each of the resistance adjusters is adjusted to the resistance value of the external resistor, the resistance of the resistance value of an output buffer is adjusted.

Configurable On-Die Termination

Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.

Semiconductor device with bus terminating function

The distance between a drain contact and gate electrode in a terminating transistor, which couples a termination resistor connected to an output terminal to a power source node, is set shorter than in an output transistor, which drives an output node in accordance with an internal signal. The area of the terminating circuit is reduced while the reliability against the surge is maintained. Thus, an output circuit containing the terminating circuit that occupies a small area and is capable of transmitting a signal/data at high speed is provided.

Impedance calibration device for semiconductor device

An impedance calibration device for a semiconductor device includes a process sensor that detects a process condition for the semiconductor device and outputs a process signal, a temperature monitoring sensor that detects a temperature of the semiconductor device and outputs a temperature signal, a converter that converts the process signal and the temperature signal into a digital signal, and a code generation circuit that generates and outputs a driving code for controlling a level of a voltage at an output node according to the digital signal of the converter and a data signal. The impedance calibration device further includes an output driver that pulls up or pulls down the voltage at the output node according to the driving code.

Semiconductor device including buffer circuit

A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals.

Method and apparatus for output driver calibration, and memory devices and system embodying same

A method, system, and output driver calibration circuit determines calibration values for configuring adjustable impedance output drivers. The calibration circuit includes a pull-up calibration circuit configured to generate an averaged pull-up count signal for calibrating p-channel devices in the output driver with the averaged pull-up count signal being an average of a plurality of pull-up count signals. The calibration circuit further includes a pull-down calibration circuit configured to generate an averaged pull-down count signal for calibrating n-channel devices in the output driver with the averaged pull-down count signal being an average of a plurality of pull-down count signals.

Termination circuit

A termination circuit for terminating a transmission line comprises a resistance unit which is formed by connecting a P-channel type MOS transistor and an N-channel type MOS transistor in parallel, and Thevenin termination is formed by providing this resistance unit between the transmission line and a power supply line and between the transmission line and a ground line.

Method and apparatus for compensated slew rate control of line termination

In one embodiment, a high speed bi-directional driver/receiver is provided. When a first component driving data onto a bi-directional bus switches to receiving data from the bus, a second component drives the last logic value received back onto the bus. The first component then disengages its driver circuit and engages a center-tapped line termination circuit, but in order to avoid glitches, the line termination is engaged at a controlled slew rate. The controlled slew rate is generated through a combination of variably sized transistors connected with a voltage source and a charge accumulation node. By controlling which transistors are turned on, the rate at which the node accumulates a charge can be adjusted. When the termination circuit is to be activated, the charge, which is accumulating at a controlled rate, is connected to the gate of the termination transistors, thereby controlling the change in impedance of the termination resistors to avoid voltage glitches on the transmission ...

Termination circuit

In order to prevent malfunction due to fluctuations in signal level, a terminating resistor circuit includes terminating resistors the connections whereof to an input/output terminal are capable of being turned on and off, whereby a Thevenin termination is formed. A control circuit exercises control so as to temporally stagger on/off timings of respective ones of the terminating resistors.

Semiconductor device with impedance calibration function

Disclosed is a semiconductor device comprising a reference circuit for receiving a plurality of impedance control signals and generating a reference voltage, a transmission driving circuit for receiving the impedance control signals and a pair of differential input signals and outputting a pair of differential output signals to an external cable, and an impedance control signal generating circuit for receiving a difference signal of the differential output signals and the reference voltage and generating the impedance control signals.

Method for reducing leakage current and increasing drive current in a metal-oxide semiconductor (MOS) transistor

An apparatus and method of manufacture for metal-oxide semiconductor (MOS) transistors is disclosed. Devices in accordance with the invention are operable at voltages below 2V. The devices are area efficient, have improved drive strength, and have reduced leakage current. A dynamic threshold voltage control scheme comprised of a forward biased diode in parallel with a capacitor is used, implemented without changing the existing MOS technology process. This scheme controls the threshold voltage of each transistor. In the OFF state, the magnitude of the threshold voltage of the transistor increases, keeping the transistor leakage to a minimum. In the ON state, the magnitude of the threshold voltage decreases, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The use of reverse biasing of the well, in conjunction with the above construct to further decrease leakage in a MOS transistor, is also shown ...

Semiconductor device with bus terminating function

The distance between a drain contact and gate electrode in a terminating transistor, which couples a termination resistor connected to an output terminal to a power source node, is set shorter than in an output transistor, which drives an output node in accordance with an internal signal. The area of the terminating circuit is reduced while the reliability against the surge is maintained. Thus, an output circuit containing the terminating circuit that occupies a small area and is capable of transmitting a signal/data at high speed is provided.

Clock control signal generation using transition of the control signal

A integrated circuit includes a clock control signal generation circuit configured to generate a clock control signal using transition of a control signal, a clock control unit configured to activate a control clock in an activated period of the clock control signal, and to deactivate the control clock in a deactivated period of the clock control signal, and a control circuit configured to operate in response to the control signal and in synchronization with the control clock.

Compensated impedance calibration circuit

Aspects of the invention provide for compensating impedance calibration circuits. In one embodiment, a compensated impedance calibration circuit, includes: a variable resistor network including a tunable resistor and a fixed resistor; and an external resistance network including a target external precision resistor and a parasitic distribution resistance; wherein a resistance of the variable resistor network is proportional to a resistance of the external resistance network, such that a ratio of an output voltage of the variable resistor network to a power supply voltage is constant.

Calibration methods and circuits for optimized on-die termination

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

DATA TRANSMISSION DEVICE, AND SEMICONDUCTOR DEVICE AND SYSTEM INCLUDING THE SAME

A data transmission device may include a calibration circuit and an output driver. The calibration circuit may generate a pull-up calibration voltage and a pull-down calibration voltage. The resistance value of the output driver may be changed based on the pull-up calibration voltage and the pull-down calibration voltage. 1. A data transmission device comprising:a calibration circuit configured to perform a calibration operation, and generate a pull-up calibration voltage and a pull-down calibration voltage; andan output driver configured to receive the pull-up calibration voltage and the pull-down calibration voltage, and to drive a data transmission line based on the pull-up calibration voltage, the pull-down calibration voltage, and data.2. The data transmission device according to claim 1 , wherein the pull-up calibration voltage and the pull-down calibration voltage are analog voltages.3. The data transmission device according to claim 1 , wherein the calibration circuit comprises:a calibration code generator coupled to an external reference resistor, and configured to generate a pull-up calibration code and a pull-down calibration code; anda calibration voltage generator configured to generate the pull-up calibration voltage based on the pull-up calibration code, and generate the pull-down calibration voltage based on the pull-down calibration code.4. The data transmission device according to claim 1 , wherein:the pull-up calibration voltage and the pull-down calibration voltage have voltage levels between a high voltage and a ground voltage; andthe high voltage has a level higher than a power supply voltage of the output driver.5. The data transmission device according to claim 1 , wherein the output driver comprises:a data driver configured to drive the data transmission line based on the data;a pull-up resistor coupled between the power supply voltage and the data driver, and having a resistance value that is changed based on the pull-up calibration voltage ...

Ring based impedance control of an output driver

In one embodiment, there is a method that can include utilizing a ring oscillator module to determine a process corner of an integrated circuit as fabricated that includes the ring oscillator module. The impedance of an output driver of the integrated circuit can be altered based on the process corner of the integrated circuit as fabricated.

Transmission-end impedance matching circuit

A transmission-end impedance matching circuit operates according to a signal of an overvoltage signal source and includes a first level shifter, a voltage generating circuit, and an impedance matching circuit. The first level shifter generates a first conversion voltage according to a source signal and operates between a first high voltage and a ground voltage. The voltage generating circuit generates a second high voltage according to the first conversion voltage, the first high voltage, and a medium voltage. The impedance matching circuit includes a second level shifter, a transistor, and two resistors. The second level shifter generates a gate voltage according to the second high voltage, a low voltage, and an input signal. The transistor is turned on/off according to the gate voltage and has a withstand voltage lower than the first high voltage. Each of the two resistors is coupled between the transistor and a differential signal transmission end.

LVDS DRIVER FOR BACK-PLANE APPLICATION

PROBLEM TO BE SOLVED: To suppress variation in output voltage by holding a desired offset voltage constant by providing a reference voltage generating circuit and a current adjusting circuit and adjusting a supply current by comparing the output voltage with a reference voltage signal. SOLUTION: When an input signal IN varies from a low to a high stage, transistors(TR) N21 and N24 turn on and a driving current I2 is supplied from a TR P2 through a resistance load RL in a direction A to raise the voltage of a node NP2. When the reference voltage from a simulating circuit MC is compared and exceeded, the output of an OPAMP1 increases to raise the gate- source voltage of the P2 and the current I2 is reduced to continue the operation until the voltage becomes as high as the reference voltage. Similarly, when a low output voltage exceeds a low reference voltage, the output of the OPAMP 1 decreases and the current from a TR N1 is reduced. Consequently, even when a resistive load RL varies, it ...

Output driver circuitry with min. transition impedance variations - has two pulse expanders, first one in high pass signal release, and second one in low pass signal release

The output driver circuitry contains a control circuit (2), generating a high pass release signal and a low pass release signal. To the control circuit is coupled a high pass lateral transmission gate (8) via a high pass release path. Via the low pass release signal path a low pass transmission gate (9) is coupled to the control circuit. A first variable pulse expander (4) is incorporated in the high pass release signal path, while a second variable pulse expander (6) is incorporated in the low pass release signal path. Pref. the two expanders have each a NOR gate with two inputs and a variable delay element. ADVANTAGE - The logic state transition uses two transmit gates with matching active impedances.

Leistungsoptimierung durch topologieabhängige Kompensation

Sharing common calibration components

An external component, such as resistor R1, is periodically connected, by a multiplexer 414 to a plurality of circuits PVT1 - PVT8 on an integrated circuit. Circuits PVT1 - PVT8 may be process-voltage-temperature (PVT) circuits (fig 2a) that adjust an output impedance to be approximately the same as that of a resistor R1. Hence individual external calibration components (fig 2, R1-R8) are not required. The integrated circuit may comprise P-type and N-type PVT circuits and a further multiplexer 416 may connect a second terminal of the external component R1 to either of VDD or ground, as appropriate.

Output buffer circuit for driving a transmission line

Current mode logic circuit

Apparatus and method for calibrating an adjustable impedance of a semiconductor device

Low swing amplitude voltage mode driver

PROCESS AND DEVICE FOR THE ORDERING OF DRIFT

Procédé de commande de dérive comprenant la prévision (310) d'un circuit de sortie possédant une pluralité d'impédances variables pouvant être sélectionnées. Chaque impédance variable pouvant être sélectionnée est couplée, de façon successive, (320) à une prise du circuit de sortie en réponse au début d'une transition de premier signal pour faire varier, de façon monotonique, une impédance de source de circuit de sortie sur toute la transition du signal.

임피던스 조절회로 및 이를 포함하는 반도체 장치

... 본 발명의 실시예에 따른 임피던스 조절회로는, 외부저항이 연결되는 제1노드의 전압을 이용해 풀업 임피던스 제어코드를 생성하는 풀업 코드생성부; 상기 풀업 임피던스 제어코드에 의해 결정되는 임피던스 값을 가지고 상기 제1노드를 풀업 구동하는 풀업 임피던스부; 각각이 상기 풀업 임피던스 제어코드에 의해 결정되는 임피던스 값을 가지며, 제1 내지 제M선택신호(단, M은 자연수) 각각에 응답해 활성화/비활성화되고, 제2노드를 풀업 구동하는 제1 내지 제M더미 임피던스부; 상기 제2노드의 전압을 이용해 풀다운 임피던스 제어코드를 생성하는 풀다운 코드생성부; 및 각각이 상기 풀다운 임피던스 제어코드에 의해 결정되는 임피던스 값을 가지며, 상기 제1 내지 제M선택신호 각각에 응답해 활성화/비활성화되고, 상기 제2노드를 풀다운 구동하는 제1 내지 제M풀다운 임피던스부를 포함할 수 있다.

INTEGRATED CIRCUIT AND OPERATION METHOD FOR THE SAME

SIGNAL OUTPUTTING APPARATUS, COMMUNICATION SYSTEM, SIGNAL OUTPUTTING METHOD, AND COMMUNICATION METHOD

The objective of the invention is to increase the signal transmission amount per unit time without increasing the clock rate and the number of signal lines. A control unit (22) causes the output impedance of an output unit (20) to match the characteristic impedance of a signal line (26) during a signal level non-transition time period. If the second bit of a signal to be processed is a first value, the control unit (22) causes the output impedance to match the characteristic impedance during a signal level transition time period as well. If the second bit is a second value, the control unit (22) causes the output impedance not to match the characteristic impedance during the signal level transition time period.

On-die termination circuit and driving method thereof

An on-die termination circuit is capable of increasing a resolution without enlargement of a chip or a layout size. The on-die termination circuit includes a control means, a termination resistance supply means, a code signal generating means. The control means sequentially generates a plurality of control signals in a response to a driving signal. The termination resistance supply means supplies a termination resistance in response to a coarse code signal having a plurality of bits and a fine code signal having a plurality of bits. The code signal generating means controls the fine code signal and the coarse code signal in response to the plurality of the control signals in order that the termination resistance has a level which is correspondent to an input resistance.

Digital calibration circuits, devices and systems including same, and methods of operation

A calibration circuit for matching the output impedance of a driver by calibrating adjustments to the driver is described. The calibration circuit includes a driver circuit with a plurality of calibration transistors configured to receive a plurality of adjustment signals. The calibration circuit also includes a comparator circuit, and a binary searcher. The driver provides a signal corresponding to an output impedance to the comparator circuit. The output impedance signal is compared to a target impedance, and the comparator circuit then provides logic signals to the binary searcher representing whether the output impedance is greater than the target impedance. The binary searcher then selects a type of step size and count direction, in response to the logic signals, to count the number of steps for adjusting the calibration transistors of the driver.

RESISTOR ARRAY, OUTPUT BUFFER, AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

A resistor array made of a semiconductor includes a plurality of resistor groups and a common line that electrically connects the M-th resistors of the plurality of resistor groups. Each resistor group includes first to M-th resistors connected in series, M being an integer of 2 or greater, and at least one short-circuit line, each short-circuiting at least one, but not all, of the M resistors.

Self-adjusting impedance matching driver

A self-adjusting impedance matching driver for a digital circuit. The driver has both a pull-up gate to VDD and a pull-down gate to ground. An array of gates is provided in parallel with each of the pull-up gate and the pull-down gate, with any one or more of such gates being selectively enabled in response to circuit means that monitors the impedance match between the output of the driver and the network it drives. By enabling selectively such gates, any impedance mismatch can be minimized. The selective enablement may be done only at power up, and thereafter only if the driven network is changed substantially.

Integrated circuit capable of controlling impedance and electronic device including the same

Disclosed is an electronic device. The electronic device may include a printed circuit board (PCB) including at least one conducting wire, a first integrated circuit (IC) placed on the printed circuit board and including a transmit pin electrically connected to the at least one conducting wire, and a second IC placed on the printed circuit board and including a receive pin electrically connected to the at least one conducting wire, wherein the first IC is configured to transmit a specified signal having a first voltage through the transmit pin, and change an internal impedance of the first IC based on a reflected signal of the specified signal at a first time point.

Receiving circuit

A receiving circuit includes first and second input sections through which signals are to be received, first and second signal lines connected to the first and second input sections, respectively, a first circuit connected to the first and second signal lines and including a termination circuit and a self-test circuit, first and second capacitive elements that are provided in the first and second signal lines and configured to allow alternating-current components of the received signals to pass therethrough and interrupt at least direct-current components of the received signals from passing through, a second circuit that is connected to the first and second signal lines and configured to boost a gain of the received signals in a certain frequency band that have passed through the first and second capacitive elements, and first and second output sections through which the received signals boosted by the second circuit are output.

Integrated circuit with configurable on-die termination

Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.

IMPEDANCE CONTROL IN RADIO-FREQUENCY SWITCHES

A radio-frequency switch includes a first field-effect transistor disposed between a first node and a second node, the first field-effect transistor having a source, a drain, a gate, and a body. The switch further includes a coupling path connected between the body of the first field-effect transistor and the gate of the first field-effect transistor, the coupling path including a diode. The switch further includes an adjustable impedance network connected between the body of the first field-effect transistor and a ground reference, the adjustable impedance network being configured to reduce radio-frequency distortion in the first field-effect transistor.

Impedance controllable output drive circuit in semiconductor device and impedance control method therefor

A drive circuit having impedance control includes an impedance matching array unit having a plurality of transistors, the plurality of transistors selectively driven in accordance with an array drive control signal generated by control code data, and an update prohibition control unit for generating a transfer control signal to prohibit driving the transistors during a first time interval occurring when internal data transition, and applying the transfer control signal to the impedance matching array unit.

Techniques For Providing Calibrated On-Chip Termination Impedance

Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.

Method and apparatus for calibrating driver impedance

The present invention provides a method and apparatus is provided for calibrating a driver impedance in an integrated circuit device. The method includes providing a signal from a synchronous circuit that is indicative of an impedance mismatch between a driver circuit and a load. The method also includes selecting one of a plurality of impedances of the driver circuit to reduce the impedance mismatch in response to the signal.

Controlling slew rate performance across different output driver impedances

Embodiments are provided including one directed to an output driver system, having an adjustable pre-driver configured to maintain a generally constant slew rate of an output driver across a plurality of output driver impedances. Other embodiments provide a method of operating a memory device, including determining an output driver strength of an output driver and configuring the pre-driver based on the determined output driver strength.

Hybrid binary/thermometer code for controlled-voltage integrated circuit output drivers

A hybrid binary/thermometer code is employed to adjust the output impedance of a variable impedance output driver circuit having an impedance network comprising a plurality of impedance legs each programmably electrically connectable according to the hybrid binary/thermometer code in parallel between a voltage source and the signal pad. The plurality of impedance legs are partitioned into one or more set pairs of binary stepped impedance legs and corresponding thermometer stepped impedance legs. A binary set of calibration signals in the hybrid binary/thermometer code steps a given set of binary stepped impedance legs according to a binary code and a thermometer set of calibration signals in the hybrid binary/thermometer code steps the corresponding set of thermometer stepped impedance legs according to a thermometer code once per full count iteration of the binary set of calibration signals.

Semiconductor device capable of adjusting output impedance of external semiconductor device and output impedance adjusting method

In a semiconductor device capable of adjusting an output impedance of a first output impedance adjustable output buffer of an external semiconductor device connectable to the semiconductor device, a second output impedance adjustable output buffer is provided. A comparator compares a first output voltage of a real load circuit including the first output impedance adjustable output buffer with a second output voltage of a replica load circuit including the second output impedance adjustable output buffer. An output impedance control circuit transmits an output signal of the comparator to the external semiconductor device to adjust the output impedance of the first output impedance adjustable output buffer, so that the first output voltage is made equal to the second output voltage.

Dynamic output buffer circuit

A dynamic output buffer circuit performs an impedance matching function and a pre-emphasis function by using input and output signals, and consumes relatively less power, occupies a relatively smaller layout area, and dynamically varies an output impedance. The dynamic output buffer circuit dynamically matches an output impedance to the characteristic impedance of a metal line connected to an external circuit, pre-emphasizes at least one input signal, and includes a control circuit and an output circuit. The control circuit matches the output impedance of the dynamic output circuit to the characteristic impedance of the metal line in response to at least one output signal, and outputs a plurality of resistor control signals which are used to pre-emphasize at least one input signal in response to the input signal. The output circuit controls the output impedance and pre-emphasizes the input signal in response to the resistor control signals, and outputs the output signal.

Impedance control system for a center tapped termination bus

A method and apparatus for an impedance control system for a center tapped termination bus. One method of the present invention comprises comparing an output potential of a buffer with a pair of reference potentials. The output impedance of the buffer is adjusted to cause the buffer output voltage swing to match the reference potentials.

CMOS small signal switchable, impedence and voltage adjustable terminator network

A CMOS terminator circuit for connection to a network can be fabricated and used within for carrying small logic level signals for connecting data from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from said first circuit to said second circuit. The terminator circuit has a reference circuit coupled to a terminal circuit. The reference circuit has SOI devices back to back source coupled devices to each other for a tuned center reference voltage node, with their bodies connect to upper and lower level power supplies respectively. An upper level power source is connected to one side of the reference voltage node and a lower reference voltage power source is connected to the other side of the reference voltage node. The voltage level above the common tuned reference voltage and a lower level voltage is supplied to the terminator's ...

Line reflection reduction with energy-recovery driver

A system and method for reducing reflections in a transmission line and for recovering energy from the load in the transmission during the process. At least three drive signal levels are utilized. The transition from the second level to the third level during a rising transition and the transition from the second level to the first level during a falling transition is timed to coincide with the arrival of the reflected signal from the immediately-preceding transition. A capacitor is advantageously used as the source for the intermediate drive signal levels and advantageously facilitates energy recovery and conservation.

Impedance calibration circuit

An impedance calibration circuit for a serial ATA (SATA) transmitter has a resistor in series with each leg of the differential output of the transmitter. An array of selectable resistors is in parallel with each of the series resistors. Resistors in the array are selected to be in parallel with the series resistors. A calibration circuit utilizes a comparator to determine when the minimum error in the impedance calibration is reached. Offset errors in the comparator are compensated for by a circuit which determines the center of alternate ones and zeros generated by the comparator when the input signals are within the offset of the comparator, which should be the point of minimum error in the calibration.

LOW SWING VOLTAGE MODE DRIVER

An output driver includes control logic configured to switch on a pull-up circuit and a pull-down circuit to provide an output impedance for a logic low on a transmission line. The output driver includes a variable pull-up resistor. The control logic is configured to switch on the pull-up circuit to a first value of impedance to drive a logic high on the transmission line. The control logic is configured to switch on the pull-up circuit to a second value of impedance and to switch on the pull-down circuit to provide the output impedance to drive a logic low on the transmission line. The system could alternatively be configured for the inverse to switch on a combination of pull-up and pull-down circuits for a logic high, where the pull-down circuit is switched on for a logic low.

IMPEDANCE CALIBRATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME

An impedance calibration circuit may include: a first driver having an impedance calibrated according to a first impedance control code, and configured to drive an output terminal according to first data; a second driver having an impedance calibrated according to a second impedance control code, and configured to drive the output terminal according to second data; and an impedance calibration circuit configured to calibrate the first impedance control code to a first target value set to a resistance value of an external resistor, and calibrate the second impedance control code to a second target value different from the resistance value of the external resistor.

Method and apparatus for self-calibrating driving capability and resistance of on-die termination

A method and an apparatus for self-calibration of a driving capability and a resistance of an on-die termination are provided. The apparatus includes an output interface physical layer (PHY) and a ring oscillator. The output interface PHY receives an operation voltage. The ring oscillator surrounds the output interface PHY to sense a work temperature or the operation voltage and accordingly outputs a sensing result. The driving capability or the resistance of the on-die termination of the output interface PHY is adjusted according to the sensing result.

Dynamic output buffer circuit

A dynamic output buffer circuit performs an impedance matching function and a pre-emphasis function by using input and output signals, and consumes relatively less power, occupies a relatively smaller layout area, and dynamically varies an output impedance. The dynamic output buffer circuit dynamically matches an output impedance to the characteristic impedance of a metal line connected to an external circuit, pre-emphasizes at least one input signal, and includes a control circuit and an output circuit. The control circuit matches the output impedance of the dynamic output circuit to the characteristic impedance of the metal line in response to at least one output signal, and outputs a plurality of resistor control signals which are used to pre-emphasize at least one input signal in response to the input signal. The output circuit controls the output impedance and pre-emphasizes the input signal in response to the resistor control signals, and outputs the output signal.

Data output buffer and semiconductor apparatus including the same

A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.

TERMINATION CIRCUIT FOR ON-DIE TERMINATION

Digitally controlled impedance for I/O of an integrated device

Transceiver circuit for an integrated circuit

Interfaceschaltung zur Realisierung einer S/T-Schnittstelle nach Spezifikation ITU-T I.430

CMOS-Logikschaltung

HYBRID COMPENSATED OUTPUT BUFFER STRUCTURE

SUPERCONDUCTING TUNABLE COUPLER

A superconducting system is provided that includes a coplanar superconducting circuit. The coplanar superconducting circuit includes a first ground plane region, a second ground plane region electrically isolated from the first ground plane region by portions of the coplanar superconducting circuit, and a tunable coupler having a first port and a second port. The tunable coupler comprises a variable inductance coupling element coupled between the first port and the second port, a first termination inductor having a first end coupled between a first end of the variable inductance element and a second end coupled to the first ground plane region, and a second termination inductor having a first end coupled between a second end of the variable inductance element and a second end coupled to the second ground plane region.

SUPERCONDUCTING TUNABLE COUPLER

A superconducting system is provided that includes a coplanar superconducting circuit. The coplanar superconducting circuit includes a first ground plane region, a second ground plane region electrically isolated from the first ground plane region by portions of the coplanar superconducting circuit, and a tunable coupler having a first port and a second port. The tunable coupler comprises a variable inductance coupling element coupled between the first port and the second port, a first termination inductor having a first end coupled between a first end of the variable inductance element and a second end coupled to the first ground plane region, and a second termination inductor having a first end coupled between a second end of the variable inductance element and a second end coupled to the second ground plane region.

DIGITALLY CONTROLLED IMPEDANCE FOR I/O OF AN INTEGRATED CIRCUIT DEVICE

A system for controlling the impedances of circuits on an integrated circuit chip is provided. At least one circuit is selected to operate as a p-channel reference circuit, and at least one circuit is selected to operate as an n- channel reference circuit. Other circuits are selected to operate as circuits and/or line termination circuits. A digitally controlled impedance (DCI) circuit controls the p-channel reference circuit to determine a desired configuration of p-channel transistors for use in the circuits. The DCI circuit further controls the n-channel reference circuit to determine a desired configuration of n-channel transistors for use in the circuits. The DCI circuit takes into account such factors as resistances of p-channel transistors in the p-channel reference circuit, resistances of n-channel transistors in the n-channel reference circuit, as well as temperature, voltage and process variations. The DCI cirucit relays information identifying the desired configurations of the ...

IMPEDANCE ADJUSTMENT CIRCUIT, IMPEDANCE ADJUSTMENT METHOD, AND SEMICONDUCTOR DEVICE

An impedance adjustment circuit has an external resistor, a comparator which compares the potential of one terminal of the external resistor with a predetermined voltage, a counter whose counted value changes in accordance with an output from the comparator and which outputs a control signal corresponding to the counted value, an NMOS array whose value of resistance changes in accordance with the control signal and which is connected to one terminal of the external resistor and an NMOS arbitration circuit which detects an output from the NMOS comparator a plurality of times and outputs a signal determined by a majority decision logic taken on the detected signals to the counter.

DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS

A system and method of performing off chip drive (OCD) and on-die termina tion (ODT) are provided A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implemen t both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an "on" output is to be generat ed, and the pull-down network is configured to produce a calibrated drive im pedance when an "off" output is to be generated. In termination mode, the pu ll- up network and the pull-down network are configured to produce a calibra ted pull-up resistance and pull-down resistance, respectively, such that tog ether they form a split termination.

Impedance Matching Process and Device for a Transmitter and/or a Receiver and Integrated Circuit and Transmission System Using Same

IMPEDANCE MATCHING PROCESS AND DEVICE FOR A TRANSMITTER AND/OR A RECEIVER AND INTEGRATED CIRCUIT AND TRANSMISSION SYSTEM USING SAME

Le circuit intégré (IC) comprend un dispositif (10) d'adaptation d'impédance sur l'impédance caractéristique (Zc) de lignes de transmission (13) reliant chacune un émetteur (11) à un récepteur (12). Deux blocs d'adaptation (14, 15) reproduisent les structures respectives des émetteurs (11) et des récepteurs (12) et leur adaptation d'impédance est faite à partir d'une résistance de référence (Rr). Un dispositif d'asservissement (Len, Lep, Lrn, Lrp) reproduit les conditions d'adaptation dans les émetteurs (11) et les récepteurs (12) respectifs.

High resolution output driver

High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such "differential" or "non not uniform" sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC.; In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather ...

Dynamic impedance control for input/output buffers

A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.

Ring based impedance control of an output driver

In one embodiment, there is a method that can include utilizing a ring oscillator module to determine a process corner of an integrated circuit as fabricated that includes the ring oscillator module. The impedance of an output driver of the integrated circuit can be altered based on the process corner of the integrated circuit as fabricated.

Semiconductor device and method of adjusting characteristic thereof

To suppress the number of clocks needed to adjust the impedance of an output buffer. A pull-up replica buffer is connected between a calibration terminal and power supply wiring, and is controlled in impedance by a DRZQP signal supplied from a counter. A pull-down replica buffer is connected between ground wiring and a connection node A, and is controlled in impedance by a DRZQN signal supplied from the counter. More specifically, the DRZQP signal and the DRZQN signal indicate count values. The impedances of the replica buffers are increased or decreased stepwise in proportion to the count values. The count values are updated according to a binary search method.

Data output buffer and memory device

A data output buffer includes a driving unit and a control unit. The driving unit selectively performs a termination operation that provides a termination impedance to a transmission line coupled to an external pin, and a driving operation that provides a drive impedance to the transmission line while outputting read data. The control unit adjusts a value of the termination impedance and a value of the drive impedance based on an output voltage at the external pin during a termination mode, and controls the driving unit to selectively perform one of the termination operation and the driving operation during a driving mode.

High resolution output driver

High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such “differential” or “non-uniform” sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested “DAC within a DAC” arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions.

Semiconductor device, circuit board device, and information processing device

In a semiconductor device, a selector selects a different reference voltage depending on whether the impedance of a transmitter or of a receiver is to be adjusted, and causes a reference voltage generator to generate the selected reference voltage. The reference voltage generator generates the reference voltage selected by the selector and applies the generated reference voltage to an impedance adjuster. The impedance adjuster adjusts the impedance of the transmitter and the impedance of the receiver, separately from each other, in accordance with the input reference voltage.

Driver Calibration Methods and Circuits

Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e.g., clock or data) transmission. Some embodiments identify inactive elements by examining incoming signals.

TERMINATION DEVICE SYSTEM

A termination device system is provided that includes a device required to be terminated with a resistor and a termination circuit. The termination circuit includes a termination resistor circuit and a judgment circuit connected to the termination resistor circuit. The termination resistor circuit includes at least one controlled termination unit. Each controlled termination unit includes a termination connecting end for connecting the device required to be terminated with a resistor, a controlled switch and a resistor, and provides, based on on/off of the controlled switch, a termination resistor for the device connected to the termination connecting end. The judgment circuit judges whether the device is required to be connected to the termination resistor based on a control instruction of a control device controlling the device connected to the termination connecting end, to output an on/off control signal to the controlled switch of the termination resistor circuit to control on/off. 1. A termination resistor circuit , comprising:at least one controlled termination unit, each of which comprising a termination connecting end for connecting a device required to be terminated with a resistor, a controlled switch and a resistor, for providing a termination resistor for the device connected to the termination connecting end based on on/off of the controlled switch.2. The termination resistor circuit as in claim 1 , wherein the at least one controlled termination unit comprises a voltage divider resistor circuit for performing voltage division on a power supply voltage claim 1 , wherein the voltage divider resistor circuit comprises resistors and controlled switches.3. The termination resistor circuit as in claim 1 , wherein the termination resistor circuit is a termination chip claim 1 , and each controlled termination unit is within the termination chip.4. The termination resistor circuit as in claim 1 , wherein the termination resistor circuit comprises a ...

Device

A semiconductor device has a first controlled chip, including a first replica output circuit having the same configuration as a first output circuit, a first ZQ terminal connected to the first replica output circuit, a first through electrode connected to the first ZQ terminal, and a first control circuit which sets the impedance of the first replica output circuit. A control chip includes a second ZQ terminal connected to the first through electrode, a comparator circuit which compares a voltage of the second ZQ terminal with a reference voltage, and a second control circuit 123 which performs a process based on a comparison by the comparator circuit. The first control circuit and the second control circuit receive a common input signal to operate and sequentially change and set the impedance until the comparison result changes when an external resistance element is connected to the second ZQ terminal.

TERMINATION CIRCUIT AND DC BALANCE METHOD THEREOF

A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers. 1. A termination circuit for a plurality of memories controlled by a controller , comprising:a plurality of drivers, each coupled to the memories via a transmission line;a plurality of resistors, each coupled to the corresponding driver via the corresponding transmission line; anda plurality of capacitors, each coupled between the corresponding resistor and a reference voltage,wherein the controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers.2. The termination circuit as claimed in claim 1 , wherein the controller further provides data to the memories via the drivers claim 1 , wherein the controller further records the data provided to the memories via each of the drivers and obtains a plurality of statistic values according to a quantity of logic “0” and a quantity of logic “1” of the recorded data.3 ...

HIGH-SPEED DRIVER CIRCUIT

An inverter-type high speed driver circuit having a first inverter branch and a second inverter branch wherein each of the inverter branches comprising a parallel circuit of a serial connection of a first impedance tuning unit and a respective first clocking transistor and a serial connection of a second impedance tuning unit and a respective second clocking transistor. The impedance tuning units are configured to adapt the conductivity of the respective inverter branch to set the output impedance of the driver circuit and each of the impedance tuning units is controlled in accordance with a data stream. 1. An inverter-type high speed driver circuit comprising:a first inverter branch and a second inverter branch, wherein each of the inverter branches comprising a parallel circuit of a serial connection of a first impedance tuning unit and a respective first clocking transistor and a serial connection of a second impedance tuning unit and a respective second clocking transistor, wherein the impedance tuning units are configured to adapt conductivity of a respective inverter branch to set an output impedance of the driver circuit; wherein each of the impedance tuning units is controlled in accordance with a data stream.2. The driver circuit according to claim 1 , wherein each impedance tuning unit comprises a plurality of parallelized impedance tuning transistors separately controlled by respective weighted data control signals claim 1 , and wherein an impedance weighting unit is provided to generate weighted data control signals as a result of an incoming data signal and a given impedance setting signal.3. The driver circuit according to claim 1 , wherein each of the inverter branches comprises a resistor in series to the parallel circuit.4. The driver circuit according to claim 1 , wherein the inverter branches are interconnected at a node wherein a resistor is serially connected between an output of the driver circuit and the node.5. The driver circuit according to ...

Adaptive termination

A system for receiving data is provided the system includes an inductive data device, such as a device that receives high-speed data over an inductive coupling. An adjustable impedance is coupled to the inductive data device, where the adjustable impedance is used for dynamically controlling ringing in the inductive data device, such as by damping ringing signals generated by circuit inductances or capacitances.

ADAPTIVE BUFFER

An embodiment of a buffer for a transmission line, a circuit including such a buffer, a high-speed data link, and a low-voltage differential signaling (LVDS) system. 115.-. (canceled)16. A circuit , comprising:a node configured to be coupled to load that includes a signal-propagation medium, the load having an impedance;a driver configured to drive a calibration signal onto the node; anda calibrator coupled to the node and configured to generate, in response to the calibration signal, an impedance signal that is related to the impedance of the load.17. The circuit of wherein the node includes an output node.18. The circuit of wherein the node includes an input node.19. The circuit of wherein the driver has an output impedance and is configured to adjust the output impedance in response to the impedance signal.20. The circuit of claim 16 , further comprising a receiving stage coupled to the node claim 16 , having an input impedance claim 16 , and configured to adjust the input impedance in response to the impedance signal.21. The circuit of claim 16 , further comprising a transmitting stage coupled to the node claim 16 , having an output impedance claim 16 , and configured to adjust the output impedance in response to the impedance signal.22. The circuit of wherein the driver includes driver elements that selectively activate in response to the impedance signal to adjust the output impedance of the driver claim 16 ,23. The circuit of wherein the driver has an output impedance and is configured to set the output impedance approximately equal to the impedance of the load in response to the impedance signal.24. The circuit of claim 16 , further comprising a transmitting stage coupled to the node claim 16 , having an output impedance claim 16 , and configured to set the output impedance approximately equal to the impedance of the load in response to the impedance signal.25. The circuit of wherein:the driver includes a calibration portion that is configured to drive the ...

Memory system capable of calibrating output voltage level of semiconductor memory device and method of calibrating output voltage level of semiconductor memory device

Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on a reference voltage when the semiconductor memory device is electrically connected to the memory controller.

SYMMETRICALLY OPERATING SINGLE-ENDED INPUT BUFFER DEVICES AND METHODS

Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One example buffer has a symmetrical response to a single input signal applied to the first input terminal by mimicking the transition of a signal applied to the second input terminal in the opposite direction. The buffer includes two amplifier circuits structured to be complementary with respect to each other. Each of the amplifier circuits includes a first transistor having a first input node that receives an input signal transitioning across a range of high and low voltage levels, and a second transistor having a second input node that receives a reference signal. The first input node is coupled to the second transistor through a capacitor to mimic the second input node transitioning in the direction opposite to the transition of the input signal. 1. An apparatus , comprising:a first transistor configured to receive an input signal and adjust a resistance of a second transistor based, at least in part, on the input signal, the first transistor configured to provide an output signal based, at least in part, on the input signal,wherein a rate at which the output signal is provided is based, at least in part, on a magnitude of the resistance of the second transistor.2. The apparatus of claim 1 , wherein the resistance is an ON-resistance.3. The apparatus of claim 1 , wherein the input signal comprises an analog signal and the output signal comprises a digital signal.4. The apparatus of claim 3 , wherein the first transistor is configured to provide the output signal having a first state when the input signal has a voltage less than a reference voltage and to provide the output signal having a second state when the input signal has a voltage greater than the reference voltage.5. The apparatus of claim 1 , wherein a terminal of the first transistor and a terminal of the second transistor are capacitively coupled.6. The apparatus of claim 1 , ...

IMPEDANCE CALIBRATION DEVICE AND METHOD

An impedance calibration device includes: a variable impedance, an operational unit, an analog-digital converter, and a controller. The operational unit receives a first analog signal and a second analog signal, and performs a difference operation to generate an output voltage. The analog-digital converter generates an adjustment code according to the output voltage. The controller is coupled to the analog-digital converter and the variable impedance, and adjusts a resistance value of the variable impedance according to the adjustment code. 1. An impedance calibration device , comprising:a variable impedance;an operational unit, used for receiving a first analog signal and a second analog signal and performing a difference operation to generate an output voltage, wherein the first analog signal has variation amount information of the variable impedance, and the second analog signal is a reference signal;an analog-digital converter, coupled to the operational unit, and used for receiving the output voltage to generate an adjustment code; anda controller, coupled to the analog-digital converter and the variable impedance, and used for adjusting a resistance value of the variable impedance according to the adjustment code.2. The impedance calibration device according to claim 1 , further comprising:a gain controller, coupled between the operational unit and the analog-digital converter, and used for adjusting a voltage of the output voltage.3. The impedance calibration device according to claim 2 , wherein the output voltage is mapped to a full dynamic range of the analog-digital converter.4. The impedance calibration device according to claim 1 , wherein the controller adjusts the resistance value of the variable impedance according to a maximum variation amount of the variable impedance and a full dynamic range of the analog-digital converter.5. The impedance calibration device according to claim 1 , wherein the first analog signal is a first current generated ...

Signal sensing circuit

A signal sensing circuit converts a received current input into a voltage output and provides the voltage output to an analog-to-digital converter (ADC) to generate a digital output signal. The voltage output is associated with a circuit having a first reference impedance, and a reference voltage of the ADC is associated with a circuit having a second reference impedance, wherein the circuit having the first reference impedance and the circuit having the second reference impedance are formed by the same material, so that the ratio between the changes in the current input and the changes in the value of the digital output signal is a constant.

TERMINATION CIRCUIT FOR ON-DIE TERMINATION

In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage. 1. A termination circuit for a terminal of a semiconductor device , the terminal associated with an expected voltage swing , the termination circuit comprising:a transistor connected between the terminal and a power supply at a supply voltage;analog control circuitry for controllably enabling and disabling on-die termination, comprising calibrator circuitry with access to a reference resistance, the calibrator circuitry configured to carry out a calibration process for selecting one of a plurality of analog calibration voltages that would cause the transistor to impart a resistance substantially equal to a multiple of the reference resistance if supplied thereto as gate voltage,wherein the control circuitry is configured to drive the gate of the transistor with said one of a plurality of analog calibration voltages when on-die termination is enabled, said one of a plurality of analog calibration voltages being outside a range of voltages defined by the supply voltage and the expected voltage swing.2. The termination circuit defined in claim 1 , wherein the supply voltage is Vdd claim 1 ,3. The termination circuit defined in ...

Integrated circuit and method for operating the same

A integrated circuit includes a clock control signal generation circuit configured to generate a clock control signal using transition of a control signal, a clock control unit configured to activate a control clock in an activated period of the clock control signal, and to deactivate the control clock in a deactivated period of the clock control signal, and a control circuit configured to operate in response to the control signal and in synchronization with the control clock.

ON-DIE TERMINATION CIRCUIT

An on-die termination circuit includes: a clock signal generation block configured to output a clock signal in response to a clock enable signal, a termination block configured to perform a termination operation on an input/output pad in response to the clock signal, a first termination control signal, and a second termination control signal, a first termination control block configured to generate the first termination control signal in response to the clock signal and a latency control signal, a second termination control block configured to control a latency of a second command and to generate the second termination control signal in response to the clock signal and the latency control signal, and a clock enable signal generation block configured to generate the clock enable signal in response to the first command, the first termination control signal, and the second is command. 2. The on-die termination circuit according to claim 1 , wherein the first command corresponds to an on-die termination command.3. The on-die termination circuit according to claim 1 , wherein the second command corresponds to a write command.4. The on-die termination circuit according to claim 1 , wherein the clock signal generation block corresponds to a delay-locked loop.5. The on-die termination circuit according to claim 1 , wherein the first termination control block comprises:a timing control block configured to control the timing of an external command by a set time and to generate the first command;a variable delay unit configured to delay the first command and to generate a preliminary control signal; anda first latency shift block configured to delay the preliminary control signal by a predetermined latency in response to the latency is control signal on the basis of the delay-locked clock signal, and to generate the first termination control signal.6. The on-die termination circuit according to claim 5 , wherein the first latency shift block comprises:a shift control unit ...

SYSTEM FOR TRANSMISSION LINE TERMINATION BY SIGNAL CANCELLATION

A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single connection point and is operative to at least attenuate a signal propagated between the first and second segments. In the second state, a driver is coupled to the connection point and is operative to conduct a signal over the first and second segments. 1a connector for connecting to the outlet for coupling to the digital data signal carried over the wire pair; anda termination circuit selectively couplable to said connector and constructed for terminating the digital data signal propagated over the wire pair when said device is connected to said connector,wherein said device is switchable between a first state in which said termination circuit is coupled to said connector and a second state in which said termination circuit is not coupled to said connector.. A device for use with a wire pair in walls of a building and connected to an outlet, the wire pair being connected in a bus topology for carrying a digital data signal, said device comprising: This is a continuation of U.S. application Ser. No. 13/245,433, filed on Nov. 14, 2011, which is a continuation of U.S. application Ser. No. 12/724,952, filed on Mar. 16, 2010, which is a continuation of U.S. application Ser. No. 12/252,025, filed Oct. allowed, which is a continuation of U.S. application Ser. No. 12/026,321, filed Feb. 5, 2008, now U.S. Pat. No. 7,453,284, issued on Nov. 18, 2008, which is a continuation of U.S. application Ser. No. 11/346,396, filed on Feb. 3, 2006, now U.S. Pat. No. 7,336,096, issued on Feb. 26, 2008, which is a division of U.S. application Ser. No. 11/100,453, filed on Apr. 7, 2005, now U.S. Pat. No. 7,068,066, issued on Jun. 27, 2006, which is a continuation of U.S. application Ser. No. ...

On-chip impedance network with digital coarse and analog fine tuning

System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.

METHODS AND APPARATUSES INCLUDING A VARIABLE TERMINATION IMPEDANCE RATIO

Methods of changing a centerline voltage of a data signal are described, along with apparatuses to change the centerline voltage. In one such method, portions of a termination circuit coupled to an output pin are selectively activated to change an impedance of the termination circuit to change the centerline voltage of the data signal driven to the output pin. One such apparatus includes pull-up impedances and pull-down impedances that can be activated to change the centerline voltage of the data signal. Additional embodiments are also described. 1. A memory device comprising:a memory array for storing data;a termination register configured to store termination values;a termination control circuit coupled to the termination register; andan I/O circuit, coupled to the memory array and the termination control circuit, for transmitting data from and receiving data to the memory array, the I/O circuit comprising a plurality of driver and receiver circuits, each of the plurality of driver and receiver circuits having an adjustable pull-up impedance and an adjustable pull-down impedance that are adjusted by the termination control circuit in response to the stored termination values.2. The memory device of and further comprising a control circuit to control operation of the memory device claim 1 , the control circuit coupled to the termination register.3. The memory device of wherein the control circuit is configured to write the termination values to the termination register.4. The memory device of wherein each adjustable pull-up impedance and each adjustable pull-down impedance comprises a plurality of resistance circuits coupled together in parallel claim 1 , each resistance circuit having a fuse in series with a resistance.5. The memory device of wherein the plurality of resistance circuits for the adjustable pull-up impedance are coupled in parallel between an output pin of the memory device and a supply voltage.6. The memory device of wherein the plurality of ...

Apparatus and methods for digital configuration of integrated circuits

Apparatus and method for digital configuration of integrated circuits (ICs) are provided herein. In certain implementations, an IC includes an impedance sensing circuit and at least one pin used for digital configuration. The impedance sensing circuit can detect an impedance value of an external passive network electrically connected to the pin, and can digitally configure the IC based on the detected impedance. For example, an end-user can connect an external resistor of a particular resistance to the pin, and the impedance sensing circuit can sense or detect the external resistor's resistance and digitally configure the IC based on the detected resistance. Accordingly, an end-user can digitally configure the IC by connecting a passive external component corresponding to a desired digital configuration to the pin. In certain implementations, the IC includes multiple pins, and the digital configuration is based on the impedances detected on each of the pins.

ON-DIE TERMINATION ENABLE SIGNAL GENERATOR, SEMICONDUCTOR APPARATUS, AND SEMICONDUCTOR SYSTEM

A semiconductor apparatus may include an on-die termination (ODT) enable signal generator configured to enable an ODT enable signal in response to a data strobe signal, or enable the ODT enable signal in response to a command latch enable signal and an address latch enable signal. The semiconductor apparatus may include an ODT circuit configured to perform an ODT operation in response to the ODT enable signal. 1. A semiconductor apparatus comprising:an on-die termination (ODT) enable signal generator configured to enable an ODT enable signal in response to a data strobe signal, or enable the ODT enable signal in response to a command latch enable signal and an address latch enable signal; andan ODT circuit configured to perform an ODT operation in response to the ODT enable signal,wherein the ODT enable signal generator enables the ODT enable signal in response to the data strobe signal in a non-test and enables the ODT enable signal in response to the command latch enable signal and the address latch enable signal in a test.2. (canceled)3. The semiconductor apparatus of claim 1 , wherein the ODT enable signal generator disables the ODT enable signal in response to a chip enable signal claim 1 , the command latch enable signal claim 1 , and the address latch enable signal.4. The semiconductor apparatus of claim 3 , wherein the ODT enable signal generator includes:a set signal generator configured to generate a set signal in response to the data strobe signal, the command latch enable signal, the address latch enable signal, and a test signal;a reset signal generator configured to generate a reset signal in response to the chip enable signal, the command latch enable signal, and the address latch enable signal; andan enable signal generator configured to enable the ODT enable signal in response to the set signal or disable the ODT enable signal in response to the reset signal.5. The semiconductor apparatus of claim 4 , wherein the set signal generator outputs the ...

Apparatus for transmitting and receiving a signal, a method of operating the same, a memory device, and a method of operating the memory device

A signal transmitting and receiving apparatus including: a first on-die termination circuit connected to a first pin through which a first signal is transmitted or received and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the first pin; a second on-die termination circuit connected to a second pin through which a second signal is transmitted or received and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the second pin; and an on-die termination control circuit configured to independently control an enable time and a disable time of each of the first on-die termination circuit and the second on-die termination circuit.

DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS

A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination. 1. (canceled)2. A method for controlling the impedance of a buffer having a plurality of pull-up transistors and a plurality of pull-down transistors , the method comprising:receiving a data output signal;receiving an output enable signal;receiving a termination enable signal;receiving a first plurality of impedance control bits, a second plurality of impedance control bits, a third plurality of impedance control bits, and a fourth plurality of impedance control bits;enabling, when the output enable signal is in a first state and the data output signal is in a first state, one or more of the plurality of pull-up transistors determined by the first plurality of impedance control bits;enabling, when the output enable signal is in a first state and the data output signal is in a second state, one or more of the plurality of pull-down transistors determined by the second plurality of impedance control bits; andenabling, when the termination enable signal is in a first state, one or more of the plurality of pull-up transistors determined by the third plurality of impedance control bits and one or more of the plurality of pull-down transistors determined by the fourth plurality of impedance control bits;wherein the first and second pluralities of impedance control bits ...

Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching. 1. (canceled)2. An on-die termination (ODT) control circuit comprising:at least one reference-voltage node;a reference ODT resistor to exhibit a calibrated voltage responsive to an ODT count;a comparator having a first comparator input, a second comparator input, and a comparator output;a first pass gate selectively coupling the first comparator input to the at least one reference-voltage node;a second pass gate selectively coupling the second comparator input to the reference ODT resistor to receive the calibrated voltage;a third pass gate selectively coupling the second comparator input to the at least one reference-voltage node; anda counter coupled between the comparator output and the reference ODT resistor, the counter to issue the ODT count responsive to an output of the comparator.3. The ODT control circuit of claim 2 , further comprising a voltage source between the at least one reference-voltage node and the second comparator input.4. The ODT control circuit of claim 3 , wherein the at least one reference voltage node comprising a reference-voltage node selectively coupled to the first comparator input and a second reference-voltage node selectively coupled to the second comparator input via the ...

APPARATUSES AND METHODS FOR PARTIAL BIT DE-EMPHASIS

Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes a pull-up circuit including one or more pull-up legs, and a pull-down circuit including one or more pull-down legs. The control circuit may be coupled to the output driver and configured to receive an input signal having a first logical value and a second logical value, and in response to determining the logical transition has occurred from the second logic value to the first logic value, cause the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period preceding the first portion. 1. An apparatus comprising:an external terminal; and receive a first signal having a first logical value,', 'receive a second signal following the first signal, the second signal having a second logical value different from the first logical value, and', 'drive, in response to receiving the second signal, the external terminal from a first voltage to a second voltage by way of a third voltage, wherein the third voltage is a de-emphasized first voltage based at least in part on a de-emphasis time., 'an output driver coupled to the external terminal, the output driver configured to2. The apparatus of claim 1 , wherein the output driver de-emphasizes the first voltage for two bit periods.3. The apparatus of claim 1 , further comprising a variable delay circuit to introduce a delay interval claim 1 , wherein the delay interval determines the de-emphasis time.4. The apparatus of claim 3 , wherein the delay interval comprises a half bit period to produce a half bit period de-emphasis.5. The apparatus of claim 3 , wherein the variable delay circuit is configured to receive an input signal having first and second logic values claim 3 , and generate a delayed signal that is delayed relative to ...

IMPEDANCE CALIBRATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME

An impedance calibration circuit includes a first detection unit configured to generate a first pull-up impedance detection signal according to a resistance value of an internal reference resistor, a second detection unit configured to generate a second pull-up impedance detection signal according to a resistance value of an external reference resistor coupled to an external reference resistor pad, a switching unit configured to select the first pull-up impedance detection signal or the second pull-up impedance detection signal according to the internal impedance calibration enable signal and output the selected pull-up impedance detection signal, and an impedance calibration signal generation unit configured to generate a plurality of impedance calibration signals according to an output of the switching unit. 1. An impedance calibration circuit comprising:a first detection unit configured to generate a first pull-up impedance detection signal according to a resistance value of an internal reference resistor;a second detection unit configured to generate a second pull-up impedance detection signal according to a resistance value of an external reference resistor coupled to an external reference resistor pad;a switching unit configured to select the first pull-up impedance detection signal or the second pull-up impedance detection signal according to an internal impedance calibration enable signal and output the selected pull-up impedance detection signal; andan impedance calibration signal generation unit configured to generate a plurality of impedance calibration signals according to an output of the switching unit.2. The impedance calibration circuit of claim 1 , wherein the first detection unit includes:a replica pull-up driver coupled between a power terminal and the internal reference resistor; anda comparator configured to generate the first pull-up impedance detection signal by comparing a level of a node to which the replica pull-up driver and the internal ...

Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching. 1. (canceled)2. A method for calibrating a resistance of an on-die termination (ODT) resistor against an off-die resistor using a single comparator , the method comprising:drawing a reference-resistor current through the off-die resistor to develop a reference-resistor voltage;comparing, with the single comparator, the reference-resistor voltage to a reference voltage;adjusting the reference-resistor current through the off-die resistor responsive to an output of the single comparator until the reference-resistor voltage matches the reference voltage to produce a calibrated reference-resistor current and a calibrated reference-resistor voltage;creating a calibrated ODT current proportional to the calibrated reference-resistor current;drawing the calibrated ODT current through the ODT resistor to develop an ODT voltage; andadjusting the resistance of the ODT resistor responsive to the output of the single comparator until the ODT voltage matches the calibrated reference-resistor voltage and the reference voltage.3. The method of claim 2 , further comprising comparing claim 2 , with the single comparator claim 2 , the ODT voltage to the calibrated reference-resistor voltage.4. The method of claim 2 , ...

APPARATUSES AND METHODS FOR PROVIDING AN INDICATOR OF OPERATIONAL READINESS OF VARIOUS CIRCUITS OF A SEMICONDUCTOR DEVICE FOLLOWING POWER UP

Apparatuses and methods for providing an indicator of operational readiness of various circuits of a semiconductor device following power up are described in the present disclosure. An example apparatus includes a first circuit configured to receive a supply voltage and further configured to provide an active first signal responsive to the supply voltage exceeding a threshold voltage. The example apparatus further includes a second circuit coupled to the first circuit and activated by the active first signal, the second circuit configured to provide an active second signal when a third circuit is ready for operation. 1. An apparatus , comprising:an oscillator circuit configured to receive an activation signal and provide an oscillating signal based on the received activation signal;a timing circuit coupled to the oscillator circuit and configured to provide an oscillating data signal based at least in part on the oscillating signal; anda flip flop circuit coupled to the timing circuit and configured to latch a logic level of the oscillating data signal and provide an output signal to the oscillator circuit having a logic level based at least in part on the latched logic level.2. The apparatus of claim 1 , wherein the flip flop circuit is a model circuit configured to model other flip flop circuits.3. The apparatus of claim 1 , wherein at least one other flip flop circuit is enabled based on the output signal of the flip flop circuit.4. The apparatus of claim 1 , further comprising:a plurality of other flip flop circuits configured to be enabled,wherein the flip flop circuit is a model circuit, andwherein operation of the plurality of other flip flop circuits is responsive to operation of the model circuit.5. The apparatus of claim 4 , wherein the plurality of other flip flop circuits are configured to be enabled for operation responsive to a change in the logic level of the output signal of the model circuit.6. The apparatus of claim 1 , further comprising:a ...

INTEGRATED CIRCUIT AND DATA INPUT METHOD

An integrated circuit includes a data input such as a data pad for receiving an external data signal input and an on-die termination (ODT) information input for receiving ODT information from an external device. An ODT circuit selectively couples a termination resistor to the data pad based on the ODT information. An input buffer is coupled to the data pad for determining data that is input into the pad using a reference voltage. A reference voltage generator is coupled to the input buffer and generates the reference voltage on the basis of the ODT information. 1. An integrated circuit comprising:a pad configured to receive an external data signal input;an on-die termination (ODT) information input configured to receive ODT information from an external device;an ODT circuit configured to selectively couple a termination resistor to the pad based on the ODT information;an input buffer coupled to the pad and configured to determine a data value based on a reference voltage; anda reference voltage generator coupled to the input buffer and configured to generate the reference voltage based on the ODT information.2. The integrated circuit of claim 1 , wherein the ODT information comprises on/off information indicating whether to perform an ODT operation claim 1 , termination information indicating a pull-up termination or a pull-down termination claim 1 , and resistance information indicating an ODT resistance value.3. The integrated circuit of claim 2 , further comprising a mode register configured to provide least a portion of the ODT information.4. The integrated circuit of claim 1 , wherein the ODT circuit further comprises a pull-up termination circuit including the termination resistor selectively coupled between the pad and a power supply voltage based on the ODT information.5. The integrated circuit of claim 1 , wherein the ODT circuit further comprises a pull-down termination circuit including the termination resistor selectively coupled between the pad and a ...

PACKAGED INTEGRATED CIRCUIT MEMORY DEVICES HAVING ENHANCED ON-DIE-TERMINATION CIRCUITS THEREIN AND METHODS OF OPERATING SAME

A memory device includes a pad region having a flag pad separated from an external host, and a signal pad connected to the external host. A bank region is provided having a plurality of memory cells therein. An on-die-termination (ODT) setting circuit is provided, which is configured to receive a control command including first data corresponding to termination resistance requested by the host, and a ODT enable signal. The setting circuit is configured to generate second data corresponding to the ODT resistance. An ODT enable circuit is provided, which is configured to output an ODT flag signal to the flag pad, in response to the control command and the ODT enable signal. A resistor circuit is provided, which is configured to connect the ODT resistance to the signal pad using the second data. 1. A memory device comprising:a pad region having a flag pad and a signal pad thereon;a memory bank region having a plurality of memory cells therein;an on-die-termination (ODT) setting circuit configured to receive a control command including first data corresponding to a termination resistance requested by an external host, and an ODT enable signal, and further configured to generate second data corresponding to an ODT resistance;an ODT enable circuit configured to output an ODT flag signal to the flag pad, in response to the control command and the ODT enable signal; anda resistor circuit configured to connect the ODT resistance to the signal pad, in response to the second data.2. The memory device according to claim 1 , further comprising:a transmitter having an output terminal electrically coupled to the flag pad; anda receiver having an input terminal electrically coupled to the flag pad.3. The memory device according to claim 2 , wherein the receiver is turned off and the transmitter is turned on to thereby output the ODT flag signal claim 2 , in response to receipt of the ODT enable signal by the ODT enable circuit.4. The memory device according to claim 3 , wherein the ...

ON-DIE TERMINATION CONTROL WITHOUT A DEDICATED PIN IN A MULTI-RANK SYSTEM

A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting. 1. A method for selectively applying on-die termination , comprising:sending a memory access command concurrently to a number of ranks of memory devices corresponding to a memory access operation, the memory access command directed to a target rank to execute the command;triggering one or more non-target ranks of the number of ranks to change an on-die termination (ODT) setting for a duration of the memory access operation; andselecting the target rank to execute the memory access operation.2. The method of claim 1 , wherein sending the memory access command comprises sending a read command claim 1 , and wherein triggering the one or more non-target ranks to change the ODT setting comprises triggering the a non-target rank to engage ODT.3. The method of claim 1 , wherein sending the memory access command comprises sending a write command claim 1 , and wherein triggering the one or more non-target ranks to change the ODT setting comprises triggering the target rank and at least one non-target rank to engage ODT.4. The method of claim 1 , wherein sending the memory access command comprises sending the memory access command from a memory controller.5. The method of claim 1 , wherein sending the memory access command comprises sending multiple sequential commands to generate the memory access operation.6. The method of claim 5 , wherein the triggering further comprises sending a first command indicating the memory access operation ...

ON-DIE TERMINATION CIRCUIT, A MEMORY DEVICE INCLUDING THE ON-DIE TERMINATION CIRCUIT, AND A MEMORY SYSTEM INCLUDING THE MEMORY DEVICE

An on-die termination (ODT) circuit connected to an input buffer that receives a data signal, the ODT circuit includes at least one termination resistor connected to the input buffer and at least one switching device configured to control a connection between the termination resistor and the input buffer. The switching device is turned on or off according to information about the data signal. 1. An on-die termination circuit connected to an input buffer that receives a data signal , the on-die termination circuit comprising:at least one termination resistor connected to the input buffer; andat least one switching device configured to control a connection between the termination resistor and the input buffer;wherein the switching device is turned on or off according to information about the data signal,wherein the information about the data signal includes at least one of pattern information of the data signal, frequency information of the data signal, and length information of a channel through which the data signal is transmitted.2. The on-die termination circuit of claim 1 , wherein the switching device is turned on or off according to the pattern information of the data signal.3. The on-die termination circuit of claim 2 , wherein the pattern information of the data signal indicates a level change of the data signal claim 2 ,wherein the switching device is turned on when a level of the data signal changes and is turned off when the level of the data signal remains constant for a predetermined time.4. The on-die termination circuit of claim 1 , wherein the switching device is turned on or off according to a determination result after a predetermined delay interval.5. The on-die termination circuit of claim 4 , wherein the predetermined delay interval is changed based on the frequency information of the data signal or the channel length information.6. The on-die termination circuit of claim 5 , wherein the predetermined delay interval increases with respect to a ...

METHODS AND SYSTEMS FOR AVERAGING IMPEDANCE CALIBRATION

A semiconductor device also includes programmable termination components and a calibration circuit. The calibration circuit generates impedance calibration codes. The calibration circuit also calibrates impedance of the programmable termination components based on an average impedance calibration code of the impedance calibration codes. The semiconductor device further includes an averaging circuit that determines the average impedance calibration code of the impedance calibration codes. 1. A semiconductor device comprising:one or more programmable termination components; generate a plurality of impedance calibration codes based on a periodic supply voltage signal; and', 'calibrate impedance of the one or more programmable termination components based on an average impedance calibration code of the plurality of impedance calibration codes; and, 'a calibration circuit configured toan averaging circuit configured to determine the average impedance calibration code of the plurality of impedance calibration codes.2. The semiconductor device of claim 1 , wherein the calibration circuit is configured to calibrate the impedance of the one or more programmable termination components based on each impedance calibration code of the plurality of impedance calibration codes.3. The semiconductor device of claim 1 , wherein the one or more programmable termination components comprise a data output circuit of the semiconductor device.4. A system comprising:a controller; one or more programmable termination components;', generate a plurality of impedance calibration codes based on a periodic supply voltage signal in response to receiving a command signal from the controller; and', 'calibrate impedance of the one or more programmable termination components based on an average impedance calibration code of the plurality of impedance calibration codes; and, 'a calibration circuit configured to], 'a semiconductor device communicatively coupled to the controller, wherein the ...

SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME

The semiconductor memory device including a data strobe signal input buffer configured to receive a data strobe signal and generate an input data strobe signal, a data input buffer configured to receive data delayed by a first delay time compared to the data strobe signal and generate input data, a latency control signal generator configured to generate and activate a first on-die termination control signal during a first period in which the data strobe signal is applied in response to receiving a write command, a first on-die termination control circuit configured to vary a first variable resistance code in response to the first on-die termination control signal, and a data strobe signal termination circuit configured to terminate the data strobe signal and including a first on-die termination resistor, a resistance value of which varies in response to the first variable resistance code may be provided. 1. A semiconductor memory device comprising:a data strobe signal input buffer configured to receive a data strobe signal and generate an input data strobe signal;a data input buffer configured to receive data, which is delayed by a first delay time compared to the data strobe signal, and generate input data;a latency control signal generator configured to generate a first on-die termination control signal, which is activated during a first period in which the data strobe signal is applied, in response to receiving a write command;a first on-die termination control circuit configured to vary a first variable resistance code in response to the first on-die termination control signal;a data strobe signal termination circuit configured to terminate the data strobe signal, the data strobe signal termination circuit including a first on-die termination resistor, the first on-die termination resistor configured to vary a resistance value thereof in response to the first variable resistance code;a row decoder configured to decode a row address signal and generate a ...

CALIBRATION CIRCUIT FOR CONTROLLING RESISTANCE OF OUTPUT DRIVER CIRCUIT, MEMORY DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY DEVICE

A memory device includes a calibration circuit having a pull-up code generator including a pull-up resistor block and generating a pull-up code, and a pull-down code generator including a replica pull-up resistor block and a pull-down resistor block and generating a pull-down code, and an off chip driver/on die termination circuit providing a termination resistance having a resistance value set by the calibration circuit in a data reception operation and outputting data at an output strength set by the calibration circuit in a data output operation. In a calibration operation, a resistance value of the replica pull-up resistor block is adjusted to be less than a resistance value of the pull-up resistor block, and the pull-down code has a code value by which a resistance value of the pull-down resistor block corresponds to the resistance value of the replica pull-up resistor block. 1. A memory device comprising:a calibration circuit having a pull-up code generator comprising a pull-up resistor block and configured to generate a pull-up code, and a pull-down code generator comprising a replica pull-up resistor block and a pull-down resistor block and configured to generate a pull-down code; andan off chip driver (OCD)/on die termination (ODT) circuit configured to provide a termination resistance having a resistance value set by the calibration circuit in a data reception operation and to output data at an output strength set by the calibration circuit in a data output operation,wherein, in a calibration operation, a resistance value of the replica pull-up resistor block is adjusted to be less than a resistance value of the pull-up resistor block, and the pull-down code has a code value by which a resistance value of the pull-down resistor block corresponds to the resistance value of the replica pull-up resistor block.2. The memory device of claim 1 , whereinthe pull-up resistor block comprises at least one pull-up resistor set connected to a power source voltage, the ...

COMPENSATED IMPEDANCE CALIBRATION CIRCUIT

Aspects of the invention provide for compensating impedance calibration circuits. In one embodiment, a compensated impedance calibration circuit, includes: a variable resistor network including a tunable resistor and a fixed resistor; and an external resistance network including a target external precision resistor and a parasitic distribution resistance; wherein a resistance of the variable resistor network is proportional to a resistance of the external resistance network, such that a ratio of an output voltage of the variable resistor network to a power supply voltage is constant. 1. A compensated impedance calibration circuit , comprising:a variable resistor network including a tunable resistor and a fixed resistor; andan external resistance network including a target external precision resistor and a parasitic distribution resistance;wherein a resistance of the variable resistor network is proportional to a resistance of the external resistance network, such that a ratio of an output voltage of the variable resistor network to a power supply voltage is constant.2. The compensated impedance calibration circuit of claim 1 , wherein a value for the fixed resistor is selected from a range of discrete values.3. The compensated impedance calibration circuit of claim 1 , further comprising a voltage reference generator for generating a reference voltage.4. The compensated impedance calibration circuit of claim 3 , further comprising a comparator for comparing the reference voltage to the output voltage of the variable resistor network.5. The compensated impedance calibration circuit of claim 4 , further comprising control logic for receiving an output of the comparator and for tuning the variable resistor network claim 4 , such that the output voltage of the variable resistor network is equal to the reference voltage.6. The compensated impedance calibration circuit of claim 1 , wherein the fixed resistor is a pluggable on-chip resistor. The disclosure relates ...

SEMICONDUCTOR MEMORY DEVICE, A MEMORY MODULE INCLUDING THE SAME, AND A MEMORY SYSTEM INCLUDING THE SAME

A method of operating a memory controller includes: receiving a data signal from a memory device, wherein the data signal has an output high level voltage (VOH); determining a reference voltage according to the VOH; and comparing the data signal with the reference voltage to determine a received data value, wherein the VOH is proportional to a power supply voltage (VDDQ). 1. A method of operating a memory controller , comprising:receiving a data signal from a memory device, wherein the data signal has an output high level voltage (VOH);determining a reference voltage according to the VOH; andcomparing the data signal with the reference voltage to determine a received data value,wherein the VOH is proportional to a power supply voltage (VDDQ).2. The method of claim 1 , wherein the VOH has a value of VDDQ/2.5.3. The method of claim 1 , wherein the VOH has a value of VDDQ/3.4. The method of claim 1 , wherein a value of the VOH depends on a resistance of an on-die termination (ODT) resistor of the memory controller.5. The method of claim 4 , wherein the VOH has a value of VDDQ/2.5 when the ODT resistor is 80 claim 4 , 120 or 240 ohms.6. The method of claim 4 , wherein the VOH has a value of VDDQ/3 when the ODT resistor is 40 claim 4 , 60 claim 4 , 80 claim 4 , 120 or 240 ohms.7. The method of claim 1 , wherein the data signal is generated at the memory device in response to an instruction from the memory controller.8. The method of claim 7 , wherein the instruction includes information about the VOH.9. The method of claim 7 , wherein the instruction includes information about an on-die termination (ODT) resistor of the memory controller.10. The method of claim 7 , wherein the instruction causes a mode register set (MRS) signal to be generated by the memory device.11. The method of claim 10 , wherein the MRS signal varies according to the value of an on-die termination (ODT) resistor of the memory controller.12. The method of claim 1 , wherein a mode register in the ...

NONVOLATILE MEMORY DEVICES WITH ON DIE TERMINATION CIRCUITS AND CONTROL METHODS THEREOF

Non-volatile memory devices including on-die termination circuits connected to an input/output circuit and an on-die termination control logic detecting a preamble of a strobe signal based on a command and a control signal and activating the on-die termination within the preamble period. 136-. (canceled)37. A method of operating a nonvolatile memory device , comprising:receiving a write command via data input/output terminals in synchronization with a write enable signal while a command latch enable signal (CLE) is enabled;receiving an address via the data input/output terminals in synchronization with the write enable signal while an address latch enable signal (ALE) is enabled, wherein after the receiving the write command and the address, the CLE and the ALE is disabled;after the CLE and the ALE is disabled, activating an on-die termination mode of the data input/output terminals in response to a rising edge or a falling edge of a data strobe signal;receiving write data in synchronization with the data strobe signal; anddeactivating the on-die termination mode of the data input/output terminals in response to a transition of at least one of a chip enable signal, the ALE, and the CLE.38. The method of claim 37 , wherein before the receiving the write command or the address claim 37 , the chip enable signal is enabled.39. The method of claim 37 , wherein the activating the on-die termination mode of the data input/output terminals includes adjusting impedance of the data input/output terminals.40. The method of claim 37 , wherein the activating the on-die termination mode of the data input/output terminals includes activating a pseudo differential signaling mode of the data input/output terminals.41. The method of claim 40 , wherein the activating the on-die termination mode of the data input/output terminals includes activating a differential signaling mode of the data strobe signal.42. The method of claim 37 , further comprising:detecting a command attribute of ...

FAST VOLTAGE DOMAIN CONVERTERS WITH SYMMETRIC AND SUPPLY INSENSITIVE PROPAGATION DELAY

In one embodiment, a circuit comprises a phase interpolator that converts a single-ended input to a pair of symmetric differential signals within a first voltage domain. The circuit further comprises a comparator that converts the symmetric differential signals into single-ended output in a second different voltage domain. In one embodiment, the single ended output of the comparator is configured to be coupled to drive a switching driver in a switching regulator. In one embodiment, the interpolator comprises a first inverter, a second inverter, and a third inverter connected in series. The interpolator further comprises a first resistor and a second resistor connected in series. The second inverter provides a first output signal. Outputs of the first inverter and the third inverter are connected by the series connected resistors. A node between the resistors provides a second output signal. The first and second output signals are inverted and symmetric. 1. A level shifter comprising:a phase interpolator configured to convert a single-ended input to a pair of symmetric differential signals within a first voltage domain; anda comparator configured to convert the symmetric differential signals into a single-ended output in a second different voltage domain.2. The level shifter of wherein the single ended output of the comparator is configured to be coupled to drive a switching driver of a switching regulator.3. The level shifter of wherein the interpolator comprises a first inverter claim 1 , a second inverter and a third inverter connected in series claim 1 , and further comprises a first resistor and a second resistor connected in series claim 1 , the second inverter providing a first output signal claim 1 ,wherein the first resistor comprises an input terminal and an output terminal and the second resistor comprises an input terminal and an output terminal, andwherein output of the first inverter is connected to the input terminal of the first resistor and output of ...

TRANSMIT NOISE AND IMPEDANCE CHANGE MITIGATION IN WIRED COMMUNICATION SYSTEM

A method, system and circuit for providing for part or all of a transmitter, when it is in mute mode (not actively transmitting), to be turned off, removed, decoupled or modified in general in order to reduce the total noise submitted by the transmitter to the wired network into network controller. In parallel, an auxiliary circuit or impedance is added or coupled to the transmitter in order to mitigate the total return loss change of the transmitter. When in active transmitter mode, this auxiliary circuit or impedance will be removed or decoupled from the transmitter and transmitter will transmit in normal mode. 1. A method of mitigating transmit noise in a transmission system , comprising: coupling a first stage output to a second stage input; and', 'decoupling an auxiliary circuit from the second stage input to ground; and, 'in an active mode decoupling an output of the first stage to the second stage input; and', 'coupling the auxiliary circuit from the second stage input to ground., 'in a mute mode2. The method of wherein coupling and decoupling comprises using a member from the group consisting of hardware claim 1 , software claim 1 , and firmware.3. The method of further comprising operating the auxiliary circuit to mimic an impedance of a first amplifier of the first stage.4. The method of further comprising configuring the auxiliary circuit to comprise at least one member from the group consisting of a resistive component claim 1 , a capacitive component and a reactive component.5. The method of further comprising selecting the auxiliary circuit based on a frequency range.6. The method of further comprising selecting the auxiliary circuit by circuit simulation or by measurement.7. The method of further comprising synthesizing the auxiliary circuit to achieve a small mismatching error.8. The method of further comprising operating a plurality of active and mute transmitters.9. A method of mitigating effects of an impedance change in a transmission system ...

Active Low-Power Termination

An active termination circuit comprising an input node connected to a transmission line, a first transistor, and a second transistor. The transmission line supplies a signal to the input node. The first transistor is diode connected between a high voltage supply and the input node. The first transistor terminates the signal when the signal is at a low logic level. The second transistor is diode connected between the input node and a low voltage supply. The second transistor terminates the signal when the signal is at a high logic level.

SEMICONDUCTOR DEVICE AND MEMORY DEVICE

A semiconductor device of an embodiment includes a buffer configured to perform data transmission by turning on and off a first output transistor group and a second output transistor group; a first correction circuit configured to calibrate a resistance value of the buffer by controlling an on-off state of each of first transistors of the first output transistor group; a second correction circuit configured to calibrate the resistance value of the buffer by controlling an on-off state of each of second transistors of the second output transistor group; and a control circuit configured to cause the calibration by the first correction circuit to be performed in a non-communication duration other than a duration of data transmission from the buffer and cause the calibration by the second correction circuit to be performed in a duration other than a duration of the calibration by the first correction circuit. 1. A semiconductor device comprising:a buffer configured to perform data transmission by turning on and off a first output transistor group and a second output transistor group;a first correction circuit including the first output transistor group and configured to calibrate a resistance value of the buffer by controlling an on-off state of each of first transistors of the first output transistor group;a second correction circuit including the second output transistor group and configured to calibrate the resistance value of the buffer by controlling an on-off state of each of second transistors of the second output transistor group; anda control circuit configured to cause the calibration by the first correction circuit to be performed in a non-communication duration other than a duration of data transmission from the buffer and cause the calibration by the second correction circuit to be performed in a duration other than a duration of the calibration by the first correction circuit.2. The semiconductor device according to claim 1 , whereinthe first correction ...

SEMICONDUCTOR DEVICE AND MEMORY SYSTEM

A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal. 1. A semiconductor device configured to communicate with a controller , the semiconductor device comprising:a first chip that includes a first circuit having a first output terminal; anda second chip that includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line, whereinupon receipt of a first command, the first circuit calibrates an output impedance at the first output terminal through a first calibration operation,upon receipt of a second command after the first calibration operation is performed, the second circuit calibrates an output impedance at the second output terminal through a second calibration operation based on the output impedance at the first output terminal, anda duration of the second calibration operation is shorter than a duration of the first calibration operation.2. The semiconductor device according to claim 1 , whereinthe first chip transmits to the controller a signal indicating that the first chip is in a busy state upon starting the first calibration operation, and transmits to the controller a signal indicating that the first chip is in a ready state upon completion of the first calibration operation, andthe second chip transmits to the controller a signal indicating that the second chip is in the busy state upon starting the second calibration operation, and transmits to the controller a signal indicating that the second ...

Buffered memory module having multi-valued on-die termination

In a memory module having an integrated-circuit buffer device coupled to one or more integrated-circuit memory devices, the buffer device receives write data signals from an external control component via a set of data inputs, the write data signals indicating write data to be stored within one or more of the memory devices. Logic within the buffer device sequentially applies controllable termination impedance configurations at the data inputs based on an indication received from the control component and an internal state of the buffer device, applying a first controllable termination impedance configuration at each of the data inputs during a first internal state of the buffer device corresponding to the reception of the write data signals on the data inputs, and applying a second controllable termination impedance configuration at each of the data inputs during a second internal state of the buffer device that succeeds the first internal state.

SEMICONDUCTOR DEVICE HAVING IMPEDANCE CALIBRATION FUNCTION TO DATA OUTPUT BUFFER AND SEMICONDUCTOR MODULE HAVING THE SAME

A method for calibrating an output buffer including adjusting a first impedance code applied to a first plurality of first transistor units connected in parallel between a calibration terminal and a first power supply potential so that the potential on the calibration terminal substantially equals a reference potential, applying the first impedance code to a second plurality of first transistor units connected in parallel between a node and the first power supply potential, adjusting a second impedance code applied to a second transistor unit connected between the node and a second power supply potential so that the potential on the node substantially equals the reference potential, applying the first impedance code to a third plurality of first transistor units connected in parallel between a data terminal and the first power supply potential, and applying the second impedance code to a fourth plurality of second transistor units. 1. A method for calibrating an output buffer , the method comprising:adjusting a first impedance code applied to a first plurality of first transistor units connected in parallel between a calibration terminal and a first power supply potential so that the potential on the calibration terminal substantially equals a reference potential;applying the first impedance code to a second plurality of first transistor units connected in parallel between a node and the first power supply potential;adjusting a second impedance code applied to a second transistor unit connected between the node and a second power supply potential so that the potential on the node substantially equals the reference potential;applying the first impedance code to a third plurality of first transistor units connected in parallel between a data terminal and the first power supply potential; andapplying the second impedance code to a fourth plurality of second transistor units connected in parallel between the data terminal and the second power supply potential,wherein ...

SIGNAL RECEIVING CIRCUITS INCLUDING TERMINATION RESISTANCE HAVING ADJUSTABLE RESISTANCE VALUE, OPERATING METHODS THEREOF, AND STORAGE DEVICES THEREWITH

A receiving circuit includes a termination resistance circuit and a resistance adjustment circuit. The termination resistance circuit is configured to receive a first differential signal via a first input terminal and a second differential signal via a second input terminal, and to be selectively connected to the first and second input terminals. The termination resistance circuit has an adjustable resistance value. The resistance adjustment circuit is configured to decrease the resistance value of the termination resistance circuit in response to a signal reception preparation command and connection of the termination resistance circuit to the first and second input terminals. 1. A receiving circuit configured to receive a differential signal , the receiving circuit comprising:a termination resistance circuit connected between a first input terminal and a second input terminal, the termination resistance circuit having a resistance value that is adjustable between a first resistance value and a second resistance value, the second resistance value being less than the first resistance value;a switching circuit configured to control a connection between the termination resistance circuit and each of the first and second input terminals; anda resistance adjustment circuit configured to adjust the resistance value of the termination resistance circuit from the first resistance value to the second resistance value when the termination resistance circuit is disconnected from at least one of the first and second input terminals, and then connected to the first and second input terminals by the switching circuit.2. The receiving circuit of claim 1 , further comprising:the first and second input terminals configured to transmit the received differential signal.3. The receiving circuit of claim 1 , wherein the switching circuit is configured to connect the termination resistance circuit to the first and second input terminals in response to a signal reception preparation ...

ELECTRONIC DEVICES EXECUTING A TERMINATION OPERATION

An electronic device includes a termination control circuit and a data input/output (I/O) circuit. The termination control circuit is configured to generate a termination enablement signal which is activated during a termination operation period for activating a termination resistor while a write operation is performed. In addition, the termination control circuit is configured to adjust a period that the termination enablement signal is activated according to whether a write command is inputted to the termination control circuit during a set detection period of the write operation. The data I/O circuit is configured to receive data by activating the termination resistor during a period that the termination enablement signal is activated when the write operation is performed. 1. An electronic device comprising:{'claim-text': ['generate a termination enablement signal which is activated during a termination operation period for activating a termination resistor while a write operation is performed; and', 'adjust a period that the termination enablement signal is activated according to whether a write command is inputted to the termination control circuit during a set detection period of the write operation; and'], '#text': 'a termination control circuit configured to:'}a data input/output (I/O) circuit configured to receive data by activating the termination resistor during a period that the termination enablement signal is activated when the write operation is performed.2. The electronic device of claim 1 ,wherein the set detection period is set as a period from a point in time when the write command for the write operation is activated until a point in time when an internal termination-off signal is activated during the write operation; andwherein the internal termination-off signal is generated by delaying a write signal, which is generated based on the write command for the write operation, by a period including a write latency period and a burst length period.3. ...

SEMICONDUCTOR STORAGE DEVICE

A semiconductor storage device including an output pad, a first circuit connected to the output pad, a second circuit connected to the first circuit, a third circuit configured to output a first setting signal for controlling the first circuit accordance with a characteristic variation of the first circuit, and a fourth circuit configured to generate a second setting signal for controlling the second circuit in accordance with the first setting signal received from the third circuit and output the second setting signal to the second circuit. 1. A semiconductor storage device comprising:an output pad;a first circuit connected to the output pad;a second circuit connected to the first circuit;a third circuit configured to output a first setting signal for controlling the first circuit accordance with a characteristic variation of the first circuit; anda fourth circuit configured to generate a second setting signal for controlling the second circuit in accordance with the first setting signal received from the third circuit and output the second setting signal to the second circuit.2. The semiconductor storage device according to claim 1 , wherein the second circuit controls the first circuit.3. The semiconductor storage device according to claim 1 , whereinthe first setting signal adjusts an output resistance of the first circuit, andthe second setting signal adjusts an output timing of the first circuit.4. The semiconductor storage device according to claim 1 , further comprising a temperature sensor claim 1 ,wherein the fourth circuit adjusts the second setting signal based on information related to a temperature output from the temperature sensor.5. The semiconductor storage device according to claim 1 , further comprising a detection circuit configured to detect a supply voltage claim 1 , a voltage having the same magnitude with the supply voltage being supplied to the first circuit claim 1 ,wherein the fourth circuit adjusts the second setting signal based on ...

ASYMMETRICAL I/O STRUCTURE

An asymmetrical I/O structure is provided. In one embodiment, the asymmetrical I/O structure comprises a first power supply node connected to a first voltage, a second power supply node connected to a second voltage, a pull-up unit and a pull-down unit which are connected between the first power supply node and the second power supply node. The first voltage is higher than the second voltage. A node between the pull-up unit and the pull-down unit is connected to an I/O node. The pull-up unit comprises one or more pull-up transistors, and the pull-down unit comprises one or more pull-down transistors. The number of the pull-up transistors is different from the number of the pull-down transistors. 1. An asymmetrical I/O structure , comprising:a first power supply node connected to a first voltage and a second power supply node connected to a second voltage;a pull-up unit and a pull-down unit which are connected between the first power supply node and the second power supply node, wherein a node between the pull-up unit and the pull-down unit is connected to an I/O node;wherein the pull-up unit comprises one or more pull-up transistors, the pull-down unit comprises one or more pull-down transistors, and the number of the pull-up transistors is different from the number of the pull-down transistors, and the first voltage is higher than the second voltage.2. The asymmetrical I/O structure of claim 1 , wherein the pull-up unit comprises a first pull-up transistor claim 1 , the pull-down unit comprises a first pull-down transistor and a second pull-down transistor connected in series claim 1 , wherein the pull-up transistor is a PMOS transistor and the pull-down transistors are NMOS transistors.3. The asymmetrical I/O structure of claim 2 , wherein claim 2 ,a source of the first pull-up transistor is connected to the first power supply node, a drain of the first pull-up transistor is connected to the I/O node, a gate of the first pull-up transistor is connected to an ...

UNIFORMITY BETWEEN LEVELS OF A MULTI-LEVEL SIGNAL

Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify peak-to-peak voltage differences between the amplitudes of data transmitted using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data. 1. An apparatus , comprising:a multi-leg driver that comprises a first plurality of legs coupled with a first resistive component and a second plurality of legs coupled with a second resistive component, wherein the first plurality of legs is configured to output first data that includes multiple bits and the second plurality of legs is configured to output second data that includes multiple bits;a transmitter coupled with the first resistive component and the second resistive component of the multi-leg driver, the transmitter being configured to transmit the first data and the second data;a controller coupled with the multi-leg driver, the controller being configured to determine an output impedance offset between the first transmitted data and the second transmitted data; anda first transistor coupled with the transmitter, the first transistor configured to adjust a resistance level of at least one of the first plurality of legs based at least in part on the controller determining the output impedance offset between the first transmitted data and the second transmitted data.2. The apparatus of claim 1 , further comprising:a second transistor coupled with the transmitter, the second transistor being configured to adjust a resistance level of at least one of the second plurality of legs in response to the determination.3. The apparatus of claim 2 , wherein ...

DIAGNOSTIC MONITORING FOR ANALOG-TO-DIGITAL CONVERTERS

The present disclosure describes a channel selector for use in an analog-to-digital converter that has a sampling circuit for converting an analog input to a digital output within a fault tolerance range. The channel selector includes a reception channel, a diagnostic channel, and an impedance compensator. The reception channel receives an analog signal for delivery to the sampling circuit when it is selected for coupling with the sampling circuit. The diagnostic channel receives a diagnostic signal for verifying the digital output of the sampling circuit when it is selected for coupling with the sampling circuit. The impedance compensator is configured to offset a high channel impedance of the reception channel based on the fault tolerance range of the sampling circuit and when the diagnostic channel is selected. 1. An analog-to-digital converter (ADC) , comprising:a sampling circuit having a fault tolerance range; and a reception channel having a channel impedance;', 'a diagnostic channel;', 'a switch coupled with the reception channel and the diagnostic channel, and configured to select the reception channel or the diagnostic channel for the sampling circuit; and', 'an impedance compensator coupled with the switch, the impedance compensator having a compensatory impedance equal to or greater than a product of the channel impedance and the fault tolerance range., 'a channel selector having2. The ADC of claim 1 , wherein the impedance compensator is coupled in series between the switch and the sampling circuit.3. The ADC of claim 1 , wherein the impedance compensator is coupled in series between the diagnostic channel and the switch.4. The ADC of claim 1 , wherein the impedance compensator is configured to offset the channel impedance of the reception channel based on the fault tolerance range of the sampling circuit and when the diagnostic channel is selected.5. The ADC of claim 1 , wherein:the reception channel includes a first reception channel and a second ...

CALIBRATION CIRCUIT FOR ON-CHIP DRIVE AND ON-DIE TERMINATION

Calibration circuits and methods to set an on-chip impedance to match a target impedance where the reference voltage does not equal one-half of the positive power supply voltage Vddq are described. In particular, calibration circuits and methods are provided to enable accurate impedance matching at a reference voltage Vref of K*Vddq, where K is a number between 0 and 1. In some embodiments, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed current mirror. In another embodiment, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed mirror pull-up circuit. In yet another embodiment, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed target impedance. 1. A calibration circuit for setting an on-chip impedance of an integrated circuit to match a target impedance comprising:a first pull-up circuit connected in series with the target impedance between a positive power supply voltage and a reference power supply voltage, the first pull-up circuit being a ratioed pull-up circuit sized to be K/(1−K) times a size of a pull-up circuit unit, K being a number between 0 and 1, other than 0.5, and the positive power supply voltage being a positive power supply voltage for input-output circuits of the integrated circuit;a first comparator configured to compare a voltage at a first common node between the first pull-up circuit and the target impedance to a reference voltage and to generate an output signal to drive the first pull-up circuit so that the voltage at the first common node equals the reference voltage, the reference voltage being K times the positive power supply voltage other than one-half the positive power supply voltage, wherein the first pull-up circuit has an impedance being set equal to (1−K)/K times the target impedance;a second pull-up circuit connected in series with a pull-down circuit between the positive power supply voltage and the ...

CURRENT LIMITING I/O INTERFACE AND ISOLATED LOAD SWITCH DRIVER IC

Disclosed examples include isolated load switch driver circuits to drive a load, including an impedance circuit that receives a digital input voltage signal from a signal source, and selectively allows a current signal to flow from the signal source to charge a buffer capacitor. An impedance control circuit controls the impedance circuit to limit the current signal in response to the buffer capacitor reaching a first threshold voltage, and an output circuit provides an output isolated from the digital input voltage signal to switch the load. A signaling circuit selectively enables the output circuit to draw power from the buffer capacitor in response to the voltage of the buffer capacitor reaching the first threshold voltage. 1. An integrated circuit (IC) , comprising:a first input pin having a reference voltage;a second input pin to receive a digital input voltage signal having a first voltage relative to the reference voltage in a first state, and a different second voltage relative to the reference voltage in a second state; an impedance circuit, including an input connected to the second input pin, and an output to deliver a current signal to a buffer capacitor, the impedance circuit operative in a first mode to connect the second input pin to the buffer capacitor, and in a second mode to provide a controlled impedance between the second input pin and the buffer capacitor to limit an amplitude of the current signal,', 'a precharge circuit to provide a first signal in response to a supply voltage across the buffer capacitor reaching a first threshold voltage, and', 'an impedance connection control circuit to switch the impedance circuit from the first mode to the second mode in response to the first signal;, 'a current limiter circuit, includingan output circuit, including an input connected to the buffer capacitor to receive the supply voltage, and an output isolated from the supply voltage, the output being connected to third and fourth pins of the IC; anda ...

CURRENT LIMITING I/O INTERFACE AND ISOLATED LOAD SWITCH DRIVER IC

Disclosed examples include isolated load switch driver circuits to drive a load, including an impedance circuit that receives a digital input voltage signal from a signal source, and selectively allows a current signal to flow from the signal source to charge a buffer capacitor. An impedance control circuit controls the impedance circuit to limit the current signal in response to the buffer capacitor reaching a first threshold voltage, and an output circuit provides an output isolated from the digital input voltage signal to switch the load. A signaling circuit selectively enables the output circuit to draw power from the buffer capacitor in response to the voltage of the buffer capacitor reaching the first threshold voltage. 1. An isolated load switch driver circuit , comprising:a signal input to receive a digital input voltage signal;an output circuit to provide a digital output voltage signal isolated from the digital input voltage signal;a buffer capacitor having a first terminal connected to a reference voltage and a second terminal;current limiter circuit, including first and second transistors connected in a back-to-back configuration between the signal input and the second terminal of the buffer capacitor; a first output to provide a first signal to a control terminal of the first transistor to turn the first transistor on in response to the digital input voltage signal transitioning from the reference voltage to a second voltage, and', 'a second output to provide a second signal to a control terminal of the second transistor to turn the second transistor on in response to the digital input voltage signal transitioning from the reference voltage to the second voltage until a voltage of the second terminal of the buffer capacitor reaches a first threshold voltage; and, 'a first control circuit, includinga second control circuit to provide a third signal to the control terminal of the second transistor to limit an amplitude of a current signal flowing from the ...

Memory modules, memory systems including the same, and methods of calibrating multi-die impedance of the memory modules

A memory module includes an external resistor and a plurality of memory devices commonly connected to the external resistor. Each of the memory devices includes a first reception pad and a first transmission pad. The first reception pad is associated with receiving an impedance calibration command and the first transmission pad is associated with transmitting the impedance calibration command. Each of the memory devices transfers the impedance calibration command to a first memory device which is selected as a master among the plurality of memory devices through a ring topology. The first memory device performs an impedance calibration operation, determines a resistance and a target output high level voltage of an output driver in response to the impedance calibration command, and transfers the impedance calibration command to a second memory device after performing the impedance calibration operation.

ON-DIE TERMINATION CONTROL

A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs. 120-. (canceled)21. A dynamic random access memory (DRAM) component comprising:a storage register; one or more commands that specify storage of a digital control value within the storage register, the digital control value specifying a termination impedance;', 'a write command; and', 'a chip-select signal indicating that the DRAM component is to receive write data associated with the write command;, 'a first interface to receivea second interface to receive the write data during a given time; and couple to the second interface, prior to the given time and responsive to the chip-select signal and the write command, one or more termination elements having the termination impedance specified by the digital control value, and', 'decouple the one or more termination elements from the second interface at conclusion of the given time, after the write data has been received via the second interface., 'control circuitry to22. The DRAM component of wherein the control circuity comprises state circuitry that transitions to a data-write operating state in response to the write command and the chip-select signal claim 21 , and wherein the given time corresponds to a time period in which the state circuitry remains in the data-write operating state.23. The DRAM component of wherein:the first interface is further to receive a read command;the state ...

Driving integrated circuit

A driving integrated circuit (IC) is disclosed. The driving IC comprises a signal processing circuit, a receiver and a terminal resistance providing circuit. The receiver is coupled to a first transmission line and a second transmission line and is output to the signal processing circuit after receiving a transmission signal through the first transmission line and the second transmission line. The terminal resistance providing circuit is coupled to the receiver.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM

A semiconductor system may include a first semiconductor device configured to output a test stop signal and a calibration control signal. The semiconductor system may include a second semiconductor device configured to generate a first state code from an external resistor, a second state code from an internal resistor, and a third state code from a fuse array in response to the calibration control signal, and to select one of the first to third state codes as a selection code in response to the test stop signal and the calibration control signal. 1. A semiconductor system comprising:a first semiconductor device configured to output a test stop signal and a calibration control signal; anda second semiconductor device configured to generate a first state code from an external resistor, a second state code from an internal resistor, and a third state code from a fuse array in response to the calibration control signal, and to select one of the first to third state codes as a selection code in response to the test stop signal and the calibration control signal.2. The semiconductor system of claim 1 , wherein the second semiconductor device includes a pad coupled to the external resistor.3. The semiconductor system of claim 2 , wherein the second semiconductor device comprises:a state code generation unit configured to compare a reference voltage generated in response to the calibration control signal with a voltage of the pad to generate a driving code for driving the voltage of the pad and a voltage of an internal node, and to compare the voltage of the internal node with the reference voltage to generate the first state code for driving the voltage of the internal node.4. The semiconductor system of claim 3 , wherein the state code generation unit comprises:a first comparator configured to compare the reference voltage with the voltage of the pad to generate the driving code; anda first pull-up driving section configured to pull-up drive the voltage of the pad in ...

SEMICONDUCTOR DEVICE INCLUDING BUFFER CIRCUIT

A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals. 1. An apparatus , comprising:a power supply line;an output terminal;a circuit configured to receive a plurality of first control signals and a data signal, the circuit configured to provide a first portion of the plurality of first control signals and further configured to provide a selection signal based on the data signal;a driver coupled between the power supply line and the output terminal, the driver configured to receive the selection signal and the first portion of the plurality of first control signals.2. The apparatus of claim 1 , wherein the circuit comprises a buffer configured to receive the data signal claim 1 , to buffer the received data signal claim 1 , and further configured to provide the buffered data signal as the selection signal.3. The apparatus of claim 1 ,wherein the driver includes first and second transistors coupled in series between the power supply line and the output terminal,wherein the first transistor between the output terminal and the second transistor comprises a control gate configured to receive the selection signal, andwherein the second transistor comprises a control gate configured to receive one of the first portion of the plurality of first control signals.4. The apparatus of claim 3 , wherein the driver further includes a third transistor ...

Analog Signal Compatible CMOS Switch as an Integrated Peripheral to a Standard Microcontroller

At least one analog signal compatible complementary metal oxide semiconductor (CMOS) switch circuit is incorporated with digital logic circuits in an integrated circuit. The integrated circuit may further comprise a digital processor and memory, e.g., microcontroller, microprocessor, digital signal processor (DSP), programmable logic array (PLA), application specific integrated circuit (ASIC), etc., for controlling operation of the at least one analog signal compatible CMOS switch for switching analog signals, e.g., audio, video, serial communications, etc. The at least one analog signal compatible CMOS switch may have first and second states, e.g., single throw “on” or “off”, or double throw common to a or b, controlled by a single digital control signal of either a logic “0” or a logic “1”. 1. An microcontroller , comprising:a plurality of external input/output connection;a digital processor;a memory coupled to the digital processor; andat least one analog signal compatible complementary metal oxide semiconductor (CMOS) switch coupled to and controlled by the digital processor, and configured to switch signals through a first and a second external input/output connection of said plurality of external input/output connections, wherein the at least one analog signal compatible CMOS switch comprises a first switching node coupled with the first external input/output connection of said plurality of external input/output connections and a second switching node coupled with the second external input/output connection of said plurality of external input/output connections, andwherein the at least one analog signal compatible CMOS switch providesa low impedance between the first external input/output connection and the second external input/output connection when the digital processor asserts a control signal at a first logic level thereto, anda high impedance between the first external input/output connection and the second external input/output connection when the ...

IMPEDANCE CALIBRATION DEVICE AND METHOD THEREOF

An impedance calibration device provided includes a timing device, a first transmitter, a first variable resistor, a second variable resistor and a first receiver. The first variable resistor is used to receive a first adjustment code. The second variable resistor is used to receive a second adjustment code. The first receiver generates a first contact digital signal according to a first contact voltage. The first receiver generates a first terminate digital signal according to a first terminate voltage and the first adjustment code. The first receiver generates a first load digital signal according to a load voltage and the second adjustment. The timing device dynamically adjust the first adjustment code and the second adjustment code according to the first contact digital signal, the first terminate digital signal and the first load digital signal. 1. An impedance calibration device having a timing device , a first channel , a first switch , a first contact resistor and a load resistor , the timing device being coupled to the first channel , the load resistor having an end coupled to an end of the first switch , the load resistor having an uncoupled end connected to ground , the first switch having an uncoupled end coupled to an end of the first contact resistor and the first switch having a load voltage , the impedance calibration device comprising:a first transmitter;a first variable resistor having an end coupled to the first transmitter and having a first terminate voltage, the first variable resistor being used to receive a first adjustment code, the first contact resistor having an uncoupled end coupled to an uncoupled end of the first variable resistor and having a first contact voltage; anda first receiver having a first input terminal, a second input terminal, a third input terminal and a first output terminal, the first input terminal being coupled to an end of a second switch, the second switch having an uncoupled end connected to the first terminate ...

LOW POWER DRIVER WITH PROGRAMMABLE OUTPUT IMPEDANCE

A low power programmable driver includes a first driver output, a first programmable driver leg and a second programmable driver leg. The first programmable driver leg has a pull-up half and a pull-down half. The pull-up half is electrically coupled between a supply voltage and the first driver output. The pull-up half is electrically coupled to receive a signal and a first control signal. The pull-down half is electrically coupled between an internal ground and the first driver output. The pull-down half is electrically coupled to receive an inversion of the signal and the first control signal. A second programmable driver leg has a pull-up half and a pull-down half. The pull-up half is electrically coupled between the supply voltage and the first driver output. The pull-up half is electrically coupled to receive the signal and a second control signal. The pull-down half is electrically coupled between the internal ground and the first driver output. The pull-down half is electrically coupled to receive the inversion of the signal and the second control signal. The first programmable driver leg contributes to a termination impedance of the driver when the first control signal is high and does not contribute to the termination impedance when the first control signal is low. The second programmable driver leg contributes to the termination impedance of the driver when the second control signal is high and does not contribute to the termination impedance when the second control signal is low. 1. A programmable low power driver , comprising:a first driver output;a first programmable driver leg having a pull-up half and a pull-down half, the pull-up half is electrically coupled between a supply voltage and the first driver output, the pull-up half is electrically coupled to receive a signal and a first control signal, the pull-down half is electrically coupled between an internal ground and the first driver output, the pull-down half is electrically coupled to receive ...

METHOD AND APPARATUS FOR DYNAMIC MEMORY TERMINATION

Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level. 117-. (canceled)18. An apparatus comprising:an interface operable to access a memory, the memory comprising a register to store a termination impedance setting for termination of an input-output (I/O) interface of the memory; and send a signal to set a default termination impedance value with the termination impedance setting of the register, wherein the default termination impedance value to be applied to the I/O interface in response to de-assertion of a termination signal to activate termination of the I/O interface of the memory, and', 'send a termination signal to switch from the default termination impedance value to a different termination impedance value for the I/O interface of the memory, wherein the default termination impedance value and the different termination impedance value are both finite values., 'a logic unit operable to'}19. The apparatus of claim 18 , wherein the I/O interface of the memory comprises a Double Data Rate 4 (DDR4) interface of the memory.20. The apparatus of claim 18 , wherein the memory comprises a Dynamic Random Access Memory (DRAM).21. The apparatus of claim 18 , wherein the memory resides in a memory module which is a Dual In-Line Memory Module (DIMM) with one or more Dynamic Random Access Memories (DRAMs).22. The apparatus of claim 18 , wherein the termination signal is to cause at ...

Integrated circuit device with programmable analog subsystem

An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, and at least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC device to the analog blocks, the analog MUX including at least one low noise signal path pair having a lower resistance than other signal paths of the analog MUX; at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; a digital section comprising digital circuits; and a processor interface coupled to the analog blocks.

Systems and methods for impedance calibration of a semiconductor device

Systems and methods for performing an efficient ZQ calibration are provided herein. The described techniques use non-linearity compensation circuitry configured to compensate for a non-linear relationship between variation in a plurality of ZQ calibration codes and corresponding resistance variations, by adjusting either: a magnitude of the adjustment to the calibration step, the ZQCODE to an alternative ZQCODE, or both the magnitude of the adjustment to the calibration step and the ZQCODE to the alternative ZQCODE.

CALIBRATION CIRCUIT AND CALIBRATION APPARATUS INCLUDING THE SAME

A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching. 1. A system comprising:a first semiconductor device;a second semiconductor device;a third semiconductor device; anda fourth semiconductor device,wherein the first semiconductor device to the fourth semiconductor device configured to share a resistor for impedance matching,wherein first semiconductor device to the fourth semiconductor device are coupled to have a chain shape,wherein the forth semiconductor device generate a completion signal when performance is completed and the first semiconductor device receive the completion signal provided from the fourth semiconductor device.2. The semiconductor device according to claim 1 , wherein at least one of the first semiconductor device to the fourth semiconductor device includes a volatile memory and at least one of the first semiconductor device to the fourth semiconductor device includes a non-volatile memory.3. The semiconductor device according to claim 1 , wherein each semiconductor device comprises:a first calibration driver configured to, based on a first calibration enable signal, perform an impedance matching operation according to the resistor, anda signal generator configured to generate a completion signal when performance is completed.4. A system comprising:a first semiconductor device to an eighth semiconductor device,wherein the first ...

I/O BUFFER OFFSET MITIGATION

Memory including an array of memory cells might include an input buffer having calibration circuitry, a first input, a second input, and an output; and calibration logic having an input selectively connected to the output of the input buffer and comprising an output connected to the calibration circuitry, wherein the calibration logic is configured to cause the memory to determine whether the input buffer exhibits offset while a particular voltage level is applied to the first and second inputs of the input buffer, and, in response to determining that the selected input buffer exhibits offset, apply an adjustment to the calibration circuitry while the particular voltage level is applied to the first and second inputs until a logic level of the output of the selected input buffer transitions. 1. A memory , comprising:an array of memory cells;an input buffer comprising calibration circuitry, a first input, a second input, and an output configured for providing signals for use in storing data to the array of memory cells; andcalibration logic comprising an input selectively connected to the output of the input buffer, and comprising an output connected to the calibration circuitry of the input buffer; determine whether the input buffer exhibits offset while a particular voltage level is applied to the first input of the input buffer and to the second input of the input buffer; and', 'in response to determining that the input buffer exhibits offset, apply an adjustment to the calibration circuitry while the particular voltage level is applied to the first input of the input buffer and to the second input of the input buffer until a logic level of the output of the input buffer transitions., 'wherein the calibration logic is configured to cause the memory to2. The memory of claim 1 , wherein the calibration circuitry comprises:a first variable current device connected to a first current path of the input buffer regulated by the first input of the input buffer; anda ...

INTEGRATED CIRCUIT AND OPERATION METHOD THEREOF

An integrated circuit of a multiple die package structure having a plurality of semiconductor devices, each of the plurality of semiconductor devices may include an active termination circuit configured to perform an active termination operation to the semiconductor device, and to be turned off in a disable state of an active termination setting code, a multiple die package information transfer unit configured to transfer a multiple die package information signal, and a compulsory termination unit configured to selectively convert the active termination setting code into the disable state in response to the multiple die package information signal. 1. An integrated circuit of a multiple die package structure having a plurality of semiconductor devices , each of the plurality of semiconductor devices comprising:an active termination circuit configured to perform an active termination operation to the semiconductor device, and to be turned off according to a disable state of an active termination setting code;a multiple die package information transfer unit configured to transfer a multiple die package information signal; anda compulsory termination unit configured to selectively convert the active termination setting code into the disable state in response to the multiple die package information signal.2. The Integrated circuit of claim 1 , wherein the active termination setting code indicates the disable state when the active termination setting code is set to a predetermined value.3. The Integrated circuit of claim 2 , wherein the compulsory termination unit converts the active termination setting code into the predetermined value in response to an enable state of the multiple die package information signal.4. The integrated circuit of claim 1 , wherein the multiple die package information signal transfer unit outputs the multiple die package information signal as a signal claim 1 , which is applied from a predetermined pad.5. The integrated circuit of claim 1 , ...

MEMORY WITH TERMINATION CIRCUIT

A semiconductor integrated circuit is described. A transmitter-receiver transmits and receives data to and from outside by a first external terminal and transmits a first control signal by a second external terminal. When another data is transmitted after the data is transmitted and when a data transmission interval from a time when the data is transmitted to a time when the another data is transmitted is equal to or smaller than a first threshold, the transmitter-receiver continuously outputs, from the first external terminal, a potential level of about 1/2 of a potential level obtained by adding a first potential level and a second potential level, during the data transmission interval, and changes the second potential level of the first control signal to the first potential level when the data transmission interval exceeds the first threshold. 1. A semiconductor integrated circuit system , comprising: a first transmitter-receiver;', 'a second termination circuit; and', 'a second transmitter-receiver, wherein, 'a first termination circuit;'}when transmitted data from the second transmitter-receiver is received by the first transmitter-receiver, the second termination circuit is inactivated,when the data is transmitted to the second transmitter-receiver by the first transmitter-receiver, the second termination circuit is activated, and when a data transmission interval from a time when the data is transmitted to a time when the another data is transmitted is equal to or smaller than a first threshold, the activation of the second termination circuit is maintained, and', 'when the data transmission interval exceeds the first threshold, the second termination circuit is inactivated., 'when another data is transmitted from the first transmitter-receiver to the second transmitter-receiver after the data is transmitted from the first transmitter-receiver to the second transmitter-receiver,'}2. The semiconductor integrated circuit system according to claim 1 , wherein ...

Driver for a shared bus, in particular a lin bus

A driver for a shared bus, such as a LIN bus, having a supply node (Vbat), a bus node (LIN), a transmit data input node (TX) and a receive data output node (RX), said driver comprising: a pull-up circuitry between the supply node and the bus node, driver circuitry (100) having a control input connected to the transmit data input node, feedback circuitry (200) configured to provide feedback from the shared bus to the control input of the driver circuitry; said feedback circuitry comprising copy circuitry (210) configured to obtain at least one copy signal representative for a signal on the bus node, filter circuitry (220) configured to low-pass filter the at least one copy signal, derivative circuitry (230) configured to obtain at least one derivative signal representative for the speed at which the signal on the bus node varies.

MATRIX MATCHING CROSSTALK REDUCTION DEVICE AND METHOD

This disclosure relates generally to devices, systems, and methods that include conductive lines configured to transmit electrical signals between a first electronic component and a second electronic component between which the conductive lines are coupled. The devices, systems, and methods further include a transmitter, configured to generate the electrical signals, the transmitter including a source impedance based, at least in part, on a resistive coupling between individual ones of the conductive lines, a source impedance matrix of the source impedance being substantially proportional to the characteristic impedance matrix of the plurality of conductive lines. 1. An electrical circuit , comprising:a plurality of conductive lines configured to transmit electrical signals between a first electronic component and a second electronic component between which the plurality of conductive lines are coupled;a transmitter, configured to generate the electrical signals, the transmitter including a source impedance based, at least in part, on a resistive coupling between individual ones of the plurality of conductive lines, a source impedance matrix of the source impedance being substantially proportional to a characteristic impedance matrix of the plurality of conductive lines.2. The electrical circuit of claim 1 , wherein the characteristic impedance matrix is approximately equal to the source impedance matrix of the transmitter.3. The electrical circuit of claim 1 , wherein the resistive coupling comprises resistive coupling elements claim 1 , wherein each one of the resistive coupling elements is coupled between individual ones of the plurality of conductive lines.4. The electrical circuit of claim 3 , wherein each of the resistive coupling elements corresponds to one pair of the plurality of conductive lines and each pair of the plurality of conductive lines corresponds to one of the resistive coupling elements.5. The electrical circuit of claim 3 , wherein the ...

OPERATING METHOD OF INPUT/OUTPUT INTERFACE

A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal. 1. A method of operating an input/output interface comprising:selecting, by an output block of the input/output interface, one of a plurality of output driver circuits according to a mode selection signal, the mode selection signal being a control signal for controlling an on-die termination (ODT) circuit included in the input/output interface; andoutputting a data signal using the selected one of the plurality of output driver circuits.2. The method of claim 1 , before the selecting claim 1 , further comprising:generating the mode selection signal according to memory latency.3. The method of claim 2 , wherein the memory latency is one of a read latency and a write latency.4. The method of claim 1 , before the selecting claim 1 , further comprising:generating the mode selection signal based on a mode register set (MRS) command, the MRS command being used to adjust an operation frequency of the ODT circuit.5. The method of claim 1 , wherein the selecting selects claim 1 ,one of the output driver circuits including a NMOS pull-up transistor when the mode selection signal indicates an operation mode for a high speed operation, andone of the output driver circuits including a PMOS pull-up transistor is selected when the mode selection signal indicates an operation mode for a ...

SEMICONDUCTOR DEVICE AND MEMORY SYSTEM

A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal. 1. A semiconductor device comprising:a first chip that includes a first circuit having a first output terminal;a second chip that includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line,wherein when the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.2. The semiconductor device according to claim 1 ,wherein the first circuit includes a first pull-up circuit having a first terminal to which a first voltage is supplied and a second terminal electrically connected to the first output terminal, and a first pull-down circuit having a first terminal to which a second voltage smaller than the first voltage is supplied and a second terminal electrically connected to the first output terminal, andthe second circuit includes a second pull-up circuit having a first terminal to which the first voltage is supplied and a second terminal electrically connected to the second output terminal, a second pull-down circuit having a first terminal to which the second voltage is supplied and a second terminal electrically connected to the second output terminal, and a comparator having a first input terminal to which a voltage of the second output terminal is supplied and a second input ...

Resistance calibration method and related calibration system

A resistance calibration method for a first resistor of a first module includes performing resistance calibration on a calibration unit of a second module, wherein the first module is connected to the second module via a pad coupled to the first resistor and the calibration unit is coupled to the pad; obtaining a resistance value of the calibration unit after the resistance calibration; and calibrating a resistance value of the first resistor according to the resistance value of the calibration unit. 1. A resistance calibration method for a first resistor of a first module , the resistance calibration method comprising:performing resistance calibration on a calibration unit of a second module, wherein the first module is connected to the second module via a pad coupled to the first resistor, and the calibration unit is coupled to the pad;obtaining a resistance value of the calibration unit after the resistance calibration; andcalibrating a resistance value of the first resistor according to the resistance value of the calibration unit.2. The resistance calibration method of claim 1 , wherein the step of calibrating the resistance value of the first resistor according to the resistance value of the calibration unit comprises:determining a specific voltage value corresponding to a target resistance value of the first resistor;adjusting the resistance value of the first resistor, wherein a voltage value of an output voltage generated from the pad varies in response to variation of the resistance value of the first resistor; anddetermining that the resistance value of the first resistor reaches the target resistance value when the voltage value of the output voltage reaches the specific voltage value.3. The resistance calibration method of claim 2 , wherein the step of determining that the resistance value of the first resistor reaches the target resistance value when the voltage value of the output voltage reaches the specific voltage value comprises:comparing the ...

ON-DIE TERMINATION CONTROL WITHOUT A DEDICATED PIN IN A MULTI-RANK SYSTEM

A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting. 1. A method for selectively applying on-die termination , comprising:sending a memory access command concurrently to a number of ranks of memory devices corresponding to a memory access operation, the memory access command directed to a target rank to execute the command;triggering one or more non-target ranks of the number of ranks to change an on-die termination (ODT) setting for a duration of the memory access operation; andselecting the target rank to execute the memory access operation.2. The method of claim 1 , wherein sending the memory access command comprises sending a read command claim 1 , and wherein triggering the one or more non-target ranks to change the ODT setting comprises triggering the a non-target rank to engage ODT.3. The method of claim 1 , wherein sending the memory access command comprises sending a write command claim 1 , and wherein triggering the one or more non-target ranks to change the ODT setting comprises triggering the target rank and at least one non-target rank to engage ODT.4. The method of claim 1 , wherein sending the memory access command comprises sending the memory access command from a memory controller.5. The method of claim 1 , wherein sending the memory access command comprises sending multiple sequential commands to generate the memory access operation.6. The method of claim 5 , wherein the triggering further comprises sending a first command indicating the memory access operation ...

PROGRAMMABLE EQUALIZATION WITH COMPENSATED IMPEDANCE

Described is a chip comprising: a pull-up driver with a first impedance, the pull-up driver coupled to a node; a pull-down driver with a second impedance, the pull-down driver coupled to the node; and an equalizer coupled to the pull-up and pull-down drivers, wherein the equalizer is operable to be trained to deemphasize a signal driven on the node while maintaining the first and second impedances substantially constant. 1. A chip comprising:a pull-up driver with a first impedance, the pull-up driver coupled to a node;a pull-down driver with a second impedance, the pull-down driver coupled to the node; andan equalizer coupled to the pull-up and pull-down drivers, wherein the equalizer is operable to be trained to deemphasize a signal driven on the node while maintaining the first and second impedances substantially constant.2. The chip of claim 1 , wherein the equalizer is part of a parallel input-output (I/O) link.3. The chip of claim 1 , wherein the first impedance is independently controllable from control of the second impedance.4. The chip of further comprises:a pull-up driver compensation unit which is operable to determine a code for setting the first impedance for the pull-up driver, and a code for setting a pull-up granularity for de-emphasizing the signal by the equalizer.5. The chip of further comprises:a pull-down driver compensation unit which is operable to determine a code for setting the second impedance for the pull-down driver, and a code for setting a pull-down granularity for de-emphasizing the signal by the equalizer.6. The chip of claim 4 , wherein the equalizer is disabled when the pull-up driver compensation unit is determining the code for setting the first impedance for the pull-up driver.7. The chip of claim 5 , wherein the equalizer is disabled when the pull-down driver compensation unit is determining the code for setting the second impedance for the pull-up driver.8. The chip of claim 5 , wherein the pull-up driver compensation unit and ...

Memory system

A memory system includes: a buffer memory device; and a memory controller including a data output driver configured to output data to the buffer memory device, wherein the data output driver includes: a pull-up switching unit coupled to an input/output power voltage, the pull-up switching unit including a PMOS transistor controlled by a data signal that varies according to the output data; a pull-up resistor unit including an NMOS transistor coupled to a DQ pad; a pull-down switching unit controlled by the data signal; and a pull-down resistor unit coupled to the pull-down switching unit.

TERMINATION CIRCUIT, RECEIVER AND ASSOCIATED TERMINATING METHOD CAPABLE OF SUPPRESSING CROSSTALK

A termination circuit, a receiver and associated terminating method are provided. The termination circuit is applied to a receiving terminal for receiving a channel transmission signal. Being coupled to a control module, the termination circuit includes an upper circuit and a lower circuit. The upper circuit selectively conducts the receiving terminal to a first voltage terminal, and the lower circuit selectively conducts the receiving terminal to a second voltage terminal. The control module detects a voltage level of the receiving terminal in response to a trigger signal, and accordingly controls the first switching signal and the second switching signal for a termination duration. The termination duration is corresponding to an n-th data bit carried by the channel transmission signal. 1. A termination circuit coupled to a control module and a receiving terminal for receiving a channel transmission signal , wherein the termination circuit comprises: a first termination component, coupled to a first voltage terminal; and', 'a first switch, coupled to the first termination component and the receiving terminal, for selectively conducting the receiving terminal to the first termination component according to a first switching signal; and, 'an upper circuit, comprising a second termination component, coupled to a second voltage terminal; and', 'wherein the control module detects a voltage level of the receiving terminal in response to a trigger signal, and accordingly controls the first and the second switching signals for a termination duration, wherein the termination duration is corresponding to an n-th data bit carried by the channel transmission signal.', 'a second switch, coupled to the second termination component and the receiving terminal, for selectively conducting the receiving terminal to the second termination component according to a second switching signal,'}], 'a lower circuit, comprising2. The termination circuit according to claim 1 , wherein the ...

Current-mode logic circuit

A current-mode logic circuit is provided. The current-mode logic circuit includes a transmitter module. The transmitter module includes an output impedance circuit, a switch circuit, and a current source. The output impedance circuit provides an adjustable output resistor. The adjustable output resistor includes floating resistors and/or pull-up resistors. The switch circuit is coupled to the output impedance circuit. The switch circuit receives differential input signals, outputs differential output signals, and controls high-low level switching of the differential input signals and the differential output signals according to the adjustable output resistor. The current source is coupled to the output impedance circuit and the switch circuit. The current source provides currents to the output impedance circuit and the switch circuit. The floating resistors are resistors coupled between the differential output signals, and the pull-up resistors are resistors coupled between the differential output signals and a power source.

STORAGE CONTROLLERS, METHODS OF OPERATING THE SAME AND SOLID STATE DISKS INCLUDING THE SAME

A storage controller includes a first on-die termination (ODT) circuit, a second ODT circuit and an ODT control circuit. The first ODT circuit provides a first termination resistance with a strobe signal line transferring a data strobe signal. The second ODT circuit provides a second termination resistance with at least one data line transferring data. The ODT control circuit individually controls activation and deactivation of the first ODT circuit and the second ODT circuit. 1. A storage controller comprising:a first on-die termination (ODT) circuit that is configured to provide a first termination resistance with a strobe signal line that is configured to transfer a data strobe signal;a second ODT circuit that is configured to provide a second termination resistance with at least one data line that transfers data; andan ODT control circuit that is configured to individually control activation and deactivation of the first ODT circuit and the second ODT circuit.2. The storage controller of claim 1 , wherein the ODT control circuit activates the first ODT circuit and deactivates the second ODT circuit during a reception operation in which the storage controller receives the data from a nonvolatile memory device.3. The storage controller of claim 2 , wherein the ODT control circuit provides a first ODT control signal to the first ODT circuit to activate the first ODT circuit and provides a second ODT control signal to the second ODT circuit to deactivate the second ODT circuit claim 2 , in response to receiving a mode signal.4. The storage controller of claim 1 , further comprising:an I/O circuit that receives the data and the data strobe signal,wherein the I/O circuit determines a logic value of the data based on the data strobe signal.5. The storage controller of claim 4 , wherein the I/O circuit is connected with the first ODT circuit via the strobe signal line and is connected with the second ODT circuit via the at least one data line.6. The storage controller ...

IMPEDANCE CALIBRATION CIRCUITS

Impedance calibration circuits are provided. The impedance calibration circuit includes an operation control signal generator and an impedance calibrator. The operation control signal generator receives temperature code signals to generate an operation control signal enabled when an internal temperature is changed from a first temperature to a second temperature. The impedance calibrator receives an external command signal or the operation control signal to generate pull-up code signals for pulling up an output signal and pull-down code signals for pulling down the output signal according to an external resistor. 1. An impedance calibration circuit comprising:an operation control signal generator suitable for receiving temperature code signals to generate an operation control signal enabled when an internal temperature is changed from a first temperature to a second temperature; andan impedance calibrator suitable for receiving an external command signal or the operation control signal to generate pull-up code signals for pulling up an output signal and pull-down code signals for pulling down the output signal according to an external resistor.2. The impedance calibration circuit of claim 1 , wherein the operation control signal generator includes:a first logic unit suitable for generating a first reset signal enabled when at least one of the external command signal and an operation delay signal is enabled;a latch pulse generator suitable for generating a latch pulse signal enabled when the temperature code signals having a logic combination corresponding to the second temperature are inputted thereto after the temperature code signals having a logic combination corresponding to the first temperature are inputted thereto;a control signal generator suitable for generating the operation control signal which is initialized in response to the first reset signal and which is enabled in response to the latch pulse signal; anda first delay unit suitable for retarding the ...

Modular analog signal multiplexers for differential signals

An example analog signal multiplexer includes two differential input signal ports for receiving a first and a second differential input signals, IN1 and IN2. The multiplexer further includes a differential output signal port with two output terminals OUT+ and OUT−, for outputting a signal based on one or more of the input signals IN1 and IN2. Furthermore, the multiplexer includes a pair of load elements, and an additional differential output signal port that has two output terminals TERM+ and TERM−. The load elements are not coupled directly to the output terminals OUT+ and OUT−, but, rather, are coupled to the output terminals of the additional output signal port, TERM+ and TERM−, enabling a modular approach where multiple instances of the multiplexer may be combined on an “as-needed” basis to realize multiplexing between a larger number of differential inputs that a single multiplexer would allow.

Pam-4 calibration

A hybrid voltage mode (VM) and current mode (CM) four-level pulse amplitude modulation (PAM-4) transmitter circuits (a.k.a. drivers) is calibrated using a configurable replica circuit and calibration control circuitry. The replica circuit includes an on-chip termination impedance to mimic a receiver's termination impedance. The amount of level enhancement provided by the current mode circuitry is calibrated by adjusting the current provided to the output node and sunk from the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving an intermediate PAM-4 level. After the level enhancement has been set, the non-linearity between levels is calibrated by adjusting the amount of current provided to the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving a maximum output voltage level.

Output driver circuit with auto-equalization based on drive strength calibration

Systems and methods for equalizing an output driver circuit based on information from calibration of the output impedance of the driver circuit are disclosed. Settings that result from the calibration are referred to as calibration codes. The output driver circuit includes multiple pull-up elements that are enabled or disabled to produce a desired output impedance when the output is high and multiple pull-down elements that are enabled or disabled to produce the desired output impedance when the output is low. The number of pull-up elements that are enabled and the number of pull-down elements that are enabled is set by calibration. The results of the calibration (i.e., the number of enabled elements for the pull-up and the number of enabled elements for the pull-down) are used to set controls for an amount of pre-emphasis and/or to set controls for output slew rates.

ON-DIE TERMINATION/DRIVING CIRCUIT AND METHOD OF USING THE SAME

An on-die termination (ODT)/driving circuit includes a connection pad, and a sub-circuit. A first side of the sub-circuit is connected to the connection pad. The ODT/driving circuit further includes a first switch directly connected to a second side of the sub-circuit. The second side of the sub-circuit is opposite the first side of the sub-circuit. The first switch is configured to selectively connect the second side of the sub-circuit to a supply voltage. The ODT/driving circuit further includes a second switch directly connected to the second side of the sub-circuit. The second switch is configured to selectively connect the second side of the sub-circuit to a reference voltage. The ODT/driving circuit further includes a receiver connected to a node located between the connection pad and the first side of the sub-circuit. 1. An on-die termination (ODT)/driving circuit comprising:a connection pad;a sub-circuit, wherein a first side of the sub-circuit is connected to the connection pad;a first switch directly connected to a second side of the sub-circuit, wherein the second side of the sub-circuit is opposite the first side of the sub-circuit, and the first switch is configured to selectively connect the second side of the sub-circuit to a supply voltage;a second switch directly connected to the second side of the sub-circuit, wherein the second switch is configured to selectively connect the second side of the sub-circuit to a reference voltage; anda receiver connected to a node located between the connection pad and the first side of the sub-circuit.2. The ODT/driving circuit of claim 1 , wherein the sub-circuit is a single resistor.3. The ODT/driving circuit of claim 1 , wherein the sub-circuit is a variable resistor.4. The ODT/driving circuit of claim 1 , wherein the first switch includes a plurality of transistors claim 1 , wherein the plurality of transistors is configured to vary a resistance between the second side of the sub-circuit and the supply voltage ...

ON-CHIP IMPEDANCE NETWORK WITH DIGITAL COARSE AND ANALOG FINE TUNING

System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network. 130-. (canceled)31. A method of self-calibrating a configurable resistance on an integrated circuit capable of being coupled to a reference resistor , the method comprising:(A) tuning a digital resistor network to configure a digital portion of the configurable resistance; and(B) tuning an analog resistor network to configure an analog portion of the configurable resistance:wherein the configurable resistance comprises the digital resistor network and the analog resistor network coupled in parallel, andwherein the configurable resistance is capable of being coupled in series with the reference resistor to form a voltage divider with an output.32. The method of :wherein the digital resistor network comprises a plurality of selectable resistive branches in parallel and a plurality of digital control signals, each branch being coupled to one of the digital control signals and selected according to the state of that digital control signal; andwherein the tuned resistance of the digital resistor network is determined by the combined state of the digital control signals.33. The method of wherein step (A) comprises the sub-steps of:(A1) varying the number of selected resistive branches in the digital resistor ...

HIGH SPEED DRIVER WITH ADAPTIVE TERMINATION IMPEDANCE

An apparatus is provided which comprises: a data sampler coupled to an output of a driver, wherein the data sampler is to sample data and to compare it with a first threshold voltage and a second threshold voltage, and wherein the data sampler is to generate an up or down indicator according to comparing the data with the first and second threshold voltages; and logic coupled to the data sampler, wherein the logic is to receive the up or down indicator and to increment or decrement a number of already DC compensated impedance legs of the driver according to the up or down indicator. 1. An apparatus comprising:a data sampler coupled to an output of a driver, wherein the data sampler is to sample data using a clock, and to compare it with a first threshold voltage and a second threshold voltage, and wherein the data sampler is to generate an up or down indicator according to comparing the data with the first and second threshold voltages; andlogic coupled to the data sampler, wherein the logic is to receive the up or down indicator and to increment or decrement a number of already DC compensated impedance legs of the driver according to the up or down indicator.2. The apparatus of claim 1 , wherein the second threshold voltage is lower than the first threshold voltage.3. The apparatus of comprises a bias generator to generate the first and second threshold voltages.4. The apparatus of claim 3 , wherein the first and second threshold voltages are nearer to a logic high level of the data than to a logic low level of the data.5. The apparatus of claim 3 , wherein the first and second threshold voltages are nearer to a logic low level of the data than to a logic high level of the data.6. The apparatus of comprises a clock generator to provide a set of sampling clocks with different phases to the data sampler for sampling data by the set of sampling clocks.7. The apparatus of claim 1 , wherein the data sampler comprises a strong arm latch.8. The apparatus of claim 1 , ...

On-Die Termination

Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

APPARATUS FOR TRANSMITTING AND RECEIVING A SIGNAL, A METHOD OF OPERATING THE SAME, A MEMORY DEVICE, AND A METHOD OF OPERATING THE MEMORY DEVICE

A signal transmitting and receiving apparatus including: a first on-die termination circuit connected to a first pin through which a first signal is transmitted or received and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the first pin; a second on-die termination circuit connected to a second pin through which a second signal is transmitted or received and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the second pin; and an on-die termination control circuit configured to independently control an enable time and a disable time of each of the first on-die termination circuit and the second on-die termination circuit.

CMOS INPUT BUFFER CIRCUIT

A high-linearity CMOS input buffer circuit is provided for neutralizing non-linearity of follower circuits' transconductance and output impedance resulting from input signals' variation. In doing so, the linearity of CMOS input buffer is improved. The buffer circuit includes a CMOS input follower circuit, a linearity improvement circuit of follower transistor, a current source load, and a linearity improvement circuit of load impedance. The buffer circuit is fabricated in standard CMOS process, featuring low cost, simplicity and strong linearity at high frequency. It has wide applications in analog and hybrid analog-digital CMOS ICs requiring high linearity input buffer. 1. A Complementary Metal Oxide Semiconductor (CMOS) input buffer circuit , comprising a CMOS input follower circuit , a linearity improvement circuit of follower transistor , a current source load , and a linearity improvement circuit of load impedance; whereinthe CMOS input follower circuit, for following changes of input signals and outputting follower input signals;the linearity improvement circuit of follower transistor, for obtaining changes of input signals and giving feedback to CMOS input follower circuit;the current source load, for providing a bias current for CMOS input follower circuit;the linearity improvement circuit of load impedance, being placed between CMOS input follower circuit and current source load, for enhancing absolute load impedance of current source, restraining its fluctuation and improving load impedance linearity of CMOS input buffer.2. The CMOS input buffer circuit as recited in claim 1 , wherein said CMOS input follower circuit comprises a M0 NMOS (N-Channel MOS) transistor claim 1 , the gate of the M0 NMOS transistor serves as the input end of CMOS input follower circuit claim 1 , its source as the output end claim 1 , said linearity improvement circuit of follower transistor is set between the gate and drain of the M0 NMOS transistor claim 1 , one end of said ...

APPARATUSES AND METHODS FOR CALIBRATING ADJUSTABLE IMPEDANCES OF A SEMICONDUCTOR DEVICE

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation. 1. An apparatus , comprising:a temperature sensor configured to provide temperature information indicative of a temperature;programmable termination resistances having a programmable impedance; andan impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances based on the temperature information provided by the temperature sensor.2. The apparatus of claim 1 , wherein the impedance calibration information is configured to perform the calibration operation based on the temperature information responsive to a change in the temperature exceeding a temperature range.3. The apparatus of claim 1 , wherein the impedance calibration information is configured to perform the calibration operation based on the temperature information responsive to the temperature exceeding a temperature limit.4. The apparatus of claim 1 , wherein the impedance calibration circuit comprises:an impedance calibration engine configured to perform the calibration operation responsive to being activated and determine the calibration parameters; and impedance calibration control logic configured to provide a calibration activation signal to activate the impedance ...

SEMICONDUCTOR APPARATUS PERFORMING CALIBRATION OPERATION AND A SEMICONDUCTOR SYSTEM USING THE SAME

A semiconductor apparatus includes a calibration circuit and a main driver. The calibration circuit is configured to generate a first calibration code when set to have a positive offset and generate a second calibration code when set to have a negative offset complementary to the positive offset. The main driver is configured to set a resistance value of the main driver based on the first and second calibration codes. 1. A semiconductor apparatus comprising:a calibration circuit including a comparator configured to compare a calibration voltage and a reference voltage to generate a comparison signal, and configured to generate a first calibration code based on the comparison signal when the comparator is set to have a positive offset and generate a second calibration code based on the comparison signal when the comparator is set to have a negative offset complementary to the positive offset; anda main driver configured to set a resistance value of the main driver based on the first calibration code and the second calibration code.2. The semiconductor apparatus of claim 1 , a first input node;', 'a second input node;', 'a third input node;', 'a fourth input node;', 'first differential output nodes configured to output a first amplified signal pair by differentially amplifying signals input to the first input node and the second input node; and', 'second differential output nodes configured to output a second amplified signal pair by differentially amplifying signals input to the third input node and the fourth input node,, 'wherein the comparator includeswherein, when an offset setting signal has a first logic level, the comparator is configured to receive the calibration voltage through the first input node and the fourth input node, receive the reference voltage through the second input node and the third input node, and generate the comparison signal based on one between the first amplified signal pair and one between the second amplified signal pair, andwherein, ...

IMPEDANCE CALIBRATION CIRCUIT AND METHOD OF CALIBRATING IMPEDANCE IN MEMORY DEVICE

An impedance calibration circuit includes a first variable impedance, a second variable impedance, a third variable impedance. The first variable impedance is connected to a ZQ terminal. A first control circuit performs a first impedance calibration on the first variable impedance based on an output signal from an output of a first comparator. A second control circuit performs a second impedance calibration on the third variable impedance based on an output signal from an output of a second comparator. A first switch connects an input of the first comparator to one of the ZQ terminal and the first node. A second switch connects the output of the first comparator to one of the first and second control circuits. A third switch connects an output of the first switch to one of first and second input terminals of the first comparator and connects the reference voltage to the other. 1. An impedance calibration circuit included in a memory device comprising:a first variable impedance circuit connected to a ZQ terminal;a second variable impedance circuit and a third variable impedance circuit connected to a first node;a first comparator configured to compare one of a voltage at the ZQ terminal and a voltage at the first node with a reference voltage;a second comparator configured to compare the voltage at the first node with the reference voltage;a first control circuit configured to perform a first impedance calibration operation on the first variable impedance circuit based on an output signal from an output of the first comparator;a second control circuit configured to perform a second impedance calibration operation on the third variable impedance circuit based on an output signal from an output of the second comparator;a first switch circuit configured to connect an input of the first comparator to one of the ZQ terminal and the first node;a second switch circuit configured to connect the output of the first comparator to one of the first control circuit and the second ...

TRANSMITTING DEVICE USING CALIBRATION CIRCUIT, SEMICONDUCTOR APPARATUS AND SYSTEM INCLUDING THE SAME

A transmitting device includes a calibration circuit and a transmission circuit. The calibration circuit generates calibration codes by performing a calibration operation. The calibration circuit also generates compensation calibration codes by increasing or decreasing values of the calibration codes according to whether a number of codes among the calibration codes having a predetermined level is greater than or equal to a threshold value. The transmission circuit drives a signal transmission line based on an input signal and the compensation calibration codes. 1. A transmitting device comprising:a calibration circuit configured to generate calibration codes by performing a calibration operation and configured to generate compensation calibration codes by increasing or decreasing values of the calibration codes when a number of codes among the calibration codes having a predetermined level is greater than or equal to a threshold value, such that a number of codes among the compensation calibration codes having the predetermined level is less than the threshold value; anda transmission circuit configured to drive a signal transmission line based on an input signal and the compensation calibration codes.2. The transmitting device of claim 1 , wherein the calibration circuit comprises:a calibration code generator coupled to an external reference resistance and configured to generate the calibration codes; anda calibration code converter configured to generate converted calibration codes from the calibration codes and configured to select the calibration codes or the converted calibration codes as the compensation calibration codes based on an operation mode signal.3. The transmitting device of claim 2 , wherein the calibration code converter comprises:a code decoder configured to generate the converted calibration codes by increasing or decreasing values of the calibration codes when the number of codes among the calibration codes having the predetermined level is ...

MEMORY SYSTEMS WITH ZQ GLOBAL MANAGEMENT AND METHODS OF OPERATING SAME

A memory system includes a memory module and a memory controller. The memory module includes a plurality of memory devices with corresponding ZQ calibration circuits therein. The memory controller, which is electrically coupled to the memory module, includes a ZQ global managing circuit therein. This ZQ global managing circuit is configured to determine a plurality of calibration values associated the corresponding ZQ calibration circuits in the plurality of memory devices, in response to calibration result data generated by the plurality of ZQ calibration circuits. The memory module is mounted within a memory slot. In addition, the plurality of calibration values account for signal loading characteristics of the memory module within the memory slot. 1. A memory system , comprising:a memory module mounted on a memory slot and comprising a plurality of semiconductor memory devices each having a ZQ calibration circuit; anda memory controller configured to control the memory module,wherein the memory controller comprises a ZQ global managing circuit configured to receive calibration result data of the ZQ calibration circuit through the memory slot and to determine a final calibration value of the ZQ calibration circuit based on a signal loading characteristic of the memory slot on which the memory module is mounted.2. The memory system of claim 1 , wherein the calibration result data comprises a pull-up calibration code and a pull-down calibration code.3. The memory system of claim 1 , wherein the final calibration value is transmitted to the ZQ calibration circuit to control the ZQ calibration circuit.4. The memory system of claim 1 , wherein the calibration result data changed by the final calibration value is applied to an on-die termination operation of an on-die termination circuit.5. The memory system of claim 1 , wherein the ZQ global managing circuit comprises:a signal integrity register configured to store signal integrity information based on a signal loading ...