PROGRAMMABLE BUFFER CIRCUIT

Buffer with compensating drive strength

Random number generator

Generally, this disclosure describes a system and method for generating random numbers. In at least one embodiment described herein, the method may include generating random bits in accordance with at least one security application via an integrated circuit, the integrated circuit including a true random number generator having an analog core. The method may further include providing, via an internally generated power supply, power to the analog core via a voltage regulator associated with the true random number generator. Of course, additional operations are also within the scope of the present disclosure.

Cross-clock domain data transfer method and apparatus

An apparatus and method for transferring units of information between clock domains. A respective set of N units of information is loaded from an output circuit in a first clock domain into a storage circuit in a second clock domain during each cycle of the first clock domain. Each set of N units is selected by the output circuit to include (1) units of information that have previously loaded into the storage circuit and that will not be output from the storage output from the storage circuit prior to the storage circuit being loaded with a subsequent set of N units of information, and (2) a complement number of units of information that have not previously been loaded into the storage circuit.

Method and apparatus for increasing linearity and reducing noise coupling in a digital to analog converter

A DAC stage having a ground offset switch driver control signal generator, provides greater linearity by preventing rail-to-rail voltage swings of the switch driver signals. In one embodiment of the present invention, a pair of inverting logic gates, coupled between a power rail and a node positively offset from ground, are used to drive the current switches in a DAC stage.

Verfahren und Einrichtung für ein Energiemanagement in einer integrierten Schaltung

The chip controlling an external device eg a floppy disc drive, monitors its own operating state and switches itself into a lower power consumption state when the chip determines that it is in a predetermined state from which it can power down cleanly. The power down operation is transparent ie the chip appears no different to the external device than when it operates at full power. Non-core activities such as the oscillator operation can be maintained when the chip is in the power down state. ...

Hub link mechanism for impedance compensation update

A method and apparatus of performing impedance compensation on signals on interfaces between chipset components is disclosed.In one embodiment, a present impedance adjustment value is generated, and a controlled impedance adjustment value is also established based on the present impedance adjustment value. Then a special cycle with a deterministic amount of time is generated to stabilize the interfaces. With the interfaces in a known state, the signals on the interfaces are updated with the controlled impedance adjustment value during the special cycle, where embodiment ensures the signals to be glitch-free.

Impedance control system for a center tapped termination bus

A method and apparatus for an impedance control system for a center tapped termination bus. One method of the present invention comprises comparing an output potential of a buffer with a pair of reference potentials. The output impedance of the buffer is adjusted to cause the buffer output voltage swing to match the reference potentials.

Method and apparatus for detecting time domains on a communication channel

According to one embodiment, a computer system is disclosed. The computer system includes a memory controller, a first Rambus channel coupled to the memory controller, a memory system coupled to the first Rambus channel and a second Rambus channel coupled to the memory system. The memory system is adaptable to determine the number of time domains on the first Rambus channel and the second Rambus channel. In a further embodiment, the memory system is adaptable to levelize memory devices coupled to the first and second Rambus channels.

Phase comparator for extending capture range

An extended range logic circuit is activated to decrease the settling time and prevent slip, when phase difference of two signals being compared by a phase comparator reaches a slip point. The circuit provides error correction signals to compensate for the phase correction at a much faster rate when the phase error reaches a predetermined point, which is proximate to the slip point. However, the extended capture range circuit in only active during the lock acquisition. After lock is achieved the extended capture range logic is disabled, to provide better jitter performance.

BUFFER WITH COMPENSATING CONTROL STRENGTH

Programmable buffer circuit

Circuitry and method to measure a duty cycle of a clock signal

In some embodiments, a chip includes clock generation circuitry to create a clock signal, and reference signal oscillator circuitry to produce a reference signal with a higher frequency than the clock signal. The chip includes a counter to change a count value in response to changes in the reference signal; and count logic circuitry to cause count storage circuitry to read the count value in response to at least some changes in the clock signal and to make at least some of the values in the count storage circuitry related to a duty cycle of the clock signal available to an external tester. Other embodiments are described and claimed.

Low power self-biasing oscillator circuit

A clock oscillator circuit that includes an inverting amplifier and a resonator configured to generate an oscillating signal. The clock oscillator includes a bias circuit having a relatively constant current source configured to create a bias voltage to bias the amplifier in an operating state that can sustain the oscillating signal. The inverting amplifier and the bias circuit are configured to operate in a low power state.

Fast lock scheme for phase locked loops and delay locked loops

A fast lock scheme for phase locked loops and delay locked loops, where an embodiment comprises a startup circuit that is enabled at the beginning of a startup mode and is disabled upon a phase transition detection in the reference and feedback signals to the phase locked loop or delay locked loop. Further embodiments enable a first charge pump when a phase transition is detected, and enable a second charge pump when the phase difference between the reference and feedback signals fall within a predetermined range. Other embodiments are described and claimed.

Method and apparatus for detecting time domains on a communication channel

Dual clock domain read fifo

High impedance current mode voltage scalable driver

A high impedance current mode voltage scalable driver allows signals from a higher supply voltage platform to transition to lower supply platforms. The scalable driver uses a current source to provide high impedance onto a load coupled to the driver. The driving of the load by the current source is controlled by symmetrical switches which are operated by the transition of the input signal. The driver utilizes voltage scaling to allow a particular higher supply voltage platform to transition to a variety of lower supply voltage platforms.

Cross-clock domain data transfer method and apparatus

Low power consumption chip controller

Method and apparatus for automatic power management in a high integration floppy disk controller

RANDOM NUMBER GENERATOR

【課題】 本発明の課題は、攻撃免疫性を備えた真性乱数生成装置に係る発明を提供することである。 【解決手段】 本発明の一特徴は、少なくとも１つのセキュリティアプリケーションに従ってランダムビットを生成するよう構成される集積回路を有する装置であって、前記集積回路は、アナログコアを有する真性乱数生成装置を有し、前記真性乱数生成装置は、前記アナログコアに電力を供給するよう構成される内部的に生成された電源を有するよう構成される電圧レギュレータを有する装置に関する。 【選択図】 図３

Buffer with compensating drive strength

A self-synchronizing method and apparatus for exiting dynamic random access memory from a low power state

Verfahren und Einrichtung zum automatischen Steuern des Energieverbrauches einer integrierten Schaltung in einem Computersystem

Method and apparatus for detecting time domains on a communication channel

STABILIZED PHASE LOCKED LOOP

Stabilized phase locked loop

A dual loop phase locked loop system having a secondary loop for controlling various circuit, environmental and process variations. The secondary loop is comprised of a phase comparator, a filter, a transconductance amplifier and a one-shot, wherein the output of the one-shot is fed back as an input signal for comparison with a reference signal at the input of the phase comparator. The filter generates a correction voltage which is dependent on the phase difference determined by the phase comparator, and the transconductance amplifier generates a charging current corresponding to the error voltage from the filter, wherein the charging current controls the charging of the input capacitor to the one-shot circuit for determining the duration of the pulse width of the output of the one-shot. The one-shot based loop is inherently stable since there is only one pole near the origin of the S-Plane. The primary loop is comprised of a phase comparator, a filter, a transconductance amplifier and ...

PHASE COMPARATOR FOR EXTENDING CAPTURE RANGE

Method and apparatus for synchronizing dynamic random access memory exiting froma low power state

Method and apparatus for timing-dependent transfers using fifos

Phase difference magnifier

Input-output bus interface

Fractional divisors for multiple-phase PLL systems

A frequency multiplier is described for synthesizing frequencies. The frequency multiplier includes a phase locked loop (PLL) circuit having an oscillator to generate a number of phase signals and a phase-shifting circuit coupled to the PLL circuit to select one of the phase signals generated by the oscillator according to a defined phase sequence to be passed to a feedback loop. Also included in the frequency multiplier is a divide-by-M circuit inserted in the feedback loop which divides a frequency of the signal selected by the phase-shifting circuit to generate a feedback signal for the PLL circuit. In one embodiment, the feedback signal generated by the divide-by-M circuit serves as a control signal to enable the phase-shifting circuit.

SYNCHRONOUS FREQUENCY SYNTHESIZER

An apparatus for clock generation is presented. In one embodiment, the apparatus comprises a phase interpolator that generates an output with a phase value within reference phases associated with two input clocks. Logic units are coupled to determine a number of phase settings for the phase interpolator. A divider is coupled to the phase interpolator to generate an output clock based on a modifiable divider setting.

Zufallszahlengenerator

Allgemein beschreibt diese Erfindung ein System und ein Verfahren zum Erzeugen von Zufallszahlen. Bei mindestens einer Ausführungsform, die hier beschrieben wird, kann das Verfahren das Erzeugen von Zufallsbits entsprechend mindestens einer Sicherheifassen, wobei der integrierte Schaltkreis einen echten Zufallszahlengenerator mit einem analogen Kern aufweist. Das Verfahren kann weiterhin das Bereitstellen, über eine intern erzeugte Energieversorgung, von Energie für den analogen Kern über einen dem echten Zufallszahlengenerator zugeordneten Spannungsregler umfassen. Natürlich liegen weitere Operationen ebenfalls innerhalb des Schutzumfangs der vorliegenden Erfindung.

Circuitry and method to measure a duty cycle of a clock signal

In some embodiments, a chip includes clock generation circuitry to create a clock signal, and reference signal oscillator circuitry to produce a reference signal with a higher frequency than the clock signal. The chip includes a counter to change a count value in response to changes in the reference signal; and count logic circuitry to cause count storage circuitry to read the count value in response to at least some changes in the clock signal and to make at least some of the values in the count storage circuitry related to a duty cycle of the clock signal available to an external tester. Other embodiments are described and claimed.

Synchronous frequency synthesizer

An apparatus for clock generation is presented. In one embodiment, the apparatus comprises a phase interpolator that generates an output with a phase value within reference phases associated with two input clocks. Logic units are coupled to determine a number of phase settings for the phase interpolator. A divider is coupled to the phase interpolator to generate an output clock based on a modifiable divider setting.

Means to extend tTR range of RDRAMS via the RDRAM memory controller

A method and system for extending t TR range of memory devices coupled to a memory devices is described. A first group of memory devices and a second group of memory devices are identified. The first group includes memory devices located close to a memory controller and the second group includes memory devices located a distance away from the memory controller. Commands to access memory devices in the first and second groups are sent. A command to the first group is sent with a transitional delay when the command to the first group follows a command to the second group. In response to the commands, data from the first and second groups is received.

Method and apparatus for changing bias levels to reduce CMOS leakage of a real time clock when switching to a battery mode of operation

A CMOS circuit for low leakage battery operation connects the real time clock to the power supply when available or to a low leakage source when the power supply is not available.

Zufallszahlengenerator

Vorrichtung zur Erzeugung von Zufallszahlen, umfassend einen integrierten Schaltkreis, der dazu eingerichtet ist, Zufallsbits entsprechend mindestens einer Sicherheitsanwendung zu erzeugen, wobei der integrierte Schaltkreis einen echten Zufallszahlengenerator (300) mit einem analogen Kern (302) umfasst, wobei der echte Zufallszahlengenerator über einen Takt gesteuert wird, der von dem analogen Kern erzeugt wird, wobei der echte Zufallszahlengenerator (300) einen Spannungsregler (304) umfasst, der dazu eingerichtet ist, eine intern erzeugte Energieversorgung zu umfassen, die dazu eingerichtet ist, Energie für den analogen Kern (302) bereitzustellen, wobei ferner eine Von-Neumann-Korrekturschaltung (204) vorgesehen ist, den vom echten Zufallszahlengenerator (300) erzeugten Bitstrom in Bitsequenzen, bestehend aus 2 oder 3 Bits, einzuteilen und zu analysieren, wobei diejenigen Bitsequenzen aussortiert werden, bei denen das erste und das zweite Bit übereinstimmen, und wobei die Von-Neumann-Korrekturschaltung ...

Method and system for reducing the effects of simultaneously switching outputs

A delay element is coupled to a first interface, which is coupled to a second interface via interconnect. Traces in the interconnect for propagating output signals from the first interface to the second interface have varying lengths. In order to reduce undesirable effects resulting from simultaneously switching the output signals, the delay element programmably and selectably delays the output signals according to the lengths of the traces they respectively travel to the second interface. Additionally, the effect of varying lengths of interconnect on receiver timings can be accommodated by using the delay element to programmably and selectably sample data at a receiver interface.

Method and apparatus for reducing sub-threshold off current for a real time clock circuit during battery operation

A CMOS circuit for low leakage battery operation connects the real time clock to the power supply when available or to a low leakage source when the power supply is not available.

Apparatus for reduced glitch energy in digital-to-analog converter

A current mode digital to analog converter (DAC) that can provide an output signal having reduced glitch energy over a wide range of manufacturing tolerances and operating conditions includes a cross-over voltage controller with feedback, disposed between the current switch and the input data source. In a further aspect of the present invention, circuitry operable to generate a synchronized differential pair of digital signals as input to the cross-over voltage controller is included. In a still further aspect of the present invention, load matching circuitry is coupled to the cross-over voltage controller output terminals to reduce timing differences between various stages of the DAC.

Self-start circuits for low-power clock oscillators

A clock circuit includes an oscillator having a biasing node that causes the oscillator to enter a low-power state. The clock circuit also includes a kick-start circuit and a first mechanism. The kick-start circuit operates to provide an excitation to the oscillator, where the excitation enables the oscillator to start its oscillation. The first mechanism is configured to inhibit kick-start based on certain conditions, such as when the oscillator reaches a particular level capable of sustaining oscillation by itself or when the oscillator is already running.

Spread spectrum clock generator

Disclosed are embodiments of methods and circuits to generate spread spectrum clocks.

Method and apparatus for minimizing leakage current in semiconductor logic

Leakage current in semiconductor logic can be minimized using the present systems and techniques. For example, a CMOS circuit for low leakage battery operation can connect a real time clock to the power supply when available or to a low leakage source when the power supply is not available.

Universal impedance control for wide range loaded signals

In one embodiment of the present invention, a compensation driving circuit includes a code generator, an enable circuit, and a driver. The code generator generates a driver code from a compensation code according to a selector signal. The driver code corresponds to a buffer having an impedance. The enable circuit enables the driver code. The driver controls impedance of the buffer according to the driver code.

Programmable buffer circuit

A first buffer impedance value is established by electronically adjusting a first impedance between a first voltage source and a first reference point until the potential at the first reference point has a predetermined relationship to a reference voltage. A second buffer impedance value is established by adjusting the impedance between a second reference point and a second voltage source, until the potential at the second reference point has a predetermined relationship with the reference voltage.

Method to reduce glitch energy in digital-to-analog converter

A current mode digital to analog converter (DAC) that can provide an output signal having reduced glitch energy over a wide range of manufacturing tolerances and operating conditions includes a cross-over voltage controller with feedback, disposed between the current switch and the input data source. In a further aspect of the present invention, circuitry operable to generate a synchronized differential pair of digital signals as input to the cross-over voltage controller is included. In a still further aspect of the present invention, load matching circuitry is coupled to the cross-over voltage controller output terminals to reduce timing differences between various stages of the DAC.

Programlanabilir geçici bellek devresi

SYNCHRONOUS FREQUENCY SYNTHESIZER

【課題】同期周波数合成器によるクロック生成装置を提供する。 【解決手段】クロック生成装置において、２つの入力クロックに関連付けられた基準位相の範囲内の位相値を有する出力を生成する位相補間器１２１を有する。ロジック・ユニット１３０は、位相補間器１２１の複数の位相設定を決定するために結合され、分周器１２２は位相補間器１２１に結合され、変更可能な分周設定に基づき出力クロックを生成する。 【選択図】図１

Method and system for reducing the effects of simultaneously switching outputs

A delay element is coupled to a first interface, which is coupled to a second interface via interconnect. Traces in the interconnect for propagating output signals from the first interface to the second interface have varying lengths. In order to reduce undesirable effects resulting from simultaneously switching the output signals, the delay element programmably and selectably delays the output signals according to the lengths of the traces they respectively travel to the second interface. Additionally, the effect of varying lengths of interconnect on receiver timings can be accommodated by using the delay element to programmably and selectably sample data at a receiver interface.

Dynamic swing voltage adjustment

The disclosure presents a device comprising a driver configured to transmit a signal on a bus line, including a driver element configured to pull against termination impedance. The impedance of the driver element is dynamically adjustable. The disclosure also presents a method of electronically adjusting the impedance of the driver element to regulate the swing voltage on the bus line.

Determining an optimal sampling clock

In some embodiments, a phase detector receives a set of sampling clock signals and a data signal and compares each of the clock signals to the data signal. A clock selector selects an optimal sampling clock signal from the set of sampling clock signals based on a trend of a relationship between the clock signals and the data signal. Other embodiments are described and claimed.

Reading a FIFO in dual clock domains

A first-in first-out buffer (FIFO) with multiple outputs. The FIFO has an input for writing data into the FIFO. The FIFO has multiple outputs for reading the data out of the FIFO. Each output is independent from the other outputs, and can be used to read data from a different address at a different time using a different clock signal. In one embodiment, the FIFO is implemented as a storage array with circular pointers to repeatedly loop through the addressable locations. It includes a write pointer to indicate which address represents the input. It includes multiple read pointers to indicate which addresses represent the outputs. Overrun prevention logic is used to assure that the write pointer will not cause new data to be written into any address that has not been read by all outputs, and to assure that data will not be read from any address that has not been written into.

Measuring and identifying analog characteristics of a microelectronic component at a wafer level and a platform level

A die includes circuit components to perform normal operations and duplicated components of selective ones of the circuit components. Each end of the duplicated components is connected to a pad on the die to allow access by measurement devices. The measurement devices apply electricity to the pads to measure analog characteristics of the duplicated components.

Method and apparatus for minimizing leakage current in semiconductor logic

Leakage current in semiconductor logic can be minimized using the present systems and techniques. For example, a CMOS circuit for low leakage battery operation can connect a real time clock to the power supply when available or to a low leakage source when the power supply is not available.

Apparatus and method for low latency power management on a serial data link

An apparatus and method for low latency power management on a serial data link are described. In one embodiment, the method includes the detection of an electrical idle exit condition during receiver operation in an electrical idle state. Once detected, data synchronization is performed according to one or more received data synchronization training patterns. Finally, when the synchronization is performed within a determined synchronization re-establishment period, the receiver will resume operation according to a normal power state. Accordingly, the embodiment described illustrates an open loop, low latency power resumption operation for power management within 3GIO links.

Random number generator

Generally, this disclosure describes a system and method for generating random numbers. In at least one embodiment described herein, the method may include generating random bits in accordance with at least one security application via an integrated circuit, said integrated circuit including a true random number generator having an analog core. The method may further include providing, via an internally generated power supply, power to said analog core via a voltage regulator associated with said true random number generator. Of course, additional operations are also within the scope of the present disclosure.

Method and apparatus for local parameter variation compensation

In order to detect performance parameter variations at different locations, local parameter detectors are located at the various local locations. One of the local locations is selected as the reference location while the other local locations are selected as destination locations. The reference location is utilized to determine a reference parameter value, while each destination location compares its local parameter value to the reference parameter value. The parameter values are current encoded and the reference parameter value is sent to the other locations for the comparisons. The comparison at the destination locations each generates a corrective signal to compensate for the difference in the parameter value between the locations. Parameter compensation is provided to reduce performance skew among the distributed locations.

Fast lock scheme for phase locked loops and delay locked loops

A fast lock scheme for phase locked loops and delay locked loops, where apparatus, systems, and methods include a startup circuit that is enabled at the beginning of a startup mode and is disabled upon a phase transition detection in the reference and feedback signals to the phase locked loop or delay locked loop. Further apparatus, systems, and methods enable a first charge pump when a phase transition is detected, and enable a second charge pump when the phase difference between the reference and feedback signals fall within a predetermined range.

Method and apparatus for increasing linearity and reducing noise coupling in a digital to analog converter

A DAC stage having a ground offset switch driver control signal generator, provides greater linearity by preventing rail-to-rail voltage swings of the switch driver signals. In one embodiment of the present invention, a pair of inverting logic gates, coupled between a power rail and a node positively offset from ground, are used to drive the current switches in a DAC stage.

RANDOM NUMBER GENERATOR

Generally, this disclosure describes a system and method for generating random numbers. In at least one embodiment described herein, the method may include generating random bits in accordance with at least one security application via an integrated circuit, said integrated circuit including a true random number generator having an analog core. The method may further include providing, via an internally generated power supply, power to said analog core via a voltage regulator associated with said true random number generator. Of course, additional operations are also within the scope of the present disclosure.

Low supply voltage differential signal driver

The invention provides a low voltage differential signaling driver (LVDS) which can operate with a lower supply voltage than conventional LVDS drivers. The common-mode voltage of the driver circuit is set to a certain level, or maintained within a certain range, by adjusting the driver current, the pull-up resistance, or both. In one implementation, the common-mode voltage of a differential driver circuit is regulated via a feedback signal.

Signal drive de-emphasis control for serial bus

Transmitting a transition between high and low states across a lengthy conductor with a main transmitter to transmit data, providing emphasis with an emphasis transmitter to strengthen the transmission of the transition, transmitting a low-to-high transition to test for the absence of an electronic device coupled to the lengthy conductor, and detecting an occurrence of an overvoltage level indicating the absence of such an electronic device.

Impedance control for wide range loaded signals using distributed methodology

In one embodiment of the present invention, a compensation controller includes a counter, K driving circuits, K feedback circuits, and a state machine. The counter generates a compensation code. The K driving circuits control impedances of K buffers at K pads using the compensation code. The K feedback circuits provide K comparison results for K voltage levels at the K pads. The state machine controls the counter and the K driving circuits based on the K comparison results.

Method and apparatus for synchronizing dynamic random access memory exiting from a low power state

A method and apparatus for exiting a dynamic random access memory from a low power state is provided. The exit from the low power state is first initiated. After the expiration of an exit delay period, a quiet time command is routed through a queue circuit. In one embodiment the use of a bypass circuit allows the interruption of the memory pipeline with a subsequent restart of the pipeline without excessive delay. A flexible clock is delayed by the onset of the quiet time command until the subsequent quiet time event.

Mechanism to control an on die voltage regulator

According to one embodiment, a voltage regulator system is disclosed. The system includes a load, a voltage regulator circuit coupled to the load, and control logic coupled to the voltage regulator circuit. The control logic controls the voltage regulator circuit so that the voltage regulator circuit supplies power to the load if activated by the control logic and a core voltage power supply supplies power to the load if the voltage regulator circuit is de-activated by the control logic.

Circuit and method for generating a clock signal

In some embodiments, a circuit includes an oscillator circuit and a control circuit. The oscillator circuit generates a clock signal and includes a plurality of selectable delay circuits. The control circuit receives the clock signal from the oscillator and a reference signal. The control circuit provides a control signal to the oscillator circuit to activate one or more of the plurality of selectable delay circuits to change the frequency of the clock signal. In some embodiments, a method includes generating a clock signal in an oscillator circuit, processing the clock signal to generate a control signal, and activating one or more of a plurality of selectable delay circuits in the oscillator circuit, in response to the control signal.

Devices and methods for automatically producing a clock signal that follows the master clock signal

An electronic device such as a processor receives a master clock signal from a system clock generator. The clock signal may be single-ended or differential. The disclosure presents methods and devices for automatically producing a clock signal that follows the master clock signal, regardless of whether the master clock signal is single-ended or differential.

Synchronizing and aligning differing clock domains

Embodiments of the invention relate to a memory control hub (MCH) clock master of an MCH. Typically, in a computer system, a processor is coupled to the MCH by a front-side bus (FSB). Further, an input/output control hub (ICH) is typically coupled to the MCH by a back-side bus or Hub Link. In one embodiment, a host phase locked loop (HPLL) of the MCH clock master receives an FSB clock signal transmitted on the FSB and generates a local synchronous clock signal based upon the FSB clock signal. A delayed lock loop (DLL) of the MCH clock master also receives the FSB clock signal and generates a system clock signal. Particularly, the DLL synchronizes the system clock signal to the local synchronous clock and drives the system clock signal to many different devices on the board.

Dynamic impedance matched driver for improved slew rate and glitch termination

The impedance of a driver driving a load on the other end of a transmission line is dynamically changed to improve slew rate and glitch termination. The driver is controlled to have a low impedance during an initial part of an edge transition, giving the strong drive needed at that time. At a first predetermined position in the edge transition, approximately equal to the flight time, the driver impedance is raised to a value approximately equal to the transmission line impedance to effectively terminate any reflected signals.

Method and apparatus for timing-dependant transfers using FIFOs

A method and apparatus for communicating commands and/or data between two different time domains. In one embodiment, multiple memory commands are placed into one or more FIFOs in a manner that specifies the delays that must take place between execution of the different commands. Along with the commands, delay information is placed into the FIFOs, specifying the number of clock cycles, or other form of time delay, that must elapse between execution of a command and execution of a subsequent command. This delay information is used to delay the execution of the subsequent command for the specified time period, while minimizing or eliminating any excess delays. Cue information can also be placed into the FIFOs with the commands to specify which commands must wait for other commands before beginning execution. The delay and cue information is determined and created in the time domain that initiates the transfers. The delays and cueing are executed in the other time domain. Although the different ...

Low supply voltage differential signal driver

The invention provides a low voltage differential signaling driver (LVDS) which can operate with a lower supply voltage than conventional LVDS drivers. The common-mode voltage of the driver circuit is set to a certain level, or maintained within a certain range, by adjusting the driver current, the pull-up resistance, or both. In one implementation, the common-mode voltage of a differential driver circuit is regulated via a feedback signal.

Apparatus and method of mirroring a voltage to a different reference voltage point

A voltage mirroring circuit to output a voltage that is derived from a reference voltage. A reference voltage is applied to the positive input of an operational amplifier, which is used as a unity gain amplifier to generate a feedback voltage. The feedback voltage is applied across a resistor to form a current. The current is directed through a load resistor to form the output voltage. The output voltage is a function of the resistance ratio of the load resistor to the current-setting resistor. Also, a multiple-output voltage mirroring circuit in which the current formed by the use of the operational amplifier and the current-settings resistor is mirrored to generate a plurality of currents. These currents are directed through respective load resistors to form output voltages. The output voltages are a function of the resistance ratios of the respective load resistors to the current-setting resistor.

Synchronous frequency synthesizer

An apparatus for clock generation is presented. In one embodiment, the apparatus comprises a phase interpolator that generates an output with a phase value within reference phases associated with twoinput clocks. Logic units are coupled to determine a number of phase settings for the phase interpolator. A divider is coupled to the phase interpolator to generate an output clock based on a modifiable divider setting.

Input-output bus interface to bridge different process technologies

A bus in which a transmission line is excited by a pMOSFET having a drain connected to the transmission line and having a source at a core voltage VCC, and in which the transmission line is terminated by a device connected to ground.

Method and apparatus for configuring an I/O buffer having an initialized default signaling level to operate at a sampled external circuit signaling level

A method for automatically detecting signal levels for buffer configuration. The method of one embodiment first samples a first signal. The first signal is compared with a second signal to determine whether the first signal has a higher voltage potential than the second signal. The result of the comparison is latched. The result of the comparison is used to program buffer characteristics.

Method and apparatus for reduced glitch energy in digital-to-analog converter

A current mode digital to analog converter (DAC) that can provide an output signal having reduced glitch energy over a wide range of manufacturing tolerances and operating conditions includes a cross-over voltage controller with feedback, disposed between the current switch and the input data source. In a further aspect of the present invention, circuitry operable to generate a synchronized differential pair of digital signals as input to the cross-over voltage controller is included. In a still further aspect of the present invention, load matching circuitry is coupled to the cross-over voltage controller output terminals to reduce timing differences between various stages of the DAC.

Buffer with compensating drive strength

A compensating buffer providing both course tuning on initialization and fine-tuning during operation is disclosed. The course tuning is provided by a plurality of binary-weighted driver legs which are selected during initialization. The fine-tuning which is selectable during both initialization and during operation is provided through linear-weighted biasing. The linear-weighted biasing is simplified through the use of a digital-to-analog converter.

Buffer with compensating drive strength

METHOD AND DEVICE FOR AUTOMATICALLY REDUCING POWER CONSUMPTION OF CHIP

PURPOSE: To automatically place a chip to a state where power consumption is reduced by making the chip monitor its own operation and placing the chip in the state where power is reduced in response to a monitoring process for judging that the chip is in a prescribed state. CONSTITUTION: A power consumption reduction logic 500 reduces the power consumption of an FDC by stopping internal clocks generated in a clock generation part 509 and adding power consumption reduction state signals (PD-STATE) to a circuit. An REG-ACCESS logic 501 judges whether or not one of the motors of the drive of a floppy disk is turned to a possible state, whether or not a FIFO is accessed at present by a read operation or a write operation and whether or not an MSR command register is read. The REG-ACCESS logic 501 outputs REG-ACCESS signals to an automatic power consumption reduction logic 503 and the logic 503 decides whether or not to place the FDC in a power consumption reduction state in response to the ...

A method and apparatus for automatic power management in a highly integrated flexible disk control device.

L'invention concerne un procédé de débranchement automatique d'une microplaquette dans lequel la microplaquette interagit avec un système externe et peut être dans une série d'états de fonctionnement. La microplaquette se surveille elle-même (101) quant à un état prédéterminé où elle peut, sans conséquences gênantes se mettre en état de consommation réduite de puissance, dit débranché. Elle se met dans l'état débranché (102) quand elle détermine qu'elle est dans ledit état prédéterminé. De préférence elle présente audit système externe une interface telle qu'elle semble branchée quand elle est débranchée. De préférence, elle peut se réveiller automatiquement (103) sur demande. Dans cet état, l'oscillateur peut à volonté être en fonction ou hors fonction. Elle comprend de préférence une partie central où l'accès n'est possible que dans l'état d'éveil, et une partie non centrale, où l'accès est possible sans exiger l'éveil. L'invention comprend aussi un appareillage correspondant.

METHOD AND APPARATUS FOR AUTOMATIC POWER MANAGEMENT IN A HIGHLY INTEGRATED FLEXIBLE DISK CONTROL DEVICE.

Stabilized phase locked loop

A dual loop phase locked loop system having a secondary loop for controlling various circuit, environmental and process variations. The secondary loop is comprised of a phase comparator, a filter, a transconductance amplifier and a one-shot, wherein the output of the one-shot is fed back as an input signal for comparison with a reference signal at the input of the phase comparator. The filter generates a correction voltage which is dependent on the phase difference determined by the phase comparator, and the transconductance amplifier generates a charging current corresponding to the error voltage from the filter, wherein the charging current controls the charging of the input capacitor to the one-shot circuit for determining the duration of the pulse width of the output of the one-shot. The one-shot based loop is inherently stable since there is only one pole near the origin of the S-Plane. The primary loop is comprised of a phase comparator, a filter, a transconductance amplifier and an output means, which is a VCO and a voltage divider. The primary loop provides the actual phased locked loop of an input reference signal, however, it derives compensating analog trim information from the secondary loop. The dynamic characteristics of the primary loop are established by the reference loop, based on the reference clock frequency. Further, the loop response is controlled by the reference frequency, and is immune to process, temperature and voltage variations. In addition the loop frequency characteristics can be programmed by adjusting the reference clock.

Self-synchronizing method and apparatus for exiting dynamic random access memory from a low power state

A self-synchronizing method and apparatus for exiting a dynamic random access memory from a low power state is provided. The exit from the low power state is initiated. After the expiration of an exit delay period, a first quiet time is sent on a column-access pin. A second quiet time is sent on a row-access pins to reset the memory. The first quiet time and the second quiet time are not necessarily concurrent.

A self-synchronizing method and apparatus for exiting dynamic random access memory from a low power state

A self-synchronizing method and apparatus for exiting a dynamic random access memory (DRAM)(510) from a low power state is provided. The exit from the low power state is initiated. After the expiration of an exit delay period, a first quiet time is sent on a column access pin (COL). A second quiet time is sent on row access pins (ROW) to reset the memory (510). The first quiet time and second quiet time are not necessarily concurrent.

Programmable buffer circuit

A first buffer impedance value is established by electronically adjusting a first impedance (340A) between a first voltage source (VCCP) and a first reference point (RCOMP) until the potential at a first reference point has a predetermined relationship to a reference voltage (V SWING). A second buffer impedance (350B) value is established by adjusting the impedance between a second reference point (RCMP2) and a second voltage source (FROUND), until the potential at the second reference point has a predetermined relationship with the reference voltage (V SWING).

Programmable buffer circuit

A first buffer impedance value is established by electronically adjusting a first impedance (340A) between a first voltage source (VCCP) and a first reference point (RCOMP) until the potential at a first reference point has a predetermined relationship to a reference voltage (V SWING). A second buffer impedance (350B) value is established by adjusting the impedance between a second reference point (RCMP2) and a second voltage source (FROUND), until the potential at the second reference point has a predetermined relationship with the reference voltage (V SWING).

Dual clock domain read fifo

Circuitry and method to measure a duty cycle of a clock signal

In some embodiments, a chip includes clock generation circuitry to create a clock signal, and reference signal oscillator circuitry to produce a reference signal with a higher frequency than the clock signal. The chip includes a counter to change a count value in response to changes in the reference signal; and count logic circuitry to cause count storage circuitry to read the count value in response to at least some changes in the clock signal and to make at least some of the values in the count storage circuitry related to a duty cycle of the clock signal available to an external tester. Other embodiments are described and claimed.

Method and apparatus for synchronizing dynamic random access memory exiting from a low power state

A method and apparatus for exiting a dynamic random access memory from a low power state is provided. The exit from the low power state is first initiated. After the expiration of an exit delay period, a quiet time command is routed through a queue circuit. In one embodiment the use of a bypass circuit allows the interruption of the memory pipeline with a subsequent restart of the pipeline without excessive delay. A flexible clock is delayed by the onset of the quiet time command until the subsequent quiet time event.

Dual clock domain read FIFO

Puffer mit kompensierender steuerungsstärke

Method and apparatus for timing-dependent transfers using fifos

Input-output bus driver

A bus in which a transmission line is excited by a pMOSFET having a drain connected to the transmission line and having a source at a core voltage VCC, and in which the transmission line is terminated by a device connected to ground.

Method and apparatus for timing-dependent transfers using FIFOs

METHOD AND APPARATUS FOR TIMING-DEPENDENT TRANSFERS USING FIFOs

A method and apparatus for communicating commands and/or data between two different time domains. In one embodiment, multiple memory commands are placed into one or more FIFOs in a manner that specifies the delays that must take place between execution of the different commands. Along with the commands, delay information is placed into the FIFOs, specifying the number of clock cycles, or other form of time delay, that must elapse between execution of a command and execution of a subsequent command. This delay information is used to delay the execution of the subsequent command for the specified time period, while minimizing or eliminating any excess delays. Cue information can also be placed into the FIFOs with the commands to specify which commands must wait for other commands before beginning execution. The delay and cue information is determined and created in the time domain that initiates the transfers. The delays and cueing are executed in the other time domain. Although the different commands may be delivered through different FIFOs and can therefore have unpredictable arrival times with respect to each other, the delay and cueing information maintains the proper executing order and timing between the commands. Interactive control logic at the output of each FIFO uses the timing data to maintain execution in the proper order and with the proper inter-command delays.

Dynamic swing voltage adjustment

Input-output bus driver

A bus in which a transmission line is excited by a pMOSFET having a drain connected to the transmission line and having a source at a core voltage VCC, and in which the transmission line is terminated by a device connected to ground.

Phase difference magnifier

An apparatus (55) and method for indicating a phase difference between a first input signal (46) and a second input signal (47). A first delayed signal (D2) is generated by delaying a reference signal for a first predetermined time and a second delayed signal (D3) is generated by delaying the reference signal for a second predetermined time, the second predetermined time being longer than the first predetermined time. The leading signal of the first and second input signals is detected. If the first input signal leads the second input signal, the first delayed signal is output to represent the first input signal and a signal that lags the first delayed signal by a third predetermined time is output to represent the second input signal. If the second input signal leads the first input signal, the second delayed signal is output to represent the first input signal and a signal that leads the second delayed signal by a fourth predetermined time is output to represent the second input signal.

Phase difference magnifier

Phase difference magnifier

METHOD AND APPARATUS FOR TIMING-DEPENDENT TRANSFERS USING FIFOs

A method and apparatus for communicating commands and/or data between two different time domains. In one embodiment, multiple memory commands are placed into one or more FIFOs in a manner that specifies the delays that must take place between execution of the different commands. Along with the commands, delay information is placed into the FIFOs, specifying the number of clock cycles, or other form of time delay, that must elapse between execution of a command and execution of a subsequent command. This delay information is used to delay the execution of the subsequent command for the specified time period, while minimizing or eliminating any excess delays. Cue information can also be placed into the FIFOs with the commands to specify which commands must wait for other commands before beginning execution. The delay and cue information is determined and created in the time domain that initiates the transfers. The delays and cueing are executed in the other time domain. Although the different commands may be delivered through different FIFOs and can therefore have unpredictable arrival times with respect to each other, the delay and cueing information maintains the proper executing order and timing between the commands. Interactive control logic at the output of each FIFO uses the timing data to maintain execution in the proper order and with the proper inter-command delays.

Programmierbare pufferschaltung

在一個通訊渠道探測時域的方法及裝置